WO2022088749A1 - 校准电路、存储器以及校准方法 - Google Patents

校准电路、存储器以及校准方法 Download PDF

Info

Publication number
WO2022088749A1
WO2022088749A1 PCT/CN2021/105250 CN2021105250W WO2022088749A1 WO 2022088749 A1 WO2022088749 A1 WO 2022088749A1 CN 2021105250 W CN2021105250 W CN 2021105250W WO 2022088749 A1 WO2022088749 A1 WO 2022088749A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
internal signal
duty cycle
internal
ibo
Prior art date
Application number
PCT/CN2021/105250
Other languages
English (en)
French (fr)
Inventor
田凯
汪玉霞
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020227029212A priority Critical patent/KR20220131979A/ko
Priority to EP21870482.3A priority patent/EP4033662B1/en
Priority to JP2022552390A priority patent/JP7467655B2/ja
Priority to US17/448,051 priority patent/US11935621B2/en
Publication of WO2022088749A1 publication Critical patent/WO2022088749A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to, but are not limited to, a calibration circuit, a memory, and a calibration method.
  • Semiconductor memory is used in many electronic systems to store retrievable data. As the demand for electronic systems to be faster, have greater data capacity and consume less power continues to grow, to meet changing demands, semiconductor memory may need to be faster, store more data and use less power .
  • the semiconductor memory is controlled by providing commands, memory addresses and clocks to the memory, and various commands, memory addresses and clocks can be provided by a memory controller. These three types of signals can control the memory to perform various storage operations, such as read operations to read data from the memory, and write operations to store data into the memory. Data is transferred between the memory and the memory controller based on known timings associated with "related commands" received by the memory. Specifically, a system clock (system clock) for timing commands and addresses can be provided to the memory, and further, a data clock (data clock) can also be provided to the memory, and the data clock is used as a timing sequence for reading data and Timing of writing data. In addition, the memory can also provide a clock to the controller for timing the transfer of data to the controller.
  • system clock system clock
  • data clock data clock
  • the memory can also provide a clock to the controller for timing the transfer of data to the controller.
  • the external clock provided to the memory is used to generate internal clocks that control the timing of various internal circuits during the memory operation of the memory. Timing of internal circuits during memory operation is critical, and deviations in the internal clock, including duty cycle distortion, where the duty cycle of the clock signal deviates from the preset duty cycle, may cause erroneous operation.
  • the memory needs to have the DCA function and the DCM function, that is, the memory includes a duty cycle adjustment (DCA, Duty Cycle Adjust) circuit and a duty cycle monitor (DCM, Duty Cycle Monitor) circuit.
  • the duty cycle adjustment circuit can be used to adjust the external The duty cycle of the internal clock generated by the clock, and the duty cycle monitoring circuit can be used to monitor whether the duty cycle of the clock deviates from the preset duty cycle.
  • An embodiment of the present application provides a calibration circuit, including: a differential input circuit for receiving a first oscillating signal and a second oscillating signal, the first oscillating signal and the second oscillating signal have the same frequency and opposite phases, so The duty cycle of the first oscillating signal and the duty cycle of the second oscillating signal are within a first preset range, and the differential input circuit outputs the first internal signal and the second internal signal; the comparison unit is connected to the an output end of the differential input circuit, and compares the duty cycle of the first internal signal and/or the duty cycle of the second internal signal; a logic unit, connected to the comparison unit and the differential input circuit, for controlling the differential input circuit according to the output result of the comparison unit, so that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range .
  • An embodiment of the present application further provides a memory, including the above-mentioned calibration circuit.
  • An embodiment of the present application further provides a calibration method, including: a differential input circuit receives a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal have the same frequency and opposite phase, and the first oscillation signal and the second oscillation signal have the same frequency and opposite phase, and the The duty ratios of an oscillating signal and a second oscillating signal are within a first preset range, the differential input circuit outputs the first internal signal and the second internal signal; the comparison unit receives the first internal signal and the second internal signal , and compare the duty cycle of the first internal signal or the duty cycle of the second internal signal; the logic unit controls the differential input circuit according to the output result of the comparison unit, so that the first internal signal The duty cycle of the signal and/or the duty cycle of the second internal signal falls within the second preset range.
  • FIG. 1 is a functional block diagram of a calibration circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a calibration circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a calibration method provided by another embodiment of the present application.
  • the memory has a differential input circuit that receives an external clock signal to generate an internal clock signal.
  • the inherent circuit characteristics of the differential input circuit may cause a duty cycle deviation of the internal clock signal. If the influence of the differential input circuit on the duty cycle deviation is not detected and calibrated in time, the read and write performance of the memory will be affected.
  • the present application provides a calibration circuit. After the first oscillating signal and the second oscillating signal whose duty ratio is in the first preset range are passed through the differential input circuit, the first internal signal and the second internal signal are output, The first internal signal and the second internal signal can be used as actual input signals used when testing the memory; the duty ratio of the first internal signal and the second internal signal is detected by the comparison unit, and the logic unit based on the detection result
  • the differential input circuit performs control to ensure that the duty cycle of the first internal signal and the duty cycle of the second internal signal can reach and stabilize within the second preset range, and the first internal signal and the second internal signal are used for testing, Can improve the accuracy of test results.
  • the calibration circuit also has DCM function and DCM function, which can calibrate the working state of the differential input circuit, reduce or even avoid the influence of the differential input circuit on the duty cycle deviation, and improve the read and write of the memory with the calibration circuit. performance.
  • FIG. 1 is a functional block diagram of a calibration circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a calibration circuit provided by an embodiment of the present application.
  • the calibration circuit includes: a differential input circuit 101 for receiving the first oscillation signal OSC+ and the second oscillation signal OSC-, the difference between the first oscillation signal OSC+ and the second oscillation signal OSC- The frequency is the same and the phase is opposite, the duty cycle of the first oscillating signal OSC+ and the duty cycle of the second oscillating signal OSC- are within the first preset range, and the differential input circuit 101 outputs the first internal signal IBO+ and the second internal signal IBO -; comparison unit 102, connected to the output of the differential input circuit 101, and compares the duty cycle of the first internal signal IBO+ and/or the duty cycle of the second internal signal IBO-; the logic unit 103, connected to the comparison unit 102 And the differential input circuit 101 is used to control the differential input circuit 101 according to the output result of the comparison unit 102, so that the duty cycle of the first internal signal IBO+ and/or the duty cycle of the second internal signal IBO- reach the second pre-
  • the calibration circuit can be built in the memory, and can be used not only to receive an external clock signal to generate an internal clock signal, but also to receive a first oscillating signal and a second oscillating signal for testing to generate a first internal signal and a second internal signal, and The duty cycle of the first internal signal and the duty cycle of the second internal signal can be stabilized within the second preset range, thereby improving the accuracy of the test result of the test memory.
  • the calibration circuit can also realize the duty cycle calibration function and the duty cycle monitoring function of the memory, and realize the calibration function of the differential input circuit, so as to avoid the duty cycle deviation problem caused by the differential input circuit to the clock signal.
  • the first oscillating signal OSC+ and the second oscillating signal OSC- are differential clock signals, and the duty cycle of the first oscillating signal OSC+ and the duty cycle of the second oscillating signal OSC- are within the first preset range, that is, , the first oscillating signal OSC+ and the second oscillating signal OSC- are high-quality signals.
  • the first preset range may be 48% ⁇ 52%.
  • the first oscillating signal OSC+ and the second oscillating signal OSC- may have high-frequency characteristics, that is, the frequency of the first oscillating signal OSC+ and the frequency of the second oscillating signal OSC- and the memory are read and written
  • the frequencies of the clock signals required for operation are equivalent, and the equivalent here can either mean the same frequency or the frequency difference is within the allowable range of the test.
  • the frequencies of the first oscillating signal OSC+ and the second oscillating signal OSC- may reach 3.2 GHz or 4.8 GHz or even 6.4 GHz.
  • first oscillation signal OSC+ and the second oscillation signal OSC- may be provided by an oscillation circuit built in the memory.
  • the differential input circuit 101 may include an input buffer (IB, Input Buffer) for receiving the differential first oscillating signal OSC+ and the second oscillating signal OSC-, and outputting the differential first internal signal IBO+ and the first differential oscillating signal OSC- Two internal signals IBO-.
  • IB input buffer
  • IB Input Buffer
  • the differential input circuit 101 can also be used to receive the first external signal PAD+ and the second external signal PAD-, and the frequency of the first external signal is the same as the frequency of the second external signal and the phase is opposite, that is to say , the first external signal PAD+ and the second external signal PAD- are also differential signals.
  • the calibration circuit further includes: a selector 111, the first oscillating signal OSC+, the second oscillating signal OSC-, the first external signal PAD+ and the second external signal PAD- are all connected to the differential input circuit 101 through the selector 111, marked as The first oscillating signal OSC+ and the second oscillating signal OSC- are the first differential pair signals, the first external signal PAD+ and the second external signal PAD- are the second differential pair signals, and the selector 111 is used to select the first differential pair signal and one of the second differential pair signals are input to the differential input circuit 101 .
  • the comparison unit 102 is used to detect the duty cycle of the first internal signal IBO+ and the duty cycle of the second internal signal IBO-.
  • the comparison unit 102 compares the duty cycle of the first internal signal IBO+ and/or the duty cycle of the second internal signal IBO-, including at least one of the following three situations:
  • the comparison unit 102 compares the duty ratio of the first internal signal IBO+. Specifically, the comparison unit 102 compares whether the duty cycle of the first internal signal IBO+ reaches a second preset range, and the second preset range may be the same as the first preset range. For example, the second preset range may be 48 % ⁇ 52%. If the comparing unit 102 compares the duty cycle of the first internal signal IBO+ to be within the second preset range, it means that the duty cycle of the second internal signal IBO- is also within the second preset range; if the comparing unit 102 compares the first If the duty cycle of the internal signal IBO+ is not within the second preset range, it means that the duty cycle of the second internal signal IBO- is also not within the second preset range.
  • the comparison unit 102 compares the duty ratio of the second internal signal IBO-. Specifically, the comparison unit 102 compares whether the duty cycle of the second internal signal IBO- reaches a second preset range, and the second preset range may be 48% ⁇ 52%. If the comparing unit 102 compares the duty cycle of the second internal signal IBO- within the second preset range, it means that the duty cycle of the first internal signal IBO+ is also within the second preset range; if the comparing unit 102 compares the second internal signal IBO+ If the duty cycle of the internal signal IBO- is not within the second preset range, it means that the duty cycle of the first internal signal IBO+ is also not within the second preset range.
  • the comparison unit 102 compares the duty ratio of the first internal signal IBO+ with the duty ratio of the second internal signal IBO ⁇ . Specifically, the comparison unit 102 obtains whether the difference between the duty cycle of the first internal signal IBO+ and the duty cycle of the second internal signal IBO- is within a preset difference range, and the preset difference range may be -4% ⁇ 4%; if the comparison unit 102 compares the difference within the preset difference range, it means that the duty ratios of the first internal signal IBO+ and the second internal signal IBO- are within the second preset range, otherwise, the first The duty ratios of the internal signal IBO+ and the second internal signal IBO- do not reach the second preset range.
  • the above-mentioned numerical ranges of the second preset range and the preset difference range are all exemplary descriptions, and this embodiment does not limit the second preset range and the preset difference range.
  • the second preset range and the preset difference range are reasonably set according to actual performance requirements.
  • the comparing unit 102 includes: an integrating unit 112, which has a first input terminal 3 and a second input terminal 4, and the first input terminal 3 receives one of the first internal signal IBO+ or the second internal signal IBO- , the second input terminal 4 receives the other of the first internal signal IBO+ or the second internal signal IBO-; the comparator 122 is connected to the output terminal of the integrating unit 112 .
  • the integrating unit 112 includes two integrating circuits, and the first input terminal 3 is used as the input terminal of one integrating circuit, and the second input terminal 4 is used as the input terminal of another integrating circuit.
  • the comparator 122 is used to compare the outputs of the two integrating circuits and output a high level or a low level.
  • the comparison unit 102 performs an integration operation on the input first internal signal IBO+ and the second internal signal IBO ⁇ by two integration circuits, and the result of the integration operation is input into the comparator 122, and the comparator 122 outputs the comparison result. .
  • the output of the comparator 122 is at a high level, indicating that the first internal signal The duty cycle of IBO+ is greater than that of the second internal signal IBO-; the output of the comparator 122 is low, indicating that the duty cycle of the first internal signal IBO+ is smaller than that of the second internal signal IBO-.
  • the output result of the comparison unit 102 may be sampled and output by the sampling clock clk1 .
  • the comparison unit 102 is driven by a sampling clock clk1, and the frequency of the sampling clock clk1 is lower than the frequency of the first internal signal IBO+ and/or the frequency of the second internal signal IBO-.
  • the clock generating circuit further includes: a frequency divider 104, which receives an external clock signal CLK and generates a sampling clock clk1.
  • the external clock signal CLK can either be provided by the testing machine or provided by the memory.
  • the clock generation circuit may further include: a fifth register group 105, Connected to the frequency divider 104 for configuring the frequency of the sampling clock.
  • the fifth register group 105 may be mode registers.
  • the comparison unit 102 can also be configured as the first input terminal 3 Interchangeable with the second input 4. Specifically, the comparison unit 102 is configured to:
  • the first input terminal 3 of the integration unit 112 receives the first internal signal IBO+ when the inversion identification signal is at a low level, and receives the second internal signal IBO- when the inversion identification signal is at a high level; the second input terminal 4 of the integration unit 112 The second internal signal IBO- is received when the inversion identification signal is at a low level, and the first internal signal IBO+ is received when the inversion identification signal is at a high level.
  • the memory has a mode register, and the inversion identification signal can be provided by the mode register.
  • the logic unit 103 controls the differential input circuit 101 based on the detection result of the comparison unit 102, and adjusts the circuit characteristics of the differential input circuit 101, so that the adjusted differential input circuit 101 outputs the first internal signal IBO+ and the second internal signal IBO- The duty cycle reaches the second preset range.
  • the logic unit 103 includes: a counter 113 for adjusting the duty cycle of the first internal signal IBO+ and/or the second internal signal IBO-; a first register group 123 for comparing the The output of the comparator 122 stores the first value of the counter 113 ; the second register group 133 stores the second value of the counter 113 according to the output of the comparator 122 when the inversion identification signal is at a high level.
  • the functions of the counter 113 include: adjusting the circuit characteristics of the differential input circuit 101, and changing the duty cycle of the first internal signal IBO+ and the duty cycle of the second internal signal IBO-, and the duty cycle of the first internal signal IBO+
  • the variation of the ratio and the duty ratio of the second internal signal IBO- is a monotonic variation, eg, the duty ratio changes from a minimum to a maximum or from a maximum to a minimum within one count period.
  • the output result of the comparator 122 will have one and only one inversion point, and the value of the counter 113 corresponding to the inversion point is the first internal signal IBO+ and the second internal signal IBO output by the differential input circuit 101
  • the duty cycle of - is closest to the setting of the second preset range, and this value is stored in the first register group 123 or the second register group 133 as the value of the counter 113 .
  • the first value of the counter 113 is stored according to the output of the comparator 122, and the first value is stored in the first register group 123; when the rollover identification signal is at a high level, according to the comparison
  • the output of the counter 122 stores the second value of the counter 113 which is stored in the second register set 133 .
  • the working principle of the logic unit 103 will be described in detail below:
  • the first input terminal 3 of the integration unit 112 receives the first internal signal IBO+, and the second input terminal 4 receives the second internal signal IBO-; the counter 113 starts counting, for example, from Counting starts from 0 and reaches 31.
  • the duty cycle of the first internal signal IBO+ and the second internal signal IBO- output by the differential input circuit 101 also changes from the minimum to the maximum (for example, from 40% to 60%) or from the maximum In this way, in one count period (for example, from 0 to 31), the comparator 122 will have one and only one reversal point, the value of the counter 113 corresponding to the reversal point is the first value, the first The value is the setting where the duty cycle of the first internal signal IBO+ output by the differential input circuit 101 is closest to the second preset range, for example, it may be the setting where the duty cycle is closest to 50%, and the first value is stored in the first register group 123.
  • the first input terminal 3 of the integration unit 112 receives the second internal signal IBO-
  • the second input terminal 4 receives the first internal signal IBO+, that is, the input terminals of the comparison unit 102 are interchanged, and the counter 113 Entering a new counting cycle, for example, counting from 0 and counting to 31 again, and similarly, the second value of the counter 113 corresponding to the output inversion point of the comparator 122 is stored in the second register group 133 .
  • the counter 113 may be a subtraction counter in addition to an addition counter, which may be sequentially incremented.
  • the counting can be counted down, and it can also be counted up or down in a stepwise manner, so as to ensure that the counter 113 changes monotonically within a single counting period.
  • the first input terminal 3 and the second input terminal 4 of the comparison unit 102 are interchanged, and the differential input circuit 101 is controlled by counting twice, which can eliminate the adverse effects caused by the input deviation of the comparison unit 102 itself, and further improve the test results. accuracy.
  • the logic unit 103 may further include: an arithmetic component 143, connected to the first register group 123 and the second register group 133, for performing addition, subtraction, multiplication and division operations on the outputs of the first register group 123 and the second register group 133; the third The register group 153 is connected to the operation component 143 and is used for storing the output result of the operation component 143 .
  • the output of the first register group 123 refers to the first value stored in the first register group 123
  • the output of the second register group 133 refers to the second value stored in the second register group 133
  • the arithmetic component 143 adds and divides the first value and the second value by 2 to obtain an average value
  • the average value is used as the output result of the arithmetic component 143
  • the average value is stored in the third register group 153 . Since the average value has eliminated the input deviation of the comparison unit 102 , the average value is that the duty ratios of the first internal signal IBO+ and the second internal signal IBO- output by the differential input circuit 101 are closest to the second preset range. , for example, the duty cycle of the first internal signal IBO+ and the second internal signal IBO- is closest to 50%.
  • the average value can be either the first value and the second value are added and divided by 2 and rounded up, or the first value and the second value can be added and divided by 2 and rounded down. the integer.
  • the average of the first value and the second value is used as an example, and in other embodiments, other operation methods may also be used to perform operation on the first value and the second value.
  • the first register group 123, the second register group 133 and the third register group 153 may all be mode registers.
  • the counter 113 is driven by a counter clock, and the frequency of the counter clock is lower than the frequency of the first internal signal IBO+ and/or the frequency of the second internal signal IBO-.
  • the frequency of the calculator clock is adjustable, and the frequency of the calculator clock is reasonably selected according to the speed of adjusting the differential input circuit 101 .
  • the frequency of the sampling clock can be the same as the frequency of the calculator clock.
  • the frequency divider can also be used to receive an external clock signal to generate the sampling clock and the calculator clock; similarly, the fifth register group can also be used to configure the frequency of the calculator clock.
  • the value stored in the third register group 153 corresponds to the setting of the differential input circuit 101.
  • the duty cycle selection of the differential input circuit 101 is switched from the counter 113 to the third register group 153, so that the fixed output of the differential input circuit has the optimal value.
  • the duty cycle of the first internal signal IBO+ and the second internal signal IBO- It can be understood that, during the period when the differential input circuit 101 outputs the first internal signal IBO+ and the second internal signal IBO- at the optimal duty ratio, the comparison unit 102 can continue to control the duty ratio and/or the duty ratio of the first internal signal IBO+.
  • the duty ratio of the second internal signal IBO- is compared. If the duty ratio of the first internal signal IBO+ and the duty ratio of the second internal signal IBO- deviate from the preset range, the problem can be detected in time.
  • the control terminal of the selector 111 receives a calibration enable signal dca.
  • the calibration enable signal dca is at a low level
  • the first external signal PAD+ and the second external signal PAD- are input to the differential input circuit 101
  • the calibration enable signal dca is at a high level
  • the first oscillation signal OSC+ and the second oscillation signal OSC ⁇ are input to the differential input circuit 101 .
  • the calibration circuit When the calibration enable signal dca is at a high level, the calibration circuit enters the duty cycle calibration state, and the corresponding first oscillating signal OSC+ and second oscillating signal OSC- with an initial duty cycle are input to the differential input circuit 101 to perform the duty cycle. Duty cycle calibration or duty cycle adjustment to realize the DCA function; when the calibration enable signal dca is at a low level, the calibration circuit exits the duty cycle calibration state, and the first external signal PAD+ and the second external signal PAD- are input to the differential input circuit 101, to perform duty cycle detection or duty cycle monitoring to implement the DCM function.
  • the calibration circuit provided in this embodiment, through the differential input circuit 101, the comparison unit 102 and the logic unit 103, can generate a stable first internal signal IBO+ and a second internal signal IBO- inside the memory, the first internal signal IBO+ and the third internal signal IBO- 2.
  • Internal signal IBO-meet the needs of the high-frequency working signal of the memory, so it can be used as the test input signal of the test memory, so that the memory can realize the built-in self-test function, without using an additional test machine to provide the test input signal, and at the same time solve the difficulty of the test machine.
  • the problem of providing a high frequency test input signal is a stable test input signal IBO+ and a second internal signal IBO- inside the memory, the first internal signal IBO+ and the third internal signal IBO- 2.
  • Internal signal IBO-meet the needs of the high-frequency working signal of the memory, so it can be used as the test input signal of the test memory, so that the memory can realize the built-in self-test function, without using an
  • the calibration circuit can also correct the differential input circuit 101.
  • the duty cycle deviation caused by the differential input circuit 101 itself can be reduced, thereby improving the read-write operation performance of the memory. , such as increased noise margin and improved signal integrity.
  • the comparison unit 102 detects the output of the differential input circuit 101, and the logic unit 103 controls the differential input circuit 101 based on the output result of the comparison unit 102, so as to ensure the first internal signal IBO+ and the second internal signal IBO+
  • the duty cycle of the signal IBO- can be stabilized within the second preset range, thereby avoiding the adverse effect of the duty cycle deviation on the test accuracy, and improving the use of the first internal signal IBO+ and the second internal signal IBO-.
  • the duty ratio of the first internal signal IBO+ and the second internal signal IBO- may be precisely controlled at 50%.
  • the calibration circuit provided in this embodiment also has a duty cycle monitoring function and a duty cycle calibration function.
  • an embodiment of the present application further provides a memory including the calibration circuit provided by the foregoing embodiments.
  • the memory may be memory such as DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, and NOR.
  • FIG. 3 is a schematic flowchart of a calibration method provided by an embodiment of the present application.
  • the calibration method in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, the calibration method can be performed by using the calibration circuit provided in the foregoing embodiment.
  • the calibration method includes the following steps:
  • Step S1 the differential input circuit receives the first oscillating signal OSC+ and the second oscillating signal OSC-, the first oscillating signal OSC+ and the second oscillating signal OSC- have the same frequency and opposite phase, the first oscillating signal OSC+ and the second oscillating signal OSC
  • the duty cycle of - is within the first preset range, and the differential input circuit outputs the first internal signal IBO+ and the second internal signal IBO-.
  • the first oscillating signal OSC+ and the second oscillating signal OSC- are signals with stable duty ratios, for example, the duty ratios of the first oscillating signal OSC+ and the second oscillating signal OSC- are both 50%.
  • Step S2 the comparing unit receives the first internal signal IBO+ and the second internal signal IBO-, and compares the duty ratio of the first internal signal IBO+ or the duty ratio of the second internal signal IBO-.
  • the duty cycle of the first internal signal IBO+ and the second internal signal IBO- output by the differential input circuit may deviate, for example, the duty cycle of the first internal signal IBO+ becomes 40%, and the duty cycle of the second internal signal IBO- is 60%.
  • the comparison unit compares the duty cycle of the first internal signal IBO+; when the inversion identification signal is at a high level, the comparison unit compares the duty cycle of the second internal signal IBO- Compare.
  • the comparing unit includes: an integrating unit, which has a first input terminal and a second input terminal, the first input terminal receives one of the first internal signal IBO+ or the second internal signal IBO-, and the second input terminal receives the second internal signal The other one of IBO- or the first internal signal IBO+; a comparator, connected to the output terminal of the integrating unit.
  • the comparator compares the duty cycle of the first internal signal IBO+ and has a corresponding Output; the comparator compares the duty ratio of the first internal signal IBO+, which can be: comparing the duty ratio of the first internal signal IBO+ and the duty ratio of the second internal signal IBO-, or comparing the first internal signal IBO+ and the preset duty cycle.
  • the comparator compares the duty cycle of the second internal signal IBO- and has a corresponding The comparator compares the duty ratio of the second internal signal IBO-, which can be: comparing the duty ratio of the second internal signal IBO- and the duty ratio of the first internal signal IBO+, or comparing the second internal signal IBO+.
  • the duty cycle of the signal IBO- is the same as the preset duty cycle.
  • the output result of the comparison unit represents the difference between the duty cycle of the first internal signal IBO+ and the duty cycle of the second internal signal IBO-.
  • the output result of the comparison unit is a high level, which indicates that the duty cycle of the first internal signal IBO+ is greater than the duty cycle of the second internal signal IBO-; the output result of the comparison unit is a low level, which indicates that the first internal signal IBO+
  • the duty cycle of is smaller than that of the second internal signal IBO-.
  • Step S3 the logic unit controls the differential input circuit according to the output result of the comparison unit, so that the duty cycle of the first internal signal IBO+ and/or the duty cycle of the second internal signal IBO- reach the second preset range.
  • the logic unit includes a counter, a first register group, and a second register group.
  • the differential input circuit is controlled by the counter to adjust the duty cycle of the first internal signal IBO+ and the duty cycle of the second internal signal IBO-.
  • the counter When the rollover identification signal is low, the counter counts from U to V, when the counter is U, the duty cycle corresponding to the first internal signal IBO+ is X%, and when the counter is V, the duty cycle corresponding to the first internal signal IBO+ is Y%, when the output result of the comparison unit changes from a low level to a high level, the counter value corresponding to the counter at this time is stored in the first register group.
  • U could be 0, V could be 7, X could be 40, and Y could be 60%.
  • the counter When the rollover identification signal is at high level, the counter counts from U to V, when the counter is U, the duty cycle corresponding to the second internal signal IBO- is Y%, and when the counter is V, the duty cycle corresponding to the second internal signal IBO- The empty ratio is X%.
  • the counter value corresponding to the counter at this time is stored in the second register group. For example, U could be 0, V could be 7, X could be 40, and Y could be 60%.
  • the first input terminal receives the first internal signal IBO+ and the second input terminal receives the second internal signal IBO-, and the counter counts from 0 to 7 in one count period
  • the output result of the comparison unit is a low level, it means that the duty cycle of the first internal signal IBO+ is smaller than the duty cycle of the second internal signal IBO-; when the output result of the comparison unit is a high level, it means that the duty cycle of the first internal signal IBO+ is less than that of the first internal signal IBO+.
  • the duty ratio is greater than that of the second internal signal IBO-.
  • the output result of the comparison unit jumps from a low level to a high level corresponding to a reversal point.
  • the value of the counter at this time is 3, and the counter value 3 of the counter corresponding to the reversal point is stored as the first value.
  • first register set the value of the counter at this time.
  • the first input terminal receives the second internal signal IBO- and the second input terminal receives the first internal signal IBO+
  • the counter counts from 0 to 7 in one count cycle, and the output of the comparison unit
  • the result is a high level, it means that the duty cycle of the first internal signal IBO+ is smaller than that of the second internal signal IBO-; when the output result of the comparison unit is a low level, it means that the duty cycle of the first internal signal IBO+ is greater than that of the first internal signal IBO+. 2.
  • Duty cycle of internal signal IBO- Therefore, the output result of the comparison unit jumps from a high level to a low level corresponding to an inversion point.
  • the value of the counter at this time is 4, and the counter value 4 of the counter corresponding to the inversion point is stored as the second value.
  • the second register group is 4, and the counter value 4 of the counter corresponding to the inversion point is stored as the second value.
  • the duty cycle of the first internal signal IBO+ can be a preset step. Incrementally, for example, each time the counter value of the counter increases by 1, the duty cycle of the first internal signal IBO+ increases by ((60-40)/8)%.
  • the flip identification signal is at a high level, the counter counts from 0 to 7, and the duty cycle of the second internal signal IBO- changes monotonically.
  • the duty cycle of the first internal signal IBO+ can be a preset step. The formula increases, for example, every time the counter value of the counter increases by 1, the duty cycle of the first internal signal IBO+ increases by ((60-40)/8)%.
  • the logic unit also includes an operation component and a third register group; the operation component performs addition, subtraction, multiplication and division operations on the outputs of the first register group and the second register group, and stores the obtained value H in the third register group; wherein, H is a positive Integer, H is greater than or equal to U and less than or equal to V.
  • the value H is the addition of the first value and the second value divided by 2, that is, the value H is the average of the first value and the second value, and the value H corresponds to the first internal signal IBO+ and the second internal signal
  • H is equal to (3+4)/2, that is, H is equal to 3.5
  • H can be rounded up to 3 or rounded down to 4. That is, the value H corresponds to the duty ratio of the first internal signal IBO+ within a second preset range, and the second preset range may be 48% ⁇ 52%, for example, 50%.
  • the counter is no longer controlled by the differential input circuit, but the value H is used as the setting of the differential input circuit, so that the differential input circuit outputs the first internal signal IBO+ with a preset duty cycle, and the corresponding second
  • the internal signal IBO- is also a signal whose duty cycle meets the requirements.
  • the solution of the calibration method provided in this embodiment can generate the first internal signal IBO+ and the second internal signal IBO- with high speed and high quality, and the first internal signal IBO+ and the second internal signal IBO- have stable duty ratios.
  • clock signal, and the first internal signal IBO+ and the second internal signal IBO- can be used as clock signals required for the memory to perform read and write operations.
  • the differential input circuit can also be calibrated, the influence of the differential input circuit on the duty cycle can be detected in time, and the duty cycle of the first internal signal IBO+ and the second internal signal IBO- outputted by the differential input circuit can be guaranteed.
  • the empty ratio reaches the second preset range. For example, referring to FIG. 2 and FIG.
  • the duty cycle of the first internal signal IBO+ is adjusted from 40% to 50%
  • the duty cycle of the second internal signal IBO- is adjusted from 60% to 50%. In this way, the deviation caused by the differential input circuit 101 to the clock duty ratio is eliminated.
  • the calibration circuit includes: a differential input circuit, configured to receive a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal have the same frequency and opposite phase, and the first oscillation signal and the second oscillation signal have the same frequency and opposite phase.
  • the duty cycle of an oscillating signal and the duty cycle of the second oscillating signal are within a first preset range, the differential input circuit outputs a first internal signal and a second internal signal; a comparison unit is connected to the differential input an output end of the circuit, and compares the duty cycle of the first internal signal and/or the duty cycle of the second internal signal; a logic unit, connected to the comparison unit and the differential input circuit, is used for The differential input circuit is controlled according to the output result of the comparison unit, so that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reach a second preset range.
  • the calibration circuit provided by the embodiment of the present application can not only generate a differential internal signal based on the first oscillation signal and the second oscillation signal, but also have the functions of duty cycle monitoring and duty cycle calibration, ensuring that the first internal signal generated by the calibration circuit is The duty cycle of the signal and the second internal signal is stable within the second preset range; correspondingly, when the first internal signal and the second internal signal are used to test the memory, it is beneficial to avoid the duty cycle deviation of the input signal The resulting test deviation problem is conducive to improving the test accuracy of the memory test, and at the same time, the memory can also realize the functions of duty cycle monitoring and duty cycle calibration.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

本申请实施例提供一种校准电路、存储器以及校准方法，校准电路包括：差分输入电路，用于接收第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反，所述第一振荡信号的占空比和所述第二振荡信号的占空比在第一预设范围内，所述差分输入电路输出第一内部信号和第二内部信号；比较单元，连接所述差分输入电路的输出端，并对所述第一内部信号的占空比和/或所述第二内部信号的占空比进行比较；逻辑单元，连接所述比较单元和所述差分输入电路，用于根据所述比较单元的输出结果对所述差分输入电路进行控制，使得所述第一内部信号的占空比和/或所述第二内部信号的占空比到达第二预设范围内。本申请实施例中，校准电路具有DCM功能以及DCA功能，且还能够实现对差分输入电路的检测和校准。

Description

校准电路、存储器以及校准方法
相关申请的交叉引用
本申请要求在2020年10月28日提交中国专利局、申请号为202011173755.3、申请名称为“校准电路、存储器以及校准方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及但不限于一种校准电路、存储器以及校准方法。
背景技术
半导体存储器被用于许多电子系统中，以存储可取回的数据。随着对电子系统更快、具有更大数据容量和消耗更少电力的需求不断增长，为了满足不断变化的需求，半导体存储器可能需要更快的速度，存储更多的数据并使用更少的电力。
通常的，通过向存储器提供命令(commands)、存储地址(memory address)以及时钟(clocks)来控制半导体存储器，且各种命令、存储地址以及时钟可以由存储控制器(memory controller)提供。这三类信号可以控制存储器执行各种存储操作，例如从存储器中读取数据的读取操作，以及将数据存储到存储器的写入操作。基于与存储器接收到的“相关命令”相关的已知时序，在存储器与存储控制器之间传输数据。具体地，可以向存储器提供用于对命令和地址进行计时的系统时钟(system clock)，进一步地，还可以向存储器提供数据时钟(data clock)，该数据时钟用于作为读取数据的时序以及写入数据的时序。此外，存储器还可以向控制器提供时钟，以作为向控制器传输数据的时序。提供给存储器的外部时钟用于产生内部时钟，这些内部时钟在存储器的存储操作期间控制各种内部电路的时序。在存储器操作期间内部电路的时序很关键，并且内部时钟的偏差可能会导致错误的操作，时钟的偏差包括占空比失真，即时钟信号的 占空比偏离预设占空比。
因此，存储器需具备DCA功能以及DCM功能，即存储器包括占空比调节(DCA，Duty Cycle Adjust)电路以及占空比监测(DCM，Duty Cycle Monitor)电路，占空比调节电路可以用于调节外部时钟生成的内部时钟的占空比，占空比监测电路可用于监测时钟的占空比是否偏离预设占空比。
发明内容
本申请实施例提供一种校准电路，包括：差分输入电路，用于接收第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反，所述第一振荡信号的占空比和所述第二振荡信号的占空比在第一预设范围内，所述差分输入电路输出第一内部信号和第二内部信号；比较单元，连接所述差分输入电路的输出端，并对所述第一内部信号的占空比和/或所述第二内部信号的占空比进行比较；逻辑单元，连接所述比较单元和所述差分输入电路，用于根据所述比较单元的输出结果对所述差分输入电路进行控制，使得所述第一内部信号的占空比和/或所述第二内部信号的占空比到达第二预设范围内。
本申请实施例还提供一种存储器，包括上述的校准电路。
本申请实施例还提供一种校准方法，包括：差分输入电路接收第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反，所述第一振荡信号和第二振荡信号的占空比在第一预设范围内，所述差分输入电路输出第一内部信号和第二内部信号；比较单元接收所述第一内部信号和第二内部信号，并对所述第一内部信号的占空比或第二内部信号的占空比进行比较；逻辑单元根据所述比较单元的输出结果对所述差分输入电路进行控制，使得所述第一内部信号的占空比和/或第二内部信号的占空比到达第二预设范围内。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请一实施例提供的校准电路的功能框图；
图2为本申请一实施例提供的校准电路的结构示意图；
图3为本申请另一实施例提供的校准方法的流程示意图。
具体实施方式
由背景技术可知，目前存储器的工作频率越来越快，因此对输入信号的占空比要求越来越严格，利用符合需求的DCA功能以及DCM功能对输入信号的占空比的校准和监测很重要。此外，存储器中具有接收外部时钟信号以产生内部时钟信号的差分输入电路，差分输入电路固有的电路特性可能会造成内部时钟信号的占空比偏差。若不及时将差分输入电路对占空比偏差的影响进行检测并校准，则会影响存储器的读写性能。
为解决上述问题，本申请实施提供一种校准电路，占空比在第一预设范围的第一振荡信号和第二振荡信号经由差分输入电路后，输出第一内部信号和第二内部信号，该第一内部信号和第二内部信号可作为对存储器进行测试时采用的实际输入信号；通过比较单元对第一内部信号和第二内部信号的占空比的检测，以及逻辑单元基于检测结果对差分输入电路进行控制，保证第一内部信号的占空比和第二内部信号的占空比能够到达且稳定在第二预设范围内，使用该第一内部信号和第二内部信号进行测试，能够改善测试结果的准确性。此外，该校准电路还具有DCM功能和DCM功能，能够对差分输入电路的工作状态进行校准，减小甚至避免差分输入电路对占空比偏差造成的影响，改善具有该校准电路的存储器的读写性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解， 在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请一实施例提供的校准电路的功能框图，图2为本申请一实施例提供的校准电路的结构示意图。
参考图1及图2，本实施例中，校准电路包括：差分输入电路101，用于接收第一振荡信号OSC+和第二振荡信号OSC-，第一振荡信号OSC+与第二振荡信号OSC-的频率相同且相位相反，第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比在第一预设范围内，差分输入电路101输出第一内部信号IBO+和第二内部信号IBO-；比较单元102，连接差分输入电路101的输出端，并对第一内部信号IBO+的占空比和/或第二内部信号IBO-的占空比进行比较；逻辑单元103，连接比较单元102和差分输入电路101，用于根据比较单元102的输出结果对差分输入电路101进行控制，使得第一内部信号IBO+的占空比和/或第二内部信号IBO-的占空比到达第二预设范围内。
该校准电路可内置于存储器内，既能够用于接收外部时钟信号产生内部时钟信号，还能够接收用于测试的第一振荡信号和第二振荡信号产生第一内部信号和第二内部信号，且第一内部信号的占空比和第二内部信号的占空比可稳定在第二预设范围内，从而提高了测试存储器的测试结果的准确性。此外，校准电路还可以实现存储器的占空比校准功能以及占空比监测功能，以及实现对差分输入电路的校准功能，避免差分输入电路对时钟信号造成的占空比偏差问题。
以下将结合附图对本实施例提供的校准电路进行详细说明。
第一振荡信号OSC+和第二振荡信号OSC-为差分的时钟信号，且第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比在第一预设范围内，也就是说，第一振荡信号OSC+和第二振荡信号OSC-为高质量信号。在一个例子中，第一预设范围可以为48％～52％。
此外，本实施例中，第一振荡信号OSC+和第二振荡信号OSC-可以具有高频特性，也就是说，第一振荡信号OSC+的频率与第二振荡信号OSC-的频率与 存储器进行读写操作所需的时钟信号的频率相当，此处的相当既可以为频率相同，也可以指频率差异在测试允许范围内。例如，第一振荡信号OSC+和第二振荡信号OSC-的频率可以达到3.2GHz或4.8GHz甚至6.4GHz。
此外，第一振荡信号OSC+和第二振荡信号OSC-可由内置于存储器内的振荡电路提供。
本实施例中，差分输入电路101可以包括输入缓冲器(IB，Input Buffer)，用于接收差分的第一振荡信号OSC+和第二振荡信号OSC-，并输出差分的第一内部信号IBO+和第二内部信号IBO-。
此外，本实施例中，差分输入电路101还可用于接收第一外部信号PAD+和第二外部信号PAD-，且第一外部信号的频率与第二外部信号的频率相同且相位相反，也就是说，第一外部信号PAD+和第二外部信号PAD-也为差分信号。相应的，校准电路还包括：选择器111，第一振荡信号OSC+、第二振荡信号OSC-、第一外部信号PAD+以及第二外部信号PAD-均通过选择器111连接至差分输入电路101，记第一振荡信号OSC+和第二振荡信号OSC-为第一差分对信号，记第一外部信号PAD+和第二外部信号PAD-为第二差分对信号，选择器111用于选择第一差分对信号和第二差分对信号之一输入差分输入电路101。
由于差分输入电路101具有固有的电路特性，即使第一振荡信号OSC+和第二振荡信号OSC-的占空比符合要求，但经由差分输入电路101输出后获得的第一内部信号IBO+和第二内部信号IBO-的占空比可能发生偏离。为此，采用比较单元102对第一内部信号IBO+的占空比和第二内部信号IBO-的占空比进行检测。
由于第一内部信号IBO+与第二内部信号IBO-为差分信号，因此第一内部信号IBO+的占空比与第二内部信号IBO-的占空比之和为100％，通过设置比较单元102检测差分的第一内部信号IBO+和第二内部信号IBO-的占空比大小。具体地，比较单元102对第一内部信号IBO+的占空比和/或第二内部信号IBO-的占空比进行比较，包括以下三种情况中的至少一种：
比较单元102对第一内部信号IBO+的占空比进行比较。具体地，比较单元 102比较第一内部信号IBO+的占空比是否到达第二预设范围内，第二预设范围可以与第一预设范围相同，例如，该第二预设范围可以为48％～52％。若比较单元102比较第一内部信号IBO+的占空比在第二预设范围内，则说明第二内部信号IBO-的占空比也在第二预设范围内；若比较单元102比较第一内部信号IBO+的占空比不在第二预设范围内，则说明第二内部信号IBO-的占空比也不在第二预设范围内。
比较单元102对第二内部信号IBO-的占空比进行比较。具体地，比较单元102比较第二内部信号IBO-的占空比是否到达第二预设范围内，该第二预设范围可以为48％～52％。若比较单元102比较第二内部信号IBO-的占空比在第二预设范围内，则说明第一内部信号IBO+的占空比也在第二预设范围内；若比较单元102比较第二内部信号IBO-的占空比不在第二预设范围内，则说明第一内部信号IBO+的占空比也不在第二预设范围内。
比较单元102对第一内部信号IBO+的占空比与第二内部信号IBO-的占空比进行比较。具体地，比较单元102获取第一内部信号IBO+的占空比与第二内部信号IBO-的占空比的差值是否在预设差值范围内，该预设差值范围可以为-4％～4％；若比较单元102比较该差值在预设差值范围内，则说明第一内部信号IBO+和第二内部信号IBO-的占空比在第二预设范围内，否则，第一内部信号IBO+和第二内部信号IBO-的占空比未到达第二预设范围。
需要说明的是，上述的第二预设范围以及预设差值范围的数值范围均为示例性说明，本实施例并不对第二预设范围以及预设差值范围做限定，可根据存储器的实际性能需求合理设置第二预设范围以及预设差值范围。
本实施例中，比较单元102包括：积分单元112，其具有第一输入端3和第二输入端4，第一输入端3接收第一内部信号IBO+或者第二内部信号IBO-中的一者，第二输入端4接收第一内部信号IBO+或第二内部信号IBO-中的另一者；比较器122，连接积分单元112的输出端。
具体地，积分单元112包括两个积分电路，且第一输入端3作为一积分电路的输入端，第二输入端4作为另一积分电路的输入端。比较器122用于比较 两个积分电路的输出并输出高电平或者低电平。
更具体地，比较单元102由两个积分电路对输入的第一内部信号IBO+和第二内部信号IBO-进行积分运算，且积分运算的结果输入至比较器122中，且比较器122输出比较结果。
以第一内部信号IBO+为正端(duty+)且第二内部信号IBO-为负端(duty-)为例，在一个例子中，比较器122的输出为高电平，则表明第一内部信号IBO+的占空比大于第二内部信号IBO-的占空比；比较器122的输出为低电平，则表明第一内部信号IBO+的占空比小于第二内部信号IBO-的占空比。
需要说明的是，上述关于比较单元102的输出结果与第一内部信号IBO+的占空比和第二内部信号IBO-的占空比之间的对应关系仅为示例，本实施例并不限定高电平以及低电平与第一内部信号IBO+的占空比和第二内部信号IBO-的占空比之间的对应关系，只要保证不同的输出结果对应不同的第一内部信号IBO+的占空比和第二内部信号IBO-的占空比之间的对应关系即可。
如图2所示，比较单元102的输出结果可以经采样时钟clk1采样输出。本实施例中，比较单元102由一采样时钟clk1驱动，采样时钟clk1的频率低于第一内部信号IBO+的频率和/或第二内部信号IBO-的频率。采样时钟clk1的频率越快，则采样误差越大；采样时钟clk1的频率越慢，则采样误差越小，但测试时间越长。因此，可根据采样误差以及测试时间综合选择采样时钟clk1的最优频率。
本实施例中，时钟产生电路还包括：分频器104，接收一外部时钟信号CLK，产生采样时钟clk1。该外部时钟信号CLK既可以是测试机提供的，也可以是存储器提供的。
此外，由前述分析可知，若采样时钟clk1的频率可调，则可根据实际情况选择不同的采样时钟clk1频率，为此，本实施例中，时钟产生电路还可以包括：第五寄存器组105，与分频器104连接，用于配置采样时钟的频率。第五寄存器组105可以为模式寄存器。
由于比较单元102的固有特性可能会带来输入偏差，为了消除比较单元102 自有的输入偏差对测试结果带来的误差，本实施例中，比较单元102还可以被配置为第一输入端3和第二输入端4可互换。具体地，比较单元102被配置为：
积分单元112的第一输入端3在一翻转标识信号为低电平时接收第一内部信号IBO+，在翻转标识信号为高电平时接收第二内部信号IBO-；积分单元112的第二输入端4在翻转标识信号为低电平时接收第二内部信号IBO-，在翻转标识信号为高电平时接收第一内部信号IBO+。其中，存储器中具有模式寄存器，该翻转标识信号可以由模式寄存器提供，例如在LPDDR4或者LPDDR5或者LPDDR6中，翻转标识信号可定义为DCM MR OP[1]，DCM MR OP[1]＝0表示翻转标识信号为低电平，DCM MR OP[1]＝1表示翻转标识信号为高电平。
逻辑单元103基于比较单元102的检测结果对差分输入电路101进行控制，调整差分输入电路101的电路特性，以使调整后的差分输入电路101输出的第一内部信号IBO+和第二内部信号IBO-的占空比到达第二预设范围内。
具体地，逻辑单元103包括：计数器113，用于调节第一内部信号IBO+和/或第二内部信号IBO-的占空比；第一寄存器组123，当翻转标识信号为低电平时，根据比较器122的输出存储计数器113的第一值；第二寄存器组133，当翻转标识信号为高电平时，根据比较器122的输出存储计数器113的第二值。
具体地，计数器113的作用包括：调节差分输入电路101的电路特性，且改变第一内部信号IBO+的占空比以及第二内部信号IBO-的占空比，且第一内部信号IBO+的占空比以及第二内部信号IBO-的占空比的变化为单调性变化，例如在一个计数周期内占空比从最小变到最大或者从最大变到最小。在一个计数周期内，比较器122的输出结果将有且仅有一个反转点，该反转点对应的计数器113的值是差分输入电路101输出的第一内部信号IBO+和第二内部信号IBO-的占空比最接近第二预设范围的设置，将这个值作为计数器113的值存入第一寄存器组123或者第二寄存器组133。
更具体地，当翻转标识信号为低电平时，根据比较器122的输出存储计数器113的第一值，该第一值存入第一寄存器组123；当翻转标识信号为高电平时，根据比较器122的输出存储计数器113的第二值，该第二值存入第二寄存 器组133。为便于理解，以下将对逻辑单元103的工作原理进行详细说明：
当翻转标识信号为低电平时，积分单元112的第一输入端3接收第一内部信号IBO+，第二输入端4接收第二内部信号IBO-；计数器113开始计数，例如在一个计数周期内从0开始计数且计到31，同时差分输入电路101输出的第一内部信号IBO+和第二内部信号IBO-的占空比也从最小变到最大(例如从40％变到60％)或者从最大变到最小；这样，在一个计数周期(例如从0到31)内，比较器122将有且仅有一个反转点，该反转点对应的计数器113的值为第一值，该第一值是差分输入电路101输出的第一内部信号IBO+的占空比最接近第二预设范围的设置，例如可以是占空比最接近50％的设置，该第一值存入第一寄存器组123中。
当翻转标识信号为高电平时，积分单元112的第一输入端3接收第二内部信号IBO-，第二输入端4接收第一内部信号IBO+，即比较单元102的输入端互换，计数器113进入新的计数周期，例如重新从0开始计数且计到31，同样的，将比较器122的输出反转点对应的计数器113的第二值存入第二寄存器组133中。
需要说明的是，上述从0到31的计数周期仅为示例说明，本实施例中并不对计数器113的计数方式进行限定，计数器113除为加法计数器外也可以为减法计数器，既可以为依次递增或者递减式计数，也可以为步进式递增或者递减计数，保证计数器113在单个计数周期内单调性变化即可。
比较单元102的第一输入端3与第二输入端4互换，通过两次计数控制差分输入电路101的方式，可以消除比较单元102自身的输入偏差带来的不良影响，进一步的提高测试结果的准确性。
此外，逻辑单元103还可以包括：运算组件143，连接第一寄存器组123和第二寄存器组133，用于对第一寄存器组123和第二寄存器组133的输出做加减乘除运算；第三寄存器组153，连接运算组件143，用于存储运算组件143的输出结果。
具体地，第一寄存器组123的输出指的是存入第一寄存器组123的第一值， 第二寄存器组133的输出指的是存入第二寄存器组133的第二值。本实施例中，运算组件143对第一值和第二值进行相加除以2，得到平均值，且该平均值作为运算组件143的输出结果，该平均值被存入第三寄存器组153。由于该平均值已经消除掉比较单元102自有的输入偏差，因此该平均值为差分输入电路101输出的第一内部信号IBO+和第二内部信号IBO-的占空比最接近第二预设范围的设置，例如第一内部信号IBO+和第二内部信号IBO-的占空比最接近50％。
可以理解的是，该平均值既可以是第一值和第二值进行相加除以2向上取整的整数，也可以是第一值和第二值进行相加除以2向下取整的整数。
需要说明的是，本实施例中以对第一值和第二值取平均作为示例，在其他实施例中，也可以采用其他的运算方式对第一值和第二值进行运算。
第一寄存器组123、第二寄存器组133以及第三寄存器组153均可以为模式寄存器。
本实施例中，计数器113由一计算器时钟驱动，计算器时钟的频率低于第一内部信号IBO+的频率和/或第二内部信号IBO-的频率。计算器时钟的频率可调，根据调整差分输入电路101的速度合理选择计算器时钟的频率。
此外，采样时钟的频率可以与计算器时钟的频率相同。分频器还可以用于接收一外部时钟信号，产生采样时钟和计算器时钟；同样的，第五寄存器组还可以用于配置计算器时钟的频率。
存入第三寄存器组153的值对应为差分输入电路101的设置，此时，差分输入电路101的占空比选择由计数器113切换为第三寄存器组153，使得差分输入电路固定输出具有最优占空比的第一内部信号IBO+和第二内部信号IBO-。可以理解的是，在差分输入电路101固定以最优占空比输出第一内部信号IBO+和第二内部信号IBO-期间，比较单元102可以持续对第一内部信号IBO+的占空比和/或第二内部信号IBO-的占空比进行比较，若第一内部信号IBO+的占空比和第二内部信号IBO-的占空比偏离预设范围，能够及时检测出这一问题。
另外，本实施例中，选择器111的控制端接收一校准使能信号dca，当所述校准使能信号dca为低电平时，第一外部信号PAD+和第二外部信号PAD-输入 差分输入电路101，当所述校准使能信号dca为高电平时，第一振荡信号OSC+和第二振荡信号OSC-输入差分输入电路101。
校准使能信号dca为高电平，则校准电路进入占空比校准状态，相应的具有初始占空比的第一振荡信号OSC+和第二振荡信号OSC-输入至差分输入电路101，以执行占空比校准或占空比调节，实现DCA功能；校准使能信号dca为低电平，则校准电路退出占空比校准状态，第一外部信号PAD+和第二外部信号PAD-输入至差分输入电路101，以执行占空比检测或占空比监测，实现DCM功能。
本实施例提供的校准电路，通过差分输入电路101、比较单元102以及逻辑单元103，能够在存储器内部产生稳定的第一内部信号IBO+和第二内部信号IBO-，该第一内部信号IBO+和第二内部信号IBO-满足存储器高频工作信号的需求，因此能够作为测试存储器的测试输入信号，使得存储器能够实现内置自测功能，无需利用额外的测试机提供测试输入信号，同时解决了测试机难以提供高频的测试输入信号的问题。
同时，该校准电路还能够对差分输入电路101进行校正，当存储器中应用该校准电路时，可以减小由差分输入电路101本身所引起的占空比偏差，从而提高了存储器的读写操作性能，例如提高了噪声容限且改善了信号完整性。
此外，本实施例中，比较单元102对差分输入电路101的输出进行检测，且逻辑单元103基于比较单元102的输出结果对差分输入电路101进行控制，从而保证第一内部信号IBO+和第二内部信号IBO-的占空比能够稳定在第二预设范围内，从而避免了占空比偏差对测试准确度带来的不良影响，提高利用第一内部信号IBO+和第二内部信号IBO-对存储器进行测试的测试准确度。例如，第一内部信号IBO+和第二内部信号IBO-的占空比可精确控制在50％。
同时，本实施例提供的校准电路，还具有占空比监测功能以及占空比校准功能。
相应的，本申请实施例还提供一种存储器，包括前述实施例提供的校准电 路。具体地，该存储器可以为DRAM、SRAM、MRAM、FeRAM、PCRAM、NAND、NOR等存储器。
由前述分析可知，在存储器内部可产生可用于测试的高速第一内部信号和第二内部信号，且第一内部信号和第二内部信号的占空比能够维持在第二预设范围内，因而无需利用额外的测试机提供测试信号，从而有利于提高对存储器进行测试的测试准确度。
相应的，本申请实施例还提供一种校准方法。图3为本申请一实施例提供的校准方法的流程示意图。以下将结合附图对本申请实施例中校准方法进行详细说明。需要说明的是，该校准方法可利用前述实施例提供的校准电路进行。
参考图2和图3，本实施例中，校准方法包括以下步骤：
步骤S1、差分输入电路接收第一振荡信号OSC+和第二振荡信号OSC-，第一振荡信号OSC+与第二振荡信号OSC-的频率相同且相位相反，第一振荡信号OSC+和第二振荡信号OSC-的占空比在第一预设范围内，差分输入电路输出第一内部信号IBO+和第二内部信号IBO-。
具体地，第一振荡信号OSC+和第二振荡信号OSC-为具有稳定占空比的信号，例如第一振荡信号OSC+和第二振荡信号OSC-的占空比都为50％。
步骤S2、比较单元接收第一内部信号IBO+和第二内部信号IBO-，并对第一内部信号IBO+的占空比或第二内部信号IBO-的占空比进行比较。
差分输入电路输出的第一内部信号IBO+和第二内部信号IBO-的占空比有可能出现偏差，例如第一内部信号IBO+占空比变为40％，第二内部信号IBO-占空比变为60％。
具体地，当翻转标识信号为低电平时，比较单元对第一内部信号IBO+的占空比进行比较；当翻转标识信号为高电平时，比较单元对第二内部信号IBO-的占空比进行比较。
比较单元包括：积分单元，其具有第一输入端和第二输入端，第一输入端接收第一内部信号IBO+或第二内部信号IBO-中的一者，第二输入端接收第二 内部信号IBO-或第一内部信号IBO+中的另一者；比较器，连接积分单元的输出端。
当翻转标识信号为低电平时，第一输入端接收第一内部信号IBO+且第二输入端接收第二内部信号IBO-，比较器对第一内部信号IBO+的占空比进行比较且具有相应的输出；比较器对第一内部信号IBO+的占空比进行比较，可以为：比较第一内部信号IBO+的占空比与第二内部信号IBO-的占空比，或者，比较第一内部信号IBO+的占空比与预设占空比。
当翻转标识信号为高电平时，第一输入端接收第二内部信号IBO-且第二输入端接收第一内部信号IBO+，比较器对第二内部信号IBO-的占空比件比较且具有相应的输出；比较器对第二内部信号IBO-的占空比进行比较，可以为：比较第二内部信号IBO-的占空比与第一内部信号IBO+的占空比，或者，比较第二内部信号IBO-的占空比与预设占空比。
比较单元的输出结果表征第一内部信号IBO+的占空比与第二内部信号IBO-的占空比之间的差值。例如，比较单元的输出结果为高电平，表征第一内部信号IBO+的占空比大于第二内部信号IBO-的占空比；比较单元的输出结果为低电平，表征第一内部信号IBO+的占空比小于第二内部信号IBO-的占空比。
步骤S3、逻辑单元根据比较单元的输出结果对差分输入电路进行控制，使得第一内部信号IBO+的占空比和/或第二内部信号IBO-的占空比到达第二预设范围内。
具体地，逻辑单元包括计数器、第一寄存器组、第二寄存器组。通过计数器控制差分输入电路，以调整第一内部信号IBO+的占空比和第二内部信号IBO-的占空比。
当翻转标识信号为低电平时，计数器从U计数至V，当计数器为U时对应第一内部信号IBO+的占空比为X％，当计数器为V时对应第一内部信号IBO+的占空比为Y％，当比较单元的输出结果由低电平变为高电平时，将此时计数器对应的计数器值存入所述第一寄存器组。例如，U可以为0，V可以为7，X可以为40，Y可以为60％。
当翻转标识信号为高电平时，计数器从U计数至V，当计数器为U时对应第二内部信号IBO-的占空比为Y％，当计数器为V时对应第二内部信号IBO-的占空比为X％，当比较单元的输出结果由高电平变为低电平时，将此时计数器对应的计数器值存入第二寄存器组。例如，U可以为0，V可以为7，X可以为40，Y可以为60％。
更具体地，例如，当翻转标识信号为低电平时，第一输入端接收第一内部信号IBO+且第二输入端接收第二内部信号IBO-，计数器在一个计数周期内由0计数至7，比较单元的输出结果为低电平时，说明第一内部信号IBO+的占空比小于第二内部信号IBO-的占空比；比较单元的输出结果为高电平时，说明第一内部信号IBO+的占空比大于第二内部信号IBO-的占空比。因此，比较单元的输出结果由低电平跳转为高电平对应具有一个反转点，例如此时计数器的值为3，该反转点对应的计数器的计数器值3作为第一值存入第一寄存器组。
例如，当翻转标识信号为高电平时，第一输入端接收第二内部信号IBO-且第二输入端接收第一内部信号IBO+，计数器在一个计数周期内由0计数至7，比较单元的输出结果为高电平时，说明第一内部信号IBO+的占空比小于第二内部信号IBO-的占空比；比较单元的输出结果为低电平时，说明第一内部信号IBO+的占空比大于第二内部信号IBO-的占空比。因此，比较单元的输出结果由高电平跳转为低电平对应具有一个反转点，例如此时计数器的值为4，该反转点对应的计数器的计数器值4作为第二值存入第二寄存器组。
需要说明的是，当翻转标识信号为低电平，计数器从0计数至7，第一内部信号IBO+的占空比是单调性变化，例如第一内部信号IBO+的占空比可以为预设步进式递增，如计数器的计数器值每增加1，则第一内部信号IBO+的占空比增加((60-40)/8)％。同理，当翻转标识信号为高电平，计数器从0计数至7，第二内部信号IBO-的占空比是单调性变化，例如第一内部信号IBO+的占空比可以为预设步进式递增，如计数器的计数器值每增加1，则第一内部信号IBO+的占空比增加((60-40)/8)％。
逻辑单元还包括运算组件、第三寄存器组；运算组件将第一寄存器组和第 二寄存器组的输出做加减乘除运算，并将得到的数值H存入第三寄存器组；其中，H为正整数，H大于等于U且小于等于V。
本实施例中，数值H为第一值和第二值相加除以2，即数值H为第一值和第二值取平均，该数值H即为对应第一内部信号IBO+和第二内部信号IBO-到达第二预设范围的设置，例如H等于(3+4)/2，即H等于3.5，H还可以上取整为3或下取整为4。也就是说，数值H对应第一内部信号IBO+的占空比在第二预设范围内，该第二预设范围可以为48％～52％，例如为50％。
在获取数值H后，不再由计数器控制差分输入电路，而是将数值H作为差分输入电路的设置，以使差分输入电路输出具有预设占空比的第一内部信号IBO+，相应的第二内部信号IBO-也为占空比符合要求的信号。
本实施例提供的校准方法的方案，能够产生高速高质量的第一内部信号IBO+和第二内部信号IBO-，且第一内部信号IBO+和第二内部信号IBO-为具有稳定的占空比的时钟信号，且第一内部信号IBO+和第二内部信号IBO-可作为存储器进行读写操作所需的时钟信号。此外，利用该校准方法还能够对差分输入电路进行校准，以及时检测出差分输入电路对占空比的影响，保证经由差分输入电路输出的第一内部信号IBO+和第二内部信号IBO-的占空比达到第二预设范围。例如，参考图2和图3，经过本实施例提供的校准方法，第一内部信号IBO+的占空比由40％调节到50％，第二内部信号IBO-的占空比由60％调节到50％。如此，从而消除了差分输入电路101对时钟占空比引起的偏差。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例中，校准电路包括：差分输入电路，用于接收第一振荡信号 和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反，所述第一振荡信号的占空比和所述第二振荡信号的占空比在第一预设范围内，所述差分输入电路输出第一内部信号和第二内部信号；比较单元，连接所述差分输入电路的输出端，并对所述第一内部信号的占空比和/或所述第二内部信号的占空比进行比较；逻辑单元，连接所述比较单元和所述差分输入电路，用于根据所述比较单元的输出结果对所述差分输入电路进行控制，使得所述第一内部信号的占空比和/或所述第二内部信号的占空比到达第二预设范围内。这样，本申请实施例提供的校准电路不仅能够基于第一振荡信号和第二振荡信号产生差分的内部信号，且还具有占空比监测和占空比校准功能，保证校准电路产生的第一内部信号和第二内部信号的占空比稳定在第二预设范围内；相应的，当采用该第一内部信号和第二内部信号对存储器进行测试时，有利于避免输入信号的占空比偏差带来的测试偏差问题，有利于提高对存储器进行测试的测试准确性，同时使得存储器还可以实现占空比监测和占空比校准功能。

Claims (19)

  1. 一种校准电路，包括：
    差分输入电路，用于接收第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反，所述第一振荡信号的占空比和所述第二振荡信号的占空比在第一预设范围内，所述差分输入电路输出第一内部信号和第二内部信号；
    比较单元，连接所述差分输入电路的输出端，并对所述第一内部信号的占空比和/或所述第二内部信号的占空比进行比较；
    逻辑单元，连接所述比较单元和所述差分输入电路，用于根据所述比较单元的输出结果对所述差分输入电路进行控制，使得所述第一内部信号的占空比和/或所述第二内部信号的占空比到达第二预设范围内。
  2. 根据权利要求1所述的校准电路，其中，所述比较单元包括：
    积分单元，其具有第一输入端和第二输入端，所述第一输入端接收所述第一内部信号或第二内部信号中的一者，所述第二输入端接收所述第二内部信号或第一内部信号中的另一者；
    比较器，连接所述积分单元的输出端。
  3. 根据权利要求2所述的校准电路，其中，
    所述积分单元的第一输入端在一翻转标识信号为低电平时接收所述第一内部信号，在所述翻转标识信号为高电平时接收所述第二内部信号；
    所述积分单元的第二输入端在所述翻转标识信号为低电平时接收所述第二内部信号，在所述翻转标识信号为高电平时接收所述第一内部信号。
  4. 根据权利要求3所述的校准电路，其中，所述逻辑单元包括：
    计数器，用于调节所述第一内部信号的占空比和/或第二内部信号的占空比；
    第一寄存器组，当所述翻转标识信号为低电平时，根据所述比较器的输出存储所述计数器的第一值；
    第二寄存器组，当所述翻转标识信号为高电平时，根据所述比较器的输出存储所述计数器的第二值。
  5. 根据权利要求4所述的校准电路，其中，所述逻辑单元还包括：
    运算组件，连接所述第一寄存器组和所述第二寄存器组，用于对所述第一寄存器组和所述第二寄存器组的输出做加减乘除运算；
    第三寄存器组，连接所述运算组件，用于存储所述运算组件的输出结果。
  6. 根据权利要求5所述的校准电路，其中，所述比较单元由一采样时钟驱动，所述采样时钟的频率低于所述第一内部信号的频率和/或第二内部信号的频率。
  7. 根据权利要求6所述的校准电路，其中，所述计数器由一计算器时钟驱动，所述计算器时钟频率低于所述第一内部信号的频率和/或第二内部信号的频率。
  8. 根据权利要求7所述的校准电路，其中，所述采样时钟的频率和所述计算器时钟的频率相同。
  9. 根据权利要求8所述的校准电路，还包括：
    分频器，接收一外部时钟信号，产生所述采样时钟和所述计算器时钟。
  10. 根据权利要求9所述的校准电路，还包括：
    第五寄存器组，与所述分频器连接，用于配置所述采样时钟的频率和所述计算器时钟的频率。
  11. 根据权利要求1所述的校准电路，其中，所述差分输入电路还用于接收第一外部信号和第二外部信号，所述第一外部信号的频率与所述第二外部信号的频率相同且相位相反。
  12. 根据权利要求11所述的校准电路，还包括：
    选择器，所述第一振荡信号、所述第二振荡信号、所述第一外部信号、所述第二外部信号均通过所述选择器连接至所述差分输入电路，记所述第一振荡信号和第二振荡信号为第一差分对信号，记所述第一外部信号和第二外部信号为第二差分对信号，所述选择器用于选择所述第一差分对信号和第二差分对信 号之一输入所述差分输入电路。
  13. 根据权利要求12所述的校准电路，其中，选择器的控制端接收一校准使能信号，当所述校准使能信号为低电平时，所述第一外部信号和第二外部信号输入所述差分输入电路，当所述校准使能信号为高电平时，所述第一振荡信号和第二振荡信号输入所述差分输入电路。
  14. 一种存储器，包括：
    如权利要求1至13任一所述的校准电路。
  15. 一种校准方法，包括：
    差分输入电路接收第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反，所述第一振荡信号和第二振荡信号的占空比在第一预设范围内，所述差分输入电路输出第一内部信号和第二内部信号；
    比较单元接收所述第一内部信号和第二内部信号，并对所述第一内部信号的占空比或第二内部信号的占空比进行比较；
    逻辑单元根据所述比较单元的输出结果对所述差分输入电路进行控制，使得所述第一内部信号的占空比和/或第二内部信号的占空比到达第二预设范围内。
  16. 根据权利要求15所述的校准方法，其中，所述比较单元接收所述第一内部信号和第二内部信号包括：
    当输入翻转标识信号为低电平时，所述比较单元对第一内部信号的占空比进行比较；
    当输入翻转标识信号为高电平时，所述比较单元对第二内部信号的占空比进行比较。
  17. 根据权利要求16所述的校准方法，其中，所述逻辑单元根据所述比较单元的输出结果对所述差分输入电路进行控制包括：
    所述逻辑单元包括计数器、第一寄存器组、第二寄存器组；
    当翻转标识信号为低电平时，计数器从U计数至V，当计数器为U时对应 所述第一内部信号的占空比为X％，当计数器为V时对应所述第一内部信号的占空比为Y％，当所述比较单元的输出结果由低电平变为高电平时，将此时所述计数器对应的计数器值存入所述第一寄存器组；
    当所述翻转标识信号为高电平时，计数器从U计数至V，当计数器为U时对应所述第二内部信号的占空比为Y％，当计数器为V时对应所述第二振荡信号的占空比为X％，当所述比较单元的输出结果由高电平变为低电平时，将此时所述计数器对应的计数器值存入所述第二寄存器组；
    其中，所述U和V均为整数，所述U小于V，所述X和Y均为正整数，所述X小于50，所述Y大于50。
  18. 根据权利要求17所述的校准方法，其中，所述逻辑单元根据所述比较单元的输出结果对所述差分输入电路进行控制还包括：
    所述逻辑单元还包括运算组件、第三寄存器组；
    所述运算组件将所述第一寄存器组和所述第二寄存器组的输出做加减乘除运算，并将得到的数值H存入所述第三寄存器组；
    其中，所述H为整数，所述H大于等于所述U且小于等于所述V。
  19. 根据权利要求18所述的校准方法，其中，所述H对应所述第一内部信号的占空比在所述第二预设范围内。
PCT/CN2021/105250 2020-10-28 2021-07-08 校准电路、存储器以及校准方法 WO2022088749A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020227029212A KR20220131979A (ko) 2020-10-28 2021-07-08 교정 회로, 메모리 및 교정 방법
EP21870482.3A EP4033662B1 (en) 2020-10-28 2021-07-08 Calibration circuit, memory, and calibration method
JP2022552390A JP7467655B2 (ja) 2020-10-28 2021-07-08 較正回路、メモリ及び較正方法
US17/448,051 US11935621B2 (en) 2020-10-28 2021-09-19 Calibration circuit, memory and calibration method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011173755.3A CN114420187B (zh) 2020-10-28 2020-10-28 校准电路、存储器以及校准方法
CN202011173755.3 2020-10-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/448,051 Continuation US11935621B2 (en) 2020-10-28 2021-09-19 Calibration circuit, memory and calibration method

Publications (1)

Publication Number Publication Date
WO2022088749A1 true WO2022088749A1 (zh) 2022-05-05

Family

ID=81260481

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/105250 WO2022088749A1 (zh) 2020-10-28 2021-07-08 校准电路、存储器以及校准方法

Country Status (2)

Country Link
CN (1) CN114420187B (zh)
WO (1) WO2022088749A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116994639A (zh) * 2022-04-26 2023-11-03 长鑫存储技术有限公司 测试电路、测试方法及存储器
US11703905B1 (en) 2022-04-26 2023-07-18 Changxin Memory Technologies, Inc. Clock generation circuit, equidistant four-phase signal generation method, and memory
CN115273953A (zh) * 2022-07-27 2022-11-01 长鑫存储技术有限公司 阻抗校准电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1542861A (zh) * 2003-03-28 2004-11-03 ���ǵ�����ʽ���� 具有改善的忙闲度校正的集成电路器件及其操作方法
CN104270122A (zh) * 2014-09-16 2015-01-07 中国科学院微电子研究所 一种占空比校正电路
CN104716929A (zh) * 2013-12-12 2015-06-17 爱思开海力士有限公司 占空比校正电路
US10249354B1 (en) * 2018-02-23 2019-04-02 Micron Technology, Inc. Apparatuses and methods for duty cycle distortion correction of clocks

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100808591B1 (ko) * 2006-06-30 2008-02-29 주식회사 하이닉스반도체 클럭 트리 회로 및 그를 이용한 듀티 보정 테스트 방법과그를 포함하는 반도체 메모리 장치
US7786782B2 (en) * 2008-09-29 2010-08-31 Xilinx, Inc. Method and apparatus for counter-based clock signal adaptation
KR101605459B1 (ko) * 2009-02-02 2016-03-23 삼성전자 주식회사 지연 고정 루프 회로 및 그를 채용한 반도체 메모리 장치
JP5547217B2 (ja) * 2012-01-25 2014-07-09 株式会社東芝 増幅回路
CN103095295B (zh) * 2012-12-28 2015-09-23 重庆西南集成电路设计有限责任公司 锁相频率合成器及自适应频率校准电路和校准方法
KR20150142852A (ko) * 2014-06-12 2015-12-23 에스케이하이닉스 주식회사 다중 위상 클럭을 생성하는 반도체 시스템 및 이의 트레이닝 방법
CN104753499B (zh) * 2015-04-17 2017-05-24 上海华虹宏力半导体制造有限公司 占空比校准电路
KR20170046389A (ko) * 2015-10-21 2017-05-02 삼성전자주식회사 듀티 사이클 정정 회로, 이를 포함하는 반도체 장치 및 듀티 사이클 정정 회로의 동작방법
CN108134602B (zh) * 2017-12-21 2021-08-24 长鑫存储技术有限公司 占空比校准电路及半导体存储器
CN111161773A (zh) * 2018-11-08 2020-05-15 长鑫存储技术有限公司 低频时钟占空比校准电路、校准方法和存储器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1542861A (zh) * 2003-03-28 2004-11-03 ���ǵ�����ʽ���� 具有改善的忙闲度校正的集成电路器件及其操作方法
CN104716929A (zh) * 2013-12-12 2015-06-17 爱思开海力士有限公司 占空比校正电路
CN104270122A (zh) * 2014-09-16 2015-01-07 中国科学院微电子研究所 一种占空比校正电路
US10249354B1 (en) * 2018-02-23 2019-04-02 Micron Technology, Inc. Apparatuses and methods for duty cycle distortion correction of clocks

Also Published As

Publication number Publication date
CN114420187A (zh) 2022-04-29
CN114420187B (zh) 2023-09-08

Similar Documents

Publication Publication Date Title
WO2022088749A1 (zh) 校准电路、存储器以及校准方法
US11935621B2 (en) Calibration circuit, memory and calibration method
US7636001B2 (en) Digital DLL circuit
KR101010649B1 (ko) 디지털 ｄｌｌ 회로
US7863955B2 (en) Semiconductor device and operation method thereof
US20120051493A1 (en) Continous high-frequency event filter
US10840896B2 (en) Digital measurement circuit and memory system using the same
US10411719B1 (en) Direct measurement delay calibration method and apparatus
WO2022088757A1 (zh) 存储器
WO2022088748A1 (zh) 时钟产生电路、存储器以及时钟占空比校准方法
RU2800031C1 (ru) Схема калибровки, запоминающее устройство и способ калибровки
EP4044187B1 (en) Memory
US20080278246A1 (en) Memory controller
US11881858B2 (en) Clock generation circuit, memory and method for calibrating clock duty cycle
KR102666336B1 (ko) 클록 생성 회로, 메모리 및 클록 듀티 사이클 교정 방법
WO2024098852A1 (zh) 校准电路
US20120002779A1 (en) State detection circuit and semiconductor memory device
CN117331867A (zh) 一种控制电路及数据读写方法、数字处理器

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2021870482

Country of ref document: EP

Effective date: 20220329

ENP Entry into the national phase

Ref document number: 20227029212

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2022552390

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE