WO2022088748A1 - 时钟产生电路、存储器以及时钟占空比校准方法 - Google Patents

时钟产生电路、存储器以及时钟占空比校准方法 Download PDF

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Publication number
WO2022088748A1
WO2022088748A1 PCT/CN2021/105207 CN2021105207W WO2022088748A1 WO 2022088748 A1 WO2022088748 A1 WO 2022088748A1 CN 2021105207 W CN2021105207 W CN 2021105207W WO 2022088748 A1 WO2022088748 A1 WO 2022088748A1
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Prior art keywords
duty cycle
oscillating signal
signal
clock
oscillation
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PCT/CN2021/105207
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English (en)
French (fr)
Inventor
田凯
汪玉霞
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21856922.6A priority Critical patent/EP4044434B1/en
Priority to JP2022540538A priority patent/JP7387902B2/ja
Priority to KR1020227022248A priority patent/KR102666336B1/ko
Priority to US17/502,111 priority patent/US11881858B2/en
Publication of WO2022088748A1 publication Critical patent/WO2022088748A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/06—Modifications of generator to ensure starting of oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

  • the embodiments of the present application relate to, but are not limited to, a clock generation circuit, a memory, and a clock duty cycle calibration method.
  • Semiconductor memory is used in many electronic systems to store retrievable data. As the demand for electronic systems to be faster, have greater data capacity and consume less power continues to grow, to meet changing demands, semiconductor memory may need to be faster, store more data and use less power .
  • the semiconductor memory is controlled by providing commands, memory addresses and clocks to the memory, and various commands, memory addresses and clocks can be provided by a memory controller. These three types of signals can control the memory to perform various storage operations, such as read operations to read data from the memory, and write operations to store data into the memory. Data is transferred between the memory and the memory controller based on known timings associated with "related commands" received by the memory. Specifically, a system clock (system clock) for timing commands and addresses can be provided to the memory, and further, a data clock (data clock) can also be provided to the memory, and the data clock is used as a timing sequence for reading data and Timing of writing data. In addition, the memory can also provide a clock to the controller for timing the transfer of data to the controller.
  • system clock system clock
  • data clock data clock
  • the memory can also provide a clock to the controller for timing the transfer of data to the controller.
  • the external clock provided to the memory is used to generate internal clocks that control the timing of various internal circuits during the memory operation of the memory. Timing of internal circuits is critical during memory operation, and erroneous operation may be caused by skew in the internal clock, including duty cycle distortion, where the duty cycle of the clock signal deviates from the preset duty cycle.
  • the memory needs to have the DCA function and the DCM function, that is, the memory includes a duty cycle adjustment (DCA, Duty Cycle Adjust) circuit and a duty cycle monitor (DCM, Duty Cycle Monitor) circuit.
  • the duty cycle adjustment circuit can be used to adjust the external The duty cycle of the internal clock generated by the clock, and the duty cycle monitoring circuit can be used to monitor whether the duty cycle of the clock deviates from the preset duty cycle.
  • the memory needs to be tested before the memory leaves the factory.
  • the performance of the testing machine has a great influence on the test results and affects the accuracy of the test results.
  • the current mainstream test machines can usually only work at lower frequencies (such as around 200MHz), far from the maximum operating frequency of high-speed memory.
  • High-speed memory includes DRAM, such as LPDDR4 or LPDDR5 or LPDDR6, so use the test It is difficult for the computer to judge and screen the characteristics of the high-speed input port of the DRAM, and the high-speed input port includes the data port/system clock port/data clock port (DQ/CK/WCK).
  • DQ/CK/WCK data port/system clock port/data clock port
  • some high-speed testing machines can only set the frequency of the input signal, and it is difficult to ensure that the duty cycle is accurately and stabilized within the preset duty cycle, which will cause test deviations and affect the accuracy of the test results.
  • An embodiment of the present application provides a clock generation circuit, including: an oscillation circuit for generating a first oscillation signal and a second oscillation signal, wherein the first oscillation signal and the second oscillation signal have the same frequency and opposite phase; compare a unit for receiving the first oscillating signal and the second oscillating signal, for comparing the duty cycle of the first oscillating signal and/or the duty cycle of the second oscillating signal; a logic unit, connected to The comparison unit and the oscillation circuit are configured to control the oscillation circuit according to the output result of the comparison unit, so that the duty ratio reaches a preset range.
  • Embodiments of the present application further provide a memory including the above clock generation circuit.
  • An embodiment of the present application further provides a method for calibrating a clock duty cycle, including: an oscillation circuit generating a first oscillation signal and a second oscillation signal, wherein the first oscillation signal and the second oscillation signal have the same frequency and opposite phases,
  • the first oscillating signal has an initial duty cycle;
  • the comparison unit receives the first oscillating signal and the second oscillating signal, and compares the duty ratio of the first oscillating signal or the second oscillating signal to the duty cycle.
  • the duty cycle is compared; the logic unit controls the oscillator circuit according to the output result of the comparison unit, so that the duty cycle of the first oscillator signal generated by the oscillator circuit changes from the initial duty cycle to Preset duty cycle.
  • FIG. 1 is a functional block diagram of a clock generation circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a clock generation circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a circuit structure of the oscillator in the oscillator circuit in FIG. 1;
  • FIG. 4 is a schematic diagram of a storage system
  • FIG. 5 is a schematic flowchart of a method for calibrating a clock duty cycle provided by an embodiment of the present application.
  • FIG. 1 is a functional block diagram of a clock generation circuit provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a clock generation circuit provided by an embodiment of the application.
  • the clock generation circuit includes: an oscillation circuit 101 for generating a first oscillation signal OSC+ and a second oscillation signal OSC-, and the first oscillation signal OSC+ and the second oscillation signal OSC- The frequency is the same and the phase is opposite; the comparison unit 102 receives the first oscillating signal OSC+ and the second oscillating signal OSC-, and is used to perform the duty cycle of the first oscillating signal OSC+ and/or the duty cycle of the second oscillating signal OSC- Comparison; the logic unit 103 is connected to the comparison unit 102 and the oscillation circuit 101, and is used for controlling the oscillation circuit 101 according to the output result of the comparison unit 102, so that the duty cycle reaches a preset range.
  • the clock generation circuit is built in the memory and can be used as a key component of the built-in self-test system (BIST, (Built-In Self Test) of the memory, using the oscillator circuit to generate a differential high-speed oscillator signal, that is, the high-frequency first oscillator signal and the second oscillating signal, the characteristics of the high-speed input circuit can be tested, thus solving the problem of poor accuracy of the test results caused by the low frequency of the input signal provided by the testing machine, and greatly reducing the impact on the automatic testing machine (ATE, Automatic Test Equipment), thereby reducing the test cost.
  • the clock generation circuit can also realize the duty cycle calibration function of the memory and the duty cycle monitoring function.
  • the first oscillating signal OSC+ and the second oscillating signal OSC- are differential clock signals.
  • the first oscillating signal OSC+ and the second oscillating signal OSC- have high-frequency characteristics, that is, the frequency of the first oscillating signal OSC+ and the frequency of the second oscillating signal OSC- are read and written to the memory.
  • the frequencies of the required clock signals are equivalent, and the equivalent here can either mean the same frequency or the frequency difference is within the allowable range of the test.
  • the frequencies of the first oscillating signal OSC+ and the second oscillating signal OSC- may reach 3.2 GHz or 4.8 GHz or even 6.4 GHz.
  • the oscillating circuit 101 includes an oscillator 111 for generating a first initial oscillating signal osc+ and a second initial oscillating signal osc-, and the first initial oscillating signal osc+ and the second initial oscillating signal osc- have the same frequency and opposite phases , that is, the first initial oscillation signal osc+ and the second initial oscillation signal osc- are differential signals.
  • FIG. 3 is a schematic diagram of a circuit structure of the oscillator 111 provided in this embodiment. More specifically, as shown in FIG. 3 , the oscillator 111 includes a first ring topology structure and a second ring topology structure that are electrically connected to each other, and the first ring topology structure is connected end to end by a plurality of first inverters 11 to form a first The transmission speed propagates the oscillating signal, and the second ring topology is connected end-to-end by a plurality of second inverters 12 to propagate the oscillating signal at the second transmission speed, and the second propagation speed is lower than the first propagation speed.
  • the number of the first inverters 11 is an integer greater than or equal to 4, and the number of the second inverters 12 is an integer greater than or equal to 2. Furthermore, the second propagation speed may be greater than or equal to 0.5 times the first propagation speed.
  • the oscillator 111 may further include: a third ring topology structure, connected end to end by a plurality of third inverters 13, to propagate the oscillation signal at a third propagation speed, and the first ring topology structure is electrically connected to the third ring topology structure, and the first ring topology structure is electrically connected to the third ring topology structure.
  • the third propagation speed is less than the first propagation speed.
  • the number of the third inverters 13 is an integer greater than or equal to 2, and the third propagation speed may be the same as the second propagation speed.
  • the setting of the second ring topology can make the oscillating signal in the It flips more times per unit time, thereby obtaining the high-speed first initial oscillation signal osc+ and the second initial oscillation signal osc-, and then obtaining the high-speed first oscillating signal OSC+ and the second oscillating signal OSC-.
  • the oscillation circuit 101 may further include: a path simulation circuit 121, which is interposed between the oscillator 111 and the comparison unit 102, one end is connected to the output end of the oscillator 111, and the other end is connected to the input end of the comparison unit 102, for The circuit characteristics of the first path are simulated, and the first initial oscillating signal osc+ is received to generate the first oscillating signal OSC+, and the second initial oscillating signal osc- is received to generate the second oscillating signal OSC-.
  • a path simulation circuit 121 which is interposed between the oscillator 111 and the comparison unit 102, one end is connected to the output end of the oscillator 111, and the other end is connected to the input end of the comparison unit 102, for The circuit characteristics of the first path are simulated, and the first initial oscillating signal osc+ is received to generate the first oscillating signal OSC+, and the second initial oscillating signal osc- is received to generate the second oscill
  • the circuit characteristics include one or any combination of device resistance, device capacitance, parasitic resistance, parasitic capacitance, input and output impedance, driving capability, and noise environment of the first path.
  • the first path refers to a signal path in which the clock signal is transmitted to the output end of the high-speed differential input circuit of the memory via a controller.
  • the first path will be described below with reference to FIG. 3 :
  • FIG. 4 is a schematic diagram of a storage system.
  • the storage system includes a controller 10 and a plurality of memories 20 .
  • Each of the memories 20 and the controller 10 is coupled to a command/address bus 21 , a data bus 22 and a clock bus 23 .
  • the memory 20 may be LPDDR4, LPDDR5 or LPDDR6.
  • the memory 20 receives the command/address signal provided by the controller 10 through the command/address bus 21, and indicates the command/address signal with CMD/ADD;
  • the data signals are transmitted between the memories 20, and the data signals are marked with DQ;
  • a variety of clock signals are transmitted between the controller 10 and the memory 20 through the clock bus 23, and the clock signals can include system clock signals, read and write data clock signals, with CK_t and CK_c indicates the differential system clock signal, and WCK_t and WCK_c indicate the differential read and write data clock signals.
  • the controller 10 is coupled to a high-speed differential input circuit of the memory 20, and the high-speed differential input circuit is used to receive an external clock signal and generate an internal clock signal, and the internal clock signal can be used as a differential input signal for completing data read and write operations . More specifically, the high-speed differential input circuit receives CK_t, CK_c, WCK_t and WCK_c to generate an internal clock signal.
  • the high-speed differential input circuit may include an input buffer (IB, Input Buffer).
  • the command/address bus 21 , the data bus 22 and the clock bus 23 all have resistance and may also generate parasitic resistance or parasitic capacitance.
  • the high-speed differential input circuit 24 itself also has circuit characteristics such as resistance or capacitance, and a path is set in the oscillator circuit 101 The simulation circuit 121 can simulate these circuit characteristics.
  • the path simulation circuit 121 can not only amplify and output the first initial oscillation signal osc+ and the second initial oscillation signal osc-, but also simulate the controller 10 to high-speed
  • the circuit characteristics of the output end of the differential input circuit 24 make the first oscillating signal OSC+ and the second oscillating signal OSC- more suitable for the high-speed clock signals of the actual application scenario of the memory, thereby making the test results more accurate and effective.
  • the path analog circuit 121 may include an analog buffer 1 and an analog on-chip termination resistor (ODT, On Die Termination) 2 .
  • ODT On Die Termination
  • the level of the input signal is usually a fixed value and cannot be changed at will, which is different from the actual application of the memory, so test deviations will be introduced. affect the accuracy of the test results.
  • the first oscillating signal OSC+ and the second oscillating signal OSC- are used as input signals, and the level of the first oscillating signal OSC+ and the level of the second oscillating signal OSC- can be adjusted through the path simulation circuit 112, so that the test The results are more accurate.
  • the oscillator circuit may also only include an oscillator, that is, the oscillator directly generates the first oscillator signal OSC+ and the second oscillator signal OSC-.
  • the oscillation circuit 101 may further include: a fourth register group 131, which is connected to the oscillator 111 and used to configure the frequencies of the first oscillation signal OSC+ and the second oscillation signal OSC-.
  • the fourth register group 131 configures the frequency of the first oscillation signal OSC+ by configuring the frequency of the first initial oscillation signal osc+, and configures the frequency of the second oscillation signal OSC- by configuring the frequency of the second initial oscillation signal osc-.
  • the fourth register group 131 can be a mode register (MR, Model Register), the mode register can also be integrated in the mode register required by the memory to realize the read-write operation function, and the mode register can also be a mode register with the memory independent functional modules.
  • MR Mode Register
  • Model Register the mode register can also be integrated in the mode register required by the memory to realize the read-write operation function
  • the mode register can also be a mode register with the memory independent functional modules.
  • the oscillation circuit 101 may further include: a sixth register group 141 connected to the path simulation circuit 121 for configuring electrical parameters of the path simulation circuit 121 . Specifically, the electrical parameters of the path simulation circuit 121 are adjusted through the sixth register group 141 to adjust the circuit characteristics of the first path simulated by the path simulation circuit 121 .
  • the sixth register group 141 can be a mode register, which can also be integrated into a mode register required by the memory to realize the read-write operation function, and the mode register can also be a functional module independent of the mode register of the memory.
  • the output state of the selected path simulation circuit 121 is set through the sixth register group 141.
  • PDDS 40ohm
  • ODT 40ohm
  • VOH is the output drive voltage
  • PDDS (Pull Down Drive Strength) is the input pull-down drive strength
  • ODT (on-die termination) is the on-die termination resistor.
  • the comparison unit 102 compares the duty cycle of the first oscillating signal OSC+ and/or the duty cycle of the second oscillating signal OSC-, including at least one of the following three situations:
  • the comparison unit 102 compares the duty ratio of the first oscillation signal OSC+. Specifically, the comparison unit 102 compares whether the duty cycle of the first oscillation signal OSC+ is within a preset range, for example, the preset range may be 48% ⁇ 52%. If the comparison unit 102 compares the duty cycle of the first oscillation signal OSC+ within the preset range, it means that the duty cycle of the second oscillation signal OSC- is also within the preset range; if the comparison unit 102 compares the duty cycle of the first oscillation signal OSC+ If the duty cycle is not within the preset range, it means that the duty cycle of the second oscillation signal OSC- is also not within the preset range.
  • the comparison unit 102 compares the duty ratio of the second oscillation signal OSC-. Specifically, the comparison unit 102 compares whether the duty cycle of the second oscillation signal OSC- reaches a preset range, and the preset range may be 48% ⁇ 52%. If the comparing unit 102 compares the duty cycle of the second oscillating signal OSC- within the preset range, it means that the duty cycle of the first oscillating signal OSC+ is also within the preset range; if the comparing unit 102 compares the second oscillating signal OSC- The duty cycle of the first oscillating signal OSC+ is also not within the preset range.
  • the comparing unit 102 compares the duty ratio of the first oscillating signal OSC+ with the duty ratio of the second oscillating signal OSC-. Specifically, the comparison unit 102 obtains whether the difference between the duty cycle of the first oscillating signal OSC+ and the duty cycle of the second oscillating signal OSC- is within a preset difference range, and the preset difference range may be -4% ⁇ 4%; if the comparison unit 102 compares the difference within the preset difference range, it means that the duty cycle of the first oscillation signal OSC+ and the second oscillation signal OSC- is within the preset range, otherwise, the first oscillation signal The duty ratios of OSC+ and the second oscillating signal OSC- do not reach the preset range.
  • the comparing unit 102 includes: an integrating unit 112, which has a first input terminal 3 and a second input terminal 4, and the first input terminal 3 receives one of the first oscillation signal OSC+ or the second oscillation signal OSC- , the second input terminal 4 receives the other of the first oscillating signal OSC+ or the second oscillating signal OSC-; the comparator 122 is connected to the output terminal of the integrating unit 112 .
  • the integrating unit 112 includes two integrating circuits, and the first input terminal 3 is used as the input terminal of one integrating circuit, and the second input terminal 4 is used as the input terminal of another integrating circuit.
  • the comparator 122 is used to compare the outputs of the two integrating circuits and output a high level or a low level.
  • the comparison unit 102 performs an integration operation on the input first oscillation signal OSC+ and the second oscillation signal OSC ⁇ by two integration circuits, and the result of the integration operation is input into the comparator 122 , and the comparator 122 outputs the comparison result. .
  • the output of the comparator 122 is at a high level, indicating that the first oscillating signal The duty cycle of OSC+ is greater than that of the second oscillating signal OSC-; the output of the comparator 122 is low, indicating that the duty cycle of the first oscillating signal OSC+ is smaller than that of the second oscillating signal OSC-.
  • the above-mentioned correspondence between the output result of the comparison unit 102 and the duty cycle of the first oscillation signal OSC+ and the duty cycle of the second oscillation signal OSC- is only an example, and this embodiment does not limit the high
  • the corresponding relationship between the ratio and the duty cycle of the second oscillation signal OSC- is sufficient.
  • the output result of the comparison unit 102 may be sampled and output by the sampling clock clk1 .
  • the comparison unit 102 is driven by a sampling clock clk1, and the frequency of the sampling clock clk1 is lower than the frequency of the first oscillating signal OSC+ and/or the frequency of the second oscillating signal OSC-.
  • the clock generating circuit further includes: a frequency divider 104, which receives an external clock signal CLK and generates a sampling clock clk1.
  • the external clock signal CLK can be either provided by the tester or the main clock signal of the memory.
  • the clock generation circuit may further include: a fifth register group 105, Connected to the frequency divider 104 for configuring the frequency of the sampling clock.
  • the fifth register group 105 may be a mode register.
  • the fifth register group 105 please refer to the foregoing descriptions about the fourth register group 131 and the sixth register group 141 .
  • the comparison unit 102 can also be configured as the first input terminal and the second input terminal. The two inputs are interchangeable. Specifically, the comparison unit 102 is configured to:
  • the first input terminal of the integration unit 112 receives the first oscillation signal OSC+ when the inversion identification signal is at a low level, and receives the second oscillation signal OSC- when the inversion identification signal is at a high level; the second input terminal of the integration unit 112 is in the inversion
  • the second oscillation signal OSC- is received when the identification signal is at a low level
  • the first oscillation signal OSC+ is received when the inverted identification signal is at a high level.
  • the memory has a mode register, and the inversion identification signal can be provided by the mode register.
  • DCM MR OP[1] 0 means that the inversion identification signal is Low level
  • DCM MR OP[1] 1 indicates that the inversion identification signal is high level
  • the logic unit 103 includes: a counter 113 for adjusting the duty cycle of the first oscillating signal OSC+ and/or the second oscillating signal OSC-;
  • the output stores the first value of the counter 113 ;
  • the second register group 133 stores the second value of the counter 113 according to the output of the comparator 122 when the inversion identification signal is at a high level.
  • the role of the counter 113 includes: adjusting the duty cycle of the first oscillation signal OSC+ and the duty cycle of the second oscillation signal OSC- output by the oscillation circuit 101 , and the duty cycle of the first oscillation signal OSC+ and the second oscillation
  • the variation of the duty cycle of the signal OSC- is a monotonic variation, eg, the duty cycle changes from a minimum to a maximum or from a maximum to a minimum within one count period.
  • the output result of the comparator 122 will have only one inversion point, and the value of the counter 113 corresponding to the inversion point is the first oscillation signal OSC+ and the second oscillation signal OSC- output by the oscillation circuit 101 .
  • the duty cycle of is closest to the preset range, and this value is stored in the first register group 123 or the second register group 133 as the value of the counter.
  • the first value of the counter 113 is stored according to the output of the comparator 122, and the first value is stored in the first register group 123; when the rollover identification signal is at a high level, according to the comparison
  • the output of the counter 122 stores the second value of the counter 113 which is stored in the second register set 133 .
  • the working principle of the logic unit 103 will be described in detail below:
  • the first input terminal of the integration unit 112 receives the first oscillation signal OSC+, and the second input terminal receives the second oscillation signal OSC-; the counter 113 starts counting, for example, starts from 0 in one count period Count and count to 31, and at the same time, the duty ratios of the first oscillating signal OSC+ and the second oscillating signal OSC- output by the oscillating circuit 101 also change from the minimum to the maximum (for example, from 40% to 60%) or from the maximum to the minimum ; In this way, in one count period (eg from 0 to 31), the comparator 122 will have and only one reversal point, the value of the counter 113 corresponding to the reversal point is the first value, and the first value is the oscillation
  • the duty cycle of the oscillation signal output by the controller 111 via the path simulation circuit 121 is set closest to the preset range, for example, the duty cycle may be set closest to 50%, and the first value is stored in the first register group
  • the first input terminal of the integrating unit 112 receives the second oscillating signal OSC-, and the second input terminal receives the first oscillating signal OSC+, that is, the input terminals of the comparing unit 102 are interchanged, and the counter 113 enters a new For example, the counting period starts from 0 and reaches 31. Similarly, the second value of the counter 113 corresponding to the output inversion point of the comparator 122 is stored in the second register group 133 .
  • the counter 113 may be a subtraction counter in addition to an addition counter, which may be sequentially incremented.
  • the counting can be counted down, and it can also be counted up or down in a stepwise manner, so as to ensure that the counter 113 changes monotonically within a single counting period.
  • the first input terminal and the second input terminal of the comparison unit 102 are interchanged, and the oscillating circuit 101 is controlled by counting twice, which can eliminate the adverse effects caused by the input deviation of the comparison unit 102 itself, and further improve the accuracy of the test results. .
  • the logic unit 103 may further include: an arithmetic component 143, connected to the first register group 123 and the second register group 133, for performing addition, subtraction, multiplication and division operations on the outputs of the first register group 123 and the second register group 133; the third The register group 153 is connected to the operation component 143 and is used for storing the output result of the operation component 143 .
  • the output of the first register group 123 refers to the first value stored in the first register group 123
  • the output of the second register group 133 refers to the second value stored in the second register group 133
  • the arithmetic component 143 adds and divides the first value and the second value by 2 to obtain an average value, and the average value is used as the output result of the arithmetic component 143 , and the average value is stored in the third register group 153 .
  • the average value is the setting where the duty ratios of the first oscillation signal OSC+ and the second oscillation signal OSC- output by the oscillation circuit 101 are closest to the preset range, For example, the duty ratios of the first oscillating signal OSC+ and the second oscillating signal OSC- are closest to 50%.
  • the average value can be either the first value and the second value are added and divided by 2 and rounded up, or the first value and the second value can be added and divided by 2 and rounded down. the integer.
  • the average of the first value and the second value is used as an example, and in other embodiments, other operation methods may also be used to perform operation on the first value and the second value.
  • the first register group 123, the second register group 133 and the third register group 153 may all be mode registers.
  • the counter 113 is driven by a calculator clock, and the frequency of the calculator clock is lower than the frequency of the first oscillating signal OSC+ and/or the frequency of the second oscillating signal OSC-.
  • the frequency of the calculator clock is adjustable, and the frequency of the calculator clock is reasonably selected according to the speed of adjusting the oscillator circuit 101 .
  • the frequency of the sampling clock can be the same as the frequency of the calculator clock.
  • the frequency divider can also be used to receive an external clock signal to generate the sampling clock and the calculator clock; similarly, the fifth register group can also be used to configure the frequency of the calculator clock.
  • the value stored in the third register group 153 corresponds to the setting of the oscillator circuit 101.
  • the duty cycle selection of the oscillator circuit 101 is switched from the counter 113 to the third register group 153, so that the fixed output of the oscillator circuit 101 has an optimal duty cycle
  • the ratio of the first oscillating signal OSC+ and the second oscillating signal OSC- can be understood that, during the period when the oscillator circuit 101 outputs the first oscillating signal OSC+ and the second oscillating signal OSC- at the optimal duty ratio, the comparison unit 102 can continue to control the duty ratio and/or the second oscillating signal OSC+ of the first oscillating signal OSC+.
  • the duty ratio of the two oscillation signals OSC- is compared. If the duty ratio of the first oscillation signal OSC+ and the duty cycle of the second oscillation signal OSC- deviate from the preset range, the problem can be detected in time.
  • the clock generation circuit provided in this embodiment, through the oscillation circuit 101 , the comparison unit 102 and the logic unit 103 , can generate the first oscillation signal and the second oscillation signal with high speed and adjustable duty cycle inside the memory, and the first oscillation signal It is a differential signal with the second oscillating signal, the first oscillating signal and the second oscillating signal meet the requirements of the high-frequency working signal of the memory, so they can be used as the test input signal of the test memory, so that the memory can realize the built-in self-test function without using additional
  • the test machine provides test input signals, and at the same time solves the problem that the test machine is difficult to provide high-frequency test input signals.
  • the comparison unit 102 detects the output of the oscillation circuit 101, and the logic unit 103 controls the oscillation circuit 101 based on the output result of the comparison unit 102, so as to ensure that the first oscillation signal and the second oscillation signal occupy the
  • the duty ratio can be stabilized within a preset range, thereby avoiding the adverse effect of the duty ratio deviation on the test accuracy, and improving the test accuracy of the memory test using the first oscillation signal and the second oscillation signal.
  • the duty cycle of the first oscillating signal and the duty cycle of the second oscillating signal can be precisely controlled at 50%.
  • the path simulation circuit 121 can not only amplify and output the high-speed oscillation signal, but also simulate the signal characteristics from the controller to the output end of the high-speed differential input circuit, so that the first oscillation signal and the second oscillating signal are more in line with the actual application of the memory, thereby further improving the test accuracy of using the first oscillating signal and the second oscillating signal for testing.
  • the clock generation circuit provided in this embodiment also has a duty cycle monitoring function and a duty cycle calibration function.
  • an embodiment of the present application further provides a memory including the clock generating circuit provided by the foregoing embodiments.
  • the memory may be memory such as DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, and NOR.
  • the memory has a built-in self-test function, so it can generate high-speed first and second oscillation signals that can be used for testing inside the memory, and the duty cycle of the first and second oscillation signals can be maintained at Within the preset range, there is no need to use an additional testing machine to provide a test signal, which is beneficial to improve the test accuracy of the memory test.
  • FIG. 5 is a schematic flowchart of a method for calibrating a clock duty cycle provided by an embodiment of the present application.
  • the clock duty cycle calibration method in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, the clock duty cycle calibration method can be performed by using the clock generation circuit provided in the foregoing embodiment.
  • the method for calibrating the clock duty cycle includes the following steps:
  • Step S1 the oscillator circuit generates a first oscillator signal and a second oscillator signal, the first oscillator signal and the second oscillator signal have the same frequency and opposite phases, and the first oscillator signal has an initial duty cycle.
  • the initial duty cycle may be within a preset range, for example, the initial duty cycle is 48% to 52%; the initial duty cycle may also not reach the preset range, for example, the initial duty cycle is 45%.
  • the sum of the duty ratio of the first oscillating signal OSC+ and the duty ratio of the second oscillating signal OSC- is 100%.
  • Step S2 the comparison unit receives the first oscillation signal and the second oscillation signal, and compares the duty cycle of the first oscillation signal or the duty cycle of the second oscillation signal.
  • the comparison unit compares the duty cycle of the first oscillation signal OSC+, for example, the comparison unit can determine whether the duty cycle of the first oscillation signal OSC+ is equal to a preset duty cycle , if it is less than the preset duty cycle, the comparison unit outputs a low level, if it is greater than or equal to the preset duty cycle, the comparison unit outputs a high level; when the flip identification signal is a high level, the comparison unit compares the second oscillation signal OSC- For example, the comparison unit can determine whether the duty cycle of the second oscillation signal OSC- is equal to the preset duty cycle, if it is less than the preset duty cycle, the comparison unit outputs a low level, if it is greater than or equal to the preset duty cycle Set the duty cycle, the comparison unit outputs a high level.
  • the preset duty cycle may be, for example, 50%, and the output of the comparison unit is not limited to a high level and a low level and the duty cycle of the first oscillating signal OSC+ and the duty cycle of the second oscillating signal OSC- As long as it is ensured that different output results correspond to different corresponding relationships between the duty ratios of the first oscillating signal OSC+ and the duty ratios of the second oscillating signal OSC-.
  • the output result of the comparison unit can also represent the difference between the duty cycle of the first oscillating signal OSC+ and the duty cycle of the second oscillating signal OSC-.
  • the output result of the comparison unit is a high level, which indicates that the duty cycle of the first oscillation signal OSC+ is greater than that of the second oscillation signal OSC-; the output result of the comparison unit is a low level, which indicates that the first oscillation signal OSC+
  • the duty cycle of is smaller than that of the second oscillation signal OSC-.
  • the sum of the duty cycle of the first oscillating signal OSC+ and the duty cycle of the second oscillating signal OSC- is 100%. For example, when the duty cycle of the first oscillating signal OSC+ changes from 49% to 51%, the comparison unit’s The output result changes from low to high.
  • the comparing unit includes: an integrating unit, which has a first input terminal and a second input terminal, the first input terminal receives one of the first oscillating signal OSC+ or the second oscillating signal OSC-, and the second input terminal receives the second oscillating signal OSC- or the other of the first oscillation signal OSC+; a comparator, connected to the output terminal of the integrating unit.
  • the first input terminal receives the first oscillation signal OSC+ and the second input terminal receives the second oscillation signal OSC-, the comparator compares the duty cycle of the first oscillation signal OSC+ and has a corresponding Output; the comparator compares the duty cycle of the first oscillating signal OSC+, which may be: comparing the duty cycle of the first oscillating signal OSC+ with that of the second oscillating signal OSC-, or comparing the first oscillating signal OSC+ and the preset duty cycle.
  • the first input terminal receives the second oscillating signal OSC- and the second input terminal receives the first oscillating signal OSC+, and the comparator compares the duty cycle of the second oscillating signal OSC- and has a corresponding The comparator compares the duty cycle of the second oscillating signal OSC-, which may be: comparing the duty cycle of the second oscillating signal OSC- with the duty cycle of the first oscillating signal OSC+, or comparing the second oscillating signal OSC+
  • the duty cycle of the signal OSC- is the same as the preset duty cycle.
  • Step S3 the logic unit controls the oscillation circuit according to the output result of the comparison unit, so that the duty cycle of the first oscillation signal generated by the oscillation circuit changes from the initial duty cycle to the preset duty cycle.
  • the logic unit includes a counter, a first register group, and a second register group.
  • the oscillating circuit is controlled by the counter to adjust the duty ratio of the first oscillating signal OSC+ and the duty ratio of the second oscillating signal OSC-.
  • the counter When the rollover identification signal is low, the counter counts from M to N.
  • the duty cycle corresponding to the first oscillating signal OSC+ is P%
  • the counter when the counter is N, it corresponds to the duty cycle of the first oscillating signal OSC+.
  • Q% when the output result of the comparison unit changes from a low level to a high level, the counter value corresponding to the counter at this time is stored in the first register group.
  • M can be 0, N can be 31, P can be 45, Q can be 55, the initial duty cycle can be 45%, or other values.
  • the counter When the rollover identification signal is at a high level, the counter counts from M to N.
  • the counter When the counter is M, the duty cycle corresponding to the second oscillating signal OSC- is Q%, and when the counter is N, the corresponding duty cycle of the second oscillating signal OSC- is Q%.
  • the empty ratio is P%.
  • the counter value corresponding to the counter at this time is stored in the second register group. For example, M can be 0, N can be 31, P can be 45, Q can be 55, the initial duty cycle can be 45%, or other values.
  • M and N are both integers, M is less than N, P and Q are both positive integers, P is less than 50, and Q is greater than 50.
  • the initial duty cycle may be, for example, any value between 1% and 99%, the preset duty cycle may be, for example, any value between 48% and 52%, and even the preset duty cycle may be equal to 50%.
  • the first input terminal receives the first oscillating signal OSC+ and the second input terminal receives the second oscillating signal OSC-
  • the counter counts from 0 to 31 in one count cycle
  • the comparison unit When the output result of the comparison unit is a low level, it indicates that the duty cycle of the first oscillation signal OSC+ is smaller than that of the second oscillation signal OSC-; when the output result of the comparison unit is a high level, it indicates that the duty cycle of the first oscillation signal OSC+ greater than the duty cycle of the second oscillation signal OSC-. Therefore, the output result of the comparison unit jumps from a low level to a high level corresponding to an inversion point, and the counter value of the counter corresponding to the inversion point is stored in the first register group as the first value.
  • the first input terminal receives the second oscillation signal OSC- and the second input terminal receives the first oscillation signal OSC+, the counter counts from 0 to 31 in one count cycle, and the output result of the comparison unit is
  • it is at a high level, it means that the duty cycle of the first oscillating signal OSC+ is smaller than that of the second oscillating signal OSC-; when the output result of the comparison unit is a low level, it means that the duty cycle of the first oscillating signal OSC+ is greater than that of the second oscillating signal.
  • Duty cycle of signal OSC- Therefore, the output result of the comparison unit jumps from a high level to a low level corresponding to an inversion point, and the counter value of the counter corresponding to the inversion point is stored in the second register group as the second value.
  • the counter when the rollover identification signal is at a low level, the counter counts from 0 to 31, and the duty cycle of the first oscillation signal OSC+ changes monotonically. Increasing by 1 increases the duty cycle of the first oscillation signal OSC+ by ((55-45)/32)%. Similarly, when the flip identification signal is at a high level, the counter counts from 0 to 31, and the duty cycle of the second oscillating signal changes monotonically. The duty cycle of the second oscillation signal is increased by ((55-45)/32)%.
  • the logic unit also includes an operation component and a third register group; the operation component performs addition, subtraction, multiplication and division operations on the outputs of the first register group and the second register group, and stores the obtained value L in the third register group; wherein, L is a positive Integer, L is greater than or equal to M and less than or equal to N.
  • the value L is the addition of the first value and the second value divided by 2, that is, the value L is the average of the first value and the second value, and the value L is the first oscillation signal OSC+ output by the corresponding oscillation circuit and the second oscillating signal OSC- reaches the preset range of settings. That is to say, the duty ratio of the value L corresponding to the first oscillation signal OSC+ is a preset duty ratio, and the preset duty ratio may be 48% ⁇ 52%, for example, 50%.
  • the oscillator circuit is no longer controlled by the counter, but the value L is used as the setting of the oscillator circuit, so that the oscillator circuit outputs the first oscillator signal OSC+ with a preset duty cycle, and the corresponding second oscillator signal OSC -Also an oscillation signal with a duty cycle that meets the requirements.
  • the technical solution of the clock duty cycle calibration method provided by this embodiment can obtain high-speed and high-quality first oscillating signal OSC+ and second oscillating signal OSC-, the duty cycle of the first oscillating signal OSC+ and the second oscillating signal OSC -
  • the duty cycle can be stabilized at the preset duty cycle.
  • the clock generation circuit includes: an oscillation circuit for generating a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal have the same frequency and opposite phase; a comparison unit, receiving the first oscillating signal and the second oscillating signal, for comparing the duty cycle of the first oscillating signal and/or the duty cycle of the second oscillating signal; a logic unit, connected to the The comparison unit and the oscillation circuit are used to control the oscillation circuit according to the output result of the comparison unit, so that the duty ratio reaches a preset range.
  • the embodiments of the present application can generate a first oscillation signal and a second oscillation signal with a stable duty cycle that can be used for memory testing.
  • the memory with this clock generation circuit not only has a built-in self-test function, but also can be used to realize the DCA function and DCM functionality.

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Abstract

提供一种时钟产生电路、存储器以及时钟占空比校准方法，时钟产生电路包括：振荡电路(101)，用于产生第一振荡信号(OSC+)和第二振荡信号(OSC-)，第一振荡信号(OSC+)与第二振荡信号(OSC-)的频率相同且相位相反；比较单元(102)，接收第一振荡信号(OSC+)和第二振荡信号(OSC-)，用于对第一振荡信号(OSC+)的占空比和/或第二振荡信号(OSC-)的占空比进行比较；逻辑单元(103)，连接比较单元(102)和振荡电路(101)，用于根据比较单元(102)的输出结果对振荡电路(101)进行控制，使得占空比到达一预设范围内。

Description

时钟产生电路、存储器以及时钟占空比校准方法
相关申请的交叉引用
本申请要求在2020年10月28日提交中国专利局、申请号为202011176592.4、申请名称为“时钟产生电路、存储器以及时钟占空比校准方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及但不限于一种时钟产生电路、存储器以及时钟占空比校准方法。
背景技术
半导体存储器被用于许多电子系统中，以存储可取回的数据。随着对电子系统更快、具有更大数据容量和消耗更少电力的需求不断增长，为了满足不断变化的需求，半导体存储器可能需要更快的速度，存储更多的数据并使用更少的电力。
通常的，通过向存储器提供命令(commands)、存储地址(memory address)以及时钟(clocks)来控制半导体存储器，且各种命令、存储地址以及时钟可以由存储控制器(memory controller)提供。这三类信号可以控制存储器执行各种存储操作，例如从存储器中读取数据的读取操作，以及将数据存储到存储器的写入操作。基于与存储器接收到的“相关命令”相关的已知时序，在存储器与存储控制器之间传输数据。具体地，可以向存储器提供用于对命令和地址进行计时的系统时钟(system clock)，进一步地，还可以向存储器提供数据时钟(data clock)，该数据时钟用于作为读取数据的时序以及写入数据的时序。此外，存储器还可以向控制器提供时钟，以作为向控制器传输数据的时序。提供给存储器的外部时钟用于产生内部时钟，这些内部时钟在存储器的存储操作期间控制各种内部电路的时序。在存储器操作期间内部电路的时序很关键，并且内部时 钟的偏差可能会导致错误的操作，时钟的偏差包括占空比失真，即时钟信号的占空比偏离预设占空比。
因此，存储器需具备DCA功能以及DCM功能，即存储器包括占空比调节(DCA，Duty Cycle Adjust)电路以及占空比监测(DCM，Duty Cycle Monitor)电路，占空比调节电路可以用于调节外部时钟生成的内部时钟的占空比，占空比监测电路可用于监测时钟的占空比是否偏离预设占空比。
此外，在存储器出厂前需要对存储器进行测试，然而测试机的性能对测试结果影响较大，影响测试结果的准确性。分析发现，目前采用测试机向存储器提供输入信号，该输入信号为存储器完成读写操作所需的工作信号。然而，目前主流的测试机通常仅能工作于较低的频率(如200MHz左右)，远远达不到高速存储器的最高工作频率，高速存储器包括DRAM，例如为LPDDR4或者LPDDR5或者LPDDR6，因此利用测试机难以对DRAM的高速输入端口的特性进行良好的判断及筛选，高速输入端口包括数据端口/系统时钟端口/数据时钟端口(DQ/CK/WCK)。另外，一些高速测试机仅能对输入信号的频率进行设置，难以确保占空比精确稳定在预设占空比内，由此会产生测试偏差，影响测试结果的准确性。
发明内容
本申请实施例提供一种时钟产生电路，包括：振荡电路，用于产生第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反；比较单元，接收所述第一振荡信号和所述第二振荡信号，用于对所述第一振荡信号的占空比和/或所述第二振荡信号的占空比进行比较；逻辑单元，连接所述比较单元和所述振荡电路，用于根据所述比较单元的输出结果对所述振荡电路进行控制，使得所述占空比到达一预设范围内。
本申请实施例还提供一种存储器，包括上述的时钟产生电路。
本申请实施例还提供一种时钟占空比校准方法，包括：振荡电路产生第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同 且相位相反，所述第一振荡信号具有一初始占空比；比较单元接收所述第一振荡信号和所述第二振荡信号，并对所述第一振荡信号的占空比或所述第二振荡信号的占空比进行比较；逻辑单元根据所述比较单元的输出结果对所述振荡电路进行控制，使得所述振荡电路产生的所述第一振荡信号的占空比由所述初始占空比变为预设占空比。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请一实施例提供的时钟产生电路的功能框图；
图2为本申请一实施例提供的时钟产生电路的结构示意图；
图3为图1中振荡电路中的振荡器的一种电路结构示意图；
图4为一种存储系统示意图；
图5为本申请一实施例提供的时钟占空比校准方法的流程示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请一实施例提供的时钟产生电路的功能框图，图2为本申请一实施例提供的时钟产生电路的结构示意图。
参考图1及图2，本实施例中，时钟产生电路包括：振荡电路101，用于产生第一振荡信号OSC+和第二振荡信号OSC-，第一振荡信号OSC+和第二振荡信号OSC-的频率相同且相位相反；比较单元102，接收第一振荡信号OSC+和 第二振荡信号OSC-，用于对第一振荡信号OSC+的占空比和/或第二振荡信号OSC-的占空比进行比较；逻辑单元103，连接比较单元102和振荡电路101，用于根据比较单元102的输出结果对振荡电路101进行控制，使得占空比达到一预设范围内。
该时钟产生电路内置于存储器内，可作为存储器的内置自测系统(BIST，(Built-In Self Test)的关键组成部分，利用振荡电路产生差分的高速振荡信号，即高频的第一振荡信号和第二振荡信号，可测试到高速输入电路的特性，从而解决了测试机提供的输入信号的频率过低导致的测试结果准确性差的问题，且极大的降低了对自动测试机(ATE，Automatic Test Equipment)的依赖性，从而降低测试成本。此外，时钟产生电路还可以实现存储器的占空比校准功能以及占空比监测功能。
以下将结合附图对本实施例提供的时钟产生电路进行详细说明。
第一振荡信号OSC+和第二振荡信号OSC-为差分的时钟信号。此外，本实施例中，第一振荡信号OSC+和第二振荡信号OSC-具有高频特性，也就是说，第一振荡信号OSC+的频率与第二振荡信号OSC-的频率与存储器进行读写操作所需的时钟信号的频率相当，此处的相当既可以为频率相同，也可以指频率差异在测试允许范围内。例如，第一振荡信号OSC+和第二振荡信号OSC-的频率可以达到3.2GHz或4.8GHz甚至6.4GHz。
具体地，振荡电路101包括振荡器111，用于产生第一初始振荡信号osc+和第二初始振荡信号osc-，且第一初始振荡信号osc+与第二初始振荡信号osc-的频率相同且相位相反，即第一初始振荡信号osc+与第二初始振荡信号osc-为差分信号。
图3为本实施例提供的振荡器111的一种电路结构示意图。更具体地，如图3所示，振荡器111包括相互电连接的第一环形拓扑结构和第二环形拓扑结构，第一环形拓扑结构由多个第一反相器11首尾相连，以第一传输速度传播振荡信号，第二环形拓扑结构由多个第二反相器12首尾相连，以第二传输速度传播振荡信号，且第二传播速度小于第一传播速度。
其中，第一反相器11的数量为大于或等于4的整数，第二反相器12的数量为大于或等于2的整数。此外，第二传播速度可以大于或等于0.5倍的第一传播速度。
振荡器111还可以包括：第三环拓扑结构，由多个第三反相器13首尾相连，以第三传播速度传播振荡信号，且第一环形拓扑结构与第三环形拓扑结构电连接，第三传播速度小于第一传播速度。具体地，第三反相器13的数量为大于或等于2的整数，且第三传播速度可以与第二传播速度相同。
相对于仅通过第一环形拓扑结构传播振荡信号，由于第二环形拓扑结构具有的第二传输速度小于第一环形拓扑结构具有的第一传输速度，第二环形拓扑结构的设置可使得振荡信号在单位时间内翻转更多次，从而获取高速的第一初始振荡信号osc+与第二初始振荡信号osc-，进而获取高速的第一振荡信号OSC+和第二振荡信号OSC-。
本实施例中，振荡电路101还可以包括：路径模拟电路121，介于振荡器111与比较单元102之间，一端连接振荡器111的输出端，另一端连接比较单元102的输入端，用于模拟第一路径的电路特性，且接收第一初始振荡信号osc+以产生第一振荡信号OSC+，接收第二初始振荡信号osc-以产生第二振荡信号OSC-。
电路特性包括：第一路径的器件电阻、器件电容、寄生电阻、寄生电容、输入输出阻抗、驱动能力以及噪声环境中的一者或任意组合。具体地，第一路径指的是，时钟信号经由控制器(controller)传输至存储器的高速差分输入电路的输出端的信号路径。为便于理解和说明，以下将结合图3对第一路径进行说明：
图4为一种存储系统示意图。参考图4，存储系统包括控制器10以及多个存储器20，各存储器20和控制器10均耦接命令/地址总线21、数据总线22以及时钟总线23。例如，存储器20可以是LPDDR4或LPDDR5或者LPDDR6，存储器20通过命令/地址总线21接收控制器10提供的命令/地址信号，以CMD/ADD标示命令/地址信号；通过数据总线22在控制器10与存储器20之 间传输数据信号，以DQ标示数据信号；通过时钟总线23在控制器10与存储器20之间传输多种时钟信号，时钟信号可以包括系统时钟信号、读写数据时钟信号，以CK_t和CK_c标示差分的系统时钟信号，以WCK_t和WCK_c标示差分的读写数据时钟信号。
具体地，控制器10与存储器20的高速差分输入电路耦接，高速差分输入电路用于接收外部时钟信号并产生内部时钟信号，该内部时钟信号可用于作为完成数据的读写操作的差分输入信号。更具体地，高速差分输入电路接收CK_t、CK_c、WCK_t和WCK_c产生内部时钟信号。高速差分输入电路可以包括输入缓冲器(IB，Input Buffer)。
命令/地址总线21、数据总线22以及时钟总线23均具有电阻且还可能产生寄生电阻或者寄生电容，此外，高速差分输入电路24本身也具有电阻或电容等电路特性，在振荡电路101中设置路径模拟电路121，可模拟这些电路特性。本实施例中，通过在振荡电路中设置路径模拟电路121，该路径模拟电路121不仅能够将第一初始振荡信号osc+和第二初始振荡信号osc-放大输出，且还能够模拟控制器10到高速差分输入电路24的输出端的电路特性，使得第一振荡信号OSC+以及第二振荡信号OSC-更加符合存储器的真实应用情景的高速时钟信号，从而使得测试结果更加准确有效。
如图2所示，路径模拟电路121可包括模拟缓冲器1以及模拟片上终结电阻(ODT，On Die Termination)2。
一般地，采用高速测试机提供输入信号时，为了能保证输入信号的稳定性，输入信号的电平通常为固定值且不能随意改变，这与存储器的实际应用情况不同，因此会引入测试偏差，影响测试结果的准确性。而本实施例中，第一振荡信号OSC+和第二振荡信号OSC-作为输入信号，可以通过路径模拟电路112调整第一振荡信号OSC+的电平和第二振荡信号OSC-的电平，从而使得测试结果更加准确。
需要说明的是，在其他实施例中，振荡电路也可以仅包括振荡器，即振荡器直接产生第一振荡信号OSC+以及第二振荡信号OSC-。
本实施例中，振荡电路101还可以包括：第四寄存器组131，与振荡器111连接，用于配置第一振荡信号OSC+和第二振荡信号OSC-的频率。具体地，第四寄存器组131通过配置第一初始振荡信号osc+的频率以配置第一振荡信号OSC+的频率，通过配置第二初始振荡信号osc-的频率以配置第二振荡信号OSC-的频率。
其中，第四寄存器组131可以为模式寄存器(MR，Model Register)，该模式寄存器还可以集成于存储器为实现读写操作功能所需的模式寄存器中，该模式寄存器也可以为与存储器的模式寄存器相互独立的功能模块。
振荡电路101还可以包括：第六寄存器组141，与路径模拟电路121连接，用于配置路径模拟电路121的电性参数。具体地，通过第六寄存器组141调整路径模拟电路121的电性参数，以调整路径模拟电路121模拟的第一路径的电路特性。
其中，第六寄存器组141可以为模式寄存器，该模式寄存器还可以集成于存储器为实现读写操作功能所需的模式寄存器中，该模式寄存器也可以为与存储器的模式寄存器相互独立的功能模块。
举例来说，通过第六寄存器组141设置选择路径模拟电路121的输出状态，以LPDDR4为例，设置VOH＝(1/3)*VDDQ或者VOH＝(1/2.5)*VDDQ，PDDS＝40ohm，ODT＝40ohm，其中，VOH为输出驱动电压，PDDS(Pull Down Drive Strength)为输入下拉驱动强度，ODT(on-die termination)为片上终结电阻。
由于第一振荡信号OSC+与第二振荡信号OSC-为差分信号，因此第一振荡信号OSC+的占空比与第二振荡信号OSC-的占空比之和为100％，通过设置比较单元102检测差分的第一振荡信号OSC+和第二振荡信号OSC-的占空比大小。具体地，比较单元102对第一振荡信号OSC+的占空比和/或第二振荡信号OSC-的占空比进行比较，包括以下三种情况中的至少一种：
比较单元102对第一振荡信号OSC+的占空比进行比较。具体地，比较单元102比较第一振荡信号OSC+的占空比是否到达预设范围内，例如，该预设 范围可以为48％～52％。若比较单元102比较第一振荡信号OSC+的占空比在预设范围内，则说明第二振荡信号OSC-的占空比也在预设范围内；若比较单元102比较第一振荡信号OSC+的占空比不在预设范围内，则说明第二振荡信号OSC-的占空比也不在预设范围内。
比较单元102对第二振荡信号OSC-的占空比进行比较。具体地，比较单元102比较第二振荡信号OSC-的占空比是否到达预设范围内，该预设范围可以为48％～52％。若比较单元102比较第二振荡信号OSC-的占空比在预设范围内，则说明第一振荡信号OSC+的占空比也在预设范围内；若比较单元102比较第二振荡信号OSC-的占空比不在预设范围内，则说明第一振荡信号OSC+的占空比也不在预设范围内。
比较单元102对第一振荡信号OSC+的占空比与第二振荡信号OSC-的占空比进行比较。具体地，比较单元102获取第一振荡信号OSC+的占空比与第二振荡信号OSC-的占空比的差值是否在预设差值范围内，该预设差值范围可以为-4％～4％；若比较单元102比较该差值在预设差值范围内，则说明第一振荡信号OSC+和第二振荡信号OSC-的占空比在预设范围内，否则，第一振荡信号OSC+和第二振荡信号OSC-的占空比未到达预设范围。
需要说明的是，上述的预设范围以及预设差值范围的数值范围均为示例性说明，本实施例并不对预设范围以及预设差值范围做限定，可根据存储器的实际性能需求合理设置预设范围以及预设差值范围。
本实施例中，比较单元102包括：积分单元112，其具有第一输入端3和第二输入端4，第一输入端3接收第一振荡信号OSC+或者第二振荡信号OSC-中的一者，第二输入端4接收第一振荡信号OSC+或第二振荡信号OSC-中的另一者；比较器122，连接积分单元112的输出端。
具体地，积分单元112包括两个积分电路，且第一输入端3作为一积分电路的输入端，第二输入端4作为另一积分电路的输入端。比较器122用于比较两个积分电路的输出并输出高电平或者低电平。
更具体地，比较单元102由两个积分电路对输入的第一振荡信号OSC+和 第二振荡信号OSC-进行积分运算，且积分运算的结果输入至比较器122中，且比较器122输出比较结果。
以第一振荡信号OSC+为正端(duty+)且第二振荡信号OSC-为负端(duty-)为例，在一个例子中，比较器122的输出为高电平，则表明第一振荡信号OSC+的占空比大于第二振荡信号OSC-的占空比；比较器122的输出为低电平，则表明第一振荡信号OSC+的占空比小于第二振荡信号OSC-的占空比。
需要说明的是，上述关于比较单元102的输出结果与第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比之间的对应关系仅为示例，本实施例并不限定高电平以及低电平与第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比之间的对应关系，只要保证不同的输出结果对应不同的第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比之间的对应关系即可。
如图2所示，比较单元102的输出结果可以经采样时钟clk1采样输出。本实施例中，比较单元102由一采样时钟clk1驱动，采样时钟clk1的频率低于第一振荡信号OSC+的频率和/或第二振荡信号OSC-的频率。采样时钟clk1的频率越快，则采样误差越大；采样时钟clk1的频率越慢，则采样误差越小，但测试时间越长。因此，可根据采样误差以及测试时间综合选择采样时钟clk1的最优频率。
本实施例中，时钟产生电路还包括：分频器104，接收一外部时钟信号CLK，产生采样时钟clk1。该外部时钟信号CLK既可以是测试机提供的，也可以是存储器的主时钟信号。
此外，由前述分析可知，若采样时钟clk1的频率可调，则可根据实际情况选择不同的采样时钟clk1频率，为此，本实施例中，时钟产生电路还可以包括：第五寄存器组105，与分频器104连接，用于配置采样时钟的频率。第五寄存器组105可以为模式寄存器，有关第五寄存器组105的详细说明，可参考前述关于第四寄存器组131以及第六寄存器组141的描述。
由于比较单元102的固有特性可能会带来输入偏差，为了消除比较单元102自由的输入偏差对测试结果带来的误差，本实施例中，比较单元102还可以被 配置为第一输入端和第二输入端可互换。具体地，比较单元102被配置为：
积分单元112的第一输入端在一翻转标识信号为低电平时接收第一振荡信号OSC+，在翻转标识信号为高电平时接收第二振荡信号OSC-；积分单元112的第二输入端在翻转标识信号为低电平时接收第二振荡信号OSC-，在翻转标识信号为高电平时接收第一振荡信号OSC+。其中，存储器中具有模式寄存器，该翻转标识信号可以由模式寄存器提供，例如，在LPDDR4或LPDDR5或者LPDDR6中，可以为DCM MR OP[1]，DCM MR OP[1]＝0表示翻转标识信号为低电平，DCM MR OP[1]＝1表示翻转标识信号为高电平。
逻辑单元103包括：计数器113，用于调节第一振荡信号OSC+和/或第二振荡信号OSC-的占空比；第一寄存器组123，当翻转标识信号为低电平时，根据比较器122的输出存储计数器113的第一值；第二寄存器组133，当翻转标识信号为高电平时，根据比较器122的输出存储计数器113的第二值。
具体地，计数器113的作用包括：调节振荡电路101输出的第一振荡信号OSC+的占空比以及第二振荡信号OSC-的占空比，且第一振荡信号OSC+的占空比以及第二振荡信号OSC-的占空比的变化为单调性变化，例如在一个计数周期内占空比从最小变到最大或者从最大变到最小。在一个计数周期内，比较器122的输出结果将有且仅有一个反转点，该反转点对应的计数器113的值是振荡电路101输出的第一振荡信号OSC+和第二振荡信号OSC-的占空比最接近预设范围的设置，将这个值作为计数器的值存入第一寄存器组123或者第二寄存器组133。
更具体地，当翻转标识信号为低电平时，根据比较器122的输出存储计数器113的第一值，该第一值存入第一寄存器组123；当翻转标识信号为高电平时，根据比较器122的输出存储计数器113的第二值，该第二值存入第二寄存器组133。为便于理解，以下将对逻辑单元103的工作原理进行详细说明：
当翻转标识信号为低电平时，积分单元112的第一输入端接收第一振荡信号OSC+，第二输入端接收第二振荡信号OSC-；计数器113开始计数，例如在一个计数周期内从0开始计数且计到31，同时振荡电路101输出的第一振荡信 号OSC+和第二振荡信号OSC-的占空比也从最小变到最大(例如从40％变到60％)或者从最大变到最小；这样，在一个计数周期(例如从0到31)内，比较器122将有且仅有一个反转点，该反转点对应的计数器113的值为第一值，该第一值是振荡器111经由路径模拟电路121输出的振荡信号的占空比最接近预设范围的设置，例如可以是占空比最接近50％的设置，该第一值存入第一寄存器组123中。
当翻转标识信号为高电平时，积分单元112的第一输入端接收第二振荡信号OSC-，第二输入端接收第一振荡信号OSC+，即比较单元102的输入端互换，计数器113进入新的计数周期，例如从0开始计数且计到31，同样的，将比较器122的输出反转点对应的计数器113的第二值存入第二寄存器组133中。
需要说明的是，上述从0到31的计数周期仅为示例说明，本实施例中并不对计数器113的计数方式进行限定，计数器113除为加法计数器外也可以为减法计数器，既可以为依次递增或者递减式计数，也可以为步进式递增或者递减计数，保证计数器113在单个计数周期内单调性变化即可。
比较单元102的第一输入端与第二输入端互换，通过两次计数控制振荡电路101的方式，可以消除比较单元102自身的输入偏差带来的不良影响，进一步的提高测试结果的准确性。
此外，逻辑单元103还可以包括：运算组件143，连接第一寄存器组123和第二寄存器组133，用于对第一寄存器组123和第二寄存器组133的输出做加减乘除运算；第三寄存器组153，连接运算组件143，用于存储运算组件143的输出结果。
具体地，第一寄存器组123的输出指的是存入第一寄存器组123的第一值，第二寄存器组133的输出指的是存入第二寄存器组133的第二值。本实施例中，运算组件143对第一值和第二值进行相加除以2，得到平均值，且该平均值作为运算组件143的输出结果，该平均值被存入第三寄存器组153。由于该平均值已经消除掉比较单元102自有的输入偏差，因此该平均值为振荡电路101输出的第一振荡信号OSC+和第二振荡信号OSC-的占空比最接近预设范围的设 置，例如第一振荡信号OSC+和第二振荡信号OSC-的占空比最接近50％。
可以理解的是，该平均值既可以是第一值和第二值进行相加除以2向上取整的整数，也可以是第一值和第二值进行相加除以2向下取整的整数。
需要说明的是，本实施例中以对第一值和第二值取平均作为示例，在其他实施例中，也可以采用其他的运算方式对第一值和第二值进行运算。
第一寄存器组123、第二寄存器组133以及第三寄存器组153均可以为模式寄存器。
本实施例中，计数器113由一计算器时钟驱动，计算器时钟的频率低于第一振荡信号OSC+的频率和/或第二振荡信号OSC-的频率。计算器时钟的频率可调，根据调整振荡电路101的速度合理选择计算器时钟的频率。
此外，采样时钟的频率可以与计算器时钟的频率相同。分频器还可以用于接收一外部时钟信号，产生采样时钟和计算器时钟；同样的，第五寄存器组还可以用于配置计算器时钟的频率。
存入第三寄存器组153的值对应为振荡电路101的设置，此时，振荡电路101的占空比选择由计数器113切换为第三寄存器组153，使得振荡电路101固定输出具有最优占空比的第一振荡信号OSC+和第二振荡信号OSC-。可以理解的是，在振荡电路101固定以最优占空比输出第一振荡信号OSC+和第二振荡信号OSC-期间，比较单元102可以持续对第一振荡信号OSC+的占空比和/或第二振荡信号OSC-的占空比进行比较，若第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比偏离预设范围，能够及时检测出这一问题。
本实施例提供的时钟产生电路，通过振荡电路101、比较单元102以及逻辑单元103，能够在存储器内部产生高速且占空比可调的第一振荡信号和第二振荡信号，且第一振荡信号与第二振荡信号为差分信号，该第一振荡信号和第二振荡信号满足存储器高频工作信号的需求，因此能够作为测试存储器的测试输入信号，使得存储器能够实现内置自测功能，无需利用额外的测试机提供测试输入信号，同时解决了测试机难以提供高频的测试输入信号的问题。
此外，本实施例中，比较单元102对振荡电路101的输出进行检测，且逻 辑单元103基于比较单元102的输出结果对振荡电路101进行控制，从而保证第一振荡信号和第二振荡信号的占空比能够稳定在预设范围内，从而避免了占空比偏差对测试准确度带来的不良影响，提高利用第一振荡信号和第二振荡信号对存储器进行测试的测试准确度。例如，第一振荡信号的占空比和第二振荡信号的占空比可精确控制在50％。
另外，由于振荡电路101还包括路径模拟电路121，该路径模拟电路121不仅能够将高速振荡信号放大输出，且还可以模拟从控制器到高速差分输入电路的输出端的信号特性，使得第一振荡信号和第二振荡信号更加符合存储器的实际应用情况，从而进一步的提高利用第一振荡信号和第二振荡信号进行测试的测试准确性。
同时，本实施例提供的时钟产生电路，还具有占空比监测功能以及占空比校准功能。
相应的，本申请实施例还提供一种存储器，包括前述实施例提供的时钟产生电路。具体地，该存储器可以为DRAM、SRAM、MRAM、FeRAM、PCRAM、NAND、NOR等存储器。
由前述分析可知，存储器具有内置自测功能，因而能够在存储器内部产生可用于测试的高速第一振荡信号和第二振荡信号，且第一振荡信号和第二振荡信号的占空比能够维持在预设范围内，因而无需利用额外的测试机提供测试信号，从而有利于提高对存储器进行测试的测试准确度。
相应的，本申请实施例还提供一种时钟占空比校准方法。图5为本申请一实施例提供的时钟占空比校准方法的流程示意图。以下将结合附图对本申请实施例中时钟占空比校准方法进行详细说明。需要说明的是，该时钟占空比校准方法可利用前述实施例提供的时钟产生电路进行。
参考图2和图5，本实施例中，时钟占空比校准方法包括以下步骤：
步骤S1、振荡电路产生第一振荡信号和第二振荡信号，第一振荡信号与第 二振荡信号的频率相同且相位相反，第一振荡信号具有一初始占空比。
具体地，该初始占空比可以在预设范围内，例如初始占空比在48％～52％；该初始占空比也可以未达到预设范围，例如初始占空比为45％。此外，第一振荡信号OSC+的占空比与第二振荡信号OSC-的占空比之和为100％。
步骤S2、比较单元接收第一振荡信号和第二振荡信号，并对第一振荡信号的占空比或第二振荡信号的占空比进行比较。
具体地，当翻转标识信号为低电平时，比较单元对第一振荡信号OSC+的占空比进行比较，例如，比较单元可以判断第一振荡信号OSC+的占空比是否等于一预设占空比，如果小于预设占空比，比较单元输出低电平，如果大于等于预设占空比，比较单元输出高电平；当翻转标识信号为高电平时，比较单元对第二振荡信号OSC-的占空比进行比较，例如，比较单元可以判断第二振荡信号OSC-的占空比是否等于预设占空比，如果小于预设占空比，比较单元输出低电平，如果大于等于预设占空比，比较单元输出高电平。该预设占空比例如可以为50％，该比较单元的输出并不限定高电平以及低电平与第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比之间的对应关系，只要保证不同的输出结果对应不同的第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比之间的对应关系即可。
比较单元的输出结果还可以表征第一振荡信号OSC+的占空比与第二振荡信号OSC-的占空比之间的差值。例如，比较单元的输出结果为高电平，表征第一振荡信号OSC+的占空比大于第二振荡信号OSC-的占空比；比较单元的输出结果为低电平，表征第一振荡信号OSC+的占空比小于第二振荡信号OSC-的占空比。第一振荡信号OSC+的占空比与第二振荡信号OSC-的占空比之和为100％，例如，当第一振荡信号OSC+的占空比由49％变为51％时，比较单元的输出结果由低电平变为高电平。
比较单元包括：积分单元，其具有第一输入端和第二输入端，第一输入端接收第一振荡信号OSC+或第二振荡信号OSC-中的一者，第二输入端接收第二振荡信号OSC-或第一振荡信号OSC+中的另一者；比较器，连接积分单元的输 出端。
当翻转标识信号为低电平时，第一输入端接收第一振荡信号OSC+且第二输入端接收第二振荡信号OSC-，比较器对第一振荡信号OSC+的占空比进行比较且具有相应的输出；比较器对第一振荡信号OSC+的占空比进行比较，可以为：比较第一振荡信号OSC+的占空比与第二振荡信号OSC-的占空比，或者，比较第一振荡信号OSC+的占空比与预设占空比。
当翻转标识信号为高电平时，第一输入端接收第二振荡信号OSC-且第二输入端接收第一振荡信号OSC+，比较器对第二振荡信号OSC-的占空比进行比较且具有相应的输出；比较器对第二振荡信号OSC-的占空比进行比较，可以为：比较第二振荡信号OSC-的占空比与第一振荡信号OSC+的占空比，或者，比较第二振荡信号OSC-的占空比与预设占空比。
步骤S3、逻辑单元根据比较单元的输出结果对振荡电路进行控制，使得振荡电路产生的所述第一振荡信号的占空比由初始占空比变为预设占空比。
具体地，逻辑单元包括计数器、第一寄存器组、第二寄存器组。通过计数器控制振荡电路，以调整第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比。
当翻转标识信号为低电平时，计数器从M计数至N，当计数器为M时对应第一振荡信号OSC+的占空比为P％，当计数器为N时对应第一振荡信号OSC+的占空比为Q％，当比较单元的输出结果由低电平变为高电平时，将此时计数器对应的计数器值存入所述第一寄存器组。例如，M可以为0，N可以为31，P可以为45，Q可以为55，初始占空比可以为45％，也可以为其他值。
当翻转标识信号为高电平时，计数器从M计数至N，当计数器为M时对应第二振荡信号OSC-的占空比为Q％，当计数器为N时对应第二振荡信号OSC-的占空比为P％，当比较单元的输出结果由高电平变为低电平时，将此时计数器对应的计数器值存入第二寄存器组。例如，M可以为0，N可以为31，P可以为45，Q可以为55，初始占空比可以为45％，也可以为其他值。
其中，M和N均为整数，M小于N，P和Q均为正整数，P小于50，Q大 于50。初始占空比例如可以为介于1％至99％的任意值，预设占空比例如可以为48％至52％的任意值，甚至预设占空比可以等于50％。
更具体地，当翻转标识信号为低电平时，第一输入端接收第一振荡信号OSC+且第二输入端接收第二振荡信号OSC-，计数器在一个计数周期内由0计数至31，比较单元的输出结果为低电平时，说明第一振荡信号OSC+的占空比小于第二振荡信号OSC-的占空比；比较单元的输出结果为高电平时，说明第一振荡信号OSC+的占空比大于第二振荡信号OSC-的占空比。因此，比较单元的输出结果由低电平跳转为高电平对应具有一个反转点，该反转点对应的计数器的计数器值作为第一值存入第一寄存器组。
当翻转标识信号为高电平时，第一输入端接收第二振荡信号OSC-且第二输入端接收第一振荡信号OSC+，计数器在一个计数周期内由0计数至31，比较单元的输出结果为高电平时，说明第一振荡信号OSC+的占空比小于第二振荡信号OSC-的占空比；比较单元的输出结果为低电平时，说明第一振荡信号OSC+的占空比大于第二振荡信号OSC-的占空比。因此，比较单元的输出结果由高电平跳转为低电平对应具有一个反转点，该反转点对应的计数器的计数器值作为第二值存入第二寄存器组。
需要说明的是，当翻转标识信号为低电平，计数器从0计数至31，第一振荡信号OSC+的占空比单调性变化，例如可以为预设步进式递增，如计数器的计数器值每增加1则第一振荡信号OSC+的占空比增加((55-45)/32)％。同理，当翻转标识信号为高电平，计数器从0计数至31，第二振荡信号的占空比单调性变化，例如可以为预设步进式递增，如计数器的计数器值每增加1则第二振荡信号的占空比增加((55-45)/32)％。
逻辑单元还包括运算组件、第三寄存器组；运算组件将第一寄存器组和第二寄存器组的输出做加减乘除运算，并将得到的数值L存入第三寄存器组；其中，L为正整数，L大于等于M且小于等于N。
本实施例中，数值L为第一值和第二值相加除以2，即数值L为第一值和第二值取平均，该数值L即为对应振荡电路输出的第一振荡信号OSC+和第二 振荡信号OSC-到达预设范围的设置。也就是说，数值L对应第一振荡信号OSC+的占空比为预设占空比，该预设占空比可以为48％～52％，例如为50％。
在获取数值L后，不再由计数器控制振荡电路，而是将数值L作为振荡电路的设置，以使振荡电路输出具有预设占空比的第一振荡信号OSC+，相应的第二振荡信号OSC-也为占空比符合要求的振荡信号。
本实施例提供的时钟占空比校准方法的技术方案，能够获取高速且高质量的第一振荡信号OSC+和第二振荡信号OSC-，第一振荡信号OSC+的占空比和第二振荡信号OSC-的占空比可稳定在预设占空比。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例中，时钟产生电路包括：振荡电路，用于产生第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反；比较单元，接收所述第一振荡信号和所述第二振荡信号，用于对所述第一振荡信号的占空比和/或所述第二振荡信号的占空比进行比较；逻辑单元，连接所述比较单元和所述振荡电路，用于根据所述比较单元的输出结果对所述振荡电路进行控制，使得所述占空比到达一预设范围内。这样，本申请实施例能够产生可用于存储器测试的占空比稳定的第一振荡信号和第二振荡信号，该第一振荡信号和第二振荡信号可作为测试存储器的输入信号，因此有利于提高存储器的测试准确度；此外，该时钟产生电路还具有占空比校准功能和占空比监测功能，因此，具有该时钟产生电路的存储器不仅具有内置自测功能，且还可以用于实现DCA功能以及DCM功能。

Claims (19)

  1. 一种时钟产生电路，包括：
    振荡电路，用于产生第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反；
    比较单元，接收所述第一振荡信号和所述第二振荡信号，用于对所述第一振荡信号的占空比和/或所述第二振荡信号的占空比进行比较；
    逻辑单元，连接所述比较单元和所述振荡电路，用于根据所述比较单元的输出结果对所述振荡电路进行控制，使得所述占空比到达一预设范围内。
  2. 根据权利要求1所述的时钟产生电路，其中，所述比较单元包括：
    积分单元，其具有第一输入端和第二输入端，所述第一输入端接收所述第一振荡信号或所述第二振荡信号中的一者，所述第二输入端接收所述第二振荡信号或所述第一振荡信号中的另一者；
    比较器，连接所述积分单元的输出端。
  3. 根据权利要求2所述的时钟产生电路，其中，所述积分单元被配置为：
    所述积分单元的第一输入端在一翻转标识信号为低电平时接收所述第一振荡信号，在所述翻转标识信号为高电平时接收所述第二振荡信号；
    所述积分单元的第二输入端在所述翻转标识信号为低电平时接收所述第二振荡信号，在所述翻转标识信号为高电平时接收所述第一振荡信号。
  4. 根据权利要求3所述的时钟产生电路，其中，所述逻辑单元包括：
    计数器，用于调节所述第一振荡信号的占空比和/或第二振荡信号的占空比；
    第一寄存器组，当所述翻转标识信号为低电平时，根据所述比较器的输出存储所述计数器的第一值；
    第二寄存器组，当所述翻转标识信号为高电平时，根据所述比较器的输出存储所述计数器的第二值。
  5. 根据权利要求4所述的时钟产生电路，其中，所述逻辑单元还包括：
    运算组件，连接所述第一寄存器组和所述第二寄存器组，用于对所述第一寄存器组和所述第二寄存器组的输出做加减乘除运算；
    第三寄存器组，连接所述运算组件，用于存储所述运算组件的输出结果。
  6. 根据权利要求5所述的时钟产生电路，其中，所述比较单元由一采样时钟驱动，所述采样时钟的频率低于所述第一振荡信号和/或第二振荡信号的频率。
  7. 根据权利要求6所述的时钟产生电路，其中，所述计数器由一计算器时钟驱动，所述计算器时钟的频率低于所述第一振荡信号的频率和/或第二振荡信号的频率。
  8. 根据权利要求7所述的时钟产生电路，其中，所述采样时钟的频率和所述计算器时钟的频率相同。
  9. 根据权利要求8所述的时钟产生电路，还包括：
    分频器，接收一外部时钟信号，产生所述采样时钟和所述计算器时钟。
  10. 根据权利要求9所述的时钟产生电路，还包括：
    第五寄存器组，与所述分频器连接，用于配置所述采样时钟和所述计算器时钟的频率。
  11. 根据权利要求1所述的时钟产生电路，其中，所述振荡电路包括：
    振荡器，用于产生第一初始振荡信号和第二初始振荡信号，所述第一初始振荡信号与所述第二初始振荡信号的频率相同且相位相反；
    路径模拟电路，介于所述振荡器和所述比较单元之间，一端连接所述振荡器的输出端，另一端连接所述比较单元的输入端，用于模拟第一路径的电路特性，接收所述第一初始振荡信号以产生所述第一振荡信号，接收所述第二初始振荡信号以产生所述第二振荡信号。
  12. 根据权利要求11所述的时钟产生电路，还包括：
    第四寄存器组，与所述振荡器连接，用于配置所述第一振荡信号的频率和第二振荡信号的频率。
  13. 根据权利要求12所述的时钟产生电路，还包括：
    第六寄存器组，与所述路径模拟电路连接，用于配置所述路径模拟电路的电性参数。
  14. 一种存储器，包括：
    如权利要求1至13任一所述的时钟产生电路。
  15. 一种时钟占空比校准方法，包括：
    振荡电路产生第一振荡信号和第二振荡信号，所述第一振荡信号与所述第二振荡信号的频率相同且相位相反，所述第一振荡信号具有一初始占空比；
    比较单元接收所述第一振荡信号和所述第二振荡信号，并对所述第一振荡信号的占空比或所述第二振荡信号的占空比进行比较；
    逻辑单元根据所述比较单元的输出结果对所述振荡电路进行控制，使得所述振荡电路产生的所述第一振荡信号的占空比由所述初始占空比变为预设占空比。
  16. 根据权利要求15所述的时钟占空比校准方法，其中，所述比较单元接收所述第一振荡信号和第二振荡信号包括：
    当翻转标识信号为低电平时，所述比较单元对第一振荡信号的占空比进行比较；
    当所述翻转标识信号为高电平时，所述比较单元对第二振荡信号的占空比进行比较。
  17. 根据权利要求16所述的时钟占空比校准方法，其中，所述逻辑单元根据所述比较单元的输出结果对所述振荡电路进行控制包括：
    所述逻辑单元包括计数器、第一寄存器组、第二寄存器组；
    当所述翻转标识信号为低电平时，所述计数器从M计数至N，当所述计数器为M时对应所述第一振荡信号的占空比为P％，当所述计数器为N时对应所述第一振荡信号的占空比为Q％，当所述比较单元的输出结果由低电平变为高电平时，将此时所述计数器对应的计数器值存入所述第一寄存器组；
    当所述翻转标识信号为高电平时，所述计数器从M计数至N，当所述计数器为M时对应所述第二振荡信号的占空比为Q％，当所述计数器为N时对应所 述第二振荡信号的占空比为P％，当所述比较单元的输出结果由高电平变为低电平时，将此时所述计数器对应的计数器值存入所述第二寄存器组；
    其中，所述M和N均为整数，所述M小于N，所述P和Q均为正整数，所述P小于50，所述Q大于50。
  18. 根据权利要求17所述的时钟占空比校准方法，其中，所述逻辑单元根据所述比较单元的输出结果对所述振荡电路进行控制还包括：
    所述逻辑单元还包括运算组件、第三寄存器组；
    所述运算组件将所述第一寄存器组和所述第二寄存器组的输出做加减乘除运算，并将得到的数值L存入所述第三寄存器组；
    其中，所述L为整数，所述L大于等于所述M且小于等于所述N。
  19. 根据权利要求18所述的时钟占空比校准方法，其中，所述L对应所述第一振荡信号的占空比为所述预设占空比。
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