WO2024098852A1 - 校准电路 - Google Patents

校准电路 Download PDF

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Publication number
WO2024098852A1
WO2024098852A1 PCT/CN2023/111038 CN2023111038W WO2024098852A1 WO 2024098852 A1 WO2024098852 A1 WO 2024098852A1 CN 2023111038 W CN2023111038 W CN 2023111038W WO 2024098852 A1 WO2024098852 A1 WO 2024098852A1
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Prior art keywords
circuit
signal
con
calibration
calibration control
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PCT/CN2023/111038
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English (en)
French (fr)
Inventor
关琢玮
田凯
朱玲
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长鑫存储技术有限公司
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Publication of WO2024098852A1 publication Critical patent/WO2024098852A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular to a calibration circuit.
  • the calibration circuit in the related technology has the problem of a large layout area.
  • An embodiment of the present disclosure provides a calibration circuit, which includes: a calibration control circuit, which is used to generate a clock signal and an automatic calibration control signal, and is used to automatically calibrate the offset of a target circuit according to the automatic calibration control signal, wherein the automatic calibration control signal is generated based on the clock signal; a calibration monitoring circuit, which is coupled to the calibration control circuit, receives the clock signal and the automatic calibration control signal, and is used to monitor the change state of the output signal of the target circuit based on the clock signal, and latches the automatic calibration control signal when the state of the output signal is flipped, and determines the offset calibration value corresponding to the latched automatic calibration control signal as the target offset calibration value of the target circuit.
  • FIG. 1 is a schematic diagram of a calibration circuit in an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a calibration control circuit in an exemplary embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a calibration circuit in another exemplary embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a calibration monitoring subcircuit in an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a calibration monitoring subcircuit in another exemplary embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a calibration monitoring subcircuit in yet another exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a calibration monitoring subcircuit in yet another exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a calibration monitoring subcircuit in yet another exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a signal monitoring circuit in an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a signal sampling circuit in an exemplary embodiment of the present disclosure.
  • FIG. 11 is a timing diagram based on the signal sampling circuit shown in FIG. 10 .
  • FIG. 12 is a schematic diagram of a target circuit in an exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a control-end signal generating circuit of a calibration module in an exemplary embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a calibration circuit in another exemplary embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a control signal generating circuit in an exemplary embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a control signal generating circuit in another exemplary embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of a control signal generating circuit in yet another exemplary embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a calibration circuit in an exemplary embodiment of the present disclosure.
  • the calibration circuit 100 may include a calibration control circuit 110 and a calibration monitoring circuit 120 .
  • the calibration control circuit 110 can be used to generate a clock signal OscClk and an automatic calibration control signal Con, and can be used to automatically calibrate the offset of the target circuit 130 according to the automatic calibration control signal Con output by the calibration control circuit 110.
  • the automatic calibration control signal Con can be generated based on the clock signal OscClk.
  • the target circuit in the embodiment of the present disclosure refers to a circuit that needs to be offset calibrated, for example, a data receiving circuit.
  • the present disclosure is not limited to this.
  • it can also be an ODT (On-Die Termination, a termination resistor on a DRAM (Dynamic Random Access Memory) chip) circuit or any other circuit that requires offset calibration.
  • the target circuit to be calibrated is taken as a data receiving circuit for example.
  • the calibration monitoring circuit 120 can be coupled to the calibration control circuit 110, can receive the clock signal OscClk and the automatic calibration control signal Con, and can be used to monitor the change state of the output signal Din of the target circuit 130 based on the clock signal OscClk, and latch the automatic calibration control signal Con when the state of the output signal Din is flipped, and determine the offset calibration value corresponding to the latched automatic calibration control signal Con (represented as Con’ in Figure 1) as the target offset calibration value of the target circuit 130.
  • the state flipping (toggle) of the output signal Din of the target circuit 130 refers to the output signal Din being converted from a first level state to a second level state, or from a second level state to a first level state.
  • the first level state may be, for example, a high level
  • the second level state may be, for example, a low level, or vice versa, and the present disclosure does not limit this.
  • the calibration circuit provided in the embodiment of the present disclosure realizes automatic calibration of the offset of the target circuit to be calibrated by using the automatic calibration control signal output by the calibration control circuit as the input of the calibration monitoring circuit. There is no need to set a control signal generating circuit in the calibration monitoring circuit to convert and obtain the offset calibration value input to the target circuit, thereby reducing the layout area of the calibration circuit.
  • FIG. 2 is a schematic diagram of a calibration control circuit in an exemplary embodiment of the present disclosure.
  • the calibration control circuit 110 in the embodiment of the present disclosure may further include a clock generating circuit 111 , a counting circuit 112 , and a control signal generating circuit 113 .
  • the clock generating circuit 111 can be used to generate a clock signal OscClk.
  • the clock generating circuit 111 can use any circuit that can realize the function of generating the clock signal OscClk.
  • the clock generating circuit using a crystal oscillator (abbreviated as Osc) is used as an example below, but the present disclosure is not limited to this.
  • the counting circuit 112 may be coupled to the clock generating circuit 111 , may receive the clock signal OscClk, and may be configured to generate a counting signal Cnt according to the clock signal OscClk.
  • the counting signal Cnt may indicate a count value of the clock signal OscClk.
  • the control signal generating circuit 113 may be coupled to the counting circuit 112 , may receive the counting signal Cnt, and may be used to convert the counting signal Cnt into the automatic calibration control signal Con.
  • the calibration circuit provided by the embodiment of the present disclosure generates different automatic calibration control signals Con when the count value of the clock signal OscClk is different, that is, the automatic calibration control signal Con corresponds to the count value OscClk of the clock signal one by one.
  • different control signal generating circuits can be designed to realize different corresponding relationships between the count signal and the automatic calibration control signal to meet the offset calibration requirements of different target circuits.
  • the calibration monitoring circuit may include n calibration monitoring sub-circuits, where n may be a positive integer greater than or equal to 1.
  • Each calibration monitoring sub-circuit may be coupled to the calibration control circuit, and may receive a clock signal and an automatic calibration control signal.
  • the calibration circuit 300 may include a calibration control circuit 110 and a calibration monitoring circuit, wherein the calibration monitoring circuit may further include n calibration monitoring sub-circuits, such as the calibration monitoring sub-circuit 120-1, calibration monitoring sub-circuit 120-2, calibration monitoring sub-circuit 120-3,... and calibration monitoring sub-circuit 120-n shown in Figure 3.
  • the calibration monitoring subcircuit 120-n are respectively coupled to the calibration control circuit 110, and respectively receive the clock signal OscClk and the automatic calibration control signal Con output by the calibration control circuit 110, and can respectively monitor the change state of the output signal of the target circuit corresponding to each calibration monitoring subcircuit based on the received clock signal OscClk, and latch the corresponding automatic calibration control signal when the state of the output signal of the corresponding target circuit is reversed, such as Con-1', Con-2', Con-3', ... or Con-n' shown in Figure 3, and determine the offset calibration value corresponding to the latched corresponding automatic calibration control signal Con-1', Con-2', Con-3', ... or Con-n' as the target offset calibration value of the corresponding target circuit 130-1, 130-2, 130-3, ... 130-n.
  • RocCnt in FIG. 14 below can represent a calibration control circuit
  • DqRoc can represent any calibration monitoring subcircuit in the calibration monitoring circuit.
  • each DqByte on the DCPNA contains eight DqPads, and each DqPad has a DqRoc circuit.
  • the automatic calibration control signal output by the control signal generating circuit in one RocCnt can calibrate the target circuits in four DqPads simultaneously or sequentially, that is, the DqRoc circuits in four DqPads can be controlled simultaneously or sequentially for calibration monitoring simultaneously or sequentially, that is, the automatic calibration control signal output by the control signal generating circuit in one RocCnt can control four DqRoc circuits, and every four DqRoc circuits can share the same control signal generating circuit in RocCnt.
  • n may also be 8.
  • one RocCnt may control the DqRoc circuits in eight DqPads, thereby further reducing the area of the eight DqRoc circuits on the DqPads.
  • the value of n may be appropriately balanced between the saved circuit layout area and the loading of the calibration control circuit.
  • the calibration circuit provided by the embodiment of the present disclosure can provide an automatic calibration control signal for n calibration monitoring sub-circuits at the same time through one calibration control circuit.
  • the automatic calibration control signal is generated by converting the counting signal output by the counting circuit. Therefore, the calibration control circuit can perform automatic calibration of the offsets of n target circuits to be calibrated simultaneously or sequentially.
  • the calibration efficiency can be improved and the complexity of the calibration circuit can be reduced.
  • n is a positive integer greater than 1
  • multiple calibration monitoring sub-circuits can share the same calibration control circuit, thereby further reducing the layout area of the calibration circuit.
  • each calibration monitoring sub-circuit may include: a signal sampling circuit, which can be coupled to the calibration control circuit and the target circuit respectively, can receive the clock signal and the output signal of the target circuit, and can be used to sample the output signal of the target circuit based on the clock signal to generate a sampling pulse signal; a signal monitoring circuit, which can be coupled to the calibration control circuit and the signal sampling circuit respectively, can receive the automatic calibration control signal and the sampling pulse signal, can be used to monitor the change state of the output signal of the target circuit according to the sampling pulse signal, and output the automatic calibration control signal when the output signal flips state (it should be noted that the automatic calibration control signal here refers to the automatic calibration control signal currently received by the corresponding calibration monitoring sub-circuit from the calibration control circuit, and the automatic calibration control signal will change with the clock signal); a latch circuit, which can be coupled to the signal monitoring circuit, can be used to latch the automatic calibration control signal output by the signal monitoring circuit, and determine the offset calibration value corresponding to the latched automatic calibration control signal as the target offset calibration
  • Fig. 4 takes the calibration monitoring subcircuit 120-1 of the embodiment of Fig. 3 as an example, and other calibration monitoring subcircuits may refer to the calibration monitoring subcircuit 120-1 of the embodiment of Fig. 4.
  • the calibration monitoring subcircuit 120-1 may include a signal sampling circuit 120-11, a signal monitoring circuit 120-12, and a latch circuit 120-13.
  • the signal sampling circuit 120-11 can be coupled to the target circuit 130 (for example, the target circuit 130-1 in Figure 3) and the calibration control circuit 110, and respectively receive the output signal Din of the target circuit 130 and the clock signal OscClk output by the calibration control circuit 140.
  • the signal sampling circuit 120-11 can be used to sample the output signal Din of the target circuit 130 according to the received clock signal OscClk to generate a sampling pulse signal Pul.
  • the target circuit 130 receives the automatic calibration control signal Con output by the control signal generating circuit 113 and changes with the clock signal OscClk.
  • the target circuit 130 corresponds to different automatic calibration control signals Con at different times. Therefore, the output signal Din of the target circuit 130 will change when the automatic calibration control signal Con meets the calibration requirements, that is, the output signal Din will change with the clock signal OscClk.
  • the output signal Din of the target circuit 130 sampled according to the clock signal OscClk will also change when the automatic calibration control signal Con meets the calibration requirements.
  • the signal monitoring circuit 120-12 can be coupled to the calibration control circuit 110 and the signal sampling circuit 120-11 respectively, and can respectively receive the automatic calibration control signal Con output by the calibration control circuit 110 and the sampling pulse signal Pul output by the signal sampling circuit 120-11.
  • the signal monitoring circuit 120-12 can be used to monitor the change state of the output signal Din of the target circuit 130 according to the sampling pulse signal Pul, and output the automatic calibration control signal Con of the calibration control circuit 110 when the state of the output signal Din of the target circuit 130 is reversed.
  • the latch circuit 120-13 can be coupled to the signal monitoring circuit 120-12, and the latch circuit 120-1 can be used to latch the automatic calibration control signal Con output by the signal monitoring circuit 120-12 (i.e., Con-1’ shown in FIG4 , Con-1’ is the automatic calibration control signal received when the output signal Din of the target circuit 130 flips state), and determine the offset calibration value corresponding to the latched automatic calibration control signal Con-1’ as the target offset calibration value of the target circuit 130.
  • Con-1 is the automatic calibration control signal received when the output signal Din of the target circuit 130 flips state
  • the signal monitoring circuit in each calibration monitoring sub-circuit adopts the automatic calibration control signal output by the calibration control circuit, thereby enabling the latch circuit in the calibration monitoring sub-circuit to latch the automatic calibration control signal when the output signal of the target circuit flips state, and there is no need to set a control signal generating circuit between the signal monitoring circuit and the latch circuit (because the generation of the automatic calibration control signal for calibrating the target circuit has been completed in the calibration control circuit, the calibration monitoring sub-circuit can be directly latched without data conversion).
  • one calibration monitoring circuit includes multiple (2 or more) calibration monitoring sub-circuits, the layout area of the calibration circuit can be reduced.
  • the calibration control circuit may be further configured to perform m automatic calibrations on the offset of each target circuit according to the automatic calibration control signal Con, where m may be a positive integer greater than or equal to 1.
  • the signal monitoring circuit when the offset calibration value corresponding to the automatic calibration control signal Con changes from large to small, the signal monitoring circuit outputs the automatic calibration control signal Con' that causes the output signal Din to change from a first level state to a second level state.
  • the output signal is converted from the second level state to the automatic calibration control signal Con' of the first level state.
  • the calibration control circuit performing one automatic calibration on the offset of each target circuit is referred to as one shmoo.
  • the calibration control circuit may perform one shmoo, two shmoos, or multiple (more than two) shmoos on the offset of each target circuit.
  • the automatic calibration control signal during each shmoo may be in a consistent order, such as changing from large to small or from small to large according to the corresponding offset calibration value, or may be in an inconsistent order, such as changing from large to small and from small to large according to the corresponding offset calibration value.
  • each calibration monitoring sub-circuit may also include: a first operation circuit, which can be coupled to the signal monitoring circuit and the latch circuit respectively, and can be used to calculate the average value of m automatic calibration control signals output by the signal monitoring circuit in m automatic calibrations, and output the average value to the latch circuit for latching.
  • a first operation circuit which can be coupled to the signal monitoring circuit and the latch circuit respectively, and can be used to calculate the average value of m automatic calibration control signals output by the signal monitoring circuit in m automatic calibrations, and output the average value to the latch circuit for latching.
  • the first operation circuit may adopt any circuit that can realize the function of averaging the m automatic calibration control signals output by the signal monitoring circuit in m automatic calibrations.
  • the first operation circuit may include a full adder, but the present disclosure is not limited to this.
  • the full adder is used as an example in the following embodiments.
  • the full adder can calculate the average value of the automatic calibration control signal Con’ output by the above-mentioned signal monitoring circuit to cause the output signal Din to convert from a first level state to a second level state, and/or the automatic calibration control signal Con’ output by the signal monitoring circuit to cause the output signal to convert from a second level state to a first level state (a total of m automatic calibration control signals Con’), and latch the average value into the latch circuit.
  • Fig. 5 still uses the calibration monitoring sub-circuit 120-1 of the embodiment of Fig. 3 as an example, and other calibration monitoring sub-circuits may refer to the calibration monitoring sub-circuit 120-1 in the embodiment of Fig. 5.
  • the calibration monitoring sub-circuit 120-1 may include a signal sampling circuit 120-11, a signal monitoring circuit 120-12, a first operation circuit 120-14, and a latch circuit 120-13.
  • the signal sampling circuit 120-11 can be coupled to the target circuit 130 and the calibration control circuit 110 respectively, and respectively receive the output signal Din of the target circuit 130 and the clock signal OscClk output by the calibration control circuit 110.
  • the signal sampling circuit 120-11 can be used to sample the output signal Din of the target circuit 130 according to the received clock signal OscClk to generate a sampling pulse signal Pul.
  • the signal monitoring circuit 120-12 can be coupled to the calibration control circuit 110 and the signal sampling circuit 120-11 respectively, and can respectively receive the automatic calibration control signal Con output by the calibration control circuit 110 and the sampling pulse signal Pul output by the signal sampling circuit 120-11.
  • the signal monitoring circuit 120-12 can be used to monitor the changing state of the output signal Din of the target circuit 130 according to the sampling pulse signal Pul, and output the automatic calibration control signal Con (represented as Con-1 in Figure 5) of the calibration control circuit 110 when the state of the output signal Din of the target circuit 130 is reversed.
  • the first operation circuit 120-14 can be coupled to the signal monitoring circuit 120-12 and the latch circuit 120-13 respectively, and the automatic calibration control signal Con-1 output by the received signal monitoring circuit 120-12 can be used to calculate the average value Con-1' of the m received automatic calibration control signals Con-1, and output the average value Con-1' to the latch circuit 120-13 for latching, and determine the offset calibration value corresponding to the latched automatic calibration control signal Con-1' as the target offset calibration value of the target circuit 130.
  • the calibration circuit provided by the embodiment of the present disclosure can also perform automatic calibration on the offset of each target circuit m times according to the automatic calibration control signal, so that each calibration monitoring subcircuit can receive m automatic calibration control signals.
  • Each calibration monitoring subcircuit can calculate the average value of the m received automatic calibration control signals by adding a first operation circuit, and output the average value to the latch circuit for latching, thereby further improving the accuracy of the calibration.
  • each of the calibration monitoring sub-circuit may also include: a second operation circuit, which can be coupled to the signal monitoring circuit and the latch circuit respectively, and can be used to select the automatic calibration control signal with the highest occurrence frequency from the m automatic calibration control signals output by the signal monitoring circuit in m automatic calibrations, and output it to the latch circuit for latching.
  • a second operation circuit which can be coupled to the signal monitoring circuit and the latch circuit respectively, and can be used to select the automatic calibration control signal with the highest occurrence frequency from the m automatic calibration control signals output by the signal monitoring circuit in m automatic calibrations, and output it to the latch circuit for latching.
  • Fig. 6 still uses the calibration monitoring sub-circuit 120-1 of the embodiment of Fig. 3 as an example, and other calibration monitoring sub-circuits may refer to the calibration monitoring sub-circuit 120-1 in the embodiment of Fig. 6.
  • the calibration monitoring sub-circuit 120-1 may include a signal sampling circuit 120-11, a signal monitoring circuit 120-12, a second operation circuit 120-15, and a latch circuit 120-13.
  • the signal sampling circuit 120-11 can be coupled to the target circuit 130 and the calibration control circuit 110 respectively, and respectively receive the output signal Din of the target circuit 130 and the clock signal OscClk output by the calibration control circuit 110.
  • the signal sampling circuit 120-11 can be used to sample the output signal Din of the target circuit 130 according to the received clock signal OscClk to generate a sampling pulse signal Pul.
  • the signal monitoring circuit 120-12 can be coupled to the calibration control circuit 110 and the signal sampling circuit 120-11 respectively, and can be connected to The signal monitoring circuit 120-12 receives the automatic calibration control signal Con output by the calibration control circuit 110 and the sampling pulse signal Pul output by the signal sampling circuit 120-11.
  • the signal monitoring circuit 120-12 can be used to monitor the change state of the output signal Din of the target circuit 130 according to the sampling pulse signal Pul, and output the automatic calibration control signal Con (represented as Con-1 in Figure 6) of the calibration control circuit 110 when the state of the output signal Din of the target circuit 130 is reversed.
  • the second operation circuit 120-15 can be coupled to the signal monitoring circuit 120-12 and the latch circuit 120-13 respectively, and the automatic calibration control signal Con-1 output by the received signal monitoring circuit 120-12 can be used to select the automatic calibration control signal Con-1' with the highest occurrence frequency from the m received automatic calibration control signals Con-1, and output it to the latch circuit for latching, and the offset calibration value corresponding to the latched automatic calibration control signal Con-1' is determined as the target offset calibration value of the target circuit 130.
  • the calibration circuit provided by the embodiment of the present disclosure can also perform automatic calibration on the offset of each target circuit m times according to the automatic calibration control signal, so that each calibration monitoring subcircuit can receive m automatic calibration control signals.
  • Each calibration monitoring subcircuit can add a second operation circuit to select the automatic calibration control signal with the highest frequency from the m received automatic calibration control signals and latch it into the latch circuit, thereby further improving the accuracy of the calibration.
  • the target circuit may be a data receiving circuit
  • the output signal may include a first phase output signal, a second phase output signal, a third phase output signal, and a fourth phase output signal.
  • Each calibration monitoring subcircuit may also include: a selection circuit, which may be coupled to the target circuit and the signal sampling circuit respectively, may receive the first phase output signal, the second phase output signal, the third phase output signal, and the fourth phase output signal, and may be used to sequentially select one of the first phase output signal, the second phase output signal, the third phase output signal, or the fourth phase output signal to be sent to the signal sampling circuit, so as to sequentially complete the offset calibration of the target circuit for each phase output signal, and latch the target offset calibration value corresponding to each phase output signal.
  • Fig. 7 still uses the calibration monitoring subcircuit 120-1 of the embodiment of Fig. 3 as an example, and other calibration monitoring subcircuits may refer to the calibration monitoring subcircuit 120-1 of the embodiment of Fig. 7.
  • the calibration monitoring subcircuit 120-1 may include a selection circuit 120-16, a signal sampling circuit 120-11, a signal monitoring circuit 120-12, and a latch circuit 120-13.
  • the selection circuit 120-16 can be coupled to the target circuit 130 and the signal sampling circuit 120-11, respectively.
  • the target circuit 130 is a data receiving circuit, which can output a first phase output signal DinOr, a second phase output signal DinOf, a third phase output signal DinEr, and a fourth phase output signal DinEf, respectively.
  • the selection circuit 120-16 receives the first phase output signal DinOr, the second phase output signal DinOf, the third phase output signal DinEr, and the fourth phase output signal DinEf output by the data receiving circuit, respectively, and selects one of the phase output signals from the first phase output signal DinOr, the second phase output signal DinOf, the third phase output signal DinEr, and the fourth phase output signal DinEf in turn as the output signal Din of the target circuit 130 input to the signal sampling circuit 120-11 at the corresponding time.
  • DinOr is selected at the first time t1 as Din input to the signal sampling circuit 120-11
  • DinOf is selected at the second time t2
  • DinEf is selected as Din input to the signal sampling circuit 120-11
  • DinOr is selected as Din input to the signal sampling circuit 120-11
  • DinOf is selected as Din input to the signal sampling circuit 120-11
  • DinOr is selected as Din input to the signal sampling circuit 120-11
  • DinOf is selected as Din input to the signal sampling circuit 120-11
  • DinEr is selected as Din input to the signal sampling circuit 120-11
  • DinEf is selected as Din input to the signal sampling circuit 120-11, ..., and the cycle is executed in sequence.
  • the description of the signal sampling circuit 120 - 11 , the signal monitoring circuit 120 - 12 and the latch circuit 120 - 13 in the embodiment of FIG. 7 may refer to the other embodiments described above.
  • the calibration circuit provided in the embodiment of the present disclosure can output four phase output signals with different phases for one target circuit to be calibrated.
  • By adding a selection circuit in each calibration monitoring subcircuit it is possible to automatically calibrate the four phase output signals output by the target circuit in turn, thereby simplifying the calibration process and improving the calibration efficiency.
  • the latch circuit may include: a first latch circuit, which can be used to latch a target offset calibration value corresponding to a first phase output signal; a second latch circuit, which can be used to latch a target offset calibration value corresponding to a second phase output signal; a third latch circuit, which can be used to latch a target offset calibration value corresponding to a third phase output signal; and a fourth latch circuit, which can be used to latch a target offset calibration value corresponding to a fourth phase output signal.
  • Fig. 8 is still illustrated by taking the calibration monitoring sub-circuit 120-1 of the embodiment of Fig. 7 as an example, and other calibration monitoring sub-circuits may refer to the calibration monitoring sub-circuit 120-1 of the embodiment of Fig. 8. As shown in Fig. 8, based on the embodiment of Fig.
  • the latch circuit may include a first latch circuit 120-131, a second latch circuit 120-132, a third latch circuit 120-133, and a fourth latch circuit 120-134.
  • the first latch circuit 120-131 can be used to latch the target offset calibration value corresponding to the corresponding automatic calibration control signal Con-11' latched when the state of the first phase output signal DinOr is flipped.
  • the second latch circuit 120-132 can be used to latch the corresponding automatic calibration control signal Con-12' latched when the state of the second phase output signal DinOf is flipped.
  • the third latch circuit 120-133 can be used to latch the target offset calibration value corresponding to the corresponding automatic calibration control signal Con-13' latched when the state of the third phase output signal DinEr is flipped.
  • the fourth latch circuit 120-134 can be used to latch the target offset calibration value corresponding to the corresponding automatic calibration control signal Con-14' latched when the state of the fourth phase output signal DinEf is flipped.
  • the target circuit can output k phase output signals, and k can be a positive integer greater than or equal to 1.
  • the selection circuit can select one phase output signal from these k phase output signals in turn and input it into the signal sampling circuit, and the latch circuit can correspondingly include the first latch circuit to the kth latch circuit, and the kth latch circuit is used to latch the target offset calibration value corresponding to the corresponding automatic calibration control signal latched when the state of the kth phase output signal is flipped.
  • the calibration circuit when a target circuit to be calibrated can output k phase output signals with different phases, can realize automatic calibration of the offset of the phase output signals with k different phases of the target circuit by setting corresponding first to k-th latch circuits in the latch circuit in each calibration monitoring sub-circuit to respectively latch the automatic calibration control signals when the corresponding phase output signals are flipped in state, thereby simplifying the calibration process and improving the calibration efficiency.
  • the automatic calibration control signal may be N-bit binary data, where N may be a positive integer greater than or equal to 1.
  • the signal monitoring circuit may include: a first trigger to an N-th trigger, wherein: the i-th trigger may be coupled to the calibration control circuit, may receive the i-th bit and the sampling pulse signal in the automatic calibration control signal, and may be used to determine the automatic calibration control signal that causes the output signal to flip state according to the i-th bit and the sampling pulse signal in the automatic calibration control signal, where i is a positive integer greater than or equal to 1 and less than or equal to N.
  • the signal monitoring circuit 120-12 in the calibration monitoring sub-circuit 120-1 is used as an example for illustration, and the signal monitoring circuits in other calibration monitoring sub-circuits can refer to the embodiment of Fig. 9.
  • the signal monitoring circuit 120-12 may include a first trigger D1, a second trigger D2, ..., and an Nth trigger DN, and the automatic calibration control signal output by the calibration control circuit 110 includes N bits of binary data, respectively represented as Con ⁇ 0>, Con ⁇ 1>, ..., Con ⁇ N-1>.
  • the first trigger D1 can be coupled to the calibration control circuit 110 and the signal sampling circuit respectively, and can receive the first bit Con ⁇ 0> in the automatic calibration control signal output by the calibration control circuit 110 and the sampling pulse signal Pul output by the signal sampling circuit 120-11 respectively.
  • the first trigger D1 can be used to determine the first bit Con ⁇ 0>' in the automatic calibration control signal that causes the output signal Din of the target circuit to flip state according to Con ⁇ 0> and Pul. Specifically, when the output signal Din of the target circuit flips state, the sampled Pul signal will also flip, that is, the Pul signal generates a level jump edge, triggering the first trigger D1 to output the data of the current automatic calibration control signal.
  • the second trigger D2 can be coupled to the calibration control circuit 110 and the signal sampling circuit respectively, and can respectively receive the second bit Con ⁇ 1> in the automatic calibration control signal output by the calibration control circuit 110 and the sampling pulse signal Pul output by the signal sampling circuit.
  • the first trigger D2 can be used to determine the second bit Con ⁇ 1>’ in the automatic calibration control signal that causes the output signal Din of the target circuit to flip its state according to Con ⁇ 1> and Pul.
  • the Nth trigger DN can be coupled to the calibration control circuit 110 and the signal sampling circuit respectively, and can respectively receive the Nth bit Con ⁇ N-1> in the automatic calibration control signal output by the calibration control circuit 110 and the sampling pulse signal Pul output by the signal sampling circuit.
  • the first trigger D1 can be used to determine the Nth bit Con ⁇ N-1>’ in the automatic calibration control signal that causes the output signal Din of the target circuit to flip its state according to Con ⁇ N-1> and Pul.
  • the first to Nth triggers in the embodiments of the present disclosure can adopt any triggers that can realize the automatic calibration control signal function of determining whether the output signal of the target circuit has flipped state.
  • the present disclosure does not limit the type of trigger.
  • D triggers are used as examples, but the present disclosure is not limited to this.
  • the signal monitoring circuit in each calibration monitoring sub-circuit may include N triggers to determine the 1st to Nth bits in the automatic calibration control signal that cause the output signal of the corresponding target circuit to flip state.
  • the signal sampling circuit may include: an N+1th trigger, which may receive an output signal and a clock signal, and may be used to sample the output signal according to the clock signal to generate a first sampling data, where N may be a positive integer greater than or equal to 1; an inverter, which may receive a clock signal, and may be used to generate a complementary clock signal according to the clock signal; an N+2th trigger, The device can be coupled to the inverter, can receive the output signal and the complementary clock signal, and can be used to sample the output signal according to the complementary clock signal to generate second sampling data; the XOR gate can be coupled to the N+1th trigger and the N+2th trigger respectively, can receive the first sampling data and the second sampling data, and can be used to generate a sampling pulse signal according to the first sampling data and the second sampling data.
  • the signal sampling circuit 120-11 in the calibration monitoring sub-circuit 120-1 is used as an example for illustration, and the signal sampling circuits in other calibration monitoring sub-circuits can refer to the embodiment of Fig. 10.
  • the signal sampling circuit 120-11 may include an inverter 120-111, an N+1th flip-flop D(N+1), an N+2th flip-flop D(N+2), and an XOR gate 120-112.
  • the N+1th trigger D(N+1) can receive the output signal Din and the clock signal OscClk of the target circuit, and the N+1th trigger D(N+1) can be used to sample the output signal Din of the target circuit according to the clock signal OscClk to generate the first sampled data Samp1.
  • the inverter 120-111 can receive the clock signal OscClk, and can be used to generate the complementary clock signal /OscClk according to the clock signal OscClk, that is, the phases of the clock signal OscClk and the complementary clock signal /OscClk at the same time are opposite.
  • the N+2th trigger D(N+2) can be coupled to the inverter 120-111, can receive the output signal Din and the complementary clock signal /OscClk of the target circuit, and can be used to sample the output signal Din of the target circuit according to the complementary clock signal /OscClk to generate the second sampled data Samp2.
  • the XOR gates 120-112 can be coupled to the N+1th trigger D(N+1) and the N+2th trigger D(N+2), respectively, and can receive the first sampling data Samp1 output by the N+1th trigger D(N+1) and the second sampling data Samp2 output by the N+2th trigger D(N+2).
  • the XOR gates 120-112 can be used to generate a sampling pulse signal Pul according to the first sampling data Samp1 and the second sampling data Samp2.
  • FIG11 is a timing diagram based on the signal sampling circuit shown in FIG10. As shown in FIG11, the horizontal coordinates of the Din, OscClk, /OscClk, Samp1, Samp2 and Pul signals are all time t, and the vertical coordinates are all voltage values. The phases of OscClk and /OscClk at the same time are opposite.
  • the Samp1 signal jumps from a low level to a high level at the next falling edge of the rising edge of the OscClk
  • the Samp2 signal jumps from a low level to a high level at the next falling edge of /OscClk.
  • a high-level Pul signal is generated.
  • the signal sampling circuit in each calibration monitoring sub-circuit may include an inverter, an N+1th trigger, an N+2th trigger and an XOR gate, thereby realizing the function of generating a sampling pulse signal, and the sampling pulse signal can be used to monitor the change state of the output signal of the target circuit corresponding to the calibration monitoring sub-circuit, so as to output an automatic calibration control signal to the latch circuit when the output signal of the target circuit flips state, thereby accurately calibrating the offset of the target circuit automatically.
  • the target circuit may control a switch of a corresponding calibration device in the calibration module according to an automatic calibration control signal.
  • the target circuit in the embodiments of the present disclosure can control the switch of the corresponding calibration device in the calibration module according to the automatic calibration control signal latched in the latch circuit.
  • the calibration module can be set in the target circuit or in the calibration test circuit.
  • the present disclosure does not limit the setting position of the calibration module. In the following embodiments, the calibration module is set in the target circuit for example, but the present disclosure is not limited to this.
  • an input buffer (IB, included in a data receiving circuit) is used to compare the level of an input signal with a reference level to determine whether the level of the input signal is higher or lower than the reference level.
  • IB input buffer
  • the calibration circuit provided in the disclosed embodiment may be used to compensate for the mismatch of the device on a differential pair.
  • the target circuit includes four data receiving circuits as shown in FIG12 (these four Rx circuits can be used to output four phase output signals DinOr, DinOf, DinEr and DinEf respectively), and the calibration module is set in the target circuit for example, but the present disclosure is not limited to this.
  • the input buffer includes switch elements P22 and P25 that receive the reference voltage signal Vref and the input signal DQ_IN respectively, and switches corresponding to the calibration devices in the calibration module.
  • the switches corresponding to the calibration devices in the calibration module may include multiple compensation switch elements, such as transistors P23-P24 and transistors P26-P27 shown in FIG12, the first end of the transistor P11 is coupled to the first power supply voltage VDD, the second end is respectively coupled to the first end of P25 and P22, the control end is input with a data sampling clock signal CLK, and the Din output by the Rx circuit in FIG12 may be any one of DinOr, DinOf, DinEr and DinEf, and DinN represents the inverted signal of Din.
  • the control end of P22 receives Vref, and the second end is respectively coupled to the control ends of transistors P31, P32 and P33 and the first end of P13.
  • the control end of P25 receives DQ_IN, and the second end is respectively coupled to the control ends of transistors P34, P35 and P36 and the first end of P12.
  • the control end of P12 is coupled to the control end of P13 for receiving CLK; the second ends of P12, P13, P31, P32 and P33, P34, P35 and P36 are all used to receive the second power supply voltage VSS.
  • the first end of P23 and the first end of P24 are both coupled to the first end of P31 for outputting DinN.
  • the control ends of P23, P24, P26 and P27 are respectively used to receive the control end signal offset ⁇ 3:0>(offset ⁇ 3> ⁇ offset ⁇ 0>).
  • the second end of P23 is coupled to the first end of P32, and the second end of P24 is coupled to the first end of P31.
  • the second end is coupled to the first end of P33, the second end of P27 is coupled to the first end of P35, and the second end of P26 is coupled to the first end of P34.
  • the latched automatic calibration control signal Con ⁇ 2:0> (Con ⁇ 2> ⁇ Con ⁇ 0>) is used to control the generation of the control end signal offset ⁇ 3:0> (offset ⁇ 3> ⁇ offset ⁇ 0>) of the four compensation switch elements, thereby controlling the closing of the compensation switch elements P23 ⁇ P24 and opening of the compensation switch elements P26 ⁇ P27 to obtain more current for the compensation switch element P25.
  • the latched automatic calibration control signal Con ⁇ 2:0> is used to control the generation of the control terminal signal offset ⁇ 3:0> of the four compensation switch elements, thereby controlling the opening of the compensation switch elements P23 ⁇ P24 and the closing of the compensation switch elements P26 ⁇ P27 to obtain more current for the compensation switch element P22.
  • the circuit composed of the compensation switch elements shown in FIG12 can be used to calibrate the data receiving circuit, so it can be called a ROC (Rx Offset Calibration) module.
  • the ROC module can be a circuit for calibrating the mismatch of the tubes on both sides of the comparator in the memory such as LPDDR5X.
  • a clock signal (which can be expressed as OscClk) can be generated by Osc (crystal oscillator), and then the IB is calibrated in the order from the extreme value of the mismatch on the left to the extreme value of the mismatch on the right.
  • Osc crystal oscillator
  • the output signal toggles (e.g., switches between two states, converts), indicating that the mismatch of the offset gradually reaches a balance.
  • the automatic calibration control signal is adjusted in sequence, when Con ⁇ 2:0> is "110", the output signal remains "0 (indicating a low level)" and does not change, and the control end signal offset ⁇ 3:0> of the compensation switch element corresponding to the state of "110" is "0010", that is, the two compensation switch elements on the left are not turned on, and a relatively large transistor on the right, such as P24, is turned on, and when the automatic control signal Con ⁇ 2:0> changes to "101", the output signal toggles, and the control end signal offset ⁇ 3:0> of the compensation switch element corresponding to the state of "101" is "0001", that is, the two compensation switch elements on the left are not turned on, and a relatively small transistor on the right, such as P23, is turned on.
  • the output signal changes from "0 (indicating a low level)" to "1 (indicating a high level)", indicating that transistors P22 and P25 match at this time.
  • the differential tube may cause mismatch due to process reasons. This effect will become more obvious under high-speed conditions. Therefore, it needs to be calibrated through a calibration module.
  • the calibration module calibrates the mismatch by adding transistors P23 ⁇ P24/P26 ⁇ P27 on the left and right sides of transistors P22 and P25 respectively.
  • the target circuit can be correctly flipped in the calibration mode (that is, the data (data, i.e. Din in the diagram) output after comparison between DQ_IN (input) and VREFDQ (reference voltage) can be flipped), it means that the difference between the input and reference voltage is very small and can be identified, and the sensitivity is high, then the corresponding automatic calibration control signal (which can be represented by code) is locked. That is, if the output data Din is always 0 or 1, there will be no flip. At this time, it is necessary to continue to adjust the code and continue calibration until the output data Din flips. At this time, the calibration is completed and the code can be locked.
  • the target circuit provided by the embodiment of the present disclosure is not limited to the example of FIG. 12.
  • a resistor and/or capacitor and other devices may be added to the drain of each switch element shown in FIG. 12 to adjust the current in the path where each adjustment transistor is located, thereby setting the accuracy and adjustment range of the offset calibration.
  • the transistors P32-P35 in FIG. 12 may be removed, and the transistors P23-P24/P26-P27 may be coupled to the ground terminal VSS.
  • the calibration circuit provided in the embodiment of the present disclosure can be used to compensate for the offset of the comparator.
  • it can be adjusted through the latched code so that the data output by the comparator can be correctly flipped, that is, the comparison result of DQ_IN and VREFDQ can be correct.
  • DQ_IN is greater than VREFDQ
  • the output data is accurately flipped to 1
  • DQ_IN is less than VREFDQ
  • the output data is accurately flipped to 0.
  • FIG13 is a schematic diagram of a circuit for generating a control terminal signal of a calibration module according to an automatic calibration control signal in an exemplary embodiment of the present disclosure.
  • an inverter 1310, a selector 1320, a selector 1330, a selector 1340, an inverter 1350, a NOR gate 1360, a NOR gate 1370, a NOR gate 1380, and a NOR gate 1390 may be included.
  • the input end of the inverter 1310 can be used to receive the selection signal sel, and the output end of the inverter 1310 is respectively coupled to the selection input ends of the selectors 1320 to 1340, so as to help the selector 1320 select one from Default ⁇ 2> and Con ⁇ 2> respectively inputted from the two input ends as the third calibration signal AdjIbTrip ⁇ 2>, help the selector 1330 select one from Default ⁇ 1> and Con ⁇ 1> respectively inputted from the two input ends as the second calibration signal AdjIbTrip ⁇ 1>, and help the selector 1340 select one from Default ⁇ 0> and Con ⁇ 0> respectively inputted from the two input ends as the first calibration signal AdjIbTrip ⁇ 0>.
  • the output end of the selector 1320 is respectively coupled to the input end of the inverter 1350, the second input end of the NOR gate 1380, and the first input end of the NOR gate 1390.
  • the output end of the inverter 1350 is respectively coupled to the second input end of the NOR gate 1360 and the first input end of the NOR gate 1390.
  • the output end of the selector 1330 is respectively coupled to the first input end of the NOR gate 1360 and the first input end of the NOR gate 1380.
  • the output end of the selector 1340 is respectively coupled to the second input end of the NOR gate 1370 and the second input end of the NOR gate 1390.
  • the output ends of the NOR gates 1360 to 1390 are respectively used to output offset ⁇ 3> to offset ⁇ 0>.
  • Table 1 below takes Con ⁇ 2:0> as the calibration signal AdjIbTrip ⁇ 2:0> as an example to illustrate the conversion relationship between Con ⁇ 2:0> and offset ⁇ 3:0>.
  • “1" represents “on” and “0” represents “off”.
  • the control terminal signals of the compensation switch elements P23-P24 and P26-P27 generated by the latched automatic calibration control signal Con ⁇ 2:0> can be represented by Table 1 below:
  • the compensation switch element P24 when the compensation switch element P24 is turned on and the compensation switch elements P23, P26 and P27 are turned off at the same time, that is, when the value of offset ⁇ 3:0> is "0100" and the corresponding Con ⁇ 2:0> is "001", P22 and P25 match, then the output signal Din will toggle, and the latch circuit can record this value "001" and send it to the Rx circuit of the corresponding target circuit to automatically calibrate the offset of the Rx circuit of the target circuit.
  • the value of offset ⁇ 3:0> "0100” can be called the offset calibration value corresponding to the latched automatic calibration control signal.
  • FIG14 is a schematic diagram of a calibration circuit in another exemplary embodiment of the present disclosure.
  • the first to Nth triggers are all D triggers, and the N+1th trigger and the N+2th trigger are also D triggers
  • the clock generation circuit uses Osc
  • the counting circuit uses a counter
  • the control signal generation circuit uses a converter
  • a calibration module is provided in the target circuit
  • the 4 Rx circuits of the target circuit respectively output 4 phase output signals DinOr, DinOf, DinEr and DinEf
  • the latch circuit includes four latches
  • the first operation circuit included in the signal monitoring circuit includes a full adder
  • the number of bits of the counter, the number of bits of the converter output, the number of bits of the automatic calibration control signal, and the number of latches are all corresponding and can all be N. They can be designed according to needs. When there are more calibration components to be controlled and higher calibration accuracy requirements, more bits can be set accordingly.
  • the four phase output signals DinOr, DinOf, DinEr and DinEf are output signals of four different phases output by the target circuit (here, the Rx circuit is used as an example).
  • the mismatch conditions of the output signals of the four different phases may be different. Therefore, in the embodiment of the present disclosure, the calibration control circuit RocCnt can be used to calibrate the output signals of the four different phases respectively, and four latches can be used to lock the corresponding automatic calibration control signals.
  • the output signal may be one or more, and the present disclosure does not limit this.
  • the calibration circuit 1400 may include a calibration control circuit 1410 and a calibration monitoring circuit 1420 .
  • the calibration control circuit 1410 may be represented as RocCnt, and the calibration monitoring circuit 1420 may be represented as DqRoc.
  • the calibration control circuit 1410 may include an Osc 1411, a counter 1412, and a converter 1413.
  • the Osc 1411 may be used to output a clock signal OscClk.
  • the counter 1412 may be coupled to the Osc 1411, receive the clock signal OscClk output by the Osc 1411, and generate a count signal Cnt ⁇ 2:0> (i.e., Cnt ⁇ 2> to Cnt ⁇ 0>), wherein the count signal Cnt ⁇ 2:0> indicates a count value of the clock signal OscClk.
  • the converter 1413 may be coupled to the counter 1412, receive the count signal Cnt ⁇ 2:0> output by the counter 1412, and convert it into an automatic calibration control signal Con ⁇ 2:0> (i.e., Con ⁇ 2> to Con ⁇ 0>).
  • the calibration control circuit 1410 may further include a selector 1414, and the selector 1414 may include two input terminals, one of which may be used to receive Default ⁇ 2:0>, and the other input terminal may be used to receive the automatic calibration control signal Con ⁇ 2:0> output by the converter 1413.
  • the selector 1414 may be used to select one of the received Default ⁇ 2:0> and the automatic calibration control signal Con ⁇ 2:0> as AdjIbTrip ⁇ 2:0>, and input AdjIbTrip ⁇ 2:0> to the calibration module 1431 of the target circuit 1430 to calibrate the offset of the target circuit 1430.
  • the Default ⁇ 2:0> signal in the RocCnt circuit can be set by programming the DRAM fuse or by setting the parameters in the mode register. If the ROC can be understood as an automatic calibration process of the Rx offset, then this Default ⁇ 2:0> is the default parameter setting when there is no automatic calibration process. The difference is that the Rx circuits corresponding to the four phases (DinOr, DinOf, DinEr and DinEf) of the ROC automatic calibration process are not connected, and the generated Con ⁇ 2:0> may also be different. In addition, the offset calibration value set by automatic calibration is more accurate. However, if the offset calibration value set by Default ⁇ 2:0> is set in advance or the controller is configured through the mode register, it has not been automatically calibrated and its accuracy is not high.
  • the value range of Default ⁇ 2:0> is 0-7, and it is set by burning or setting the parameters in the mode register, which can be considered as a manual intervention, that is, the calibration circuit provided in the embodiment of the present disclosure can simultaneously realize manual configuration (or default configuration) and automatic calibration.
  • the selector 1414 selects Default ⁇ 2:0> as the AdjIbTrip ⁇ 2:0> signal input to the calibration module 1431 of the target circuit 1430, the manual calibration mode or the default calibration mode is adopted; when the selector 1414 selects Con ⁇ 2:0> as the AdjIbTrip ⁇ 2:0> signal input to the calibration module 1431 of the target circuit 1430, the automatic calibration mode is adopted.
  • the AdjIbTrip ⁇ 2:0> signal represents the signal entering the Rx offset, which means that the entire process of ROC relies on the shmoo AdjIbTrip ⁇ 2:0> signal to achieve automatic calibration of the Rx offset. Therefore, when automatic calibration is selected, the output of the converter 1413 is selected as the input of the selector 1414 to shmoo offset, so that the offset calibration value (i.e., gear position) corresponding to the output signal Din of the current target circuit 1430 can be known.
  • the calibration monitoring circuit 1420 may include a selection circuit (i.e., Mux 1421), a signal sampling circuit 1422, a signal monitoring circuit 1423, and a latch circuit.
  • Mux 1421 can be coupled to a target circuit 1430, and the target circuit 1430 can output four phase output signals DinOr, DinOf, DinEr, and DinEf, which are respectively input to Mux 1421.
  • Mux 1421 can sequentially select one of the four phase output signals DinOr, DinOf, DinEr, and DinEf as the output signal Din of the target circuit 1430, that is, sequentially select the four phase output signals DinOr, DinOf, DinEr, and DinEf to calibrate different Rx circuits in the target circuit.
  • the signal sampling circuit 1422 may include a D flip-flop 14221 (a fourth flip-flop), a D flip-flop 14222 (a fifth flip-flop), an inverter, and an XOR gate 14223.
  • the inverter is coupled to Osc 1411, receives the clock signal OscClk, and generates a complementary clock signal /OscClk, and the clock signal OscClk and the complementary clock signal /OscClk are mutually inverted signals.
  • the data input terminal D of the D flip-flop 14221 and the data input terminal D of the D flip-flop 14222 are respectively coupled to Mux 1421, and receive the output signal Din output by Mux 1421.
  • the clock input terminal of the D flip-flop 14221 is coupled to Osc 1411, and receives the clock signal OscClk output by Osc 1411.
  • the clock input terminal of the D flip-flop 14222 is coupled to the inverter, and receives the complementary clock signal /OscClk.
  • the D flip-flop 14221 samples the output signal Din based on the clock signal OscClk to generate the first sampled data Samp1, and outputs the first sampled data Samp1 through the data output terminal Q of the D flip-flop 14221.
  • the D flip-flop 14222 samples the output signal Din based on the complementary clock signal /OscClk to generate the second sampled data Samp2, and outputs the second sampled data Samp2 through the data output terminal Q of the D flip-flop 14222.
  • the two input terminals of the XOR gate 14223 are respectively coupled to the data output terminal Q of the D flip-flop 14221 and the data output terminal Q of the D flip-flop 14222 to receive the first sampled data Samp1 and the second sampled data Samp2, and generate a sampling pulse signal Pul according to the first sampled data Samp1 and the second sampled data Samp2, that is, when the state of the output signal Din is flipped, the signal sampling circuit 1422 outputs a sampling pulse signal Pul.
  • the signal monitoring circuit may also be used to monitor the changing state of the output signal of the target circuit during each automatic calibration process, and output a corresponding automatic calibration control signal each time the state of the output signal flips.
  • the signal monitoring circuit 1423 may include a D flip-flop 14231 (i.e., a first flip-flop), a D flip-flop 14232 (i.e., a second flip-flop), and a D flip-flop 14233 (i.e., a third flip-flop).
  • the data input terminal D of the D flip-flop 14231, the data input terminal D of the D flip-flop 14232, and the data input terminal D of the D flip-flop 14233 are respectively coupled to the converter 1413 in the calibration control circuit 1410 to respectively receive the third bit Con ⁇ 2>, the second bit Con ⁇ 1>, and the first bit Con ⁇ 0> of the automatic calibration control signal output by the converter 1413.
  • the clock input terminal of the D flip-flop 14231, the clock input terminal of the D flip-flop 14232, and the clock input terminal of the D flip-flop 14233 are respectively coupled to the XOR gate 14223 to respectively receive the sampling pulse signal Pul.
  • the D flip-flop 14231 determines the automatic calibration control signal that causes the output signal Din to flip state according to the third bit Con ⁇ 2> in the automatic calibration control signal and the sampling pulse signal Pul, and outputs it through the data output terminal Q of the D flip-flop 14231, which is represented as Q ⁇ 2> here.
  • the D flip-flop 14232 determines the automatic calibration control signal that causes the output signal Din to flip state according to the second bit Con ⁇ 1> in the automatic calibration control signal and the sampling pulse signal Pul, and outputs it through the data output terminal Q of the D flip-flop 14232, which is represented as Q ⁇ 1> here.
  • the D flip-flop 14233 determines the automatic calibration control signal that causes the output signal Din to flip state according to the first bit Con ⁇ 0> in the automatic calibration control signal and the sampling pulse signal Pul, and outputs it through the data output terminal Q of the D flip-flop 14233, which is represented as Q ⁇ 0> here.
  • the ellipsis “...” in the DqRoc circuit in FIG14 indicates that other circuits may exist between the D flip-flops 14231 - 14233 and between the full adder 14234 as long as they can play a latching role.
  • the signal monitoring circuit 1423 may further include a full adder 14234.
  • the input end of the full adder 14234 may be coupled to the data output end Q of the D flip-flop 14231, the data output end Q of the D flip-flop 14232, and the data output end Q of the D flip-flop 14233, respectively.
  • the output terminal Q is used to calculate the average value of the m automatic calibration control signals output by the signal monitoring circuit in m automatic calibrations, and output the average value to latch 14241, latch 14242, latch 14243 or latch 14244 in the latch circuit for latching.
  • the full adder 14234 can realize the function of (Number+Number)/2, where the first Number represents the value of Con ⁇ 2:0> that causes the OUT of IB in the target circuit (i.e., the output signal Din) to change from a low level to a high level, and the second Number represents the value of Con ⁇ 2:0> that causes the OUT of IB to change from a high level to a low level, that is, the average of the two is calculated as the final latched automatic calibration control signal.
  • latch 14241 (LatchEr, corresponding to the first latch circuit mentioned above) is the average value of the two Con ⁇ 2:0> when the state of DinOr is flipped.
  • latch 14242 (corresponding to the second latch circuit mentioned above) is the average value of the two Con ⁇ 2:0> when the state of DinOf is flipped.
  • latch 14243 (corresponding to the third latch circuit mentioned above) is the average value of the two Con ⁇ 2:0> when the state of DinEr is flipped.
  • latch 14244 (corresponding to the fourth latch circuit mentioned above) is the average value of the two Con ⁇ 2:0> when the state of DinEf is flipped.
  • the calibration circuit provided in the embodiment of the present disclosure can, on the one hand, realize the automatic calibration function of Rx offset in DRAM.
  • Rx is an input circuit.
  • the specification (SPEC) of LPDDR5X stipulates that such a circuit is required to realize the automatic calibration of Rx offset.
  • the calibration circuit can automatically calibrate the mismatch of the Rx circuit to a better effect, adjust the mismatch of the differential signal under high-frequency input, and finally improve the signal to make the write eye diagram larger.
  • the converter is set in RocCnt, the count signal Cnt output by the counter is converted, the automatic calibration control signal Con is output, and the automatic calibration control signal Con is input into the signal monitoring circuit of DqRoc.
  • the D flip-flop in the signal monitoring circuit outputs the automatic calibration control signal corresponding to the target circuit (rather than other corresponding codes), so that the output value of the signal monitoring circuit can be directly latched in the DqRoc circuit and applied to the calibration of the target circuit, without setting a converter for code conversion and then latching, thereby reducing the layout area of the calibration circuit.
  • the following takes the use of the calibration circuit to calibrate the Rx offset in LPDDR5X as an example.
  • the constructed digital logic structure is used to shmoo the mismatch of the 8 Rx gears from small to large or from large to small.
  • the order of counters from 0-7 is changed to an order that conforms to the Rx offset from small to large (i.e. 7-6-5-4-0-1-2-3), or the order of counters from 7-0 is changed to an order that conforms to the Rx offset from large to small (i.e. 3-2-1-0-4-5-6-7).
  • the gear of the output signal change is latched and input into Rx to complete automatic calibration. That is, the automatic calibration control signal Con can be sorted in the order of small to large or from large to small according to the corresponding offset calibration values.
  • the RocCnt circuit includes an Osc circuit, a counter controlled by a clock signal output by the Osc circuit, and a converter that converts the counter count value into an automatic calibration control signal.
  • the present disclosure provides several converter implementation circuits for one of the conversion correspondences, as shown in Figures 15-17 (different conversion correspondences have different specific implementation circuits.
  • the same conversion correspondence may have multiple implementation circuits, which are not specifically limited here), which are used to convert the count signal 000-001-010-011-100-101-110-111 into an automatic calibration control signal 111-110-101-100-011-010-001-000, which increases the flexibility of the ROC design, so that when calibrating the offset, it can be either automatically calibrated by the ROC or input through the test mode.
  • RocEn calibration enable signal
  • trim value the converted automatic calibration control signal
  • the calibration circuit provided by the embodiment of the present disclosure is for serving the Rx circuit.
  • There are four gears in the Rx circuit to adjust the mismatch namely the 2 gears on the left and the 2 gears on the right of the differential signal.
  • the left side as an example, that is, "11-10-01-00" on the left, and the same on the right, so there are a total of 8 gears.
  • these 8 gears are made into corresponding logical relationships, corresponding to the counting signal "000-001-010-011-100-101-110-111", but this order is not the desired order in the calibration process.
  • the gears on the left are opened from large to small, that is, 11-10-01-00", and the same on the right, then the corresponding 8 gears should be in the order of "111-110-101-100-00-001-010-011", which is conducive to the Rx offset calibration order, and is arranged in order from small to large from the mismatch on the left to the mismatch on the right.
  • FIG15 is a schematic diagram of a control signal generating circuit in an exemplary embodiment of the present disclosure.
  • the control signal generating circuit 1500 may include an inverter 1510, an inverter 1520, an inverter 1530, an inverter 1560, an inverter 1570, a selector 1540, and a selector 1550.
  • the input terminal of the inverter 1510 can be used to receive the third bit Cnt ⁇ 2> in the counting signal, and the output terminal of the inverter 1510 can be used to output the third bit Con ⁇ 2> of the automatic calibration control signal.
  • the input end of the inverter 1520 can be used to receive the second bit Cnt ⁇ 1> in the count signal, and the output end of the inverter 1520 can be used to output the second bit CntN ⁇ 1> in the complementary count signal.
  • the first input end of the selector 1540 can be used to receive the second bit Cnt ⁇ 1> in the count signal, the second input end can be used to receive the second bit CntN ⁇ 1> in the complementary count signal, and the control end can be used to receive the third bit Cnt ⁇ 2> in the count signal, that is, when Cnt ⁇ 2> takes a value of 0, select and output CntN ⁇ 1> and invert it.
  • Con ⁇ 1> is obtained, that is, path 2 is selected, which is equivalent to three inversions of Cnt ⁇ 1>; when Cnt ⁇ 2> takes a value of 1, the output Cnt ⁇ 1> is selected and inverted to obtain Con ⁇ 1>, that is, path 1 is selected, which is equivalent to two inversions of Cnt ⁇ 1>.
  • the input end of the inverter 1560 can be coupled to the output end of the selector 1540, and the output end of the inverter 1560 can be used to output the second bit Con ⁇ 1> in the automatic calibration control signal.
  • the input terminal of the inverter 1530 can be used to receive the first bit Cnt ⁇ 0> in the counting signal, and the inverter 1530 can be used to generate the first bit CntN ⁇ 0> in the complementary counting signal according to the first bit Cnt ⁇ 0> in the counting signal.
  • the first input terminal of the selector 1550 can be used to receive the first bit Cnt ⁇ 0> in the counting signal
  • the second input terminal can be used to receive the first bit CntN ⁇ 0> in the complementary counting signal
  • the control terminal can be used to receive the third bit Cnt ⁇ 2> in the counting signal, that is, when Cnt ⁇ 2> takes a value of 0, the output CntN ⁇ 0> is selected and inverted to obtain Con ⁇ 0>, that is, the selection path 4 is enabled, which is equivalent to the three-time inversion of Cnt ⁇ 0>; when Cnt ⁇ 2> takes a value of 1, the output Cnt ⁇ 0> is selected and inverted to obtain Con ⁇ 0>, that is, the selection path 3 is enabled, which is equivalent to the two-time inversion of Cnt ⁇ 0>.
  • An input terminal of the inverter 1570 may be coupled to an output terminal of the selector 1550 , and an output terminal of the inverter 1570 may be used to output the first bit Con ⁇ 0>
  • the calibration circuit provided by the embodiment of the present disclosure, on the one hand, by adding a converter in the RocCnt circuit, the converter can convert the original sequence of the counter from 0-7 to the sequence of "7-6-5-4-0-1-2-3" output by the converter, and the converted sequence is the trim (adjustment) sequence of the offset, that is, "111-110-101-100-000-001-010-011" shmoo1 times, after being latched by the corresponding latch, it is input into the four-phase Rx circuit respectively.
  • one DqRoc circuit corresponds to four DqPads, which reduces the circuit area of the converter in the DqRoc, and can achieve the benefit of four times the circuit area reduction, making the circuit function simpler and clearer.
  • control signal generating circuit provided in the embodiment of the present disclosure can be implemented by any logic structure, not limited to the example of FIG. 15 above.
  • the circuit structure shown in FIG. 16 below can also be used.
  • the control signal generating circuit 1600 may include an inverter 1610, an inverter 1620, an inverter 1630, a selector 1640, and a selector 1650.
  • the input end of the inverter 1610 can be used to receive the third bit Cnt ⁇ 2> in the counting signal, and the inverter 1610 can be used to generate the third bit Con ⁇ 2> of the automatic calibration control signal according to the third bit Cnt ⁇ 2> in the counting signal.
  • the input end of the inverter 1620 can be used to receive the second bit Cnt ⁇ 1> in the counting signal, and the inverter 1620 can be used to generate the second bit CntN ⁇ 1> in the complementary counting signal according to the second bit Cnt ⁇ 1> in the counting signal.
  • the first input terminal of the selector 1640 can be used to receive the second bit Cnt ⁇ 1> in the count signal
  • the second input terminal can be used to receive the second bit CntN ⁇ 1> in the complementary count signal
  • the control terminal can be used to receive Con ⁇ 2>, that is, when the value of Con ⁇ 2> is 0, the output CntN ⁇ 1> is selected as Con ⁇ 1>, that is, path 2 is selected; when the value of Con ⁇ 2> is 1, the output Cnt ⁇ 1> is selected as Con ⁇ 1>, that is, path 1 is selected.
  • the output terminal of the selector 1640 can be used to output the second bit Con ⁇ 1> in the automatic calibration control signal.
  • the input terminal of the inverter 1630 can be used to receive the first bit Cnt ⁇ 0> in the count signal, and the inverter 1630 can be used to generate the first bit CntN ⁇ 0> in the complementary count signal.
  • the first input terminal of the selector 1650 can be used to receive the first bit Cnt ⁇ 0> in the count signal
  • the second input terminal can be used to receive the first bit CntN ⁇ 0> in the complementary count signal
  • the control terminal can be used to receive the third bit Con ⁇ 2> in the count signal, that is, when Con ⁇ 2> takes a value of 0, the output CntN ⁇ 0> is selected as Con ⁇ 0>, that is, the path 4 is selected; when Con ⁇ 2> takes a value of 1, the output Cnt ⁇ 0> is selected as Con ⁇ 0>, that is, the path 3 is selected.
  • the output terminal of the selector 1650 can be used to output the first bit Con ⁇ 0> in the automatic calibration control signal.
  • the converter output Con ⁇ 2:0> in the RocCnt circuit is used as the input of the signal monitoring circuit in DqRoc instead of the counter output Cnt ⁇ 2:0>.
  • the counter is converted from the original sequence of 0-7 to the sequence of "7-6-5-4-0-1-2-3" and "3-2-1-0-4-5-6-7" output by the converter.
  • the converted sequence is the trim sequence of the offset.
  • the control signal generating circuit 1700 may include an inverter 1711 , a selector 1720 , an inverter 1712 , an inverter 1713 , an inverter 1714 , an inverter 1715 , a selector 1740 , a selector 1750 , a selector 1780 , and a selector 1790 .
  • the input terminal of the inverter 1711 can be used to receive Cnt ⁇ 2>, and the output terminal of the inverter 1711 can be used to output the third bit CntN ⁇ 2> in the complementary count signal.
  • the first input terminal of the selector 1720 can be used to receive Cnt ⁇ 2>, the second input terminal can be used to receive CntN ⁇ 2>, the control terminal can be used to receive Cnt ⁇ 3>, and the output terminal of the selector 1720 can be used to output Con ⁇ 2>.
  • the input terminal of the inverter 1712 can be used to receive Cnt ⁇ 1>, and the output terminal of the inverter 1712 can be used to output CntN ⁇ 1>.
  • the first input terminal of the selector 1740 can be used to receive Cnt ⁇ 1>
  • the second input terminal can be used to receive CntN ⁇ 1>
  • the control terminal can be used to receive Cnt ⁇ 2>
  • the output terminal of the selector 1740 can be used to output the second bit conN ⁇ 1> in the complementary automatic calibration control signal.
  • the input terminal of the inverter 1713 can be coupled to the output terminal of the selector 1740, receive conN ⁇ 1> to generate con ⁇ 1>, and the output terminal of the inverter 1713 can be used to output con ⁇ 1>.
  • the first input terminal of the selector 1780 is used to receive conN ⁇ 1>, the second input terminal is used to receive con ⁇ 1>, and the control terminal is used to receive Cnt ⁇ 3>.
  • the selector 1780 can select the received conN ⁇ 1> or con ⁇ 1> as the second bit Con ⁇ 1> in the final automatic calibration control signal according to Cnt ⁇ 3>, and output Con ⁇ 1> in the final automatic calibration control signal through the output terminal of the selector 1780.
  • the input terminal of the inverter 1714 can be used to receive Cnt ⁇ 0>, and the output terminal of the inverter 17140 can output CntN ⁇ 0>.
  • the first input terminal of the selector 1750 can be used to receive Cnt ⁇ 0>
  • the second input terminal can be used to receive CntN ⁇ 0>
  • the control terminal can be used to receive Cnt ⁇ 2>
  • the output terminal of the selector 1750 can be used to output conN ⁇ 0>.
  • the input terminal of the inverter 1715 can be coupled to the output terminal of the selector 1750, receive conN ⁇ 0> to generate con ⁇ 0>, and the output terminal of the inverter 1715 can be used to output con ⁇ 0>.
  • the first input terminal of the selector 1790 is used to receive conN ⁇ 0>, the second input terminal is used to receive con ⁇ 0>, and the control terminal is used to receive Cnt ⁇ 3>.
  • the selector 1790 can select the received conN ⁇ 0> or con ⁇ 0> as Con ⁇ 0> in the final automatic calibration control signal according to Cnt ⁇ 3>, and output Con ⁇ 0> in the final automatic calibration control signal through the output terminal of the selector 1790.
  • Cnt ⁇ 3> is used to control whether the conversion is performed from 0 to 7 or from 7 to 0.
  • the selector 1580 if the conversion is performed from 0 to 7, when Cnt ⁇ 3> is 0, direct output of Con ⁇ 1> is selected; if the conversion is performed from 7 to 0, when Cnt ⁇ 3> is 1, output of ConN ⁇ 1> is selected.
  • the correspondence between the counting signal and the automatic calibration control signal can be designed according to actual needs.
  • the implementation circuit of each different correspondence can be different, and the same correspondence can also be implemented using different circuits, as long as the converted signal can be directly corresponded to the switch control signal of the calibration module.

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Abstract

一种校准电路，属于集成电路技术领域。该校准电路（100）包括：校准控制电路(110)，用于产生时钟信号(OscClk)和自动校准控制信号(Con)，并用于根据自动校准控制信号(Con)对目标电路(130)的偏移进行自动校准，自动校准控制信号(Con)基于时钟信号(OscClk)产生；校准监测电路(120)，耦接校准控制电路(110)，接收时钟信号(OscClk)和自动校准控制信号(Con)，用于基于时钟信号(OscClk)监测目标电路(130)的输出信号(Din)的变化状态，并在输出信号(Din)发生状态翻转时锁存自动校准控制信号(Con)，将锁存的自动校准控制信号(Con')对应的偏移校准值确定为目标电路(130)的目标偏移校准值。

Description

校准电路
交叉引用
本公开要求于2022年11月7日提交的申请号为202211387529.4名称为“校准电路”的中国发明专利申请的优先权，该中国发明专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种校准电路。
背景技术
实际应用场景中，由于目标电路(例如数据接收电路)中两边的晶体管可能存在失配(mismatch)的情况，从而导致需要采用校准电路对该目标电路的偏移进行校准，但相关技术中的校准电路存在版图面积较大的问题。
发明内容
本公开实施例提供了一种校准电路，该校准电路包括：校准控制电路，用于产生时钟信号和自动校准控制信号，并用于根据所述自动校准控制信号对目标电路的偏移进行自动校准，所述自动校准控制信号基于所述时钟信号产生；校准监测电路，耦接所述校准控制电路，接收所述时钟信号和所述自动校准控制信号，用于基于所述时钟信号监测所述目标电路的输出信号的变化状态，并在所述输出信号发生状态翻转时锁存所述自动校准控制信号，将锁存的所述自动校准控制信号对应的偏移校准值确定为所述目标电路的目标偏移校准值。
附图说明
图1是本公开一示例性实施例中的校准电路的示意图。
图2是本公开一示例性实施例中的校准控制电路的示意图。
图3是本公开另一示例性实施例中的校准电路的示意图。
图4是本公开一示例性实施例中的校准监测子电路的示意图。
图5是本公开另一示例性实施例中的校准监测子电路的示意图。
图6是本公开又一示例性实施例中的校准监测子电路的示意图。
图7是本公开再一示例性实施例中的校准监测子电路的示意图。
图8是本公开再一示例性实施例中的校准监测子电路的示意图。
图9是本公开一示例性实施例中的信号监测电路的示意图。
图10是本公开一示例性实施例中的信号采样电路的示意图。
图11是基于图10所示的信号采样电路的时序图。
图12是本公开一示例性实施例中的目标电路的示意图。
图13是本公开一示例性实施例中的校准模块控制端信号产生电路的示意图。
图14是本公开另一示例性实施例中的校准电路的示意图。
图15是本公开一示例性实施例中的控制信号产生电路的示意图。
图16是本公开另一示例性实施例中的控制信号产生电路的示意图。
图17是本公开又一示例性实施例中的控制信号产生电路的示意图。
具体实施方式
下面结合附图对本公开实施方式提供的校准电路进行举例说明。
图1是本公开一示例性实施例中的校准电路的示意图。
如图1所示，本公开实施例提供的校准电路100可以包括校准控制电路110和校准监测电路120。
校准控制电路110可以用于产生时钟信号OscClk和自动校准控制信号Con，并可以用于根据校准控制电路110输出的自动校准控制信号Con对目标电路130的偏移进行自动校准，自动校准控制信号Con可以基于时钟信号OscClk产生。
本公开实施例中的目标电路是指需要进行偏移校准的电路，例如可以是数据接收电路，但 本公开并不限定于此，例如还可以是ODT(On-Die Termination，DRAM(Dynamic Random Access Memory，动态随机存取存储器)芯片上的终结电阻)电路或其它任意需要进行偏移校准的电路，在下面的实施例中均以待校准的目标电路为数据接收电路进行举例说明。
校准监测电路120可以耦接校准控制电路110，可以接收时钟信号OscClk和自动校准控制信号Con，可以用于基于时钟信号OscClk监测目标电路130的输出信号Din的变化状态，并在输出信号Din发生状态翻转时锁存所述自动校准控制信号Con，将锁存的自动校准控制信号Con(在图1中表示为Con’)对应的偏移校准值确定为目标电路130的目标偏移校准值。
本公开实施例中目标电路130的输出信号Din发生状态翻转(toggle)是指输出信号Din从第一电平状态转换为第二电平状态，或者从第二电平状态转换为第一电平状态，第一电平状态例如可以为高电平，第二电平状态例如可以为低电平，反之也可以，本公开对此不做限定。
本公开实施例提供的校准电路，通过将校准控制电路输出的自动校准控制信号作为校准监测电路的输入，来实现对待校准的目标电路的偏移进行自动校准，不再需要在校准监测电路中设置控制信号产生电路来转换获得输入至目标电路的偏移校准值，从而可以减小校准电路的版图面积。
图2是本公开一示例性实施例中的校准控制电路的示意图。
如图2所示，本公开实施例中的校准控制电路110可以进一步包括时钟产生电路111、计数电路112以及控制信号产生电路113。
时钟产生电路111可以用于产生时钟信号OscClk。本公开实施例中，时钟产生电路111可以采用任意能够实现产生时钟信号OscClk功能的电路，例如下面以时钟产生电路采用晶振(oscillator，简写为Osc)进行举例说明，但本公开并不限定于此。
计数电路112可以耦接时钟产生电路111，可以接收时钟信号OscClk，可以用于根据时钟信号OscClk产生计数信号Cnt，计数信号Cnt可以指示时钟信号OscClk的计数值。
控制信号产生电路113可以耦接计数电路112，可以接收计数信号Cnt，可以用于将计数信号Cnt转换为自动校准控制信号Con。
本公开实施例提供的校准电路，当时钟信号OscClk的计数值不同时，产生的自动校准控制信号Con不同，即自动校准控制信号Con与时钟信号的计数值OscClk一一对应，针对不同的目标电路，可以设计不同的控制信号产生电路实现计数信号与自动校准控制信号之间不同的对应关系，以满足不同目标电路的偏移校准需求。当将该校准控制电路输出的自动校准控制信号输入至校准监测电路时，可以实现对待校准的目标电路的偏移进行自动校准，且不再需要在校准监测电路中设置控制信号产生电路来转换获得输入至目标电路的偏移校准值，可以减小校准电路的版图面积。
在示例性实施例中，校准监测电路可以包括n个校准监测子电路，n可以为大于或等于1的正整数。每个校准监测子电路可以耦接校准控制电路，可以接收时钟信号和自动校准控制信号。
如图3所示，本公开实施例提供的校准电路300可以包括校准控制电路110和校准监测电路，其中校准监测电路可以进一步包括n个校准监测子电路，例如图3中所示的校准监测子电路120-1、校准监测子电路120-2、校准监测子电路120-3、…以及校准监测子电路120-n。校准监测子电路120-1、校准监测子电路120-2、校准监测子电路120-3、…以及校准监测子电路120-n分别耦接校准控制电路110，分别接收校准控制电路110输出的时钟信号OscClk和自动校准控制信号Con，并可以分别基于接收到的时钟信号OscClk监测各个校准监测子电路对应的目标电路的输出信号的变化状态，并在对应的目标电路的输出信号发生状态翻转时锁存对应的自动校准控制信号，例如图3中所示的Con-1’、Con-2’、Con-3’、…或者Con-n’，将锁存的对应的自动校准控制信号Con-1’、Con-2’、Con-3’、…或者Con-n’对应的偏移校准值确定为对应的目标电路130-1、130-2、130-3、…130-n的目标偏移校准值。
本公开实施例中，n的取值可以根据待校准的目标电路的数量来确定的，每个校准监测子电路对应一个待校准的目标电路，在下面的举例说明中均以n＝4进行举例说明，但本公开并不限定于此。
下图14中的RocCnt可以表示1个校准控制电路，DqRoc可以表示校准监测电路中的任意一个校准监测子电路，例如在DCPNA上每一个DqByte中包含八个DqPad，每一个DqPad中都有DqRoc电路，当n＝4时，1个RocCnt中的控制信号产生电路输出的自动校准控制信号可以同时或依次校准4个DqPad中的目标电路，即可同时或依次控制4个DqPad中的DqRoc电路同时或依次进行校准监测，即1个RocCnt中的控制信号产生电路输出的自动校准控制信号可以控制4个DqRoc电路，每4个DqRoc电路可以共用同一个RocCnt中的控制信号产生电路，而 不用在每个DqRoc电路中设置对应目标电路的控制信号产生电路，因此可以节省4个DqRoc电路在DqPad上的面积，而且通过1个RocCnt可以同时或依次完成4个DqRoc中目标电路的校准。一个DqByte中可以有2个RocCnt电路。
但本公开并不限定于此，在其它实施例中，例如n还可以取值为8，此时1个RocCnt可以控制8个DqPad中的DqRoc电路，由此可以进一步降低8个DqRoc电路在DqPad上的面积。n的取值可以在所节省的电路版图面积和校准控制电路的负载(loading)之间进行适当的平衡。
本公开实施例提供的校准电路，通过1个校准控制电路可以同时为n个校准监测子电路提供自动校准控制信号，该自动校准控制信号是对计数电路输出的计数信号进行转换产生的，由此可以实现该校准控制电路同时或依次对n个待校准的目标电路进行偏移的自动校准，一方面可以提高校准效率，降低校准电路的复杂度；另一方面，当n为大于1的正整数时，多个校准监测子电路可以共用同一个校准控制电路，由此可以进一步减小校准电路的版图面积。
在示例性实施例中，每个校准监测子电路均可以包括：信号采样电路，可以分别耦接校准控制电路和目标电路，可以接收时钟信号和目标电路的输出信号，可以用于基于时钟信号对目标电路的输出信号进行采样，产生采样脉冲信号；信号监测电路，可以分别耦接校准控制电路和信号采样电路，可以接收自动校准控制信号和采样脉冲信号，可以用于根据采样脉冲信号监测目标电路的输出信号的变化状态，并在输出信号发生状态翻转时输出自动校准控制信号(需要说明的是，这里的自动校准控制信号是指对应的校准监测子电路当前从校准控制电路接收到的自动校准控制信号，自动校准控制信号是会随着时钟信号进行变化的)；锁存电路，可以耦接信号监测电路，可以用于锁存信号监测电路输出的自动校准控制信号，将锁存的自动校准控制信号对应的偏移校准值确定为目标电路的目标偏移校准值。
图4中以图3实施例的校准监测子电路120-1进行举例说明，其它的校准监测子电路可以参照图4实施例中的校准监测子电路120-1。校准监测子电路120-1可以包括信号采样电路120-11、信号监测电路120-12以及锁存电路120-13。
其中，信号采样电路120-11可以分别耦接目标电路130(例如图3中的目标电路130-1)和校准控制电路110，并分别接收目标电路130的输出信号Din和校准控制电路140输出的时钟信号OscClk，信号采样电路120-11可以用于根据接收到的时钟信号OscClk对目标电路130的输出信号Din进行采样，产生采样脉冲信号Pul。
可以理解的是，目标电路130接收控制信号产生电路113输出的随时钟信号OscClk变化的自动校准控制信号Con，目标电路130在不同时刻对应不同的自动校准控制信号Con，因此目标电路130的输出信号Din会在自动校准控制信号Con达到校准要求时发生变化，即输出信号Din会随时钟信号OscClk发生变化，根据时钟信号OscClk采样到的目标电路130的输出信号Din也会在自动校准控制信号Con达到校准要求时发生变化。
信号监测电路120-12可以分别耦接校准控制电路110和信号采样电路120-11，可以分别接收校准控制电路110输出的自动校准控制信号Con和信号采样电路120-11输出的采样脉冲信号Pul，信号监测电路120-12可以用于根据采样脉冲信号Pul监测目标电路130的输出信号Din的变化状态，并在目标电路130的输出信号Din发生状态翻转时输出校准控制电路110的自动校准控制信号Con。
锁存电路120-13可以耦接信号监测电路120-12，锁存电路120-1可以用于锁存信号监测电路120-12输出的自动校准控制信号Con(即图4中所示的Con-1’，Con-1’为目标电路130的输出信号Din发生状态翻转时接收的自动校准控制信号)，将锁存的自动校准控制信号Con-1’对应的偏移校准值确定为目标电路130的目标偏移校准值。
本公开实施例提供的校准电路，每个校准监测子电路中的信号监测电路均采用校准控制电路输出的自动校准控制信号，由此使得校准监测子电路中的锁存电路可以锁存在目标电路的输出信号发生状态翻转时的自动校准控制信号，而不再需要在信号监测电路和锁存电路之间设置控制信号产生电路(因为已在校准控制电路中完成用于校准目标电路的自动校准控制信号的生成，校准监测子电路可直接锁存，无需进行数据转换)，当1个校准监测电路中包括多个(2个或2个以上)校准监测子电路时，可以减小校准电路的版图面积。
在示例性实施例中，所述校准控制电路还可以用于根据自动校准控制信号Con对每个目标电路的偏移进行m次自动校准，m可以为大于或等于1的正整数。
在示例性实施例中，当自动校准控制信号Con对应的偏移校准值从大到小变化时，所述信号监测电路输出使得输出信号Din从第一电平状态转换为第二电平状态的自动校准控制信号Con’。当自动校准控制信号Con对应的偏移校准值从小到大变化时，所述信号监测电路输出使 得输出信号从第二电平状态转换为第一电平状态的自动校准控制信号Con’。
本公开实施例中，将校准控制电路对每个目标电路的偏移进行1次自动校准(即利用所有偏移校准值对目标电路进行一次校准)称之为1次shmoo，校准控制电路可以对每个目标电路的偏移进行1次shmoo、2次shmoo或者多次(2次以上)shmoo，每次shmoo时的自动校准控制信号可以都是一致的顺序，例如按照对应的偏移校准值从大到小或从小到大的变化，或者也可以是不一致的顺序，例如按照对应的偏移校准值从大到小和从小到大的变化都有。
在示例性实施例中，每个校准监测子电路还可以包括：第一运算电路，可以分别耦接信号监测电路和锁存电路，可以用于对m次自动校准中信号监测电路输出的m个自动校准控制信号计算平均值，并将平均值输出至锁存电路进行锁存。
本公开实施例中，第一运算电路可以采用任意能够实现对m次自动校准中信号监测电路输出的m个自动校准控制信号求平均值功能的电路，例如第一运算电路中可以包括全加器，但本公开并不限定于此，在下面的实施例中以全加器进行举例说明。
例如，该全加器可以对上述信号监测电路输出的使得输出信号Din从第一电平状态转换为第二电平状态的自动校准控制信号Con’，和/或信号监测电路输出的使得输出信号从第二电平状态转换为第一电平状态的自动校准控制信号Con’(共m个自动校准控制信号Con’)求平均值，将该平均值锁存至锁存电路中。
图5中还是以上述图3实施例的校准监测子电路120-1进行举例说明，其它的校准监测子电路可以参照图5实施例中的校准监测子电路120-1。在图5实施例中，校准监测子电路120-1可以包括信号采样电路120-11、信号监测电路120-12、第一运算电路120-14以及锁存电路120-13。
其中，信号采样电路120-11可以分别耦接目标电路130和校准控制电路110，并分别接收目标电路130的输出信号Din和校准控制电路110输出的时钟信号OscClk，信号采样电路120-11可以用于根据接收到的时钟信号OscClk对目标电路130的输出信号Din进行采样，产生采样脉冲信号Pul。
信号监测电路120-12可以分别耦接校准控制电路110和信号采样电路120-11，可以分别接收校准控制电路110输出的自动校准控制信号Con和信号采样电路120-11输出的采样脉冲信号Pul，信号监测电路120-12可以用于根据采样脉冲信号Pul监测目标电路130的输出信号Din的变化状态，并在目标电路130的输出信号Din发生状态翻转时输出校准控制电路110的自动校准控制信号Con(图5中表示为Con-1)。
第一运算电路120-14可以分别耦接信号监测电路120-12和锁存电路120-13，接收信号监测电路120-12输出的自动校准控制信号Con-1，可以用于对接收到的m个所述自动校准控制信号Con-1计算平均值Con-1’，并将所述平均值Con-1’输出至锁存电路120-13进行锁存，将锁存的自动校准控制信号Con-1’对应的偏移校准值确定为目标电路130的目标偏移校准值。
可以理解的是，当m＝1时，即进行1次shmoo时可以无需全加器，直接锁存在输出信号发生状态翻转时的自动校准控制信号；m的值越大，校准次数越多，获得目标偏移校准值也越准确，但第一运算电路占用的面积和校准消耗的时间也越大。
本公开实施例提供的校准电路，校准控制电路还可以根据自动校准控制信号对每个目标电路的偏移进行m次自动校准，由此使得每个校准监测子电路可以接收到m个自动校准控制信号，每个校准监测子电路可以通过增设第一运算电路来实现对接收到的m个自动校准控制信号计算平均值，并将平均值输出至锁存电路进行锁存，由此可以进一步提高校准的准确性。
在示例性实施例中，每个所述校准监测子电路还可以包括：第二运算电路，可以分别耦接信号监测电路和锁存电路，可以用于从m次自动校准中信号监测电路输出的m个自动校准控制信号中选择出现频次最高的自动校准控制信号，输出至锁存电路进行锁存。
图6中还是以上述图3实施例的校准监测子电路120-1进行举例说明，其它的校准监测子电路可以参照图6实施例中的校准监测子电路120-1。在图6实施例中，校准监测子电路120-1可以包括信号采样电路120-11、信号监测电路120-12、第二运算电路120-15以及锁存电路120-13。
其中，信号采样电路120-11可以分别耦接目标电路130和校准控制电路110，并分别接收目标电路130的输出信号Din和校准控制电路110输出的时钟信号OscClk，信号采样电路120-11可以用于根据接收到的时钟信号OscClk对目标电路130的输出信号Din进行采样，产生采样脉冲信号Pul。
信号监测电路120-12可以分别耦接校准控制电路110和信号采样电路120-11，可以分别接 收校准控制电路110输出的自动校准控制信号Con和信号采样电路120-11输出的采样脉冲信号Pul，信号监测电路120-12可以用于根据采样脉冲信号Pul监测目标电路130的输出信号Din的变化状态，并在目标电路130的输出信号Din发生状态翻转时输出校准控制电路110的自动校准控制信号Con(图6中表示为Con-1)。
第二运算电路120-15可以分别耦接信号监测电路120-12和锁存电路120-13，接收信号监测电路120-12输出的自动校准控制信号Con-1，可以用于从接收到的m个所述自动校准控制信号Con-1中选择出现频次最高的自动校准控制信号Con-1’，输出至所述锁存电路进行锁存，将锁存的自动校准控制信号Con-1’对应的偏移校准值确定为目标电路130的目标偏移校准值。
本公开实施例提供的校准电路，校准控制电路还可以根据自动校准控制信号对每个目标电路的偏移进行m次自动校准，由此使得每个校准监测子电路可以接收到m个自动校准控制信号，每个校准监测子电路可以通过增设第二运算电路，来实现从接收到的m个自动校准控制信号选择出现频次最高的自动校准控制信号锁存至锁存电路，由此可以进一步提高校准的准确性。
在示例性实施例中，目标电路可以为数据接收电路，输出信号可以包括第一相位输出信号、第二相位输出信号、第三相位输出信号和第四相位输出信号。每个校准监测子电路还可以包括：选择电路，可以分别耦接目标电路和信号采样电路，可以接收第一相位输出信号、第二相位输出信号、第三相位输出信号和第四相位输出信号，可以用于依次选择第一相位输出信号、第二相位输出信号、第三相位输出信号或第四相位输出信号之一发送至信号采样电路，以依次针对每个相位输出信号完成目标电路的偏移校准，并锁存每个相位输出信号对应的目标偏移校准值。
图7中还是以图3实施例的校准监测子电路120-1进行举例说明，其它的校准监测子电路可以参照图7实施例中的校准监测子电路120-1。如图7所示，校准监测子电路120-1可以包括选择电路120-16、信号采样电路120-11、信号监测电路120-12以及锁存电路120-13。
其中，选择电路120-16可以分别耦接目标电路130和信号采样电路120-11，这里假设目标电路130为数据接收电路，该数据接收电路可以分别输出第一相位输出信号DinOr、第二相位输出信号DinOf、第三相位输出信号DinEr和第四相位输出信号DinEf。选择电路120-16分别接收数据接收电路输出的第一相位输出信号DinOr、第二相位输出信号DinOf、第三相位输出信号DinEr和第四相位输出信号DinEf，并依次从第一相位输出信号DinOr、第二相位输出信号DinOf、第三相位输出信号DinEr、第四相位输出信号DinEf中选择其中的一个相位输出信号作为目标电路130在相应时刻输入至信号采样电路120-11的输出信号Din，例如在第一时刻t1选择DinOr作为Din输入至信号采样电路120-11，在第二时刻t2选择DinOf作为Din输入至信号采样电路120-11，在第三时刻t3选择DinEr作为Din输入至信号采样电路120-11，在第四时刻t4选择DinEf作为Din输入至信号采样电路120-11，在第五时刻t5选择DinOr作为Din输入至信号采样电路120-11，在第六时刻t6选择DinOf作为Din输入至信号采样电路120-11，在第七时刻t7选择DinEr作为Din输入至信号采样电路120-11，在第八时刻t8选择DinEf作为Din输入至信号采样电路120-11，……，依序循环执行。
图7实施例中关于信号采样电路120-11、信号监测电路120-12和锁存电路120-13的描述可以参照上述其它实施例。
本公开实施例提供的校准电路，待校准的1个目标电路可以输出4个具有不同相位的相位输出信号，通过在每个校准监测子电路中增设选择电路，可以实现依次对该目标电路输出的4个相位输出信号进行自动校准，由此可以简化校准过程，提高校准效率。
在示例性实施例中，锁存电路可以包括：第一锁存电路，可以用于锁存第一相位输出信号对应的目标偏移校准值；第二锁存电路，可以用于锁存第二相位输出信号对应的目标偏移校准值；第三锁存电路，可以用于锁存第三相位输出信号对应的目标偏移校准值；第四锁存电路，可以用于锁存第四相位输出信号对应的目标偏移校准值。
图8中还是以图7实施例的校准监测子电路120-1进行举例说明，其它的校准监测子电路可以参照图8实施例中的校准监测子电路120-1。如图8所示，在图7实施例的基础上，当校准监测子电路120-1进一步还包括选择电路120-16，且目标电路130为数据接收电路，该数据接收电路可以分别输出第一相位输出信号DinOr、第二相位输出信号DinOf、第三相位输出信号DinEr和第四相位输出信号DinEf时，锁存电路可以包括第一锁存电路120-131、第二锁存电路120-132、第三锁存电路120-133和第四锁存电路120-134。
其中，第一锁存电路120-131可以用于锁存第一相位输出信号DinOr发生状态翻转时锁存的对应的自动校准控制信号Con-11’对应的所述目标偏移校准值。第二锁存电路120-132可以用于锁存第二相位输出信号DinOf发生状态翻转时锁存的对应的自动校准控制信号Con-12’对应 的所述目标偏移校准值。第三锁存电路120-133可以用于锁存第三相位输出信号DinEr发生状态翻转时锁存的对应的自动校准控制信号Con-13’对应的所述目标偏移校准值。第四锁存电路120-134可以用于锁存第四相位输出信号DinEf发生状态翻转时锁存的对应的自动校准控制信号Con-14’对应的所述目标偏移校准值。
可以理解的是，图7和图8实施例中虽然以目标电路输出4个相位输出信号进行举例说明，但本公开并不限定于此，目标电路可以输出k个相位输出信号，k可以为大于或等于1的正整数，当目标电路输出k个相位输出信号时，选择电路可以依次从这k个相位输出信号中选择一个相位输出信号输入至信号采样电路，且锁存电路对应的可以包括第一锁存电路至第k锁存电路，第k个锁存电路用于锁存第k个相位输出信号发生状态翻转时锁存的对应的自动校准控制信号对应的目标偏移校准值。
本公开实施例提供的校准电路，当待校准的1个目标电路可以输出k个具有不同相位的相位输出信号时，通过在每个校准监测子电路中的锁存电路中设置对应的第一至第k锁存电路，以用于分别锁存对应的相位输出信号发生状态翻转时的自动校准控制信号，从而能够实现对该目标电路的k个不同相位的相位输出信号的偏移的自动校准，由此可以简化校准过程，提高校准效率。
在示例性实施例中，自动校准控制信号可以为N位二进制数据，N可以为大于或等于1的正整数。信号监测电路可以包括：第一触发器至第N触发器，其中：第i触发器，可以耦接校准控制电路，可以接收自动校准控制信号中的第i位和采样脉冲信号，可以用于根据自动校准控制信号中的第i位和采样脉冲信号确定使得输出信号发生状态翻转的所述自动校准控制信号，i为大于或等于1且小于或等于N的正整数。
本公开实施例中，N的取值可以根据shmoo中目标电路对应的自动校准控制信号的取值数量或者目标电路对应可调的偏移校准值的数量来设置，例如当shmoo中自动校准控制信号的取值数量为8个，则N可以取值为3；再例如当shmoo中自动校准控制信号的取值数量为16个，则N可以取值为4；等等，其它取值以此类推。在下面的举例说明中以N＝3进行举例说明，但本公开并不限定于此。
图9实施例中以校准监测子电路120-1中的信号监测电路120-12进行举例说明，其它校准监测子电路中的信号监测电路可以参照图9实施例。如图9所示，信号监测电路120-12可以包括第一触发器D1、第二触发器D2、…以及第N触发器DN，且校准控制电路110输出的自动校准控制信号包括N位二进制数据，分别表示为Con<0>，Con<1>，…，Con<N-1>。
其中，第一触发器D1可以分别耦接校准控制电路110和信号采样电路，可以分别接收校准控制电路110输出的自动校准控制信号中的第1位Con<0>和信号采样电路120-11输出的采样脉冲信号Pul，第一触发器D1可以用于根据Con<0>和Pul确定使得目标电路的输出信号Din发生状态翻转的自动校准控制信号中的第1位Con<0>’。具体地，目标电路的输出信号Din发生状态翻转时，采样到的Pul信号也会发生翻转，即Pul信号产生电平跳变沿，触发第一触发器D1输出当前的自动校准控制信号的数据。
第二触发器D2可以分别耦接校准控制电路110和信号采样电路，可以分别接收校准控制电路110输出的自动校准控制信号中的第2位Con<1>和信号采样电路输出的采样脉冲信号Pul，第一触发器D2可以用于根据Con<1>和Pul确定使得目标电路的输出信号Din发生状态翻转的自动校准控制信号中的第2位Con<1>’。
第N触发器DN可以分别耦接校准控制电路110和信号采样电路，可以分别接收校准控制电路110输出的自动校准控制信号中的第N位Con<N-1>和信号采样电路输出的采样脉冲信号Pul，第一触发器D1可以用于根据Con<N-1>和Pul确定使得目标电路的输出信号Din发生状态翻转的自动校准控制信号中的第N位Con<N-1>’。
需要说明的是，本公开实施例中的第一至第N触发器可以采用任意能够实现确定目标电路的输出信号发生状态翻转的自动校准控制信号功能的触发器，本公开对触发器的类型不做限定，在下面的实施例中均以D触发器进行举例说明，但本公开并不限定于此。
本公开实施例提供的校准电路，当自动校准控制信号用N位二进制数据表示时，每个校准监测子电路中的信号监测电路可以包括N个触发器来，以此来确定使得对应的目标电路的输出信号发生状态翻转的自动校准控制信号中的第1位至第N位。
在示例性实施例中，信号采样电路可以包括：第N+1触发器，可以接收输出信号和时钟信号，可以用于根据时钟信号对输出信号进行采样产生第一采样数据，N可以为大于或等于1的正整数；反相器，可以接收时钟信号，可以用于根据时钟信号产生互补时钟信号；第N+2触发 器，可以耦接反相器，可以接收输出信号和互补时钟信号，可以用于根据互补时钟信号对输出信号进行采样产生第二采样数据；异或门，可以分别耦接第N+1触发器和第N+2触发器，可以接收第一采样数据和第二采样数据，可以用于根据第一采样数据和第二采样数据产生采样脉冲信号。
图10实施例中以校准监测子电路120-1中的信号采样电路120-11进行举例说明，其它校准监测子电路中的信号采样电路可以参照图10实施例。如图10所示，信号采样电路120-11可以包括反相器120-111、第N+1触发器D(N+1)、第N+2触发器D(N+2)以及异或门120-112。
其中，第N+1触发器D(N+1)可以接收目标电路的输出信号Din和时钟信号OscClk，第N+1触发器D(N+1)可以用于根据时钟信号OscClk对目标电路的输出信号Din进行采样产生第一采样数据Samp1。反相器120-111可以接收时钟信号OscClk，可以用于根据时钟信号OscClk产生互补时钟信号/OscClk，即时钟信号OscClk和互补时钟信号/OscClk在相同时刻的相位是相反的。第N+2触发器D(N+2)可以耦接反相器120-111，可以接收目标电路的输出信号Din和互补时钟信号/OscClk，可以用于根据互补时钟信号/OscClk对目标电路的输出信号Din进行采样产生第二采样数据Samp2。异或门120-112可以分别耦接第N+1触发器D(N+1)和第N+2触发器D(N+2)，可以接收第N+1触发器D(N+1)输出的第一采样数据Samp1和第N+2触发器D(N+2)输出的第二采样数据Samp2，异或门120-112可以用于根据第一采样数据Samp1和第二采样数据Samp2产生采样脉冲信号Pul。
图11是基于图10所示的信号采样电路的时序图。如图11所示，Din、OscClk、/OscClk、Samp1、Samp2和Pul信号的横坐标均为时间t，纵坐标均为电压值，OscClk和/OscClk在相同时刻的相位是相反的。当在某个OscClk的上升沿检测到Din从低电平跳变为高电平，则Samp1信号在该OscClk的该上升沿的下一个下降沿从低电平跳变为高电平，Samp2信号在/OscClk的下一个下降沿从低电平跳变为高电平，在Samp1为高电平，Samp2为低电平的期间，产生高电平的Pul信号。
本公开实施例提供的校准电路，每个校准监测子电路中的信号采样电路可以包括反相器、第N+1触发器、第N+2触发器以及异或门，由此可以实现产生采样脉冲信号的功能，该采样脉冲信号可以用于监测该校准监测子电路对应的目标电路的输出信号的变化状态，以此实现在该目标电路的输出信号发生状态翻转时向锁存电路输出自动校准控制信号，从而能够准确的对该目标电路的偏移进行自动校准。
在示例性实施例中，目标电路可以根据自动校准控制信号控制校准模块中对应校准器件的开关。
本公开实施例中的目标电路可以根据锁存在锁存电路中的自动校准控制信号控制校准模块中对应的校准器件的开关，该校准模块可以设置在目标电路中，也可以设置在校准测试电路中，本公开不对校准模块的设置位置进行限定，在下面的实施例中，均以校准模块设置在目标电路中进行举例说明，但本公开并不限定于此。
在具有DRAM等的半导体设备中，输入缓冲器(Input Buffer，IB，包括在数据接收电路中)用于将输入信号的电平与参考电平进行比较，判断输入信号的电平是高于还是低于参考电平。然而，器件失配会影响输入缓冲器的比较结果。本公开实施例提供的校准电路可以用于补偿器件在差分对上的失配。
图12实施例中以目标电路包括4个如图12所示的数据接收电路(这4个Rx电路可以分别用于输出4个相位输出信号DinOr、DinOf、DinEr和DinEf)、且将校准模块设置在该目标电路中进行举例说明，但本公开并不限定于此。参照图12来说明输入缓冲器的偏移校准的原理。如图12所示，输入缓冲器包括分别接收参考电压信号Vref和输入信号DQ_IN的开关元件P22、P25及校准模块中对应校准器件的开关，该校准模块中对应校准器件的开关可以包括多个补偿开关元件，例如图12中所示的晶体管P23～P24以及晶体管P26～P27，晶体管P11的第一端耦接第一电源电压VDD，第二端分别耦接P25和P22的第一端，控制端输入有数据采样时钟信号CLK，且图12中的Rx电路输出的Din可以是DinOr、DinOf、DinEr和DinEf中的任意一个，DinN表示Din的反相信号。P22的控制端接收Vref，第二端分别耦接晶体管P31、P32和P33的控制端以及P13的第一端。P25的控制端接收DQ_IN，第二端分别耦接晶体管P34、P35和P36的控制端以及P12的第一端。P12的控制端耦接P13的控制端，用于接收CLK；P12、P13、P31、P32和P33、P34、P35和P36的第二端均用于接收第二电源电压VSS。P23的第一端和P24的第一端均耦接P31的第一端，以用于输出DinN。P23、P24、P26和P27的控制端分别用于接收控制端信号offset<3:0>(offset<3>～offset<0>)。P23的第二端耦接P32的第一端，P24的 第二端耦接P33的第一端。P27的第二端耦接P35的第一端，P26的第二端耦接P34的第一端。
如图12所示，当开始校准时，首先在Rx电路中设置输入信号DQ_IN＝Vref，使之进入校准模式。如果开关元件P22的阈值电压与左侧的开关元件P25的阈值电压不相等，则可根据自动校准控制信号控制补偿开关元件P23～P24/P26～P27进行失配校准。
例如，如果开关元件P25的阈值电压高于右侧的开关元件P22，则利用锁存的自动校准控制信号Con<2:0>(Con<2>～Con<0>)来控制生成4个补偿开关元件的控制端信号offset<3:0>(offset<3>～offset<0>)，以此控制关闭补偿开关元件P23～P24，并打开补偿开关元件P26～P27，以获得更多的电流用于补偿开关元件P25。
再比如，如果开关元件P22的阈值电压高于左侧的开关元件P25，则利用锁存的自动校准控制信号Con<2:0>来控制生成4个补偿开关元件的控制端信号offset<3:0>，以此控制打开补偿开关元件P23～P24，并关闭补偿开关元件P26～P27，以获得更多的电流用于补偿开关元件P22。
图12中所示的补偿开关元件组成的电路可以用于校准数据接收电路，因此可以称之为ROC(Rx Offset Calibration，接收偏移校准)模块，ROC模块可以是存储器例如LPDDR5X中校准IB(Input Buffer，输入缓冲器)中比较器两边管子mismatch(失配)的电路，可以通过Osc(晶振)产生一个时钟信号(可以表示为OscClk)，然后按照从左侧mismatch的极端值到右侧mismatch的极端值的顺序去校准IB，当IB的数据发生翻转时，表明此时比较器的两边相匹配。当锁存电路监测到IB出来的值翻转时，则将用于校准的自动校准控制信号对应的值锁存，作为校准的结果。
本公开实施例中，输出信号发生toggle(例如在两种状态之间切换，转换)说明offset(偏移)的mismatch逐渐达到平衡。假如说依次调整自动校准控制信号，在Con<2:0>为“110”时输出信号仍保持“0(表示低电平)”未发生改变，“110”的状态对应的补偿开关元件的控制端信号offset<3:0>为“0010”，也就是左侧的两个补偿开关元件不打开，打开右侧一支相对较大的晶体管例如P24，而在自动控制信号Con<2:0>变为“101”时，输出信号出现toggle，“101”的状态对应的补偿开关元件的控制端信号offset<3:0>为“0001”，也就是左侧的两个补偿开关元件不打开，打开右侧一支相对较小的晶体管例如P23，这个时候输出信号从“0(表示低电平)”变到“1(表示高电平)”，则说明这个时候晶体管P22和P25才match。差分管由于工艺的原因会导致mismatch，高速状态下这个效果会变得比较明显，因此，需要通过校准模块对其进行校准，校准模块是通过在晶体管P22和P25的左右两侧分别增设晶体管P23～P24/P26～P27来把这个失配校准回来。
如果目标电路在校准模式下能够正确翻转(即DQ_IN(输入)端和VREFDQ(参考电压)端比较后输出的data(数据，即图示中的Din)能够翻转)，即表示输入端和参考电压端差异很小也能够识别出来不同，灵敏度高，则把此时对应的自动校准控制信号(可以用code表示)锁存住。即如果输出数据Din始终是0或者1，那就不会有翻转，此时需要继续调整code继续进行校准，直至输出数据Din发生翻转，那么此时校准就完成了，把code锁住即可。
需要说明的是，本公开实施例提供的目标电路不限于图12的举例说明，例如在其它实施例中，可以在图12中所示的各个开关元件的漏极增加电阻和/或电容等器件，调整每一个调整晶体管所在通路的电流，进而设置偏移校准的精度和调整范围。此外，还可以将图12中的晶体管P32-P35去除，同时将晶体管P23-P24/P26-P27均耦接至接地端VSS。
本公开实施例提供的校准电路，能够用于补偿比较器的offset(偏移)，当比较器的两侧的晶体管存在阈值电压偏移时，可以通过锁存的code来调整，使得比较器输出的data能够正确翻转，即使得DQ_IN和VREFDQ的比较结果能够正确，DQ_IN大于VREFDQ时输出的data准确翻转为1，DQ_IN小于VREFDQ时输出的data准确翻转为0。
图13是本公开一示例性实施例中的根据自动校准控制信号产生校准模块的控制端信号的电路示意图。如图13所示，可以包括反相器1310、选择器1320、选择器1330、选择器1340、反相器1350、或非门1360、或非门1370、或非门1380以及或非门1390。
其中，反相器1310的输入端可以用于接收选择信号sel，反相器1310的输出端分别耦接选择器1320至1340的选择输入端，以用于帮助选择器1320从两个输入端分别输入的Default<2>和Con<2>中选择一个作为第三校准信号AdjIbTrip<2>，帮助选择器1330从两个输入端分别输入的Default<1>和Con<1>中选择一个作为第二校准信号AdjIbTrip<1>，帮助选择器1340从两个输入端分别输入的Default<0>和Con<0>中选择一个作为第一校准信号AdjIbTrip<0>。
选择器1320的输出端分别耦接反相器1350的输入端和或非门1380的第二输入端以及或非门1390的第一输入端，反相器1350的输出端分别耦接或非门1360的第二输入端和或非门 1370的第一输入端。选择器1330的输出端分别耦接或非门1360的第一输入端和或非门1380的第一输入端。选择器1340的输出端分别耦接或非门1370的第二输入端和或非门1390的第二输入端。或非门1360至1390的输出端分别用于输出offset<3>～offset<0>。
下表1以选择Con<2:0>作为校准信号AdjIbTrip<2:0>为例，说明Con<2:0>和offset<3:0>之间的转换关系。在下表1中，用“1”表示“打开”，用“0”表示“关闭”，则采用锁存的自动校准控制信号Con<2:0>来产生补偿开关元件P23～P24和P26～P27的控制端信号可以用下表1表示：
表1
例如，当打开补偿开关元件P24，同时关闭补偿开关元件P23、P26和P27，即offset<3:0>取值为“0100”，对应的Con<2:0>为“001”时P22和P25匹配(match)，那么此时输出信号Din就会toggle，锁存电路可以把这个值“001”记录下来并送到对应的目标电路的Rx电路中，以对该目标电路的Rx电路的偏移进行自动校准，此时offset<3:0>的取值“0100”可以称之为锁存的自动校准控制信号对应的偏移校准值。
图14是本公开另一示例性实施例中的校准电路的示意图。图14实施例中以上述第一触发器至第N触发器均为D触发器，且第N+1触发器和第N+2触发器也均为D触发器，时钟产生电路采用Osc，计数电路采用计数器，控制信号产生电路采用转换器，目标电路中设置有校准模块，同时该目标电路的4个Rx电路分别输出4个相位输出信号DinOr、DinOf、DinEr和DinEf，锁存电路包括四个锁存器，此外信号监测电路中包括的第一运算电路中包括全加器，自动校准控制信号包括3位二进制数据(即N＝3)进行举例说明，但本公开并不限定于此。
可以理解的是，计数器的位数、转换器输出的位数、自动校准控制信号的位数、以及锁存器的个数都是对应的，都可以是N个，可以根据需要去设计，当需要控制的校准元器件较多，校准精度要求较高时，可以对应设置更多位。
本公开实施例中，4个相位输出信号DinOr、DinOf、DinEr和DinEf是目标电路(这里以Rx电路举例说明)输出的4个不同相位的输出信号，这4个不同相位的输出信号失配的条件可能是不一样的，因此，在本公开实施例中可以通过校准控制电路RocCnt来分别对这4个不同相位的输出信号进行校准，对应的可以采用4个锁存器去锁住对应的自动校准控制信号。当目标电路为其它类型的电路时，输出信号可能是1个或多个，本公开对此不做限定。
如图14所示，校准电路1400可以包括校准控制电路1410和校准监测电路1420，校准控制电路1410可以表示为RocCnt，校准监测电路1420可以表示为DqRoc。
校准控制电路1410可以包括Osc 1411、计数器(Counter)1412和转换器(Converter)1413。Osc 1411可以用于输出时钟信号OscClk。计数器1412可以耦接Osc 1411，接收Osc 1411输出的时钟信号OscClk，以产生计数信号Cnt<2:0>(即Cnt<2>～Cnt<0>)，计数信号Cnt<2:0>指示时钟信号OscClk的计数值。转换器1413可以耦接计数器1412，接收计数器1412输出的计数信号Cnt<2:0>，将其转换为自动校准控制信号Con<2:0>(即Con<2>～Con<0>)。
可选的，校准控制电路1410还可以包括选择器1414，选择器1414可以包括两个输入端，其中一个输入端可以用于接收Default<2:0>，另一个输入端可以用于接收转换器1413输出的自动校准控制信号Con<2:0>。选择器1414可以用于从接收到的Default<2:0>和自动校准控制信号Con<2:0>中选择一个作为AdjIbTrip<2:0>，将AdjIbTrip<2:0>输入至目标电路1430的校准模块1431，以对目标电路1430的偏移进行校准。
RocCnt电路中的Default<2:0>信号可以是由DRAM的fuse(熔丝)烧写设置或者通过模式寄存器中的参数进行设置，如果说可以把ROC整体理解为Rx offset的自动校准过程，那么这 个Default<2:0>就是无自动校准过程时的默认参数设置，不同的是ROC自动校准过程4个相位(DinOr、DinOf、DinEr和DinEf)对应的Rx电路不通，产生的Con<2:0>也可能是不同的，而且经过自动校准设置的偏移校准值准确度更高，但如果通过Default<2:0>设置的偏移校准值是提前设置好的或者控制器通过模式寄存器进行配置的，其未经过自动校准，准确度不高。Default<2:0>的取值范围是0-7，通过烧写或者模式寄存器中的参数进行设置，可以认为是一种手动干预，即本公开实施例提供的校准电路可以同时实现手动配置(或者默认配置)和自动校准，当选择器1414选择Default<2:0>作为输入至目标电路1430的校准模块1431的AdjIbTrip<2:0>信号时，采用的是手动校准模式或者默认校准模式；当选择器1414选择Con<2:0>作为输入至目标电路1430的校准模块1431的AdjIbTrip<2:0>信号时，采用的是自动校准模式。
AdjIbTrip<2:0>信号表示进入Rx offset中的信号，也就是说ROC的整个过程都是靠着shmoo AdjIbTrip<2:0>信号来实现自动校准Rx offset，因此选择自动校准时选择转换器1413的输出作为选择器1414的输入来shmoo offset，才能知道当前目标电路1430的输出信号Din对应的偏移校准值(即档位)是什么。
校准监测电路1420可以包括选择电路(即Mux 1421)、信号采样电路1422、信号监测电路1423和锁存电路。
Mux 1421可以耦接目标电路1430，目标电路1430可以输出4个相位输出信号DinOr、DinOf、DinEr和DinEf，这4个相位输出信号DinOr、DinOf、DinEr和DinEf分别输入至Mux1421。Mux 1421可以依次选择4个相位输出信号DinOr、DinOf、DinEr和DinEf中的一个相位输出信号作为目标电路1430的输出信号Din，即依次选择4个相位输出信号DinOr、DinOf、DinEr和DinEf对目标电路中不同的Rx电路进行校准。
信号采样电路1422可以包括D触发器14221(第四触发器)、D触发器14222(第五触发器)、反相器和异或门14223。反相器耦接Osc 1411，接收时钟信号OscClk，以产生互补时钟信号/OscClk，时钟信号OscClk和互补时钟信号/OscClk互为反相信号。D触发器14221的数据输入端D和D触发器14222的数据输入端D分别耦接Mux 1421，接收Mux 1421输出的输出信号Din，D触发器14221的时钟输入端耦接Osc 1411，接收Osc 1411输出的时钟信号OscClk，D触发器14222的时钟输入端耦接反相器，接收互补时钟信号/OscClk。D触发器14221基于时钟信号OscClk对输出信号Din进行采样，产生第一采样数据Samp1，并通过D触发器14221的数据输出端Q输出该第一采样数据Samp1。D触发器14222基于互补时钟信号/OscClk对输出信号Din进行采样，产生第二采样数据Samp2，并通过D触发器14222的数据输出端Q输出该第二采样数据Samp2。异或门14223的两个输入端分别耦接D触发器14221的数据输出端Q和D触发器14222的数据输出端Q，以接收第一采样数据Samp1和第二采样数据Samp2，并根据第一采样数据Samp1和第二采样数据Samp2生成采样脉冲信号Pul，即在输出信号Din出现状态翻转时，信号采样电路1422输出一个采样脉冲信号Pul。
在示例性实施例中，信号监测电路还可以用于对每次自动校准过程中目标电路的输出信号的变化状态进行监测，并在每次输出信号发生状态翻转时输出对应的自动校准控制信号。
信号监测电路1423可以包括D触发器14231(即第一触发器)、D触发器14232(即第二触发器)和D触发器14233(即第三触发器)。D触发器14231的数据输入端D、D触发器14232的数据输入端D和D触发器14233的数据输入端D分别耦接校准控制电路1410中的转换器1413，以分别接收转换器1413输出的自动校准控制信号中的第3位Con<2>、第2位Con<1>、第1位Con<0>。D触发器14231的时钟输入端、D触发器14232的时钟输入端和D触发器14233的时钟输入端分别耦接异或门14223，以分别接收采样脉冲信号Pul。D触发器14231根据自动校准控制信号中的第3位Con<2>和采样脉冲信号Pul确定使得输出信号Din发生状态翻转的自动校准控制信号，并通过D触发器14231的数据输出端Q输出，这里表示为Q<2>。D触发器14232根据自动校准控制信号中的第2位Con<1>和采样脉冲信号Pul确定使得输出信号Din发生状态翻转的自动校准控制信号，并通过D触发器14232的数据输出端Q输出，这里表示为Q<1>。D触发器14233根据自动校准控制信号中的第1位Con<0>和采样脉冲信号Pul确定使得输出信号Din发生状态翻转的自动校准控制信号，并通过D触发器14233的数据输出端Q输出，这里表示为Q<0>。
图14中DqRoc电路中的省略号“…”表示D触发器14231-14233之间和全加器14234之间还可以有别的电路存在只要能够起到锁存作用即可。
可选的，信号监测电路1423还可以包括全加器14234。全加器14234的输入端可以分别耦接D触发器14231的数据输出端Q、D触发器14232的数据输出端Q和D触发器14233的数据 输出端Q，以用于对m次自动校准中信号监测电路输出的m个自动校准控制信号计算平均值，并将平均值输出至锁存电路中的锁存器14241、锁存器14242、锁存器14243或者锁存器14244中进行锁存。
这里以m＝2为例，全加器14234可以实现(Number+Number)/2的功能，其中第一个Number代表使得目标电路中的IB的OUT(即输出信号Din)从低电平变为高电平的Con<2:0>的值，第二个Number代表使得IB的OUT从高电平变为低电平的Con<2:0>的值，即对这两者求平均值，作为最终锁存的自动校准控制信号。
锁存器14241(LatchEr，对应上述的第一锁存电路)中锁存的是使得DinOr的状态发生翻转时的两个Con<2:0>的平均值。锁存器14242(对应上述的第二锁存电路)中锁存的是使得DinOf的状态发生翻转时的两个Con<2:0>的平均值。锁存器14243(对应上述的第三锁存电路)中锁存的是使得DinEr的状态发生翻转时的两个Con<2:0>的平均值。锁存器14244(对应上述的第四锁存电路)中锁存的是使得DinEf的状态发生翻转时的两个Con<2:0>的平均值。
本公开实施方式提供的校准电路，一方面，可以实现DRAM中Rx offset的自动校准功能，Rx是input电路，例如在LPDDR5X的规格(SPEC)中规定需要有这样的电路实现Rx offset的自动校准，通过打开校准模块中的开关，校准电路可以自动把Rx电路的mismatch校准到较好的效果，调整高频输入下差分信号的mismatch，最终可以改善信号使write(写)眼图变大。另一方面，本公开实施例中将转换器设置在RocCnt中，对计数器输出的计数信号Cnt进行转换，输出自动校准控制信号Con，并将该自动校准控制信号Con输入至DqRoc的信号监测电路中，信号监测电路中D触发器输出的是对应于目标电路的自动校准控制信号(而非其他对应的code)，从而使得在DqRoc电路中可直接锁存信号监测电路的输出值并应用于目标电路的校准，而不需要再设置转换器进行code转换后再锁存，由此可以减小校准电路的版图面积。
下面以将校准电路用于进行LPDDR5X中Rx offset的校准进行举例，利用搭建的数字逻辑结构将Rx 8个档位的mismatch从小到大shmoo一遍或者从大到小shmoo一遍，例如将counter从0-7的顺序变成一个符合Rx offset从小到大的顺序(即7-6-5-4-0-1-2-3)，或者将counter从7-0的顺序变成一个符合Rx offset从大到小的顺序(即3-2-1-0-4-5-6-7)，将输出信号变化的档位锁存并输入到Rx中完成自动校准，即自动校准控制信号Con可以按照对应的偏移校准值从小到大或者从大到小的顺序进行排序。
下面以从小到大shmoo一次进行举例说明。根据上图14可知，RocCnt电路包括Osc电路、由Osc电路输出的时钟信号控制的counter以及将counter计数值转换为自动校准控制信号的转换器，本公开针对其中一种转换对应关系，给出了几种转换器实现电路，如图15-17所示(不同的转换对应关系，具体的实现电路不同，此外，相同的转换对应关系，可以有多种实现电路，这里不做具体限定)，用于将计数信号000-001-010-011-100-101-110-111转换为自动校准控制信号111-110-101-100-011-010-001-000，为ROC的设计增加灵活性，使得在校准offset时既可以通过ROC自动校准，也可以通过测试模式输入。在RocEn(校准使能信号)开启后输出转换后的自动校准控制信号(可以称之为trim值)到Rx中，保证trim顺序。
以待校准的目标电路为图12中的Rx电路为例，本公开实施例提供的校准电路是为了Rx电路服务的，Rx电路中有四个档位调节mismatch，分别是差分信号左边2个档位和右边2个档位，以左边为例，也就是左边“11-10-01-00”，右边同理，所以一共8个档位，在转换器中把这8个档位做成相应的逻辑关系，对应的就是计数信号“000-001-010-011-100-101-110-111，但是这个顺序并不是校准过程中想要的顺序，希望的是左边的档位是从大到小开启的也就是11-10-01-00”，右边同理，那么对应的8个档位顺序应该是“111-110-101-100-000-001-010-011”，这样的顺序有利于Rx offset校准顺序，按照左侧mismatch到右侧mismatch从小到大的顺序排列。
图15是本公开一示例性实施例中的控制信号产生电路的示意图。图15实施例还是以N＝3进行举例说明，但本公开并不限定于此，可以根据实际需求设置N的取值。如图15所示，控制信号产生电路1500可以包括反相器1510、反相器1520、反相器1530、反相器1560、反相器1570、选择器1540和选择器1550。
反相器1510的输入端可以用于接收计数信号中的第3位Cnt<2>，反相器1510的输出端可以用于输出自动校准控制信号的第3位Con<2>。
反相器1520的输入端可以用于接收计数信号中的第2位Cnt<1>，反相器1520的输出端可以用于输出互补计数信号中的第2位CntN<1>。选择器1540的第一输入端可以用于接收计数信号中的第2位Cnt<1>，第二输入端可以用于接收互补计数信号中的第2位CntN<1>，控制端可以用于接收计数信号中的第3位Cnt<2>，即当Cnt<2>取值为0时，选择输出CntN<1>并取反 即得到Con<1>，即选通路径2，相当于三次取反Cnt<1>；当Cnt<2>取值为1时，选择输出Cnt<1>并取反即得到Con<1>，即选通路径1，相当于二次取反Cnt<1>。反相器1560的输入端可以耦接选择器1540的输出端，反相器1560的输出端可以用于输出自动校准控制信号中的第2位Con<1>。
反相器1530的输入端可以用于接收计数信号中的第1位Cnt<0>，反相器1530可以用于根据计数信号中的第1位Cnt<0>产生互补计数信号中的第1位CntN<0>。选择器1550的第一输入端可以用于接收计数信号中的第1位Cnt<0>，第二输入端可以用于接收互补计数信号中的第1位CntN<0>，控制端可以用于接收计数信号中的第3位Cnt<2>，即当Cnt<2>取值为0时，选择输出CntN<0>并取反即得到Con<0>，即选通路径4，相当于三次取反Cnt<0>；当Cnt<2>取值为1时，选择输出Cnt<0>并取反即得到Con<0>，即选通路径3，相当于二次取反Cnt<0>。反相器1570的输入端可以耦接选择器1550的输出端，反相器1570的输出端可以用于输出自动校准控制信号中的第1位Con<0>。
图15实施例中Cnt<2:0>和Con<2:0>之间的转换关系可以用下表2表示：
表2
本公开实施方式提供的校准电路，一方面，通过在RocCnt电路中增设转换器，该转换器可以将计数器原本从0-7的顺序转换为转换器输出的从“7-6-5-4-0-1-2-3”的顺序，该转换后的顺序为offset的trim(调整)顺序，也就是“111-110-101-100-000-001-010-011”shmoo1次，通过对应的锁存器锁存后，再分别输入到四相位的Rx电路中。另一方面，1个对应4个DqPad中的DqRoc电路，减少了DqRoc中的转换器的电路面积，可以达成四倍电路面积减小的收益，使电路功能更加简单明了。
可以理解的是，本公开实施例中提供的控制信号产生电路可以采用任意的逻辑结构来实现，不限于上述图15的举例，例如同样是实现从0-7到“7-6-5-4-0-1-2-3”的顺序的转换，还可以采用下图16所示的电路结构。如图16所示，控制信号产生电路1600可以包括反相器1610、反相器1620、反相器1630、选择器1640和选择器1650。反相器1610的输入端可以用于接收计数信号中的第3位Cnt<2>，反相器1610可以用于根据计数信号中的第3位Cnt<2>产生自动校准控制信号的第3位Con<2>。反相器1620的输入端可以用于接收计数信号中的第2位Cnt<1>，反相器1620可以用于根据计数信号中的第2位Cnt<1>产生互补计数信号中的第2位CntN<1>。选择器1640的第一输入端可以用于接收计数信号中的第2位Cnt<1>，第二输入端可以用于接收互补计数信号中的第2位CntN<1>，控制端可以用于接收Con<2>，即当Con<2>取值为0时，选择输出CntN<1>作为Con<1>，即选通路径2；当Con<2>取值为1时，选择输出Cnt<1>作为Con<1>，即选通路径1。选择器1640的输出端可以用于输出自动校准控制信号中的第2位Con<1>。
反相器1630的输入端可以用于接收计数信号中的第1位Cnt<0>，反相器1630可以用于产生互补计数信号中的第1位CntN<0>。选择器1650的第一输入端可以用于接收计数信号中的第1位Cnt<0>，第二输入端可以用于接收互补计数信号中的第1位CntN<0>，控制端可以用于接收计数信号中的第3位Con<2>，即当Con<2>取值为0时，选择输出CntN<0>作为Con<0>，即选通路径4；当Con<2>取值为1时，选择输出Cnt<0>作为Con<0>，即选通路径3。选择器1650的输出端可以用于输出自动校准控制信号中的第1位Con<0>。
图17实施例以利用RocCnt电路中的转换器输出的Con<2:0>代替计数器输出的Cnt<2:0>来作为DqRoc中的信号监测电路的输入为例，将计数器原本按顺序从0-7的顺序转换为转换器输出的从“7-6-5-4-0-1-2-3”以及“3-2-1-0-4-5-6-7”的顺序，该转换后的顺序为offset的trim顺序， 也就是“111-110-101-100-000-001-010-011->011-010-001-000-001-101-011-111“shmoo两次，后续的全加器将检测到的两个toggle对应的数值相加取平均值，通过对应的锁存器锁存后，再分别输入到四相位的Rx电路中。
如图17所示，控制信号产生电路1700可以包括反相器1711、选择器1720、反相器1712、反相器1713、反相器1714、反相器1715、选择器1740、选择器1750、选择器1780和选择器1790。
反相器1711的输入端可以用于接收Cnt<2>，反相器1711的输出端可以用于输出互补计数信号中的第3位CntN<2>。选择器1720的第一输入端可以用于接收Cnt<2>，第二输入端可以用于接收CntN<2>，控制端可以用于接收Cnt<3>，选择器1720的输出端可以用于输出Con<2>。
反相器1712的输入端可以用于接收Cnt<1>，反相器1712的输出端可以用于输出CntN<1>。选择器1740的第一输入端可以用于接收Cnt<1>，第二输入端可以用于接收CntN<1>，控制端可以用于接收Cnt<2>，选择器1740的输出端可以用于输出互补自动校准控制信号中的第2位conN<1>。反相器1713的输入端可以耦接选择器1740的输出端，接收conN<1>，以产生con<1>，反相器1713的输出端可以用于输出con<1>。选择器1780的第一输入端用于接收conN<1>，第二输入端用于接收con<1>，控制端用于接收Cnt<3>，选择器1780可以根据Cnt<3>选择接收到的conN<1>或con<1>作为最终的自动校准控制信号中的第2位Con<1>，并通过该选择器1780的输出端输出该最终的自动校准控制信号中的Con<1>。
反相器1714的输入端可以用于接收Cnt<0>，反相器17140的输出端可以输出CntN<0>。选择器1750的第一输入端可以用于接收Cnt<0>，第二输入端可以用于接收CntN<0>，控制端可以用于接收Cnt<2>，选择器1750的输出端可以用于输出conN<0>。反相器1715的输入端可以耦接选择器1750的输出端，接收conN<0>，以产生con<0>，反相器1715的输出端可以用于输出con<0>。选择器1790的第一输入端用于接收conN<0>，第二输入端用于接收con<0>，控制端用于接收Cnt<3>，选择器1790可以根据Cnt<3>选择接收到的conN<0>或con<0>作为最终的自动校准控制信号中的Con<0>，并通过该选择器1790的输出端输出最终的自动校准控制信号中的Con<0>。
图17实施例中，Cnt<3>用于控制是0-7进行转换还是7-0进行转换，例如在选择器1580中，若是0-7进行转换，则Cnt<3>为0时，选择直接输出Con<1>；若7-0进行转换，则Cnt<3>为1时，选择输出ConN<1>。
7-0转换为3-2-1-0-4-5-6-7如下表3所示：
表3
需要说明的是，计数信号与自动校准控制信号之间的对应关系可以根据实际需要进行设计，每种不同的对应关系的实现电路可以是不同的，同一种对应关系也可以采用不同的电路来实现，只要能够实现将转换出的信号直接对应于校准模块的开关控制信号即可。
例如，设计的对应关系还可以如下表4所示：
表4

再例如，设计的对应关系还可以如下表5所示：
表5
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。

Claims (15)

  1. 一种校准电路(100，300，1400)，其特征在于，包括：
    校准控制电路(110，1410)，用于产生时钟信号(OscClk)和自动校准控制信号(Con，Con-1)，并用于根据所述自动校准控制信号(Con，Con-1)对目标电路(130，1430)的偏移进行自动校准，所述自动校准控制信号(Con，Con-1)基于所述时钟信号(OscClk)产生；
    校准监测电路(120)，耦接所述校准控制电路(110，1410)，接收所述时钟信号(OscClk)和所述自动校准控制信号(Con，Con-1)，用于基于所述时钟信号(OscClk)监测所述目标电路(130，1430)的输出信号(Din)的变化状态，并在所述输出信号(Din)发生状态翻转时锁存所述自动校准控制信号(Con，Con-1)，将锁存的所述自动校准控制信号(Con’，Con-1’)对应的偏移校准值确定为所述目标电路(130，1430)的目标偏移校准值。
  2. 如权利要求1所述的校准电路(100，300，1400)，其特征在于，所述校准控制电路(110，1410)包括：
    时钟产生电路(111)，用于产生所述时钟信号(OscClk)；
    计数电路(112)，耦接所述时钟产生电路(111)，接收所述时钟信号(OscClk)，用于根据所述时钟信号(OscClk)产生计数信号(Cnt)，所述计数信号(Cnt)指示所述时钟信号(OscClk)的计数值；
    控制信号产生电路(113，1500)，耦接所述计数电路(112)，接收所述计数信号(Cnt)，用于将所述计数信号(Cnt)转换为所述自动校准控制信号(Con，Con-1)。
  3. 如权利要求1或2所述的校准电路(100，300，1400)，其特征在于，所述校准监测电路(120)包括n个校准监测子电路(120-1，…，120-n)，n为大于或等于1的正整数；
    每个所述校准监测子电路耦接所述校准控制电路(110，1410)，接收所述时钟信号(OscClk)和所述自动校准控制信号(Con，Con-1)。
  4. 如权利要求3所述的校准电路(100，300，1400)，其特征在于，每个所述校准监测子电路均包括：
    信号采样电路(120-11，1422)，分别耦接所述校准控制电路(110，1410)和所述目标电路(130，1430)，接收所述时钟信号(OscClk)和所述目标电路(130，1430)的输出信号(Din)，用于基于所述时钟信号(OscClk)对所述目标电路(130，1430)的输出信号(Din)进行采样，产生采样脉冲信号(Pul)；
    信号监测电路(120-12)，分别耦接所述校准控制电路(110，1410)和所述信号采样电路(120-11，1422)，接收所述自动校准控制信号(Con，Con-1)和所述采样脉冲信号(Pul)，用于根据所述采样脉冲信号(Pul)监测所述目标电路(130，1430)的输出信号(Din)的变化状态，并在所述输出信号(Din)发生状态翻转时输出所述自动校准控制信号(Con，Con-1)；
    锁存电路(120-13)，耦接所述信号监测电路(120-12)，用于锁存所述信号监测电路(120-12)输出的所述自动校准控制信号(Con，Con-1)，将锁存的所述自动校准控制信号(Con’，Con-1’)对应的偏移校准值确定为所述目标电路(130，1430)的目标偏移校准值。
  5. 如权利要求4所述的校准电路(100，300，1400)，其特征在于，所述校准控制电路(110，1410)，还用于根据所述自动校准控制信号(Con，Con-1)对每个所述目标电路(130，1430)的偏移进行m次自动校准，m为大于或等于1的正整数；
    所述信号监测电路(120-12)，还用于对每次自动校准过程中所述目标电路(130，1430)的输出信号(Din)的变化状态进行监测，并在每次所述输出信号(Din)发生状态翻转时输出对应的所述自动校准控制信号(Con，Con-1)。
  6. 如权利要求5所述的校准电路(100，300，1400)，其特征在于，当所述自动校准控制信号(Con，Con-1)对应的偏移校准值从大到小变化时，所述信号监测电路(120-12)输出使得所述输出信号(Din)从第一电平状态转换为第二电平状态的所述自动校准控制信号(Con，Con-1)；
    当所述自动校准控制信号(Con，Con-1)对应的偏移校准值从小到大变化时，所述信号监测电路(120-12)输出使得所述输出信号(Din)从所述第二电平状态转换为所述第一电平状态的所述自动校准控制信号(Con，Con-1)。
  7. 如权利要求5或6所述的校准电路(100，300，1400)，其特征在于，每个所述校准监测子电路还包括：
    第一运算电路(120-14)，分别耦接所述信号监测电路(120-12)和所述锁存电路(120-13)，用于对所述m次自动校准中所述信号监测电路(120-12)输出的m个所述自动校准控制信号 (Con，Con-1)计算平均值(Con-1’)，并将所述平均值(Con-1’)输出至所述锁存电路(120-13)进行锁存。
  8. 如权利要求5或6所述的校准电路(100，300，1400)，其特征在于，每个所述校准监测子电路还包括：
    第二运算电路(120-15)，分别耦接所述信号监测电路(120-12)和所述锁存电路(120-13)，用于从所述m次自动校准中所述信号监测电路(120-12)输出的m个所述自动校准控制信号(Con，Con-1)中选择出现频次最高的自动校准控制信号(Con-1’)，输出至所述锁存电路(120-13)进行锁存。
  9. 如权利要求4至8任一项所述的校准电路(100，300，1400)，其特征在于，所述自动校准控制信号(Con，Con-1)为N位二进制数据(Con<0>，Con<1>，…，Con<N-1>)，N为大于或等于1的正整数；
    所述信号监测电路(120-12)包括：第一触发器(D1)至第N触发器(DN)，其中：
    第i触发器，耦接所述校准控制电路(110，1410)，接收所述自动校准控制信号(Con，Con-1)中的第i位和所述采样脉冲信号(Pul)，用于根据所述自动校准控制信号(Con，Con-1)中的第i位和所述采样脉冲信号(Pul)确定使得所述输出信号(Din)发生状态翻转的所述自动校准控制信号(Con，Con-1)，i为大于或等于1且小于或等于N的正整数。
  10. 如权利要求9所述的校准电路(100，300，1400)，其特征在于，第一触发器(D1)至第N触发器(DN)均为D触发器。
  11. 如权利要求4至10任一项所述的校准电路，其特征在于，所述信号采样电路(120-11，1422)包括：
    第N+1触发器(D(N+1))，接收所述输出信号(Din)和所述时钟信号(OscClk)，用于根据所述时钟信号(OscClk)对所述输出信号(Din)进行采样产生第一采样数据(Samp1)，N为大于或等于1的正整数；
    反相器(120-111)，接收所述时钟信号(OscClk)，用于根据所述时钟信号(OscClk)产生互补时钟信号(/OscClk)；
    第N+2触发器(D(N+2))，耦接所述反相器(120-111)，接收所述输出信号(Din)和所述互补时钟信号(/OscClk)，用于根据所述互补时钟信号(/OscClk)对所述输出信号(Din)进行采样产生第二采样数据(Samp2)；
    异或门(120-112)，分别耦接所述第N+1触发器(D(N+1))和所述第N+2触发器(D(N+2))，接收所述第一采样数据(Samp1)和所述第二采样数据(Samp2)，用于根据所述第一采样数据(Samp1)和所述第二采样数据(Samp2)产生所述采样脉冲信号(Pul)。
  12. 如权利要求11所述的校准电路(100，300，1400)，其特征在于，所述第N+1触发器(D(N+1))和所述第N+2触发器(D(N+2))均为D触发器。
  13. 如权利要求4至12任一项所述的校准电路(100，300，1400)，其特征在于，所述目标电路(130，1430)为数据接收电路，所述输出信号(Din)包括第一相位输出信号(DinOr)、第二相位输出信号(DinOf)、第三相位输出信号(DinEr)和第四相位输出信号(DinEf)；
    每个所述校准监测子电路还包括：
    选择电路(120-16，1421)，耦接所述目标电路(130，1430)和所述信号采样电路(120-11，1422)，接收所述第一相位输出信号(DinOr)、所述第二相位输出信号(DinOf)、所述第三相位输出信号(DinEr)和所述第四相位输出信号(DinEf)，用于依次选择所述第一相位输出信号(DinOr)、所述第二相位输出信号(DinOf)、所述第三相位输出信号(DinEr)或所述第四相位输出信号(DinEf)之一发送至所述信号采样电路(120-11，1422)，以依次针对每个相位输出信号完成所述目标电路(130，1430)的偏移校准，并锁存每个相位输出信号对应的目标偏移校准值。
  14. 如权利要求13所述的校准电路(100，300，1400)，其特征在于，所述锁存电路(120-13)包括：
    第一锁存电路(120-131)，用于锁存所述第一相位输出信号(DinOr)对应的所述目标偏移校准值；
    第二锁存电路(120-132)，用于锁存所述第二相位输出信号(DinOf)对应的所述目标偏移校准值；
    第三锁存电路(120-133)，用于锁存所述第三相位输出信号(DinEr)对应的所述目标偏移校准值；
    第四锁存电路(120-134)，用于锁存所述第四相位输出信号(DinEf)对应的所述目标偏移校准值。
  15. 如权利要求1至14任一项所述的校准电路(100，300，1400)，其特征在于，所述目标电路(130，1430)根据所述自动校准控制信号(Con，Con-1)控制校准模块(1431)中对应校准器件的开关。
PCT/CN2023/111038 2022-11-07 2023-08-03 校准电路 WO2024098852A1 (zh)

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