WO2024011768A1 - 延迟锁相环的延迟检测电路、延迟锁相环电路及存储装置 - Google Patents

延迟锁相环的延迟检测电路、延迟锁相环电路及存储装置 Download PDF

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WO2024011768A1
WO2024011768A1 PCT/CN2022/124152 CN2022124152W WO2024011768A1 WO 2024011768 A1 WO2024011768 A1 WO 2024011768A1 CN 2022124152 W CN2022124152 W CN 2022124152W WO 2024011768 A1 WO2024011768 A1 WO 2024011768A1
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signal
delay
clock signal
output
circuit
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PCT/CN2022/124152
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English (en)
French (fr)
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张亚南
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a delay detection circuit of a delay locked loop, a delay locked loop circuit and a storage device.
  • Clock signals are widely used as signals to synchronize the operation timing of semiconductor devices.
  • a clock signal applied from an external device is used inside a semiconductor device, the internal circuitry of the semiconductor device may cause a time delay problem. Therefore, a delay-locked loop is usually integrated into a semiconductor device. The delay-locked loop can be used to compensate for the time delay so that the clock signal inside the semiconductor device is synchronized with the externally input clock signal.
  • Embodiments of the present disclosure provide a delay detection circuit for a delay locked loop, including: a phase detector configured to receive a feedback clock signal and a reference clock signal, and output a first signal and a second signal, the edge of the first signal The difference between the edge of the second signal and the edge of the second signal represents the phase difference between the feedback clock signal and the reference clock signal; the conversion circuit is configured to receive the first signal and the second signal, delay the first signal at least once, and compare The edge difference between the first signal and the second signal after each delay is calculated, and a code value is output.
  • the code value represents the actual delay amount of the last delayed first signal compared to the first signal.
  • the phase detector is further configured to: receive an initial signal, sample the initial signal in response to the feedback clock signal, and output the first signal; sample the first complementary signal in response to the reference clock signal, and output The second signal, the first complementary signal and the first signal are inverse signals of each other.
  • the phase detector includes: a first sampling circuit configured to receive an initial signal, sample the initial signal in response to a feedback clock signal, and output the first signal and the first complementary signal; a second sampling circuit , is configured to receive a first complementary signal, sample the first complementary signal in response to a reference clock signal, and output a second signal.
  • the first sampling circuit includes: a plurality of cascaded first flip-flops, the clock signal terminal of the first flip-flop of each stage receives the feedback clock signal, and the data input terminal of the first flip-flop of each stage is connected to The first output terminal of the first flip-flop of the upper stage and the data input terminal of the first flip-flop of the first stage receive the initial signal, and the first output terminal and the second output terminal of the first flip-flop of the last stage respectively output the first A signal and a first complementary signal; the second sampling circuit includes a second flip-flop, the data input end of the second flip-flop is connected to the second output end of the first flip-flop of the last stage, and the clock signal end of the second flip-flop receives Reference clock signal.
  • the conversion circuit includes: N cascaded delay conversion units, the delay conversion unit is configured to receive the delayed first signal output by the delay conversion unit of the upper stage, and delay the reception by a preset delay amount.
  • the first signal is received to generate a first delayed signal, and the first delayed signal is output to the delay conversion unit of the next stage, wherein the first signal received by the delay conversion unit at the first stage is provided by the phase detector;
  • the delay conversion unit It is also configured to compare the edge difference between the second signal and the first delayed signal, and output a characterization signal, the characterization signal characterizes whether the edge of the second signal is not later than the edge of the first delayed signal, wherein the code value is based on each The characterization signal of the stage delay conversion unit is obtained.
  • the delay conversion unit includes: a delay unit configured to receive the first signal output by the delay conversion unit of the previous stage, delay the first signal by a preset delay amount and output the first delay signal, wherein, The first signal received by the delay unit of the delay conversion unit at the first stage is provided by the phase detector; the comparison conversion unit is configured to receive the first delay signal and compare the edge difference between the second signal and the first delay signal. , output the representation signal.
  • the delay unit includes: a first delay unit configured to receive a delayed first signal output by a delay conversion unit of a previous stage, delay the first signal by a first delay amount and generate a sub-delay signal. ;
  • the second delay unit is configured to receive the sub-delay signal and delay the sub-delay signal by a second delay amount to generate and output a first delay signal.
  • the delay unit includes two second delay units with the same second delay amount, wherein the output end of one second delay unit is connected to the first delay unit of the delay conversion unit of the next stage, and the other The output terminal of a second delay unit is connected to the comparison conversion unit.
  • the first delay unit includes a first NAND gate, one input end of the first NAND gate is connected to the power supply voltage, and the other end receives the delayed first signal output by the delay conversion unit of the previous stage;
  • the two delay units include a second NAND gate, one input end of the second NAND gate is connected to the power supply voltage, the other input end is connected to the output end of the first delay unit, and the output end provides the first delay signal.
  • the comparison conversion unit is further configured to: if the characterization signal is a logic low level, the edge of the characterization second signal is not later than the edge of the first delayed signal; if the characterization signal includes a logic high level pulse , it means that the edge of the second signal is later than the edge of the first delayed signal.
  • the comparison conversion unit includes: a logic operation circuit, which receives the first delay signal and the second signal, performs a NAND operation on the first delay signal and the second signal, and outputs a representation signal according to the operation result.
  • the logic operation circuit includes: a first PMOS tube, the gate of the first PMOS tube receives the first delay signal, the source of the first PMOS tube is connected to the power node, and the drain is connected to the output node; a second PMOS tube, the gate of the second PMOS tube receives the second signal, the source of the second PMOS tube is connected to the power node, and the drain of the second PMOS tube is connected to the output node; the drain of the first NMOS tube is connected to the output node; the second NMOS tube, the drain is connected to the source of the first NMOS tube, and the source is connected to the ground; wherein, the gate of one of the first NMOS tube and the second NMOS tube receives the second signal, and the gate of the other receives the first delayed signal.
  • the logic operation circuit further includes a third PMOS transistor.
  • the gate of the third PMOS transistor receives the enable signal, and the third PMOS transistor is turned on in response to the enable signal.
  • the source of the third PMOS transistor is connected to the power supply. Node, the drain is connected to the source of the first PMOS tube.
  • the logic operation circuit further includes: a latch, the input terminal is connected to the output node; an even number of series-connected inverters are connected to the output terminal of the latch, and the last stage of the inverter outputs a representative signal.
  • the delay conversion units of each stage have the same preset delay amount.
  • embodiments of the present disclosure also provide a delay locked loop circuit, including: a first delay circuit configured to receive a reference clock signal and delay the reference clock signal based on the first control signal to generate a first delayed clock signal; a second delay circuit configured to receive the first delayed clock signal and delay the first delayed clock signal based on the second control signal to generate a second delayed clock signal, and the delay precision of the second delay circuit is greater than that of the first Delay fineness of the delay circuit; the replica circuit is configured to delay the second delayed clock signal to generate a feedback clock signal; the delay control circuit is configured to adjust based on a phase difference between the reference clock signal and the feedback clock signal The first control signal and the second control signal are provided to the first delay circuit and the second delay circuit respectively; the delay detection circuit according to any one of the above, the delay detection circuit is also It is configured to generate a third control signal corresponding to the actual delay amount based on the code value, and provide the third control signal to the first delay circuit, and the first delay circuit further delays the reference clock signal based on the
  • an embodiment of the present disclosure also provides a storage device, including: the above-mentioned delay-locked loop circuit.
  • the delay-locked loop circuit receives a reference clock signal and outputs an output clock signal that is in phase with the reference clock signal.
  • a feedback clock signal and a reference clock signal are received through a phase detector, and the phase difference between the feedback clock signal and the reference clock signal is converted into a first The difference between the edges of the signal and the second signal; the conversion circuit receives the first signal and the second signal, and delays the first signal at least once so that the edges of the first signal and the second signal are aligned, wherein each time After delay, the phase difference between the first signal and the second signal will be smaller. Based on this, the phase between the first signal and the second signal after each delay is compared, and a code value is output.
  • the code value represents the actual delay amount of the last delayed first signal compared to the first signal.
  • the edge difference between the last delayed first signal and the second signal is small or even 0, which means that after delay, the phase difference between the feedback clock signal and the reference clock signal is reduced or 0, that is to say, the code
  • the value represents the delay amount of the feedback clock signal compared to the reference clock signal. Therefore, when the delay locked loop compensates the next input reference clock signal based on the code value, the reference clock signal can be accurately compensated based on the amount of delay that will actually occur in the reference clock signal, so that the next output receives feedback
  • the phase between the clock signal and the reference clock signal is close to or the same, thereby improving the efficiency of the delay locked loop to compensate for the time delay.
  • Figure 1 is a functional block diagram of a delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure
  • Figure 2 is a functional block diagram of another delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure
  • Figure 3 is a circuit diagram of a first sampling circuit in a delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure
  • Figure 4 is a timing diagram of phase detection by a phase detector in a delay detection circuit provided by an embodiment of the present disclosure
  • Figure 5 is a functional block diagram of a second sampling circuit in a delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure
  • Figure 6 is a functional block diagram of a second sampling circuit in another delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure
  • Figure 7 is a circuit diagram of a second sampling circuit in another delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure
  • Figure 8 is a circuit diagram of another second sampling circuit in another delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure
  • Figure 9 is a circuit diagram of a delay conversion unit in a delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure.
  • Figure 10 is another timing diagram in a delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure.
  • FIG. 11 is a functional block diagram of a delay-locked loop circuit provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a delay detection circuit for a delay locked loop, which receives a feedback clock signal and a reference clock signal through a phase detector, and converts the phase difference between the feedback clock signal and the reference clock signal into a first signal and a third signal.
  • the phase difference is the same.
  • the edge difference between the first signal and the second signal after each delay is compared, and a code value is output.
  • the code value represents the actual delay amount of the last delayed first signal compared to the first signal.
  • the code value represents the delay amount of the feedback clock signal compared to the reference clock signal. Therefore, when the delay-locked loop compensates the next input reference clock signal based on the code value, it can be accurately based on the reference clock signal. The amount of delay actually generated by the clock signal compensates the reference clock signal, so that the next output received feedback clock signal can have the same phase as the reference clock signal, thereby improving the efficiency of the delay-locked loop in compensating for time delays.
  • FIG. 1 is a functional block diagram of a delay detection circuit of a delay locked loop provided by an embodiment of the present disclosure.
  • the delay detection circuit of the delay locked loop includes: a phase detector 101 configured to receive a feedback clock signal CLKFB and a reference clock signal CLKREF, and output a first signal Data_TDC and a second signal CLK_TDC, the first signal Data_TDC
  • the difference between the edge of and the edge of the second signal CLK_TDC represents the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF
  • the conversion circuit 102 is configured to receive the first signal Data_TDC and the second signal CLK_TDC, and A signal Data_TDC is delayed at least once, the edge difference between the first signal Data_TDC and the second signal CLK_TDC after each delay is compared, and a code value Code is output.
  • the code value Code represents the difference between the last delayed first signal Data_TDC and the first delayed signal Data_TDC. Actual delay amount of signal Data_TDC.
  • the delay locked loop is used to receive the reference clock signal CLKREF, perform delay compensation on the reference clock signal CLKREF, and output the compensated feedback clock signal CLKFB.
  • the feedback clock signal CLKFB may be applied to the semiconductor device and serve as a signal for synchronizing the timing operation of the semiconductor device. Therefore, the delay-locked loop has high requirements on the accuracy and efficiency of the compensation time delay. It is necessary to improve the accuracy of the delay-locked loop in compensating the time delay and at the same time improve the efficiency of the delay-locked loop in compensating the time delay.
  • the first signal Data_TDC is delayed at least once through the conversion circuit 102 so that the edge difference between the first signal Data_TDC and the second signal CLK_TDC is reduced or aligned, that is, through delay, the feedback clock signal CLKFB The phase difference with the reference clock signal CLKREF is reduced or consistent.
  • the edge difference between the first signal Data_TDC and the second signal CLK_TDC after each delay is compared, and a code value Code is output.
  • the code value Code represents the actual delay of the last delayed first signal Data_TDC compared to the first signal Data_TDC.
  • the quantity, that is, the code value Code represents the actual delay amount of the feedback clock signal CLKFB compared to the reference clock signal CLKREF.
  • the delay locked loop can accurately compensate the reference clock signal CLKREF based on the amount of delay that will actually be generated by the reference clock signal CLKREF, so that the phase between the output receive feedback clock signal CLKFB and the reference clock signal CLKREF is close to or the same , not only can the accuracy of the delay-locked loop's compensation of time delay be improved, but also, since the delay is compensated based on the amount of delay actually generated by the reference clock signal CLKREF, the delay-locked loop's effect on the reference clock signal CLKREF can be reduced. Delay times, thereby improving the efficiency of delay-locked loop compensation for time delays.
  • the first signal Data_TDC and the second signal CLK_TDC may be level signals, and the first signal Data_TDC is used to represent the feedback clock signal CLKFB, and the second signal CLK_TDC is used to represent the reference clock signal CLKREF. In this way, the first signal Data_TDC can be used to represent the reference clock signal CLKREF.
  • the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF is converted into a difference between edges of the level signal. Since the edge moments of the level signals are easier to obtain, the obtained differences between the edges of the level signals are more accurate.
  • the first signal Data_TDC can also be used to characterize the reference clock signal CLKREF
  • the second signal CLK_TDC can also be used to characterize the feedback clock signal CLKFB.
  • the phase detector 101 is further configured to: receive an initial signal, sample the initial signal in response to the feedback clock signal CLKFB, and output the first signal Data_TDC; and perform sampling on the first complementary signal in response to the reference clock signal CLKREF. Sample and output the second signal CLK_TDC.
  • the first complementary signal and the first signal Data_TDC are mutually inverted signals.
  • the initial signal is a level signal. Therefore, the first signal Data_TDC obtained by sampling the initial signal in response to the feedback clock signal CLKFB will also be a level signal, and the second signal CLK_TDC will also be a level signal.
  • the edge positions of the first complementary signal and the first signal Data_TDC are the same, but they are inverse signals.
  • the edge transition moments of the first complementary signal and the first signal Data_TDC are the same, but the transition modes are opposite.
  • the edge transition time of the first complementary signal is a rising edge
  • the edge transition time of the first signal Data_TDC is a falling edge.
  • the second signal CLK_TDC is obtained based on the first complementary signal. Therefore, the edge of the second signal CLK_TDC is opposite to the edge of the first signal Data_TDC. In this way, it is beneficial to subsequently use the conversion circuit 102 to convert the first signal Data_TDC with opposite edges and The second signal CLK_TDC is compared.
  • the first signal Data_TDC is obtained by sampling the initial signal in response to the feedback clock signal CLKFB
  • the second signal CLK_TDC is obtained by sampling the first complementary signal in response to the reference clock signal CLKREF
  • the first complementary signal is the same as the first signal Data_TDC The same, that is, it is also obtained based on sampling the initial signal. It can be seen that the first signal Data_TDC and the second signal CLK_TDC are actually obtained by sampling the initial signal, and the first signal Data_TDC is used to represent the feedback clock signal CLKFB, and the second signal CLK_TDC is used to represent the reference clock signal CLKREF.
  • the difference between the edges obtained by comparing the edge differences of the first signal Data_TDC and the second signal CLK_TDC can accurately represent the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF.
  • the difference between the edge moments of the first signal Data_TDC and the second signal CLK_TDC refers to the difference between the rising edge moment of the first signal Data_TDC and the rising edge moment of the second signal CLK_TDC; or it is the falling edge moment of the first signal Data_TDC. and the difference between the falling edge moment of the second signal CLK_TDC.
  • the phase detector 101 includes: a first sampling circuit 111 configured to receive an initial signal DL_TDCRSTB, sample the initial signal DL_TDCRSTB in response to a feedback clock signal CLKFB, and output a first signal Data_TDC and the first complementary signal Data_TDCB; the second sampling circuit 121 is configured to receive the first complementary signal Data_TDCB, sample the first complementary signal Data_TDCB in response to the reference clock signal CLKREF, and output the second signal CLK_TDC.
  • a first sampling circuit 111 configured to receive an initial signal DL_TDCRSTB, sample the initial signal DL_TDCRSTB in response to a feedback clock signal CLKFB, and output a first signal Data_TDC and the first complementary signal Data_TDCB
  • the second sampling circuit 121 is configured to receive the first complementary signal Data_TDCB, sample the first complementary signal Data_TDCB in response to the reference clock signal CLKREF, and output the second signal CLK_TDC.
  • the first signal Data_TDC and the first complementary signal Data_TDCB are acquired through the first sampling circuit 111, so that the first signal Data_TDC and the first complementary signal Data_TDCB are the same signal, and the first signal Data_TDC and the first complementary signal Data_TDCB are inverse signals of each other. .
  • the first sampling circuit 111 and the second sampling circuit 121 respectively perform sampling to output the first signal Data_TDC and the second signal CLK_TDC.
  • the first The edge of the signal Data_TDC is earlier than the edge of the second signal CLK_TDC, that is, there is a moment when the first signal Data_TDC and the second signal CLK_TDC are both logic high levels at the same time, and the first signal Data_TDC and the second signal CLK_TDC are both logic high levels at the same time.
  • the length of time is the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF; if there is no phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, then the edge of the first signal Data_TDC and the edge of the second signal CLK_TDC The edges are at the same time, that is, there is no time when the first signal Data_TDC and the second signal CLK_TDC are both logic high levels at the same time. In this way, sampling can be performed in response to the feedback clock signal CLKFB and the reference clock signal CLKREF respectively, so that the first sampling circuit 111 and the second sampling circuit 121 will not affect each other, which is beneficial to improving the obtained first signal Data_TDC and the second signal The accuracy of CLK_TDC.
  • the feedback clock signal CLKFB and the reference clock signal CLKREF are input to the first sampling circuit 111 and the second sampling circuit 121 at the same time, so that the difference between the edges of the first signal Data_TDC and the second signal CLK_TDC can be obtained accurately Characterizes the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF.
  • the first sampling circuit 111 includes: a plurality of cascaded first flip-flops 113.
  • the clock signal terminal of the first flip-flop 113 of each stage receives the feedback clock signal CLKFB.
  • the data input terminal of a flip-flop 113 is connected to the first output terminal of the first flip-flop 113 of the previous stage.
  • the data input terminal of the first flip-flop 113 of the first stage receives the initial signal DL_TDCRSTB.
  • the first flip-flop 113 of the last stage The first output terminal and the second output terminal respectively output the first signal Data_TDC and the first complementary signal Data_TDCB;
  • the second sampling circuit 121 includes a second flip-flop 122, and the data input terminal of the second flip-flop 122 is connected to the third stage of the last stage.
  • the second output terminal of a flip-flop 113 and the clock signal terminal of the second flip-flop 122 receive the reference clock signal CLKREF.
  • the data input terminal receives the initial signal DL_TDCRSTB
  • the clock signal terminal receives the feedback clock signal CLKFB.
  • the first flip-flop 113 is configured to, when the edge time of the feedback clock signal CLKFB arrives, the initial signal is The signal DL_TDCRSTB is sampled to output the corresponding first signal Data_TDC. In this way, the level change of the first signal Data_TDC can represent the phase change of the feedback clock signal CLKFB.
  • the first flip-flop 113 of each stage samples the initial signal DL_TDCRSTB at the edge moment of one cycle of the feedback clock signal CLKFB.
  • the first first flip-flop 113 in the cascaded first flip-flops 113 receives the initial signal DL_TDCRSTB and responds on the edge of the feedback clock signal CLKFB When the time comes, the initial signal DL_TDCRSTB is sampled and the sampled initial signal DL_TDCRSTB is output.
  • the second-stage first flip-flop 113 receives the sampled initial signal DL_TDCRSTB output by the first-stage first flip-flop 113, and samples the sampled initial signal DL_TDCRSTB when the next edge of the feedback clock signal CLKFB arrives.
  • the edge moment may be the rising edge of the feedback clock signal CLKFB, and in other embodiments, the edge moment may be the falling edge of the feedback clock signal CLKFB.
  • the last first flip-flop 113 in the cascade of first flip-flops 113 responds to the sampled initial signal output by the first flip-flop 113 of the upper stage.
  • DL_TDCRSTB is sampled. After sampling, the signal output by the first terminal is used as the first signal Data_TDC.
  • first flip-flop 113 can sample the initial signal DL_TDCRSTB within the edge moment of a complete feedback clock signal CLKFB cycle. Acquisition, so that the acquired first signal Data_TDC can represent the complete phase of the feedback clock signal CLKFB.
  • the second terminal of the last stage first flip-flop 113 may be an inverting output port, so that the first complementary signal Data_TDCB is output in inversion with the first signal Data_TDC.
  • the second flip-flop 122 is configured to sample the first complementary signal Data_TDCB to output a corresponding second signal CLK_TDC when the edge moment of the reference clock signal CLKREF arrives. In this way, the level change of the first signal Data_TDC can represent the phase change of the feedback clock signal CLKFB. Specifically, the second flip-flop 122 samples the initial signal DL_TDCRSTB at an edge moment of a reference clock signal CLKREF.
  • the first sampling circuit 111 samples the initial signal DL_TDCRSTB
  • the second sampling circuit 121 samples the first complementary signal Data_TDCB.
  • the principle can be referred to FIG. 4 .
  • FIG. 4 is a timing diagram of phase detection by a phase detector in a delay detection circuit provided by an embodiment of the present disclosure.
  • each stage of the first flip-flop 113 responds to the feedback clock signal CLKFB and responds to the initial signal DL_TDCRSTB at the arrival of the edge moment of each feedback clock signal CLKFB. Take samples. Among them, the last-stage first flip-flop 113 samples the initial signal DL_TDCRSTB output by the upper-stage first flip-flop 113 at the arrival of the fourth feedback clock signal CLKFB edge moment in the four feedback clock signal CLKFB cycles, and The first signal Data_TDC is output, and at the same time, the first complementary signal Data_TDCB is output.
  • the edge time of the first complementary signal Data_TDCB is the same as the edge time of the first signal Data_TDC, and the first complementary signal Data_TDCB and the first signal Data_TDC are inverse signals of each other.
  • the first flip-flop 113 may sample the initial signal DL_TDCRSTB at the rising edge of the feedback clock signal CLKFB.
  • the second flip-flop 122 may also sample the initial signal DL_TDCRSTB at the falling edge of the cycle of the feedback clock signal CLKFB.
  • the second terminal of the first flip-flop 113 of the last stage transmits the first complementary signal Data_TDCB to the second flip-flop 122, and the second flip-flop 122 samples the first complementary signal Data_TDCB in response to the reference clock signal CLKREF.
  • the second flip-flop 122 samples the first complementary signal Data_TDCB when the period of the reference clock signal CLKREF arrives, and obtains the second signal CLK_TDC. It is worth noting that when the first flip-flop 113 samples the initial signal DL_TDCRSTB at the rising edge of the feedback clock signal CLKFB cycle, the second flip-flop 122 also needs to sample the first complementary signal at the rising edge of the reference clock signal CLKREF.
  • Data_TDCB is sampled.
  • the second flip-flop 122 When the second flip-flop 122 samples the initial signal DL_TDCRSTB at the falling edge of the feedback clock signal CLKFB, the second flip-flop 122 also needs to sample the first complementary signal Data_TDCB at the falling edge of the reference clock signal CLKREF, thereby ensuring The difference between the acquired edges of the first signal Data_TDC and the second signal CLK_TDC can accurately represent the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF.
  • the second sampling circuit 121 Since the reference clock signal CLKREF and the feedback clock signal CLKFB are input to the first sampling circuit 111 and the second sampling circuit 121 at the same time, that is to say, the second sampling circuit 121 receives the first complementary signal Data_TDCB from the first sampling circuit 111, and the reference clock The signal CLKREF is also input to the second sampling circuit 121 in real time.
  • the second flip-flop 122 can synchronously respond to the reference clock signal CLKREF to sample the first complementary signal Data_TDCB, so that the obtained first signal Data_TDC is equal to
  • the edge difference between the second signal CLK_TDC can accurately represent the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB.
  • the second flip-flop 122 samples the first complementary signal Data_TDCB in response to the edge time of the reference clock signal CLKREF, the delay time between the edge time of the feedback clock signal CLKFB and the edge time of the reference clock signal CLKREF will pass.
  • the first complementary signal Data_TDCB when there is no phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF, since the first complementary signal Data_TDCB is the first flip-flop 113 at the edge moment of the feedback clock signal CLKFB, for example, the rising edge moment, the initial signal is DL_TDCRSTB is sampled. Therefore, when the first complementary signal Data_TDCB is input to the second flip-flop 122, the rising edge time of the reference clock signal CLKREF arrives exactly at the same time. Therefore, the second flip-flop 122 does not need to go through the edge time of the feedback clock signal CLKFB and the reference clock signal CLKREF. By the delay time difference between the edge moments, the first complementary signal Data_TDCB can be synchronously sampled, so that the edge of the output first complementary signal Data_TDCB is aligned with the edge of the second signal CLK_TDC.
  • the feedback clock signal CLKFB and the reference clock signal CLKREF transmitted to the phase detector 101 may be turned off, that is, the feedback clock signal CLKFB and the reference clock signal CLKREF may be gated.
  • the gated signals are respectively the gated feedback clock signal CLKFB_SYSC and the gated reference clock signal CLKREF_SYSC.
  • the phase difference of the gated feedback clock signal CLKFB_SYSC and the gated reference clock signal CLKREF_SYSC is detected to obtain the feedback clock signal CLKFB and
  • the phase difference between the reference clock signals CLKREF can reduce the power consumption generated by the delay detection circuit.
  • the second sampling circuit 121 may also include a plurality of cascaded second flip-flops 122 , and the number of the second flip-flops 122 is equal to the number of the first flip-flops 113 .
  • the clock signal terminal of the second flip-flop 122 of each stage receives the reference clock signal CLKREF, and the data input terminal of the second flip-flop 122 of each stage is connected to the first output terminal of the second flip-flop 122 of the previous stage.
  • the data input terminal of the second flip-flop 122 receives the initial signal DL_TDCRSTB.
  • the second flip-flop 122 of the last stage outputs the second signal CLK_TDC, and the second signal CLK_TDC is the inverted signal, that is, the second signal CLK_TDC is the same as the first signal.
  • Signal Data_TDC has opposite edges. That is to say, the first sampling circuit 111 and the second sampling circuit 121 simultaneously and respectively respond to the feedback clock signal CLKFB and the reference clock signal CLKREF to sample the initial signal DL_TDCRSTB, and output the first signal Data_TDC and the second signal CLK_TDC.
  • the same initial signal DL_TDCRSTB is sampled in response to the feedback clock signal CLKFB and the reference clock signal CLKREF. Therefore, the difference between the edges of the first signal Data_TDC and the second signal CLK_TDC can be used to characterize the feedback clock signal CLKFB and the reference clock signal CLKREF. phase difference.
  • the first sampling circuit 111 may sample the initial signal DL_TDCRSTB in response to the reference clock signal CLKREF to output the first signal Data_TDC, and accordingly, the second sampling circuit 121 may respond to the feedback clock signal CLKFB samples the first complementary signal Data_TDCB and outputs the second signal CLK_TDC.
  • the conversion circuit 102 receives the first signal Data_TDC and the second signal CLK_TDC, and delays the first signal Data_TDC at least once, so that the edge of the first signal Data_TDC is aligned with the edge of the second signal CLK_TDC or is later than the edge of the first signal Data_TDC. At the edge of the second signal CLK_TDC, after each delay, the edge difference between the first signal Data_TDC and the second signal CLK_TDC will be smaller, so that the edge difference between the first signal Data_TDC and the second signal CLK_TDC is smaller or aligned.
  • the conversion circuit 102 includes: N cascaded delay conversion units, the delay conversion unit is configured to receive the delayed first signal Data_TDC output by the delay conversion unit of the upper stage, to The preset delay amount delays the received first signal Data_TDC to generate a first delay signal, and outputs the first delay signal to the delay conversion unit of the next stage, where the first signal Data_TDC received by the delay conversion unit at the first stage is The phase detector 101 provides; the delay conversion unit is further configured to compare the edge difference between the second signal CLK_TDC and the first delay signal, and output a characterization signal, the characterization signal characterizes whether the edge of the second signal CLK_TDC is not later than the first delay signal.
  • the conversion circuit can delay the first signal Data_TDC to obtain the first delayed signal, and then compare the edge difference between the first delayed signal and the second signal CLK_TDC.
  • the third signal obtained after delaying several stages of delay conversion units is The edge of a delayed signal is still earlier than the edge of the second signal CLK_TDC, that is, the delay of the first signal Data_TDC by several stages of delay conversion units is still not enough to offset the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF; if after the nth The edge of the first delay signal obtained after delay by the delay conversion unit is later than or equal to the edge of the second signal CLK_TDC, so the delay of the first signal Data_TDC by the n-stage delay conversion unit is still not enough to offset the feedback clock signal CLKFB and the reference clock signal. The phase difference between CLKREF.
  • the representation signal output by each stage of the delay conversion unit from the 1st stage to the n-1th stage is a level signal including a logic high level
  • the delay conversion unit from the nth stage to the Nth stage each The representation signal of the first-level output is a logic low level signal, that is, the code value Code output by the N-level delay conversion unit is 1 in the first n-1 bits, and 0 in the last N-n+1 bits.
  • the obtained code value code represents the feedback clock signal
  • the phase difference between CLKFB and the reference clock signal CLKREF is greater than the delay of the n-1 level delay conversion unit, and is less than or equal to the delay of the n-level delay conversion unit, and then the obtained code value code is used to delay the feedback clock signal CLKFB Coarse adjustment is performed to adjust the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF.
  • the delay conversion unit 112 of the first stage receives the first signal Data_TDC0 from the phase detector and is used to output the delayed first signal Data_TDC1; the delay conversion unit of the next stage then receives the first signal Data_TDC1 and uses the preset Delay by the delay amount, output the delayed first signal Data_TDC2, and so on, repeat the above steps.
  • Each stage of delay unit delays the received first signal Data_TDC by a preset delay amount.
  • the total delay amount for the first signal Data_TDC is the preset delay amount ⁇ N.
  • the code value Code is obtained based on the representation signal of each stage of delay unit. That is to say, the code value Code is obtained based on the total delay amount to the first signal Data_TDC, so that the code value Code can accurately represent the last delayed first signal.
  • the actual delay amount of Data_TDC compared to the first signal Data_TDC.
  • the reference clock signal CLKREF can be accurately compensated based on the actual delay amount of the reference clock signal CLKREF, so that the next output
  • the received feedback clock signal CLKFB may have the same phase as the reference clock signal CLKREF, thereby improving the efficiency of the delay locked loop to compensate for the time delay.
  • the delay conversion unit 112 includes: a delay unit configured to receive the first signal Data_TDC output by the delay conversion unit 112 of the previous stage, delay the first signal Data_TDC by a preset delay amount, and output the first delay signal, wherein the first signal Data_TDC received by the delay unit of the delay conversion unit 112 at the first stage is provided by the phase detector 101; the comparison conversion unit is configured to receive the first delay signal and compare the second signal CLK_TDC with the first signal. The difference between the edges of a delayed signal, the output represents the signal.
  • the delay unit is used to delay the first signal Data_TDC
  • the comparison conversion unit is used to detect whether the delayed first signal Data_TDC, that is, the edge of the second signal CLK_TDC is not later than the edge of the first delayed signal.
  • characterization signals In some embodiments, different logic level signals may be used to represent the characterization signals.
  • the delay unit 11 includes: a first delay unit 1101 configured to receive the delayed first signal Data_TDC output by the delay conversion unit 112 of the previous stage, and delay it by a first delay amount.
  • the first signal Data_TDC generates a sub-delay signal;
  • the second delay unit 1102 is configured to receive the sub-delay signal and delay the sub-delay signal by a second delay amount to generate and output a first delay signal D_OUT.
  • each delay unit 11 may include different first delay units 1101 and second delay units 1102, so that the first delay unit 1101 and the second delay unit 1102 can respectively delay the first signal Data_TDC, Flexibly adjust the delay amount to the first signal Data_TDC.
  • the number of first delay units 1101 in each stage of delay conversion unit 112 can be changed, so that the amount of delay to the first signal Data_TDC can be changed to adapt to different requirements.
  • the number of the first delay units 1101 can be larger, so that the delay amount of the first-stage delay conversion unit 112 on the first signal Data_TDC is larger, Equivalent to coarse adjustment;
  • the second-stage delay conversion unit 112 delays the delayed first signal Data_TDC again the number of first delay units 1101 can be smaller, so that the second-stage delay conversion unit 112 delays the delayed first signal Data_TDC.
  • the delay amount of the first signal Data_TDC is small, which is equivalent to fine adjustment, thereby improving the efficiency of delay processing of the first signal Data_TDC.
  • the delay unit 11 includes two second delay units 1102 with the same second delay amount, wherein the output end of a second delay unit 1102 is connected to the first delay unit of the delay conversion unit 112 of the next stage. 1101.
  • the output terminal of another second delay unit 1102 is connected to the comparison conversion unit.
  • the output end of a second delay unit 1102 is used to provide the first delay signal to the delay conversion unit 112 of the next stage, and further perform delay adjustment on the first signal Data_TDC.
  • the output end of the other second delay unit 1102 is used to transmit the first delay signal to the comparison conversion unit 112 to detect the edge difference between the first delay signal and the second signal CLK_TDC.
  • the first delay signals D_OUT output by the two second delay units 1102 are the same signal. In this way, the first delay signal used for detection can be guaranteed.
  • D_OUT has a high degree of consistency with the first delay signal used to delay again, ensuring that when obtaining the total delay amount for obtaining the code value Code, the total delay amount to the first signal Data_TDC is the delay conversion of each stage
  • the code value Code obtained based on the sum of the preset delays of the unit 112 has high reliability.
  • the second delay unit 1102 includes a first terminal and a second terminal, respectively used for inputting the first delay signal to the delay conversion unit 112 of the next level, and for For inputting the first delay signal to the comparison conversion unit, two second delay units 1102 with the same second delay amount are used, so that the transmitted first delay signal has higher integrity.
  • the delay unit 11 may also include only one second delay unit 1102, wherein the first end of the second delay unit 1102 is connected to the first end of the delay conversion unit 112 of the next stage.
  • the delay unit 1101 is used to input the first delay signal to the delay conversion unit 112 of the next stage, and the second end is connected to the comparison conversion unit 112, and is used to input the first delay signal to the comparison conversion unit.
  • the first delay unit 1101 includes a first NAND gate, one input end of the first NAND gate is connected to the power supply voltage, and the other end receives the delayed output of the delay conversion unit 112 of the previous stage.
  • the second delay unit 1102 includes a second NAND gate.
  • One input end of the second NAND gate is connected to the power supply voltage VDD, and the other input end is connected to the output end of the first delay unit 1101. The output end provides The first delayed signal.
  • the working principle of the NAND gate is: when any input terminal of the NAND gate circuit receives a low level, the output terminal of the NAND gate circuit is a high level; if both input terminals of the NAND gate circuit receive a high level If it is flat, the output terminal of the NAND gate circuit outputs a high level.
  • one input terminal of the first NAND gate is connected to the power supply voltage, that is, one input terminal of the first NAND gate is connected to a high level, therefore, when the first signal Data_TDC input to the other input terminal is a low level, the first NAND gate The output terminal of the NOT gate outputs a high level; when the first signal Data_TDC input to the other input terminal is a high level, the output terminal of the first NAND gate outputs a low level, which is equivalent to the pair of the first NAND gate and the first NAND gate.
  • a signal Data_TDC acts as an inverter.
  • One input terminal of the second NAND gate is also connected to the power supply voltage, that is, a high level is also input.
  • the second NAND gate is equivalent to inverting the first signal Data_TDC delayed by the first NAND gate again, so that the edge of the first delayed signal output by the second NAND gate is still in line with the first signal.
  • the edges of signal Data_TDC are the same. Since the first signal Data_TDC undergoes the logical operation of the first NAND gate and the second NAND gate, the transmission speed of the first signal Data_TDC is slowed down, that is, it plays a buffering role in the transmission of the first signal Data_TDC, thereby playing a role in buffering the transmission of the first signal Data_TDC.
  • the delay effect on the edge of the first signal Data_TDC may, for example, delay the rising edge of the first signal Data_TDC.
  • the first delay unit 1101 may also be other logic gate circuits, such as an inverter.
  • the comparison conversion unit is further configured to: if the characterization signal is a logic low level, the edge of the characterization second signal CLK_TDC is not later than the edge of the first delayed signal; if the characterization signal includes a logic high level pulse, it means that the edge of the second signal CLK_TDC is later than the edge of the first delayed signal. That is to say, when the first signal is not delayed, the edge time of the first signal is earlier than the edge time of the second signal. In this way, the difference value between the edges of the first signal and the second signal CLK_TDC can be used to determine Determine the phase difference between the reference clock signal and the feedback clock signal.
  • the edge of the second signal CLK_TDC is earlier than the edge of the first delay signal or is the same as the edge of the first delay signal.
  • Edge alignment that is, after delay processing, the edge moment of the first delayed signal is delayed, so that the edge difference between the second signal CLK_TDC and the first delayed signal is reduced, so the delay processing of the first delayed signal can no longer be continued.
  • the logic level representing the signal includes a logic high level pulse, that is, the logic level representing the signal will jump from low level to high level at a certain moment, then it is considered that the edge moment of the second signal CLK_TDC is later than
  • the edge moment of the first delayed signal that is, the edge difference between the first delayed signal and the second signal CLK_TDC is still large, and the first delayed signal needs to continue to be delayed.
  • the comparison conversion unit 12 includes: a logic operation circuit 1201 that receives the first delay signal and the second signal CLK_TDC, and is used to perform a NAND operation on the first delay signal and the second signal CLK_TDC and perform a NAND operation on the first delay signal and the second signal CLK_TDC.
  • the operation result output represents the signal. Specifically, if the edge of the second signal CLK_TDC is later than the edge of the first delay signal, it means that there is a time when the second signal CLK_TDC and the first delay signal are both logic high levels at the same time, and the logic operation circuit 1201 performs the operation on the first delay signal.
  • the logical NAND operation result of the delayed signal and the second signal CLK_TDC is a level signal including a logic high level pulse
  • the representation signal output according to the operation result of the logical NAND operation is a level signal including a logic high level pulse. That is, the representation signal is 1; if the edge of the second signal CLK_TDC is not later than the edge of the first delay signal, it means that there is no situation where the second signal CLK_TDC and the first delay signal are both high levels at the same time.
  • the logic operation circuit 1201 The result of the logic operation on the first delay signal and the second signal CLK_TDC is a logic high level signal.
  • the representation signal obtained according to the operation result of the logic NAND operation is a logic low level signal, that is, the representation signal The signal is 0.
  • the logic operation circuit 1201 includes: a first PMOS transistor MP1, the gate of the first PMOS transistor MP1 receives the first delay signal, and the source of the first PMOS transistor MP1 is connected to the power node, and the drain
  • the gate of the second PMOS tube MP2 receives the second signal CLK_TDC, the source of the second PMOS tube MP2 is connected to the power node, and the drain of the second PMOS tube MP2 is connected to the output node;
  • One NMOS transistor MN1, the drain is connected to the output node NET; the second NMOS transistor MN2, the drain is connected to the source of the first NMOS transistor MN1, and the source is connected to the ground; wherein, the first NMOS transistor MN1 and the second NMOS transistor MN2
  • the gate of one receives the second signal CLK_TDC, and the gate of the other receives the first delay signal.
  • the logic operation circuit 1201 further includes a third PMOS transistor MP3.
  • the gate of the third PMOS transistor MP3 receives the enable signal LRSTB, and the third PMOS transistor MP3 is turned on in response to the enable signal LRSTB.
  • the third PMOS transistor MP3 The source of the tube MP3 is connected to the power node, and the drain is connected to the source of the first PMOS tube MP1.
  • the second signal CLK_TDC is inverted with the first signal Data_TDC, that is, the second signal CLK_TDC is inverted with the first delay signal.
  • the edge of the second signal CLK_TDC is later than the edge of the first delay signal, for example, before time T1, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off.
  • the output node NET outputs the logic A high level signal, the logic level is "1"; at time T1, the pulse level signal of the first delayed signal jumps from low level to high level, at time T2, the level of the second signal CLK_TDC level only jumps from high level to low level.
  • the level of the first delayed signal is the same as the logic level of the second signal CLK_TDC, and both are high level. That is, during the period T1-T2, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on. According to the operation result of the logic operation, the output node NET outputs a logic low level signal, and the logic level is "0". Outside the T1-T2 time, the level of the first delay signal and the logic level of the second delay signal are different, so that the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off. According to the operation result of the logic operation, the output node NET outputs a logic high level signal, and the logic level is "1".
  • the edge time of the second signal CLK_TDC is not later than the edge time of the first delayed signal
  • the edge time of the second signal CLK_TDC is earlier than the edge time of the first delayed signal
  • the level of the second signal CLK_TDC jumps from high level to low level.
  • the level of the first delayed signal The edge transitions from low level to high level.
  • the level of the second signal CLK_TDC is high level, the level of the first delayed signal is low level, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, and according to the logic operation
  • the operation result causes the output node NET to output a logic high-level pulse signal, and the logic level is "1"; during the period of T2-T3, the level of the second signal CLK_TDC is low level, and the first delayed signal level is low, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, causing the output node NET to output a logic high-level pulse signal, and the logic level is "1"; after time T3, the second signal CLK_TDC The level of is low level, the level of the first delayed signal is high level, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, so that the output node NET outputs a logic high level pulse signal, and the logic level is "1
  • the output representation signal is 0, which can represent the first signal after delay processing.
  • the edge time of the second signal CLK_TDC is made earlier than the edge time of the first delayed signal.
  • the level of the first delay signal is the same as the pulse level signal of the second signal, and both are logic high levels.
  • the first NMOS transistor MN1 and the second NMOS transistor MN2 will be turned on.
  • the source of tube MP3 is transmitted to the output node NET, which can prevent the problem of voltage division between the first NMOS tube MN1 and the second NMOS tube MN2, ensuring that the output node NET outputs a logic low level pulse signal, and the logic low level is "0 ”, and then through the NAND operation result of the logic operation circuit, the output representation signal is 1, which is used to represent that the edge of the second signal CLK_TDC is later than the edge of the first delay signal.
  • the edge time of the second signal CLK_TDC is earlier than the edge time of the first delayed signal, before time T2, the level of the second signal CLK_TDC is high level, and the level of the first delayed signal is low level.
  • the NMOS transistor MN1 and the second NMOS transistor MN2 are turned off.
  • the first PMOS transistor MP1 is turned on in response to the low-level first delay signal D_OUT, and the second PMOS transistor MP2 is turned off in response to the high-level second signal CLK_TDC, so that the signal of the power node is transmitted from the source of the third PMOS transistor MP3 is transmitted to the drain of the third PMOS transistor MP3, and transmitted to the output node NET via the source and drain of the first PMOS transistor MP1, so that the output node NET outputs a logic high level pulse signal, and the logic level is "1 ".
  • the level of the second signal CLK_TDC is low level
  • the level of the first delayed signal is low level
  • the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off
  • the first PMOS transistor MP1 is turned on in response to the low-level first delay signal D_OUT
  • the second PMOS transistor MP2 is turned on in response to the low-level second signal CLK_TDC, so that the signal of the power node is transmitted from the source of the third PMOS transistor MP3 to
  • the drain of the third PMOS transistor is transmitted to the output node NET via the source and drain of the first PMOS transistor MP1 and the second PMOS transistor MP2, so that the output node NET outputs a logic high level pulse signal, and the logic level is "1".
  • the level of the second signal CLK_TDC is low level
  • the level of the first delay signal is high level
  • the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off
  • the first PMOS transistor MP1 responds to the high level.
  • the first delay signal D_OUT of low level is turned off, and the second PMOS transistor MP2 is turned on in response to the second signal CLK_TDC of low level, so that the signal of the power node is transmitted from the source of the third PMOS transistor MP3 to the third PMOS transistor MP3
  • the drain of the second PMOS transistor MP2 is transmitted to the output node NET through the source and drain of the second PMOS transistor MP2, so that the output node NET outputs a logic high level pulse signal, and the logic level is "1". That is to say, when the logic pulse signal level output by the output node NET is always a high-level pulse signal, it can mean that after the first signal is delayed, the edge moment of the second signal CLK_TDC is earlier than the edge of the first delayed signal. time.
  • the logic operation circuit 1201 also includes: a latch 1203, the input terminal is connected to the output node NET; an even number of series-connected inverters 1204 connected to the output terminal of the latch 1203, the inverter of the last stage Device 1204 outputs a representation signal. That is to say, the level signal output by the output node NET will be latched in the latch 1203, so that the level signal output through the output terminal of the latch 1203 is relatively stable.
  • the principle of the inverter is: when the input terminal of the inverter receives a high level, the output terminal is a low level; when the input terminal of the inverter receives a low level, the output terminal is a high level.
  • the level signal passes through an even number of series-connected inverters 1204, the level of the output level signal will not change. Since the level signal has gone through the logical operation of multiple inverters, it plays a buffering role in the transmission of the level signal, which makes the level signal last longer and is conducive to the output of stable representation signals.
  • the latch 1203 may be composed of two inverters connected end to end. Among them, the input end of one inverter is connected to the output node NET for receiving the level signal from the output node NET, the output end of the inverter is connected to the input end of the other inverter, and the output end of the inverter is also Used to connect the input end of the first stage inverter in an even number of series-connected inverters. That is to say, one inverter in the latch 1203 also plays the role of inverting, so that the number of inverters connected in series is an odd number.
  • the output node NET outputs a logic high level pulse signal.
  • the output representation signal will be A pulse signal with a logic low level makes the code value 0.
  • the logic level pulse signal output by the output node NET jumps from a high-level pulse level signal to a low-level pulse level signal, After the logic operation of the latch 1203 and the inverter, the output representation signal is a level signal including a logic high level pulse, and the code value is 1.
  • the latch and an even number of series-connected inverters may not be provided in the logic operation circuit, so that the logic operation circuit receives the first delay signal and the second signal CLK_TDC for processing.
  • the first delay signal and the second signal CLK_TDC perform an AND operation and output a representation signal according to the operation result, where the representation signal is output by the output node.
  • the comparison conversion unit may also include: a fourth PMOS transistor MP4 , a third NMOS transistor MN3 and a fourth NMOS transistor MN4 .
  • the input terminal of the latch 1203 is connected to the output node NET; an even number of series-connected inverters 1204 are connected to the output terminal of the latch 1203, and the last stage inverter 1204 outputs a representative signal.
  • the gate of the fourth PMOS transistor MP4 receives the enable signal LRSTB, the source of the fourth PMOS transistor MP4 is connected to the power node, and the drain is connected to the output node NET.
  • the drain of the third NMOS transistor MN3 is connected to the output node NET
  • the drain of the fourth NMOS transistor MN4 is connected to the source of the third NMOS transistor MN3
  • the source is connected to the ground. That is to say, the third NMOS transistor MN3 is in a continuously conducting state in response to the low-level enable signal LRSTB.
  • the number of transistors in the logic operation circuit 1201 can be saved.
  • the logic operation circuit 1201 only includes: the fourth PMOS transistor MP4, the third NMOS transistor MN3 and the fourth NMOS transistor MN4.
  • the working principle of the circuit is as follows:
  • edge time of the second signal CLK_TDC When the edge time of the second signal CLK_TDC is aligned no later than the edge time of the first delayed signal, there are two situations: namely, the edge time of the second signal CLK_TDC is earlier than the edge time of the first delayed signal; and the edge time of the second signal CLK_TDC The edge time is aligned with the edge time of the first delayed signal.
  • the edge time of the second signal CLK_TDC is earlier than the edge time of the first delayed signal, before time T2, the level of the second signal CLK_TDC is high level, the level of the first delayed signal is low level, and the third The NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, and the level of the output node NET is pulled to be consistent with the power supply voltage, so that the output node NET outputs a logic high-level pulse signal, and the logic level is "1"; during T2-T3 During this period, the level of the second signal CLK_TDC is low level, the level of the first delayed signal is low level, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, and the level of the output node NET is pulled.
  • the logic level is "1"; after the T3 moment, the level of the second signal CLK_TDC is low level, and the level of the first delayed signal is high level, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, and the level of the output node NET is pulled to be consistent with the power supply voltage, so that the output node NET has a logic high level pulse signal, and the logic level is "1 ".
  • the logic level pulse signal output by the output node NET is always a high-level pulse signal, it can mean that after the first signal is delayed, the edge moment of the second signal CLK_TDC is earlier than the edge of the first delayed signal. time.
  • the output node NET When the edge moments of the second signal CLK_TDC and the first delay signal are aligned, that is, the logic levels of the second signal CLK_TDC and the first delay signal are always opposite, so that one of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 In a non-conducting state, the output node NET outputs a logic high level pulse signal, thereby indicating that the edges of the second signal CLK_TDC and the first delay signal are aligned.
  • the gate of the third NMOS transistor MN3 may receive the first delay signal
  • the gate of the fourth NMOS transistor MN4 may receive the second signal CLK_TDC.
  • the gate of the third NMOS transistor MN3 may also receive the second signal CLK_TDC, and the gate of the third NMOS transistor MN3 may receive the first delay signal.
  • the third NMOS transistor MN3 and the fourth NMOS transistor MN4 when actually selecting the third NMOS transistor MN3 and the fourth NMOS transistor MN4, it is necessary to set the resistance of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 to be smaller, thereby preventing the occurrence of
  • the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fourth PMOS transistor MP4 are turned on at the same time, the partial voltage of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 is too large, resulting in a large partial voltage of the output node NET. , making it impossible to determine whether the logic level of the output node is high level or low level.
  • the conversion circuit 102 includes N cascaded delay conversion units 112 , and each stage of the delay conversion unit 112 can receive a delayed first signal output by the delay conversion unit 112 of the previous stage.
  • Data_TDC and delays the received first signal Data_TDC by a preset delay amount to generate a first delayed signal.
  • the preset delay amount for delaying the delayed first signal Data_TDC by each delay conversion unit 112 may be different.
  • the preset delay amount of each stage of delay conversion unit 112 may be t1, t2,...tn,...tN, where n ⁇ N.
  • each stage delay conversion unit 112 will compare the first delayed signal with the second signal CLK_TDC and output a representative signal.
  • the characterizing signal may be represented by a Q value.
  • the representation signal obtained by the logic operation circuit based on the operation result of the logical NAND operation is a level signal including a logic high level pulse, that is, the representation signal is 1.
  • the Q value may be 1.
  • the representation signal obtained by the logic operation circuit based on the operation result of the logical NAND operation is a logic low level signal, that is, the representation signal is a logic low level signal.
  • a flat level signal represents a signal of 0, so it can be represented by a Q value of 0.
  • the delay conversion unit 112 of each stage will obtain a Q value after delaying by the preset delay amount, and when the edge of the second signal CLK_TDC is earlier than the edge of the first delayed signal, the obtained Q value is 1. Until the edge of the second signal CLK_TDC is no later than the edge of the first delayed signal, the Q value becomes 0. Therefore, when it is necessary to obtain the total delay amount for the first signal Data_TDC, the preset delay amounts of the delay conversion unit 112 corresponding to all effective Q values can be added, where the effective Q value is 1 and the second signal is A delayed signal has a Q value of 0 when the edges are aligned.
  • the second-stage delay conversion unit 112 delays the delayed first signal Data_TDC1 output by the upper-stage delay conversion unit 112 by a preset delay amount t2.
  • the delayed first signal Data_TDC1 The rising edge of the first signal Data_TDC2 is earlier than the rising edge of the second signal CLK_TDC.
  • the above process is repeatedly executed until the n-th stage delay conversion unit 112 delays the delayed first signal Data_TDCn output by the previous stage delay conversion unit 112 by the preset delay amount tn, and the representation signal output by the comparison conversion unit 12 is recorded as Q.
  • the subsequent rising edge of the first signal Data_TDCn is not earlier than the rising edge of the second signal CLK_TDC.
  • the N cascaded delay conversion units 112 continue to operate, that is, the N cascaded delay conversion units 112 continue to delay the delayed first signal, so that the rising edge of the delayed first signal Continuously being delayed will cause the final output first delayed signal to eventually become a low level signal.
  • the signal input to the gate of one of the first NMOS transistor MN1 or the second NMOS transistor MN2 is a continuous low-level signal, so that the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, that is, the output
  • the logic high level pulse signal of node NET has a logic level of 1. After inversion, a logic low level pulse signal is output, so that the logic level representing the signal is 0, that is, the Q value is 0.
  • the actual delay amount corresponding to the code value Code is the effective Q value corresponding to The sum of the preset delay amounts of the delay conversion unit 112.
  • the Q value obtained by the delay conversion unit 112 continuing to delay the first delayed signal is considered to be an invalid Q value. It can be seen from this that even if N cascaded delay conversion units 112 continue to delay the delayed first signal, the accuracy of the obtained code value Code will not be affected.
  • the delay conversion unit 112 of each stage has the same preset delay amount. That is, the first signal Data_TDC is delayed with the same preset delay amount. In this way, when it is necessary to obtain the total delay amount for the first signal Data_TDC, only the preset delay amount is multiplied by the number of delays, which is beneficial to Simplify computing design. It can be understood that in other embodiments, the delay conversion unit 112 of each stage can also have different preset delay amounts to flexibly adapt to different delay requirements, which is beneficial to improving the compensation delay efficiency of the first signal Data_TDC. .
  • the first signal Data_TDC is delayed at least once through the conversion circuit 102 so that the edges of the first signal Data_TDC and the second signal CLK_TDC are aligned, that is, through delay, the feedback
  • the phase difference between the clock signal CLKFB and the reference clock signal CLKREF is consistent.
  • the edge difference between the first signal Data_TDC and the second signal CLK_TDC after each delay can be compared, and a code value Code is output.
  • the code value Code represents the actual delay amount of the feedback clock signal CLKFB compared to the reference clock signal CLKREF.
  • the delay locked loop can accurately compensate the reference clock signal CLKREF based on the amount of delay that will actually be generated by the reference clock signal CLKREF, thereby causing the phase between the output received feedback clock signal CLKFB and the reference clock signal CLKREF to decrease or is 0, it can not only improve the accuracy of the delay-locked loop to compensate for the time delay, but also compensate for the delay based on the amount of delay actually generated by the reference clock signal CLKREF, thereby reducing the delay-locked loop's effect on the reference clock signal.
  • the number of delays of CLKREF thereby improving the efficiency of delay-locked loop compensation for time delays.
  • an embodiment of the present disclosure also provides a delay locked loop circuit, with reference to Figure 11, including: a first delay circuit 1 configured to receive a reference clock signal CLKREF and delay the reference clock signal CLKREF based on the first control signal. , to generate a first delayed clock signal; the second delay circuit 2 is configured to receive the first delayed clock signal and delay the first delayed clock signal based on the second control signal to generate a second delayed clock signal, the second delayed The delay precision of the circuit 2 is greater than the delay precision of the first delay circuit 1; the replication circuit 3 is configured to delay the second delay clock signal to generate the feedback clock signal CLKFB; the delay control circuit 4 is configured to, based on the reference The phase difference between the clock signal CLKREF and the feedback clock signal CLKFB adjusts the first control signal and the second control signal, and provides the first control signal and the second control signal to the first delay circuit 1 and the second delay circuit 2 respectively.
  • the delay detection circuit 5 provided in the above embodiment, the delay detection circuit 5 is also configured to generate a third control signal corresponding to the actual delay amount based on the code value Code, and provide the third control signal to the first delay circuit 1 , the first delay circuit 1 also delays the reference clock signal CLKREF based on the third control signal.
  • the reference clock signal CLKREF may be generated by the signal generation circuit 6, which is electrically connected to the duty cycle adjustment circuit.
  • a duty cycle adjustment circuit 7 is also included.
  • the duty cycle adjustment circuit 7 receives the reference clock signal CLKREF and is used to adjust the duty cycle of the reference clock signal CLKREF to 50%, which is beneficial to the first delay circuit. 1 and the second delay circuit 2 perform compensation delay on the reference clock signal CLKREF. Based on this, the first delay circuit 1 first performs a compensation delay on the reference clock signal CLKREF and outputs the first delayed clock signal; the second delay circuit 2 then performs another compensation delay on the first delayed clock signal and outputs a second delayed clock signal.
  • the compensation amount of the first delay circuit 1 for the reference clock signal CLKREF is greater than the compensation amount of the second delay circuit 2 for the reference clock signal CLKREF. That is, the first delay circuit 1 performs coarse adjustment on the reference clock signal CLKREF, and the second delay circuit 2 performs fine adjustment on the reference clock signal CLKREF, so that the reference clock signal CLKREF can be accurately compensated.
  • a feedback clock signal CLKFB is generated, and the feedback clock signal CLKFB has the same phase as the second delayed clock signal.
  • the delay control circuit 4 is used to compare the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB, and obtain the first control signal and the second control signal based on the phase difference.
  • the first control signal is used to input the first delay circuit 1, So that the first delay circuit 1 performs delay compensation on the reference clock signal CLKREF in response to the first control signal, and outputs the first delayed clock signal;
  • the second control signal is used to input the second delay circuit 2, so that the second delay circuit 2 Delay compensation is performed on the first delayed clock signal in response to the second control signal, and a second delayed clock signal is output.
  • a feedback clock signal CLKFB is generated, and then the delay control circuit 4 compares the phase difference between the reference clock signal CLKREF and the feedback clock signal CLKFB again, and repeats the above steps until the reference The clock signal CLKREF has the same phase as the feedback clock signal CLKFB.
  • the delay detection circuit 5 is electrically connected to the replica circuit 3, receives the feedback clock signal CLKFB output by the replica circuit 3, and converts the phase difference between the feedback clock signal CLKFB and the reference clock signal CLKREF into the first signal Data_TDC and the second signal CLK_TDC. The difference between edges.
  • the first signal Data_TDC is then delayed at least once through the conversion circuit 102, so that the edges of the first signal Data_TDC and the second signal CLK_TDC are aligned. And compare the edge difference between the first signal Data_TDC and the second signal CLK_TDC after each delay, obtain the code value Code, and input the code value Code into the first delay circuit 1, so that the first delay circuit 1 pairs
  • the reference clock signal CLKREF is delayed.
  • the code value Code represents the actual delay amount of the feedback clock signal CLKFB compared to the reference clock signal CLKREF.
  • the first delay circuit 1 can accurately perform the delay amount on the reference clock signal CLKREF based on the actual delay amount that the reference clock signal CLKREF will produce. compensation, so that the phase between the output received feedback clock signal CLKFB and the reference clock signal CLKREF decreases or becomes 0.
  • the first control signal is used to input the first delay circuit 1
  • the second control signal is used to input the second delay circuit 2, so that the first delay circuit 1 and the second delay circuit 2 respond respectively.
  • setting the delay detection circuit 5 can not only improve the accuracy of the delay locked loop in compensating the time delay, but also because only the code value needs to be
  • the Code is input to the first delay circuit 1 so that the first delay circuit 1 delays the reference clock signal CLKREF, thereby reducing the number of delays of the delay-locked loop on the reference clock signal CLKREF, thereby improving the efficiency of the delay-locked loop in compensating for time delays.
  • an embodiment of the present disclosure also provides a storage device, including: the delay locked loop circuit provided in the above embodiment, the delay locked loop circuit receives the reference clock signal CLKREF and outputs an output clock signal in the same phase as the reference clock signal CLKREF.
  • the memory cells may be DRAM memory cells.

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Abstract

本公开实施例涉及半导体领域，特别涉及一种延迟锁相环的延迟检测电路、延迟锁相环电路及存储装置，延迟锁相环的延迟检测电路包括：相位检测器，被配置为，接收反馈时钟信号以及参考时钟信号，并输出第一信号和第二信号，第一信号的边沿与第二信号的边沿之间的差异表征反馈时钟信号与参考时钟信号之间的相位差；转换电路，被配置为，接收第一信号以及第二信号，对第一信号进行至少一次延迟，比较每次延迟后的第一信号与第二信号的边沿差异，并输出代码值，代码值表征最后一次延迟的第一信号相较于第一信号的实际延迟量。

Description

延迟锁相环的延迟检测电路、延迟锁相环电路及存储装置
交叉引用
本公开要求于2022年07月15日递交的名称为“延迟锁相环的延迟检测电路、延迟锁相环电路及存储装置”、申请号为202210836699.X的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种延迟锁相环的延迟检测电路、延迟锁相环电路及存储装置。
背景技术
时钟信号被广泛的用于同步半导体器件的操作时序的信号，当从外部装置施加的时钟信号被用于半导体器件内部时，半导体器件的内部电路可能会引起时间延迟问题。因此，通通常会在半导体器件中集成延迟锁相环，延迟锁相环可以用于补偿时间延迟，以使半导体器件内部的时钟信号与外部输入的时钟信号同步。
然而，目前的延迟锁相环补偿时间延迟的效率较低。
发明内容
本公开实施例提供一种延迟锁相环的延迟检测电路，包括：相位检测器，被配置为，接收反馈时钟信号以及参考时钟信号，并输出第一信号和第二信号，第一信号的边沿与第二信号的边沿之间的差异表征反馈时钟信号与参考时钟信号之间的相位差；转换电路，被配置为，接收第一信号以及第二信号，对第一信号进行至少一次延迟，比较每次延迟后的第一信号与第二信号的边沿差异，并输出代码值，代码值表征最后一次延迟的第一信号相较于第一信号的实际延迟量。
在一些实施例中，相位检测器还被配置为：接收初始信号，响应于反馈时钟信号对初始信号进行采样，并输出第一信号；响应于参考时钟信号对第一互补信号进行采样，并输出第二信号，第一互补信号与第一信号互为反相信号。
在一些实施例中，相位检测器包括：第一采样电路，被配置为，接收初始信号，响应于反馈时钟信号对初始信号进行采样，并输出第一信号以及第一互补信号；第二采样电路，被配置为，接收第一互补信号，响应于参考时钟信号对第一互补信号进行采样，并输出第二信号。
在一些实施例中，第一采样电路包括：多个级联的第一触发器，每一级第一触发器的时钟信号端接收反馈时钟信号，每一级第一触发器的数据输入端连接上一级第一触发器的第一输出端，第一级的第一触发器的数据输入端接收初始信号，最后一级的第一触发器的第一输出端以及第二输出端分别输出第一信号以及第一互补信号；第二采样电路包括第二触发器，第二触发器的数据输入端连接最后一级的第一触发器的第二输出端，第二触发器的时钟信号端接收参考时钟信号。
在一些实施例中，转换电路包括：N个级联的延迟转换单元，延迟转换单元被配置为，接收上一级的延迟转换单元输出的延迟后的第一信号，以预设延迟量延迟接收到的第一信号以生成第一延迟信号，并输出第一延迟信号至下一级的延迟转换单元，其中，处于首级的延迟转换单元接收的第一信号由相位检测器提供；延迟转换单元还被配置为，比较第二信号与第一延迟信号之间的边沿差异， 并输出表征信号，表征信号表征第二信号的边沿是否不晚于第一延迟信号的边沿，其中代码值基于每一级延迟转换单元的表征信号获得。
在一些实施例中，延迟转换单元包括：延迟单元，被配置为，接收前一级的延迟转换单元输出的第一信号，以预设延迟量延迟第一信号并输出第一延迟信号，其中，处于首级的延迟转换单元的延迟单元接收的第一信号由相位检测器提供；比较转换单元，被配置为，接收第一延迟信号，并比较第二信号与第一延迟信号之间的边沿差异，输出表征信号。
在一些实施例中，延迟单元包括：第一延迟单元，被配置为，接收前一级的延迟转换单元输出的延迟后的第一信号，以第一延迟量延迟第一信号并生成子延迟信号；第二延迟单元，被配置为，接收子延迟信号，以第二延迟量延迟子延迟信号以生成输出第一延迟信号。
在一些实施例中，延迟单元包括两个相同第二延迟量的所述第二延迟单元，其中，一第二延迟单元的输出端连接至下一级的延迟转换单元的第一延迟单元，另一第二延迟单元的输出端连接至比较转换单元。
在一些实施例中，第一延迟单元包括第一与非门，第一与非门的一输入端连接电源电压，另一端接收前一级的延迟转换单元输出的延迟后的第一信号；第二延迟单元包括第二与非门，第二与非门的一输入端连接电源电压，另一输入端与第一延迟单元的输出端连接，输出端提供第一延迟信号。
在一些实施例中，比较转换单元还被配置为，若表征信号为逻辑低电平，则表征第二信号的边沿不晚于第一延迟信号的边沿；若表征信号包括逻辑高电平的脉冲，则表征第二信号的边沿晚于第一延迟信号的边沿。
在一些实施例中，比较转换单元包括：逻辑运算电路，接收第一延迟信号和第二信号，用于对第一延迟信号和第二信号进行与非运算并根据运算结果输出表征信号。
在一些实施例中，逻辑运算电路包括：第一PMOS管，第一PMOS管的栅极接收第一延迟信号，且第一PMOS管的源极连接电源节点，漏极连接输出节点；第二PMOS管，第二PMOS管的栅极接收第二信号，第二PMOS管的源极连接电源节点，第二PMOS管的漏极连接输出节点；第一NMOS管，漏极连接输出节点；第二NMOS管，漏极连接第一NMOS管的源极，源极连接地端；其中，第一NMOS管与第二NMOS管中一者的栅极接收第二信号，另一者的栅极接收第一延迟信号。
在一些实施例中，逻辑运算电路还包括第三PMOS管，第三PMOS管的栅极接收使能信号，且第三PMOS管响应于使能信号导通，第三PMOS管的源极连接电源节点，漏极连接第一PMOS管的源极。
在一些实施例中，逻辑运算电路还包括：锁存器，输入端连接输出节点；与锁存器的输出端连接的偶数个串联的反相器，最后一级的反相器输出表征信号。
在一些实施例中，每一级的延迟转换单元具有的预设延迟量相同。
相应地，本公开实施例还提供一种延迟锁相环电路，包括：第一延迟电路，被配置为，接收参考时钟信号，并基于第一控制信号延迟参考时钟信号，以生成第一延迟时钟信号；第二延迟电路，被配置为，接收第一延迟时钟信号，并基于第二控制信号延迟第一延迟时钟信号，以生第二延迟时钟信号，第二延迟电路的延迟精细度大于第一延迟电路的延迟精细度；复制电路，被配置为，延迟第二延迟时钟信号，以生成反馈时钟信号；延迟控制电路，被配置为，基于参考时钟信号与反馈时钟信号之间的相位差，调整第一控制信号以及第二控制信号，并将第一控制信号和第二控制信号分别提供到第一延迟电路以及第二延迟电路；上述任一项所述的延迟检测电路，延迟检测电路还被配置为，基于 代码值生成与实际延迟量相对应的第三控制信号，并将第三控制信号提供到第一延迟电路，第一延迟电路还基于第三控制信号延迟参考时钟信号。
相应地，本公开实施例还提供一种存储装置，包括：上述延迟锁相环电路，延迟锁相环电路接收参考时钟信号并输出与参考时钟信号同相的输出时钟信号。
本公开实施例提供的延迟锁相环的延迟检测电路的技术方案中，通过相位检测器接收反馈时钟信号以及参考时钟信号，并将反馈时钟信号与参考时钟信号之间的相位差转换为第一信号与第二信号的边沿之间的差异；转换电路接收第一信号以及第二信号，并对第一信号进行至少一次延迟，以使第一信号与第二信号的边沿对齐，其中，每一次延迟后，第一信号与第二信号之间的相位差将会更小。基于此，比较每一次延迟后的第一信号与第二信号之间的相位，并输出代码值，代码值表征最后一次延迟的第一信号相较于第一信号的实际延迟量。最后一次延迟的第一信号与第二信号之间的边沿差异较小甚至为0，表示经过延迟后，反馈时钟信号与参考时钟信号之间的相位差减小或者为0，也就是说，代码值表征的是反馈时钟信号相较于参考时钟信号的延迟量。因此，当延迟锁相环基于该代码值对下一次输入的参考时钟信号进行补偿时，可以精确地基于参考时钟信号实际会产生的延迟量对参考时钟信号进行补偿，使得下一次输出的接收反馈时钟信号与参考时钟信号之间的相位接近或者相同，从而提高延迟锁相环补偿时间延迟的效率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领缺普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种延迟锁相环的延迟检测电路的功能框图；
图2为本公开实施例提供的另一种延迟锁相环的延迟检测电路的功能框图；
图3为本公开实施例提供的一种延迟锁相环的延迟检测电路中第一采样电路的电路图；
图4为本公开实施例提供的一种延迟检测电路中的相位检测器进行相位检测的时序图；
图5为本公开实施例提供的一种延迟锁相环的延迟检测电路中第二采样电路的功能框图；
图6为本公开实施例提供的另一种延迟锁相环的延迟检测电路中第二采样电路的功能框图；
图7为本公开实施例提供的另一种延迟锁相环的延迟检测电路中一种第二采样电路的电路图；
图8为本公开实施例提供的另一中延迟锁相环的延迟检测电路中另一种第二采样电路的电路图；
图9为本公开实施例提供的一种延迟锁相环的延迟检测电路中延迟转换单元的电路图；
图10为本公开实施例提供的一种延迟锁相环的延迟检测电路中另一种时序图；
图11为本公开实施例提供的一种延迟锁相环电路的功能框图。
具体实施方式
本公开实施例提供一种延迟锁相环的延迟检测电路，通过相位检测器接收反馈时钟信号以及参考时钟信号，并将反馈时钟信号与参考时钟信号之间的相位差转换为第一信号与第二信号的边沿之 间的差异；转换电路对第一信号进行至少一次延迟，以使第一信号与第二信号的边沿对齐，也就是说，经过延迟后，反馈时钟信号与参考时钟信号之间的相位差相同。比较每一次延迟后的第一信号与第二信号之间边沿差异，输出代码值，代码值表征最后一次延迟的第一信号相较于第一信号的实际延迟量。也就是说，代码值表征的是反馈时钟信号相较于参考时钟信号的延迟量，因此，当延迟锁相环基于该代码值对下一次输入的参考时钟信号进行补偿时，可以精确地基于参考时钟信号实际将产生的延迟量对参考时钟信号进行补偿，使得下一次输出的接收反馈时钟信号可以具有与参考时钟信号相同的相位，从而提高延迟锁相环补偿时间延迟的效率。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1为本公开实施例提供的一种延迟锁相环的延迟检测电路的功能框图。
参考图1，延迟锁相环的延迟检测电路包括：相位检测器101，被配置为，接收反馈时钟信号CLKFB以及参考时钟信号CLKREF，并输出第一信号Data_TDC和第二信号CLK_TDC，第一信号Data_TDC的边沿与第二信号CLK_TDC的边沿之间的差异表征反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位差；转换电路102，被配置为，接收第一信号Data_TDC以及第二信号CLK_TDC，对第一信号Data_TDC进行至少一次延迟，比较每次延迟后的第一信号Data_TDC与第二信号CLK_TDC的边沿差异，并输出代码值Code，代码值Code表征最后一次延迟的第一信号Data_TDC相较于第一信号Data_TDC的实际延迟量。
延迟锁相环用于接收参考时钟信号CLKREF，并对参考时钟信号CLKREF进行延迟补偿，输出经过补偿之后的反馈时钟信号CLKFB。反馈时钟信号CLKFB可以用于施加于半导体器件中，并作为用于同步半导体器件时序操作的信号。因此，延迟锁相环对补偿时间延迟的精确度以及效率要求较高，需要在提高延迟锁相环对补偿时间延迟的精确度的同时，提高延迟锁相环对补偿时间延迟的效率。
基于此，本公开实施例中，通过转换电路102对第一信号Data_TDC进行至少一次延迟，使得第一信号Data_TDC与第二信号CLK_TDC的边沿差异减小或者对齐，即通过延迟，使得反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位差减小或者一致。具体地，比较每一次延迟后的第一信号Data_TDC与第二信号CLK_TDC的边沿差异，并输出代码值Code，代码值Code表征最后一次延迟的第一信号Data_TDC相较于第一信号Data_TDC的实际延迟量，即代码值Code表征反馈时钟信号CLKFB相较于参考时钟信号CLKREF的实际延迟量。如此，使得延迟锁相环可以精确地基于参考时钟信号CLKREF实际将产生的延迟量对参考时钟信号CLKREF进行补偿，从而使得输出的接收反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位接近或者相同，不仅可以提高延迟锁相环对补偿时间延迟的精确度，并且，由于基于参考时钟信号CLKREF实际产生的延迟量来对延迟来进行补偿，从而可以减小延迟锁相环对参考时钟信号CLKREF的延迟次数，进而提高延迟锁相环补偿时间延迟的效率。
在一些实施例中，第一信号Data_TDC以及第二信号CLK_TDC可以是电平信号，且第一信号Data_TDC用于表征反馈时钟信号CLKFB，第二信号CLK_TDC用于表征参考时钟信号CLKREF，如此，可以将反馈时钟信号CLKFB以及参考时钟信号CLKREF之间的相位差转换为电平信号的边沿之间的差异。由于电平信号的边沿时刻较容易获取，使得获取到的电平信号的边沿之间的差异较为准确。因此，采用电平信号的边沿之间的差异表征反馈时钟信号CLKFB以及参考时钟信号CLKREF之间的相位差，可以更准确地表征反馈时钟信号CLKFB与参考时钟信号CLKREF之间的实际相位差异， 使得延迟锁相环对补偿时间延迟的精确度较高。
在另一些实施例中，第一信号Data_TDC也可以用于表征参考时钟信号CLKREF，第二信号CLK_TDC也可以用于表征反馈时钟信号CLKFB。
在一些实施例中，相位检测器101还被配置为：接收初始信号，响应于反馈时钟信号CLKFB对初始信号进行采样，并输出第一信号Data_TDC；响应于参考时钟信号CLKREF对第一互补信号进行采样，并输出第二信号CLK_TDC，第一互补信号与第一信号Data_TDC互为反相信号初始信号为电平信号，因此，响应于反馈时钟信号CLKFB对初始信号进行采样所获取的第一信号Data_TDC也将为电平信号，且第二信号CLK_TDC也为电平信号。第一互补信号与第一信号Data_TDC边沿位置相同，但互为反相信号，即第一互补信号与第一信号Data_TDC的边沿跳变时刻相同，但是跳变方式相反。例如，第一互补信号的边沿跳变时刻为上升沿时，第一信号Data_TDC的边沿跳变时刻为下降沿。第二信号CLK_TDC为基于第一互补信号而获取的，因此，第二信号CLK_TDC的边沿与第一信号Data_TDC的边沿相反，如此，有利于后续采用转换电路102对具有相反边沿的第一信号Data_TDC以及第二信号CLK_TDC进行比较。
第一信号Data_TDC是响应于反馈时钟信号CLKFB对初始信号进行采样而获取的，第二信号CLK_TDC响应于参考时钟信号CLKREF对第一互补信号进行采样获取的，而第一互补信号与第一信号Data_TDC相同，即也是基于对初始信号进行采样获取到的。由此可知，第一信号Data_TDC与第二信号CLK_TDC实际上均为对初始信号进行采样而得到，而第一信号Data_TDC用于表征反馈时钟信号CLKFB，第二信号CLK_TDC用于表征参考时钟信号CLKREF。因此，对第一信号Data_TDC以及第二信号CLK_TDC的边沿差异进行比较而得到的边沿之间的差异可以准确表征反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位差。其中，第一信号Data_TDC与第二信号CLK_TDC的边沿时刻的差异是指第一信号Data_TDC的上升沿时刻与第二信号CLK_TDC的上升沿时刻之间的差异；或者是第一信号Data_TDC的下降沿时刻与第二信号CLK_TDC的下降沿时刻之间的差异。
参考图2，在一些实施例中，相位检测器101包括：第一采样电路111，被配置为，接收初始信号DL_TDCRSTB，响应于反馈时钟信号CLKFB对初始信号DL_TDCRSTB进行采样，并输出第一信号Data_TDC以及第一互补信号Data_TDCB；第二采样电路121，被配置为，接收第一互补信号Data_TDCB，响应于参考时钟信号CLKREF对第一互补信号Data_TDCB进行采样，并输出第二信号CLK_TDC。通过第一采样电路111获取第一信号Data_TDC以及第一互补信号Data_TDCB，使得第一信号Data_TDC以及第一互补信号Data_TDCB为相同的信号，且第一信号Data_TDC与第一互补信号Data_TDCB互为反相信号。第一采样电路111与第二采样电路121分别进行采样以输出第一信号Data_TDC以及第二信号CLK_TDC，可以知道的是，若反馈时钟信号CLKFB和参考时钟信号CLKREF之间存在相位差，则第一信号Data_TDC的边沿早于第二信号CLK_TDC的边沿，即第一信号Data_TDC和第二信号CLK_TDC之间存在同时为逻辑高电平的时刻，第一信号Data_TDC和第二信号CLK_TDC同时为逻辑高电平的时间长度即为反馈时钟信号CLKFB和参考时钟信号CLKREF之间的相位差；若反馈时钟信号CLKFB和参考时钟信号CLKREF之间不存在相位差，则第一信号Data_TDC的边沿与第二信号CLK_TDC的边沿在同一时刻，即第一信号Data_TDC和第二信号CLK_TDC之间不存在同时为逻辑高电平的时刻。如此，可以分别响应于反馈时钟信号CLKFB以及参考时钟信号CLKREF进行采样，使得第一采样电路111与第二采样电路121之间不会相互影响，有利于提高获取的第一信号Data_TDC以及第二信号CLK_TDC的准确度。值得注意的是，反馈时钟信号CLKFB与参考时钟信号CLKREF同时输入于第一采样电路111以及第二采样电路121，使得获取的到的第一信号Data_TDC与第二信号CLK_TDC边沿之间的差异可以准确表征反馈时钟信号CLKFB 与参考时钟信号CLKREF之间的相位差。
参考图3，在一些实施例中，第一采样电路111包括：多个级联的第一触发器113，每一级第一触发器113的时钟信号端接收反馈时钟信号CLKFB，每一级第一触发器113的数据输入端连接上一级第一触发器113的第一输出端，第一级的第一触发器113的数据输入端接收初始信号DL_TDCRSTB，最后一级的第一触发器113的第一输出端以及第二输出端分别输出第一信号Data_TDC以及第一互补信号Data_TDCB；第二采样电路121包括第二触发器122，第二触发器122的数据输入端连接最后一级的第一触发器113的第二输出端，第二触发器122的时钟信号端接收参考时钟信号CLKREF。
第一级的第一触发器113中，数据输入端接收初始信号DL_TDCRSTB，时钟信号端接收反馈时钟信号CLKFB，第一触发器113被配置为，当反馈时钟信号CLKFB的边沿时刻到来时，对初始信号DL_TDCRSTB进行采样，以输出相对应的第一信号Data_TDC。如此，使得第一信号Data_TDC的电平变化可以表征反馈时钟信号CLKFB的相位变化。具体地，每一级的第一触发器113在一个反馈时钟信号CLKFB周期的边沿时刻对初始信号DL_TDCRSTB进行采样。
在一些实施例中，当第一触发器113的数量为4个时，级联的第一触发器113中的第一个第一触发器113接收初始信号DL_TDCRSTB，并在反馈时钟信号CLKFB的边沿时刻到来时，对初始信号DL_TDCRSTB进行采样，输出采样后的初始信号DL_TDCRSTB。第二级第一触发器113接收第一级第一触发器113所输出的采样后的初始信号DL_TDCRSTB，并在反馈时钟信号CLKFB的下一个边沿时刻到来时，对采样后的初始信号DL_TDCRSTB进行采样，其中，边沿时刻可以为反馈时钟信号CLKFB的上升沿，在另一些实施例中，边沿时刻可以为反馈时钟信号CLKFB的下降沿。以此类推，级联的第一触发器113中的最后一个第一触发器113在第4个反馈时钟信号CLKFB边沿时刻到来时，对上一级第一触发器113所输出的采样后初始信号DL_TDCRSTB进行采样，采样后，第一端输出的信号作为第一信号Data_TDC。采用多个级联的第一触发器113对初始信号DL_TDCRSTB进行采样以获取第一信号Data_TDC，可以保证第一触发器113可以在一个完整的反馈时钟信号CLKFB周期的边沿时刻内对初始信号DL_TDCRSTB进行采集，从而使得获取得到的第一信号Data_TDC可以表征反馈时钟信号CLKFB的完整相位。
最后一级第一触发器113的第二端可以是反相输出端口，使得输出第一互补信号Data_TDCB与第一信号Data_TDC反相。
第二触发器122被配置为，当参考时钟信号CLKREF的边沿时刻到来时，对第一互补信号Data_TDCB进行采样，以输出相对应的第二信号CLK_TDC。如此，使得第一信号Data_TDC的电平变化可以表征反馈时钟信号CLKFB的相位变化。具体地，第二触发器122在一个参考时钟信号CLKREF的边沿时刻对初始信号DL_TDCRSTB进行采样。
具体地，在一些实施例中，第一采样电路111对初始信号DL_TDCRSTB进行采样，第二采样电路121对第一互补信号Data_TDCB进行采样的原理可参考图4。
图4为本公开实施例提供的一种延迟检测电路中的相位检测器进行相位检测的时序图。
参考图3以及图4，多个级联的第一触发器113中，每一级第一触发器113响应于反馈时钟信号CLKFB，在每一反馈时钟信号CLKFB边沿时刻的到来时刻对初始信号DL_TDCRSTB进行采样。其中，最后一级第一触发器113在4个反馈时钟信号CLKFB周期中的第4个反馈时钟信号CLKFB边沿时刻的到来时刻对上一级第一触发器113输出的初始信号DL_TDCRSTB进行采样，并输出第一信号Data_TDC，同时，输出第一互补信号Data_TDCB。不难发现，第一互补信号Data_TDCB的边 沿时刻与第一信号Data_TDC的边沿时刻相同，且第一互补信号Data_TDCB与第一信号Data_TDC互为反相信号。在一些实施例中，第一触发器113可以在反馈时钟信号CLKFB的上升沿时刻对初始信号DL_TDCRSTB进行采样。在另一些实施例中，第二触发器122也可以在反馈时钟信号CLKFB周期的下降沿时刻对初始信号DL_TDCRSTB进行采样。
最后一级的第一触发器113的第二端将第一互补信号Data_TDCB传输至第二触发器122，第二触发器122响应于参考时钟信号CLKREF对第一互补信号Data_TDCB进行采样。具体地，第二触发器122在参考时钟信号CLKREF周期到来的时刻，对第一互补信号Data_TDCB进行采样，获取第二信号CLK_TDC。值得注意的是，当第一触发器113在反馈时钟信号CLKFB周期的上升沿时刻对初始信号DL_TDCRSTB进行采样时，第二触发器122也需要在参考时钟信号CLKREF的上升沿时刻对第一互补信号Data_TDCB进行采样。当第二触发器122在反馈时钟信号CLKFB的下降沿时刻对初始信号DL_TDCRSTB进行采样时，第二触发器122也需要在参考时钟信号CLKREF的下降沿时刻对第一互补信号Data_TDCB进行采样，从而保证获取到的第一信号Data_TDC与第二信号CLK_TDC之间的边沿之间的差异可以准确表征反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位差。
由于参考时钟信号CLKREF与反馈时钟信号CLKFB是同时输入第一采样电路111与第二采样电路121，也就是说，第二采样电路121接收来自第一采样电路111的第一互补信号Data_TDCB，参考时钟信号CLKREF也实时输入于第二采样电路121中。如此，当第一互补信号Data_TDCB输入于第二触发器122中时，第二触发器122可以同步响应于参考时钟信号CLKREF对第一互补信号Data_TDCB进行采样，从而使得获取得到的第一信号Data_TDC与第二信号CLK_TDC之间的边沿差异可以准确表征参考时钟信号CLKREF与反馈时钟信号CLKFB之间的相位差异。
在一些实施例中，当反馈时钟信号CLKFB与参考时钟信号CLKREF之间具有相位差时，反馈时钟信号CLKFB的边沿时刻与参考时钟信号CLKREF的边沿时刻之间具有时间延迟。如此，当第二触发器122响应于参考时钟信号CLKREF的边沿时刻对第一互补信号Data_TDCB进行采样时，将经过反馈时钟信号CLKFB的边沿时刻与参考时钟信号CLKREF的边沿时刻之间相差的延迟时间之后，才会对第一互补信号Data_TDCB进行采样，从而使得输出的第二信号CLK_TDC的边沿与第一互补信号Data_TDCB的边沿之间存在时间差，且该时间差可以反映反馈时钟信号CLKFB的边沿时刻与参考时钟信号CLKREF的边沿时刻之间相差的延迟时间。
在另一些实施例中，当反馈时钟信号CLKFB与参考时钟信号CLKREF没有相位差时，由于第一互补信号Data_TDCB是第一触发器113在反馈时钟信号CLKFB的边沿时刻，例如上升沿时刻对初始信号DL_TDCRSTB进行采样得到的。因此，当第一互补信号Data_TDCB输入于第二触发器122的同时，参考时钟信号CLKREF的上升沿时刻正好到来，因此，第二触发器122无需经过反馈时钟信号CLKFB的边沿时刻与参考时钟信号CLKREF的边沿时刻之间相差的延迟时间，便可以同步对第一互补信号Data_TDCB进行采样，使得输出的第一互补信号Data_TDCB的边沿与第二信号CLK_TDC的边沿对齐。
在一些实施例中，在未使用延迟检测电路期间，可以将传输至相位检测器101的反馈时钟信号CLKFB和参考时钟信号CLKREF关闭，即对反馈时钟信号CLKFB和参考时钟信号CLKREF进行门控(clock gating)，门控后的信号分别为门控反馈时钟信号CLKFB_SYSC以及门控参考时钟信号CLKREF_SYSC，对门控反馈时钟信号CLKFB_SYSC以及门控参考时钟信号CLKREF_SYSC进行相位差的检测从而来获得反馈时钟信号CLKFB和参考时钟信号CLKREF之间的相位差，可以减少延迟检测电路所产生的功耗。
在另一些实施例中，第二采样电路121也可以包括多个级联的第二触发器122，且第二触发器122的数量与第一触发器113的数量相等。每一级第二触发器122的时钟信号端接收参考时钟信号CLKREF，且每一级第二触发器122的数据输入端连接上一级第二触发器122的第一输出端，第一级的第二触发器122的数据输入端接收初始信号DL_TDCRSTB，最后一级的第二触发器122输出第二信号CLK_TDC，且第二信号CLK_TDC为经过反相之后的信号，即第二信号CLK_TDC与第一信号Data_TDC的边沿相反。也就是说，第一采样电路111与第二采样电路121同时且分别响应于反馈时钟信号CLKFB与参考时钟信号CLKREF对初始信号DL_TDCRSTB进行采样，并输出第一信号Data_TDC与第二信号CLK_TDC，由于是响应于反馈时钟信号CLKFB与参考时钟信号CLKREF对同一初始信号DL_TDCRSTB进行采样，因此，第一信号Data_TDC与第二信号CLK_TDC的边沿之间的差异可以用于表征反馈时钟信号CLKFB与参考时钟信号CLKREF的相位差。
可以理解的是，在其他实施例中，第一采样电路111可以响应于参考时钟信号CLKREF对初始信号DL_TDCRSTB进行采样以输出第一信号Data_TDC，相应的，第二采样电路121可以响应于反馈时钟信号CLKFB对第一互补信号Data_TDCB进行采样，并输出第二信号CLK_TDC。
转换电路102接收第一信号Data_TDC以及第二信号CLK_TDC，并对第一信号Data_TDC进行至少一次延迟，以使第一信号Data_TDC的边沿与第二信号CLK_TDC的边沿对齐或者是第一信号Data_TDC的边沿晚于第二信号CLK_TDC的边沿，其中，每一次延迟后，第一信号Data_TDC与第二信号CLK_TDC的边沿差异将会更小，使得第一信号Data_TDC与第二信号CLK_TDC的边沿差异较小或者对齐。
参考图5，在一些实施例中，转换电路102包括：N个级联的延迟转换单元，延迟转换单元被配置为，接收上一级的延迟转换单元输出的延迟后的第一信号Data_TDC，以预设延迟量延迟接收到的第一信号Data_TDC以生成第一延迟信号，并输出第一延迟信号至下一级的延迟转换单元，其中，处于首级的延迟转换单元接收的第一信号Data_TDC由相位检测器101提供；延迟转换单元还被配置为，比较第二信号CLK_TDC与第一延迟信号之间的边沿差异，并输出表征信号，表征信号表征第二信号CLK_TDC的边沿是否不晚于第一延迟信号的边沿，其中代码值Code基于每一级延迟转换单元的表征信号获得。也就是说，转换电路可以对第一信号Data_TDC进行延迟得到第一延迟信号，再对第一延迟信号与第二信号CLK_TDC的边沿差异进行比较，如果经过若干级延迟转换单元延时后得到的第一延迟信号的边沿仍早于第二信号CLK_TDC的边沿，即若干级延迟转换单元对第一信号Data_TDC的延迟依旧不够抵消反馈时钟信号CLKFB和参考时钟信号CLKREF之间的相位差；如果经过第n级延迟转换单元延时后得到的第一延迟信号的边沿晚于或等于第二信号CLK_TDC的边沿，则n级延迟转换单元对第一信号Data_TDC的延迟依旧不够抵消反馈时钟信号CLKFB和参考时钟信号CLKREF之间的相位差，此时第1级至第n-1级延迟转换单元每一级输出的表征信号为包括逻辑高电平的电平信号，第n级至第N级延迟转换单元每一级输出的表征信号为逻辑低电平信号即N级延迟转换单元输出的代码值Code前n-1位为1，后N-n+1位为0，得到的代码值code表示反馈时钟信号CLKFB和参考时钟信号CLKREF之间的相位差要大于n-1级延迟转换单元的延迟，且小于或等于n级延迟转换单元的延迟，进而通过得到的代码值code来对反馈时钟信号CLKFB的延时进行粗调，从而调整反馈时钟信号CLKFB和参考时钟信号CLKREF之间的相位差。
具体地，第一级的延迟转换单元112接收来自相位检测器的第一信号Data_TDC0，用于输出延迟后的第一信号Data_TDC1；下一级的延迟转换单元再接收第一信号Data_TDC1并以预设延迟量进行延迟，输出延迟后的第一信号Data_TDC2，以此类推，重复执行上述步骤。
每一级延迟单元均以预设延迟量延迟接收到的第一信号Data_TDC，当延迟单元为N级时， 对第一信号Data_TDC的总的延迟量为预设延迟量×N。而代码值Code基于每一级延迟单元的表征信号获得，也就是说，代码值Code基于对第一信号Data_TDC的总的延迟量获得，从而使得代码值Code可以准确表征最后一次延迟的第一信号Data_TDC相较于第一信号Data_TDC的实际延迟量。当延迟锁相环基于该代码值Code对下一次输入的参考时钟信号CLKREF进行补偿时，可以精确地基于参考时钟信号CLKREF实际会产生的延迟量对参考时钟信号CLKREF进行补偿，使得下一次输出的接收反馈时钟信号CLKFB可以具有与参考时钟信号CLKREF相同的相位，从而提高延迟锁相环补偿时间延迟的效率。
在一些实施例中，延迟转换单元112包括：延迟单元，被配置为，接收前一级的延迟转换单元112输出的第一信号Data_TDC，以预设延迟量延迟第一信号Data_TDC并输出第一延迟信号，其中，处于首级的延迟转换单元112的延迟单元接收的第一信号Data_TDC由相位检测器101提供；比较转换单元，被配置为，接收第一延迟信号，并比较第二信号CLK_TDC与第一延迟信号之间的边沿差异，输出表征信号。
也就是说，延迟单元用于对第一信号Data_TDC进行延迟处理，比较转换单元用于对延迟后的第一信号Data_TDC，即第二信号CLK_TDC的边沿是否不晚于第一延迟信号的边沿进行检测，并以表征信号来表征。在一些实施例中，可以采用不同的逻辑电平信号来表示表征信号。
参考图6，在一些实施例中，延迟单元11包括：第一延迟单元1101，被配置为，接收前一级的延迟转换单元112输出的延迟后的第一信号Data_TDC，以第一延迟量延迟第一信号Data_TDC并生成子延迟信号；第二延迟单元1102，被配置为，接收子延迟信号，以第二延迟量延迟子延迟信号以生成输出第一延迟信号D_OUT。也就是说，每一延迟单元11中，可以包含不同的第一延迟单元1101以及第二延迟单元1102，从而使得第一延迟单元1101与第二延迟单元1102可以分别对第一信号Data_TDC进行延迟，灵活地调整对第一信号Data_TDC的延迟量。
具体地，在一些实施例中，可以改变每一级延迟转换单元112中第一延迟单元1101的数量，以可以改变对第一信号Data_TDC的延迟量，来适应不同的需求。例如，当第一级延迟转换单元112对第一信号Data_TDC进行延迟时，第一延迟单元1101的数量可以较多，从而使得第一级延迟转换单元112对第一信号Data_TDC的延迟量较大，相当于粗调；当第二级延迟转换单元112对延迟后的第一信号Data_TDC再次进行延迟时，第一延迟单元1101的数量可以较少，使得第二级延迟转换单元112对延迟后的第一信号Data_TDC的延迟量较小，相当于细调，从而可以提高对第一信号Data_TDC进行延迟处理的效率。
在一些实施例中，延迟单元11包括两个相同第二延迟量的第二延迟单元1102，其中，一第二延迟单元1102的输出端连接至下一级的延迟转换单元112的第一延迟单元1101，另一第二延迟单元1102的输出端连接至比较转换单元。具体地，一个第二延迟单元1102的输出端用于向下一级的延迟转换单元112提供第一延迟信号，进而进一步对第一信号Data_TDC进行延迟调整，。另一第二延迟单元1102的输出端用于向比较转换单元112传输第一延迟信号，以对第一延迟信号与第二信号CLK_TDC的边沿差异进行检测。
由于两个第二延迟单元1102具有相同的第二延迟量，因此，两个第二延迟单元1102所输出的第一延迟信号D_OUT为相同的信号，如此，可以保证用于检测的第一延迟信号D_OUT与用于进行再次延迟的第一延迟信号具有高度的一致性，确保在获取总的延迟量以用于获取代码值Code时，对第一信号Data_TDC的总的延迟量是每一级延迟转换单元112的预设延迟量之和，基于此得到的代码值Code具有较高的可靠性。
此外，相较于仅采用一个第二延迟单元1102，且第二延迟单元1102包括第一端与第二端，分别用于向下一级的延迟转换单元112输入第一延迟信号，以及用于向比较转换单元输入第一延迟信号而言，采用两个相同第二延迟量的第二延迟单元1102，使得传输的第一延迟信号具有更高的完整性。
可以理解的是，在另一些实施例中，延迟单元11也可以仅包括一个第二延迟单元1102，其中，第二延迟单元1102的第一端连接至下一级的延迟转换单元112的第一延迟单元1101，用于向下一级的延迟转换单元112输入第一延迟信号，第二端连接至比较转换单元112，用于向比较转换单元输入第一延迟信号。
参考图7，在一些实施例中，第一延迟单元1101包括第一与非门，第一与非门的一输入端连接电源电压，另一端接收前一级的延迟转换单元112输出的延迟后的第一信号Data_TDC；第二延迟单元1102包括第二与非门，第二与非门的一输入端连接电源电压VDD，另一输入端与第一延迟单元1101的输出端连接，输出端提供第一延迟信号。与非门的工作原理为：当与非门电路的任一个输入端接收到低电平时，与非门电路的输出端为高电平；若与非门电路的两个输入端接收到高电平，则与非门电路的输出端输出高电平。由于第一与非门的一个输入端连接电源电压，即第一与非门的一个输入端连接高电平，因此，当另一个输入端输入的第一信号Data_TDC为低电平时，第一与非门的输出端即输出高电平；当另一个输入端输入的第一信号Data_TDC为高电平时，第一与非门的输出端即输出低电平，相当于第一与非门对第一信号Data_TDC起到反相作用。
第二与非门的一个输入端也连接电源电压，即也输入高电平。同样地，第二与非门相当于对经第一与非门延迟后的第一信号Data_TDC起到再次反相的作用，使得第二与非门输出的第一延迟信号的边沿仍与第一信号Data_TDC的边沿相同。而由于第一信号Data_TDC经过第一与非门以及第二与非门的逻辑运算之后，使得第一信号Data_TDC的传输速度减慢，即对第一信号Data_TDC的传输起到缓冲作用，从而起到对第一信号Data_TDC的边沿的延迟效果，例如可以延迟第一信号Data_TDC的上升沿。在另一些实施例中，第一延迟单元1101也可以为其它逻辑门电路，例如可以为反相器。
在一些实施例中，比较转换单元还被配置为，若表征信号为逻辑低电平，则表征第二信号CLK_TDC的边沿不晚于第一延迟信号的边沿；若表征信号包括逻辑高电平的脉冲，则表征第二信号CLK_TDC的边沿晚于第一延迟信号的边沿。也就是说，当未对第一信号进行延迟处理时，第一信号的边沿时刻要早于第二信号的边沿时刻，如此，可以利用第一信号与第二信号CLK_TDC边沿之间的差异值来确定参考时钟信号与反馈时钟信号之间的相位差。当表征信号的逻辑电平为低电平时，即表征信号的逻辑电平保持为低电平不变时，认为第二信号CLK_TDC的边沿早于第一延迟信号的边沿或者与第一延迟信号的边沿对齐，即经过延迟处理后，使得第一延迟信号的边沿时刻被延迟，从而使得第二信号CLK_TDC与第一延迟信号的边沿差异减小，因此可以不再继续对第一延迟信号进行延迟处理；当表征信号的逻辑电平包括逻辑高电平的脉冲，即表征信号的逻辑电平在某一时刻会由低电平跳变为高电平，则认为第二信号CLK_TDC的边沿时刻晚于第一延迟信号的边沿时刻，即第一延迟信号与第二信号CLK_TDC之间的边沿差异还是较大，还需要继续对第一延迟信号进行延迟处理。
参考图6，在一些实施例中，比较转换单元12包括：逻辑运算电路1201，接收第一延迟信号和第二信号CLK_TDC，用于对第一延迟信号和第二信号CLK_TDC进行与非运算并根据运算结果输出表征信号。具体地，若第二信号CLK_TDC的边沿晚于第一延迟信号的边沿，则表示第二信号CLK_TDC和第一延迟信号之间存在同时为逻辑高电平的时刻，则逻辑运算电路1201对第一延迟信号和第二信号CLK_TDC的逻辑与非运算结果为包括逻辑高电平脉冲的电平信号，根据逻辑与非运算的运算结果输出的表征信号则为包括逻辑高电平脉冲的电平信号，即表征信号为1；若第二信号CLK_TDC的边沿不晚于第一延迟信号的边沿，则表示第二信号CLK_TDC和第一延迟信号之间不存 在同时为高电平的情况，逻辑运算电路1201对第一延迟信号和第二信号CLK_TDC的逻辑运算结果为逻辑高电平的电平信号，此时根据逻辑与非运算的运算结果得到的表征信号为逻辑低电平的电平信号，即表征信号为0，如此，有利于通过第二信号CLK_TDC的边沿和第一延迟信号的边沿之间的关系获得表征信号，从而基于表征信号获取代码值，进而根据代码值对反馈时钟信号进行延时调整。
参考图7，在一些实施例中，逻辑运算电路1201包括：第一PMOS管MP1，第一PMOS管MP1的栅极接收第一延迟信号，且第一PMOS管MP1的源极连接电源节点，漏极连接输出节点；第二PMOS管MP2，第二PMOS管MP2的栅极接收第二信号CLK_TDC，第二PMOS管MP2的源极连接电源节点，第二PMOS管MP2的漏极连接输出节点；第一NMOS管MN1，漏极连接输出节点NET；第二NMOS管MN2，漏极连接第一NMOS管MN1的源极，源极连接地端；其中，第一NMOS管MN1与第二NMOS管MN2中一者的栅极接收第二信号CLK_TDC，另一者的栅极接收第一延迟信号。
在一些实施例中，逻辑运算电路1201还包括第三PMOS管MP3，第三PMOS管MP3的栅极接收使能信号LRSTB，且第三PMOS管MP3响应于使能信号LRSTB导通，第三PMOS管MP3的源极连接电源节点，漏极连接第一PMOS管MP1的源极。在开始检测反馈时钟信号和参考时钟信号之间的延迟时，使能信号LRSTB为逻辑低电平信号，当结束检测时，使能信号LRSTB为逻辑高电平信号。
由于第二信号CLK_TDC与第一信号Data_TDC反相，即第二信号CLK_TDC与第一延迟信号之间反相。当第二信号CLK_TDC的边沿晚于第一延迟信号的边沿时，例如，在T1时刻之前，使得第一NMOS管MN1以及第二NMOS管MN2截止，根据逻辑运算的运算结果，输出节点NET输出逻辑高电平的电平信号，逻辑电平为“1”；在T1时刻，第一延迟信号的脉冲电平信号从低电平跳变为高电平，在T2时刻，第二信号CLK_TDC的电平才由高电平跳变为低电平。因此，在T1-T2这段时间内，第一延迟信号的电平与第二信号CLK_TDC的逻辑电平相同，且均为高电平，即在T1-T2这段时间内，第一NMOS管MN1以及第二NMOS管MN2导通，根据逻辑运算的运算结果，输出节点NET输出逻辑低电平的电平信号，逻辑电平为“0”。在T1-T2时间之外，第一延迟信号的电平与第二延迟信号的逻辑电平均不相同，使得第一NMOS管MN1以及第二NMOS管MN2截止，根据逻辑运算的运算结果，输出节点NET输出逻辑高电平的电平信号，逻辑电平为“1”。
当第二信号CLK_TDC的边沿时刻不晚于第一延迟信号的边沿时刻时，包括两种情况：即第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻；以及第二信号CLK_TDC的边沿时刻与第一延迟信号的边沿时刻对齐。当第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻时，在T2时刻，第二信号CLK_TDC的电平才由高电平跳变为低电平，在T3时刻，第一延迟信号的边沿由低电平跳变为高电平。也就是说，在T1时刻之前，第二信号CLK_TDC的电平为高电平，第一延迟信号的电平为低电平，第一NMOS管MN1以及第二NMOS管MN2截止，根据逻辑运算的运算结果，使得输出节点NET输出逻辑高电平的脉冲信号，逻辑电平为“1”；在T2-T3这段时间内，第二信号CLK_TDC的电平为低电平，第一延迟信号的电平为低电平，第一NMOS管MN1以及第二NMOS管MN2截止，使得输出节点NET输出逻辑高电平的脉冲信号，逻辑电平为“1”；在T3时刻之后，第二信号CLK_TDC的电平为低电平，第一延迟信号的电平为高电平，第一NMOS管MN1以及第二NMOS管MN2截止，使得输出节点NET输出逻辑高电平的脉冲信号，逻辑电平为“1”。也就是说，当输出节点NET所输出的逻辑电平始终为“1”时，再经过逻辑运算电路的与非运算结果，使得输出的表征信号为0，可以表征第一信号经延迟处理之后，使得第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻。
具体地，当第二信号CLK_TDC的边沿晚于第一延迟信号的边沿时，在T1-T2时刻，第一延迟信号的电平与第二信号的脉冲电平信号相同，且均为逻辑高电平脉冲，即在T1-T2时刻，第一NMOS管MN1以及第二NMOS管MN2将导通。且第一PMOS管MP1响应于逻辑高电平脉冲的第一延迟信号截止，第二PMOS管MP2响应于逻辑高电平脉冲的第一延迟信号截止，从而使得电源节点的信号无法经由第三PMOS管MP3的源极传输至输出节点NET，进而可以防止第一NMOS管MN1与第二NMOS管MN2产生分压的问题，确保输出节点NET输出逻辑低电平的脉冲信号，逻辑低电平“0”，再经过逻辑运算电路的与非运算结果，使得输出的表征信号为1，用于表征第二信号CLK_TDC的边沿晚于第一延迟信号的边沿。
当第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻时，在T2时刻之前，第二信号CLK_TDC的电平为高电平，第一延迟信号的电平为低电平，第一NMOS管MN1以及第二NMOS管MN2截止。第一PMOS管MP1响应于低电平的第一延迟信号D_OUT导通，第二PMOS管MP2响应于高电平的第二信号CLK_TDC截止，使得电源节点的信号由第三PMOS管MP3的源极被传输至第三PMOS管MP3的漏极，并经由第一PMOS管MP1的源极以及漏极传输至输出节点NET，使得输出节点NET输出逻辑高电平的脉冲信号，逻辑电平为“1”。
在T2-T3这段时间内，第二信号CLK_TDC的电平为低电平，第一延迟信号的电平为低电平，第一NMOS管MN1以及第二NMOS管MN2截止，第一PMOS管MP1响应于低电平的第一延迟信号D_OUT导通，第二PMOS管MP2响应于低电平的第二信号CLK_TDC导通，使得电源节点的信号由第三PMOS管MP3的源极被传输至第三PMOS管的漏极，并经由第一PMOS管MP1以及第二PMOS管MP2的源极与漏极传输至输出节点NET，使得输出节点NET输出逻辑高电平的脉冲信号，逻辑电平为“1”。
在T3时刻之后，第二信号CLK_TDC的电平为低电平，第一延迟信号的电平为高电平，第一NMOS管MN1以及第二NMOS管MN2截止，第一PMOS管MP1响应于高电平的第一延迟信号D_OUT截止，第二PMOS管MP2响应于低电平的第二信号CLK_TDC导通，使得电源节点的信号由第三PMOS管MP3的源极被传输至第三PMOS管MP3的漏极，并经由第二PMOS管MP2的源极以及漏极传输至输出节点NET，使得输出节点NET输出逻辑高电平的脉冲信号，逻辑电平为“1”。也就是说，当输出节点NET所输出的逻辑脉冲信号电平始终为高电平脉冲信号，可以表征第一信号经延迟处理之后，使得第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻。
在一些实施例中，逻辑运算电路1201还包括：锁存器1203，输入端连接输出节点NET；与锁存器1203的输出端连接的偶数个串联的反相器1204，最后一级的反相器1204输出表征信号。也就是说，输出节点NET输出的电平信号将被锁存在锁存器1203中，使得经由锁存器1203的输出端输出的电平信号较为稳定。反相器的原理为：当反相器的输入端接收到高电平时，输出端为低电平；当反相器的输入端接收到低电平时，输出端为高电平。因此，当电平信号经由偶数个串联的反相器1204后，输出的电平信号的电平将不变。而由于电平信号经过了多个反相器的逻辑运算，从而对电平信号的传输起到了缓冲的作用，从而使得电平信号的持续时间较长，有利于输出稳定的表征信号。
在一些实施例中，锁存器1203可以由首尾相连的2个反相器构成。其中，一个反相器的输入端连接输出节点NET，用于接收来自输出节点NET的电平信号，反相器的输出端连接另一反相器的输入端，且反相器的输出端还用于连接偶数个串联的反相器中，第一级的反相器的输入端。也就是说，锁存器1203中的一个反相器也起到反相作用，从而使得串联的反相器为奇数个，因此，当电平信号输入锁存器1203后，再由最后一级的方向器输出的表征信号的电平信号将会与输出节点NET的电平信号反相。因此，当第二信号CLK_TDC与第一延迟信号的边沿时刻对齐时，输出节点NET输 出逻辑高电平的脉冲信号，经过锁存器1203以及反相器的逻辑运算之后，输出的表征信号将为逻辑低电平的脉冲信号，使得代码值为0。当第二信号CLK_TDC的边沿早于第一延迟信号的边沿时，输出节点NET所输出的逻辑电平的脉冲信号由高电平脉冲的电平信号跳变为低电平脉冲的电平信号，经过锁存器1203以及反相器的逻辑运算之后，输出的表征信号为包括逻辑高电平脉冲的电平信号，代码值为1。
可以理解的是，在另一些实施例中，逻辑运算电路中也可以不设置锁存器以及偶数个串联的反相器，使得逻辑运算电路接收第一延迟信号和第二信号CLK_TDC，用于对第一延迟信号和第二信号CLK_TDC进行与运算并根据运算结果输出表征信号，其中表征信号由输出节点输出。
参考图8，可以理解的是，在又一些实施例中，比较转换单元也可以包括：第四PMOS管MP4，第三NMOS管MN3以及第四NMOS管MN4。锁存器1203，输入端连接输出节点NET；与锁存器1203的输出端连接的偶数个串联的反相器1204，最后一级的反相器1204输出表征信号。其中，第四PMOS管MP4的栅极接收使能信号LRSTB，第四PMOS管MP4的源极连接电源节点，漏极连接输出节点NET。第三NMOS管MN3的漏极连接输出节点NET，第四NMOS管MN4的漏极连接第三NMOS管MN3的源极，且源极连接地端。也就是说，第三NMOS管MN3响应于低电平的使能信号LRSTB，处于持续导通的状态。如此，可以节省逻辑运算电路1201中晶体管的数量。具体地，锁存器以及反相器的工作原理可参考图7对应的实施例描述，逻辑运算电路1201中仅包括：第四PMOS管MP4，第三NMOS管MN3以及第四NMOS管MN4，逻辑电路的工作原理如下：
当第二信号CLK_TDC的边沿时刻不晚于第一延迟信号的边沿时刻对齐时，包括两种情况：即第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻；以及第二信号CLK_TDC的边沿时刻与第一延迟信号的边沿时刻对齐。
当第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻时，在T2时刻之前，第二信号CLK_TDC的电平为高电平，第一延迟信号的电平为低电平，第三NMOS管MN3以及第四NMOS管MN4截止，输出节点NET的电平被拉至与电源电压一致，使得输出节点NET输出逻辑高电平的脉冲信号，逻辑电平为“1”；在T2-T3这段时间内，第二信号CLK_TDC的电平为低电平，第一延迟信号的电平为低电平，第三NMOS管MN3以及第四NMOS管MN4截止，输出节点NET的电平被拉至与电源电压一致，使得输出节点NET逻辑高电平的脉冲信号，逻辑电平为“1”；在T3时刻之后，第二信号CLK_TDC的电平为低电平，第一延迟信号的电平为高电平，第三NMOS管MN3以及第四NMOS管MN4截止，输出节点NET的电平被拉至与电源电压一致，使得输出节点NET逻辑高电平的脉冲信号，逻辑电平为“1”。也就是说，当输出节点NET输出的逻辑电平脉冲信号始终为高电平脉冲信号时，可以表征第一信号经延迟处理之后，使得第二信号CLK_TDC的边沿时刻早于第一延迟信号的边沿时刻。
当第二信号CLK_TDC与第一延迟信号的边沿时刻对齐时，即第二信号CLK_TDC与第一延迟信号的逻辑电平始终相反，从而使得第三NMOS管MN3与第四NMOS管MN4中的一者处于不导通的状态，使得输出节点NET输出逻辑高电平的脉冲信号，从而表征第二信号CLK_TDC与第一延迟信号的边沿对齐。具体地，在一些实施例中，可以是第三NMOS管MN3的栅极接收第一延迟信号，第四NMOS管MN4的栅极接收第二信号CLK_TDC。在另一些实施例中，也可以是第三NMOS管MN3的栅极接收第二信号CLK_TDC，第三NMOS管MN3的栅极接收第一延迟信号。
可以理解的是，在一些实施例中，在实际选取第三NMOS管MN3与第四NMOS管MN4时，需要设置第三NMOS管MN3与第四NMOS管MN4的电阻较小，从而可以防止发生在第三NMOS 管MN3、第四NMOS管MN4、第四PMOS管MP4同时导通时，第三NMOS管MN3与第四NMOS管MN4处的分压过大，而导致输出节点NET的分压较大，从而无法确定输出节点的逻辑电平为高电平或者低电平的问题。
参考图9，在一些实施例中，转换电路102包括N个级联的延迟转换单元112，每一级延迟转换单元112均可以接收上一级的延迟转换单元112输出的延迟后的第一信号Data_TDC，并以预设延迟量延迟接收到的第一信号Data_TDC以生成第一延迟信号。且每一延迟转换单元112对延迟后的第一信号Data_TDC进行延迟的预设延迟量可以不同。例如，每一级延迟转换单元112的预设延迟量可以为t1、t2、……tn、……tN，其中，n≤N。每一级延迟转换单元112对第一信号Data_TDC以预设延迟量进行延迟后，将会对第一延迟信号与第二信号CLK_TDC进行比较，并输出表征信号。
在一些实施例中，表征信号可以用Q值来表示。当第二信号CLK_TDC的边沿晚于第一延迟信号的边沿时，逻辑运算电路基于逻辑与非运算的运算结果得到的表征信号为包括逻辑高电平脉冲的电平信号，即表征信号为1。基于此，当第二信号CLK_TDC的边沿晚于第一延迟信号的边沿时，Q值可以为1。当第二信号CLK_TDC的边沿不晚于第一延迟信号的边沿时，逻辑运算电路基于逻辑与非运算的运算结果得到的表征信号为逻辑低电平的电平信号，即表征信号为逻辑低电平的电平信号，表征信号为0，因此，可以用Q值为0来表示。
由于每一级的延迟转换单元112以预设延迟量进行延迟后，均会得到一个Q值，且第二信号CLK_TDC的边沿早于第一延迟信号的边沿时，得到的Q值均为1，直至第二信号CLK_TDC的边沿不晚于第一延迟信号的边沿时，Q值变为0。因此，当需要获取对第一信号Data_TDC的总的延迟量时，可以将所有有效Q值对应的延迟转换单元112的预设延迟量相加，其中，有效Q值为1以及第二信号与第一延迟信号的边沿对齐时的Q值0。
具体可对应参考图9以及图10，当第一级延迟转换单元112以预设延迟量t1对第一信号Data_TDC进行延迟后，比较转换单元12输出的表征信号记为Q<1>＝1，即，第一级延迟转换单元112输出的表征信号包括逻辑高电平的脉冲信号，即表征信号为1，表征信号Q<1>＝1对应的延迟后的第一信号Data_TDC1的上升沿相较于第一信号Data_TDC的上升沿延迟了t1时间，此时，延迟后的第一信号Data_TDC1的上升沿早于第二信号CLK_TDC的上升沿。
接着，第二级延迟转换单元112以预设延迟量t2对上一级延迟转换单元112输出的延迟后的第一信号Data_TDC1进行延迟。比较转换单元12输出的表征信号记为Q<2>＝1，即，第二级延迟转换单元112输出的表征信号包括逻辑高电平的脉冲信号，即表征信号为1，表征信号Q<2>＝1对应的延迟后的第一信号Data_TDC2的上升沿相较于表征信号Q<1>＝1对应的延迟后的第一信号Data_TDC1的上升沿延迟了t2时间，此时，延迟后的第一信号Data_TDC2的上升沿早于第二信号CLK_TDC的上升沿。
重复执行上述过程，直至第n级延迟转换单元112以预设延迟量tn对上一级延迟转换单元112输出的延迟后的第一信号Data_TDCn进行延迟，比较转换单元12输出的表征信号记为Q<n>＝0，即第n级延迟转换单元112输出的表征信号为逻辑低电平的电平信号，即表征信号为0，由此可知，表征信号为Q<n>＝0对应的延迟后的第一信号Data_TDCn的上升沿不早于第二信号CLK_TDC的上升沿。
值得注意的是，由于N个级联的延迟转换单元112在持续运行，即N个级联的延迟转换单元112持续对延迟后的第一信号进行延迟，使得延迟后的第一信号的上升沿持续被延迟，将导致最终输出的第一延迟信号最终变为一个低电平信号，例如表征信号为Q<n+1>＝0对应的第一延迟信号以及表征信号为Q<n+x>＝0对应的第一延迟信号。如此，使得第一NMOS管MN1或者第二NMOS管MN2 中的其中一者的栅极输入的信号为持续的低电平信号，从而使得第一NMOS管MN1以及第二NMOS管MN2截止，即输出节点NET逻辑高电平的脉冲信号，逻辑电平为1，经过反相后，输出逻辑低电平的脉冲信号，使得表征信号的逻辑电平为0，即Q值为0。而由于本公开实施例中，当需要获取对第一信号Data_TDC的总的延迟量时，所有的有效Q值用于构成代码值Code，代码值Code对应的实际的延迟量为有效Q值对应的延迟转换单元112的预设延迟量的总和。而当第二信号与第一延迟信号的边沿对齐后，延迟转换单元112继续对第一延迟信号进行延迟所得到的Q值，被认为是无效Q值。由此可知，即使N个级联的延迟转换单元112持续对延迟后的第一信号进行延迟，也不会影响获取的代码值Code的准确性。
在一些实施例中，每一级的延迟转换单元112具有的预设延迟量相同。即以相同的预设延迟量对第一信号Data_TDC进行延迟，如此，当需要获取对第一信号Data_TDC的总的延迟量时，仅需将预设延迟量乘以延迟的次数即可，有利于简化运算设计。可以理解的是，在另一些实施例中，每一级的延迟转换单元112也可以具有不同的预设延迟量，以灵活适应不同的延迟需求，有利于提高对第一信号Data_TDC的补偿延迟效率。
上述公开实施例提供的延迟锁相环的延迟检测电路中，通过转换电路102对第一信号Data_TDC进行至少一次延迟，使得第一信号Data_TDC与第二信号CLK_TDC的边沿对齐，即通过延迟，使得反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位差一致。具体可以比较每一次延迟后的第一信号Data_TDC与第二信号CLK_TDC的边沿差异，并输出代码值Code，代码值Code表征反馈时钟信号CLKFB相较于参考时钟信号CLKREF的实际延迟量。如此，使得延迟锁相环可以精确地基于参考时钟信号CLKREF实际将产生的延迟量对参考时钟信号CLKREF进行补偿，从而使得输出的接收反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位减小或者为0，不仅可以提高延迟锁相环对补偿时间延迟的精确度，并且，由于基于参考时钟信号CLKREF实际产生的延迟量来对延迟来进行补偿，从而可以减小延迟锁相环对参考时钟信号CLKREF的延迟次数，进而提高延迟锁相环补偿时间延迟的效率。
相应地，本公开实施例还提供一种延迟锁相环电路，参考图11，包括：第一延迟电路1，被配置为，接收参考时钟信号CLKREF，并基于第一控制信号延迟参考时钟信号CLKREF，以生成第一延迟时钟信号；第二延迟电路2，被配置为，接收第一延迟时钟信号，并基于第二控制信号延迟第一延迟时钟信号，以生第二延迟时钟信号，第二延迟电路2的延迟精细度大于第一延迟电路1的延迟精细度；复制电路3，被配置为，延迟第二延迟时钟信号，以生成反馈时钟信号CLKFB；延迟控制电路4，被配置为，基于参考时钟信号CLKREF与反馈时钟信号CLKFB之间的相位差，调整第一控制信号以及第二控制信号，并将第一控制信号和第二控制信号分别提供到第一延迟电路1以及第二延迟电路2；上述实施例提供的延迟检测电路5，延迟检测电路5还被配置为，基于代码值Code生成与实际延迟量相对应的第三控制信号，并将第三控制信号提供到第一延迟电路1，第一延迟电路1还基于第三控制信号延迟参考时钟信号CLKREF。
参考时钟信号CLKREF可以由信号生成电路6产生，信号生成电路6与占空比调节电路电连接。在一些实施例中，还包括：占空比调节电路7，占空比调节电路7接收参考时钟信号CLKREF，用于对参考时钟信号CLKREF的占空比调整至50％，有利于第一延迟电路1以及第二延迟电路2对参考时钟信号CLKREF进行补偿延迟。基于此，第一延迟电路1对参考时钟信号CLKREF首先进行一次补偿延迟，输出第一延迟时钟信号；第二延迟电路2再对第一延迟时钟信号再进行一次补偿延迟，输出第二延迟时钟信号，且第一延迟电路1对参考时钟信号CLKREF的补偿量大于第二延迟电路2对参考时钟信号CLKREF的补偿量。即第一延迟电路1是对参考时钟信号CLKREF进行粗调，第二 延迟电路2是对参考时钟信号CLKREF进行细调，从而可以对参考时钟信号CLKREF进行精确地补偿。经过补偿之后的第二延迟时钟信号经由复制电路3输出后，生成反馈时钟信号CLKFB，反馈时钟信号CLKFB与第二延迟时钟信号具有相同的相位。
延迟控制电路4用于比较参考时钟信号CLKREF与反馈时钟信号CLKFB之间的相位差，并基于相位差获取第一控制信号与第二控制信号，第一控制信号用于输入第一延迟电路1，以使第一延迟电路1响应于第一控制信号对参考时钟信号CLKREF进行延迟补偿，并输出第一延迟时钟信号；第二控制信号用于输入第二延迟电路2，以使第二延迟电路2响应于第二控制信号对第一延迟时钟信号进行延迟补偿，并输出第二延迟时钟信号。经过补偿之后的第二延迟时钟信号经由复制电路3输出后，生成反馈时钟信号CLKFB，接着延迟控制电路4再次比较参考时钟信号CLKREF与反馈时钟信号CLKFB之间的相位差，重复上述步骤，直至参考时钟信号CLKREF与反馈时钟信号CLKFB的相位相同。
延迟检测电路5与复制电路3电连接，接收复制电路3输出的反馈时钟信号CLKFB，并将反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位差转换为第一信号Data_TDC与第二信号CLK_TDC的边沿之间的差异。再通过转换电路102对第一信号Data_TDC进行至少一次延迟，使得第一信号Data_TDC与第二信号CLK_TDC的边沿对齐。并比较每一次延迟后的第一信号Data_TDC与第二信号CLK_TDC的边沿差异，获取代码值Code，并将代码值Code输入值第一延迟电路1，以使第一延迟电路1基于代码值Code对参考时钟信号CLKREF进行延迟。其中，代码值Code表征反馈时钟信号CLKFB相较于参考时钟信号CLKREF的实际延迟量，如此，使得第一延迟电路1可以精确地基于参考时钟信号CLKREF实际将产生的延迟量对参考时钟信号CLKREF进行补偿，从而使得输出的接收反馈时钟信号CLKFB与参考时钟信号CLKREF之间的相位减小或者为0。
相较于延迟控制电路4将第一控制信号用于输入第一延迟电路1，将第二控制信号用于输入第二延迟电路2，以使第一延迟电路1与第二延迟电路2分别响应于第一控制信号与第二控制信号对参考时钟信号CLKREF进行延迟补偿而言，设置延迟检测电路5，不仅可以提高延迟锁相环对补偿时间延迟的精确度，并且，由于仅需将代码值Code输入第一延迟电路1，以使第一延迟电路1对参考时钟信号CLKREF进行延迟，使得延迟锁相环对参考时钟信号CLKREF的延迟次数减少，进而提高延迟锁相环补偿时间延迟的效率。
相应地，本公开实施例还提供一种存储装置，包括：上述实施例提供的延迟锁相环电路，延迟锁相环电路接收参考时钟信号CLKREF并输出与参考时钟信号CLKREF同相的输出时钟信号。在一些实施例中，存储单元可以为DRAM存储单元。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (17)

  1. 一种延迟锁相环的延迟检测电路，其中，包括：
    相位检测器，被配置为，接收反馈时钟信号以及参考时钟信号，并输出第一信号和第二信号，所述第一信号的边沿与所述第二信号的边沿之间的差异表征所述反馈时钟信号与所述参考时钟信号之间的相位差；
    转换电路，被配置为，接收所述第一信号以及所述第二信号，对所述第一信号进行至少一次延迟，比较每次延迟后的所述第一信号与所述第二信号的边沿差异，并输出代码值，所述代码值表征最后一次延迟的所述第一信号相较于所述第一信号的实际延迟量。
  2. 如权利要求1所述的延迟检测电路，其中，所述相位检测器还被配置为：
    接收初始信号，响应于所述反馈时钟信号对所述初始信号进行采样，并输出所述第一信号；
    响应于所述参考时钟信号对第一互补信号进行采样，并输出所述第二信号，所述第一互补信号与所述第一信号互为反相信号。
  3. 如权利要求2所述的延迟检测电路，其中，所述相位检测器包括：
    第一采样电路，被配置为，接收所述初始信号，响应于所述反馈时钟信号对所述初始信号进行采样，并输出所述第一信号以及所述第一互补信号；
    第二采样电路，被配置为，接收所述第一互补信号，响应于所述参考时钟信号对所述第一互补信号进行采样，并输出所述第二信号。
  4. 如权利要求3所述的延迟检测电路，其中，所述第一采样电路包括：多个级联的第一触发器，每一级所述第一触发器的时钟信号端接收所述反馈时钟信号，每一级所述第一触发器的数据输入端连接上一级所述第一触发器的第一输出端，第一级的所述第一触发器的数据输入端接收所述初始信号，最后一级的所述第一触发器的第一输出端以及第二输出端分别输出所述第一信号以及所述第一互补信号；
    所述第二采样电路包括第二触发器，所述第二触发器的数据输入端连接最后一级的所述第一触发器的所述第二输出端，所述第二触发器的时钟信号端接收所述参考时钟信号。
  5. 如权利要求1所述的延迟检测电路，其中，所述转换电路包括：
    N个级联的延迟转换单元，所述延迟转换单元被配置为，接收上一级的所述延迟转换单元输出的延迟后的所述第一信号，以预设延迟量延迟接收到的所述第一信号以生成第一延迟信号，并输出所述第一延迟信号至下一级的所述延迟转换单元，其中，处于首级的所述延迟转换单元接收的所述第一信号由所述相位检测器提供；
    所述延迟转换单元还被配置为，比较第二信号与所述第一延迟信号之间的边沿差异，并输出表征信号，所述表征信号表征第二信号的边沿是否不晚于所述第一延迟信号的边沿，其中所述代码值基于每一级所述延迟转换单元的所述表征信号获得。
  6. 如权利要求5所述的延迟检测电路，其中，所述延迟转换单元包括：
    延迟单元，被配置为，接收前一级的所述延迟转换单元输出的所述第一信号，以所述预设延迟量延迟所述第一信号并输出所述第一延迟信号，其中，处于首级的所述延迟转换单元的所述延迟单元接收的所述第一信号由所述相位检测器提供；
    比较转换单元，被配置为，接收所述第一延迟信号，并比较所述第二信号与所述第一延迟信号之间的边沿差异，输出所述表征信号。
  7. 如权利要求6所述的延迟检测电路，其中，所述延迟单元包括：
    第一延迟单元，被配置为，接收前一级的所述延迟转换单元输出的延迟后的所述第一信号，以第一延迟量延迟所述第一信号并生成子延迟信号；
    第二延迟单元，被配置为，接收所述子延迟信号，以第二延迟量延迟所述子延迟信号以生成输出所述第一延迟信号。
  8. 如权利要求7所述的延迟检测电路，其中，所述延迟单元包括两个相同所述第二延迟量的所述第二延迟单元，其中，一所述第二延迟单元的输出端连接至下一级的所述延迟转换单元的所述第一延迟单元，另一所述第二延迟单元的输出端连接至所述比较转换单元。
  9. 如权利要求7所述的延迟检测电路，其中，所述第一延迟单元包括第一与非门，所述第一与非门的一输入端连接电源电压，另一端接收前一级的所述延迟转换单元输出的延迟后的所述第一信号；所述第二延迟单元包括第二与非门，所述第二与非门的一输入端连接所述电源电压，另一输入端与所述第一延迟单元的输出端连接，输出端提供所述第一延迟信号。
  10. 如权利要求6所述的延迟检测电路，其中，所述比较转换单元还被配置为，若所述表征信号为逻辑低电平，则表征所述第二信号的边沿不晚于所述第一延迟信号的边沿；若所述表征信号包括逻辑高电平的脉冲，则表征所述第二信号的边沿晚于所述第一延迟信号的边沿。
  11. 如权利要求6所述的延迟检测电路，其中，所述比较转换单元包括：
    逻辑运算电路，接收所述第一延迟信号和所述第二信号，用于对所述第一延迟信号和所述第二信号进行与非运算并根据运算结果输出所述表征信号。
  12. 如权利要求11所述的延迟检测电路，其中，所述逻辑运算电路包括：
    第一PMOS管，所述第一PMOS管的栅极接收所述第一延迟信号，且所述第一PMOS管的源极连接电源节点，漏极连接输出节点；
    第二PMOS管，所述第二PMOS管的栅极接收所述第二信号，所述第二PMOS管的源极连接所述电源节点，所述第二PMOS管的漏极连接所述输出节点；
    第一NMOS管，漏极连接所述输出节点；
    第二NMOS管，漏极连接所述第一NMOS管的源极，源极连接地端；
    其中，所述第一NMOS管与所述第二NMOS管中一者的栅极接收所述第二信号，另一者的栅极接收所述第一延迟信号。
  13. 如权利要求12所述的延迟检测电路，其中，所述逻辑运算电路还包括第三PMOS管，所述第三PMOS管的栅极接收使能信号，且所述第三PMOS管响应于所述使能信号导通，所述第三PMOS管的源极连接所述电源节点，漏极连接所述第一PMOS管的源极。
  14. 如权利要求11所述的延迟检测电路，其中，逻辑运算电路还包括：
    锁存器，输入端连接所述输出节点；
    与所述锁存器的输出端连接的偶数个串联的反相器，最后一级的所述反相器输出所述表征信号。
  15. 如权利要求6所述的延迟检测电路，其中，每一级的所述延迟转换单元具有的所述预设延迟量相同。
  16. 一种延迟锁相环电路，其中，包括：
    第一延迟电路，被配置为，接收参考时钟信号，并基于第一控制信号延迟所述参考时钟信号，以生成第一延迟时钟信号；
    第二延迟电路，被配置为，接收所述第一延迟时钟信号，并基于第二控制信号延迟所述第一延迟时钟信号，以生成所述第二延迟时钟信号，所述第二延迟电路的延迟精细度大于所述第一延迟电路的延迟精细度；
    复制电路，被配置为，延迟所述第二延迟时钟信号，以生成反馈时钟信号；
    延迟控制电路，被配置为，基于所述参考时钟信号与所述反馈时钟信号之间的相位差，调整所述第一控制信号以及所述第二控制信号，并将所述第一控制信号和所述第二控制信号分别提供到所述第一延迟电路以及所述第二延迟电路；
    如权利要求1-15任一项所述的延迟检测电路，所述延迟检测电路还被配置为，基于所述代码值生成与所述实际延迟量相对应的第三控制信号，并将所述第三控制信号提供到所述第一延迟电路，所述第一延迟电路还基于所述第三控制信号延迟所述参考时钟信号。
  17. 一种存储装置，其中，包括：
    如权利要求16所述的延迟锁相环电路，所述延迟锁相环电路接收参考时钟信号并输出与所述参考时钟信号同相的输出时钟信号。
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US20050218937A1 (en) * 2004-03-31 2005-10-06 Gary Johnson Phase detector and method having hysteresis characteristics
US20080042704A1 (en) * 2006-06-29 2008-02-21 Hynix Semiconductor Inc. Delayed locked loop (DLL)
US20080061851A1 (en) * 2006-09-13 2008-03-13 Samsung Electronics Co., Ltd. Delay locked loop circuit capable of reducing bang-bang jitter
CN104753524A (zh) * 2013-12-25 2015-07-01 中国科学院电子学研究所 一种延时锁定环路
CN112234956A (zh) * 2019-06-27 2021-01-15 意法半导体股份有限公司 亚时钟电流脉冲生成器

Patent Citations (5)

* Cited by examiner, † Cited by third party
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US20050218937A1 (en) * 2004-03-31 2005-10-06 Gary Johnson Phase detector and method having hysteresis characteristics
US20080042704A1 (en) * 2006-06-29 2008-02-21 Hynix Semiconductor Inc. Delayed locked loop (DLL)
US20080061851A1 (en) * 2006-09-13 2008-03-13 Samsung Electronics Co., Ltd. Delay locked loop circuit capable of reducing bang-bang jitter
CN104753524A (zh) * 2013-12-25 2015-07-01 中国科学院电子学研究所 一种延时锁定环路
CN112234956A (zh) * 2019-06-27 2021-01-15 意法半导体股份有限公司 亚时钟电流脉冲生成器

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