WO2022074706A1 - デジタルアナログ変換器 - Google Patents

デジタルアナログ変換器 Download PDF

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Publication number
WO2022074706A1
WO2022074706A1 PCT/JP2020/037699 JP2020037699W WO2022074706A1 WO 2022074706 A1 WO2022074706 A1 WO 2022074706A1 JP 2020037699 W JP2020037699 W JP 2020037699W WO 2022074706 A1 WO2022074706 A1 WO 2022074706A1
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Prior art keywords
current source
current
type
transistor
transistors
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PCT/JP2020/037699
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English (en)
French (fr)
Japanese (ja)
Inventor
睦夫 大東
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三菱電機株式会社
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Priority to JP2022554981A priority Critical patent/JP7353512B2/ja
Priority to PCT/JP2020/037699 priority patent/WO2022074706A1/ja
Publication of WO2022074706A1 publication Critical patent/WO2022074706A1/ja

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/78—Simultaneous conversion using ladder network

Definitions

  • This disclosure relates to a digital-to-analog converter.
  • a binary type R-2R type D / A converter that performs digital-to-analog conversion (hereinafter referred to as "D / A (Digital / Analog) conversion") using an R-2R ladder resistance circuit is known.
  • D / A (Digital / Analog) conversion digital-to-analog conversion
  • the conversion circuit is separately configured by the upper bit and the lower bit of the digital input signal (for example, Patent Document 1). reference).
  • both the high-order bit conversion circuit and the low-order bit conversion circuit are binary R-2R type D / A conversion circuits (weighted current distribution by the R-2R ladder method). Method).
  • R-2R type D / A conversion circuits weighted current distribution by the R-2R ladder method. Method.
  • it is necessary to change the current by a power of 2 so that the size of the transistors constituting the circuit also needs to be increased by a power of 2. Therefore, if both the high-order bit conversion circuit and the low-order bit conversion circuit are configured by the binary type R-2R type D / A conversion circuit, the circuit area of the entire D / A converter becomes large.
  • the present disclosure has been made to solve such a problem, and the purpose of the present disclosure is to provide a highly accurate D / A converter while suppressing the circuit area.
  • the D / A converter of the present disclosure is a D / A converter that converts a digital signal into an analog signal, and includes a binary type R-2R type D / A conversion circuit.
  • the R-2R type D / A conversion circuit includes an R-2R ladder circuit, a plurality of current source transistors, and a variable current source.
  • a plurality of current source transistors are provided for each bit of the upper bit of the digital signal, and a current corresponding to the state of the upper bit is passed through the R-2R ladder circuit.
  • the variable current source causes a current corresponding to the state of the lower bits of the digital signal to flow in the R-2R ladder circuit.
  • the variable current source is composed of a binary type L-2L type D / A conversion circuit.
  • the conversion circuit is configured separately for the upper bit and the lower bit of the digital signal, and the conversion circuit on the lower bit side is configured by the binary type L-2L type D / A conversion circuit. Will be done. Since this L-2L type D / A conversion circuit does not need to increase the size of the transistors constituting the circuit by a power of 2, it is possible to construct a highly accurate D / A converter while suppressing the circuit area. can.
  • FIG. It is a figure which shows the circuit structure of the D / A converter according to Embodiment 1.
  • FIG. It is a figure which shows the structure of the variable current source shown in FIG. It is a figure which shows the structure of the variable current source in the modification 1.
  • FIG. It is a figure which shows the circuit structure of the D / A converter according to Embodiment 2.
  • It is a figure which shows the structure of the variable current source shown in FIG. It is a flowchart which shows an example of the procedure of the current correction processing executed by the control unit shown in FIG. It is a figure which shows the structure of the variable current source in the modification 2.
  • Embodiment 1 The circuit configuration of the D / A converter according to the first embodiment will be described with reference to FIGS. 1 and 2. In the following, a D / A converter capable of obtaining a weighted voltage output with 6-bit accuracy will be described, but the number of bits is not limited to this.
  • the D / A converter 10 includes a resistance network 20, selective transistors 31 to 34, a variable current source 41, current source transistors 42 to 44, 51, and a current source 52.
  • the resistance network 20 includes resistance elements 22 to 24 having a resistance value of 2R and resistance elements 21, 25 to 27 having a resistance value of R. Such a resistance network 20 is referred to as an R-2R ladder circuit.
  • Each of the selection transistors 31 to 34 and the current source transistors 42 to 44, 51 is composed of an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
  • the drain terminal of the selection transistor 31 is connected to the connection node of the resistance elements 21 and 25, and the source terminal of the selection transistor 31 is connected to the drain side of the variable current source 41.
  • the drain terminal of the selection transistor 32 is connected to the connection node of the resistance elements 22, 25, 26, and the source terminal of the selection transistor 32 is connected to the drain terminal of the current source transistor 42.
  • drain terminal of the selection transistor 33 is connected to the connection node of the resistance elements 23, 26, 27, and the source terminal of the selection transistor 33 is connected to the drain terminal of the current source transistor 43.
  • the drain terminal of the selection transistor 34 is connected to the connection node of the resistance elements 24 and 27, and the source terminal of the selection transistor 34 is connected to the drain terminal of the current source transistor 44.
  • the source side of the variable current source 41 and the source terminals of the current source transistors 42 to 44 are connected to the ground node 55.
  • the drain terminal and source terminal of the current source transistor 51 are connected to the current source 52 and the ground node 55, respectively.
  • the gate terminal of the current source transistor 51 is connected to the drain terminal of the current source transistor 51. That is, the current source transistor 51 is connected by a diode.
  • the gate terminals of the current source transistors 42 to 44 are connected to the gate terminal and the drain terminal of the current source transistor 51.
  • the current source transistor 51 and the current source 52 form a reference current source that generates a reference current I1.
  • the current source transistors 51 and the current source transistors 42 to 44 form a current mirror circuit, and the current flowing through each of the current source transistors 42 to 44 is duplicated from the reference current source.
  • the selection transistors 32 to 34 are switched according to the control bits (upper 3 bits) of the digital input signal.
  • the selection transistor 31 is always turned on during the execution of D / A conversion by the D / A converter 10. Therefore, in the first embodiment, the selection transistor 31 may be omitted.
  • the current source transistors 42 to 44 are provided for each bit of the upper bit of the digital signal.
  • the selection transistors 32 to 34 can switch whether or not a current flows from the current source transistors 42 to 44 to the resistance network 20, respectively.
  • the variable current source 41 is a current source that causes a current corresponding to the state of the lower bits of the digital signal to flow to the resistance network 20.
  • the current of the variable current source 41 is switched stepwise according to the control bits (lower 3 bits) of the digital input signal. The configuration of the variable current source 41 will be described later with reference to FIG.
  • the selection transistors 32 to 34 are switched according to the digital input signal, the current of the variable current source 41 is switched, and the current corresponding to the digital input signal flows through the resistance network 20. Then, the current corresponding to the digital input signal is converted into a voltage by the resistance network 20, and is output from the terminal 29 as a voltage output Vout.
  • the terminals 28 and 29 are connected to an input terminal and an output terminal of an operational amplifier (not shown), respectively.
  • the D / A converter 10 having such a circuit configuration is referred to as an R-2R type D / A conversion circuit (binary type). Further, the D / A converter 10 having a current source transistor for each bit is also referred to as a current type D / A conversion circuit.
  • the D / A converter 10 shown in FIG. 1 is composed of an N-type MOSFET and has a circuit configuration in which a current is drawn to the grounded node 55 by an N-type MOSFET. It may be configured and a circuit configuration may be used in which a current is supplied from the power supply into the circuit. Alternatively, a circuit configuration using both an N-type MOSFET and a P-type MOSFET may be adopted.
  • variable current source 41 is composed of the same transistors as the current source transistors 42 to 44. .. In the following description of the circuit configuration of this assumption, the variable current source 41 is referred to as a current source transistor 41.
  • the current source transistor 41 has the same size as the current source transistors 42 to 44, and its gate terminal is connected to the gate terminal and drain terminal of the current source transistor 51 in the same manner as the current source transistors 42 to 44.
  • Vout Va + R ⁇ I1 ⁇ b5 + R ⁇ I1 / 2 ⁇ b4 + R ⁇ I1 / 4 ⁇ b3 + R ⁇ I1 / 8 ⁇ b2...
  • Vout Va + R ⁇ I1 ⁇ b5 + R ⁇ I1 / 2 ⁇ b4 + R ⁇ I1 / 4 ⁇ b3 + R ⁇ Iv / 8...
  • the variable current source is configured by a current type D / A conversion circuit (binary type), and that the variable current source changes the current Iv with a 3-bit accuracy according to the control bits b0 to b2.
  • Current Iv is expressed by the following equation.
  • Vout Va + R ⁇ I1 ⁇ b5 + R ⁇ I1 / 2 ⁇ b4 + R ⁇ I1 / 4 ⁇ b3 + R ⁇ I1 / 8 ⁇ b2 + R ⁇ I1 / 16 ⁇ b1 + R ⁇ I1 / 32 ⁇ b0... (4) From this equation (4), it can be understood that a weighted voltage output Vout with 6-bit precision corresponding to the control bits b0 to b5 can be obtained.
  • the conversion circuit is configured separately for the upper bit and the lower bit of the digital input signal, and the lower bit is D / A converted by the variable current source 41.
  • variable current source 41 needs to generate a current smaller than the reference current I1.
  • the variable current source 41 also has a circuit configuration of a weighted current distribution method, the current needs to be changed by a power of 2, so the size of the transistor constituting the circuit is also 2. It needs to be increased by the power. Therefore, the circuit area of the entire D / A converter becomes large.
  • the variable current source 41 is configured by a binary type L-2L type D / A conversion circuit.
  • the L-2L type D / A conversion circuit can make the current variable stepwise without increasing the size of the transistors constituting the circuit by a power of 2.
  • variable current source 41 includes transistors 61, 71 to 76, a current source 62, and selection switches 81 to 83.
  • Each of the transistors 61, 71 to 76 is composed of an N-type MOSFET.
  • the drain terminal of the transistor 71 is connected to the selection switch 81, and the source terminal of the transistor 71 is connected to the ground node 85.
  • the drain terminal of the transistor 72 is connected to the selection switch 82, and the source terminal of the transistor 72 is connected to the connection node of the transistors 75 and 76.
  • the drain terminal of the transistor 73 is connected to the selection switch 83, and the source terminal of the transistor 73 is connected to the connection node of the transistors 74 and 76.
  • the drain terminal of the transistor 74 is connected to the terminal 91, and the source terminal of the transistor 74 is connected to the drain terminal of the transistor 76.
  • the transistor 75 is connected between the source terminals of the transistors 71 and 72, and the transistor 76 is connected between the source terminals of the transistors 72 and 73.
  • the drain terminal and the source terminal of the transistor 61 are connected to the current source 62 and the ground node 85, respectively.
  • the gate terminal of the transistor 61 is connected to the drain terminal of the transistor 61. That is, the transistor 61 is diode-connected.
  • the gate terminals of the transistors 71 to 74 are connected to the gate terminal and the drain terminal of the transistor 61.
  • the transistor 61 and the current source 62 constitute a reference current source that generates a reference current I2.
  • the transistor 61 and the transistors 71 to 74 form a current mirror circuit, and the current flowing through each of the transistors 71 to 74 is duplicated from the reference current source.
  • the selection switches 81 to 83 are switched according to the control bits (lower 3 bits) of the digital input signal, and control the output current Iout to be passed through the terminal 90. Specifically, the selection switch 81 connects the drain terminal of the transistor 71 to the terminal 90 when the corresponding control bit is 1. Further, the selection switch 82 connects the drain terminal of the transistor 72 to the terminal 90 when the corresponding control bit is 1, and the selection switch 83 connects the drain terminal of the transistor 73 when the corresponding control bit is 1. Connect the terminal to the terminal 90.
  • the terminal 91 and its output current Ical are used in the second embodiment described later and not used in the first embodiment, in the first embodiment, the terminal 91 is passed through an appropriate resistance element (not shown). Connected to a power source.
  • Each of the transistors 75 and 76 has twice the gate width (W) or half the gate length (L) or twice the number of transistors (parallel connection) with respect to each of the transistors 71 to 74.
  • a D / A conversion circuit having such a circuit configuration is referred to as an L-2L type D / A conversion circuit (binary type).
  • the current I flowing through the transistor having the gate width W and the gate length L is expressed by the following equation.
  • I ⁇ ⁇ Cox ⁇ W / L (Vgs-Vth) 2 ...
  • ⁇ mobility
  • Cox gate capacitance
  • Vgs gate-source potential
  • Vth threshold voltage
  • the transistors 73 and 74 having a gate width W and a gate length L (hereinafter referred to as “W / L”) are connected in parallel, the gate width W and the gate length L (hereinafter referred to as “2W / L”). It can be regarded as equivalent to the transistor of (referred to as "L").
  • the current that flows is halved because it can be regarded as equivalent to a transistor to which the gate length (L) of the transistor is added. Therefore, for example, since the transistors 73, 74 connected in parallel are connected in series with the transistor 76 of 2 W / L, the three transistors 73, 74, 76 are one transistor having a size of W / L. Can be equated with.
  • the selection switches 81 to 83 are controlled so that the current always flows through the transistors 71 to 76.
  • the output current Iout of the variable current source 41 is expressed by the following equation, where the reference current generated by the transistor 61 and the current source 62 is I2.
  • the equation (6) becomes the same as the above equation (3). Therefore, by configuring the transistor 61 and the current source 62 so that the reference current I2 is equal to the reference current I1, the D / A converter 10 shown in FIG. 1 provides a weighted voltage output Vout with 6-bit accuracy. Obtainable.
  • variable current source 41 configured by such an L-2L type D / A conversion circuit does not need to increase the size of the transistor by a power of 2 in order to change the current by a power of 2, so that the circuit area is increased. It can be suppressed.
  • the D / A conversion unit is configured separately for the upper bit and the lower bit of the digital signal, and the variable current source 41 that performs the D / A conversion on the lower bit side is binary. It is composed of a type L-2L type D / A conversion circuit. Since this L-2L type D / A conversion circuit does not need to increase the size of the transistors constituting the circuit by a power of 2, according to the first embodiment, the circuit area is suppressed and the high-precision D is performed.
  • the / A converter 10 can be configured.
  • the reference current source transistor 61 and the current source 62 are configured so that the reference current I2 becomes equal to the reference current I1, but the variable is shown in FIG.
  • the size of the transistors 71 to 74 is the same as the size of the current source transistor 51, and the bias voltage generated by the current source transistor 51 and the current source 52 (FIG. 1) is set to the transistors 71 to 74. It may be received as a bias voltage.
  • variable current source it is not necessary to separately provide a reference current source separately from the current source transistor 51 and the current source 52, so that the circuit area can be further suppressed.
  • Embodiment 2 In the above D / A converter 10, the D / A conversion accuracy may deteriorate due to manufacturing variations of the resistance element of the resistance network 20, the variable current source 41, the current source transistors 42 to 44, 51, and the like. .. In particular, since the D / A converter 10 performs D / A conversion separately for the upper bit and the lower bit, when the lower bits change from all 1 to all 0 (or all 0 to all 1), the upper bit is changed. The influence on the conversion accuracy is large at the boundary between the bit and the lower bit.
  • the reference current I2 in the variable current source 41 (FIG. 2) that performs D / A conversion of the lower bits, and the reference current generated by the current source transistor 51 and the current source 52 (FIG. 1).
  • I1 and I1 an error occurs between the current Iout shown in the above equation (6) and the current Iv shown in the equation (3).
  • an error occurs in the output Vout of the equation (4), and if the error becomes large, the monotonous increase (or monotonic decrease) of the voltage output Vout with respect to the digital input signal may be impaired.
  • the reference current I1 used for the conversion of the upper bits is corrected by using the current output of the variable current source 41 that converts the lower bits. This suppresses the deterioration of the conversion accuracy at the boundary between the high-order bit and the low-order bit.
  • the D / A converter 10A according to the second embodiment includes a variable current source 102 instead of the current source 52, a current comparator 104, and a control unit 106. And further prepare.
  • One of the input terminals of the current comparator 104 is connected to the terminal 91 (FIG. 2) of the variable current source 41, and the other of the input terminals of the current comparator 104 is connected to the drain terminal of the current source transistor 42.
  • the current comparator 104 compares the current Ical output from the terminal 91 of the variable current source 41 with the current flowing through the current source transistor 42 when the selection transistors 31 and 32 are off, and controls the comparison result. Output to unit 106.
  • the control bits of the selection switches 81 to 83 are set so that the current Ical is maximized. This is to adjust the variable current source 102 so that the maximum current of the variable current source 41 that converts the lower bits and the minimum current (current flowing through the current source transistor 42) in the conversion unit of the upper bits are the same. ..
  • the comparison result of the current comparator 104 is output to the control unit 106.
  • the control unit 106 controls the variable current source 102 based on the comparison result of the current comparator 104. Specifically, since the gate terminal of the current source transistor 42 is connected to the gate terminal of the current source transistor 51 and the variable current source 102, the current can be adjusted (corrected) by adjusting (correcting) the output current of the variable current source 102. The current flowing through the source transistor 42 can be adjusted.
  • control unit 106 is based on the output of the current comparator 104 so that the difference between the current Ical (maximum current of the variable current source 41) from the variable current source 41 and the current flowing through the current source transistor 42 becomes small.
  • the variable current source 102 is controlled. As a result, it is possible to prevent the D / A conversion accuracy from deteriorating at the boundary between the high-order bit and the low-order bit.
  • the variable current source 102 includes a variable current source 110 and transistors 152 and 154.
  • the variable current source 110 includes transistors 121, 131 to 136, a current source 122, and switches 141 to 143.
  • variable current source 110 has the same circuit configuration as the variable current source 41 shown in FIG. That is, the variable current source 110 is also a binary type L-2L type D / A conversion circuit.
  • the switches 141 to 143 are switched by the control unit 106 to control the current Iout2 flowing through the current source transistor 51 (FIG. 4).
  • the switches 141 to 143 connect the drain terminals of the transistors 131 to 133 to the drain terminals of the transistor 152, respectively, when the corresponding control bit is 1.
  • Each of the transistors 152 and 154 is composed of a P-type MOSFET.
  • the outputs of switches 141 to 143 are connected to the drain terminal of the transistor 152.
  • the gate terminal of the transistor 152 is connected to the drain terminal of the transistor 152. That is, the transistor 152 is diode-connected.
  • the gate terminal of the transistor 154 is connected to the gate terminal and the drain terminal of the transistor 152.
  • the transistors 152 and 154 form a polyclonal type current mirror circuit, and the current generated by the variable current source 110 is duplicated by the transistors 152 and 154 and output from the terminal 156 as the current Iout2.
  • the current Iout2 supplied to the current source transistor 51 is duplicated in the current source transistor 42, and the current flowing through the current source transistor 42 is compared with the current Ical of the variable current source 41 by the current comparator 104.
  • control unit 106 turns off the selection transistors 31 and 32 (FIG. 4) (step S10).
  • control unit 106 sets all the control bits of the selection switches 81 to 83 (FIG. 2) of the variable current source 41 (FIG. 4) to 0 (step S20). As a result, all the current flowing through the transistors 71 to 73 is supplied to the terminal 91. That is, the control unit 106 controls the selection switches 81 to 83 so that the current Ical output from the variable current source 41 is maximized.
  • control unit 106 controls the switches 141 to 143 (FIG. 5) of the variable current source 102 based on the comparison result of the current comparator 104 (step S30). Specifically, the control unit 106 sets switches 141 to 143 so that the difference between the current Ical from the variable current source 41 and the current flowing through the current source transistor 42 becomes small based on the comparison result of the current comparator 104. To control.
  • variable current source 41 that performs D / A conversion of the lower bits and the minimum current (current flowing through the current source transistor 42) of the D / A conversion of the upper bits is reduced.
  • control unit 106 By controlling the variable current source 102 by the control unit 106, it is possible to suppress deterioration of the D / A conversion accuracy at the boundary between the upper bit and the lower bit.
  • the variable current source 110 internally generates a bias voltage by the transistor 121 and the current source 122, but as in the variable current source 102A shown in FIG. ,
  • the bias voltage generated by the transistor 61 and the current source 62 constituting the reference current source of the variable current source 41 (FIG. 2) may be received as the bias voltage of the transistors 131 to 134 of the variable current source 110A.
  • variable current source it is not necessary to separately provide a reference current source separately from the transistor 61 and the current source 62, so that the circuit area can be further suppressed.
  • variable current sources 110 and 110A are composed of N-type MOSFETs in the above-described second embodiment and second modification, they may be composed of P-type MOSFETs.
  • the current Iout2 can be supplied to the current source transistor 51 without replicating the current with the transistors 152 and 154.
  • 10,10A D / A converter 20 resistance network, 21-27 resistance element, 28,29,90,91,156 terminals, 31-34 selection transistor, 41,41A,102,102A,110,110A variable current Source, 42-44,51 current source transistor, 52,62,122 current source, 55,85 ground node, 61,71-76,121,131-136,152,154 transistor, 81-83 selection switch, 104 current Comparer, 106 control unit, 141-143 switch.

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PCT/JP2020/037699 2020-10-05 2020-10-05 デジタルアナログ変換器 WO2022074706A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5566126A (en) * 1978-11-11 1980-05-19 Nippon Telegr & Teleph Corp <Ntt> Multi-ladder type d/a converter
JPH10107637A (ja) * 1996-09-30 1998-04-24 Toshiba Corp Ｄ／ａコンバ−タ
JPH1188059A (ja) * 1997-09-09 1999-03-30 Matsushita Electric Ind Co Ltd 乗算器回路
JP2001237705A (ja) * 2000-02-22 2001-08-31 Canon Inc 重みづけ定電流源およびｄ−ａ変換器
JP2012151728A (ja) * 2011-01-20 2012-08-09 Nippon Telegr & Teleph Corp <Ntt> ディジタル／アナログ変換器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61197732U (enrdf_load_stackoverflow) * 1985-05-29 1986-12-10
JP2002009623A (ja) * 2000-06-27 2002-01-11 Nec Corp ディジタルアナログ変換回路
JP2002076897A (ja) * 2000-08-29 2002-03-15 Toshiba Corp Ｄａコンバータ
GB2568108B (en) * 2017-11-07 2021-06-30 Analog Devices Global Current steering digital to analog converter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5566126A (en) * 1978-11-11 1980-05-19 Nippon Telegr & Teleph Corp <Ntt> Multi-ladder type d/a converter
JPH10107637A (ja) * 1996-09-30 1998-04-24 Toshiba Corp Ｄ／ａコンバ−タ
JPH1188059A (ja) * 1997-09-09 1999-03-30 Matsushita Electric Ind Co Ltd 乗算器回路
JP2001237705A (ja) * 2000-02-22 2001-08-31 Canon Inc 重みづけ定電流源およびｄ−ａ変換器
JP2012151728A (ja) * 2011-01-20 2012-08-09 Nippon Telegr & Teleph Corp <Ntt> ディジタル／アナログ変換器

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