WO2022067770A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022067770A1
WO2022067770A1 PCT/CN2020/119673 CN2020119673W WO2022067770A1 WO 2022067770 A1 WO2022067770 A1 WO 2022067770A1 CN 2020119673 W CN2020119673 W CN 2020119673W WO 2022067770 A1 WO2022067770 A1 WO 2022067770A1
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WO
WIPO (PCT)
Prior art keywords
light
emitting element
conductive line
sub
line segment
Prior art date
Application number
PCT/CN2020/119673
Other languages
English (en)
French (fr)
Other versions
WO2022067770A9 (zh
Inventor
程羽雕
王本莲
黄耀
黄炜赟
杜丽丽
龙跃
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020237009296A priority Critical patent/KR20230078648A/ko
Priority to EP20955793.3A priority patent/EP4203046A4/en
Priority to JP2023518291A priority patent/JP2023544272A/ja
Priority to PCT/CN2020/119673 priority patent/WO2022067770A1/zh
Priority to US17/609,878 priority patent/US11862081B2/en
Priority to CN202080002265.9A priority patent/CN114586168A/zh
Priority to CN202211413382.1A priority patent/CN115662351B/zh
Priority to CN202080002535.6A priority patent/CN114762125B/zh
Priority to PCT/CN2020/124401 priority patent/WO2022067931A1/zh
Priority to US17/433,292 priority patent/US11810504B2/en
Priority to CN202410058279.2A priority patent/CN118251048A/zh
Priority to CN202310334057.4A priority patent/CN116782696B/zh
Priority to CN202080002656.0A priority patent/CN114930544A/zh
Priority to CN202080002653.7A priority patent/CN114730799A/zh
Priority to US17/423,885 priority patent/US20220376015A1/en
Priority to PCT/CN2020/127186 priority patent/WO2022067965A1/zh
Priority to PCT/CN2020/127256 priority patent/WO2022067967A1/zh
Priority to US17/427,151 priority patent/US20220376000A1/en
Priority to US17/789,007 priority patent/US11847964B2/en
Priority to CN202180000474.4A priority patent/CN114586169A/zh
Priority to PCT/CN2021/080494 priority patent/WO2022068152A1/zh
Priority to PCT/CN2022/071427 priority patent/WO2022188542A1/zh
Priority to CN202280000031.XA priority patent/CN115349173A/zh
Priority to US18/025,962 priority patent/US20230371324A1/en
Publication of WO2022067770A1 publication Critical patent/WO2022067770A1/zh
Publication of WO2022067770A9 publication Critical patent/WO2022067770A9/zh
Priority to US18/477,479 priority patent/US20240029647A1/en
Priority to US18/489,382 priority patent/US20240078970A1/en
Priority to US18/385,071 priority patent/US20240062717A1/en

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H—ELECTRICITY
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Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • the under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of the display device.
  • a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for setting the camera.
  • the second display area generally includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit is connected to a light-emitting element, and is used to drive the light-emitting element to emit light, and the mutually connected pixel circuits and light-emitting elements are perpendicular to the display panel. overlapping in direction.
  • the present application provides a display panel and a display device, and the technical solutions are as follows:
  • a display panel comprising:
  • a base substrate having a first display area and a second display area, the first display area at least partially surrounds the second display area;
  • a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of first light-emitting elements are located in the first display area, and the plurality of second pixel circuits are distributed among the plurality of first pixel circuits at intervals between;
  • At least one first pixel circuit in the plurality of first pixel circuits is connected to at least one first light-emitting element in the plurality of first light-emitting elements, and the at least one first pixel circuit is in the backing
  • the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element on the base substrate; at least one second pixel circuit in the plurality of second pixel circuits overlaps with the plurality of second pixel circuits.
  • At least one of the second light-emitting elements is connected by a conductive wire.
  • the plurality of second light-emitting elements and the plurality of first light-emitting elements have the same density.
  • the resolution of the first display area is the same as the resolution of the second display area; or, the resolution of the first display area and the resolution of the second display area are different.
  • each of the first pixel circuits is connected to one of the first light-emitting elements
  • the orthographic projection of each of the first pixel circuits on the base substrate at least partially overlaps with the orthographic projection of the connected first light-emitting element on the base substrate.
  • the plurality of first pixel circuits include a plurality of columns of first pixel circuits extending along a first direction
  • the plurality of second pixel circuits include a plurality of columns of second pixel circuits extending along the first direction
  • the plurality of columns of second pixel circuits are distributed among the plurality of columns of first pixel circuits at intervals.
  • any two adjacent columns of the second pixel circuits are separated by the first pixel circuits of the same number of columns or different numbers of columns.
  • the multiple first pixel circuits include multiple rows of first pixel circuits extending along the second direction
  • the multiple second pixel circuits include multiple rows of second pixel circuits extending along the second direction
  • the The second direction intersects the first direction.
  • the plurality of rows of second pixel circuits are distributed among the plurality of rows of first pixel circuits at intervals.
  • the first direction is perpendicular to the second direction.
  • the first display area includes: a first sub-display area and a second sub-display area arranged in sequence along the first direction; the first sub-display area includes: two symmetrical target sub-display areas;
  • one of the target sub-display areas, the second display area and the other target sub-display area are arranged in sequence along the second direction.
  • the second display area includes two third sub-display areas symmetrically arranged along the second direction;
  • the display panel includes: a first conductive line, a second conductive line and a third conductive line;
  • Each of the third sub-display areas includes k light-emitting element groups, each of the light-emitting element groups includes a plurality of adjacent rows of the second light-emitting elements, and the first to the k-th light-emitting element group
  • the light-emitting element groups are sequentially arranged along the direction close to the other third sub-display area, and k is an integer greater than 0;
  • Each of the target sub-display areas includes k pixel circuit groups corresponding to the k light-emitting element groups one-to-one, each of the pixel circuit groups includes a plurality of adjacent columns of the second pixel circuits, and the first The pixel circuit groups to the k-th pixel circuit group are sequentially arranged in a direction away from the adjacent third sub-display areas; and each of the second light-emitting element groups in each of the light-emitting element groups The element is connected to each of the second pixel circuits in the corresponding one of the pixel circuit groups through the first conductive line, the second conductive line and/or the third conductive line.
  • k is 4.
  • each of the second light-emitting elements in the first light-emitting element group is connected to each of the second pixel circuits in the first pixel circuit group through the first conductive wire;
  • Each of the second light-emitting elements in the second light-emitting element group is connected to each of the second pixel circuits in the second pixel circuit group through the second conductive wire;
  • Each of the second light-emitting elements in the third light-emitting element group is connected to each of the second pixel circuits in the third pixel circuit group through the third conductive wire;
  • Each of the second light-emitting elements in the fourth light-emitting element group and each of the second pixel circuits in the fourth pixel circuit group pass through the first conductive wire and the second conductive wire connected to the third conductive wire.
  • the first conductive wire connected to each of the second light-emitting elements in the first light-emitting element group is connected to each of the second light-emitting elements in the second light-emitting element group.
  • the second conductive line, and each of the third conductive lines connected to each of the second light-emitting elements in the third light-emitting element group includes: a first conductive line segment, a second conductive line segment, and the third conductive line segment;
  • One end of the first conductive line segment is connected to the corresponding second light-emitting element, and the other end of the first conductive line segment is connected to one end of the second conductive line segment;
  • the other end of the second conductive line segment is connected to one end of the third conductive line segment
  • the other end of the third conductive line segment is connected to the corresponding second pixel circuit
  • first conductive line segment and the third conductive line segment extend along the first direction
  • second conductive line segment extends along the second direction
  • second conductive line segment extends on the base substrate
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the connected second light-emitting element on the base substrate.
  • the second conductive line segment included in the first conductive line and the second conductive line segment included in the third conductive line at least partially overlap, and the second conductive line segment included in the first conductive line
  • the line segment does not overlap with the second conductive line segment included in the second conductive line
  • the second conductive line segment included in the third conductive line does not overlap with the second conductive line segment included in the second conductive line.
  • the fourth light-emitting element group includes: two first sub-light-emitting element groups, two second sub-light-emitting element groups, and two third sub-light-emitting element groups that are symmetrically arranged along the axis of the third sub-display area.
  • Sub-light-emitting element groups, each sub-light-emitting element group includes multiple adjacent rows of the second light-emitting elements, and the first sub-light-emitting element group, the second sub-light-emitting element group and the third light-emitting element group located on the same side
  • the sub-light-emitting element groups are sequentially arranged along the direction away from the axis, and the axis extends along the second direction;
  • the fourth pixel circuit group includes: two first sub-pixel circuit groups corresponding to the two first sub-light-emitting element groups one-to-one, and two second sub-light-emitting element groups corresponding to one-to-one two second sub-pixel circuit groups, two third sub-pixel circuit groups corresponding to the two third sub-light-emitting element groups one-to-one;
  • each of the second light-emitting elements in each of the first sub-light-emitting element groups is connected with each of the second pixel circuits in the corresponding first sub-pixel circuit group through the first conductive line ; each of the second light-emitting elements in each of the second sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding second sub-pixel circuit group through the second conductive lines; Each of the second light-emitting elements in each of the third sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding third sub-pixel circuit group through the third conductive lines.
  • the first conductive lines to which each of the second light-emitting elements in each of the first sub-light-emitting element groups are connected, and each of the second light-emitting elements in each of the second sub-light-emitting element groups The second conductive line connected to the light-emitting element, the third conductive line connected to each of the second light-emitting elements in each of the third sub-light-emitting element groups, including: a fourth conductive line segment, a fifth conductive line a conductive line segment and a sixth conductive line segment and a seventh conductive line segment;
  • One end of the fourth conductive line segment is connected to the corresponding second light-emitting element, and the other end of the fourth conductive line segment is connected to one end of the fifth conductive line segment;
  • the other end of the fifth conductive line segment is connected to one end of the sixth conductive line segment;
  • the other end of the sixth conductive line segment is connected to one end of the seventh conductive line segment
  • the other end of the seventh conductive line segment is connected to the corresponding second pixel circuit
  • the fifth conductive line segment and the seventh conductive line segment extend along the first direction
  • the sixth conductive line segment extends along the second direction
  • the fourth conductive line segment is located in the connected between the row where the two light-emitting elements are located and the adjacent row
  • the fifth conductive line segment included in the first conductive line is located in the region where the second light-emitting element group to the fourth light-emitting element group are located, and the fifth conductive line segment included in the second conductive line is located in the third light-emitting element group.
  • the fifth conductive line segment included in the third conductive line is located in the region where the fourth light-emitting element group is located;
  • the sixth conductive line segment on the side of the second sub-display area is located on the side of the second display area away from the second sub-display area, and the sixth conductive line segment on the side of the second sub-display area along the axis is close to the second sub-display area.
  • the six conductive line segments are located in the second display area adjacent to the second sub-display area.
  • the first light-emitting element group to the third light-emitting element group respectively include 12 columns of the second light-emitting elements;
  • the fourth light-emitting element group includes 8 columns of the second light-emitting elements;
  • the first pixel circuit group to the third pixel circuit group respectively include 12 columns of the second pixel circuits; the fourth pixel circuit group includes 8 columns of the second pixel circuits.
  • the display panel further includes: a plurality of metal layers;
  • a data line connected to each of the second pixel circuits is arranged in the same layer as any one of the metal layers;
  • the plurality of metal layers include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer.
  • the odd-numbered columns are located in the second pixel circuits.
  • the data lines connected to the second pixel circuit are in the same layer as the first gate metal layer; the data lines connected to the second pixel circuits located in the even columns are in the same layer as the second gate metal layer; the i-th The data lines connected to the second pixel circuits from the columns to the nth column are in the same layer as the first source-drain metal layer, i is an integer greater than 1 and less than n, and n is equal to each target sub-display area. Total number of columns.
  • the data lines connected to each of the second pixel circuits include: a first data line segment, a second data line segment, and a third data line segment;
  • One end of the first data line segment is connected to the corresponding metal layer, the other end is connected to one end of the second data line segment, the other end of the second data line segment is connected to one end of the third data line segment, and the The other end of the third data line segment is connected to the second pixel circuit;
  • the second data line segment extends along the first direction, and the second data line segment included in the data line on the same layer as the first gate metal layer, and the second data line segment on the same layer as the second gate metal layer
  • the second data line segment included in the data line and the second data line segment included in the data line at the same layer as the first source-drain metal layer do not overlap with each other.
  • the second source-drain metal layer covers the first gate metal layer, the second gate metal layer and the first source-drain metal layer.
  • the data line connected to the second pixel circuit located in the first sub-display area is connected to the second pixel located in the second sub-display area.
  • the data lines connected to the circuit are different.
  • the display panel further includes at least one column of dummy second pixel circuits, and the at least one column of dummy second pixel circuits is located in the target sub-display area close to the second display area.
  • the width of any pixel circuit is smaller than the width of any of the first light-emitting elements.
  • the width of each pixel circuit is different from the width of the first light-emitting element by 4 microns.
  • each of the second pixel circuits and each of the second light-emitting elements has an adapter portion, the conductive lines are respectively connected to the adapter portion of the at least one second pixel circuit, and the at least one adapter of the second light-emitting element.
  • the conductive wire is a transparent conductive wire.
  • the material of the transparent conductive wire is indium tin oxide.
  • the second display area is a light-transmitting display area.
  • a display device comprising: an integrated circuit, and the display panel according to the above aspect;
  • the integrated circuit is connected to the first pixel circuit and the second pixel circuit in the display panel, and is used for driving the first pixel circuit and the second pixel circuit to work;
  • the display device further includes: a photosensitive sensor, and the photosensitive sensor is located in the second display area of the display panel.
  • the second display area is rectangular, and the orthographic projection area of the photosensitive sensor on the base substrate is less than or equal to an area of an inscribed circle of the second display area.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 7 is a layout of a pixel circuit before and after compression provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 10 is a structural layout of a pixel circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • 16 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • 21 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of a conductive wire provided by an embodiment of the present application.
  • 24 is a schematic structural diagram of a conductive wire provided by an embodiment of the present application.
  • 25 is a schematic structural diagram of a conductive wire provided by an embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 27 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 29 is a cross-sectional view of a display panel provided by an embodiment of the present application.
  • FIG. 30 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 31 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • 32 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • 33 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 34 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 35 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • 36 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 37 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 38 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 39 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 40 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 41 is a schematic structural diagram of a data line provided by an embodiment of the present application.
  • FIG. 42 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 43 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • FIG. 44 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the embodiment of the present application provides a display panel, which does not reduce the non-transparent display area on the premise of ensuring reliable driving of light-emitting elements in the transparent display area and ensuring good light transmittance of the transparent display area
  • the number of internal pixels ensures a better display effect in the non-transparent display area.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in Figure 1, the display panel may include:
  • a base substrate 01 the base substrate 01 may have a first display area A1 and a second display area A2, and the first display area A1 may at least partially surround the second display area A2.
  • the second display area A2 shown in FIG. 1 is located at the top middle position of the base substrate 01.
  • the four sides of the rectangular first display area A1 may surround the second display area A2, that is, the second display area.
  • the area A2 may be surrounded by the first display area A1.
  • the second display area A2 may not be located at the top middle position of the base substrate 01 shown in FIG. 1 , but may be located at other positions.
  • the second display area A2 may be located at the upper left corner or the upper right corner of the base substrate 01 .
  • the display panel may further include: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20 and a plurality of first light emitting circuits located in the first display area A1
  • the element 30, and the plurality of second light-emitting elements 40 located in the second display area A2 and the plurality of second pixel circuits 20 may be distributed among the plurality of first pixel circuits 10 at intervals.
  • At least one first pixel circuit 10 of the plurality of first pixel circuits 10 may be connected to at least one first light-emitting element 30 of the plurality of first light-emitting elements 30, and the at least one first pixel circuit 10 is located on the base substrate
  • the orthographic projection on 01 and the orthographic projection of the at least one first light-emitting element 30 on the base substrate 01 may at least partially overlap.
  • the at least one first pixel circuit 10 can be used to provide a driving signal for the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light.
  • At least one second pixel circuit 20 in the plurality of second pixel circuits 20 can be connected with at least one second light emitting element 40 in the plurality of second light emitting elements 40 through the conductive line L1, and the at least one second pixel circuit 20 can be connected with the conductive line L1.
  • a driving signal is provided for the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light.
  • the second light-emitting element 40 and the second pixel circuit 20 are located in different regions, as shown in FIG.
  • the orthographic projections on the base substrate 01 do not have overlapping portions.
  • the first display area A1 may be set as a non-transmissive display area
  • the second display area A2 may be set as a light-transmissive display area. That is, the first display area A1 described in the embodiments of the present application is not transparent to light, and the second display area A2 is transparent to light. In this way, there is no need to perform hole-digging processing on the display panel, and required hardware structures such as photosensitive sensors can be directly disposed in the second display area A2, which lays a solid foundation for the realization of a true full screen.
  • the second display area A2 since the second display area A2 only includes light-emitting elements and does not include pixel circuits, it can also ensure that the second display area A2 has a better light transmittance.
  • the embodiments of the present application provide a display panel including a base substrate having a first display area and a second display area. Since the pixel circuits driving the light-emitting elements in the second display area are only located in the first display area and not located in the second display area, it is ensured that the light transmittance of the second display area is good. Correspondingly, the display panel described in the embodiments of the present application has a better display effect.
  • FIG. 3 takes the display panel shown in FIG. 2 as an example, and shows a schematic structural diagram of another display panel. Referring to FIG. 3 , it can be further seen that the first display area A1 not only includes a plurality of pixels, but also includes multiple columns of second pixel circuits 20 , and the second display area A2 only includes a plurality of second light-emitting elements 40 .
  • the pixel refers to a structure including a pixel circuit and a light-emitting element.
  • each pixel shown includes: a red sub-pixel R , two green sub-pixels G1 and G2, and one blue sub-pixel B, and the red sub-pixel R and the blue sub-pixel B are located in the same column, and the two green sub-pixels G1 and G2 are located in the same column.
  • the pixel may also include other colors and other numbers of sub-pixels, and the arrangement of each sub-pixel is not limited to the structure shown in FIG. 3 .
  • each pixel may include only one red sub-pixel R, one blue sub-pixel B, and one green sub-pixel G.
  • the electrical connection relationships between the plurality of first pixel circuits 10 and the plurality of first light emitting elements 30 may be in one-to-one correspondence. That is, each of the first pixel circuits 10 may be connected to one first light-emitting element 30 , and the first light-emitting elements 30 connected to each of the first pixel circuits 10 are different. Therefore, with reference to the display panel shown in FIG. 2 , the orthographic projection of each first pixel circuit 10 on the base substrate 01 and the orthographic projection of the connected first light-emitting element 30 on the base substrate 01 both at least partially overlap.
  • the electrical connection relationship between the plurality of second pixel circuits 20 and the plurality of second light emitting elements 40 can also be in one-to-one correspondence. Moreover, the orthographic projection of each two-pixel circuit 20 on the base substrate 01 does not overlap with the orthographic projection of the connected second light-emitting element 40 on the base substrate 01 .
  • the density of the plurality of second light-emitting elements 40 located in the second display area A2 and the plurality of first light-emitting elements 30 located in the first display area A1 may be the same. That is, the number of light-emitting elements included per inch in the first display area A1 and the second display area A2 is the same. That is, the first display area A1 (ie, the main display area) does not have two sub-areas with different pixel densities. Furthermore, compared with the related art, when displaying a picture, the first display area A1 does not have a light-dark boundary, and the display of the display panel The effect is better.
  • FIG. 4 shows a structural layout of a display panel.
  • the resolution of the first display area A1 may be greater than that of the second display area A2. That is, the area of the first display area A1 is larger than that of the second display area A2, and the number of light-emitting elements included in the first display area A1 is larger than that of the second display area A2.
  • the resolution of the first display area A1 may be less than or equal to the resolution of the second display area A2.
  • the area of the first display area A1 and the area of the second display area A2 may be the same, and the number of light-emitting elements included in the first display area A1 and the number of light-emitting elements included in the second display area A2 are also the same.
  • the area of the first display area A1 may be smaller than that of the second display area A2, and the number of light-emitting elements included in the first display area A1 is smaller than that of the second display area A2.
  • FIG. 5 shows a partially enlarged schematic diagram of the display panel shown in FIG. 4 . 4 and 5, it can be seen that the size of the first light-emitting element 30 may be larger than the size of the second light-emitting element 40, that is, the anode of the light-emitting element in the second display area A2 is compared to the anode of the light-emitting element in the first display area A1.
  • the anode is smaller.
  • the shape and size of the anode of the second light-emitting element 40 can be further optimized to ensure better light transmittance.
  • the anode of the second light-emitting element 40 shown is elliptical.
  • the conductive wire L1 described in the embodiment of the present application may be a transparent conductive wire.
  • the conductive line L1 may be made of transparent materials such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO).
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • the conductive line L1 may also be called an ITO trace.
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • the photosensitive sensor 50 in the display module included in the display device is The structure (eg, the camera) can be directly disposed in the second display area A2, that is, there is no need to dig additional holes in the display panel. In this way, a solid foundation has been laid for the realization of the full-screen display panel.
  • the second display area A2 may be a rectangle, and the area of the orthographic projection of the photosensitive sensor 50 on the base substrate 01 may be smaller than or equal to the area of the inscribed circle of the second display area A2. That is, the size of the area where the photosensitive sensor 50 is located may be smaller than or equal to the size of the inscribed circle of the second display area A2.
  • the area of the orthographic projection of the photosensitive sensor 50 on the base substrate 01 may be smaller than or equal to the area of the inscribed circle of the second display area A2. That is, the size of the area where the photosensitive sensor 50 is located may be smaller than or equal to the size of the inscribed circle of the second display area A2.
  • the size of the area where the photosensitive sensor 50 is located is equal to the size of the inscribed circle Y0 of the second display area A2, that is, the shape of the area where the photosensitive sensor 50 is located may be a circle, Correspondingly, the area where the photosensitive sensor 50 is located may also be referred to as a light-transmitting hole.
  • the second display area A2 may also have other shapes than rectangles, such as circles or ellipses.
  • the pixel circuit (including the first pixel circuit 10 and the second pixel circuit 20 ) and the first light-emitting element 30 have the same pitch.
  • a typical width is about 30 micrometers ( ⁇ m) to 32 ⁇ m, and a length is about 60 ⁇ m to 65 ⁇ m.
  • the The line extending direction also referred to as lateral direction
  • the light emitting element 30 is extended so that the width of the first light emitting element 30 in the second direction is larger than the width of the first light emitting element 30 .
  • the width of each pixel circuit and the width of the first light emitting element 30 may be different by about 4 ⁇ m.
  • FIG. 7 shows the structural layout of the pixel circuit before and after compression (ie, the related art and the embodiments of the present application).
  • the pixel circuit may include a driving structure and a transition portion B1 for connecting to the anode of the light-emitting element, and the size of the transition portion B1 may represent the size of the pixel circuit.
  • the size of the pixel circuit and the light-emitting element before compression is 1-100 ⁇ m wide and 2-200 ⁇ m high.
  • the size of the light-emitting element remains unchanged, the height of the pixel circuit remains unchanged, but the width is narrowed by 1-20 ⁇ m, so that every few columns
  • the compressed pixel circuit will add one or more columns of compressed pixel circuits, and the entire screen adopts this design to achieve full-screen compression.
  • the extra columns can be selected to connect the second light emitting elements 40 in the second display area A2 to control the second light emitting elements 40 to emit light.
  • more columns of pixel circuits close to the periphery of the second display area A2 are preferably used as the second pixel circuits 20 to connect to the second light-emitting element 40 . In this way, normal display can be ensured without changing the resolution of the display panel. That is, the existing space of the display panel is fully utilized to realize normal display.
  • the width of the pixel circuit may refer to the length of the orthographic projection of the layout of the pixel circuit along the second direction X2 on the base substrate 01 .
  • the width of the first light-emitting element 30 refers to the length of the orthographic projection of the anode of the first light-emitting element 30 on the base substrate 01 along the second direction X2.
  • each of the first light-emitting elements described in the embodiments of the present application belongs to one sub-pixel in one pixel.
  • it may be red sub-pixel R, green sub-pixel G1, G2 or blue sub-pixel B.
  • the width D10 of the pixel in the first direction X1 or the second direction X2 can be measured in a period of one pixel, and then for the width D01 of each first light-emitting element , the total pixel width D10 may be divided by the number of sub-pixels included in the pixel (for example, 4 shown in FIG. 8 ).
  • each first light-emitting element is connected to a corresponding pixel circuit, it is still possible to measure the width of each pixel circuit in the first direction X1 or the second direction X2 with each pixel circuit connected to a pixel as a cycle, and then For the width D0 of each pixel circuit, the total width may be divided by the number of sub-pixels included in the pixel.
  • the pixel circuit described in this embodiment of the present application may have a 7T1C structure, that is, including 7 transistors and 1 capacitor.
  • FIG. 9 shows a schematic structural diagram of a 7T1C pixel circuit
  • FIG. 10 shows a structural layout of the 7T1C pixel circuit.
  • the 7T1C pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, and a third light-emitting control transistor T5.
  • the pixel circuit can be connected to the gate signal terminal Gate, the data signal terminal Data, the reset signal terminals RST1 and RST2, the light-emitting control signal terminal EM, the power supply terminal VDD, the initial power supply terminals Vinit1 and Vinit2, and the light-emitting element.
  • the light-emitting element can also be connected. Connect to the power supply terminal VSS.
  • the pixel circuit can be used to drive the connected light-emitting element to emit light in response to signals provided by the connected signal terminals.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the embodiments of the present application are described by taking P-type transistors as an example for all the transistors. Based on the descriptions and teachings of the implementation in this application, those of ordinary skill in the art can easily think of using N-type transistors for at least some of the transistors in the pixel circuit structure of the embodiments of the application, that is, using N-type transistors without any creative work. Therefore, these implementations are also within the protection scope of the embodiments of the present application.
  • FIG. 11 shows a schematic structural diagram of a first display area A1 .
  • FIG. 12 shows a schematic diagram of a partial structure (including only pixel circuits) in FIG. 4
  • FIG. 13 shows a schematic diagram of a partial structure (including only light-emitting elements) in FIG. 4 .
  • each of the first light emitting elements 30 may include a total of 4 types of anodes of RG1BG2 and a transition part B2 for connecting with the first pixel circuit 10 .
  • the connecting portion B1 of the first pixel circuit 10 and the connecting portion B2 of the first light-emitting element 30 may be connected through the source-drain metal layer SD2. Alternatively, if the first pixel circuit 10 and the first light-emitting element 30 are already overlapped together, there is no need to set the SD2 line connection.
  • At least one second pixel circuit 20 and at least one second light-emitting element 40 may also both have adapters, and at least one second pixel circuit 20 and at least one second light-emitting element 40 may be connected by conductive lines L1.
  • the conductive lines L1 are respectively connected to at least one transition part of the second pixel circuit 20 and at least one transition part of the second light emitting element 40 .
  • the axis of the transition portion of each second pixel circuit 20 located in the same row can be parallel to the axis of the transition portion of any second light-emitting element 40. Aligned, the axis may extend along the second direction X2. That is, in the same row in the row direction, the transition portion of the second pixel circuit 20 and the transition portion of the second light-emitting element 40 are located directly on the same line. 11 to 13 , in the same row, the transition part B1 of the first pixel circuit 10 and the transition part B2 of the first light-emitting element 30 can also be located directly on the same line, so that the wiring can be arranged. tidy.
  • FIG. 14 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • the first display area A1 may include: a first sub-display area A11 and a second sub-display area A12 arranged in sequence along the first direction X1.
  • the first sub-display area A11 may include: two symmetrical target sub-display areas A110. That is, the layouts of the two target sub-display areas A110 are the same.
  • the second display area A2 may include two third sub-display areas A21 symmetrically arranged along the second direction X2. That is, the layouts of the two third sub-display areas A21 are the same.
  • one target sub-display area A110, the second display area A2 and the other target sub-display area A110 may be sequentially arranged along the second direction X2.
  • the following embodiments only show the structure of the left half of the display panel, that is, a target sub-display area A110 and an adjacent third sub-display area A21 located in the left half. The same is true for the right half and will not be repeated here.
  • the multi-column pixel circuits described in the embodiments of the present application that is, a plurality of second pixel circuits 20 can be dispersedly arranged in the first display area A1, and the arrangement position can be flexibly adjusted according to the requirements, as long as it is guaranteed to be compatible with the second pixel circuits 20 .
  • the element 40 is effectively connected and the second light-emitting element 40 is driven to emit light reliably.
  • the arrangement positions of the second pixel circuits 20 are schematically described as follows by taking a plurality of second pixel circuits 20 dispersedly arranged in the column direction, the row direction and the diagonal direction as an example:
  • FIG. 15 is a schematic structural diagram of still another display panel provided by an embodiment of the present application. 14 and 15, it can be seen that the plurality of first pixel circuits 10 may include a plurality of columns of first pixel circuits 10 extending along the first direction X1, and the plurality of second pixel circuits 20 may include a plurality of second pixel circuits 20 extending along the first direction X1 A plurality of columns of second pixel circuits 20 are provided.
  • the plurality of columns of second pixel circuits 20 may be distributed among the plurality of columns of first pixel circuits 10 at intervals. For example, there is one column of second pixel circuits 20 at every interval of a plurality of adjacent columns of first pixel circuits 10 . In other words, multiple adjacent columns of the first pixel circuits 10 may be spaced between every two adjacent columns of the second pixel circuits 20 .
  • the same number of columns of first pixel circuits 10 may be spaced between any two adjacent columns of second pixel circuits 20, thus ensuring the uniformity of the arrangement.
  • any two adjacent columns of the second pixel circuits 20 are spaced apart by eight adjacent columns of the first pixel circuits 10 .
  • any two adjacent columns of the second pixel circuits 20 may be spaced with different columns of the first pixel circuits 10 .
  • the pixel circuits in the second column, the pixel circuits in the 12th column, and the 20th column to the left are The pixel circuits may all be the second pixel circuits 20 . It should be noted that the additional columns of the second pixel circuits 20 below the second display area A2 can be used as dummy columns and are not connected to any light-emitting elements.
  • FIG. 17 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • the plurality of first pixel circuits 10 may include a plurality of rows of first pixel circuits 10 extending along the second direction X2
  • the plurality of second pixel circuits 20 may include a plurality of rows of second pixel circuits 10 extending along the second direction X2 pixel circuit 20 .
  • the first direction X1 and the second direction X2 may intersect.
  • the plurality of second pixel circuits 20 may be arranged in a diagonal direction.
  • the plurality of second pixel circuits 20 can be arranged in the row direction.
  • the plurality of rows of second pixel circuits 20 are distributed between the plurality of rows of first pixel circuits 10 at intervals.
  • the plurality of second pixel circuits 20 shown in FIG. 17 extend in the row direction, that is, there is one row of the second pixel circuits 20 for every adjacent row of the first pixel circuits 10 .
  • multiple rows of adjacent first pixel circuits 10 may be spaced between every two adjacent rows of the second pixel circuits 20 .
  • the following embodiments are all described by taking as an example that the plurality of second pixel circuits 20 are sequentially arranged in the column direction.
  • FIG. 18 is a schematic structural diagram of still another display panel provided by an embodiment of the present application.
  • the display panel may include: a first conductive line L11 (ie, ITO1 ), a second conductive line L12 (ie, ITO2 ) and a third conductive line L13 (ie, ITO3 ).
  • Each third sub-display area A21 may include k light-emitting element groups.
  • Each light-emitting element group may include multiple adjacent rows of second light-emitting elements 40 , and the first to the k-th light-emitting element group may be sequentially arranged in a direction close to another third sub-display area.
  • each target sub-display area A110 includes k pixel circuit groups corresponding to the k light-emitting element groups Z0 one-to-one.
  • Each pixel circuit group may include multiple adjacent columns of second pixel circuits 20 , and the first pixel circuit group to the kth pixel circuit group may be sequentially arranged in a direction away from the adjacent third sub-display areas.
  • k can be an integer greater than 0.
  • k is 4 as an example for description.
  • the first light-emitting element group Z01 to the third light-emitting element group Z03 may respectively include 12 columns of second light-emitting elements 40 .
  • the fourth light-emitting element group Z04 may include eight columns of the second light-emitting elements 40 .
  • the first pixel circuit group Z11 to the third pixel circuit group Z13 may respectively include 12 columns of second pixel circuits 20 .
  • the fourth pixel circuit group Z14 may include 8 columns of second pixel circuits 20 .
  • the second light-emitting elements 40 in the first row to the second light-emitting elements 40 in the thirteenth row belong to the first light-emitting element group Z01 ;
  • the 14th column of the second light-emitting element 40 to the 26th column of the second light-emitting element 40 belong to the second light-emitting element group Z02;
  • the 27th column of the second light-emitting element 40 to the 39th column of the second light-emitting element 40 ie, R27 to R39
  • the 40th column second light emitting element 40 to the 48th column second light emitting element 40 belong to the 4th light emitting element group Z04.
  • the second pixel circuit 20 in the first column to the second pixel circuit 20 in the thirteenth column (ie, P1 to P13) belong to the first pixel circuit group Z11; the second pixel circuit in the 14th column belongs to the first pixel circuit group Z11;
  • the second pixel circuits 20 in the 20th to 26th columns (ie, P14 to P26) belong to the second pixel circuit group Z12; belong to the 3rd pixel circuit group Z13; the 40th column second pixel circuit 20 to the 48th column second pixel circuit 20 (ie, P40 to P48) belong to the 4th pixel circuit group Z14. Only the first pixel circuit 10 and the first light emitting element 30 are not shown in FIG. 18 .
  • each second light-emitting element 40 in each light-emitting element group and each second pixel circuit 20 in a corresponding pixel circuit group can pass through the first conductive line L11, the second The conductive line L12 and/or the third conductive line L13 are connected.
  • each second light emitting element 40 in the first light emitting element group Z01 and each second pixel circuit 20 in the first pixel circuit group Z11 can pass through the first conductive line L11 (FIG. 19
  • the first conductive line L11) is connected by ITO1.
  • each second light emitting element 40 in the second light emitting element group Z02 and each second pixel circuit 202 in the second pixel circuit group Z12 can pass through the second conductive line L12 (in FIG. 20, ITO2 Represents the connection of the second conductive line L12).
  • each second light emitting element 40 in the third light emitting element group Z03 and each second pixel circuit 20 in the third pixel circuit group Z13 can pass through the third conductive line L13 (in FIG. 21, ITO3 It represents the connection of the third conductive line L13).
  • each second light emitting element 40 in the fourth light emitting element group Z04 and each second pixel circuit 20 in the fourth pixel circuit group Z14 can pass through the first conductive line L11 (ie, ITO1 ) , the second conductive line L12 (ie, ITO2) and the third conductive line L13 are connected (ie, ITO3).
  • the fourth light-emitting element group Z04 may include: two first sub-light-emitting element groups Z041, two second sub-light-emitting element groups Z042 and two symmetrically arranged along the axis xx of the third sub-display area A21 Two third sub-light-emitting element groups Z043.
  • each sub-light-emitting element group may include adjacent rows of second light-emitting elements 40, and the number of rows of second light-emitting elements 40 included in each sub-light-emitting element group may be the same or different.
  • first sub-light-emitting element group Z041, the second sub-light-emitting element group Z042 and the third sub-light-emitting element group Z043 located on the same side may be sequentially arranged in a direction away from the axis xx, which extends along the second direction X2.
  • the fourth pixel circuit group Z14 may include two first sub-pixel circuit groups Z141 one-to-one corresponding to the two first sub-light-emitting element groups Z041, and two first sub-pixel circuit groups Z141 one-to-one corresponding to the two second sub-light-emitting element groups Z042 Two sub-pixel circuit groups Z142, and two third sub-pixel circuit groups Z143 corresponding to the two third sub-pixel circuit groups Z043 one-to-one. And the arrangement of the first sub-pixel circuit group Z141 , the second sub-pixel circuit group Z142 and the third sub-pixel circuit group Z143 located on the same side is the same as that of the sub-light-emitting element group.
  • each second light-emitting element 40 in each first sub-light-emitting element group Z041 and each second pixel circuit 20 in the corresponding first sub-pixel circuit group Z141 can pass through the first conductive line L11 (ie, ITO1) connect.
  • Each second light-emitting element 40 in each second sub-light-emitting element group Z042 and each second pixel circuit 20 in the corresponding second sub-pixel circuit group Z142 may be connected through second conductive lines L12 (ie, ITO2 ).
  • Each second light-emitting element 40 in each third sub-light-emitting element group Z043 and each second pixel circuit 20 in the corresponding third sub-pixel circuit group Z143 may be connected through third conductive lines L13 (ie, ITO3).
  • FIG. 23 is a schematic structural diagram of a conductive wire provided by an embodiment of the present application.
  • FIG. 24 is a layout of the structure shown in FIGS. 19 to 21 . 19 to 21, it can be seen that the first conductive lines L11 connected to the second light-emitting elements 40 in the first light-emitting element group Z01, and the second light-emitting elements 40 in the second light-emitting element group Z02
  • the connected second conductive line L12 and each third conductive line L13 connected to each second light-emitting element 40 in the third light-emitting element group Z03 may include: a first conductive line segment La, a second conductive line segment Lb and the third conductive line segment Lc.
  • One end of the first conductive line segment La may be connected to the corresponding second light emitting element 40, and the other end of the first conductive line segment La is connected to one end of the second conductive line segment Lb.
  • the other end of the second conductive line segment Lb may be connected to one end of the third conductive line segment Lc.
  • the other end of the third conductive line segment Lc may be connected to the corresponding second pixel circuit 20 .
  • first conductive line segment La and the third conductive line segment Lc may extend along the first direction X1
  • the second conductive line segment Lb may extend along the second direction X2
  • the orthographic projection of the second conductive line segment Lb on the base substrate 01 is at least Part of it overlaps with the orthographic projection of the second light-emitting element 40 on the base substrate 01 (see FIG. 24 below). That is, the first conductive line L11, the second conductive line L12 and the third conductive line L13 can all be drawn out from the connected second light-emitting element 40, and extend laterally to the position of the second pixel circuit 20 in their own direction, so as to be connected with the second pixel circuit 20. Circuit 20 is connected.
  • the second conductive line segment Lb included in the first conductive line L11 and the second conductive line segment Lb included in the third conductive line L13 may at least partially overlap.
  • the second conductive line segment Lb included in the first conductive line L11 and the second conductive line segment Lb included in the second conductive line L12 may not overlap, and the second conductive line segment Lb included in the third conductive line L13 and the second conductive line segment L1 included in the second conductive line L12
  • the second conductive line segments Lb may also not overlap. Overlapping parts can be switched through vias.
  • FIG. 24 only schematically shows the first conductive line L11 connected to each second light-emitting element 40 in the first light-emitting element group Z01 , that is, the structure layout of the ITO1 wiring in the display panel.
  • the second conductive lines L12 ie, ITO2 wiring
  • the third light-emitting element group Z03 the second light-emitting elements 40 are connected to each other
  • the structural layout of the third conductive line L13 ie, the ITO3 line
  • FIG. 25 is a schematic structural diagram of a conductive wire provided by an embodiment of the present application.
  • the first conductive line L11 connected to each second light-emitting element 40 in each first sub-light-emitting element group Z041 is connected to each second light-emitting element 40 in each second sub-light-emitting element group Z042
  • the connected second conductive lines L12 and the third conductive lines L13 connected to the respective second light-emitting elements 40 in each third sub-light-emitting element group Z043 may include: a fourth conductive line segment Ld, a fifth conductive line segment Le and The sixth conductive line segment Lf and the seventh conductive line segment Lg.
  • One end of the fourth conductive line segment Ld may be connected to the corresponding second light emitting element 40, and the other end of the fourth conductive line segment Ld is connected to one end of the fifth conductive line segment Le.
  • the other end of the fifth conductive line segment Le may be connected to one end of the sixth conductive line segment Lf.
  • the other end of the sixth conductive line segment Lf may be connected to one end of the seventh conductive line segment Lg.
  • the other end of the seventh conductive line segment Lg may be connected to the corresponding second pixel circuit 20 .
  • the fifth conductive line segment Le and the seventh conductive line segment Lg may extend along the first direction X1
  • the sixth conductive line segment Lf may extend along the second direction X2.
  • the fourth conductive line segment Ld may be located between the row where the connected second light emitting elements 40 are located and the adjacent row.
  • FIG. 26 is a schematic structural diagram of still another display panel provided by an embodiment of the present application
  • FIG. 27 is a structural schematic diagram of still another display panel provided by an embodiment of the present application
  • FIG. 28 is a simplified schematic diagram of the display panel shown in FIG. 27 . 26 to 28, it can be seen that the fifth conductive line segment Le included in the first conductive line L11 (ie, ITO1 in the figure) can be located in the region where the second light-emitting element group Z02 to the fourth light-emitting element group Z04 are located.
  • the fifth conductive line segment Le included in the second conductive line L12 may be located in the region where the third light-emitting element group Z03 and the fourth light-emitting element group Z04 are located.
  • the fifth conductive line segment Le included in the third conductive line L13 may be located in the region where the fourth light-emitting element group Z04 is located.
  • the sixth conductive line segment Lf on the side away from the second sub-display area A12 along the axis may be located on the side of the second display area A2 away from the second sub-display area A12, and the sixth conductive line segment on the side close to the second sub-display area A12 along the axis Lf may be located in the second display area A2 close to the second sub-display area A12.
  • the fifth conductive line segment Le included in the first conductive line L11 can be drawn out from the connected second light-emitting element 40, and can be drawn from the region where the second light-emitting element 40 is located in the columns R14 to R48 (ie, the region where Z02 to Z04 are located) It extends along the column direction to the side of the third sub-display area A21 that is close to the non-display area or close to the second sub-display area A12, and then extends laterally along the row direction to the area where the corresponding second pixel circuit 20 is located to be compatible with the second pixel. Circuit 20 is connected.
  • the fifth conductive line segment Le included in the second conductive line L12 can be drawn out from the connected second light-emitting elements 40 and extend in the column direction from the regions of the columns R27 to R48 where the second light-emitting elements 40 are located (ie, the regions where Z03 and Z04 are located)
  • the third sub-display area A21 is close to the non-display area or the side of the second sub-display area A12, and then extends laterally along the row direction to the corresponding area of the second pixel circuit 20 for connection with the second pixel circuit 20.
  • the fifth conductive line segment Le included in the third conductive line L13 can be drawn out from the connected second light-emitting element 40, and extends from the area where the second light-emitting element 40 is located (ie, the area where Z04 is located) in the column direction from R40 to R48 in the column direction to the second light-emitting element 40.
  • the three sub-display areas A21 are close to the non-display area or one side of the second sub-display area A12 , and then extend laterally along the row direction to the corresponding area of the second pixel circuit 20 to be connected to the second pixel circuit 20 .
  • the sixth conductive line segments Lf included in the conductive lines located on the same side and extending in the row direction may partially overlap, or may not overlap.
  • the display panel may further include at least one column of dummy second pixel circuits 20, and the at least one column of dummy second pixel circuits 20 may be located in the target sub-display area A110.
  • the column of dummy second pixel circuits 20 may also be called a transition column, and the column of dummy second pixel circuits 20 is not connected to any light-emitting element.
  • the distance between the second light-emitting elements 40 in the first column and the second pixel circuits 20 to which they are connected can be avoided.
  • the problem of the large turn-on time difference between the second light-emitting element 40 in the row and the second light-emitting element 40 in the last row further ensures a better display effect.
  • the first conductive lines L11 ie, ITO1 shown in the figure
  • the second conductive lines L12 ie, ITO2 shown in the figure
  • the second conductive lines L12 connected to the second light-emitting elements 40 located in adjacent rows may be located on the same upward side, or may be located on different sides symmetrically Arrange.
  • the third conductive lines L13 (ie, ITO1 shown in the figure) connected to the second light-emitting elements 40 located in adjacent rows may be located on the same side facing upward, or may be located on different sides symmetrically Arrange.
  • the above signal lines may also all be located on the same side facing downward, which will not be repeated in the accompanying drawings.
  • FIG. 29 shows a cross-sectional view of the display panel.
  • ITO1 represents the first conductive line L11
  • ITO2 represents the second conductive line L12
  • ITO3 represents the third conductive line L13.
  • Anode refers to the anode of the light-emitting element
  • PLN refers to the flat layer
  • the display panel shown in FIG. 29 includes a total of 5 layers of flat layers PLN1 to PLN5
  • SD1 refers to the first source-drain metal layer
  • SD2 refers to the second source-drain layer metal layer.
  • the display panel may further include: a first gate metal layer GATE1 , a second gate metal layer GATE2 , a first source-drain metal layer SD1 and a second source-drain metal layer SD2 and other metal layers.
  • the data line DATA connected to each second pixel circuit 20 may be disposed in the same layer as any metal layer.
  • the second pixel circuits 20 in the first to i-th columns in each target sub-display area A110 are located in odd-numbered columns
  • the data line DATA connected to the second pixel circuit 20 may be in the same layer as the first gate metal layer GATE1.
  • the data lines DATA connected to the second pixel circuits 20 in the even-numbered columns may be in the same layer as the second gate metal layer GATE2.
  • the data lines DATA connected to the second pixel circuits 20 in the i-th to n-th columns may be at the same layer as the first source-drain metal layer SD1.
  • i may be an integer greater than 1 and less than n
  • n may be equal to the total number of columns in each target sub-display area A110. That is, the data lines DATA connected to the second pixel circuits 20 in the first i columns can be alternately arranged at the same layer as GATE1 and GATE2. The data lines DATA connected to the second pixel circuits 20 in the i-th column to the n-th column may all be arranged in the same layer as SD1.
  • the third sub-display area A21 includes 48 columns of second light-emitting elements 40, i may be 24, that is, every 24 columns of second light-emitting elements 40 may be a group.
  • the data lines DATA connected to the odd-numbered columns may be in the same layer as the first gate metal layer GATE1
  • the data lines connected to the even-numbered columns DATA may be in the same layer as the second gate metal layer GATE2
  • the data lines DATA connected to the 24th to 48th columns are all in the same layer as the first source-drain metal layer SD1.
  • FIG. 31 and FIG. 32 show the structural layouts of the data lines DATA connected to the second pixel circuits 20 in odd-numbered columns at the same layer as the first gate metal layer GATE1 at different positions.
  • FIG. 33 and FIG. 34 show the structural layouts of the data lines DATA connected to the second pixel circuits 20 in the even-numbered columns at the same layer as the second gate metal layer GATE2 at different positions.
  • FIG. 35 and FIG. 36 show the structural layout of the same layer as SD1 and the data lines DATA connected to the second pixel circuits 20 in the i-th to n-th columns at different positions.
  • FIG. 38 show the overall layout of the display panel at different positions, on the same layer as the first gate metal layer GATE1, on the same layer as the second gate metal layer GATE2, and on the same layer as SD1.
  • FIG. 39 and FIG. 40 show the structure layout including the conductive line L1 and the data line DATA.
  • FIG. 41 shows a schematic structural diagram of a data line. It can be seen from the above figures related to the data lines that the data line DATA connected to each second pixel circuit 20 may include a first data line segment D11, a second data line segment D12 and a third data line segment D13.
  • One end of the first data line segment D11 may be connected to the corresponding metal layer, the other end may be connected to one end of the second data line segment D12, the other end of the second data line segment D12 may be connected to one end of the third data line segment D13, and the third The other end of the three data line segments D13 may be connected to the second pixel circuit 20 .
  • the second data line segment D12 may extend along the first direction X1, and the data line DATA in the same layer as the first gate metal layer GATE1 includes the second data line segment D12 and the data in the same layer as the second gate metal layer GATE2
  • the second data line segment D12 included in the line DATA and the second data line segment D12 included in the data line DATA at the same layer as the first source-drain metal layer SD1 may not overlap with each other.
  • each data line DATA can be drawn from the boundary line between the third sub-display area A21 and the second sub-display area A12 through the metal layer, and extend from the display area in the column direction in the third sub-display area A21 to the non-display area, and then extends to the second pixel circuit 20 in the corresponding column along the row direction, and is connected to the second pixel circuit 20 .
  • the data line DATA connected to the second pixel circuit 20 located in the first sub-display area A11 is connected to the second pixel circuit 20 located in the second sub-display area A12.
  • the data lines DATA connected to the two pixel circuits 20 may be different.
  • the data line DATA connected to a column of the second pixel circuits 20 is disconnected from the boundary line between the first sub-display area A11 and the second sub-display area A12. In this way, the problem of mutual interference between signals provided by the data lines can be avoided, and effective and reliable driving of the second light-emitting element 40 can be ensured.
  • the second source-drain metal layer SD2 may cover the first gate metal layer GATE1 , the second gate metal layer GATE2 and the first source-drain metal layer SD1 . In this way, signal shielding of the point where the driving transistor and the light emitting element are connected can be achieved, thereby reducing signal crosstalk.
  • the influence of the parasitic capacitance on the conductive line L1 can be shielded to a certain extent, so as to ensure a better display effect.
  • the embodiments of the present application provide a display panel including a base substrate having a first display area and a second display area. Since the pixel circuits driving the light-emitting elements in the second display area are only located in the first display area and not located in the second display area, it is ensured that the light transmittance of the second display area is good. Correspondingly, the display panel described in the embodiments of the present application has a better display effect.
  • FIG. 44 is a schematic structural diagram of a display device provided by an embodiment of the present application. As shown in FIG. 44, the display device may include: an integrated circuit 100, and a display panel 200 as shown in any of the above-mentioned figures.
  • the integrated circuit 100 can be connected to the first pixel circuit and the second pixel circuit in the display panel 200, and is used for driving the first pixel circuit and the second pixel circuit to work.
  • the driving circuit 100 can be connected to each signal terminal connected to the pixel circuit, and is used to provide signals for each signal terminal.
  • FIG. 44 only schematically shows the position of the integrated circuit 100 , and the integrated circuit 100 may also be located on the right side of the display panel 200 , or may be located on both the left side and the right side of the display panel 200 . Alternatively, it may also be located on the upper side and/or the lower side of the display panel 200 .
  • the display device can be: an organic light-emitting diode (organic light-emitting diode, OLED) display device, an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED) display device, a mobile phone, a tablet computer , flexible display devices, televisions, monitors and any other product or component with display function.
  • OLED organic light-emitting diode
  • AMOLED active-matrix organic light-emitting diode

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Abstract

本申请公开了一种显示面板及显示装置，该显示面板包括具有第一显示区和第二显示区的衬底基板。由于驱动第二显示区内发光元件的像素电路仅位于第一显示区而不位于第二显示区，因此确保了第二显示区的透光率较好。相应的，本申请公开的显示面板显示效果较好。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
相关技术中，具有屏下摄像头的显示面板一般包括用于正常显示的第一显示区以及用于设置摄像头的第二显示区。该第二显示区一般包括：多个发光元件和多个像素电路，每个像素电路与一个发光元件连接，并用于驱动发光元件发光，且相互连接的像素电路和发光元件在垂直于显示面板的方向上重叠。
由于相关技术中第二显示区内还设置有像素电路，因此第二显示区的透光率较差，相应的，显示面板的显示效果较差。
发明内容
本申请提供了一种显示面板及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，具有第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区；
多个第一像素电路、多个第二像素电路和多个第一发光元件，位于所述第一显示区，且所述多个第二像素电路间隔分布于所述多个第一像素电路之间；
多个第二发光元件，位于所述第二显示区；
其中，所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件连接，且所述至少一个第一像素电路在所述衬底基板上的正投影与所述至少一个第一发光元件在所述衬底基板上的正投影至少部分重叠；所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件通过导电线连接。
可选的，所述多个第二发光元件和所述多个第一发光元件的密度相同。
可选的，所述第一显示区的分辨率与所述第二显示区的分辨率相同；或，所述第一显示区的分辨率与所述第二显示区的分辨率不同。
可选的，每个所述第一像素电路与一个所述第一发光元件连接；
并且，每个所述第一像素电路在所述衬底基板上的正投影与所连接的所述第一发光元件在所述衬底基板上的正投影至少部分重叠。
可选的，所述多个第一像素电路包括沿第一方向延伸的多列第一像素电路，所述多个第二像素电路包括沿第一方向延伸的多列第二像素电路；
其中，所述多列第二像素电路间隔分布在所述多列第一像素电路之间。
可选的，任意相邻两列所述第二像素电路之间间隔相同列数或不同列数的所述第一像素电路。
可选的，所述多个第一像素电路包括沿第二方向延伸的多行第一像素电路，所述多个第二像素电路包括沿第二方向延伸的多行第二像素电路，所述第二方向与第一方向相交。其中，所述多行第二像素电路间隔分布在所述多行第一像素电路之间。
可选的，所述第一方向与所述第二方向垂直。
可选的，所述第一显示区包括：沿第一方向依次排布的第一子显示区和第二子显示区；所述第一子显示区包括：对称的两个目标子显示区；
其中，一个所述目标子显示区、所述第二显示区和另一个所述目标子显示区沿第二方向依次排布。
可选的，所述第二显示区包括沿所述第二方向对称排布的两个第三子显示区；所述显示面板包括：第一导电线、第二导电线和第三导电线；
每个所述第三子显示区包括k个发光元件组，每个所述发光元件组包括相邻的多列所述第二发光元件，且第1个所述发光元件组至第k个所述发光元件组沿靠近另一所述第三子显示区的方向依次排布，k为大于0的整数；
每个所述目标子显示区包括与所述k个发光元件组一一对应的k个像素电路组，每个所述像素电路组包括相邻的多列所述第二像素电路，且第1个所述像素电路组至第k个所述像素电路组沿远离相邻的所述第三子显示区的方向依次排布；且，每个所述发光元件组中的各个所述第二发光元件，与对应的一个所述像素电路组中的各个所述第二像素电路通过所述第一导电线、所述第二导电线和/或所述第三导电线连接。
可选的，k为4。
可选的，第1个所述发光元件组中的各个所述第二发光元件，与第1个所述像素电路组中的各个所述第二像素电路通过所述第一导电线连接；
第2个所述发光元件组中的各个所述第二发光元件，与第2个所述像素电路组中的各个所述第二像素电路通过所述第二导电线连接；
第3个所述发光元件组中的各个所述第二发光元件，与第3个所述像素电路组中的各个所述第二像素电路通过所述第三导电线连接；
第4个所述发光元件组中的各个所述第二发光元件，与第4个所述像素电路组中的各个所述第二像素电路通过所述第一导电线、所述第二导电线和所述第三导电线连接。
可选的，第1个所述发光元件组中的各个所述第二发光元件所连接的所述第一导电线，第2个所述发光元件组中的各个所述第二发光元件所连接的所述第二导电线，以及第3个所述发光元件组中的各个所述第二发光元件所连接的每条所述第三导电线，包括：第一导电线段、第二导电线段和第三导电线段；
所述第一导电线段的一端与对应的所述第二发光元件连接，所述第一导电线段的另一端与所述第二导电线段的一端连接；
所述第二导电线段的另一端与所述第三导电线段的一端连接；
所述第三导电线段的另一端与对应的所述第二像素电路连接；
其中，所述第一导电线段和所述第三导电线段沿所述第一方向延伸，所述第二导电线段沿所述第二方向延伸，且所述第二导电线段在所述衬底基板上的正投影至少部分与其所连接第二发光元件在所述衬底基板上的正投影重叠。
可选的，所述第一导电线包括的所述第二导电线段与所述第三导电线包括的所述第二导电线段至少部分重叠，所述第一导电线包括的所述第二导电线段与所述第二导电线包括的所述第二导电线段不重叠，且所述第三导电线包括的所述第二导电线段与所述第二导电线包括的所述第二导电线段不重叠。
可选的，第4个所述发光元件组包括：沿所述第三子显示区的轴线对称排布的两个第一子发光元件组，两个第二子发光元件组以及两个第三子发光元件组，每个子发光元件组包括相邻的多行所述第二发光元件，且位于同一侧的所述第一子发光元件组、所述第二子发光元件组和所述第三子发光元件组沿远离所述轴线的方向依次排布，所述轴线沿所述第二方向延伸；
第4个所述像素电路组包括：与所述两个第一子发光元件组一一对应的两个第一子像素电路组，与所述两个第二子发光元件组一一对应的两个第二子像素电路组，与所述两个第三子发光元件组一一对应的两个第三子像素电路组；
其中，每个所述第一子发光元件组中的各个所述第二发光元件，与对应的所述第一子像素电路组中的各个所述第二像素电路通过所述第一导电线连接；每个所述第二子发光元件组中的各个所述第二发光元件，与对应的所述第二子像素电路组中的各个所述第二像素电路通过所述第二导电线连接；每个所述第三子发光元件组中的各个所述第二发光元件，与对应的所述第三子像素电路组中的各个所述第二像素电路通过所述第三导电线连接。
可选的，每个所述第一子发光元件组中的各个所述第二发光元件所连接的所述第一导电线，每个所述第二子发光元件组中的各个所述第二发光元件所连接的所述第二导电线，每个所述第三子发光元件组中的各个所述第二发光元件所连接的所述第三导电线，包括：第四导电线段、第五导电线段和第六导电线段和第七导电线段；
所述第四导电线段的一端与对应的所述第二发光元件连接，所述第四导电线段的另一端与所述第五导电线段的一端连接；
所述第五导电线段的另一端与所述第六导电线段的一端连接；
所述第六导电线段的另一端与所述第七导电线段的一端连接；
所述第七导电线段的另一端与对应的所述第二像素电路连接；
其中，所述第五导电线段与所述第七导电线段沿所述第一方向延伸，所述第六导电线段沿所述第二方向延伸；所述第四导电线段位于所连接的所述第二发光元件所在行与相邻行之间；
所述第一导电线包括的第五导电线段位于第2个所述发光元件组至第4个所述发光元件组所在区域内，所述第二导电线包括的第五导电线段位于第3个所述发光元件组和第4个所述发光元件组所在区域内，所述第三导电线包括的第五导电线段位于第4个所述发光元件组所在区域内；沿所述轴线远离所述第二子显示区一侧的所述第六导电线段位于所述第二显示区远离所述第二子显示区一侧，沿所述轴线靠近所述第二子显示区一侧的所述第六导电线段位于靠近所述第二子显示区的第二显示区内。
可选的，第1个所述发光元件组至第3个所述发光元件组分别包括12列所 述第二发光元件；第4个所述发光元件组包括8列所述第二发光元件；
第1个所述像素电路组至第3个所述像素电路组分别包括12列所述第二像素电路；第4个所述像素电路组包括8列所述第二像素电路。
可选的，所述显示面板还包括：多个金属层；
每个所述第二像素电路所连接的数据线与任一所述金属层同层设置；
其中，所述多个金属层包括：第一栅极金属层、第二栅极金属层、第一源漏极金属层和第二源漏极金属层。
可选的，沿远离相邻的所述第三子显示区的方向，每个所述目标子显示区内的第一列至第i列所述第二像素电路中，位于奇数列的所述第二像素电路所连接的数据线与所述第一栅极金属层同层；位于偶数列的所述第二像素电路所连接的数据线与所述第二栅极金属层同层；第i列至第n列所述第二像素电路所连接的数据线与所述第一源漏金属层同层，i为大于1且小于n的整数，n等于每个所述目标子显示区内的总列数。
可选的，每个所述第二像素电路所连接的数据线包括：第一数据线段、第二数据线段和第三数据线段；
所述第一数据线段的一端与对应的金属层连接，另一端与所述第二数据线段的一端连接，所述第二数据线段的另一端与所述第三数据线段的一端连接，所述第三数据线段的另一端与所述第二像素电路连接；
其中，所述第二数据线段沿所述第一方向延伸，且与所述第一栅极金属层同层的数据线包括的第二数据线段、与所述第二栅极金属层同层的数据线包括的第二数据线段，以及与所述第一源漏金属层同层的数据线包括的第二数据线段互不重叠。
可选的，所述第二源漏金属层覆盖所述第一栅极金属层、所述第二栅极金属层和所述第一源漏金属层。
可选的，同一列所述第二像素电路中，位于所述第一子显示区的所述第二像素电路所连接的数据线，与位于所述第二子显示区的所述第二像素电路所连接的数据线不同。
可选的，所述显示面板还包括至少一列虚设第二像素电路，且所述至少一列虚设第二像素电路位于靠近所述第二显示区的所述目标子显示区中。
可选的，所述多个第一像素电路和所述多个第二像素电路中，任一像素电 路的宽度小于任一所述第一发光元件的宽度。
可选的，每个像素电路的宽度与所述第一发光元件的宽度相差4微米。
可选的，每个所述第二像素电路和每个所述第二发光元件均具有转接部，所述导电线分别连接至所述至少一个第二像素电路的转接部，以及所述至少一个第二发光元件的转接部。
可选的，所述导电线为透明导电线。
可选的，所述透明导电线的材料为氧化铟锡。
可选的，所述第二显示区为透光显示区。
另一方面，提供了一种显示装置，所述显示装置包括：集成电路，以及如上述方面所述的显示面板；
所述集成电路与所述显示面板中的第一像素电路和第二像素电路连接，并用于驱动所述第一像素电路和所述第二像素电路工作；
可选的，所述显示装置还包括：感光传感器，且所述感光传感器位于所述显示面板的第二显示区内。
可选的，所述第二显示区为矩形，所述感光传感器在所述衬底基板上的正投影面积小于等于所述第二显示区的内切圆的面积。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示面板的结构示意图；
图2是本申请实施例提供的另一种显示面板的结构示意图；
图3是本申请实施例提供的又一种显示面板的结构示意图；
图4是本申请实施例提供的再一种显示面板的结构示意图；
图5是本申请实施例提供的再一种显示面板的结构示意图；
图6是本申请实施例提供的再一种显示面板的结构示意图；
图7是本申请实施例提供的一种像素电路压缩前后版图；
图8是本申请实施例提供的一种显示面板的结构示意图；
图9是本申请实施例提供的一种像素电路的结构示意图；
图10是本申请实施例提供的一种像素电路的结构版图；
图11是本申请实施例提供的再一种显示面板的结构示意图；
图12是本申请实施例提供的再一种显示面板的结构示意图；
图13是本申请实施例提供的再一种显示面板的结构示意图；
图14是本申请实施例提供的再一种显示面板的结构示意图；
图15是本申请实施例提供的再一种显示面板的结构示意图；
图16是本申请实施例提供的再一种显示面板的结构示意图；
图17是本申请实施例提供的再一种显示面板的结构示意图；
图18是本申请实施例提供的再一种显示面板的结构示意图；
图19是本申请实施例提供的再一种显示面板的结构示意图；
图20是本申请实施例提供的再一种显示面板的结构示意图；
图21是本申请实施例提供的再一种显示面板的结构示意图；
图22是本申请实施例提供的再一种显示面板的结构示意图；
图23是本申请实施例提供的一种导电线结构示意图；
图24是本申请实施例提供的一种导电线结构示意图；
图25是本申请实施例提供的一种导电线结构示意图；
图26是本申请实施例提供的再一种显示面板的结构示意图；
图27是本申请实施例提供的再一种显示面板的结构示意图；
图28是本申请实施例提供的再一种显示面板的结构示意图；
图29是本申请实施例提供的一种显示面板的截面图；
图30是本申请实施例提供的再一种显示面板的结构示意图；
图31是本申请实施例提供的再一种显示面板的结构示意图；
图32是本申请实施例提供的再一种显示面板的结构示意图；
图33是本申请实施例提供的再一种显示面板的结构示意图；
图34是本申请实施例提供的再一种显示面板的结构示意图；
图35是本申请实施例提供的再一种显示面板的结构示意图；
图36是本申请实施例提供的再一种显示面板的结构示意图；
图37是本申请实施例提供的再一种显示面板的结构示意图；
图38是本申请实施例提供的再一种显示面板的结构示意图；
图39是本申请实施例提供的再一种显示面板的结构示意图；
图40是本申请实施例提供的再一种显示面板的结构示意图；
图41是本申请实施例提供的一种数据线结构示意图；
图42是本申请实施例提供的再一种显示面板的结构示意图；
图43是本申请实施例提供的再一种显示面板的结构示意图；
图44是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
随着显示技术的发展，现有的刘海屏或水滴屏设计均逐渐不能满足用户对显示面板高屏占比的需求，一系列具有透光显示区的显示面板应运而生。该类显示面板中，可以将感光传感器(如，摄像头)等硬件设置于透光显示区，因无需打孔，故在确保显示面板实用性的前提下，使真全面屏成为可能。
本申请实施例提供了一种显示面板，该显示面板在确保对透光显示区内发光元件可靠驱动，且确保透光显示区透光率较好的前提下，不会减少非透光显示区内像素数量，确保了非透光显示区的显示效果较好。
图1是本申请实施例提供的一种显示面板的结构示意图。如图1所示，该显示面板可以包括：
衬底基板01，该衬底基板01可以具有第一显示区A1和第二显示区A2，该第一显示区A1可以至少部分围绕第二显示区A2。例如，图1示出的第二显示区A2位于衬底基板01的顶部正中间位置，相应的，呈矩形的第一显示区A1的四侧可以均围绕第二显示区A2，即第二显示区A2可以被第一显示区A1包围。
在一些实施例中，该第二显示区A2也可以不位于图1所示衬底基板01的顶部正中间位置处，而是位于其他位置。例如，结合图1，第二显示区A2可以位于衬底基板01的左上角位置或右上角位置处。
再结合图2所示的另一显示面板可以看出，该显示面板还可以包括：位于第一显示区A1的多个第一像素电路10、多个第二像素电路20和多个第一发光元件30，以及位于第二显示区A2的多个第二发光元件40，且多个第二像素电 路20可以间隔分布于多个第一像素电路10之间。
其中，多个第一像素电路10中的至少一个第一像素电路10可以与多个第一发光元件30中的至少一个第一发光元件30连接，且至少一个第一像素电路10在衬底基板01上的正投影与至少一个第一发光元件30在衬底基板01上的正投影可以至少部分重叠。该至少一个第一像素电路10可以用于为所连接的第一发光元件30提供驱动信号，以驱动该第一发光元件30发光。
多个第二像素电路20中的至少一个第二像素电路20可以与多个第二发光元件40中的至少一个第二发光元件40通过导电线L1连接，该至少一个第二像素电路20可以用于为所连接的第二发光元件40提供驱动信号，以驱动该第二发光元件40发光。且因第二发光元件40与第二像素电路20位于不同区域，故，如图2所示，至少一个第二像素电路20在衬底基板01上的正投影与至少一个第二发光元件40在衬底基板01上的正投影不存在重叠部分。
可选的，在本申请实施例中，可以设置该第一显示区A1为非透光显示区，以及设置该第二显示区A2为透光显示区。即，本申请实施例记载的第一显示区A1不可透光，第二显示区A2可透光。如此，无需在显示面板上进行挖孔处理，可以将感光传感器等所需硬件结构直接设置于第二显示区A2内，为真全面屏的实现奠定坚实的基础。并且，由于第二显示区A2内仅包括发光元件，而不包括像素电路，因此还可以确保第二显示区A2的透光率较好。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括具有第一显示区和第二显示区的衬底基板。由于驱动第二显示区内发光元件的像素电路仅位于第一显示区而不位于第二显示区，因此确保了第二显示区的透光率较好。相应的，本申请实施例记载的显示面板显示效果较好。
图3以图2所示显示面板为例，示出了另一种显示面板的结构示意图。参考图3可以进一步看出，第一显示区A1内不仅包括多个像素，且还包括多列第二像素电路20，第二显示区A2内仅包括多个第二发光元件40。
其中，像素是指包括像素电路以及发光元件的结构，以第一像素电路10和第一发光元件30为例，参考图3可以看出，其示出的每个像素均包括：红色子像素R，两个绿色子像素G1和G2，以及一个蓝色子像素B，且红色子像素R和蓝色子像素B位于同一列，两个绿色子像素G1和G2位于同一列。当然，在 一些实施例中，像素也可以包括其他颜色以及其他数量的子像素，且各个子像素的排列方式不限于图3所示结构。如，每个像素可以仅包括一个红色子像素R、一个蓝色子像素B，以及一个绿色子像素G。
可选的，在本申请实施例中，多个第一像素电路10与多个第一发光元件30之间的电连接关系可以一一对应。即，每个第一像素电路10可以均与一个第一发光元件30连接，且各个第一像素电路10所连接的第一发光元件30不同。由此，结合图2所示显示面板，每个第一像素电路10在衬底基板01上的正投影与所连接的第一发光元件30在衬底基板01上的正投影均至少部分重叠。
与第一像素电路10与第一发光元件30之间的电连接关系同理，多个第二像素电路20与多个第二发光元件40之间的电连接关系也可以一一对应。且，每个二像素电路20在衬底基板01上的正投影与所连接的第二发光元件40在衬底基板01上的正投影均不重叠。
可选的，位于第二显示区A2的多个第二发光元件40，与位于第一显示区A1的多个第一发光元件30的密度可以相同。即，第一显示区A1和第二显示区A2内每英寸所包括的发光元件数量相同。即第一显示区A1(即主显示区)不存在像素密度不同的两个分区，进而，相对于相关技术，在显示画面时，第一显示区A1不会存在明暗分界线，显示面板的显示效果较好。
以图2所示显示面板为例，图4示出了一种显示面板的结构版图。参考图4可以看出，第一显示区A1的分辨率可以大于第二显示区A2的分辨率。即，该第一显示区A1的面积相对于第二显示区A2的面积较大，且第一显示区A1所包括的发光元件相对于第二显示区A2所包括的发光元件的数量较多。
在一些实施例中，第一显示区A1的分辨率可以小于等于第二显示区A2的分辨率。例如，第一显示区A1的面积与第二显示区A2的面积可以相同，且第一显示区A1所包括的发光元件与第二显示区A2所包括的发光元件的数量也相同。或者，第一显示区A1的面积可以小于第二显示区A2的面积，且第一显示区A1所包括的发光元件相对于第二显示区A2所包括的发光元件的数量较少。
可选的，图5示出了图4所示显示面板的局部放大示意图。结合图4和图5可以看出，第一发光元件30的尺寸可以大于第二发光元件40的尺寸，即第二显示区A2内发光元件的阳极相比于第一显示区A1内发光元件的阳极较小。如此，可以确保第二显示区A2的透光率较第一显示区A1的透光率更大。再者， 还可以通过进一步优化第二发光元件40的阳极的形状和大小，以确保透光率更好。如，结合图3所示显示面板，其示出的第二发光元件40的阳极为椭圆状。
可选的，为了进一步确保第二显示区A2的透光率较好，本申请实施例记载的导电线L1可以为透明导电线。例如，该导电线L1可以由氧化铟锡(indium tin oxide，ITO)或铟镓锌氧化物(indium gallium zinc oxide，IGZO)等透明材料制成。假设该导电线L1由ITO材料制成，则该导电线L1也可以称为ITO走线。以下实施例均以导电线L1为ITO走线为例进行说明。
可选的，在本申请实施例中，因衬底基板01具有可透光的显示区，即第二显示区A2，则如图6所示，显示装置包括的显示模组中的感光传感器50结构(如，摄像头)，可以直接设置于该第二显示区A2内，即无需在显示面板上额外挖孔。如此，为全面屏显示面板的实现奠定了坚实的基础。
可选的，该第二显示区A2可以为矩形，感光传感器50在衬底基板01上的正投影的面积可以小于或等于第二显示区A2的内切圆的面积。即，感光传感器50所处区域的尺寸可以小于或等于该第二显示区A2的内切圆的尺寸。例如，结合图6，其示出的显示面板中，感光传感器50所处区域的尺寸等于第二显示区A2的内切圆Y0的尺寸，即该感光传感器50所在区域的形状可以为圆形，相应的，该感光传感器50所在区域也可以称为透光孔。当然，在一些实施例中，第二显示区A2也可以为除矩形之外的其他形状，如圆形或椭圆形。
相关技术中，像素电路(包括第一像素电路10和第二像素电路20)和第一发光元件30的尺寸(pitch)相同。如，一般宽度约为30微米(μm)至32μm，长度约为60μm至65μm。而在本申请实施例中，为了能够在不减少第一显示区A1内的像素数量的前提下，为第二像素电路20的设置提供充足的空间，可以通过沿第二方向X2(如，栅线延伸方向，也可以称为横向)对各像素电路进行压缩，使得像素电路在第二方向上的宽度相对于第一发光元件30的宽度较小；或者，可以通过沿第二方向对第一发光元件30进行延展，使得第一发光元件30在第二方向上的宽度相对于第一发光元件30的宽度较大。如此，在衬底基板01尺寸相同的前提下，第一显示区A1内能够多出较多区域，相应的，可以在该较多区域处设置专门用于驱动位于第二显示区A2内的第二发光元件40的第二像素电路20。
例如，每个像素电路的宽度与第一发光元件30的宽度可以相差约4μm。 以压缩像素电路，且宽度相差4μm为例，图7示出了压缩前后(即，相关技术和本申请实施例)的像素电路的结构版图。参考图7可以看出，像素电路可以包括驱动结构以及用于连接至发光元件的阳极的转接部B1，该转接部B1的尺寸可以代表像素电路的尺寸。压缩前像素电路和发光元件的尺寸均为宽1-100μm，高2-200μm，压缩后发光元件的尺寸不变，像素电路的高度不变，但宽度缩窄1-20μm，这样每隔几列压缩像素电路就会多出一列或者多列压缩像素电路，整个屏幕都采用这种设计，以实现全屏压缩。其中，这些多出列可被挑选用来连接第二显示区A2内的第二发光元件40，以控制第二发光元件40发光。在一些实施例中，优选靠近第二显示区A2周边的多出列像素电路作为第二像素电路20连接第二发光元件40。如此，可以使得在不改变显示面板的分辨率的同时，确保正常显示。即，充分利用了显示面板现有空间来实现正常显示。
需要说明的是，结合图3，像素电路的宽度可以是指沿第二方向X2像素电路的版图在衬底基板01上的正投影的长度。第一发光元件30的宽度是指沿第二方向X2，第一发光元件30的阳极(anode)在衬底基板01上的正投影的长度。
此外，结合图3和图8所示附图，本申请实施例记载的每个第一发光元件均属于一个像素中的一个子像素。如，可能为红色子像素R、绿色子像素G1、G2或蓝色子像素B。在确定第一发光元件的阳极的尺寸时，一般可以以一个像素为周期测量该像素在第一方向X1或第二方向X2上的宽度D10，然后对于每个第一发光元件的宽度D01而言，可以采用像素总宽度D10除以像素包括的子像素数量(如，图8所示4)即可。同理，因每个第一发光元件均对应连接一个像素电路，故依然可以以一个像素所连接的各个像素电路为周期测量各个像素电路在第一方向X1或第二方向X2上的宽度，然后对于每个像素电路的宽度D0而言，可以采用总宽度除以像素包括的子像素数量即可。
可选的，结合图7所示像素电路，本申请实施例记载的像素电路可以为7T1C结构，即包括7个晶体管和1个电容器。图9示出了7T1C像素电路的结构示意图，图10示出了7T1C像素电路的结构版图。
其中，结合图9和图10所示像素电路可知，该7T1C像素电路10包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容C1。该像素电路可以与栅极信号端Gate，数据信号端Data，复位信号端RST1 和RST2，发光控制信号端EM，电源端VDD，初始电源端Vinit1和Vinit2，以及发光元件连接，该发光元件还可以与电源端VSS连接。该像素电路可以用于响应于所连接的各信号端提供的信号，驱动所连接的发光元件发光。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本申请实施例以晶体管均采用P型晶体管为例进行说明。基于本申请对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本申请实施例的像素电路结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本申请实施例的保护范围内的。
为了进一步体现出压缩像素电路后，多出多列像素电路，图11示出了一种第一显示区A1的结构示意图。图12示出了图4中的部分结构(仅包括像素电路)示意图，图13示出了图4中的部分结构(仅包括发光元件)示意图。
参考图11至图13可以看出，像素电路的宽度较发光元件的宽度小，如此，可以使得从左往右第2列和第9列的像素电路不连接任何第一发光元件30，属于多出列像素电路，其可以作为第二像素电路20用于连接第二显示区A2内的第二发光元件40。此外，每个第一发光元件30可以包括RG1BG2共4种anode，以及用于和第一像素电路10连接的转接部B2。第一像素电路10的转接部B1与第一发光元件30的转接部B2可以通过源漏金属层SD2连接。或者，若第一像素电路10与第一发光元件30已搭接在一起，则无需再设置SD2线连接。
需要说明的是，至少一个第二像素电路20和至少一个第二发光元件40也可以均具有转接部，至少一个第二像素电路20和至少一个第二发光元件40通过导电线L1连接其实可以是：导电线L1分别连接至至少一个第二像素电路20的转接部，以及至少一个第二发光元件40的转接部。
由此，为了保证具有充足的空间用来走导电线L1，位于同一行的每个第二像素电路20的转接部的轴线，与任一第二发光元件40的转接部的轴线可以平齐，轴线可以沿第二方向X2延伸。也即是，在行方向的同一行中，第二像素电路20的转接部与第二发光元件40的转接部位于同一条直接上。同理，结合上述图11至图13，同一行中，第一像素电路10的转接部B1与第一发光元件30的转接部B2也可以位于同一条直接上，以使得走线排布整齐。
可选的，图14是本申请实施例提供的再一种显示面板的结构示意图。如图 14所示，第一显示区A1可以包括：沿第一方向X1依次排布的第一子显示区A11和第二子显示区A12。第一子显示区A11可以包括：对称的两个目标子显示区A110。即，两个目标子显示区A110的布局相同。第二显示区A2可以包括沿第二方向X2对称排布的两个第三子显示区A21。即，两个第三子显示区A21的布局相同。其中，一个目标子显示区A110、第二显示区A2和另一个目标子显示区A110可以沿第二方向X2依次排布。
基于图14所示显示面板，由于显示面板的左半部分和右半部分布局相同。因此下述实施例均仅示出显示面板的左半边结构，即位于左半部分的一个目标子显示区A110以及相邻的一个第三子显示区A21。右半部分同理，不再赘述。
再者，本申请实施例记载的多出列像素电路，即多个第二像素电路20可以分散设置于第一显示区A1内，且设置位置可以根据需求灵活调整，只要保证能够与第二发光元件40有效连接，并驱动第二发光元件40可靠发光即可。例如，本申请实施例以多个第二像素电路20分散设置于列方向、行方向和对角线方向为例，对第二像素电路20的设置位置进行如下示意性说明：
作为一种可选的实施方式，以第二像素电路20沿列方向延伸，图15是本申请实施例提供的再一种显示面板的结构示意图。结合图14和图15可以看出，多个第一像素电路10可以包括沿第一方向X1延伸的多列第一像素电路10，多个第二像素电路20可以包括沿第一方向X1延伸的多列第二像素电路20。
其中，多列第二像素电路20可以间隔分布在多列第一像素电路10之间。如，每间隔相邻的多列第一像素电路10，存在一列第二像素电路20。换言之，每相邻两列第二像素电路20之间可以间隔多列相邻的第一像素电路10。
且可选的，任意相邻两列第二像素电路20之间可以间隔相同列数的第一像素电路10，如此确保了排布均一性。如，任意相邻两列第二像素电路20之间均间隔相邻的8列第一像素电路10。或者，任意相邻两列第二像素电路20之间可以间隔不同列数的第一像素电路10。
示例的，结合图16所示显示面板，自第三子显示区A21和目标子显示区A110的左交界线为起始位置，向左第2列像素电路、第12列像素电路和第20列像素电路可以均为第二像素电路20。需要说明的是，第二显示区A2下方的多出列第二像素电路20可以作为虚设(dummy)列，不与任何发光元件连接。
作为另一种可选的实现方式，以第二像素电路20未沿列方向延伸，图17 是本申请实施例提供的再一种显示面板的结构示意图。如图17所示，多个第一像素电路10可以包括沿第二方向X2延伸的多行第一像素电路10，多个第二像素电路20可以包括沿第二方向X2延伸的多行第二像素电路20。
可选的，第一方向X1与第二方向X2可以相交。如，在该第一方向X1与第二方向X2不垂直时，多个第二像素电路20可以沿对角线方向排列。在该第一方向X1与第二方向X2垂直时，多个第二像素电路20即可以沿行方向排列。
其中，多行第二像素电路20间隔分布在多行第一像素电路10之间。例如，图17示出的多个第二像素电路20沿行方向延伸，即每间隔相邻的多行第一像素电路10，存在一行第二像素电路20。换言之，每相邻两行第二像素电路20之间可以间隔多行相邻的第一像素电路10。以下实施例均以多个第二像素电路20按列方向依次排布为例进行说明。
需要说明的是，多出列像素电路，即第二像素电路20与第二发光元件40之间可以通过导电线L1连接，且导电线L1的堆叠层数可以根据透光孔的半径灵活调整。例如，图18是本申请实施例提供的再一种显示面板的结构示意图。如图18所示，该显示面板可以包括：第一导电线L11(即，ITO1)、第二导电线L12(即，ITO2)和第三导电线L13(即，ITO3)。
每个第三子显示区A21可以包括k个发光元件组。每个发光元件组可以包括相邻的多列第二发光元件40，且第1个发光元件组至第k个发光元件组可以沿靠近另一第三子显示区的方向依次排布。相应的，每个目标子显示区A110包括与k个发光元件组Z0一一对应的k个像素电路组。每个像素电路组可以包括相邻的多列第二像素电路20，且第1个像素电路组至第k个像素电路组可以沿远离相邻的第三子显示区的方向依次排布。
其中，k可以为大于0的整数。如，本申请实施例以k为4为例进行说明。可选的，第1个发光元件组Z01至第3个发光元件组Z03可以分别包括12列第二发光元件40。第4个发光元件组Z04可以包括8列第二发光元件40。相应的，第1个像素电路组Z11至第3个像素电路组Z13即可以分别包括12列第二像素电路20。第4个像素电路组Z14即可以包括8列第二像素电路20。
即，如图18所示显示面板，第三子显示区A21中，第1列第二发光元件40至第13列第二发光元件40(即，R1至R13)属于第1个发光元件组Z01；第14列第二发光元件40至第26列第二发光元件40(即，R14至R26)属于第 2个发光元件组Z02；第27列第二发光元件40至第39列第二发光元件40(即，R27至R39)属于第3个发光元件组Z03；第40列第二发光元件40至第48列第二发光元件40(即，R40至R48)属于第4个发光元件组Z04。
相应的，目标子显示区A110中，第1列第二像素电路20至第13列第二像素电路20(即，P1至P13)属于第1个像素电路组Z11；第14列第二像素电路20至第26列第二像素电路20(即，P14至P26)属于第2个像素电路组Z12；第27列第二像素电路20至第39列第二像素电路20(即，P27至P39)属于第3个像素电路组Z13；第40列第二像素电路20至第48列第二像素电路20(即，P40至P48)属于第4个像素电路组Z14。图18仅未示出第一像素电路10和第一发光元件30。
可选的，在本申请实施例中，每个发光元件组中的各个第二发光元件40，与对应的一个像素电路组中的各个第二像素电路20可以通过第一导电线L11、第二导电线L12和/或第三导电线L13连接。
例如，如图19所示，第1个发光元件组Z01中的各个第二发光元件40，与第1个像素电路组Z11中的各个第二像素电路20可以通过第一导电线L11(图19以ITO1代表第一导电线L11)连接。
如图20所示，第2个发光元件组Z02中的各个第二发光元件40，与第2个像素电路组Z12中的各个第二像素电路202可以通过第二导电线L12(图20以ITO2代表第二导电线L12)连接。
如图21所示，第3个发光元件组Z03中的各个第二发光元件40，与第3个像素电路组Z13中的各个第二像素电路20可以通过第三导电线L13(图21以ITO3代表第三导电线L13)连接。
如图22所示，第4个发光元件组Z04中的各个第二发光元件40，与第4个像素电路组Z14中的各个第二像素电路20可以通过第一导电线L11(即，ITO1)、第二导电线L12(即，ITO2)和第三导电线L13连接(即，ITO3)。
例如，参考图22，第4个发光元件组Z04可以包括：沿第三子显示区A21的轴线xx对称排布的两个第一子发光元件组Z041，两个第二子发光元件组Z042以及两个第三子发光元件组Z043。其中，每个子发光元件组可以包括相邻的多行第二发光元件40，且每个子发光元件组包括的第二发光元件40的行数可以相同或不同。此外，位于同一侧的第一子发光元件组Z041、第二子发光元件组Z042 和第三子发光元件组Z043可以沿远离轴线xx的方向依次排布，轴线xx沿第二方向X2延伸。第4个像素电路组Z14可以包括与两个第一子发光元件组Z041一一对应的两个第一子像素电路组Z141，与两个第二子发光元件组Z042一一对应的两个第二子像素电路组Z142，以及与两个第三子发光元件组Z043一一对应的两个第三子像素电路组Z143。且位于同一侧的第一子像素电路组Z141、第二子像素电路组Z142和第三子像素电路组Z143的排布与子发光元件组相同。
其中，每个第一子发光元件组Z041中的各个第二发光元件40，与对应的第一子像素电路组Z141中的各个第二像素电路20可以通过第一导电线L11(即，ITO1)连接。每个第二子发光元件组Z042中的各个第二发光元件40，与对应的第二子像素电路组Z142中的各个第二像素电路20可以通过第二导电线L12(即，ITO2)连接。每个第三子发光元件组Z043中的各个第二发光元件40，与对应的第三子像素电路组Z143中的各个第二像素电路20可以通过第三导电线L13(即，ITO3)连接。
图23是本申请实施例提供的一种导电线结构示意图。图24是图19至图21所示结构的版图。再结合图19至图21可以看出，第1个发光元件组Z01中的各个第二发光元件40所连接的第一导电线L11，第2个发光元件组Z02中的各个第二发光元件40所连接的第二导电线L12，以及第3个发光元件组Z03中的各个第二发光元件40所连接的每条第三导电线L13，均可以包括：第一导电线段La、第二导电线段Lb和第三导电线段Lc。
其中，第一导电线段La的一端可以与对应的第二发光元件40连接，第一导电线段La的另一端与第二导电线段Lb的一端连接。第二导电线段Lb的另一端可以与第三导电线段Lc的一端连接。第三导电线段Lc的另一端可以与对应的第二像素电路20连接。并且，第一导电线段La和第三导电线段Lc可以沿第一方向X1延伸，第二导电线段Lb可以沿第二方向X2延伸，且第二导电线段Lb在衬底基板01上的正投影至少部分与第二发光元件40在衬底基板01上的正投影重叠(可参考下述图24看出)。即，第一导电线L11、第二导电线L12和第三导电线L13可以均由所连接第二发光元件40引出，并自行方向横向延伸至第二像素电路20位置处，以与第二像素电路20连接。
可选的，为了避免信号互相干扰，第一导电线L11包括的第二导电线段Lb与第三导电线L13包括的第二导电线段Lb可以至少部分重叠。第一导电线L11 包括的第二导电线段Lb与第二导电线L12包括的第二导电线段Lb可以不重叠，且第三导电线L13包括的第二导电线段Lb与第二导电线L12包括的第二导电线段Lb也可以不重叠。重叠的部分可以通过过孔转接。
需要说明的是，图24仅是示意性示出第1个发光元件组Z01中，各个第二发光元件40所连接的第一导电线L11，即ITO1走线在显示面板中的结构版图。对于第2个发光元件组Z02中，各个第二发光元件40所连接的第二导电线L12(即，ITO2走线)，以及第3个发光元件组Z03中，各个第二发光元件40所连接的第三导电线L13(即，ITO3走线)在显示面板中的结构版图，可以直接参考图24所示显示面板示意图，在此不再赘述。
可选的，图25是本申请实施例提供的一种导电线的结构示意图。如图25所示，每个第一子发光元件组Z041中的各个第二发光元件40所连接的第一导电线L11，每个第二子发光元件组Z042中的各个第二发光元件40所连接的第二导电线L12，每个第三子发光元件组Z043中的各个第二发光元件40所连接的第三导电线L13，均可以包括：第四导电线段Ld、第五导电线段Le和第六导电线段Lf和第七导电线段Lg。
其中，第四导电线段Ld的一端可以与对应的第二发光元件40连接，第四导电线段Ld的另一端与第五导电线段Le的一端连接。第五导电线段Le的另一端可以与第六导电线段Lf的一端连接。第六导电线段Lf的另一端可以与第七导电线段Lg的一端连接。第七导电线段Lg的另一端可以与对应的第二像素电路20连接。并且，第五导电线段Le与第七导电线段Lg可以沿第一方向X1延伸，第六导电线段Lf可以沿第二方向X2延伸。第四导电线段Ld可以位于所连接的第二发光元件40所在行与相邻行之间。
图26是本申请实施例提供的再一种显示面板结构示意图，图27是本申请实施例提供的再一种显示面板结构示意图。图28是图27所示显示面板的简易示意图。结合图26至图28可以看出，第一导电线L11(即图示ITO1)包括的第五导电线段Le可以位于第2个发光元件组Z02至第4个发光元件组Z04所在区域内。第二导电线L12(即图示ITO2)包括的第五导电线段Le可以位于第3个发光元件组Z03和第4个发光元件组Z04所在区域内。第三导电线L13(即图示ITO3)包括的第五导电线段Le可以位于第4个发光元件组Z04所在区域内。沿轴线远离第二子显示区A12一侧的第六导电线段Lf可以位于第二显示区 A2远离第二子显示区A12一侧，沿轴线靠近第二子显示区A12一侧的第六导电线段Lf可以位于靠近第二子显示区A12的第二显示区A2内。
也即是，第一导电线L11包括的第五导电线段Le可以自所连接的第二发光元件40引出，并自R14至R48列第二发光元件40所在区域(即，Z02至Z04所在区域)沿列方向延伸至第三子显示区A21靠近非显示区或靠近第二子显示区A12的一侧，然后再沿行方向横向延伸至对应的第二像素电路20所在区域，以与第二像素电路20连接。第二导电线L12包括的第五导电线段Le可以自所连接的第二发光元件40引出，并自R27至R48列第二发光元件40所在区域(即，Z03和Z04所在区域)沿列方向延伸至第三子显示区A21靠近非显示区或靠近第二子显示区A12的一侧，然后再沿行方向横向延伸至对应的第二像素电路20所在区域，以与第二像素电路20连接。第三导电线L13包括的第五导电线段Le可以自所连接的第二发光元件40引出，并自R40至R48列第二发光元件40所在区域(即，Z04所在区域)沿列方向延伸至第三子显示区A21靠近非显示区或靠近第二子显示区A12的一侧，然后再沿行方向横向延伸至对应的第二像素电路20所在区域，以与第二像素电路20连接。此外，位于同一侧且沿行方向延伸的各个导电线包括的第六导电线段Lf可以部分重叠，或者，不重叠。
参考图26和图27可以看出，显示面板还可以包括至少一列虚设第二像素电路20，且该至少一列虚设第二像素电路20可以位于目标子显示区A110内。该列虚设第二像素电路20也可以称为过渡列，该列虚设第二像素电路20不与任何发光元件连接。
通过设置过渡列，可以避免第一列第二发光元件40与其所连接第二像素电路20间距，相对于最后一列第二发光元件40与其所连接第二像素电路20间距较小，而导致第一列第二发光元件40和最后一列第二发光元件40的启亮时差较大的问题，进一步保证了显示效果较好。
此外，对比图26和图27可以看出，第1个发光元件组01中，位于相邻行的各个第二发光元件40所连接的第一导电线L11(即，图示ITO1)可以位于朝上的同一侧，或者，可以位于不同侧对称排布。第2个发光元件组01中，位于相邻行的各个第二发光元件40所连接的第二导电线L12(即，图示ITO2)可以位于朝上的同一侧，或者，可以位于不同侧对称排布。第3个发光元件组01中，位于相邻行的各个第二发光元件40所连接的第三导电线L13(即，图示ITO1) 可以位于朝上的同一侧，或者，可以位于不同侧对称排布。当然，以上信号线也可以均位于朝下的同一侧，不再附图赘述。
图29示出了显示面板的一种截面图。其中，ITO1代表第一导电线L11，ITO2代表第二导电线L12，ITO3代表第三导电线L13。Anode是指发光元件的阳极，PLN是指平坦层，图29示出的显示面板共包括5层平坦层PLN1至PLN5，SD1是指第一源漏极金属层，SD2是指第二源漏极金属层。
可选的，显示面板还可以包括：第一栅极金属层GATE1、第二栅极金属层GATE2、第一源漏极金属层SD1和第二源漏极金属层SD2等多个金属层。每个第二像素电路20所连接的数据线DATA可以与任一金属层同层设置。
例如，参考图30所示显示面板，沿远离相邻的第三子显示区A21的方向，每个目标子显示区A110内的第一列至第i列第二像素电路20中，位于奇数列的第二像素电路20所连接的数据线DATA可以与第一栅极金属层GATE1同层。位于偶数列的第二像素电路20所连接的数据线DATA可以与第二栅极金属层GATE2同层。第i列至第n列第二像素电路20所连接的数据线DATA可以与第一源漏金属层SD1同层。其中，i可以为大于1且小于n的整数，n可以等于每个目标子显示区A110内的总列数。即前i列第二像素电路20所连接数据线DATA可以交替与GATE1和GATE2同层设置。第i列至第n列第二像素电路20所连接数据线DATA可以均与SD1同层设置。
可选的，假设第三子显示区A21内包括48列第二发光元件40，则i可以为24，即每24列第二发光元件40可以为一组。相应的，即，第1列至第24列中，奇数列所连接的数据线DATA可以与第一栅极金属层GATE1同层，第1列至第24列中，偶数列所连接的数据线DATA可以与第二栅极金属层GATE2同层，第24列至第48列所连接的数据线DATA均与第一源漏极金属层SD1同层。
可选的，图31和图32示出了在不同位置处，奇数列第二像素电路20所连接数据线DATA与第一栅极金属层GATE1同层的结构版图。图33和图34示出了在不同位置处，偶数列第二像素电路20所连接数据线DATA与第二栅极金属层GATE2同层的结构版图。图35和图36示出了在不同位置处，第i列至第n列第二像素电路20所连接数据线DATA与SD1同层的结构版图。图37和图38示出了不同位置处，与第一栅极金属层GATE1同层、与第二栅极金属层GATE2同层以及与SD1同层的显示面板整体版图。图39和图40示出了包括导电线L1 和数据线DATA的结构版图。
图41示出了数据线的结构示意图。结合上述数据线相关附图可以看出：每个第二像素电路20所连接的数据线DATA均可以包括：第一数据线段D11、第二数据线段D12和第三数据线段D13。
其中，第一数据线段D11的一端可以与对应的金属层连接，另一端可以与第二数据线段D12的一端连接，第二数据线段D12的另一端可以与第三数据线段D13的一端连接，第三数据线段D13的另一端可以与第二像素电路20连接。
并且，第二数据线段D12可以沿第一方向X1延伸，且与第一栅极金属层GATE1同层的数据线DATA包括的第二数据线段D12、与第二栅极金属层GATE2同层的数据线DATA包括的第二数据线段D12，以及与第一源漏金属层SD1同层的数据线DATA包括的第二数据线段D12可以互不重叠。即，每条数据线DATA可以自第三子显示区A21与第二子显示区A12的交界线处，由金属层转接引出，并在第三子显示区A21内自列方向延伸出显示区至非显示区，然后再沿行方向延伸至对应列第二像素电路20，并与第二像素电路20连接。
此外，再结合图42所示显示面板，同一列第二像素电路20中，位于第一子显示区A11的第二像素电路20所连接的数据线DATA，与位于第二子显示区A12的第二像素电路20所连接的数据线DATA可以不同。如，与一列第二像素电路20连接的数据线DATA自第一子显示区A11和第二子显示区A12的交界线处断开。如此，可以避免数据线所提供信号产生相互干扰的问题，确保针对第二发光元件40有效且可靠的驱动。
再者，参考图43所示显示面板，第二源漏金属层SD2可以覆盖第一栅极金属层GATE1、第二栅极金属层GATE2和第一源漏金属层SD1。如此，可以实现对驱动晶体管与发光元件所连接点的信号屏蔽，由此降低了信号串扰。
可以对导电线L1上寄生电容的影响起到一定屏蔽效果，确保显示效果较好。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括具有第一显示区和第二显示区的衬底基板。由于驱动第二显示区内发光元件的像素电路仅位于第一显示区而不位于第二显示区，因此确保了第二显示区的透光率较好。相应的，本申请实施例记载的显示面板显示效果较好。
图44是本申请实施例提供的一种显示装置的结构示意图。如图44所示， 该显示装置可以包括：集成电路100，以及如上述附图任一所示显示面板200。
其中，该集成电路100可以与显示面板200中的第一像素电路和第二像素电路连接，并用于驱动第一像素电路和第二像素电路工作。如，该驱动电路100可以与像素电路所连接的各信号端连接，并用于为各信号端提供信号。
需要说明的是，图44仅是示意性示出集成电路100的位置，集成电路100也可以位于显示面板200的右侧，也可以既位于显示面板200的左侧又位于显示面板200的右侧。或者，还可以位于显示面板200的上侧和/或下侧。
可选的，该显示装置可以为：有机发光二极管(organic light-emitting diode，OLED)显示装置、有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置、手机、平板电脑、柔性显示装置、电视机和显示器等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的显示基板和显示装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (32)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底基板，具有第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区；
    多个第一像素电路、多个第二像素电路和多个第一发光元件，位于所述第一显示区，且所述多个第二像素电路间隔分布于所述多个第一像素电路之间；
    多个第二发光元件，位于所述第二显示区；
    其中，所述多个第一像素电路中的至少一个第一像素电路与所述多个第一发光元件中的至少一个第一发光元件连接，且所述至少一个第一像素电路在所述衬底基板上的正投影与所述至少一个第一发光元件在所述衬底基板上的正投影至少部分重叠；所述多个第二像素电路中的至少一个第二像素电路与所述多个第二发光元件中的至少一个第二发光元件通过导电线连接。
  2. 根据权利要求1所述的显示面板，其中，所述多个第二发光元件和所述多个第一发光元件的密度相同。
  3. 根据权利要求1所述的显示面板，其中，所述第一显示区的分辨率与所述第二显示区的分辨率相同；或，所述第一显示区的分辨率与所述第二显示区的分辨率不同。
  4. 根据权利要求1至3任一所述的显示面板，其中，每个所述第一像素电路与一个所述第一发光元件连接；
    并且，每个所述第一像素电路在所述衬底基板上的正投影与所连接的所述第一发光元件在所述衬底基板上的正投影至少部分重叠。
  5. 根据权利要求1至3任一所述的显示面板，其中，所述多个第一像素电路包括沿第一方向延伸的多列第一像素电路，所述多个第二像素电路包括沿第一方向延伸的多列第二像素电路；
    其中，所述多列第二像素电路间隔分布在所述多列第一像素电路之间。
  6. 根据权利要求5所述的显示面板，其中，任意相邻两列所述第二像素电路之间间隔相同列数或不同列数的所述第一像素电路。
  7. 根据权利要求1至6任一所述的显示面板，其中，所述多个第一像素电路包括沿第二方向延伸的多行第一像素电路，所述多个第二像素电路包括沿第二方向延伸的多行第二像素电路，所述第二方向与第一方向相交。
    其中，所述多行第二像素电路间隔分布在所述多行第一像素电路之间。
  8. 根据权利要求7所述的显示面板，其中，所述第一方向与所述第二方向垂直。
  9. 根据权利要求1至8任一所述的显示面板，其中，所述第一显示区包括：沿第一方向依次排布的第一子显示区和第二子显示区；所述第一子显示区包括：对称的两个目标子显示区；
    其中，一个所述目标子显示区、所述第二显示区和另一个所述目标子显示区沿第二方向依次排布。
  10. 根据权利要求9所述的显示面板，其中，所述第二显示区包括沿所述第二方向对称排布的两个第三子显示区；所述显示面板包括：第一导电线、第二导电线和第三导电线；
    每个所述第三子显示区包括k个发光元件组，每个所述发光元件组包括相邻的多列所述第二发光元件，且第1个所述发光元件组至第k个所述发光元件组沿靠近另一所述第三子显示区的方向依次排布，k为大于0的整数；
    每个所述目标子显示区包括与所述k个发光元件组一一对应的k个像素电路组，每个所述像素电路组包括相邻的多列所述第二像素电路，且第1个所述像素电路组至第k个所述像素电路组沿远离相邻的所述第三子显示区的方向依次排布；且，每个所述发光元件组中的各个所述第二发光元件，与对应的一个所述像素电路组中的各个所述第二像素电路通过所述第一导电线、所述第二导电线和/或所述第三导电线连接。
  11. 根据权利要求10所述的显示面板，其中，k为4。
  12. 根据权利要求11所述的显示面板，其中，第1个所述发光元件组中的各个所述第二发光元件，与第1个所述像素电路组中的各个所述第二像素电路通过所述第一导电线连接；
    第2个所述发光元件组中的各个所述第二发光元件，与第2个所述像素电路组中的各个所述第二像素电路通过所述第二导电线连接；
    第3个所述发光元件组中的各个所述第二发光元件，与第3个所述像素电路组中的各个所述第二像素电路通过所述第三导电线连接；
    第4个所述发光元件组中的各个所述第二发光元件，与第4个所述像素电路组中的各个所述第二像素电路通过所述第一导电线、所述第二导电线和所述第三导电线连接。
  13. 根据权利要求12所述的显示面板，其中，第1个所述发光元件组中的各个所述第二发光元件所连接的所述第一导电线，第2个所述发光元件组中的各个所述第二发光元件所连接的所述第二导电线，以及第3个所述发光元件组中的各个所述第二发光元件所连接的每条所述第三导电线，包括：第一导电线段、第二导电线段和第三导电线段；
    所述第一导电线段的一端与对应的所述第二发光元件连接，所述第一导电线段的另一端与所述第二导电线段的一端连接；
    所述第二导电线段的另一端与所述第三导电线段的一端连接；
    所述第三导电线段的另一端与对应的所述第二像素电路连接；
    其中，所述第一导电线段和所述第三导电线段沿所述第一方向延伸，所述第二导电线段沿所述第二方向延伸，且所述第二导电线段在所述衬底基板上的正投影至少部分与其所连接第二发光元件在所述衬底基板上的正投影重叠。
  14. 根据权利要求13所述的显示面板，其中，所述第一导电线包括的所述第二导电线段与所述第三导电线包括的所述第二导电线段至少部分重叠，所述第一导电线包括的所述第二导电线段与所述第二导电线包括的所述第二导电线 段不重叠，且所述第三导电线包括的所述第二导电线段与所述第二导电线包括的所述第二导电线段不重叠。
  15. 根据权利要求12所述的显示面板，其中，第4个所述发光元件组包括：沿所述第三子显示区的轴线对称排布的两个第一子发光元件组，两个第二子发光元件组以及两个第三子发光元件组，每个子发光元件组包括相邻的多行所述第二发光元件，且位于同一侧的所述第一子发光元件组、所述第二子发光元件组和所述第三子发光元件组沿远离所述轴线的方向依次排布，所述轴线沿所述第二方向延伸；
    第4个所述像素电路组包括：与所述两个第一子发光元件组一一对应的两个第一子像素电路组，与所述两个第二子发光元件组一一对应的两个第二子像素电路组，与所述两个第三子发光元件组一一对应的两个第三子像素电路组；
    其中，每个所述第一子发光元件组中的各个所述第二发光元件，与对应的所述第一子像素电路组中的各个所述第二像素电路通过所述第一导电线连接；每个所述第二子发光元件组中的各个所述第二发光元件，与对应的所述第二子像素电路组中的各个所述第二像素电路通过所述第二导电线连接；每个所述第三子发光元件组中的各个所述第二发光元件，与对应的所述第三子像素电路组中的各个所述第二像素电路通过所述第三导电线连接。
  16. 根据权利要求15所述的显示面板，其中，每个所述第一子发光元件组中的各个所述第二发光元件所连接的所述第一导电线，每个所述第二子发光元件组中的各个所述第二发光元件所连接的所述第二导电线，每个所述第三子发光元件组中的各个所述第二发光元件所连接的所述第三导电线，包括：第四导电线段、第五导电线段和第六导电线段和第七导电线段；
    所述第四导电线段的一端与对应的所述第二发光元件连接，所述第四导电线段的另一端与所述第五导电线段的一端连接；
    所述第五导电线段的另一端与所述第六导电线段的一端连接；
    所述第六导电线段的另一端与所述第七导电线段的一端连接；
    所述第七导电线段的另一端与对应的所述第二像素电路连接；
    其中，所述第五导电线段与所述第七导电线段沿所述第一方向延伸，所述 第六导电线段沿所述第二方向延伸；所述第四导电线段位于所连接的所述第二发光元件所在行与相邻行之间；
    所述第一导电线包括的第五导电线段位于第2个所述发光元件组至第4个所述发光元件组所在区域内，所述第二导电线包括的第五导电线段位于第3个所述发光元件组和第4个所述发光元件组所在区域内，所述第三导电线包括的第五导电线段位于第4个所述发光元件组所在区域内；沿所述轴线远离所述第二子显示区一侧的所述第六导电线段位于所述第二显示区远离所述第二子显示区一侧，沿所述轴线靠近所述第二子显示区一侧的所述第六导电线段位于靠近所述第二子显示区的第二显示区内。
  17. 根据权利要求11至16任一所述的显示面板，其中，第1个所述发光元件组至第3个所述发光元件组分别包括12列所述第二发光元件；第4个所述发光元件组包括8列所述第二发光元件；
    第1个所述像素电路组至第3个所述像素电路组分别包括12列所述第二像素电路；第4个所述像素电路组包括8列所述第二像素电路。
  18. 根据权利要求10至17任一所述的显示面板，其中，所述显示面板还包括：多个金属层；
    每个所述第二像素电路所连接的数据线与任一所述金属层同层设置；
    其中，所述多个金属层包括：第一栅极金属层、第二栅极金属层、第一源漏极金属层和第二源漏极金属层。
  19. 根据权利要求18所述的显示面板，其中，沿远离相邻的所述第三子显示区的方向，每个所述目标子显示区内的第一列至第i列所述第二像素电路中，位于奇数列的所述第二像素电路所连接的数据线与所述第一栅极金属层同层；位于偶数列的所述第二像素电路所连接的数据线与所述第二栅极金属层同层；第i列至第n列所述第二像素电路所连接的数据线与所述第一源漏金属层同层，i为大于1且小于n的整数，n等于每个所述目标子显示区内的总列数。
  20. 根据权利要求19所述的显示面板，其中，每个所述第二像素电路所连 接的数据线包括：第一数据线段、第二数据线段和第三数据线段；
    所述第一数据线段的一端与对应的金属层连接，另一端与所述第二数据线段的一端连接，所述第二数据线段的另一端与所述第三数据线段的一端连接，所述第三数据线段的另一端与所述第二像素电路连接；
    其中，所述第二数据线段沿所述第一方向延伸，且与所述第一栅极金属层同层的数据线包括的第二数据线段、与所述第二栅极金属层同层的数据线包括的第二数据线段，以及与所述第一源漏金属层同层的数据线包括的第二数据线段互不重叠。
  21. 根据权利要求19所述的显示面板，其中，所述第二源漏金属层覆盖所述第一栅极金属层、所述第二栅极金属层和所述第一源漏金属层。
  22. 根据权利要求10至21任一所述的显示面板，其中，同一列所述第二像素电路中，位于所述第一子显示区的所述第二像素电路所连接的数据线，与位于所述第二子显示区的所述第二像素电路所连接的数据线不同。
  23. 根据权利要求10至22任一所述的显示面板，其中，所述显示面板还包括至少一列虚设第二像素电路，且所述至少一列虚设第二像素电路位于靠近所述第二显示区的所述目标子显示区中。
  24. 根据权利要求1至23任一所述的显示面板，其中，所述多个第一像素电路和所述多个第二像素电路中，任一像素电路的宽度小于任一所述第一发光元件的宽度。
  25. 根据权利要求24所述的显示面板，其中，每个像素电路的宽度与所述第一发光元件的宽度相差4微米。
  26. 根据权利要求1至25任一所述的显示面板，其中，每个所述第二像素电路和每个所述第二发光元件均具有转接部，所述导电线分别连接至所述至少一个第二像素电路的转接部，以及所述至少一个第二发光元件的转接部。
  27. 根据权利要求1至26任一所述的显示面板，其中，所述导电线为透明导电线。
  28. 根据权利要求27所述的显示面板，其中，所述透明导电线的材料为氧化铟锡。
  29. 根据权利要求1至28任一所述的显示面板，其中，所述第二显示区为透光显示区。
  30. 一种显示装置，其中，所述显示装置包括：集成电路，以及如权利要求1至29任一所述的显示面板；
    所述集成电路与所述显示面板中的第一像素电路和第二像素电路连接，并用于驱动所述第一像素电路和所述第二像素电路工作。
  31. 根据权利要求30所述的显示装置，其中，所述显示装置还包括：感光传感器，且所述感光传感器位于所述显示面板的第二显示区内。
  32. 根据权利要求31所述的显示装置，其中，所述第二显示区为矩形，所述感光传感器在所述衬底基板上的正投影面积小于等于所述第二显示区的内切圆的面积。
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CN210515985U (zh) * 2019-11-21 2020-05-12 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN116665551A (zh) * 2020-02-14 2023-08-29 群创光电股份有限公司 电子装置
CN114586168A (zh) * 2020-09-30 2022-06-03 京东方科技集团股份有限公司 显示面板及显示装置
CN112072000B (zh) * 2020-11-11 2021-01-29 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
JP2022104577A (ja) * 2020-12-28 2022-07-08 大日本印刷株式会社 有機デバイス、マスク群、マスク、及び有機デバイスの製造方法
KR20220094294A (ko) * 2020-12-28 2022-07-06 삼성디스플레이 주식회사 표시 장치
CN115552622A (zh) * 2021-04-30 2022-12-30 京东方科技集团股份有限公司 显示基板及显示装置
CN113707092B (zh) * 2021-09-10 2022-09-27 武汉华星光电半导体显示技术有限公司 显示面板及电子装置
CN117837295A (zh) * 2022-07-19 2024-04-05 京东方科技集团股份有限公司 显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020038758A (ja) * 2018-09-03 2020-03-12 株式会社ジャパンディスプレイ 表示装置、及び表示装置の製造方法
CN111180494A (zh) * 2020-01-03 2020-05-19 武汉天马微电子有限公司 一种显示面板及显示装置
CN111261684A (zh) * 2020-01-22 2020-06-09 Oppo广东移动通信有限公司 显示屏及电子设备
CN111261677A (zh) * 2020-01-14 2020-06-09 昆山国显光电有限公司 显示面板以及显示装置
CN111402743A (zh) * 2020-03-24 2020-07-10 昆山国显光电有限公司 显示面板及显示装置

Family Cites Families (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4715850B2 (ja) 2008-01-15 2011-07-06 ソニー株式会社 表示装置及びその駆動方法と電子機器
US20130083080A1 (en) * 2011-09-30 2013-04-04 Apple Inc. Optical system and method to mimic zero-border display
KR102412675B1 (ko) * 2015-06-03 2022-06-24 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN105047686B (zh) 2015-06-30 2018-09-04 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN106469743A (zh) 2015-08-14 2017-03-01 昆山工研院新型平板显示技术中心有限公司 像素结构、oled显示面板及其制作方法
KR102465379B1 (ko) * 2015-12-02 2022-11-10 삼성디스플레이 주식회사 디스플레이 장치
KR20170113066A (ko) * 2016-03-24 2017-10-12 삼성전자주식회사 디스플레이를 가진 전자 장치 및 그의 이미지 표시 방법
JP2018180110A (ja) * 2017-04-06 2018-11-15 株式会社ジャパンディスプレイ 表示装置
EP3609165B1 (en) 2017-04-25 2021-09-22 Huawei Technologies Co., Ltd. Electronic device comprising lcd display screen and manufacturing method thereof
US10360854B2 (en) * 2017-06-14 2019-07-23 Lg Display Co., Ltd. Gate driving circuit having a compensating auxiliary load and display device using the same
TWI614695B (zh) 2017-07-03 2018-02-11 敦泰電子有限公司 具指紋辨識之高屏佔比顯示裝置
CN107731870B (zh) 2017-09-28 2020-12-22 上海天马有机发光显示技术有限公司 有机发光二极管像素结构及包含其的显示面板、显示装置
CN108365123A (zh) 2017-09-30 2018-08-03 云谷（固安）科技有限公司 显示屏以及电子设备
WO2019062187A1 (zh) 2017-09-30 2019-04-04 云谷（固安）科技有限公司 显示屏以及电子设备
CN108389879B (zh) 2017-09-30 2021-06-15 云谷（固安）科技有限公司 显示屏以及电子设备
CN107610645B (zh) 2017-10-26 2020-04-28 上海天马有机发光显示技术有限公司 一种oled显示面板、其驱动方法及显示装置
CN107610635B (zh) 2017-10-27 2021-03-05 武汉天马微电子有限公司 一种显示面板和电子设备
CN108010947B (zh) 2017-11-29 2021-01-08 上海天马有机发光显示技术有限公司 一种有机发光显示面板和有机发光显示装置
CN207425860U (zh) 2017-12-08 2018-05-29 京东方科技集团股份有限公司 一种有机发光显示面板及显示装置
CN108445684A (zh) 2018-02-27 2018-08-24 上海中航光电子有限公司 阵列基板、显示面板与显示装置
CN108682395B (zh) * 2018-04-09 2021-09-21 厦门天马微电子有限公司 一种显示面板、其驱动方法及显示装置
CN108922482A (zh) 2018-06-26 2018-11-30 惠科股份有限公司 显示面板及其驱动方法
CN109037287A (zh) 2018-07-27 2018-12-18 京东方科技集团股份有限公司 子像素排列结构、掩膜装置、显示面板及显示装置
US10707281B2 (en) * 2018-08-10 2020-07-07 Au Optronics Corporation Display apparatus
CN110969982B (zh) 2018-09-28 2022-09-13 北京小米移动软件有限公司 显示结构、显示面板和显示装置
CN110767681B (zh) 2018-10-31 2022-12-13 昆山国显光电有限公司 显示屏及显示终端
CN209731298U (zh) * 2018-11-09 2019-12-03 Oppo广东移动通信有限公司 折叠式移动终端
CN109671759A (zh) 2018-12-18 2019-04-23 武汉华星光电半导体显示技术有限公司 Oled像素结构
US20200194512A1 (en) 2018-12-18 2020-06-18 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Organic light-emitting diode pixel structure
CN109742128B (zh) 2019-01-28 2021-01-01 昆山国显光电有限公司 显示器及其显示面板
CN110767174B (zh) 2019-01-31 2021-05-04 昆山国显光电有限公司 显示装置及其显示面板、oled阵列基板
CN110767157B (zh) 2019-01-31 2020-11-06 昆山国显光电有限公司 显示装置及其显示面板、oled阵列基板
CN109801950B (zh) 2019-01-31 2021-02-26 厦门天马微电子有限公司 显示面板、显示装置及显示面板的制作方法
CN109950288B (zh) 2019-03-29 2021-05-28 上海天马微电子有限公司 一种显示面板和显示装置
CN109904214B (zh) 2019-03-29 2021-01-29 上海天马有机发光显示技术有限公司 一种显示面板、包含其的显示装置
CN111180483B (zh) * 2019-04-04 2021-02-26 昆山国显光电有限公司 Oled阵列基板、显示面板及显示装置
CN110061014B (zh) 2019-04-30 2021-06-08 武汉天马微电子有限公司 一种显示面板及显示装置
CN110232892A (zh) 2019-05-16 2019-09-13 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN110767720B (zh) 2019-06-05 2020-09-08 昆山国显光电有限公司 显示基板、显示面板及显示装置
US11183544B2 (en) 2019-06-25 2021-11-23 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and display device
CN110265455B (zh) 2019-06-25 2020-11-24 武汉华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN210245501U (zh) 2019-07-03 2020-04-03 昆山国显光电有限公司 阵列基板、显示面板及显示装置
CN110603578B (zh) 2019-07-31 2023-05-16 京东方科技集团股份有限公司 显示设备的全面板显示器
CN110459175A (zh) 2019-08-09 2019-11-15 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
US11074856B2 (en) 2019-08-09 2021-07-27 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and display device
CN110379356B (zh) * 2019-08-29 2022-04-22 武汉天马微电子有限公司 显示面板及显示装置
CN112542484A (zh) * 2019-09-20 2021-03-23 北京小米移动软件有限公司 显示面板、显示屏及电子设备
CN110634930B (zh) 2019-09-27 2022-02-25 京东方科技集团股份有限公司 显示面板和显示装置
CN110825264B (zh) 2019-10-31 2022-10-11 厦门天马微电子有限公司 显示面板及驱动方法、触控显示装置
EP4024377A4 (en) * 2019-10-31 2022-08-24 Guangdong Oppo Mobile Telecommunications Corp., Ltd. DISPLAY DEVICE AND ELECTRONIC DEVICE
CN210515985U (zh) 2019-11-21 2020-05-12 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN114550606A (zh) 2019-12-02 2022-05-27 武汉天马微电子有限公司 一种显示面板和显示装置
CN110890026B (zh) 2019-12-05 2021-10-15 昆山国显光电有限公司 显示面板及显示装置
CN111211152B (zh) 2020-01-14 2021-06-25 昆山国显光电有限公司 显示面板及显示装置
CN111326560B (zh) 2020-01-23 2023-08-22 京东方科技集团股份有限公司 显示基板和显示装置
WO2021157950A1 (ko) * 2020-02-06 2021-08-12 삼성전자 주식회사 디스플레이 구동 방법 및 이를 지원하는 전자 장치
CN111446282B (zh) 2020-04-28 2022-04-22 京东方科技集团股份有限公司 显示基板及显示装置
CN111508377A (zh) 2020-05-29 2020-08-07 京东方科技集团股份有限公司 一种显示面板及显示装置
CN111710276B (zh) 2020-06-24 2024-08-23 武汉天马微电子有限公司 显示面板及显示装置
CN111725287A (zh) 2020-06-30 2020-09-29 武汉天马微电子有限公司 显示面板、显示装置及显示面板的制作方法
CN115117133A (zh) 2020-07-20 2022-09-27 武汉天马微电子有限公司 一种显示面板及显示装置
CN111951727B (zh) * 2020-08-25 2022-10-18 昆山国显光电有限公司 显示面板及显示装置
CN117915689A (zh) * 2020-08-27 2024-04-19 武汉天马微电子有限公司 显示面板及显示装置
CN114586168A (zh) * 2020-09-30 2022-06-03 京东方科技集团股份有限公司 显示面板及显示装置
CN112186021B (zh) 2020-09-30 2023-08-22 武汉天马微电子有限公司 显示面板及显示装置
CN112542121B (zh) 2020-12-03 2023-01-31 Oppo广东移动通信有限公司 显示结构、显示屏及电子设备
CN113053981B (zh) * 2021-03-15 2024-09-06 京东方科技集团股份有限公司 阵列基板、其制作方法、显示面板及显示装置
CN113517324A (zh) 2021-05-25 2021-10-19 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
KR20230172135A (ko) * 2022-06-15 2023-12-22 엘지디스플레이 주식회사 디스플레이 장치 및 디스플레이 구동 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020038758A (ja) * 2018-09-03 2020-03-12 株式会社ジャパンディスプレイ 表示装置、及び表示装置の製造方法
CN111180494A (zh) * 2020-01-03 2020-05-19 武汉天马微电子有限公司 一种显示面板及显示装置
CN111261677A (zh) * 2020-01-14 2020-06-09 昆山国显光电有限公司 显示面板以及显示装置
CN111261684A (zh) * 2020-01-22 2020-06-09 Oppo广东移动通信有限公司 显示屏及电子设备
CN111402743A (zh) * 2020-03-24 2020-07-10 昆山国显光电有限公司 显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4203046A4 *

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