WO2022188542A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022188542A1
WO2022188542A1 PCT/CN2022/071427 CN2022071427W WO2022188542A1 WO 2022188542 A1 WO2022188542 A1 WO 2022188542A1 CN 2022071427 W CN2022071427 W CN 2022071427W WO 2022188542 A1 WO2022188542 A1 WO 2022188542A1
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Prior art keywords
light
emitting elements
pixel circuits
display panel
conductive lines
Prior art date
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PCT/CN2022/071427
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English (en)
French (fr)
Inventor
王琦伟
肖邦清
龙跃
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000031.XA priority Critical patent/CN115349173A/zh
Priority to US18/025,962 priority patent/US20230371324A1/en
Publication of WO2022188542A1 publication Critical patent/WO2022188542A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • H—ELECTRICITY
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    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/65—OLEDs integrated with inorganic image sensors
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Definitions

  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • the under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of the display device.
  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel, comprising: a base substrate, a plurality of light-emitting elements, a plurality of pixel circuits, and a plurality of conductive lines, the base substrate having a first display area and a second display area , the first display area is located on at least one side of the second display area; the plurality of light-emitting elements are located in the first display area and the second display area, and the plurality of light-emitting elements include multiple groups of light-emitting elements elements, the light-emitting elements in each group of the multiple groups of light-emitting elements are arranged along the first direction, the multiple groups of light-emitting elements are arranged along the second direction, and at least one group of the multiple groups of light-emitting elements includes a plurality of first An area light emitting element and a plurality of second area light emitting elements, the plurality of first area light emitting elements are located in the first display area, and the plurality of second area light emitting elements are located
  • the circuits are arranged along the second direction, and at least one of the plurality of groups of pixel circuits includes a plurality of pixel circuits of a first type and a plurality of pixel circuits of a second type, the plurality of pixel circuits of the second type Spaces are distributed between the plurality of first-type pixel circuits, at least one first-type pixel circuit in the plurality of first-type pixel circuits and at least one of the plurality of first-area light-emitting elements
  • the first area light-emitting element is connected, and the orthographic projection of the at least one first type of pixel circuit on the base substrate is at least partially the orthographic projection of the at least one first area light-emitting element on the base substrate overlapping; at least one second type pixel circuit in the plurality of second type pixel circuits and at least one second area light emitting element in the plurality of second area light emitting elements pass through at least one of the plurality of conductive lines A conductive line is connected; the plurality of second area light
  • Conductive lines, the plurality of first light-emitting elements and the plurality of first pixel circuits are connected through the plurality of first conductive lines, and the plurality of second light-emitting elements and the plurality of second pixel circuits are connected through the plurality of second pixel circuits.
  • the plurality of second conductive lines are connected, and in the at least one group of light-emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected to the plurality of first light-emitting elements are smaller than the plurality of first pixel circuits connected to the plurality of first light-emitting elements.
  • Each of the plurality of second pixel circuits connected to the plurality of second light-emitting elements is closer to the second display area, and the display panel includes a first transparent conductive pattern layer and a second transparent conductive pattern layer, so At least one first conductive line in the plurality of first conductive lines is located in the second transparent conductive pattern layer, and at least one second conductive line in the plurality of second conductive lines is located in the first transparent conductive pattern layer .
  • a display panel the plurality of conductive lines are located between the plurality of light emitting elements and the plurality of pixel circuits in a direction perpendicular to the main surface of the base substrate.
  • At least one second conductive line near the center of the second display area spans at least two groups of light emitting elements in the second direction.
  • At least one second conductive line near the center of the second display area extends from the second display area to the first display area in the second direction.
  • a display panel wherein the first conductive line is a conductive line with an integrated structure, and the second conductive line is a conductive line with an integrated structure.
  • the plurality of second area light-emitting elements further include a plurality of third light-emitting elements configured to emit light of a third color
  • the plurality of second-type light-emitting elements The pixel circuit further includes a plurality of third pixel circuits
  • the plurality of conductive lines further includes a plurality of third conductive lines
  • the plurality of third light-emitting elements and the plurality of third pixel circuits pass through the plurality of third Conductive lines are connected, and in the at least one group of light-emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected to the plurality of first conductive lines are more conductive than the plurality of third conductive lines.
  • Each of the plurality of third pixel circuits connected by lines is closer to the second display area, and a part of the third conductive lines of the plurality of third conductive lines are located in the first transparent conductive pattern layer and another part of the third conductive lines in the plurality of third conductive lines is located in the second transparent conductive pattern layer.
  • At least one third conductive line near the center of the second display area spans at least two groups of light-emitting elements in the second direction.
  • At least one third conductive line near the center of the second display area extends from the second display area to the first display area in the second direction.
  • a first conductive line connected to the group of light-emitting elements is located on a first side of the group of light-emitting elements, and is connected to the first side of the group of light-emitting elements.
  • the second conductive line and the third conductive line connected to the group of light-emitting elements are located on the second side of the group of light-emitting elements, and the first side and the second side are opposite sides of the group of light-emitting elements.
  • a display panel at least one of the plurality of sets of pixel circuits includes a dummy pixel circuit located between two pixel circuits of the second type in the first direction,
  • the orthographic projection of at least one of the second conductive line near the center of the second display area and the third conductive line near the center of the second display area on the base substrate is where the dummy pixel circuit is located.
  • the orthographic projections on the base substrate overlap.
  • a display panel is provided, and the third conductive line is a conductive line of an integrated structure.
  • a display panel is provided, the display panel further includes a planarization layer, the light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer between the first electrode and the second electrode, The first electrode is closer to the base substrate than the second electrode, the planarization layer is located between the first electrode of the light-emitting element and the pixel circuit, and the via hole in the planarization layer.
  • the orthographic projection on the base substrate does not overlap with the orthographic projection of the dummy pixel circuit on the base substrate.
  • the second conductive line near the center of the second display area and the third conductive line near the center of the second display area include a first part, a second part, a A third part, and a fourth part, the second part and the fourth part extend in the first direction, and the first part and the third part extend in the second direction.
  • a display panel is provided, the orthographic projection of the third portion on the base substrate overlaps the orthographic projection of the dummy pixel circuit on the base substrate.
  • the fourth part and the second part are located on the same side of the third part.
  • a display panel is provided, and the fourth part and the second part are located on both sides of the third part.
  • the plurality of second area light-emitting elements further include a plurality of fourth light-emitting elements configured to emit light of a fourth color
  • the plurality of second-type light-emitting elements The pixel circuit further includes a plurality of fourth pixel circuits
  • the plurality of conductive lines further includes a plurality of fourth conductive lines
  • the plurality of fourth light-emitting elements and the plurality of fourth pixel circuits pass through the plurality of fourth Conductive lines are connected, and in the at least one group of light-emitting elements and the at least one group of pixel circuits, a plurality of fourth pixel circuits connected to the plurality of fourth conductive lines are more than connected to the plurality of second conductive lines
  • Each of the plurality of second pixel circuits is closer to the second display area.
  • a display panel at least one group of light-emitting elements includes a first subset of light-emitting elements and a second subset of light-emitting elements, the first subset of light-emitting elements being closer to all the light-emitting elements than the second subset of light-emitting elements the edge of the second display area, or the second sub-group of light-emitting elements is closer to the center of the second display area than the first sub-group of light-emitting elements;
  • the at least one group of light-emitting elements includes the first group of light-emitting elements , in the first group of light-emitting elements, the conductive lines connected with the second light-emitting element and the third light-emitting element in the first sub-group of light-emitting elements are located in the first transparent conductive pattern layer, The conductive lines connected to the first light-emitting element and the fourth light-emitting element in the first subgroup of light-emitting elements are all
  • the at least one group of light-emitting elements includes a second group of light-emitting elements, the first group of light-emitting elements is closer to the center of the second display area than the second group of light-emitting elements,
  • the conductive lines connected to the light-emitting elements in the first sub-group of light-emitting elements are all located in the first transparent conductive pattern layer, and the conductive lines connected to the second sub-group of light-emitting elements are located in the first transparent conductive pattern layer.
  • the conductive lines connected to the light-emitting elements in all are located in the second transparent conductive pattern layer.
  • a display panel is provided, and the fourth conductive line is a conductive line of an integrated structure.
  • the first transparent conductive pattern layer is closer to the base substrate than the second transparent conductive pattern layer.
  • the second transparent conductive pattern layer is closer to the base substrate than the first transparent conductive pattern layer.
  • a display panel the second display area has a first axis of symmetry extending along the first direction and a second axis of symmetry extending along the second direction, the plurality of conductive lines are opposite to each other Axisymmetric about the first symmetry axis and the second symmetry axis.
  • two pixel circuits of the first type are disposed between two adjacent pixel circuits of the second type.
  • a display panel is provided, an orthographic projection of a portion of the first conductive line extending in the first direction on the base substrate and an orthographic projection of the second conductive line in the first direction
  • the orthographic projections of the extended portion on the base substrate do not overlap.
  • the fourth light emitting element and the first light emitting element are configured to emit green light
  • one of the second light emitting element and the third light emitting element is configured to emit red light
  • the other of the second light emitting element and the third light emitting element is configured to emit blue light.
  • a display panel is provided, a part of the first conductive lines of the plurality of first conductive lines is located in the second transparent conductive pattern layer, and another part of the first conductive lines of the plurality of first conductive lines is first conductive Lines are located on the first transparent conductive pattern layer.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
  • the display device further includes a photosensitive sensor, and the photosensitive sensor is located on one side of the display panel.
  • FIG. 1A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 1B is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a first display area and a second display area in a display panel according to an embodiment of the present disclosure.
  • 5A to 5C are partial plan views of a display panel according to an embodiment of the present disclosure.
  • 5D to 5F are schematic structural diagrams of display panels provided by some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of a light emitting element located in a second display area in a display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a row of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a row of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of two rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of multiple rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of multiple rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a first transparent conductive pattern layer, a light-emitting element, and a pixel circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a second transparent conductive pattern layer, a light-emitting element, and a pixel circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a plurality of rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • 15 is a schematic diagram of conductive lines located in a first transparent conductive pattern layer connected to multiple rows of light-emitting elements located in a second display area in a display panel according to an embodiment of the present disclosure.
  • Fig. 16 is a schematic diagram of conductive lines in a second conductive pattern layer connected to a plurality of rows of light-emitting elements in a second display area in a display panel according to an embodiment of the present disclosure.
  • 17 is a schematic diagram of a plurality of rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a first transparent conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of a second transparent conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a second transparent conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of a first transparent conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 22 is a schematic diagram of a layer structure of a display panel according to an embodiment of the disclosure.
  • FIG. 23 is a schematic diagram of a layer structure of a display panel according to an embodiment of the disclosure.
  • FIG. 24 is a schematic diagram of a first pixel unit in a display panel according to an embodiment of the disclosure.
  • FIG. 25 is a schematic diagram of a second pixel unit in a display panel according to an embodiment of the disclosure.
  • FIG. 26 is a cross-sectional view of a display panel.
  • FIG. 27 is a schematic diagram of forming a photoresist pattern.
  • FIG. 28 is a schematic diagram of forming conductive lines.
  • FIG. 29 is a schematic diagram of a pixel circuit of a first type in a first display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 30 is a schematic diagram of a portion of the film layer in FIG. 29 .
  • FIG. 31 is a schematic diagram of some film layers in a pixel circuit of a first type in a first display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 32 is a schematic diagram of a second type of pixel circuit in a first display area of a display panel provided by an embodiment of the present disclosure.
  • FIG. 33 is a schematic diagram of a portion of the film layer in FIG. 32 .
  • FIG. 34 is a schematic diagram of some film layers in the second type pixel circuit in the first display area of the display panel according to the embodiment of the present disclosure.
  • 35 is a schematic diagram of a pixel circuit in a region with vertical conductive lines in a first display region of a display panel according to an embodiment of the present disclosure.
  • FIG. 36 is a schematic diagram of some of the layers of FIG. 35 .
  • FIG. 37 is a schematic diagram of a part of a film layer in a region with vertical conductive lines in a first display area of a display panel according to an embodiment of the present disclosure.
  • 38 and 39 are schematic diagrams of a display device according to an embodiment of the present disclosure.
  • FIG. 40 shows the structural layout of the pixel circuit before and after compression.
  • FIG. 41 is a schematic diagram of a pixel unit in a display panel.
  • a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for setting the camera.
  • the second display area generally includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit is connected to a light-emitting element, and is used to drive the light-emitting element to emit light, and the mutually connected pixel circuits and light-emitting elements are perpendicular to the display panel. overlapping in direction.
  • FIG. 1A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 1B is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel may include: a base substrate BS.
  • the display panel includes a first display area R1 and a second display area R2, and the first display area R1 may be located at at least one side of the second display area R2.
  • the first display region R1 surrounds the second display region R2. That is, the second display area R2 may be surrounded by the first display area R1.
  • the second display area R2 may also be set at other positions, and the setting position of the second display area R2 may be determined as required.
  • the second display area R2 may be located at the top middle position of the base substrate BS, or may be located at the upper left corner position or the upper right corner position of the base substrate BS.
  • hardware such as a photosensitive sensor (such as a camera) is arranged in the second display area R2 of the display panel.
  • the second display area R2 is a light-transmitting display area
  • the first display area R1 is a display area.
  • the first display area R1 is opaque and only used for display.
  • FIG. 1B shows that the first display area R1 includes the auxiliary area Ra.
  • FIG. 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a pixel unit 100, and the pixel unit 100 is located on the base substrate.
  • the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b.
  • the pixel circuit 100a is configured to supply a drive current to drive the light-emitting element 100b to emit light.
  • the light emitting element 100b is an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit 100a.
  • the color of light emitted by the light-emitting element 100b may be determined as required.
  • the pixel circuits driving the light emitting elements of the second display area R2 may be arranged in the first display area R1. That is, the light transmittance of the second display region R2 is improved by arranging the light-emitting element and the pixel circuit separately. That is, in the second display region R2, the pixel circuit 100a is not provided.
  • FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel includes: a plurality of pixel circuits 10 of the first type, a plurality of pixel circuits 20 of the second type, and a plurality of light-emitting elements 30 of the first region located in the first display area R1 , and A plurality of second region light emitting elements 40 in the two display regions R2.
  • a plurality of pixel circuits 20 of the second type may be distributed between a plurality of pixel circuits 10 of the first type.
  • At least one first-type pixel circuit 10 among the plurality of first-type pixel circuits 10 may be connected to at least one first-area light-emitting element 30 among the plurality of first-area light-emitting elements 30 , And the orthographic projection of the at least one pixel circuit 10 of the first type on the base substrate BS and the orthographic projection of the at least one first region light-emitting element 30 on the base substrate BS may at least partially overlap.
  • the at least one pixel circuit 10 of the first type can be used to provide a driving signal for the connected first area light emitting element 30 to drive the first area light emitting element 30 to emit light.
  • At least one second-type pixel circuit 20 among the plurality of second-type pixel circuits 20 may conduct electrical conduction with at least one second-area light-emitting element 40 among the plurality of second-area light-emitting elements 40
  • the line L1 is connected, and the at least one second-type pixel circuit 20 can be used to provide a driving signal for the connected second area light-emitting element 40 to drive the second area light-emitting element 40 to emit light.
  • the orthographic projection of at least one second-type pixel circuit 20 on the base substrate BS and at least one second-area light-emitting There is no overlapping portion of the orthographic projection of the element 40 on the base substrate BS. That is, the orthographic projection of the pixel circuit 20 of the second type on the base substrate BS does not overlap with the orthographic projection of the second area light-emitting element 40 on the base substrate BS.
  • the first display area R1 may be set as a non-transmissive display area
  • the second display area R2 may be set as a light-transmissive display area.
  • the first display region R1 cannot transmit light
  • the second display region R2 can transmit light.
  • the display panel provided by the embodiment of the present disclosure does not need to perform hole-digging processing on the display panel, and required hardware structures such as a photosensitive sensor can be directly disposed at a position corresponding to the second display area R2 on one side of the display panel, which is The realization of true full screen lays a solid foundation.
  • the second display region R2 only includes light-emitting elements and does not include pixel circuits, it is beneficial to improve the light transmittance of the second display region R2, so that the display panel has a better display effect.
  • the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102 , the pixel circuit 100 a and the light-emitting element 100 b of the first pixel unit 101 are located in the first display area R1 , and the pixels of the second pixel unit 101 The circuit 100a is located in the first display region R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display region R2.
  • the pixel circuit 100 a of the first pixel unit 101 is the first type of pixel circuit 10
  • the light emitting element 100 b of the first pixel unit 101 is the first area light emitting element 30
  • the second pixel unit 101 The pixel circuit 100 a is the second type of pixel circuit 20
  • the light-emitting element 100 b of the second pixel unit 102 is the second-area light-emitting element 40 .
  • the first area light-emitting element 30 may be referred to as an in-situ light-emitting element.
  • the first type of pixel circuit 10 may be referred to as an in-situ pixel circuit
  • the second type of pixel circuit 20 may be referred to as an ex-situ pixel circuit.
  • the second area light emitting element 40 and the second type of pixel circuit 20 connected to the second area light emitting element 40 are located in the same row. That is, the light-emitting signals of the second area light-emitting elements 40 come from the second-type pixel circuits in the same row. For example, pixel circuits of the same row of pixel units are connected to the same gate line.
  • the pixel circuit of the second pixel unit 102 (the second type of pixel circuit 20 ) is connected to the light emitting element (the second area light emitting element 40 ) of the second pixel unit 102 through the conductive line L1 .
  • the conductive line L1 is made of transparent conductive material.
  • the conductive line L1 is made of conductive oxide material.
  • the conductive oxide material includes, but is not limited to, indium tin oxide (ITO).
  • one end of the conductive line L1 is connected to the pixel circuit 20 of the second type, and the other end of the conductive line L1 is connected to the second area light-emitting element 40 .
  • the conductive line L1 extends from the first display region R1 to the second display region R2 .
  • the first display region R1 may include an auxiliary region Ra, and the auxiliary region Ra may be provided for the second type of pixel circuit 20 connected to the second region light-emitting element 40 .
  • the auxiliary region Ra of the first display area R1 or an area other than the auxiliary area Ra a plurality of dummy pixel circuits may be provided.
  • the dummy pixel circuit is not connected to any light emitting element. Setting the dummy pixel circuit is beneficial to improve the uniformity of the components of each film layer in the etching process.
  • the structure of the dummy pixel circuit is the same as that of the second type of pixel circuit 20 in its row or column, but it is not connected to any light-emitting element.
  • the auxiliary area Ra and the area (non-auxiliary area) of the first display area R1 other than the auxiliary area Ra have the same pixel density or the same resolution, but are not limited thereto.
  • FIG. 3 shows three rows of light-emitting elements 100b.
  • the first row of light-emitting elements 100b shown in FIG. 3 passes through the first display region R1 and the second display region R2, and is a row of light-emitting elements 100b passing through two regions.
  • the second row of light-emitting elements 100b shown in FIG. 3 passes through the first display region R1 and the second display region R2, and is a row of light-emitting elements 100b passing through two regions.
  • the third row of light-emitting elements 100b shown in FIG. 3 only passes through the first display region R1 and does not pass through the second display region R2, and is a row of light-emitting elements 100b passing through one region.
  • the light emitting element 100b is divided to include two types of row light emitting elements, ie, a row of light emitting elements passing through two regions and a row of light emitting elements passing through one region.
  • FIG. 4 is a schematic diagram of a first display area and a second display area in a display panel according to an embodiment of the present disclosure.
  • a light-transmitting region R0 is provided between adjacent second-region light-emitting elements 40 .
  • a plurality of light-transmitting regions R0 are connected to each other to form continuous light-transmitting regions separated by a plurality of second-region light-emitting elements 40 .
  • the conductive line L1 is made of a transparent conductive material to improve the light transmittance of the light-transmitting region R0 as much as possible.
  • the regions of the second display region R2 other than the regions where the second region light-emitting elements 40 are disposed may be all light-transmitting regions.
  • 5A to 5C are partial plan views of a display panel according to an embodiment of the present disclosure. 5A to 5C are described below.
  • FIG. 5A is a schematic diagram of a first display area and a second display area of a display panel according to an embodiment of the present disclosure.
  • the second display area R2 is a light-transmitting display area
  • the first display area R1 is a display area.
  • FIG. 5B is a schematic diagram of a first area light emitting element in a first display area and a second area light emitting element in a second display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 5B shows the first area light emitting element 30 and the second area light emitting element 40 .
  • the density of the second-area light-emitting elements 40 may be equal to the density of the first-area light-emitting elements 30 . That is, the resolution of the second display region R2 is the same as the resolution of the first display region R1.
  • the density of the light-emitting elements 40 in the second area may be greater or smaller than the density of the light-emitting elements 30 in the first area. That is, the resolution of the second display region R2 may be larger or smaller than that of the first display region R1. For example, as shown in FIGS.
  • the light-emitting area of the second-area light-emitting element 40 is smaller than the light-emitting area of the first-area light-emitting element 30 . That is, the light emitting area of the first area light emitting element 30 is larger than the light emitting area of the second area light emitting element 40 .
  • the light emitting area of the light emitting element may correspond to the area of the opening of the pixel definition layer.
  • FIG. 5C shows the first area light emitting element 30, the second area light emitting element 40, the first type of pixel circuit 10, the second type of pixel circuit 20, the connection element CE0, and the conductive line L1.
  • Each pixel circuit is connected to the light emitting element through the connection element CE0. That is, each pixel unit has one connection element CE0. That is, the pixel circuit 10 of the first type is connected to the first area light emitting element 30 through the connection element CE0, and the pixel circuit 20 of the second type is connected to the second area light emitting element 40 through the connection element CE0.
  • connection element CE0 is connected to the pixel circuit 100a and the light-emitting element 100b, respectively.
  • the connection element CE0 is connected to the light-emitting control transistor in the pixel circuit 100a and the first pole of the light-emitting element 100b, respectively.
  • the connecting element CE0 can be formed from a single conductive part, or it can be formed from two different conductive parts located on different layers.
  • the connection element CE0 may comprise one conductive feature in one conductive layer and another conductive feature in another conductive layer.
  • a conductive line L1 passes through the area where the pixel circuit of the pixel unit is located to connect the second type pixel circuit 20 and the second area light emitting element 40 on both sides of the pixel unit respectively.
  • the area where the pixel circuit of the pixel unit is located overlaps with a plurality of conductive lines L1 passing through the area.
  • the region in the first display region R1 where the pixel circuits 20 of the second type are disposed may be referred to as an auxiliary region Ra (as shown in FIGS. 1B and 3 ), and the auxiliary region Ra may also be referred to as a transition region.
  • FIG. 5C takes a first-type pixel circuit 10 overlapping with at most two conductive lines L1 as an example.
  • a first-type pixel circuit 10 may also overlap with more conductive lines L1 .
  • one pixel circuit 10 of the first type may overlap 5-15 conductive lines L1. How many conductive lines L1 one pixel circuit 10 of the first type overlaps can be determined as required.
  • the pixel circuit 20 of the second type may also overlap the conductive line L1 not connected thereto.
  • the size of the pixel circuits 10 of the first type may be compressed in the first direction X to obtain an area where the pixel circuits 20 of the second type are disposed.
  • the auxiliary area in the auxiliary area, one column of pixel circuits 20 of the second type is provided for every set column of the pixel circuits 10 of the first type.
  • the number of columns of the first type of pixel circuits 10 between two adjacent columns of the second type of pixel circuits 20 may be determined as required.
  • the area where the pixel circuits 20 of the second type are disposed may be obtained by reducing the size of the pixel circuits 10 of the first type in the first direction X.
  • the size of the pixel circuit 10 of the first type in the first direction X is smaller than the size of the first area light-emitting element 30 in the first direction X.
  • the first direction X is, for example, a row direction, but is not limited thereto. In other embodiments, the first direction X may also be a column direction. The embodiments of the present disclosure are described by taking the first direction X as the row direction as an example.
  • a third direction Z which is a direction perpendicular to the main surface of the base substrate.
  • the main surface of the base substrate is the surface used to manufacture each component.
  • the upper surface of the base substrate in the cross-sectional view is the main surface of the base substrate.
  • Both the first direction X and the second direction Y are directions parallel to the main surface of the base substrate.
  • the first direction X and the second direction Y intersect.
  • the first direction X and the second direction Y are perpendicular.
  • FIG. 5D to 5F are schematic structural diagrams of display panels provided by some embodiments of the present disclosure.
  • FIG. 5D shows a schematic structural diagram of the light-emitting element in the first region of the first display region R1 .
  • Fig. 5E shows a schematic diagram of a part of the structure (including only the pixel circuit) in Fig. 5A
  • Fig. 5F shows a schematic diagram of a part of the structure (including only the light-emitting element) in Fig. 5A.
  • the width of the pixel circuit is smaller than that of the light-emitting element, so that the pixel circuits in the second and ninth columns from right to left are not connected to any light-emitting element 30 in the first area, which belongs to There is an additional column of pixel circuits, which can be used as the second type of pixel circuits 20 to connect the second region light-emitting elements 40 in the second display region R2.
  • the first region light-emitting element 30 may include the first electrodes E1 of four types of light-emitting elements, RG1BG2, which are connected to the first type of pixel circuit 10 through the connecting element CE0.
  • connection element CE0 includes two connection electrodes, which may be the connection electrode CE01 (shown in FIG. 5E ) and the connection electrode CE02 (shown in FIG. 5F ) mentioned later, respectively, but not limited thereto.
  • the axes of the connection electrodes CE01 in the same row of pixel units may be located on a straight line.
  • FIG. 5F shows four rows of connection elements CE0/connection electrodes CE02, ie, FIG. 5F shows four rows of light-emitting elements.
  • the light emitting elements in each row are sequentially arranged along the first direction X in the manner of RGBG or BGRG.
  • the light-emitting colors of the light-emitting elements are not limited to RGB, and the arrangement of the light-emitting elements is not limited to that shown in FIG. 5F .
  • the embodiments of the present disclosure are described by taking the light-emitting elements including RGBG as an example.
  • G includes G1 or G2.
  • FIG. 5F shows four rows of connection elements CE0/connection electrodes CE02, ie, FIG. 5F shows four rows of light-emitting elements.
  • the light emitting elements in each row are sequentially arranged along the first direction X in the manner of RGBG or BGRG.
  • the light-emitting colors of the light-emitting elements are not limited to RGB, and the arrangement of the light
  • one repeating unit RP includes two Gs arranged in the second direction Y and R and B respectively arranged on both sides of the two Gs in the first direction X, wherein R and G form a pixel, and borrow B in another repeating unit adjacent to it to form a virtual pixel for display, B and G form a pixel, and borrow R in another repeating unit adjacent to it to form a virtual pixels for display, but not limited to this.
  • a display panel provided by some embodiments of the present disclosure includes: a base substrate BS, a plurality of light emitting elements 100 b , and a plurality of pixel circuits 100 a.
  • the base substrate BS has a first display region R1 and a second display region R2, and the first display region R1 is located on at least one side of the second display region R2.
  • the plurality of light-emitting elements 100b are arranged in a plurality of rows and columns.
  • the plurality of light-emitting elements 100b includes a plurality of groups of light-emitting elements, the light-emitting elements in each group of the plurality of groups of light-emitting elements are arranged along the first direction X, and the plurality of groups of light-emitting elements are arranged along the second direction X. Arrangement in direction Y.
  • FIG. 3 and 5C both show three groups of light-emitting elements GP, and the three groups of light-emitting elements GP are respectively a group of light-emitting elements GPx, a group of light-emitting elements GPy, and a group of light-emitting elements GPz; a group of light-emitting elements GPx and a group of light-emitting elements GPy passes through the first display area R1 and the second display area R2, and a group of light-emitting elements GPz only passes through the first display area R1.
  • FIG. 4 shows at least four groups of light-emitting elements GP arranged in the second direction Y. As shown in FIG. FIG. FIG.
  • 5F shows at least four groups of light-emitting elements GP arranged in the second direction Y.
  • the number of groups of light emitting elements passing through the first display region R1 and the second display region R2 and the number of groups of light emitting elements passing through only the first display region R1 can be determined as required.
  • a group of light-emitting elements may be a row of light-emitting elements.
  • a group of light-emitting elements may not completely correspond to a column of light-emitting elements.
  • a group of light-emitting elements may be a column of light-emitting elements.
  • At least one of the plurality of groups of light-emitting elements includes a plurality of first-area light-emitting elements 30 and a plurality of second-area light-emitting elements 40 . That is, at least one group of the plurality of groups of light-emitting elements passes through the first display region R1 and the second display region R2.
  • the plurality of light emitting elements 100 b include at least one row of light emitting elements 100 b passing through two regions through the first display region R1 and the second display region R2 , and at least one row passing through the two regions.
  • the light-emitting element 100b in which any row of the light-emitting elements 100b passes through two regions includes a plurality of first-region light-emitting elements 30 and a plurality of second-region light-emitting elements 40 .
  • a plurality of first area light-emitting elements 30 are located in the first display area R1
  • a plurality of second area light-emitting elements 40 are located in the second display area R2 .
  • the plurality of pixel circuits include a plurality of groups of pixel circuits GR, the pixel circuits in each group of the plurality of groups of pixel circuits are arranged along a first direction X, and the plurality of groups of pixel circuits are arranged along a second direction Y arrangement.
  • at least one of the plurality of sets of pixel circuits 100a includes a plurality of pixel circuits 10 of the first type and a plurality of pixel circuits 20 of the second type.
  • 3 and 5C respectively show three groups of pixel circuits GR.
  • FIG. 5E shows four groups of pixel circuits GR. As shown in FIG. 3 and FIG. 5C , the pixel circuits are only located in the first display area R1 , and no pixel circuits are provided in the second display area R2 .
  • a plurality of pixel circuits 100a are arranged in a plurality of rows and columns, and the plurality of pixel circuits 100a include a plurality of first type pixel circuits 10 and a plurality of second type pixel circuits located in the same row 20.
  • at least one group of the plurality of groups of pixel circuits includes a plurality of pixel circuits 10 of the first type and a plurality of pixel circuits 20 of the second type.
  • a plurality of first type pixel circuits 10 and a plurality of second type pixel circuits 20 are located in the first display area R1 , and a plurality of second type pixel circuits 20 are distributed in a plurality of between the pixel circuits 10 of the first type.
  • At least one pixel circuit 10 of the first type of the plurality of pixel circuits 10 of the first type is connected to at least one of the first area light-emitting elements 30 of the plurality of first area light-emitting elements 30, and at least one pixel circuit of the first type
  • the orthographic projection of 10 on the base substrate BS at least partially overlaps with the orthographic projection of the at least one first region light-emitting element 30 on the base substrate BS; at least one of the plurality of pixel circuits 20 of the second type
  • the pixel circuit 20 is connected to at least one second area light emitting element 40 of the plurality of second area light emitting elements 40 through at least one conductive line of the plurality of conductive lines.
  • FIG. 6 is a schematic diagram of a light emitting element located in a second display area in a display panel according to an embodiment of the present disclosure.
  • 7 is a schematic diagram of a row of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • 8 is a schematic diagram of a row of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of two rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of multiple rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • 11 is a schematic diagram of multiple rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • 12 is a schematic diagram of a first transparent conductive pattern layer, a light-emitting element, and a pixel circuit in a display panel according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a second transparent conductive pattern layer, a light-emitting element, and a pixel circuit in a display panel according to an embodiment of the present disclosure.
  • 14 is a schematic diagram of a plurality of rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • 15 is a schematic diagram of conductive lines located in a first transparent conductive pattern layer connected to multiple rows of light-emitting elements located in a second display area in a display panel according to an embodiment of the present disclosure.
  • 16 is a schematic diagram of conductive lines in a second conductive pattern layer connected to multiple rows of light-emitting elements in a second display area in a display panel according to an embodiment of the present disclosure.
  • a row of light-emitting elements may refer to that pixel circuits connected to the row of light-emitting elements are all connected to the same gate line, but not limited thereto.
  • a row of pixel circuits may be connected to the same gate line as the row of pixel circuits, but is not limited thereto.
  • a row of pixel units may refer to that the pixel circuits connected to the row of pixel units are all connected to the same gate line, but it is not limited thereto.
  • the plurality of second-area light-emitting elements 40 include a plurality of first light-emitting elements 41 and a plurality of second light-emitting elements 42, and the first light-emitting elements 41
  • the second light-emitting element 42 is configured to emit light of the first color
  • the second light-emitting element 42 is configured to emit light of the second color.
  • the plurality of second-type pixel circuits 20 include a plurality of first pixel circuits 21 and a plurality of second pixel circuits 22, the plurality of conductive lines L1 include a plurality of first conductive lines La and a plurality of second conductive lines Lb, and the plurality of conductive lines L1 include a plurality of first conductive lines La and a plurality of second conductive lines Lb.
  • the first light-emitting elements 41 and the plurality of first pixel circuits 21 are connected by a plurality of first conductive lines La, and the plurality of second light-emitting elements 42 and the plurality of second pixel circuits 22 are connected by a plurality of second conductive lines Lb.
  • one first light-emitting element 41 and one first pixel circuit 21 are connected by a first conductive line La
  • one second light-emitting element 42 and one second pixel circuit 22 are connected by a second conductive line Lb.
  • the plurality of second-area light-emitting elements 40 further include a plurality of third light-emitting elements 43 configured to emit light of a third color
  • a plurality of second-type pixel circuits 20 further includes a plurality of third pixel circuits 23
  • a plurality of conductive lines L1 further includes a plurality of third conductive lines Lc
  • a plurality of third light-emitting elements 43 are connected with the plurality of third pixel circuits 23 through a plurality of third conductive lines Lc .
  • one third light-emitting element 43 is connected to one third pixel circuit 23 through a third conductive line Lc.
  • the plurality of second-area light-emitting elements 40 further include a plurality of fourth light-emitting elements 44 configured to emit light of a fourth color
  • a plurality of second-type pixel circuits 20 further includes a plurality of fourth pixel circuits 24, the plurality of conductive lines L1 further includes a plurality of fourth conductive lines Ld, and the plurality of fourth light-emitting elements 44 are connected with the plurality of fourth pixel circuits 24 through the plurality of fourth conductive lines Ld .
  • a fourth light-emitting element 44 is connected to a fourth pixel circuit 24 through a fourth conductive line Ld.
  • the first color light and the fourth color light are both green light, one of the second color light and the third color light is red light, and the other one is blue light.
  • the fourth light-emitting element 44 and the first light-emitting element 41 are arranged to emit the same color light.
  • the fourth light-emitting element 44 and the first light-emitting element 41 are configured to emit green light
  • one of the second light-emitting element 42 and the third light-emitting element 43 is configured to emit red light
  • the second light-emitting element 42 and the third light-emitting element 43 are configured to emit red light.
  • Another configuration is to emit blue light.
  • the embodiment of the present disclosure is described by taking the fourth light-emitting element 44 and the first light-emitting element 41 emitting green light, the second light-emitting element 42 emitting red light, and the third light-emitting element 43 emitting blue light as an example, in other embodiments , the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43 and the fourth light-emitting element 44 can also emit light of other colors, not limited to the three colors of red, green and blue.
  • the colors of the light emitted by the element 42, the third light emitting element 43 and the fourth light emitting element 44 may be determined as required.
  • the capacitance of the conductive lines varies greatly. Due to the different lengths of the conductive lines connecting the light-emitting elements located in the second display area, the difference in capacitance of the light-emitting elements emitting light of different colors varies.
  • the difference in capacitance of the conductive wire connected to the red light-emitting element is larger than the capacitance difference of the conductive wire connected to the blue light-emitting element, and the capacitance difference of the conductive wire connected to the green light-emitting element .
  • the capacitances of the conductive wires connected to the green-emitting light-emitting element are greatly different, the light-emitting time of the green-emitting light-emitting element is reduced, and the display panel has a brightness difference, resulting in poor display.
  • Stripes appear when the display panel is displayed. For example, purple stripes appear when the display panel is displayed. For example, vertical purple stripes appear when the display panel is displayed.
  • green light emitting elements are more defective than red light emitting elements, and red light emitting elements are more defective than blue light emitting elements.
  • the driving current for driving the light-emitting element that emits blue light is greater than the driving current for driving the light-emitting element that emits red light
  • the driving current for driving the light-emitting element that emits red light is greater than the driving current for driving the light-emitting element that emits green light. current.
  • the arrangement sequence of the second type of pixel circuits connected to the light-emitting elements emitting different colors of light is adjusted, so as to reduce or eliminate the problems caused by the large difference in the length of the conductive lines. Comes with poor display. That is, when designing the pixel circuit of the second type connected to the first light-emitting element, the length of the conductive lines and the difference in the length of the conductive lines are considered, for example, the order of G priority is adopted.
  • G priority means that the second type of pixel circuit connected to the green light-emitting element is preferentially arranged close to the second display area. In order to optimize the resistance difference between adjacent pixel units and improve product competitiveness.
  • the second display region R2 in at least one group of light-emitting elements 100 b , the second light-emitting element 42 , the first light-emitting element 41 , the second light-emitting element 41 , the second light-emitting element 41 , the The three light-emitting elements 43 and the fourth light-emitting element 44 are arranged in order in the first direction X (row direction). For example, as shown in FIGS.
  • the light emitting element 100b includes two types of light emitting element columns, the first type light emitting element column includes the first light emitting element 41 and the fourth light emitting element 44, and in the column direction, the A light-emitting element 41 and a fourth light-emitting element 44 are alternately arranged, the second-type light-emitting element column includes the second light-emitting element 42 and the third light-emitting element 43, and in the column direction, the second light-emitting element 42 and the third light-emitting element 43 Alternate arrangement.
  • the arrangement of the light-emitting elements in the first display region R1 may be the same as the arrangement of the light-emitting elements in the second display region R2, but is not limited thereto.
  • the arrangement of the light-emitting elements provided by the embodiments of the present disclosure is not limited to that shown in FIG. 6 , and other suitable arrangements may also be adopted as required.
  • the plurality of first pixel circuits 21 connected to the plurality of first light-emitting elements 41 are more connected than the plurality of second light-emitting elements 42
  • Each of the plurality of second pixel circuits 22 is closer to the second display region R2. That is, the setting position of the first pixel circuit 21 connected to the first light-emitting element 41 is adjusted so that the first pixel circuit 21 connected to the first light-emitting element 41 is closer to the second pixel circuit 21 than the other pixel circuits of the second type.
  • the difference in length of the first conductive lines La connected to the first light-emitting element 41 is reduced, so as to reduce or avoid poor display.
  • At least one group of light-emitting elements and at least one group of pixel circuits may refer to a row of light-emitting elements 100b passing through two regions, or may refer to a row of pixel units passing through two regions in, but not limited to.
  • the element A and the element B are adjacent, or the adjacent element A and the element B refer to the element A and the element B that do not have other elements A and B between them.
  • Other element B but may have other elements than element A and element B.
  • Element A and element B may be the same element or different elements.
  • a plurality of pixel circuits 10 of the first type are arranged between two adjacent pixel circuits 20 of the second type. at least one of.
  • two pixel circuits 10 of the first type are disposed between two adjacent pixel circuits 20 of the second type.
  • a plurality of first pixel circuits 21 connected to a plurality of first conductive lines La are arranged at intervals in a plurality of first type
  • the plurality of second pixel circuits 22 connected to the plurality of second conductive lines Lb are arranged in the plurality of pixel circuits 10 of the first type at intervals.
  • the plurality of first pixel circuits 21 connected to the plurality of first conductive lines La are smaller than those connected to the plurality of third conductive lines
  • Each of the plurality of third pixel circuits 23 connected to Lc is closer to the second display region R2.
  • the plurality of second pixel circuits 22 connected to the plurality of second conductive lines Lb and the plurality of third pixel circuits 23 connected to the plurality of third conductive lines Lc are alternately arranged.
  • the plurality of fourth pixel circuits 24 connected to the plurality of fourth conductive lines Ld are smaller than those connected to the plurality of second conductive lines
  • Each of the plurality of second pixel circuits 22 connected to Lb is closer to the second display region R2.
  • the fourth light-emitting element 44 and the first light-emitting element 41 emit light of the same color, so that the plurality of fourth pixel circuits 24 are also preferentially arranged, that is, the plurality of fourth pixel circuits 24 are closer to the second Display area settings.
  • the fourth light-emitting element 44 may not be provided, so that the fourth pixel circuit 24 does not need to be provided.
  • the pixels may be in the form of true RGB, but not limited thereto.
  • the plurality of fourth pixel circuits 24 connected to the plurality of fourth conductive lines Ld and the plurality of first pixel circuits 21 connected to the plurality of first conductive lines La are alternately arranged.
  • At least one of the first conductive line La, the second conductive line Lb, the third conductive line Lc, and the fourth conductive line Ld is made of a transparent conductive material.
  • the second display region R2 of the display panel has an axisymmetric shape with a first axis of symmetry X1 extending along the first direction X and a second axis of symmetry X2 extending along the second direction Y.
  • the plurality of conductive lines L1 are axisymmetric with respect to the first symmetry axis X1 and are axisymmetric with respect to the second symmetry axis X2.
  • FIG. 6 shows that the second display region R2 includes a first sub-region R21, a second sub-region R22, a third sub-region R23, and a fourth sub-region R24.
  • the first sub-region R21 and the second sub-region R22 are axis-symmetrical with respect to the second symmetry axis X2
  • the third sub-region R23 and the fourth sub-region R24 are axis-symmetrical with respect to the second symmetry axis X2
  • the first sub-region R21 and The third sub-region R23 is axisymmetric with respect to the first symmetry axis X1
  • the second sub-region R22 and the fourth sub-region R24 are axisymmetric with respect to the first symmetry axis X1.
  • the plurality of second area light-emitting elements 40 are axisymmetric with respect to the first symmetry axis X1 and are axisymmetric with respect to the second symmetry axis X2.
  • FIG. 6 shows the center CT of the second display area R2.
  • the display panel includes a first transparent conductive pattern layer LY1 and a second transparent conductive pattern layer LY2, and at least one first conductive line La among the plurality of first conductive lines La is located in the second transparent conductive pattern In the layer LY2, at least one second conductive line among the plurality of second conductive lines Lb is located in the first transparent conductive pattern layer LY1.
  • the display panel provided by the embodiments of the present disclosure includes only two transparent conductive pattern layers for forming conductive lines, and reduces the number of masks compared to a display panel including three transparent conductive pattern layers for forming conductive lines , which is beneficial to the manufacture of the display panel, to reduce the thickness of the display panel, and to improve the reliability of the display panel.
  • FIG. 15 and FIG. 16 are described by taking as an example that the plurality of first conductive lines La are located in the second transparent conductive pattern layer LY2 and the plurality of second conductive lines Lb are located in the first transparent conductive pattern layer LY1 .
  • a plurality of first conductive lines La are located between adjacent two groups of light-emitting elements, so as to facilitate the connection between the light-emitting elements in each row.
  • Arrangement of the first conductive line La may be referred to as lateral conductive lines.
  • the lateral conductive lines extend in the first direction X from the second display area R2 to the first display area.
  • the multiple first conductive lines La are located between the adjacent two groups of light-emitting elements may mean that the multiple first conductive lines La are located between the centerlines of the adjacent two groups of light-emitting elements.
  • the centerline of each group of light-emitting elements extends along the first direction X.
  • the centerlines of the adjacent two groups of light-emitting elements are arranged along the second direction Y.
  • the first conductive line La and the fourth conductive line Ld are lateral conductive lines.
  • At least one second conductive line Lb near the center of the second display area R2 is in the second direction Y
  • At least two groups of light-emitting elements are spanned.
  • At least one second conductive line Lb near the center of the second display area R2 is in the second direction Y It extends from the second display area R2 to the first display area R1.
  • At least one third conductive line Lc near the center of the second display region R2 and at least one second conductive line Lb near the center of the second display region R2 Use longitudinal conductive thread.
  • the first conductive line La is a conductive line with an integral structure
  • the second conductive line Lb is a conductive line with an integral structure
  • a part of the third conductive lines Lc in the plurality of third conductive lines Lc is located in the first transparent conductive pattern layer LY1, and another part of the third conductive lines Lc in the plurality of third conductive lines Lc is located in the second transparent conductive pattern layer LY2.
  • At least one third conductive line Lc near the center of the second display area R2 is in the second direction Y
  • At least two groups of light-emitting elements are spanned.
  • At least one third conductive line Lc near the center of the second display area R2 is in the second direction Y It extends from the second display region R2 to the first display region R1, and the conductive lines in this form can be called vertical conductive lines.
  • the vertical conductive lines extend from the second display region R2 to the first display region R1 in the second direction Y.
  • the first conductive line La connected to the group of light-emitting elements is located in the On the first side of the group of light-emitting elements, the second conductive line Lb and the third conductive line Lc connected to the group of light-emitting elements are located on the second side of the group of light-emitting elements, and the first side and the second side are the light-emitting elements of the group of light-emitting elements. opposite sides.
  • the first conductive line La and the fourth conductive line Ld connected to the group of light-emitting elements are located on the first side of the group of light-emitting elements
  • the second conductive line Lb and the third conductive line connected to the group of light-emitting elements Lc is located on the second side of the group of light-emitting elements, and the first side and the second side are opposite sides of the group of light-emitting elements.
  • the first side and the second side of a group of light-emitting elements are the upper side and the lower side of the group of light-emitting elements, respectively.
  • the third conductive line Lc is a conductive line with an integrated structure.
  • the fourth conductive line Ld is a conductive line with an integrated structure.
  • each conductive line L1 is a conductive line with an integrated structure, which is formed by a layer of conductive film, and does not need to be formed in sections.
  • At least one group of the plurality of groups of pixel circuits includes dummy pixel circuits 200 , and the dummy pixel circuits 200 are located at two positions in the first direction X.
  • the pixel circuits 20 of the second type at least one of the second conductive line Lb near the center of the second display region R2 and the third conductive line Lc near the center of the second display region R2 is positive on the base substrate The projection overlaps the orthographic projection of the dummy pixel circuit on the base substrate.
  • the dummy pixel circuit 200 is not connected to any light-emitting element.
  • the dummy pixel circuit 200 is not connected to the conductive line L1.
  • the dummy pixel circuit 200 may be the second type of pixel circuit, but not connected to the conductive line L1. That is, a part, for example, several columns, may be selected from the pixel circuits of the second type as the dummy pixel circuit columns.
  • FIGS. 9 to 12 illustrate longitudinal conductive lines including a second conductive line Lb0 near the center of the second display area and a third conductive line Lc0 near the center of the second display area.
  • the second conductive line Lb0 and the third conductive line Lc0 are located in the first transparent conductive pattern layer LY1.
  • the second conductive line Lb near the center of the second display area R2 and the third conductive line near the center of the second display area Lc includes a first part P1, a second part P2, a third part P3, and a fourth part P4 connected in sequence, the second part P2 and the fourth part P4 extend along the first direction X, the first part P1 and the third part P3 along the The second direction Y extends.
  • the orthographic projection of the third portion P3 on the base substrate overlaps with the orthographic projection of the dummy pixel circuit 200 on the base substrate .
  • the fourth part P4 and the second part P2 are located on both sides of the third part P3 .
  • the orthographic projection of the portion of the first conductive line La extending along the first direction X on the base substrate and the second conductive line do not overlap, but are not limited thereto.
  • the orthographic projections of the portion of the conductive line L1 extending along the first direction X on the base substrate may also overlap.
  • the orthographic projections of the portions of the conductive lines L1 extending along the first direction X on the base substrate do not overlap.
  • the second conductive line Lb0 and the third conductive line Lc0 are located in the same layer, and both are located in the first transparent conductive pattern layer LY1 , and the part of the second conductive line Lb0 located in the second display area R2 (th The orthographic projection of a portion of P1) on the base substrate overlaps with the orthographic projection of the conductive lines (lateral conductive lines) located on the second transparent conductive pattern layer LY2 on the base substrate.
  • the orthographic projection of the portion of the second conductive line Lb0 located in the second display region R2 (the first portion P1 ) on the base substrate is the same as the portion of the conductive line located in the second transparent conductive pattern layer LY2 extending in the direction X.
  • the orthographic projections on the base substrate overlap.
  • the orthographic projection of the part of the second conductive line Lb0 located in the second display area R2 (the first part P1 ) on the base substrate is the same as that of the lateral conductive line (the conductive line located in the second transparent conductive pattern layer LY2 ) on the base substrate Orthographic overlap.
  • the orthographic projection of the part of the third conductive line Lc0 located in the second display region R2 (the first part P1 ) on the base substrate and the conductive line located in the second transparent conductive pattern layer LY2 overlap.
  • the orthographic projection of the portion of the third conductive line Lc0 located in the second display region R2 (the first portion P1 ) on the base substrate is the same as the portion of the conductive line located in the second transparent conductive pattern layer LY2 extending in the direction X.
  • the orthographic projections on the base substrate overlap.
  • the fourth light emitting element 44 and the first light emitting element 41 are configured to emit green light, and one of the second light emitting element 42 and the third light emitting element 43 is configured to emit red light, The other of the second light emitting element 42 and the third light emitting element 43 is configured to emit blue light.
  • a group of light-emitting elements closest to the first symmetry axis X1 is called the first row of light-emitting elements, from the bottom to the top are the light-emitting elements in the second row to the Nth row.
  • the group of light-emitting elements in at least one group of light-emitting elements (as shown in FIG. 7 , the light-emitting elements in the second row, the light-emitting elements in row r2 ), the light-emitting elements near the center CT of the second display area R2 and the light-emitting elements located in the second transparent conductive pattern layer
  • the conductive lines of LY2 are connected, and the light-emitting elements near the edge of the second display region R2 are connected to the conductive lines of the first transparent conductive pattern layer LY1.
  • the group of light-emitting elements can be connected by using transverse conductive lines.
  • the above-mentioned light-emitting elements close to the center of the second display area R2 include the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43 and the fourth light-emitting element 44, that is, the light-emitting color of the light-emitting element is not distinguished, as long as the light-emitting element Near the center of the second display region R2, it is connected to the conductive lines located in the second transparent conductive pattern layer LY2.
  • the above-mentioned light-emitting elements near the edge of the second display region R2 include the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43 and the fourth light-emitting element 44, that is, the light-emitting colors of the light-emitting elements are not distinguished, as long as The light-emitting element is close to the edge of the second display region R2, and is connected to the conductive line located in the first transparent conductive pattern layer LY1.
  • the light emitting elements close to the center CT of the second display region R2 can also be regarded as light emitting elements close to the second symmetry axis X2 of the second display region R2.
  • the light-emitting elements close to the center CT of the second display area R2 may need to be connected with the vertical conductive lines (conductive lines Lb0 and Lc0), then in order to The vertical conductive lines located in the first transparent conductive pattern layer LY1 are provided with placement positions, and the light emitting elements near the center CT of the second display region R2 are connected to the conductive lines located in the second transparent conductive pattern layer LY2.
  • FIG. 9 shows the light-emitting elements in rows r1 to r5 in the first sub-region R21.
  • At least one group of light-emitting elements includes two sub-groups of light-emitting elements, that is, a first sub-group of light-emitting elements G01 and a second sub-group of light-emitting elements G02 , and the first sub-group of light-emitting elements G01 emits more light than the second sub-group
  • the element G02 is closer to the edge of the second display region R2, or the second sub-group of light-emitting elements G02 is closer to the center of the second display region R2 than the first sub-group of light-emitting elements G01.
  • the light-emitting elements in row r1 may be referred to as the first group of light-emitting elements G1, and the light-emitting elements in the first sub-group of light-emitting elements G01 (including the second light-emitting element 42 ).
  • the conductive lines L1 connected to the third light-emitting element 43) are located in the first transparent conductive pattern layer LY1, and are connected to the light-emitting elements (including the first light-emitting element 41 and the fourth light-emitting element 44) in the first subgroup of light-emitting elements G01
  • the conductive lines L1 are all located in the second transparent conductive pattern layer LY2;
  • the conductive lines L1 connected to the light-emitting elements (including the second light-emitting element 42 and the third light-emitting element 43) in the second subgroup of light-emitting elements G02 are all located in the first transparent conductive pattern layer LY2;
  • the light-emitting elements in row r2 may also be referred to as the second group of light-emitting elements G2, the first group of light-emitting elements G1 is closer to the second display than the second group of light-emitting elements G2
  • the center CT of the region, or the first group of light-emitting elements G1 is closer to the first symmetry axis X1 than the second group of light-emitting elements G2.
  • the conductive lines L1 connected to the light-emitting elements (including the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43, and the fourth light-emitting element 44) in the first subset of light-emitting elements G01 are located in the first transparent conductive line.
  • the pattern layer LY1, and the conductive lines L1 connected to the light-emitting elements (including the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43, and the fourth light-emitting element 44) in the second subgroup of light-emitting elements G02 are all on the second transparent conductive pattern layer LY2.
  • FIG. 9 is a schematic diagram of the conductive line in FIG. 8 plus the conductive line in FIG. 7 and the longitudinal conductive line. There are many light-emitting elements near the center of the second display area, involving vertical conductive lines.
  • the conductive lines located in the second transparent conductive pattern layer LY2 are used, and the other conductive lines located in the first transparent conductive pattern layer LY1 are used.
  • the conductive lines located in the second transparent conductive pattern layer LY2 are distributed on both sides of the group of light-emitting elements; for the conductive lines L1 connected with the second light-emitting element 42 and the third light-emitting element 43 (B pixel unit and R pixel unit) , start from the edge of the second display area R2, and connect with the conductive line ITO1 located in the first transparent conductive pattern layer LY1 until the horizontal conductive line is used up.
  • the pixel circuit of the second type connected to the first light-emitting element 41 and the fourth light-emitting element 44 is more
  • the second type of pixel circuit is closer to the second display area R2, only the second light-emitting element 42 and the third light-emitting element 43 remain in the center of the second display area R2, and the second light-emitting element 42 is close to the center of the second display area
  • the third light-emitting element 43 is connected to the second-type pixel circuit at the farthest end by using a vertical conductive line, which conforms to the gradient law.
  • FIG. 17 is a schematic diagram of a plurality of rows of light-emitting elements located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a first transparent conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of a second transparent conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a second transparent conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of a first transparent conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • a part of the first conductive lines La in the plurality of first conductive lines La are located in the second transparent conductive pattern layer LY2, and the plurality of first conductive lines La are located in the second transparent conductive pattern layer LY2.
  • Another part of the first conductive line La in the conductive line La is located in the first transparent conductive pattern layer LY1.
  • a part of the second conductive lines Lb are located in the second transparent conductive pattern layer LY2, and the plurality of second conductive lines Lb are located in the second transparent conductive pattern layer LY2.
  • Another part of the second conductive lines in the conductive lines Lb is located in the first transparent conductive pattern layer LY1.
  • a part of the fourth conductive lines Ld among the plurality of fourth conductive lines Ld are located in the second transparent conductive pattern layer LY2, and the plurality of fourth conductive lines Ld are located in the second transparent conductive pattern layer LY2.
  • Another part of the fourth conductive line Ld among the four conductive lines Ld is located in the first transparent conductive pattern layer LY1.
  • some of the first conductive lines La and the fourth conductive lines Ld close to the second symmetry axis X2 are located in the second transparent conductive pattern layer LY2, and are far away from the second transparent conductive pattern layer LY2.
  • Some of the first conductive lines La and the fourth conductive lines Ld of the second symmetry axis X2 are located in the first transparent conductive pattern layer LY1.
  • the fourth part P4 and the second part P2 are located on the same side of the third part P3 .
  • 19 and 20 show the conductive lines L1 located in the first transparent conductive pattern layer LY1 and the conductive lines L1 located in the second transparent conductive pattern layer LY2.
  • the second light emitting element and the third light emitting element near the center of the second display area are connected to the second type of pixel circuit by conductive lines spanning at least two groups of light emitting elements in the second direction Y.
  • the conductive lines spanning the at least two groups of light-emitting elements in the second direction Y are located in the first transparent conductive pattern layer LY1.
  • the pixel circuit adopts a vertical 2-in-1 design, that is, two pixel circuits of the first type are arranged between adjacent pixel circuits of the second type, and the pixel circuits of the extra column are the first type of pixel circuits. Two types of pixel circuits.
  • the first light-emitting element and the fourth light-emitting element Take the first light-emitting element and the fourth light-emitting element to emit green light, the second light-emitting element to emit red light, and the third light-emitting element to emit blue light as an example.
  • the pixel units in the 28th to 40th columns preferentially use the second transparent conductive pattern layer LY2, that is, 19 , 20 rows of light-emitting elements preferentially use the conductive lines located in the second transparent conductive pattern layer LY2, and the 18th row and below use the conductive lines located in the first transparent conductive pattern layer LY1 after the space of the conductive lines in the second transparent conductive pattern layer LY2 is insufficient.
  • the conductive lines are connected to the pixel units in the 1st to 27th columns; in the light-emitting elements in the 1st to 8th rows, affected by the line width and line spacing of the conductive lines of the first transparent conductive pattern layer LY1 and the second transparent conductive pattern layer LY2,
  • the connection method of the horizontal conductive lines is no longer sufficient for the connection of pixel units.
  • the conductive lines located in the second transparent conductive pattern layer LY2 are preferentially used to connect the 28th to 40th columns of G pixel units, and the remaining 6 columns of R/G pixel units.
  • Columns 1 to 27 of the light-emitting elements are sequentially connected using conductive lines located in the first transparent conductive pattern layer LY1 and the second transparent conductive pattern layer LY2.
  • the R/B pixel units in 6 columns and 8 rows are connected to the pixel circuits by conductive lines, a column of dummy pixel circuits are separated from each other.
  • the conductive lines of the R/B pixel unit, and the routing methods of the conductive lines are shown in Figure 21.
  • the nearest trace capacitance of the G pixel unit is 49.24fF
  • the farthest trace capacitance is 320.87fF
  • the ratio of the maximum value to the minimum value is 6.51
  • the closest trace capacitance of the R pixel unit is 6.51.
  • the trace capacitance is 186.56fF
  • the farthest trace capacitance is 730.65fF
  • the nearest trace capacitance of the B pixel unit is 201.56fF
  • the farthest trace capacitance is 759.08fF.
  • the R/B pixel unit Due to the G priority setting, the R/B pixel unit The lengths of the conductive lines of each are greater than the lengths of the conductive lines of the G pixel unit, so the difference between the maximum value and the minimum value of the capacitance of the R pixel unit and the B pixel unit can be reduced. Meanwhile, the ratios of the maximum value and the minimum value of the R and B pixel units are 3.9 and 3.7, respectively. If the conductive lines of the R/G/B pixel units are connected in sequence, and the G-priority method is not used, the maximum and minimum ratios of the conductive lines are 14.2, 12, and 10, respectively.
  • the display panel provided by the embodiment of the present disclosure adopts the setting method of G priority, which can not only reduce the difference between the maximum value and the minimum value of the capacitance of the R/G/B pixel unit, but also facilitate algorithm compensation and improve the display effect.
  • the display panel provided by the embodiments of the present disclosure only uses two transparent conductive pattern layers to form conductive lines, which can better reduce production costs compared with the original three transparent conductive pattern layers to form conductive lines. .
  • the conductive lines with relatively light colors are the conductive lines located in the second transparent conductive pattern layer LY2
  • the conductive lines with relatively dark colors are the conductive lines located in the first transparent conductive pattern layer LY1 Wire.
  • FIG. 22 is a schematic diagram of a layer structure of a display panel according to an embodiment of the disclosure.
  • the pixel circuit 100a is located on the base substrate BS
  • the insulating layer 700 is located on the pixel circuit 100a
  • the first transparent conductive pattern layer LY1 is located on the insulating layer 700
  • the insulating layer 701 is located on the first transparent conductive pattern layer LY1
  • the second transparent conductive pattern layer LY2 is located on the insulating layer 701
  • the insulating layer 702 is located on the second transparent conductive pattern layer LY2
  • the light-emitting element 100 b is located on the insulating layer 702 .
  • the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL between the first electrode E1 and the second electrode E2.
  • the first electrode E1 is closer to the base substrate BS than the second electrode E2.
  • the number of light-emitting elements is not limited to those shown in the figures, and can be set as required.
  • FIG. 23 is a schematic diagram of a layer structure of a display panel according to an embodiment of the disclosure. Compared with the display panel shown in FIG. 22 , the positions of the second transparent conductive pattern layer LY2 and the first transparent conductive pattern layer LY1 are reversed.
  • the first transparent conductive pattern layer LY1 is closer to the base substrate BS than the second transparent conductive pattern layer LY2.
  • the second transparent conductive pattern layer LY2 is closer to the base substrate BS than the first transparent conductive pattern layer LY1 .
  • 22 and 23 illustrate the stacking of the film layers, and do not illustrate the connection relationship between the components of the respective layer structures.
  • FIG. 24 is a schematic diagram of a first pixel unit in a display panel according to an embodiment of the disclosure.
  • FIG. 24 shows the first pixel unit 101 .
  • FIG. 25 is a schematic diagram of a second pixel unit in a display panel according to an embodiment of the disclosure.
  • FIG. 24 shows the first pixel unit 102 .
  • a buffer layer BL is provided on the base substrate BS, an isolation layer BR is provided on the buffer layer BL, an active layer LY0 is provided on the isolation layer BR, an insulating layer ISL1 is provided on the active layer LY0, and an insulating layer is provided on the insulating layer BR.
  • a conductive layer LYa is provided on the ISL1, an insulating layer ISL2 is provided on the conductive layer LYa, a conductive layer LYb is provided on the insulating layer ISL2, an insulating layer ISL3 is provided on the conductive layer LYb, a conductive layer LYc is provided on the insulating layer ISL3, and the conductive layer LYc is provided Including the connecting electrode CE01, the connecting electrode CE01 is connected with the second pole T52 of the light-emitting control transistor T5 through the via hole V8 passing through the insulating layer ISL1, the insulating layer ISL2 and the insulating layer ISL3, and the insulating layer ISL4 and the insulating layer ISL5 are provided on the conductive layer LYc , a conductive layer LYd is provided on the insulating layer ISL4 and the insulating layer ISL5, the conductive layer LYd includes a connecting electrode CE02, the connecting electrode CE02 is connected to the connecting electrode CE01 through the via
  • the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL between the first electrode E1 and the second electrode E2.
  • the connection element CE0 includes a connection electrode CE01 and a connection electrode CE02.
  • FIG. 24 also shows the second pole T52 of the light emission control transistor T5, the light emission control line EML, the first pole T51 of the light emission control transistor T5, the first plate Ca of the storage capacitor, the second plate Cb of the storage capacitor, the light emission
  • the second pole T42 of the control transistor T4 the gate line GT, the data line DT, the reset control signal line RST, and the initialization signal line INT are controlled.
  • the pixel definition layer PDL has an opening OPN2 configured to define a light emitting area (light exit area, effective light emitting area) of the pixel unit.
  • the spacer PS is configured to support the fine metal mask when the light emitting functional layer FL is formed.
  • the opening OPN2 is the light emitting area of the pixel unit.
  • the light emitting functional layer FL is located on the first electrode E1 of the light emitting element 100b, and the second electrode E2 of the light emitting element 100b is located on the light emitting functional layer FL.
  • a packaging layer CPS is provided on the light emitting element 100b.
  • the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2 and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers, and the second encapsulation layer CPS2 is an organic material layer.
  • the first electrode E1 is the anode of the light-emitting element 100b
  • the second electrode E2 is the cathode of the light-emitting element 100b, but it is not limited thereto.
  • FIG. 25 shows a conductive line L1, one end of the conductive line L1 is connected to the second region light-emitting element 40 in the second display region R2, and the other end of the conductive line L1 is connected to the pixel circuit.
  • the plurality of conductive lines L1 are located between the plurality of light emitting elements 100 b and the plurality of pixel circuits 100 a in the direction perpendicular to the main surface of the base substrate BS. 24 and 25 do not show the entire structure of the pixel circuit 100a.
  • FIGS. 24 and 25 illustrate by taking an example that the insulating layer ISL4 includes the insulating sub-layer ISL41 and the insulating sub-layer ISL42.
  • FIG. 26 is a cross-sectional view of a display panel.
  • FIG. 26 is a schematic diagram of an exposure process when patterning the transparent conductive film in the process of forming the conductive line L1.
  • FIG. 27 is a schematic diagram of forming a photoresist pattern.
  • FIG. 28 is a schematic diagram of forming conductive lines.
  • the first conductive element 111 is located on the base substrate BS; the first planarization layer 121 is located on the first conductive element 111; the second conductive element 112 is located on the first planarization layer 121,
  • the via hole V0 of a planarization layer 121 is connected to the first conductive element 111 ; the second planarization layer 122 is located on the second conductive element 112 .
  • forming the conductive line L1 includes forming a transparent conductive film F1 on the second planarization layer 122 , forming a photoresist film 201 on the transparent conductive film F1 , and using the mask 202 as a mask to cover the photoresist The film 201 is exposed, so that the photoresist film 201 forms a photoresist retaining portion 2011 and a photoresist to-be-removed portion 2012 .
  • a development process is performed after the exposure process. In the development process, the photoresist to be removed portion 2012 is removed to form a photoresist pattern 201a. As shown in FIG.
  • the transparent conductive film F1 is etched by using the photoresist pattern 201a as a mask to form conductive lines L1.
  • the conductive line L1 includes a plurality of pieces.
  • An insulating layer is arranged between adjacent transparent conductive layers.
  • the photoresist of the transparent conductive film is exposed and thinned, which leads to disconnection or thinning of the conductive lines after developing and etching, resulting in poor display of dark spots.
  • Optical microscope confirms that the position where the conductive wire is broken and thinned is the position where the conductive wire crosses the via hole V0 of the first planarizing layer 121 , and further by focusing the ion beam (Focused ion beam) on the cross section of the via hole V0 of the first planarizing layer 121.
  • the conductive line that crosses the via V0 has a bowl-shaped part of the second conductive element 112 below the position where the conductive line is broken or the conductive line is thinned. Therefore, as shown in FIG. 26, it is determined that The reason for the disconnection and poor thinning of the conductive line is that in the exposure process, the second conductive element 112 reflects light and condenses the light to the surface located above the bowl-shaped portion of the second conductive element 112 (corresponding to the position of the via hole V0 ).
  • the photoresist retaining portion 2011 makes this part of the photoresist exposed or partially exposed, and washed away after developing, so that the conductive lines formed after etching the transparent conductive film with the photoresist pattern 201a as a mask are broken and changed. thin. As shown in FIG. 26 to FIG. 28 , the photoresist retaining portion 2011 located in the middle position is irradiated by the partially reflected light, so that the conductive line below it becomes thinner.
  • the first conductive element 111 in FIGS. 26 to 28 may be the connection electrode CE01 in FIGS. 24 and 25
  • the second conductive element 112 may be the connection electrode CE02 in FIGS. 24 and 25 .
  • FIG. 29 is a schematic diagram of a pixel circuit of a first type in a first display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 30 is a schematic diagram of a portion of the film layer in FIG. 29 .
  • FIG. 31 is a schematic diagram of some film layers in a pixel circuit of a first type in a first display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 32 is a schematic diagram of a second type of pixel circuit in a first display area of a display panel provided by an embodiment of the present disclosure.
  • FIG. 33 is a schematic diagram of a portion of the film layer in FIG. 32 .
  • FIG. 34 is a schematic diagram of some film layers in the second type pixel circuit in the first display area of the display panel according to the embodiment of the present disclosure.
  • FIG. 35 is a schematic diagram of a pixel circuit in a region with vertical conductive lines in a first display region of a display panel according to an embodiment of the present disclosure.
  • FIG. 36 is a schematic diagram of some of the layers of FIG. 35 .
  • FIG. 37 is a schematic diagram of a part of a film layer in a region with vertical conductive lines in a first display area of a display panel according to an embodiment of the present disclosure.
  • connection electrode CE02 is not provided in the dummy pixel circuit 200, and further, the dummy pixel circuit 200 does not have the via hole VH penetrating the insulating layer ISL4. In some embodiments, the dummy pixel circuit 200 does not have the connection electrode CE02, but is not limited thereto. In other embodiments, the dummy pixel circuit 200 has a connection electrode CE02, and the connection electrode CE02 and the connection electrode CE01 are not connected through a via hole. That is, in the dummy pixel circuit 200, the connection electrode CE02 and the connection electrode CE01 are insulated from each other, and no via hole is provided between the connection electrode CE02 and the connection electrode CE01.
  • the display panel further includes a planarization layer PLN, and the insulating layer ISL4 in FIGS.
  • the chemical layer PLN is located between the first electrode E1 of the light-emitting element and the pixel circuit 100a.
  • the orthographic projection of the via hole VH in the planarization layer PLN on the base substrate does not overlap with the orthographic projection of the dummy pixel circuit 200 on the base substrate.
  • the thinning or disconnection of the portion of the conductive line L1 located in the dummy pixel circuit 200 can be avoided.
  • the via hole VH is not provided at the position of the dotted frame R3, and the connection electrode CE02 is not provided.
  • the data line DTm of the dummy pixel circuit 200 is disconnected.
  • the data line DTm is disconnected at the position of the dotted frame R4 to form a plurality of disconnected parts.
  • the data line DTm is not connected to the pixel circuit.
  • the via hole VH is not provided at the position of the dotted frame R5, and the connection electrode CE02 is not provided.
  • the display panel provided by some embodiments of the present disclosure includes the fourth light-emitting element, and in other embodiments, the display panel may not include the fourth light-emitting element.
  • the fourth light-emitting element in the figure and the pixel circuit connected to the fourth light-emitting element can be removed, and the positions of other components can be adjusted accordingly.
  • the transistors in the pixel circuits of the embodiments of the present disclosure are all thin film transistors.
  • the conductive layer LYa, the conductive layer LYb, the conductive layer LYc, and the conductive layer LYd are all made of metal materials.
  • the conductive layer LYa and the conductive layer LYb are formed of metal materials such as nickel and aluminum, but are not limited thereto.
  • the conductive layer LYc and the conductive layer LYd are formed of materials such as titanium, aluminum, etc., but are not limited thereto.
  • the conductive layer LYc and the conductive layer LYd are structures formed by three sub-layers of Ti/AL/Ti, respectively, but not limited thereto.
  • a glass substrate or a polyimide substrate can be used as the base substrate, but it is not limited thereto, and can be selected as required.
  • the buffer layer BL, the isolation layer BR, the insulating layer ISL1, the insulating layer ISL2, the insulating layer ISL3, the insulating layer ISL4, and the insulating layer ISL5 are all made of insulating materials.
  • the materials of the insulating layer ISL4 and the insulating layer ISL5 include organic insulating materials, and the organic insulating materials include resins, but are not limited thereto.
  • the materials of the first electrode E1 and the second electrode E2 of the light-emitting element can be selected as required.
  • the first electrode E1 may be at least one of transparent conductive metal oxide and silver, but not limited thereto.
  • the first electrode E1 may adopt a structure in which three sub-layers of ITO-Ag-ITO are provided.
  • the second electrode E2 may be a metal with low work function, and at least one of magnesium and silver may be used, but it is not limited thereto.
  • both the first transparent conductive pattern layer LY1 and the second transparent conductive pattern layer LY2 are made of transparent conductive metal oxide, and the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto.
  • ITO indium tin oxide
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display panels.
  • the sensor SS is located on one side of the display panel DS and located in the second display area R2.
  • the ambient light can be sensed by the sensor SS through the second display area R2.
  • the side of the display panel on which the sensor SS is not provided is the display side, and an image can be displayed.
  • the sensor includes a photosensitive sensor, and the photosensitive sensor is located at one side of the display panel.
  • the second display region R2 may be a rectangle, and the area of the orthographic projection of the sensor SS on the base substrate BS may be less than or equal to the area of the inscribed circle of the second display region R2. That is, the size of the area where the sensor SS is located may be smaller than or equal to the size of the inscribed circle of the second display area R2.
  • the size of the area where the sensor SS is located is equal to the size of the inscribed circle of the second display area R2, that is, the shape of the area where the sensor SS is located may be a circle.
  • the area where the sensor SS is located may also be called a light-transmitting hole .
  • the second display area R2 may also be other shapes than rectangles, such as circles or ellipses.
  • the display device is a full-screen display device with an under-screen camera.
  • the display device includes an OLED or a product including an OLED.
  • the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc., which contain the above-mentioned display panel.
  • the pixel circuit (including the pixel circuit 10 of the first type and the pixel circuit 20 of the second type) and the first area light-emitting element 30 have the same pitch.
  • a typical width is about 30 micrometers ( ⁇ m) to 32 ⁇ m, and a length is about 60 ⁇ m to 65 ⁇ m.
  • the gate line extending direction also called lateral direction
  • compresses each pixel circuit so that the width of the pixel circuit in the first direction is smaller than the width of the light-emitting element 30 in the first region
  • X extends the first-area light-emitting element 30 , so that the width of the first-area light-emitting element 30 in the first direction X is larger than the width of the first-area light-emitting element 30 .
  • the width of each pixel circuit and the width of the first region light emitting element 30 may be different by about 4 ⁇ m.
  • FIG. 40 shows the structural layout of the pixel circuit before and after compression.
  • the pixel circuit may include a drive structure and a connection element CE0 for connecting to the first pole (anode) of the light emitting element, the size of which may represent the size of the pixel circuit.
  • the dimensions of the pixel circuit and the light-emitting element before compression are both 1-100 ⁇ m in width and 2-100 ⁇ m in height. The size of the compressed light-emitting element can be unchanged compared with that before compression.
  • the size of the second area light emitting element 40 may be equal to or smaller than the size of the first area light emitting element 20 .
  • the height of the compressed pixel circuit remains unchanged, but the width is narrowed by 1-20 ⁇ m. In this way, every few columns of compressed pixel circuits will add one or more columns of compressed pixel circuits, and the entire screen adopts this design to achieve full-screen compression.
  • the extra columns can be selected to connect the second area light-emitting elements 40 in the second display region R2 to control the second area light-emitting elements 40 to emit light.
  • multiple columns of pixel circuits near the periphery of the second display region R2 are selected as the second type of pixel circuits 20 to be connected to the second region light-emitting elements 40 .
  • normal display can be achieved without changing the resolution of the display panel. That is, the existing space of the display panel is fully utilized to realize normal display.
  • the effect achieved by compressing the size of the pixel circuit is that the number of light-emitting elements (including the first-region light-emitting element 30 and the second light-emitting element 40 ) remains unchanged, and further, compared with before compression, the display effect is not significantly different, and the display panel display effect is better.
  • FIG. 41 is a schematic diagram of a pixel unit in a display panel.
  • FIG. 40 shows a pixel circuit of a pixel unit of a display panel.
  • the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b.
  • the pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor T1 and one storage capacitor Cst.
  • the six switching transistors are respectively a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7.
  • the light-emitting element 100b includes a first electrode E1 and a second electrode E2 and a light-emitting functional layer between the first electrode E1 and the second electrode E2.
  • the first electrode E1 is an anode
  • the second electrode E2 is a cathode.
  • the threshold compensation transistor T3 and the first reset transistor T6 use a dual-gate thin film transistor (Thin Film Transistor, TFT) to reduce leakage.
  • TFT Thin Film Transistor
  • the display panel includes gate lines GT, data lines DT, first power supply lines PL1, second power supply lines PL2, light emission control signal lines EML, initialization signal lines INT, reset control signal lines RST, and the like.
  • the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2.
  • the first power supply line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100
  • the second power supply line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100
  • the first voltage signal VDD is greater than the second voltage signal VSS.
  • the gate line GT is configured to provide a scan signal SCAN to the pixel unit 100
  • the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100
  • the light emission control signal line EML is configured to provide the pixel unit 100 with a light emission control signal EM
  • the first reset control signal line RST1 is configured to provide the pixel unit 100 with the first reset control signal RESET1
  • the second reset control signal line RST2 is configured to provide the pixel unit 100 with the scan signal SCAN.
  • the second reset control signal line RST2 may be connected to the gate line GT to be input with the scan signal SCAN.
  • the second reset control signal line RST2 may also be input with the second reset control signal RESET2.
  • the first initialization signal line INT1 is configured to provide the first initialization signal Vinit1 to the pixel unit 100 .
  • the second initialization signal line INT2 is configured to supply the pixel unit 100 with the second initialization signal Vinit2.
  • the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, for example, the magnitude of which may be between the first voltage signal VDD and the second voltage signal VSS, but is not limited thereto, for example, the first initialization signal Both Vinit1 and the second initialization signal Vinit2 may be less than or equal to the second voltage signal VSS.
  • the first initialization signal line INT1 and the second initialization signal line INT1 are connected, and both are configured to provide the initialization signal Vinit to the pixel unit 100 , that is, the first initialization signal line INT1 and the second initialization signal line INT2 Both are called initialization signal lines INT, the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, and both are Vinit.
  • the driving transistor T1 is electrically connected to the light-emitting element 100b, and outputs a driving current under the control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals to drive the light-emitting element 100b glow.
  • the light emitting element 100b includes an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel circuit 100a.
  • OLED organic light emitting diode
  • one pixel includes a plurality of pixel units.
  • a pixel may include a plurality of pixel units that emit light of different colors.
  • one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto.
  • the number of pixel units included in a pixel and the light-emitting condition of each pixel unit can be determined as required.
  • the gate T20 of the data writing transistor T2 is connected to the gate line GT
  • the first electrode T21 of the data writing transistor T2 is connected to the data line DT
  • the second electrode T22 of the data writing transistor T2 is connected to the data line DT.
  • the first pole T11 of the driving transistor T1 is connected.
  • the pixel circuit 100a further includes a threshold compensation transistor T3, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, and the first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1.
  • the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.
  • the display panel further includes an emission control signal line EML
  • the pixel circuit 100a further includes a first emission control transistor T4 and a second emission control transistor T5, and the gate T40 of the first emission control transistor T4 is connected to the emission control transistor T4.
  • the signal line EML is connected, the first pole T41 of the first light-emitting control transistor T4 is connected to the first power supply line PL1, and the second pole T42 of the first light-emitting control transistor T4 is connected to the first pole T11 of the driving transistor T1;
  • the gate T50 of the transistor T5 is connected to the light-emitting control signal line EML, the first electrode T51 of the second light-emitting control transistor T5 is connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second light-emitting control transistor T5 is connected to the light-emitting element.
  • the first electrode E1 of 100b is connected.
  • the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, and is configured to reset the gate of the driving transistor T1
  • the second reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b, It is configured to reset the first electrode E1 of the light-emitting element 100b.
  • the first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6.
  • the second initialization signal line INT2 is connected to the first electrode E1 of the light emitting element 100b through the second reset transistor T7.
  • first initialization signal line INT1 and the second initialization signal line INT2 are connected to receive the same initialization signal, but not limited thereto, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 are also Can be isolated from each other and configured to input signals separately.
  • the first pole T61 of the first reset transistor T6 is connected to the first initialization signal line INT1
  • the second pole T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1
  • the second reset transistor T62 is connected to the gate T10 of the driving transistor T1.
  • the first electrode T71 of the transistor T7 is connected to the second initialization signal line INT2
  • the second electrode T72 of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b.
  • the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1
  • the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.
  • the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit further includes a storage capacitor Cst, and the first plate Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1 , the second plate Cb of the storage capacitor Cst is connected to the first power line PL1.
  • the display panel further includes a second power supply line PL2, and the second power supply line PL2 is connected to the second electrode E2 of the light emitting element 100b.
  • FIG. 40 shows the first node N1, the second node N2, the third node N3 and the fourth node N4.
  • the above description takes a 7T1C pixel circuit as an example, and embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit.
  • the pixel circuit of the display panel may also have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
  • the display panel may also include pixel circuits with less than 7 transistors.
  • elements located on the same layer may be formed from the same film layer through the same patterning process.
  • elements located on the same layer may be located on a surface of the same element remote from the base substrate.
  • the patterning or patterning process may include only a photolithography process, or may include a photolithography process and an etching step, or may include other processes for forming predetermined patterns such as printing and inkjet.
  • the lithography process refers to the process of film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
  • Corresponding patterning processes may be selected according to the structures formed in the embodiments of the present disclosure.

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Abstract

提供一种显示面板和显示装置。该显示面板包括：衬底基板；多个发光元件，以及多个像素电路。多个像素电路包括多组像素电路，多组像素电路中的至少一组包括多个第一类型的像素电路和多个第二类型的像素电路，多个第二类型的像素电路间隔分布于多个第一类型的像素电路之间，多个第二类型的像素电路中的至少一个第二类型的像素电路与多个第二区域发光元件中的至少一个第二区域发光元件通过多条导电线中的至少一条导电线连接；多条导电线包括多条第一导电线和多条第二导电线，在至少一组发光元件和至少一组像素电路中，与多个第一发光元件相连的多个第一像素电路比与多个第二发光元件相连的多个第二像素电路中的每一个都更靠近第二显示区。

Description

显示面板和显示装置
相关申请的交叉引用
本专利申请要求于2021年3月12日递交的PCT专利申请第PCT/CN2021/080494号的优先权，在此全文引用上述PCT专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一实施例涉及一种显示面板和显示装置。
背景技术
随着显示技术的不断发展，有源矩阵型有机发光二极管(Active-Matrix Organic Light-Emitting Diode，AMOLED)显示技术因其自发光、广视角、高对比度、低功耗、高反应速度等优点已经在手机、平板电脑、数码相机等显示装置上得到越来越多地应用。
屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
本公开的至少一实施例涉及一种显示面板和显示装置。
本公开的至少一实施例提供一种显示面板，包括：衬底基板、多个发光元件、多个像素电路、以及多条导电线，所述衬底基板具有第一显示区和第二显示区，所述第一显示区位于所述第二显示区的至少一侧；所述多个发光元件位于所述第一显示区和所述第二显示区，所述多个发光元件包括多组发光元件，所述多组发光元件的每组中的发光元件沿第一方向排布，所述多组发光元件沿第二方向排布，所述多组发光元件中的至少一组包括多个第一区域发光元件和多个第二区域发光元件，所述多个第一区域发光元件位于所述第一显示区，所述多个第二区域发光元件位于所述第二显示区；所述多个像素电路位于所述第一显示区，所述多个像素电路包括多组像素电路，所述多组像素电路的每组中的像素电路沿所述第一方向排布，所述多组像素电路沿所述第二方向排布，所述多组像素电路中的至少一组包括多个第一类型的像素电路和多个第二类型的像素电路，所述多个第二类型的像素电路间隔分布于所述多个第一类型的像素电路之间，所述多个第一类型的像素电路中的至少一个第一类型的像素电路与所述多个第一区域发光元件中的至少一个第一区域发光元件连接，且所述至少一个第一类型的像素电路在所述衬底基板上的正投影与所述至少一个第一区域发光元件在所述衬底基板上的正投影至少 部分交叠；所述多个第二类型的像素电路中的至少一个第二类型的像素电路与所述多个第二区域发光元件中的至少一个第二区域发光元件通过多条导电线中的至少一条导电线连接；所述多个第二区域发光元件包括多个第一发光元件和多个第二发光元件，所述第一发光元件配置为发第一颜色光，所述第二发光元件配置为发第二颜色光，所述多个第二类型的像素电路包括多个第一像素电路和多个第二像素电路，所述多条导电线包括多条第一导电线和多条第二导电线，所述多个第一发光元件与所述多个第一像素电路通过所述多条第一导电线连接，所述多个第二发光元件与所述多个第二像素电路通过所述多条第二导电线连接，在所述至少一组发光元件和所述至少一组像素电路中，与所述多个第一发光元件相连的所述多个第一像素电路比与所述多个第二发光元件相连的所述多个第二像素电路中的每一个都更靠近所述第二显示区，所述显示面板包括第一透明导电图案层和第二透明导电图案层，所述多条第一导电线中的至少一条第一导电线位于所述第二透明导电图案层，所述多条第二导电线中的至少一条第二导电线位于所述第一透明导电图案层。
根据本公开的实施例提供显示面板，所述多条导电线在垂直于所述衬底基板的主表面的方向上位于所述多个发光元件和所述多个像素电路之间。
根据本公开的实施例提供显示面板，靠近所述第二显示区的中心的至少一条第二导电线在所述第二方向上跨过至少两组发光元件。
根据本公开的实施例提供显示面板，靠近所述第二显示区的中心的至少一条第二导电线在所述第二方向上由所述第二显示区延伸至所述第一显示区。
根据本公开的实施例提供显示面板，所述第一导电线为一体结构的导电线，所述第二导电线为一体结构的导电线。
根据本公开的实施例提供显示面板，所述多个第二区域发光元件还包括多个第三发光元件，所述第三发光元件配置为发第三颜色光，所述多个第二类型的像素电路还包括多个第三像素电路，所述多条导电线还包括多条第三导电线，所述多个第三发光元件与所述多个第三像素电路通过所述多条第三导电线相连，在所述至少一组发光元件和所述至少一组像素电路中，与所述多条第一导电线相连的所述多个第一像素电路比与所述多条第三导电线相连的所述多个第三像素电路中的每一个都更靠近所述第二显示区，所述多条第三导电线中的一部分第三导电线位于所述第一透明导电图案层中，所述多条第三导电线中的另一部分第三导电线位于所述第二透明导电图案层中。
根据本公开的实施例提供显示面板，靠近所述第二显示区的中心的至少一条第三导电线在所述第二方向上跨过至少两组发光元件。
根据本公开的实施例提供显示面板，靠近所述第二显示区的中心的至少一条第三导电线在所述第二方向上由所述第二显示区延伸至所述第一显示 区。
根据本公开的实施例提供显示面板，在所述至少一组发光元件和所述至少一组像素电路中，与该组发光元件相连的第一导电线位于该组发光元件的第一侧，与该组发光元件相连的第二导电线和第三导电线位于该组发光元件的第二侧，所述第一侧和所述第二侧为该组发光元件的相对的两侧。
根据本公开的实施例提供显示面板，所述多组像素电路中的至少一组包括虚设像素电路，所述虚设像素电路在所述第一方向上位于两个第二类型的像素电路之间，靠近所述第二显示区的中心的第二导电线和靠近所述第二显示区的中心的第三导电线至少之一在所述衬底基板上的正投影与所述虚设像素电路在所述衬底基板上的正投影交叠。
根据本公开的实施例提供显示面板，所述第三导电线为一体结构的导电线。
根据本公开的实施例提供显示面板，显示面板还包括平坦化层，所述发光元件包括第一电极、第二电极和位于所述第一电极和所述第二电极之间的发光功能层，所述第一电极比所述第二电极更靠近所述衬底基板，所述平坦化层位于所述发光元件的第一电极和所述像素电路之间，所述平坦化层中的过孔在所述衬底基板上的正投影与所述虚设像素电路在所述衬底基板上的正投影不交叠。
根据本公开的实施例提供显示面板，靠近所述第二显示区的中心的第二导电线和靠近所述第二显示区的中心的第三导电线包括依次相连的第一部分、第二部分、第三部分、以及第四部分，所述第二部分和所述第四部分沿所述第一方向延伸，所述第一部分和所述第三部分沿所述第二方向延伸。
根据本公开的实施例提供显示面板，所述第三部分在所述衬底基板上的正投影与所述虚设像素电路在所述衬底基板上的正投影交叠。
根据本公开的实施例提供显示面板，所述第四部分和所述第二部分位于所述第三部分的同一侧。
根据本公开的实施例提供显示面板，所述第四部分和所述第二部分位于所述第三部分的两侧。
根据本公开的实施例提供显示面板，所述多个第二区域发光元件还包括多个第四发光元件，所述第四发光元件配置为发第四颜色光，所述多个第二类型的像素电路还包括多个第四像素电路，所述多条导电线还包括多条第四导电线，所述多个第四发光元件与所述多个第四像素电路通过所述多条第四导电线相连，在所述至少一组发光元件和所述至少一组像素电路中，与所述多条第四导电线相连的多个第四像素电路比与所述多条第二导电线相连的所述多个第二像素电路中的每一个都更靠近所述第二显示区。
根据本公开的实施例提供显示面板，至少一组发光元件包括第一子组发 光元件和第二子组发光元件，所述第一子组发光元件比所述第二子组发光元件更靠近所述第二显示区的边缘，或者所述第二子组发光元件比所述第一子组发光元件更靠近所述第二显示区的中心；所述至少一组发光元件包括第一组发光元件，在所述第一组发光元件中，与所述第一子组发光元件中的所述第二发光元件和所述第三发光元件相连的导电线均位于所述第一透明导电图案层，与所述第一子组发光元件中的所述第一发光元件和所述第四发光元件相连的导电线均位于所述第二透明导电图案层；与所述第二子组发光元件中的所述第二发光元件和所述第三发光元件相连的导电线均位于所述第一透明导电图案层，与所述第二子组发光元件中的所述第一发光元件和所述第四发光元件相连的导电线均位于所述第二透明导电图案层。
根据本公开的实施例提供显示面板，所述至少一组发光元件包括第二组发光元件，所述第一组发光元件比所述第二组发光元件更靠近所述第二显示区的中心，在所述第二组发光元件中，与所述第一子组发光元件中的所述发光元件相连的导电线均位于所述第一透明导电图案层，而与所述第二子组发光元件中的发光元件相连的导电线均位于所述第二透明导电图案层。
根据本公开的实施例提供显示面板，所述第四导电线为一体结构的导电线。
根据本公开的实施例提供显示面板，所述第一透明导电图案层比所述第二透明导电图案层更靠近所述衬底基板。
根据本公开的实施例提供显示面板，所述第二透明导电图案层比所述第一透明导电图案层更靠近所述衬底基板。
根据本公开的实施例提供显示面板，所述第二显示区具有沿所述第一方向延伸的第一对称轴和沿所述第二方向延伸的第二对称轴，所述多条导电线相对于所述第一对称轴和所述第二对称轴呈轴对称。
根据本公开的实施例提供显示面板，在所述第一方向上，相邻两个第二类型的像素电路之间设有两个第一类型的像素电路。
根据本公开的实施例提供显示面板，所述第一导电线的沿所述第一方向延伸的部分在所述衬底基板上的正投影和所述第二导电线的沿所述第一方向延伸的部分在所述衬底基板上的正投影不交叠。
根据本公开的实施例提供显示面板，所述第四发光元件和所述第一发光元件配置为发绿光，所述第二发光元件和所述第三发光元件之一配置为发红光，所述第二发光元件和所述第三发光元件之另一配置为发蓝光。
根据本公开的实施例提供显示面板，所述多条第一导电线中的一部分第一导电线位于所述第二透明导电图案层，所述多条第一导电线中的另一部分第一导电线位于所述第一透明导电图案层。
本公开的至少一实施例还提供一种显示装置，包括上述任一显示面板。
例如，显示装置还包括感光传感器，所述感光传感器位于所述显示面板的一侧。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是本公开一实施例提供的一种显示面板的结构示意图。
图1B是本公开一实施例提供的一种显示面板的结构示意图。
图2是本公开一实施例提供的一种显示面板的像素单元的示意图。
图3是本公开一实施例提供的一种显示面板的示意图。
图4为本公开一实施例提供的显示面板中的第一显示区和第二显示区的示意图。
图5A至图5C为本公开一实施例提供的显示面板的局部平面图。
图5D至图5F是本公开一些实施例提供的显示面板的结构示意图。
图6为本公开的实施例提供的一种显示面板中的位于第二显示区的发光元件的示意图。
图7为本公开的实施例提供的一种显示面板中的位于第二显示区的一行发光元件和与其相连的第二类型的像素电路的示意图。
图8为本公开的实施例提供的一种显示面板中的位于第二显示区的一行发光元件和与其相连的第二类型的像素电路的示意图。
图9为本公开的实施例提供的一种显示面板中的位于第二显示区的两行发光元件和与其相连的第二类型的像素电路的示意图。
图10为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。
图11为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。
图12为本公开的实施例提供的一种显示面板中的第一透明导电图案层、发光元件以及像素电路的示意图。
图13为本公开的实施例提供的一种显示面板中的第二透明导电图案层、发光元件和像素电路的示意图。
图14为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。
图15为本公开的实施例提供的一种显示面板中的与位于第二显示区的多行发光元件相连的位于第一透明导电图案层的导电线的示意图。
图16为本公开的实施例提供的一种显示面板中的与位于第二显示区的 多行发光元件相连的位于第二导电图案层的导电线的示意图。
图17为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。
图18为本公开的实施例提供的一种显示面板中的第一透明导电图案层的示意图。
图19为本公开的实施例提供的一种显示面板中的第二透明导电图案层的示意图。
图20为本公开的实施例提供的一种显示面板中的第二透明导电图案层的示意图。
图21为本公开的实施例提供的一种显示面板中的第一透明导电图案层的示意图。
图22为本公开一实施例提供的显示面板的层结构的示意图。
图23为本公开一实施例提供的显示面板的层结构的示意图。
图24为本公开一实施例提供的显示面板中的第一像素单元的示意图。
图25为本公开一实施例提供的显示面板中的第二像素单元的示意图。
图26为一种显示面板的剖视图。
图27为形成光刻胶图形的示意图。
图28为形成导电线的示意图。
图29为本公开的实施例提供的显示面板第一显示区中的第一类型的像素电路的示意图。
图30为图29中的部分膜层的示意图。
图31为本公开的实施例提供的显示面板第一显示区中的第一类型的像素电路中的部分膜层的示意图。
图32为本公开的实施例提供的显示面板第一显示区中的第二类型的像素电路的示意图。
图33为图32中的部分膜层的示意图。
图34为本公开的实施例提供的显示面板第一显示区中的第二类型的像素电路中的部分膜层的示意图。
图35为本公开的实施例提供的显示面板第一显示区中的有纵向导电线的区域的像素电路的示意图。
图36为图35中的部分膜层的示意图。
图37为本公开的实施例提供的显示面板第一显示区中的有纵向导电线的区域的部分膜层的示意图。
图38和图39为本公开一实施例提供的显示装置的示意图。
图40示出了压缩前后的像素电路的结构版图。
图41是一种显示面板中的像素单元的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展，现有的刘海屏或水滴屏设计均逐渐不能满足用户对显示面板高屏占比的需求，一系列具有透光显示区的显示面板应运而生。该类显示面板中，可以将感光传感器(如，摄像头)等硬件设置于透光显示区，因无需打孔，故在确保显示面板实用性的前提下，使真全面屏成为可能。
相关技术中，具有屏下摄像头的显示面板一般包括用于正常显示的第一显示区以及用于设置摄像头的第二显示区。该第二显示区一般包括：多个发光元件和多个像素电路，每个像素电路与一个发光元件连接，并用于驱动发光元件发光，且相互连接的像素电路和发光元件在垂直于显示面板的方向上交叠。
由于相关技术中第二显示区内还设置有像素电路，因此第二显示区的透光率较差，相应的，显示面板的显示效果较差。
图1A是本公开一实施例提供的一种显示面板的结构示意图。图1B是本公开一实施例提供的一种显示面板的结构示意图。如图1A和图1B所示，该显示面板可以包括：衬底基板BS。显示面板包括第一显示区R1和第二显示区R2，该第一显示区R1可以位于第二显示区R2的至少一侧。例如，在一些实施例中，第一显示区R1围绕第二显示区R2。即第二显示区R2可以被第一显示区R1包围。第二显示区R2也可以设置在其他位置处，第二显示区R2的设置位置可根据需要而定。例如，第二显示区R2可以位于衬底基板BS的顶部正中间位置处，也可以位于衬底基板BS的左上角位置或右上角位置处。例如，感光传感器(如，摄像头)等硬件设置于显示面板的第二显示 区R2。例如，第二显示区R2为透光显示区，第一显示区R1为显示区。例如，第一显示区R1不透光仅用于显示。图1B示出了第一显示区R1包括辅助区Ra。
图2是本公开一实施例提供的一种显示面板的像素单元的示意图。显示面板包括像素单元100，像素单元100位于衬底基板上。如图2所示，像素单元100包括像素电路100a和发光元件100b，像素电路100a配置为驱动发光元件100b。例如，像素电路100a配置为提供驱动电流以驱动发光元件100b发光。例如，发光元件100b为有机发光二极管(OLED)，发光元件100b在其对应的像素电路100a的驱动下发出红光、绿光、蓝光，或者白光等。发光元件100b发光的颜色可根据需要而定。
为了提高第二显示区R2的光透过率，可以在第二显示区R2仅设置发光元件，而将驱动第二显示区R2的发光元件的像素电路设置在第一显示区R1。即，通过发光元件和像素电路分离设置的方式来提高第二显示区R2的光透过率。即，在第二显示区R2，不设置像素电路100a。
图3是本公开一实施例提供的一种显示面板的示意图。如图3所示，该显示面板包括：位于第一显示区R1的多个第一类型的像素电路10、多个第二类型的像素电路20和多个第一区域发光元件30，以及位于第二显示区R2的多个第二区域发光元件40。例如，多个第二类型的像素电路20可以间隔分布于多个第一类型的像素电路10之间。
例如，如图3所示，多个第一类型的像素电路10中的至少一个第一类型的像素电路10可以与多个第一区域发光元件30中的至少一个第一区域发光元件30连接，且至少一个第一类型的像素电路10在衬底基板BS上的正投影与至少一个第一区域发光元件30在衬底基板BS上的正投影可以至少部分交叠。该至少一个第一类型的像素电路10可以用于为所连接的第一区域发光元件30提供驱动信号，以驱动该第一区域发光元件30发光。
例如，如图3所示，多个第二类型的像素电路20中的至少一个第二类型的像素电路20可以与多个第二区域发光元件40中的至少一个第二区域发光元件40通过导电线L1连接，该至少一个第二类型的像素电路20可以用于为所连接的第二区域发光元件40提供驱动信号，以驱动该第二区域发光元件40发光。如图3所示，因第二区域发光元件40与第二类型的像素电路20位于不同区域，至少一个第二类型的像素电路20在衬底基板BS上的正投影与至少一个第二区域发光元件40在衬底基板BS上的正投影不存在交叠部分。即，第二类型的像素电路20在衬底基板BS上的正投影与第二区域发光元件40在衬底基板BS上的正投影不交叠。
例如，在本公开实施例中，可以设置该第一显示区R1为非透光显示区，以及设置该第二显示区R2为透光显示区。例如，第一显示区R1不可透光， 第二显示区R2可透光。如此，本公开实施例提供的显示面板，无需在显示面板上进行挖孔处理，可以将感光传感器等所需硬件结构直接设置于显示面板的一侧的对应第二显示区R2的位置处，为真全面屏的实现奠定坚实的基础。并且，由于第二显示区R2内仅包括发光元件，而不包括像素电路，从而利于提高第二显示区R2的透光率，以使得显示面板具有较好的显示效果。
如图3所示，像素单元100包括第一像素单元101和第二像素单元102，第一像素单元101的像素电路100a和发光元件100b均位于第一显示区R1，第二像素单元101的像素电路100a位于第一显示区R1，第二像素单元102的发光元件100b位于第二显示区R2。在本公开的实施例中，第一像素单元101的像素电路100a即为第一类型的像素电路10，第一像素单元101的发光元件100b即为第一区域发光元件30，第二像素单元101的像素电路100a即为第二类型的像素电路20，第二像素单元102的发光元件100b即为第二区域发光元件40。例如，第一区域发光元件30可称作原位发光元件。例如，第一类型的像素电路10可称作原位像素电路，第二类型的像素电路20可称作非原位像素电路。
例如，如图3所示，第二区域发光元件40和与该第二区域发光元件40相连的第二类型的像素电路20位于同一行。即，第二区域发光元件40的发光信号来自于同一行的第二类型的像素电路。例如，同一行像素单元的像素电路与同一条栅线相连。
如图3所示，第二像素单元102的像素电路(第二类型的像素电路20)通过导电线L1与第二像素单元102的发光元件(第二区域发光元件40)相连。例如，导电线L1采用透明导电材料制作。例如，导电线L1采用导电氧化物材料制作。例如，导电氧化物材料包括氧化铟锡(ITO)，但不限于此。
如图3所示，导电线L1的一端与第二类型的像素电路20相连，导电线L1的另一端与第二区域发光元件40相连。如图3所示，导电线L1从第一显示区R1延伸至第二显示区R2。
如图1B和图3所示，在一些实施例中，第一显示区R1可包括辅助区Ra，辅助区Ra可设置用于与第二区域发光元件40相连的第二类型的像素电路20。例如，在第一显示区R1的辅助区Ra或除了辅助区Ra外的区域，可以设置多个虚设像素电路。虚设像素电路不与任何发光元件相连。设置虚设像素电路利于提高各个膜层的部件在刻蚀工艺中的均一性。例如，虚设像素电路与其所在行或所在列的第二类型的像素电路20的结构相同，只是其不与任何发光元件相连。例如，在第一显示区R1内，辅助区Ra和第一显示区R1的除了辅助区Ra外的区域(非辅助区)的像素密度相同，或者分辨率相同，但不限于此。
图3示出了三行发光元件100b。图3示出的第一行发光元件100b经过 第一显示区R1和第二显示区R2，为一行经过两个区域的发光元件100b。图3示出的第二行发光元件100b经过第一显示区R1和第二显示区R2，为一行经过两个区域的发光元件100b。图3示出的第三行发光元件100b仅经过第一显示区R1，而不经过第二显示区R2，为一行经过一个区域的发光元件100b。例如，在一些实施例中，发光元件100b被划分为包括两种类型的行发光元件，即，包括一行经过两个区域的发光元件和一行经过一个区域的发光元件。
图4为本公开一实施例提供的显示面板中的第一显示区和第二显示区的示意图。如图4所示，在第二显示区R2中，相邻的第二区域发光元件40之间设有透光区R0。例如，如图4所示，多个透光区R0彼此相连，形成被多个第二区域发光元件40间隔的连续透光区。导电线L1采用透明导电材料制作以尽可能的提高透光区R0的透光率。如图4所示，第二显示区R2的除了设置第二区域发光元件40之外的区域可均为透光区。
图5A至图5C为本公开一实施例提供的显示面板的局部平面图。以下对图5A至图5C进行描述。
图5A为本公开一实施例提供的一种显示面板的第一显示区和第二显示区的示意图。如图5A所示，第二显示区R2为透光显示区，第一显示区R1为显示区。
图5B为本公开一实施例提供的一种显示面板的第一显示区中的第一区域发光元件和第二显示区中的第二区域发光元件的示意图。图5B示出了第一区域发光元件30和第二区域发光元件40。
参考图5A、图5B和图3，为了提高显示效果，第二区域发光元件40的密度可等于第一区域发光元件30的密度。即，第二显示区R2的分辨率与第一显示区R1的分辨率相同。当然，在其他的实施例中，第二区域发光元件40的密度可大于或小于第一区域发光元件30的密度。即，第二显示区R2的分辨率可大于或小于第一显示区R1的分辨率。例如，如图5B和图4所示，第二区域发光元件40的发光面积小于第一区域发光元件30的发光面积。即，第一区域发光元件30的发光面积大于第二区域发光元件40的发光面积，图4用虚线示出了第二区域发光元件40的发光面积和第一区域发光元件30的发光面积。例如，发光元件的发光面积可对应于像素定义层的开口的面积。
图5C示出了第一区域发光元件30、第二区域发光元件40、第一类型的像素电路10、第二类型的像素电路20、连接元件CE0，以及导电线L1。每个像素电路通过连接元件CE0与发光元件相连。即，每个像素单元均具有一个连接元件CE0。即，第一类型的像素电路10通过连接元件CE0与第一区域发光元件30相连，第二类型的像素电路20通过连接元件CE0与第二区域发光元件40相连。
例如，如图5C所示，导电线L1的一端与第二区域发光元件40相连，导电线L1的另一端通过连接元件CE0与第二类型的像素电路20相连。例如，连接元件CE0分别与像素电路100a和发光元件100b相连。例如，连接元件CE0分别与像素电路100a中的发光控制晶体管和发光元件100b的第一极相连。例如，连接元件CE0可以由单一的导电部件形成，也可以包括位于不同层的两个不同的导电部件形成。例如，连接元件CE0可以包括位于一个导电层中的一个导电部件和位于另一个导电层中的另一导电部件。
如图5C所示，一条导电线L1通过像素单元的像素电路所在的区域以分别连接该像素单元两侧的第二类型的像素电路20和第二区域发光元件40。例如，像素单元的像素电路所在的区域与多条通过该区域的导电线L1交叠。在第一显示区R1内的设置第二类型的像素电路20的区域可称作辅助区Ra(如图1B和图3所示)，辅助区Ra也可称作过渡区。图5C以一个第一类型的像素电路10最多与两条导电线L1交叠为例，在其他的实施例中，一个第一类型的像素电路10还可以与更多条导电线L1交叠。例如，在一些实施例中，一个第一类型的像素电路10可以与5-15条导电线L1交叠。一个第一类型的像素电路10与多少条导电线L1交叠可根据需要而定。如图5C所示，第二类型的像素电路20也可以和不与其相连的导电线L1交叠。
在一些实施例中，可通过在第一方向X上压缩第一类型的像素电路10的尺寸以获得设置第二类型的像素电路20的区域。例如，如图5C所示，在辅助区，每隔设定列第一类型的像素电路10设置一列第二类型的像素电路20。例如，相邻两列第二类型的像素电路20之间的第一类型的像素电路10的列数可根据需要而定。
例如，一些实施例中，可通过减小第一类型的像素电路10在第一方向X上的尺寸来获得设置第二类型的像素电路20的区域。例如，第一类型的像素电路10在第一方向X上的尺寸小于第一区域发光元件30在第一方向X上的尺寸。第一方向X例如为行方向，但不限于此，在另一些实施例中，第一方向X也可以为列方向。本公开的实施例以第一方向X为行方向为例进行说明。
一些附图示出了第三方向Z，第三方向Z为垂直于衬底基板的主表面的方向。衬底基板的主表面为用于制作各个部件的表面。剖视图中衬底基板的上表面即为衬底基板的主表面。第一方向X和第二方向Y均为平行于衬底基板的主表面的方向。例如，第一方向X和第二方向Y相交。进一步例如，第一方向X和第二方向Y垂直。
图5D至图5F是本公开一些实施例提供的显示面板的结构示意图。为了进一步体现出压缩像素电路后，多出多列像素电路，图5D示出了一种第一显示区R1的第一区域发光元件结构示意图。图5E示出了图5A中的部分结构(仅包括像素电路)示意图，图5F示出了图5A中的部分结构(仅包括发 光元件)示意图。
参考图5D至图5F可以看出，像素电路的宽度较发光元件的宽度小，如此，可以使得从右往左第2列和第9列的像素电路不连接任何第一区域发光元件30，属于多出列像素电路，其可以作为第二类型的像素电路20用于连接第二显示区R2内的第二区域发光元件40。例如，如图5F所示，第一区域发光元件30可以包括RG1BG2共4种发光元件的第一电极E1，发光元件的第一电极E1与第一类型的像素电路10通过连接元件CE0连接。R表示发红光的发光元件，G1表示发绿光的发光元件，B表示发蓝光的发光元件，G2表示发绿光的发光元件。例如，连接元件CE0包括两个连接电极，可以分别为后续提及的连接电极CE01(如图5E所示)和连接电极CE02(如图5F所示)，但不限于此。例如，为了具有充足的空间用来设置导电线L1，同一行像素单元中的连接电极CE01的轴线可以位于一条直线上。
图5F示出了四行连接元件CE0/连接电极CE02，即，图5F示出了四行发光元件。例如，每一行中的发光元件按照RGBG或BGRG的方式沿第一方向X依次排列。当然，发光元件的发光颜色不限于RGB，发光元件的排列方式也不限于图5F所示，本公开的实施例以发光元件包括RGBG为例进行说明。例如，如图5F所示，G包括G1或G2。例如，图5F所示的像素排列中，一个重复单元RP包括在第二方向Y上排列的两个G和分设在该两个G的在第一方向X上的两侧的R和B，其中R和G构成一个像素，并借用与其相邻的另一重复单元中的B构成一个虚拟像素以进行显示，B和G构成一个像素，并借用与其相邻的另一重复单元中的R构成一个虚拟像素以进行显示，但不限于此。
参考图3、图4、图5A至图5C，本公开一些实施例提供的显示面板包括：衬底基板BS、多个发光元件100b、以及多个像素电路100a。衬底基板BS具有第一显示区R1和第二显示区R2，第一显示区R1位于第二显示区R2的至少一侧。多个发光元件100b排列成多行和多列。
参考图3、图4、图5C和图5F，多个发光元件100b包括多组发光元件，多组发光元件的每组中的发光元件沿第一方向X排布，多组发光元件沿第二方向Y排布。图3和图5C均示出了三组发光元件GP，三组发光元件GP分别为一组发光元件GPx、一组发光元件GPy和一组发光元件GPz；一组发光元件GPx和一组发光元件GPy经过第一显示区R1和第二显示区R2，一组发光元件GPz仅经过第一显示区R1。图4至少示出了在第二方向Y上排列的四组发光元件GP。图5F至少示出了在第二方向Y上排列的四组发光元件GP。在显示面板中，经过第一显示区R1和第二显示区R2的发光元件的组数与仅经过第一显示区R1的发光元件的组数可根据需要而定。
例如，在一些实施例中，一组发光元件可以为一行发光元件，当然，一 组发光元件也可以不完全对应一列发光元件。在另一些实施例中，一组发光元件可以为一列发光元件，当然，一组发光元件也可以不完全对应一列发光元件。本公开的实施例以一组发光元件为一行发光元件为例进行说明。
例如，参考图3和图5C，多组发光元件中的至少一组包括多个第一区域发光元件30和多个第二区域发光元件40。即，多组发光元件中的至少一组经过第一显示区R1和第二显示区R2。
例如，参考图3、图4、以及图5C，多个发光元件100b包括经过第一显示区R1和第二显示区R2的至少一行经过两个区域的发光元件100b，至少一行经过两个区域的发光元件100b中的任意一行经过两个区域的发光元件100b包括多个第一区域发光元件30和多个第二区域发光元件40。
例如，参考图3、图4、以及图5C，多个第一区域发光元件30位于第一显示区R1，多个第二区域发光元件40位于第二显示区R2。
例如，参考图3、图5C和图5E，多个像素电路包括多组像素电路GR，多组像素电路的每组中的像素电路沿第一方向X排布，多组像素电路沿第二方向Y排布。例如，多组像素电路100a中的至少一组包括多个第一类型的像素电路10和多个第二类型的像素电路20。图3和图5C分别示出了三组像素电路GR。图5E示出了四组像素电路GR。如图3和图5C所示，像素电路仅位于第一显示区R1，第二显示区R2内不设置像素电路。
例如，参考图3和图5C，多个像素电路100a排列成多行和多列，多个像素电路100a包括位于同一行的多个第一类型的像素电路10和多个第二类型的像素电路20。或者说，多组像素电路的至少一组包括多个第一类型的像素电路10和多个第二类型的像素电路20。
例如，参考图3和图5C，多个第一类型的像素电路10和多个第二类型的像素电路20均位于第一显示区R1，多个第二类型的像素电路20间隔分布于多个第一类型的像素电路10之间。多个第一类型的像素电路10中的至少一个第一类型的像素电路10与多个第一区域发光元件30中的至少一个第一区域发光元件30连接，且至少一个第一类型的像素电路10在衬底基板BS上的正投影与至少一个第一区域发光元件30在衬底基板BS上的正投影至少部分交叠；多个第二类型的像素电路20中的至少一个第二类型的像素电路20与多个第二区域发光元件40中的至少一个第二区域发光元件40通过多条导电线中的至少一条导电线连接。
图6为本公开的实施例提供的一种显示面板中的位于第二显示区的发光元件的示意图。图7为本公开的实施例提供的一种显示面板中的位于第二显示区的一行发光元件和与其相连的第二类型的像素电路的示意图。图8为本公开的实施例提供的一种显示面板中的位于第二显示区的一行发光元件和与其相连的第二类型的像素电路的示意图。图9为本公开的实施例提供的一种 显示面板中的位于第二显示区的两行发光元件和与其相连的第二类型的像素电路的示意图。图10为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。图11为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。图12为本公开的实施例提供的一种显示面板中的第一透明导电图案层、发光元件以及像素电路的示意图。图13为本公开的实施例提供的一种显示面板中的第二透明导电图案层、发光元件和像素电路的示意图。图14为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。图15为本公开的实施例提供的一种显示面板中的与位于第二显示区的多行发光元件相连的位于第一透明导电图案层的导电线的示意图。图16为本公开的实施例提供的一种显示面板中的与位于第二显示区的多行发光元件相连的位于第二导电图案层的导电线的示意图。
例如，在本公开的实施例中，一行发光元件可指与该行发光元件相连的像素电路均与同一条栅线相连，但不限于此。例如，在本公开的实施例中，一行像素电路可指与该行像素电路均与同一条栅线相连，但不限于此。例如，在本公开的实施例中，一行像素单元可指与该行像素单元相连的像素电路均与同一条栅线相连，但不限于此。
例如，如图6至图16所示，在至少一组发光元件100b中，多个第二区域发光元件40包括多个第一发光元件41和多个第二发光元件42，第一发光元件41配置为发第一颜色光，第二发光元件42配置为发第二颜色光。多个第二类型的像素电路20包括多个第一像素电路21和多个第二像素电路22，多条导电线L1包括多条第一导电线La和多条第二导电线Lb，多个第一发光元件41与多个第一像素电路21通过多条第一导电线La连接，多个第二发光元件42与多个第二像素电路22通过多条第二导电线Lb连接。例如，一个第一发光元件41与一个第一像素电路21通过一条第一导电线La连接，一个第二发光元件42与一个第二像素电路22通过一条第二导电线Lb连接。
例如，如图6至图16所示，多个第二区域发光元件40还包括多个第三发光元件43，第三发光元件43配置为发第三颜色光，多个第二类型的像素电路20还包括多个第三像素电路23，多条导电线L1还包括多条第三导电线Lc，多个第三发光元件43与多个第三像素电路23通过多条第三导电线Lc相连。例如，一个第三发光元件43与一个第三像素电路23通过一条第三导电线Lc相连。
例如，如图6至图16所示，多个第二区域发光元件40还包括多个第四发光元件44，第四发光元件44配置为发第四颜色光，多个第二类型的像素电路20还包括多个第四像素电路24，多条导电线L1还包括多条第四导电线 Ld，多个第四发光元件44与多个第四像素电路24通过多条第四导电线Ld相连。例如，一个第四发光元件44与一个第四像素电路24通过一条第四导电线Ld相连。
例如，第一颜色光和第四颜色光均为绿光，第二颜色光和第三颜色光之一为红光，第二颜色光和第三颜色光之另一为蓝光。
例如，第四发光元件44和第一发光元件41配置为发同一颜色光。例如，第四发光元件44和第一发光元件41配置为发绿光，第二发光元件42和第三发光元件43之一配置为发红光，第二发光元件42和第三发光元件43之另一配置为发蓝光。本公开的实施例以第四发光元件44和第一发光元件41发绿光，第二发光元件42发红光，第三发光元件43之为发蓝光为例进行说明，在其他的实施例中，第一发光元件41、第二发光元件42、第三发光元件43和第四发光元件44也可发其他颜色的光，不限于红绿蓝三种颜色，第一发光元件41、第二发光元件42、第三发光元件43和第四发光元件44的发光的颜色可根据需要而定。
在显示面板中，导电线的电容量差异较大。因连接位于第二显示区的各个发光元件的导电线的长度不同，从而导致发不同颜色光的发光元件的电容量差异变化不同。与发红光的发光元件相连的导电线的电容量差异和与发蓝光的发光元件相连的导电线的电容量差异相比，与发绿光的发光元件相连的导电线的电容量差异较大。因为与发绿光的发光元件相连的导电线的电容量差异较大，造成发绿光的发光元件的发光时间减少，从而显示面板出现亮度差异，造成显示不良。显示面板显示时出现条纹。例如，显示面板显示时出现紫色条纹。例如，显示面板显示时出现紫色竖条纹。例如，在低灰阶下，发绿光的发光元件的不良程度大于发红光的发光元件的不良程度，且发红光的发光元件的不良程度大于发蓝光的发光元件的不良程度。例如，在相同灰阶下，驱动发蓝光的发光元件的驱动电流大于驱动发红光的发光元件的驱动电流，且驱动发红光的发光元件的驱动电流大于驱动发绿光的发光元件的驱动电流。
本公开的实施例提供的显示面板，为了改善显示缺陷，调整了与发不同颜色光的发光元件相连的第二类型的像素电路的设置顺序，以减轻或消除因导电线的长度差异大而带来的显示不良。即，在设计与第一发光元件相连的第二类型的像素电路时，考虑导电线的长度以及导电线的长度差异，例如，采用G优先的顺序。例如，G优先是指与发绿光的发光元件相连的第二类型的像素电路优先靠近第二显示区排布。以优化相邻像素单元的电阻差异，提升产品竞争力。
如图6至图16所示，在本公开的实施例提供的附图中，在第二显示区R2，在至少一组发光元件100b中，第二发光元件42、第一发光元件41、第 三发光元件43和第四发光元件44在第一方向X(行方向)依次排列。例如，如图6至图16所示，发光元件100b包括两种类型的发光元件列，第一类型的发光元件列包括第一发光元件41和第四发光元件44，且在列方向上，第一发光元件41和第四发光元件44交替排列，第二类型的发光元件列包括第二发光元件42和第三发光元件43，且在列方向上，第二发光元件42和第三发光元件43交替排列。在第一显示区R1的发光元件的排列方式可以与第二显示区R2的发光元件的排列方式相同，但不限于此。当然，本公开的实施例提供的发光元件的排列方式不限于图6所示，也可以根据需要采用其他适合的排列方式。
如图6至图16所示，在至少一组发光元件和至少一组像素电路中，与多个第一发光元件41相连的多个第一像素电路21比与多个第二发光元件42相连的多个第二像素电路22中的每一个都更靠近第二显示区R2。即，调整与第一发光元件41相连的第一像素电路21的设置位置，使得与第一发光元件41相连的第一像素电路21比其他的第二类型的像素电路相比，更靠近第二显示区R2，以使得与第一发光元件41相连的第一导电线La的长度差异减小，减轻或避免显示不良。
例如，在本公开的实施例中，在至少一组发光元件和至少一组像素电路中可指在经过两个区域的一行发光元件100b中，或者，可指在经过两个区域的一行像素单元中，但不限于此。
例如，如图6至图16所示，在至少一组发光元件和至少一组像素电路中，与相邻两条第一导电线La相连的两个第一像素电路21之间不设置其他的第二类型的像素电路20。该种设置方式利于减小第一导电线La的长度，也利于减小第一导电线La之间的长度差异。
需要说明的是，在本公开的实施例提供的显示面板中，元件A和元件B相邻，或者相邻的元件A和元件B是指元件A和元件B之间不具有其他的元件A和其他的元件B，但可以具有除了元件A和元件B之外的其他元件。元件A和元件B可为同一元件，也可为不同元件。
例如，如图6至图16所示，在至少一组发光元件和至少一组像素电路中，两个相邻的第二类型的像素电路20之间设置多个第一类型的像素电路10中的至少一个。例如，在本公开的实施例提供的显示面板中，在第一方向X上，相邻两个第二类型的像素电路20之间设有两个第一类型的像素电路10。
例如，如图6至图16所示，在至少一组发光元件和至少一组像素电路中，与多条第一导电线La相连的多个第一像素电路21间隔设置在多个第一类型的像素电路10中，与多条第二导电线Lb相连的多个第二像素电路22间隔设置在多个第一类型的像素电路10中。
例如，如图6至图16所示，在至少一组发光元件和至少一组像素电路中， 与多条第一导电线La相连的多个第一像素电路21比与多条第三导电线Lc相连的多个第三像素电路23中的每一个都更靠近第二显示区R2。
例如，如图6至图16所示，为了使得第二导电线Lb具有较小的电容量差异和为了使得第三导电线Lc具有较小的电容量差异，在至少一组发光元件和至少一组像素电路中，与多条第二导电线Lb相连的多个第二像素电路22和与多条第三导电线Lc相连的多个第三像素电路23交替设置。
例如，如图6至图16所示，在至少一组发光元件和至少一组像素电路中，与多条第四导电线Ld相连的多个第四像素电路24比与多条第二导电线Lb相连的多个第二像素电路22中的每一个都更靠近第二显示区R2。在本公开的实施例中，第四发光元件44和第一发光元件41发相同颜色的光，从而，多个第四像素电路24也优先设置，即多个第四像素电路24更靠近第二显示区设置。当然，在其他的实施例中，也可以不设置第四发光元件44，从而也不需要设置第四像素电路24。例如，该情况下，像素可为真实RGB的形式，但不限于此。
例如，如图6至图16所示，为了使得第一导电线La具有较小的电容量差异和使得第四导电线Ld具有较小的电容量差异，在至少一组发光元件和至少一组像素电路中，与多条第四导电线Ld相连的多个第四像素电路24和与多条第一导电线La相连的多个第一像素电路21交替设置。
例如，第一导电线La、第二导电线Lb、第三导电线Lc、以及第四导电线Ld至少之一由透明导电材料制作。
如图6至图16所示，显示面板的第二显示区R2为轴对称形状，具有沿第一方向X延伸的第一对称轴X1和沿第二方向Y延伸的第二对称轴X2。例如，如图14至图16所示，多条导电线L1相对于第一对称轴X1呈轴对称并相对于第二对称轴X2呈轴对称。图6示出了第二显示区R2包括第一子区R21、第二子区R22、第三子区R23、以及第四子区R24。第一子区R21和第二子区R22相对于第二对称轴X2呈轴对称，第三子区R23以及第四子区R24相对于第二对称轴X2呈轴对称，第一子区R21和第三子区R23相对于第一对称轴X1呈轴对称，第二子区R22以及第四子区R24相对于第一对称轴X1呈轴对称。例如，多个第二区域发光元件40相对于第一对称轴X1呈轴对称并相对于第二对称轴X2呈轴对称。图6示出了第二显示区R2的中心CT。
如图15和图16所示，显示面板包括第一透明导电图案层LY1和第二透明导电图案层LY2，多条第一导电线La中的至少一条第一导电线La位于第二透明导电图案层LY2，多条第二导电线Lb中的至少一条第二导电线位于第一透明导电图案层LY1。
本公开的实施例提供的显示面板，仅包括用于形成导电线的两个透明导 电图案层，与包括用于形成导电线的三个透明导电图案层的显示面板相比，减少掩膜版数量，利于显示面板的制作，利于减小显示面板的厚度，利于提高显示面板信赖性。
图15和图16以多条第一导电线La均位于第二透明导电图案层LY2，多条第二导电线Lb均位于第一透明导电图案层LY1为例进行说明。
例如，如图7至图16所示，在本公开的实施例提供的显示面板中，多条第一导电线La位于相邻两组发光元件之间，以利于与每一行的发光元件相连的第一导电线La的布置。位于相邻两组发光元件之间的导电线可称作横向导电线。横向导电线在第一方向X上从第二显示区R2延伸至第一显示区。例如，多条第一导电线La位于相邻两组发光元件之间可指多条第一导电线La位于相邻两组发光元件的中心线之间。例如，每组发光元件的中心线沿第一方向X延伸。相邻两组发光元件的中心线沿第二方向Y排列。
例如，如图7至图16所示，第一导电线La和第四导电线Ld采用横向导电线。
例如，如图9至图12、图14至图15所示，在本公开的实施例提供的显示面板中，靠近第二显示区R2的中心的至少一条第二导电线Lb在第二方向Y上跨过至少两组发光元件。
例如，如图9至图12、图14至图15所示，在本公开的实施例提供的显示面板中，靠近第二显示区R2的中心的至少一条第二导电线Lb在第二方向Y上由第二显示区R2延伸至第一显示区R1。
例如，如图9至图12、图14至图15所示，靠近第二显示区R2的中心的至少一条第三导电线Lc和靠近第二显示区R2的中心的至少一条第二导电线Lb采用纵向导电线。
例如，在本公开的实施例提供的显示面板中，第一导电线La为一体结构的导电线，第二导电线Lb为一体结构的导电线。
例如，多条第三导电线Lc中的一部分第三导电线Lc位于第一透明导电图案层LY1中，多条第三导电线Lc中的另一部分第三导电线Lc位于第二透明导电图案层LY2中。
例如，如图9至图12、图14至图15所示，在本公开的实施例提供的显示面板中，靠近第二显示区R2的中心的至少一条第三导电线Lc在第二方向Y上跨过至少两组发光元件。
例如，如图9至图12、图14至图15所示，在本公开的实施例提供的显示面板中，靠近第二显示区R2的中心的至少一条第三导电线Lc在第二方向Y上由第二显示区R2延伸至第一显示区R1，该形态的导电线可称作纵向导电线。纵向导电线在第二方向Y上从第二显示区R2延伸至第一显示区R1。
例如，如图7至图16所示，在本公开的实施例提供的显示面板中，在至 少一组发光元件和至少一组像素电路中，与该组发光元件相连的第一导电线La位于该组发光元件的第一侧，与该组发光元件相连的第二导电线Lb和第三导电线Lc位于该组发光元件的第二侧，第一侧和第二侧为该组发光元件的相对的两侧。
例如，如图7至图16所示，在本公开的实施例提供的显示面板中，在至少一组发光元件和至少一组像素电路中，例如，对于靠近第二显示区R2的上边缘的几组发光元件，与该组发光元件相连的第一导电线La和第四导电线Ld位于该组发光元件的第一侧，与该组发光元件相连的第二导电线Lb和第三导电线Lc位于该组发光元件的第二侧，第一侧和第二侧为该组发光元件的相对的两侧。
例如，如图7至图16所示，一组发光元件的第一侧和第二侧分别为该组发光元件的上侧和下侧。
例如，在本公开的实施例提供的显示面板中，第三导电线Lc为一体结构的导电线。
例如，在本公开的实施例提供的显示面板中，第四导电线Ld为一体结构的导电线。
例如，在本公开的实施例中，第一导电线La、第二导电线Lb、第三导电线Lc、第四导电线Ld分别为一体结构的导电线。即，每条导电线L1为一体结构的导电线，由一层导电薄膜形成，不需要分段形成。
例如，如图9至图12所示，在本公开的实施例提供的显示面板中，多组像素电路中的至少一组包括虚设像素电路200，虚设像素电路200在第一方向X上位于两个第二类型的像素电路20之间，靠近第二显示区R2的中心的第二导电线Lb和靠近第二显示区R2的中心的第三导电线Lc至少之一在衬底基板上的正投影与虚设像素电路在衬底基板上的正投影交叠。
例如，虚设像素电路200不接入任何发光元件。例如，虚设像素电路200不与导电线L1相连。例如，虚设像素电路200可以为第二类型的像素电路，只是不与导电线L1相连。即，可以从第二类型的像素电路中选出一部分，例如，几列，作为虚设像素电路列。
图9至图12示出了纵向导电线，纵向导电线包括靠近第二显示区的中心的第二导电线Lb0和靠近第二显示区的中心的第三导电线Lc0。例如，第二导电线Lb0和第三导电线Lc0位于第一透明导电图案层LY1。
例如，如图9至图12所示，在本公开的实施例提供的显示面板中，靠近第二显示区R2的中心的第二导电线Lb和靠近第二显示区的中心的第三导电线Lc包括依次相连的第一部分P1、第二部分P2、第三部分P3、以及第四部分P4，第二部分P2和第四部分P4沿第一方向X延伸，第一部分P1和第三部分P3沿第二方向Y延伸。
例如，如图9至图12所示，在本公开的实施例提供的显示面板中，第三部分P3在衬底基板上的正投影与虚设像素电路200在衬底基板上的正投影交叠。
例如，如图9至图12所示，在本公开的实施例提供的显示面板中，第四部分P4和第二部分P2位于第三部分P3的两侧。
例如，如图7至图16所示，在本公开的实施例提供的显示面板中，第一导电线La的沿第一方向X延伸的部分在衬底基板上的正投影和第二导电线Lb的沿第一方向X延伸的部分在衬底基板上的正投影不交叠，但不限于此。当然，在其他的实施例中，导电线L1的沿第一方向X延伸的部分在衬底基板上的正投影也可以交叠。
例如，在本公开的实施例中，各条导电线L1的沿第一方向X延伸的部分在衬底基板上的正投影均不交叠。
如图9至图12所示，第二导电线Lb0和第三导电线Lc0位于同一层，均位于第一透明导电图案层LY1，第二导电线Lb0的位于第二显示区R2的部分(第一部分P1)在衬底基板上的正投影与位于第二透明导电图案层LY2的导电线(横向导电线)在衬底基板上的正投影交叠。进一步例如，第二导电线Lb0的位于第二显示区R2的部分(第一部分P1)在衬底基板上的正投影与位于第二透明导电图案层LY2的导电线的沿方向X延伸的部分在衬底基板上的正投影交叠。第二导电线Lb0的位于第二显示区R2的部分(第一部分P1)在衬底基板上的正投影与横向导电线(位于第二透明导电图案层LY2的导电线)在衬底基板上的正投影交叠。
例如，如图9至图12所示，第三导电线Lc0的位于第二显示区R2的部分(第一部分P1)在衬底基板上的正投影与位于第二透明导电图案层LY2的导电线(横向导电线)在衬底基板上的正投影交叠。进一步例如，第三导电线Lc0的位于第二显示区R2的部分(第一部分P1)在衬底基板上的正投影与位于第二透明导电图案层LY2的导电线的沿方向X延伸的部分在衬底基板上的正投影交叠。
例如，在本公开的实施例提供的显示面板中，第四发光元件44和第一发光元件41配置为发绿光，第二发光元件42和第三发光元件43之一配置为发红光，第二发光元件42和第三发光元件43之另一配置为发蓝光。
如图6至图16所示，在第二显示区R2的左上四分之一的区域(第一子区R21)内，最靠近第一对称轴X1的一组发光元件称作第一行发光元件，从下往上依次为第二行直至第N行发光元件。
参考图7，在至少一组发光元件(如图7示出的第二行发光元件，r2行发光元件)中，靠近第二显示区R2的中心CT的发光元件与位于第二透明导 电图案层LY2的导电线相连，而靠近第二显示区R2的边缘的发光元件与位于第一透明导电图案层LY1的导电线相连。在至少一组发光元件中，采用横向导电线即可以将该组发光元件连接完成。上述靠近第二显示区R2的中心的发光元件包括第一发光元件41、第二发光元件42、第三发光元件43和第四发光元件44，即不区分发光元件的发光颜色，只要该发光元件靠近第二显示区R2的中心，则与位于第二透明导电图案层LY2的导电线相连。同样的，上述靠近第二显示区R2的边缘的发光元件包括第一发光元件41、第二发光元件42、第三发光元件43和第四发光元件44，即不区分发光元件的发光颜色，只要该发光元件靠近第二显示区R2的边缘，则与位于第一透明导电图案层LY1的导电线相连。靠近第二显示区R2的中心CT的发光元件也可看成是靠近第二显示区R2的第二对称轴X2的发光元件。考虑到靠近第二显示区R2的中心CT的发光元件(图9所示的第一行发光元件，r1行发光元件)可能需要与纵向导电线(导电线Lb0和导电线Lc0)相连，则为了给位于第一透明导电图案层LY1的纵向导电线提供设置位置，靠近第二显示区R2的中心CT的发光元件与位于第二透明导电图案层LY2的导电线相连。图9示出了第一子区R21内的r1行至r5行发光元件。
如图9所示，至少一组发光元件包括两个子组发光元件，即，包括第一子组发光元件G01和第二子组发光元件G02，第一子组发光元件G01比第二子组发光元件G02更靠近第二显示区R2的边缘，或者第二子组发光元件G02比第一子组发光元件G01更靠近第二显示区R2的中心。
如图9所示，在至少一组发光元件中，例如，r1行发光元件，可称作第一组发光元件G1，与第一子组发光元件G01中的发光元件(包括第二发光元件42和第三发光元件43)相连的导电线L1均位于第一透明导电图案层LY1，而与第一子组发光元件G01中的发光元件(包括第一发光元件41和第四发光元件44)相连的导电线L1均位于第二透明导电图案层LY2；与第二子组发光元件G02中的发光元件(包括第二发光元件42和第三发光元件43)相连的导电线L1均位于第一透明导电图案层LY1，与第二子组发光元件G02中的发光元件(包括第一发光元件41和第四发光元件44)相连的导电线L1均位于第二透明导电图案层LY2。
如图9所示，在至少一组发光元件中，例如，r2行发光元件，也可称作第二组发光元件G2，第一组发光元件G1比第二组发光元件G2更靠近第二显示区的中心CT，或者，第一组发光元件G1比第二组发光元件G2更靠近第一对称轴X1。与第一子组发光元件G01中的发光元件(包括第一发光元件41、第二发光元件42、第三发光元件43、以及第四发光元件44)相连的导电线L1均位于第一透明导电图案层LY1，而与第二子组发光元件G02中的发光元件(包括第一发光元件41、第二发光元件42、第三发光元件43、 以及第四发光元件44)相连的导电线L1均位于第二透明导电图案层LY2。
图9为图8中的导电线加图7中的导电线加纵向导电线的示意图。靠近第二显示区的中心处的发光元件较多，涉及纵向导电线。
如图8和图9所示，在至少一组发光元件中，对于与第一发光元件41和第四发光元件44(G像素单元)相连的导电线L1，从第二显示区R2的中心开始，采用位于第二透明导电图案层LY2的导电线，其余采用位于第一透明导电图案层LY1的导电线。对于位于第二透明导电图案层LY2的导电线，分布在该组发光元件的两侧；对于与第二发光元件42和第三发光元件43(B像素单元和R像素单元)相连的导电线L1，从第二显示区R2的边缘开始连，用位于第一透明导电图案层LY1的导电线ITO1连接，直至用完横向导电线。
如图8和图9所示，与第一发光元件41和第四发光元件44(G像素单元)相连的第二类型的像素电路比与第二发光元件42和第三发光元件43相连的第二类型的像素电路更靠近第二显示区R2，第二显示区R2的中心仅剩余第二发光元件42和第三发光元件43，且靠近第二显示区的中心位置处的第二发光元件42和第三发光元件43采用纵向导电线，连接至最远端的第二类型的像素电路，符合渐变规律。
图17为本公开的实施例提供的一种显示面板中的位于第二显示区的多行发光元件和与其相连的第二类型的像素电路的示意图。图18为本公开的实施例提供的一种显示面板中的第一透明导电图案层的示意图。图19为本公开的实施例提供的一种显示面板中的第二透明导电图案层的示意图。图20为本公开的实施例提供的一种显示面板中的第二透明导电图案层的示意图。图21为本公开的实施例提供的一种显示面板中的第一透明导电图案层的示意图。
例如，如图17至图19所示，在本公开的实施例提供的显示面板中，多条第一导电线La中的一部分第一导电线La位于第二透明导电图案层LY2，多条第一导电线La中的另一部分第一导电线La位于第一透明导电图案层LY1。
例如，如图17至图19所示，在本公开的实施例提供的显示面板中，多条第二导电线Lb中的一部分第二导电线位于第二透明导电图案层LY2，多条第二导电线Lb中的另一部分第二导电线位于第一透明导电图案层LY1。
例如，如图17至图19所示，在本公开的实施例提供的显示面板中，多条第四导电线Ld中的一部分第四导电线Ld位于第二透明导电图案层LY2，多条第四导电线Ld中的另一部分第四导电线Ld位于第一透明导电图案层LY1。
如图17所示，在至少一组发光元件和至少一组像素电路中，靠近第二对称轴X2的一些第一导电线La和第四导电线Ld位于第二透明导电图案层LY2，而远离第二对称轴X2的一些第一导电线La和第四导电线Ld位于第 一透明导电图案层LY1。
例如，如图18所示，在本公开的实施例提供的显示面板中，第四部分P4和第二部分P2位于第三部分P3的同一侧。
图19和图20中示出了位于第一透明导电图案层LY1的导电线L1和位于第二透明导电图案层LY2的导电线L1。靠近第二显示区的中心的第二发光元件和第三发光元件通过在第二方向Y上跨过至少两组发光元件的导电线与第二类型的像素电路相连。该在第二方向Y上跨过至少两组发光元件的导电线位于第一透明导电图案层LY1。
例如，如图17至图19所示，像素电路采用纵向2压1设计，即，相邻第二类型的像素电路之间设有两个第一类型的像素电路，多余1列像素电路为第二类型的像素电路。
以第一发光元件和第四发光元件发绿光，第二发光元件发红光，第三发光元件发蓝光为例。
例如，以第二显示区的左上角包括40列像素单元为例，在第二显示区的最上端，在第28列到40列的像素单元均优先使用第二透明导电图案层LY2，即19、20行发光元件优先使用位于第二透明导电图案层LY2的导电线，第18行及以下在第二透明导电图案层LY2的导电线的空间不足后，再使用位于第一透明导电图案层LY1的导电线连接第1列到27列的像素单元；在第1至8行发光元件中，受第一透明导电图案层LY1、第二透明导电图案层LY2的导电线的线宽线距影响，横向导电线的连接方式已不满足像素单元的连接，此时优先使用位于第二透明导电图案层LY2的导电线连接第28列到40列G像素单元，剩余6列R/G像素单元，第1到27列发光元件使用位于第一透明导电图案层LY1和第二透明导电图案层LY2的导电线依次连接。总剩余6列8行R/B像素单元，使用位于第一透明导电图案层LY1的导电线纵向连接R/B像素单元。例如，其中的6列8行R/B像素单元使用导电线和像素电路连接时，分别间隔一列虚设像素电路，虚设像素电路不设置贯穿平坦化层的过孔VH，用于6列8行的R/B像素单元的导电线，导电线的走线方式如图21所示。
从仿真数据上看，以第1行像素为例，G像素单元的最近走线电容为49.24fF，最远走线电容为320.87fF，最大值和最小值之比为6.51，R像素单元的最近走线电容为186.56fF，最远走线电容为730.65fF，B像素单元的最近走线电容为201.56fF，最远走线电容为759.08fF，由于使用G优先的设置方式，R/B像素单元的导电线长度均大于G像素单元的导电线的长度，故可以减小R像素单元、B像素单元的电容的最大值和最小值的差异。同时R、B像素单元的最大值和最小值之比分别为3.9和3.7。如果R/G/B像素单元的导电线依次连接，不采用G优先的方式设置，导电线的最大和最小值比值分 别为14.2，12，10，相比于RGB像素单元的导电线依次连接设计，本公开的实施例提供的显示面板，采用G优先的设置方式，既能减小R/G/B像素单元的电容的最大值和最小值的差异，更有利于算法补偿，提升显示效果，同时本公开的实施例提供的显示面板只使用了2个透明导电图案层来形成导电线，相比于原有的3个透明导电图案层来形成导电线的方式，能更好的降低生产成本。
在本公开的实施例提供的附图中，颜色相对较浅的导电线为位于第二透明导电图案层LY2的导电线，颜色相对较深的导电线为位于第一透明导电图案层LY1的导电线。
图22为本公开一实施例提供的显示面板的层结构的示意图。如图22所示，像素电路100a位于衬底基板BS上，绝缘层700位于像素电路100a上，第一透明导电图案层LY1位于绝缘层700上，绝缘层701位于第一透明导电图案层LY1上，第二透明导电图案层LY2位于绝缘层701上，绝缘层702位于第二透明导电图案层LY2上，发光元件100b位于绝缘层702上。发光元件100b包括第一电极E1、第二电极E2、以及位于第一电极E1和第二电极E2之间的发光功能层FL。第一电极E1比第二电极E2更靠近衬底基板BS。
在本公开的实施例中，发光元件的个数不限于图中所示，可根据需要设定。
图23为本公开一实施例提供的显示面板的层结构的示意图。与图22所示的显示面板相比，第二透明导电图案层LY2和第一透明导电图案层LY1的位置对调。
例如，如图22所示，在本公开的实施例提供的显示面板中，第一透明导电图案层LY1比第二透明导电图案层LY2更靠近衬底基板BS。
例如，如图23所示，在本公开的实施例提供的显示面板中，第二透明导电图案层LY2比第一透明导电图案层LY1更靠近衬底基板BS。
图22和图23示出了膜层的堆叠情况，未示出各个层结构的部件之间的连接关系。
图24为本公开一实施例提供的显示面板中的第一像素单元的示意图。图24示出了第一像素单元101。图25为本公开一实施例提供的显示面板中的第二像素单元的示意图。图24示出了第一像素单元102。
如图24所示，衬底基板BS上设置缓冲层BL，缓冲层BL上设置隔离层BR，在隔离层BR上设置有源层LY0，在有源层LY0上设置绝缘层ISL1，在绝缘层ISL1上设置导电层LYa，在导电层LYa上设置绝缘层ISL2，在绝缘层ISL2上设置导电层LYb，在导电层LYb上设置绝缘层ISL3，在绝缘层ISL3上设置导电层LYc，导电层LYc包括连接电极CE01，连接电极CE01 通过贯穿绝缘层ISL1、绝缘层ISL2以及绝缘层ISL3的过孔V8与发光控制晶体管T5的第二极T52相连，在导电层LYc上设置绝缘层ISL4和绝缘层ISL5，在绝缘层ISL4和绝缘层ISL5上设置导电层LYd，导电层LYd包括连接电极CE02，连接电极CE02通过贯穿第四绝缘层ISL4的过孔V32与连接电极CE01相连，第四导电层LYd上设置第五绝缘层ISL5，发光元件100b(第一区域发光元件30)通过贯穿绝缘层ISL5的过孔Vf与连接电极CE02相连，连接电极CE02通过贯穿绝缘层ISL4的过孔VH与连接电极CE01相连。发光元件100b包括第一电极E1、第二电极E2以及位于第一电极E1和第二电极E2之间的发光功能层FL。例如，连接元件CE0包括连接电极CE01和连接电极CE02。
图24还示出了发光控制晶体管T5的第二极T52，发光控制线EML、发光控制晶体管T5的第一极T51、存储电容的第一极板Ca、存储电容的第二极板Cb、发光控制晶体管T4的第二极T42、栅线GT、数据线DT、复位控制信号线RST、初始化信号线INT。
图24还示出了像素定义层PDL以及隔垫物PS，像素定义层PDL具有开口OPN2，开口OPN2被配置为限定像素单元的发光面积(出光区域，有效发光面积)。隔垫物PS被配置为在形成发光功能层FL时支撑精细金属掩膜。
例如，如图24所示，开口OPN2为像素单元的出光区域。发光功能层FL位于发光元件100b的第一电极E1之上，发光元件100b的第二电极E2位于发光功能层FL上，如图24所示，发光元件100b上设置封装层CPS。封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如，第一封装层CPS1和第三封装层CPS3为无机材料层，第二封装层CPS2为有机材料层。例如，第一电极E1为发光元件100b的阳极，第二电极E2为发光元件100b的阴极，但不限于此。
图25示出了导电线L1，导电线L1的一端与第二显示区R2中的第二区域发光元件40相连，导电线L1的另一端与像素电路相连。
例如，如图25、图7至图21所示，多条导电线L1在垂直于衬底基板BS的主表面的方向上位于多个发光元件100b和多个像素电路100a之间。图24和图25未示出像素电路100a的全部结构。
图24和图25以绝缘层ISL4包括绝缘子层ISL41和绝缘子层ISL42为例进行说明。
图26为一种显示面板的剖视图。图26为形成导电线L1的过程中对透明导电薄膜进行构图时的曝光工艺的示意图。图27为形成光刻胶图形的示意图。图28为形成导电线的示意图。如图26所示，第一导电元件111位于衬底基板BS上；第一平坦化层121位于第一导电元件111上；第二导电元件 112位于第一平坦化层121上，并通过贯穿第一平坦化层121的过孔V0与第一导电元件111相连；第二平坦化层122位于第二导电元件112上。如图26所示，形成导电线L1包括在第二平坦化层122上形成透明导电薄膜F1，在透明导电薄膜F1上形成光刻胶薄膜201，以掩膜版202为掩膜对光刻胶薄膜201进行曝光，从而使得光刻胶薄膜201形成光刻胶保留部2011和光刻胶待去除部2012。如图27所示，曝光工艺后进行显影工艺，在显影工艺中，将光刻胶待去除部2012去除，形成光刻胶图形201a。如图28所示，以光刻胶图形201a为掩膜对透明导电薄膜F1进行刻蚀，形成导电线L1。例如，导电线L1包括多条。相邻的透明导电层之间设置绝缘层。
在曝光工艺后，透明导电薄膜的光刻胶出现曝断和变细的情况，导致显影刻蚀后导电线出现断线或者变细，从而使得显示出现暗点不良。光学显微镜确认导电线断线和变细的位置为导电线跨越第一平坦化层121的过孔V0的位置，进一步通过对第一平坦化层121的过孔V0处截面进行聚焦离子束(Focused Ion beam，FIB)分析，发现跨越过孔V0的导电线在断线或导电线变细的位置的下方都有第二导电元件112的呈碗形的部分，因此，如图26所示，判定导电线断线和变细不良的原因在于：在曝光工艺中，第二导电元件112反射光线并聚光至位于第二导电元件112的呈碗形的部分(对应过孔V0的位置)上方的光刻胶保留部2011，使得这部分光刻胶被曝光或部分曝光，显影后被洗去，从而以光刻胶图形201a为掩膜刻蚀透明导电薄膜后形成的导电线出现断线和变细。如图26至图28所示，位于中间位置处的光刻胶保留部2011被部分反射光照射而使得其下方的导电线变细。
图26至图28中的第一导电元件111可为图24和图25中的连接电极CE01，第二导电元件112可为图24和图25中的连接电极CE02。
图29为本公开的实施例提供的显示面板第一显示区中的第一类型的像素电路的示意图。图30为图29中的部分膜层的示意图。图31为本公开的实施例提供的显示面板第一显示区中的第一类型的像素电路中的部分膜层的示意图。
图32为本公开的实施例提供的显示面板第一显示区中的第二类型的像素电路的示意图。图33为图32中的部分膜层的示意图。图34为本公开的实施例提供的显示面板第一显示区中的第二类型的像素电路中的部分膜层的示意图。
图35为本公开的实施例提供的显示面板第一显示区中的有纵向导电线的区域的像素电路的示意图。图36为图35中的部分膜层的示意图。图37为本公开的实施例提供的显示面板第一显示区中的有纵向导电线的区域的部分膜层的示意图。
为了减轻导电线L1断线或变细，在虚设像素电路200中，不设置连接 电极CE02，进而，虚设像素电路200不具有贯穿绝缘层ISL4的过孔VH。在一些实施例中，虚设像素电路200不具有连接电极CE02，但不限于此。在另一些实施例中，虚设像素电路200具有连接电极CE02，连接电极CE02与连接电极CE01不通过过孔相连。即，在虚设像素电路200中，连接电极CE02与连接电极CE01彼此绝缘，连接电极CE02与连接电极CE01之间不设置过孔。
例如，如图24和图25所示，在本公开的实施例提供的显示面板中，显示面板还包括平坦化层PLN，图24和图25中的绝缘层ISL4可为平坦化层PLN，平坦化层PLN位于发光元件的第一电极E1和像素电路100a之间。
如图29至图31、图25至图27所示，平坦化层PLN中的过孔VH在衬底基板上的正投影与虚设像素电路200在衬底基板上的正投影不交叠。从而，可以避免导电线L1的位于虚设像素电路200中的部分变细或断线的情况。
如图30所示，虚线框R3位置处不设置过孔VH，不设置连接电极CE02。
如图30所示，虚设像素电路200的数据线DTm断开。数据线DTm在虚线框R4位置处断开形成多个不相连的部分。数据线DTm不接入像素电路。
如图37所示，虚线框R5位置处不设置过孔VH，不设置连接电极CE02。
本公开的一些实施例提供的显示面板包括第四发光元件，在另一些实施例中，显示面板也可以不包括第四发光元件。在显示面板不包括第四发光元件的情况下，可去除图中的第四发光元件以及与第四发光元件相连的像素电路，并相应调整其他部件的位置即可。
例如，本公开的实施例的像素电路中的晶体管均为薄膜晶体管。例如，导电层LYa、导电层LYb、导电层LYc、导电层LYd均采用金属材料制作。例如，导电层LYa和导电层LYb采用镍、铝等金属材料形成，但不限于此。例如，导电层LYc和导电层LYd采用钛、铝等材料形成，但不限于此。例如，导电层LYc和导电层LYd分别为Ti/AL/Ti三个子层形成的结构，但不限于此。例如，衬底基板可以采用玻璃基板或聚酰亚胺基板，但不限于此，可根据需要进行选择。例如，缓冲层BL、隔离层BR、绝缘层ISL1、绝缘层ISL2、绝缘层ISL3、绝缘层ISL4、绝缘层ISL5均采用绝缘材料制作。例如，绝缘层ISL4和绝缘层ISL5的材料包括有机绝缘材料，有机绝缘材料包括树脂，但不限于此。发光元件的第一电极E1和第二电极E2的材料可根据需要进行选取。一些实施例中，第一电极E1可采用透明导电金属氧化物和银至少之一，但不限于此。例如，第一电极E1可采用ITO-Ag-ITO三个子层叠层设置的结构。一些实施例中，第二电极E2可以为低功函的金属，可采用镁和银至少之一，但不限于此。
例如，第一透明导电图案层LY1和第二透明导电图案层LY2均采用透明导电金属氧化物制作，透明导电金属氧化物包括氧化铟锡(ITO)，但不 限于此。
本公开的至少一实施例提供一种显示装置，包括上述任一显示面板。
图38和图39为本公开一实施例提供的显示装置的示意图。如图38和图39所示，传感器SS位于显示面板DS的一侧，并位于第二显示区R2。环境光可透过第二显示区R2而被传感器SS感知。如图39所示，显示面板的未设置传感器SS的一侧为显示侧，可以显示图像。例如，传感器包括感光传感器，感光传感器位于显示面板的一侧。
例如，该第二显示区R2可以为矩形，传感器SS在衬底基板BS上的正投影的面积可以小于或等于第二显示区R2的内切圆的面积。即，传感器SS所处区域的尺寸可以小于或等于该第二显示区R2的内切圆的尺寸。例如，传感器SS所处区域的尺寸等于第二显示区R2的内切圆的尺寸，即该传感器SS所在区域的形状可以为圆形，相应的，该传感器SS所在区域也可以称为透光孔。当然，在一些实施例中，第二显示区R2也可以为除矩形之外的其他形状，如圆形或椭圆形。
例如，显示装置为屏下摄像头的全面屏显示装置。例如，显示装置包括OLED或包括OLED的产品。例如，显示装置包括含有上述显示面板的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
相关技术中，像素电路(包括第一类型的像素电路10和第二类型的像素电路20)和第一区域发光元件30的尺寸(pitch)相同。如，一般宽度约为30微米(μm)至32μm，长度约为60μm至65μm。而在本公开实施例中，为了能够在不减少第一显示区R1内的像素数量的前提下，为第二类型的像素电路20的设置提供充足的空间，可以通过沿第一方向X(如，栅线延伸方向，也可以称为横向)对各像素电路进行压缩，使得像素电路在第一方向上的宽度相对于第一区域发光元件30的宽度较小；或者，可以通过沿第一方向X对第一区域发光元件30进行延展，使得第一区域发光元件30在第一方向X的宽度相对于第一区域发光元件30的宽度较大。如此，在衬底基板BS尺寸相同的前提下，第一显示区R1内能够多出较多区域，相应的，可以在该较多区域处设置用于驱动位于第二显示区R2内的第二发光元件40的第二类型的像素电路20。
例如，每个像素电路的宽度与第一区域发光元件30的宽度可以相差约4μm。以压缩像素电路，且宽度相差4μm为例，图40示出了压缩前后的像素电路的结构版图。参考图40可以看出，像素电路可以包括驱动结构以及用于连接至发光元件的第一极(阳极)的连接元件CE0，该连接元件CE0的尺寸可以代表像素电路的尺寸。压缩前的像素电路和发光元件的尺寸均为宽度为1-100μm，高度为2-100μm。压缩后的发光元件与压缩前相比的尺寸可以 不变。例如，第二区域发光元件40的尺寸可以等于或小于第一区域发光元件20的尺寸。压缩后的像素电路的高度不变，但宽度缩窄1-20μm。这样每隔几列压缩像素电路就会多出一列或者多列压缩像素电路，整个屏幕都采用这种设计，以实现全屏压缩。其中，这些多出列可被挑选用来连接第二显示区R2内的第二区域发光元件40，以控制第二区域发光元件40发光。在一些实施例中，挑选靠近第二显示区R2周边的多出列像素电路作为第二类型的像素电路20连接第二区域发光元件40。如此，可以使得在不改变显示面板的分辨率的同时，正常显示。即，充分利用了显示面板已有空间来实现正常显示。通过压缩像素电路的尺寸达到的效果是：发光元件(包括第一区域发光元件30和第二发光元件40)的数量不变，进而，与压缩前相比，显示效果无明显差异，该显示面板的显示效果较好。
图41是一种显示面板中的像素单元的示意图。图40示出了显示面板的一个像素单元的像素电路，如图40所示，像素单元100包括像素电路100a和发光元件100b。像素电路100a包括六个开关晶体管(T2-T7)、一个驱动晶体管T1和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、以及第二复位晶体管T7。发光元件100b包括第一电极E1和第二电极E2以及位于第一电极E1和第二电极E2之间的发光功能层。例如，第一电极E1为阳极，第二电极E2为阴极。通常，阈值补偿晶体管T3、第一复位晶体管T6采用双栅薄膜晶体管(Thin Film Transistor，TFT)的方式降低漏电。
如图40所示，显示面板包括栅线GT、数据线DT、第一电源线PL1、第二电源线PL2、发光控制信号线EML、初始化信号线INT、复位控制信号线RST等。例如，复位控制信号线RST包括第一复位控制信号线RST1和第二复位控制信号线RST2。第一电源线PL1配置为向像素单元100提供恒定的第一电压信号VDD、第二电源线PL2配置为向像素单元100提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。栅线GT配置为向像素单元100提供扫描信号SCAN、数据线DT配置为向像素单元100提供数据信号DATA(数据电压VDATA)、发光控制信号线EML配置为向像素单元100提供发光控制信号EM，第一复位控制信号线RST1配置为向像素单元100提供第一复位控制信号RESET1，第二复位控制信号线RST2配置为向像素单元100提供扫描信号SCAN。例如，在一行像素单元中，第二复位控制信号线RST2可以与栅线GT相连，以被输入扫描信号SCAN。当然，第二复位控制信号线RST2也可以被输入第二复位控制信号RESET2。第一初始化信号线INT1配置为向像素单元100提供第一初始化信号Vinit1。第二初始化信号线INT2配置为向像素单元100提供第二初始化信 号Vinit2。例如，第一初始化信号Vinit1和第二初始化信号Vinit2为恒定的电压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此，例如，第一初始化信号Vinit1和第二初始化信号Vinit2可均小于或等于第二电压信号VSS。例如，在一些实施例中，第一初始化信号线INT1和第二初始化信号线INT1相连，均配置为向像素单元100提供初始化信号Vinit，即，第一初始化信号线INT1和第二初始化信号线INT2均称作初始化信号线INT，第一初始化信号Vinit1和第二初始化信号Vinit2相等，均为Vinit。
如图40所示，驱动晶体管T1与发光元件100b电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件100b发光。
例如，发光元件100b包括有机发光二极管(OLED)，发光元件100b在其对应的像素电路100a的驱动下发出红光、绿光、蓝光，或者白光等。例如，一个像素包括多个像素单元。一个像素可包括发不同颜色光的多个像素单元。例如，一个像素包括发红光的像素单元，发绿光的像素单元和发蓝光的像素单元，但不限于此。一个像素包括的像素单元的个数以及每个像素单元的发光情况可根据需要而定。
例如，如图40所示，数据写入晶体管T2的栅极T20与栅线GT相连，数据写入晶体管T2的第一极T21与数据线DT相连，数据写入晶体管T2的第二极T22与驱动晶体管T1的第一极T11相连。
例如，如图40所示，像素电路100a还包括阈值补偿晶体管T3，阈值补偿晶体管T3的栅极T30与栅线GT相连，阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12相连，阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10相连。
例如，如图40所示，显示面板还包括发光控制信号线EML，像素电路100a还包括第一发光控制晶体管T4和第二发光控制晶体管T5，第一发光控制晶体管T4的栅极T40与发光控制信号线EML相连，第一发光控制晶体管T4的第一极T41与第一电源线PL1相连，第一发光控制晶体管T4的第二极T42与驱动晶体管T1的第一极T11相连；第二发光控制晶体管T5的栅极T50与发光控制信号线EML相连，第二发光控制晶体管T5的第一极T51与驱动晶体管T1的第二极T12相连，第二发光控制晶体管T5的第二极T52与发光元件100b的第一电极E1相连。
如图40所示，第一复位晶体管T6与驱动晶体管T1的栅极T10相连，并配置为对驱动晶体管T1的栅极进行复位，第二复位晶体管T7与发光元件100b的第一电极E1相连，并配置为对发光元件100b的第一电极E1进行复位。第一初始化信号线INT1通过第一复位晶体管T6与驱动晶体管T1的栅 极相连。第二初始化信号线INT2通过第二复位晶体管T7与发光元件100b的第一电极E1相连。例如，第一初始化信号线INT1和第二初始化信号线INT2相连，以被输入相同的初始化信号，但不限于此，在一些实施例中，第一初始化信号线INT1和第二初始化信号线INT2也可以彼此绝缘，并配置为分别输入信号。
例如，如图40所示，第一复位晶体管T6的第一极T61与第一初始化信号线INT1相连，第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10相连，第二复位晶体管T7的第一极T71与第二初始化信号线INT2相连，第二复位晶体管T7的第二极T72与发光元件100b的第一电极E1相连。例如，如图40所示，第一复位晶体管T6的栅极T60与第一复位控制信号线RST1相连，第二复位晶体管T7的栅极T70与第二复位控制信号线RST2相连。
如图40所示，第一电源线PL1配置为向像素电路100a提供第一电压信号VDD；像素电路还包括存储电容Cst，存储电容Cst的第一极板Ca与驱动晶体管T1的栅极T10相连，存储电容Cst的第二极板Cb与第一电源线PL1相连。
例如，如图40所示，显示面板还包括第二电源线PL2，第二电源线PL2与发光元件100b的第二电极E2相连。
图40示出了第一节点N1、第二节点N2、第三节点N3和第四节点N4。
以上以7T1C的像素电路为例进行说明，本公开的实施例包括但不限于此。需要说明的是，本公开的实施例对像素电路包括的薄膜晶体管的个数以及电容的个数不做限定。例如，在另外的一些实施例中，显示面板的像素电路还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。当然，显示面板也可以包括小于7个晶体管的像素电路。
在本公开的实施例中，位于同一层的元件可由同一膜层经同一构图工艺形成。例如，位于同一层的元件可位于同一个元件的远离衬底基板的表面上。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (29)

  1. 一种显示面板，包括：衬底基板、多个发光元件、多个像素电路、以及多条导电线，其中，
    所述衬底基板具有第一显示区和第二显示区，所述第一显示区位于所述第二显示区的至少一侧；
    所述多个发光元件位于所述第一显示区和所述第二显示区，所述多个发光元件包括多组发光元件，所述多组发光元件的每组中的发光元件沿第一方向排布，所述多组发光元件沿第二方向排布，所述多组发光元件中的至少一组包括多个第一区域发光元件和多个第二区域发光元件，所述多个第一区域发光元件位于所述第一显示区，所述多个第二区域发光元件位于所述第二显示区；
    所述多个像素电路位于所述第一显示区，所述多个像素电路包括多组像素电路，所述多组像素电路的每组中的像素电路沿所述第一方向排布，所述多组像素电路沿所述第二方向排布，所述多组像素电路中的至少一组包括多个第一类型的像素电路和多个第二类型的像素电路，所述多个第二类型的像素电路间隔分布于所述多个第一类型的像素电路之间，
    所述多个第一类型的像素电路中的至少一个第一类型的像素电路与所述多个第一区域发光元件中的至少一个第一区域发光元件连接，且所述至少一个第一类型的像素电路在所述衬底基板上的正投影与所述至少一个第一区域发光元件在所述衬底基板上的正投影至少部分交叠；所述多个第二类型的像素电路中的至少一个第二类型的像素电路与所述多个第二区域发光元件中的至少一个第二区域发光元件通过多条导电线中的至少一条导电线连接；
    所述多个第二区域发光元件包括多个第一发光元件和多个第二发光元件，所述第一发光元件配置为发第一颜色光，所述第二发光元件配置为发第二颜色光，
    所述多个第二类型的像素电路包括多个第一像素电路和多个第二像素电路，
    所述多条导电线包括多条第一导电线和多条第二导电线，所述多个第一发光元件与所述多个第一像素电路通过所述多条第一导电线连接，所述多个第二发光元件与所述多个第二像素电路通过所述多条第二导电线连接，
    在所述至少一组发光元件和所述至少一组像素电路中，与所述多个第一发光元件相连的所述多个第一像素电路比与所述多个第二发光元件相连的所述多个第二像素电路中的每一个都更靠近所述第二显示区，
    所述显示面板包括第一透明导电图案层和第二透明导电图案层，
    所述多条第一导电线中的至少一条第一导电线位于所述第二透明导电图 案层，所述多条第二导电线中的至少一条第二导电线位于所述第一透明导电图案层。
  2. 根据权利要求1所述的显示面板，其中，所述多条导电线在垂直于所述衬底基板的主表面的方向上位于所述多个发光元件和所述多个像素电路之间。
  3. 根据权利要求1或2所述的显示面板，其中，靠近所述第二显示区的中心的至少一条第二导电线在所述第二方向上跨过至少两组发光元件。
  4. 根据权利要求3所述的显示面板，其中，靠近所述第二显示区的中心的至少一条第二导电线在所述第二方向上由所述第二显示区延伸至所述第一显示区。
  5. 根据权利要求1-4任一项所述的显示面板，其中，所述第一导电线为一体结构的导电线，所述第二导电线为一体结构的导电线。
  6. 根据权利要求1-5任一项所述的显示面板，其中，所述多个第二区域发光元件还包括多个第三发光元件，所述第三发光元件配置为发第三颜色光，
    所述多个第二类型的像素电路还包括多个第三像素电路，
    所述多条导电线还包括多条第三导电线，所述多个第三发光元件与所述多个第三像素电路通过所述多条第三导电线相连，
    在所述至少一组发光元件和所述至少一组像素电路中，与所述多条第一导电线相连的所述多个第一像素电路比与所述多条第三导电线相连的所述多个第三像素电路中的每一个都更靠近所述第二显示区，
    所述多条第三导电线中的一部分第三导电线位于所述第一透明导电图案层中，所述多条第三导电线中的另一部分第三导电线位于所述第二透明导电图案层中。
  7. 根据权利要求6所述的显示面板，其中，靠近所述第二显示区的中心的至少一条第三导电线在所述第二方向上跨过至少两组发光元件。
  8. 根据权利要求7所述的显示面板，其中，靠近所述第二显示区的中心的至少一条第三导电线在所述第二方向上由所述第二显示区延伸至所述第一显示区。
  9. 根据权利要求6-8任一项所述的显示面板，其中，在所述至少一组发光元件和所述至少一组像素电路中，与该组发光元件相连的第一导电线位于该组发光元件的第一侧，与该组发光元件相连的第二导电线和第三导电线位于该组发光元件的第二侧，所述第一侧和所述第二侧为该组发光元件的相对的两侧。
  10. 根据权利要求6-9任一项所述的显示面板，其中，所述多组像素电路中的至少一组包括虚设像素电路，所述虚设像素电路在所述第一方向上位于两个第二类型的像素电路之间，靠近所述第二显示区的中心的第二导电线 和靠近所述第二显示区的中心的第三导电线至少之一在所述衬底基板上的正投影与所述虚设像素电路在所述衬底基板上的正投影交叠。
  11. 根据权利要求6-10任一项所述的显示面板，其中，所述第三导电线为一体结构的导电线。
  12. 根据权利要求6-11任一项所述的显示面板，还包括平坦化层，其中，所述发光元件包括第一电极、第二电极和位于所述第一电极和所述第二电极之间的发光功能层，所述第一电极比所述第二电极更靠近所述衬底基板，所述平坦化层位于所述发光元件的第一电极和所述像素电路之间，所述平坦化层中的过孔在所述衬底基板上的正投影与所述虚设像素电路在所述衬底基板上的正投影不交叠。
  13. 根据权利要求10所述的显示面板，其中，靠近所述第二显示区的中心的第二导电线和靠近所述第二显示区的中心的第三导电线包括依次相连的第一部分、第二部分、第三部分、以及第四部分，所述第二部分和所述第四部分沿所述第一方向延伸，所述第一部分和所述第三部分沿所述第二方向延伸。
  14. 根据权利要求13所述的显示面板，其中，所述第三部分在所述衬底基板上的正投影与所述虚设像素电路在所述衬底基板上的正投影交叠。
  15. 根据权利要求13或14所述的显示面板，其中，所述第四部分和所述第二部分位于所述第三部分的同一侧。
  16. 根据权利要求13或14所述的显示面板，其中，所述第四部分和所述第二部分位于所述第三部分的两侧。
  17. 根据权利要求6-16任一项所述的显示面板，其中，所述多个第二区域发光元件还包括多个第四发光元件，所述第四发光元件配置为发第四颜色光，
    所述多个第二类型的像素电路还包括多个第四像素电路，
    所述多条导电线还包括多条第四导电线，所述多个第四发光元件与所述多个第四像素电路通过所述多条第四导电线相连，
    在所述至少一组发光元件和所述至少一组像素电路中，与所述多条第四导电线相连的多个第四像素电路比与所述多条第二导电线相连的所述多个第二像素电路中的每一个都更靠近所述第二显示区。
  18. 根据权利要求17所述的显示面板，其中，至少一组发光元件包括第一子组发光元件和第二子组发光元件，所述第一子组发光元件比所述第二子组发光元件更靠近所述第二显示区的边缘，或者所述第二子组发光元件比所述第一子组发光元件更靠近所述第二显示区的中心；
    所述至少一组发光元件包括第一组发光元件，在所述第一组发光元件中，与所述第一子组发光元件中的所述第二发光元件和所述第三发光元件相连的 导电线均位于所述第一透明导电图案层，与所述第一子组发光元件中的所述第一发光元件和所述第四发光元件相连的导电线均位于所述第二透明导电图案层；与所述第二子组发光元件中的所述第二发光元件和所述第三发光元件相连的导电线均位于所述第一透明导电图案层，与所述第二子组发光元件中的所述第一发光元件和所述第四发光元件相连的导电线均位于所述第二透明导电图案层。
  19. 根据权利要求18所述的显示面板，其中，所述至少一组发光元件包括第二组发光元件，所述第二组发光元件比所述第一组发光元件更靠近所述第二显示区的中心，在所述第二组发光元件中，与所述第一子组发光元件中的所述发光元件相连的导电线均位于所述第一透明导电图案层，而与所述第二子组发光元件中的发光元件相连的导电线均位于所述第二透明导电图案层。
  20. 根据权利要求17-19任一项所述的显示面板，其中，所述第四导电线为一体结构的导电线。
  21. 根据权利要求1-20任一项所述的显示面板，其中，所述第一透明导电图案层比所述第二透明导电图案层更靠近所述衬底基板。
  22. 根据权利要求1-20任一项所述的显示面板，其中，所述第二透明导电图案层比所述第一透明导电图案层更靠近所述衬底基板。
  23. 根据权利要求1-22任一项所述的显示面板，其中，所述第二显示区具有沿所述第一方向延伸的第一对称轴和沿所述第二方向延伸的第二对称轴，所述多条导电线相对于所述第一对称轴和所述第二对称轴呈轴对称。
  24. 根据权利要求1-23任一项所述的显示面板，其中，在所述第一方向上，相邻两个第二类型的像素电路之间设有两个第一类型的像素电路。
  25. 根据权利要求1-24任一项所述的显示面板，其中，所述第一导电线的沿所述第一方向延伸的部分在所述衬底基板上的正投影和所述第二导电线的沿所述第一方向延伸的部分在所述衬底基板上的正投影不交叠。
  26. 根据权利要求6-20任一项所述的显示面板，其中，所述第四发光元件和所述第一发光元件配置为发绿光，所述第二发光元件和所述第三发光元件之一配置为发红光，所述第二发光元件和所述第三发光元件之另一配置为发蓝光。
  27. 根据权利要求1-26任一项所述的显示面板，其中，所述多条第一导电线中的一部分第一导电线位于所述第二透明导电图案层，所述多条第一导电线中的另一部分第一导电线位于所述第一透明导电图案层；
    所述多条第二导电线中的一部分第二导电线位于所述第二透明导电图案层，所述多条第二导电线中的另一部分第二导电线位于所述第一透明导电图案层。
  28. 根据权利要求1-27任一项所述的显示面板，其中，所述显示面板仅包括用于形成所述多条导电线的所述第一透明导电图案层和所述第二透明导电图案层。
  29. 一种显示装置，包括根据权利要求1-28任一项所述的显示面板。
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