WO2022048519A1 - 一种显示面板及终端设备 - Google Patents

一种显示面板及终端设备 Download PDF

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Publication number
WO2022048519A1
WO2022048519A1 PCT/CN2021/115425 CN2021115425W WO2022048519A1 WO 2022048519 A1 WO2022048519 A1 WO 2022048519A1 CN 2021115425 W CN2021115425 W CN 2021115425W WO 2022048519 A1 WO2022048519 A1 WO 2022048519A1
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WO
WIPO (PCT)
Prior art keywords
segment
area
winding
display panel
punched
Prior art date
Application number
PCT/CN2021/115425
Other languages
English (en)
French (fr)
Inventor
张文林
王利颖
王强
李孟庭
李秀玲
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to KR1020237010454A priority Critical patent/KR20230058666A/ko
Priority to EP21863584.5A priority patent/EP4199097A4/en
Priority to JP2023514479A priority patent/JP2023539533A/ja
Publication of WO2022048519A1 publication Critical patent/WO2022048519A1/zh
Priority to US18/176,620 priority patent/US20230209970A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0264—Details of the structure or mounting of specific components for a camera module assembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0266—Details of the structure or mounting of specific components for a display module assembly
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a terminal device.
  • holes are opened in the active display area of the display panel to provide space for the arrangement of the front camera.
  • packaging is usually performed around the punched area to form a packaging area; Make the connection of the horizontal wiring through the punched area, and the connection of the vertical wiring, the horizontal wiring and the vertical wiring are all wound around the packaging area to form a wiring area, and the packaging area and the wiring area cannot display content, As a result, a black border area is generated around the punched area. When the area of the border area is large, the display effect will be affected, resulting in a bad user experience.
  • the present application provides a display panel and a terminal device, which are used to reduce the area of a boundary area around a punched area and improve user experience.
  • a display panel in a first aspect, has an effective display area, a punched area located in the effective display area, and a boundary area surrounding the punched area; the above-mentioned effective display area is provided with a plurality of edge A first wiring extending in a first direction, and a second wiring extending along a second direction, wherein the first direction is perpendicular to the second direction; at least part of the extending direction of the first wiring passing through the punched area, The parts of each first wire arranged on both sides of the punched area are connected by a first winding to ensure that the parts of the first wire arranged on both sides of the punched area can be connected, and at least part of the first wire can be connected.
  • the windings are all located in the above-mentioned effective display area, so as to reduce the area of the boundary area occupied by the first windings, thereby reducing the area of the boundary area; and/or, at least part of the extending direction passes through the second routing in the punched area.
  • the parts of each second wire arranged on both sides of the above-mentioned punched area are connected by a second wire, and at least part of the second wire is located in the above-mentioned effective display area, so as to reduce the amount of the boundary area occupied by the second wire. area, which has the effect of reducing the area of the border region.
  • each of the first windings is located in the effective display area, and/or each of the second windings is located in the within the effective display area described above.
  • each first winding can have various forms, as long as it can bypass the punched area.
  • each first winding includes a first segment, a second segment and a third segment. segment, wherein the first segment extends along the first direction, and the second segment and the third segment both extend along the second direction; in each group of mutually corresponding first wirings and first windings, the second segment One end of the segment is connected to the part of the first trace on one side of the punched area, one end of the third segment is connected to the part of the first trace on the other side of the punched area, and the other end of the second segment passes through The first segment is connected to the other end of the third segment.
  • the probability of short circuit of the metal trace is reduced.
  • the first segment, the second segment and the third segment are arranged in layers with the corresponding first wiring, so as to simplify the metal wiring of each layer The complexity of the wiring is reduced, and the probability of short circuit is reduced.
  • both the second segment and the third segment are arranged in layers with the first segment, so that each segment of the first winding is distributed in different metal layers, and the same metal layer is further reduced probability of short circuit.
  • some of the first wirings are signal lines; in at least some of the signal lines, at least one side of each signal line in the second direction is provided with a first line. A segment, and/or, the signal line is stacked with a first segment.
  • each second winding can also have various forms, and each second winding includes a fourth section, a fifth section and a sixth section, wherein the fourth section is along the second section.
  • the fifth segment and the sixth segment both extend along the first direction; in each group of the second wiring and the second winding corresponding to each other, one end of the fifth segment and the second wiring are located in the punched hole.
  • the part of one side of the area is connected, one end of the sixth segment is connected to the part of the second trace on the other side of the punched area, and the other end of the fifth segment is connected to the other side of the sixth segment through the fourth segment. connected at one end.
  • the probability of short circuit of the metal trace is reduced.
  • the fourth segment, the fifth segment and the sixth segment are arranged in layers with the corresponding second wiring, so as to simplify the metal wiring of each layer The complexity of the wiring is reduced, and the probability of short circuit is reduced.
  • the fifth segment and the sixth segment are arranged in layers with the fourth segment. In order to distribute the segments of the second winding in different metal layers, the probability of short circuit in the same metal layer is further reduced.
  • the average resistance value per unit length of the first winding is lower than the corresponding average resistance value per unit length of the first wiring; and/or, the average resistance value per unit length of the second winding lower than the average resistance value per unit length of the corresponding second trace; in order to reduce the extra parasitic capacitance due to the wiring.
  • each of the first traces is arranged on both sides of the perforated area and is partially disconnected; and/or, among the second traces whose extension direction at least partially passes through the perforated area, each of the second traces is located on two sides of the perforated area. Partial open circuit on the side; this simplifies the wiring distribution in the active display area.
  • part of the first traces are light-emitting signal lines, and the two parts of the light-emitting signal lines whose extending direction passes through the perforated area are disconnected on both sides of the perforated area; and/or, part of the first traces
  • the lines are scanning lines, the scanning lines extending in the direction of passing through the punched area are divided into two parts on both sides of the punched area, and the lengths of the parts of the scanning lines arranged on both sides of the punched area are equal; and/or, some of the first One line is an initialization voltage line, and the two parts of the initialization voltage line extending through the punched area are separated on both sides of the punched area, and the two parts of the initialization voltage line arranged on both sides of the punched area are of equal length.
  • part of the second traces are drain voltage lines of the electroluminescent device; wherein, the drain voltage lines of the electroluminescent device whose extending direction passes through the perforated region are arranged on both sides of the perforated region. Partially disconnected.
  • a terminal device in a second aspect, can be a terminal device with a front camera such as a mobile phone, a tablet computer, and a smart watch.
  • the terminal device includes: a camera and a display panel provided by any of the above technical solutions, The camera is arranged on the side of the display panel away from the light-emitting surface, and is used to receive the light passing through the punched area for imaging.
  • the terminal device adopts the display panel provided by the above technical solution, the border area of the display panel is small, and the black borders around the camera due to the border area are small, which is beneficial to improve the aesthetics of the terminal device and the display effect.
  • FIG. 1 shows a schematic diagram of a partial structure of a display panel
  • FIG. 2 shows a display panel provided by an embodiment of the present application
  • Fig. 3a shows a partial enlarged view of A in Fig. 2;
  • Fig. 3b shows a schematic diagram of a first wiring and a second wiring in Fig. 3a being crossed;
  • Fig. 3c shows a partial enlarged view of Fig. 3a
  • Fig. 4 shows a schematic diagram of the distribution of the first wiring in Fig. 3a;
  • FIG. 5 shows a schematic diagram of a first wiring 1a in FIG. 4 cooperating with the first winding u1;
  • Fig. 6 shows the sectional view of the position B-B in Fig. 5;
  • Fig. 7 shows a schematic diagram of the distribution of the second wiring in Fig. 3a;
  • FIG. 8 shows a schematic diagram of a second wiring 2a in FIG. 7 cooperating with the second winding u2;
  • FIG. 9 shows a pixel circuit diagram of a pixel unit in the display panel 1 shown in FIG. 2;
  • Fig. 10 shows the circuit distribution diagram of the pixel circuit shown in Fig. 9;
  • FIG. 11 shows a specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10;
  • FIG. 12 shows another specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10;
  • FIG. 13 shows another specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10;
  • FIG. 14 shows another specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10;
  • Fig. 15 shows a variation of the embodiment shown in Fig. 4.
  • FIG. 16 shows a schematic diagram of the cooperation of a first wiring 1a with the first winding u1 in FIG. 15;
  • Fig. 17 shows a variation of the embodiment shown in Fig. 7;
  • FIG. 18 shows a schematic diagram of a second wiring 2a mating with the second winding u2 in FIG. 17;
  • Figure 19 shows a variation of the embodiment shown in Figure 17;
  • FIG. 20 shows a schematic diagram of the cooperation between the camera 2 and the display panel 1 in the terminal device provided by the embodiment of the present application;
  • FIG. 21 shows a schematic diagram of the cooperation between the camera 2 and the display panel 1 in another terminal device provided by an embodiment of the present application.
  • the display panel can be applied to terminal devices with front cameras, such as mobile phones, tablet computers, and smart watches, for outputting picture information.
  • the display panel can be one of an OLED (Chinese name: organic light-emitting diode; English full name: organic light-emitting diode) display screen and a microLED (Chinese name: micro light-emitting diode; English full name: micro light emitting diode) display screen, etc.
  • the OLED display screen may specifically be an AMOLED (Chinese name: active matrix organic light-emitting diode; English full name: active-matrix organic light-emitting diode) display screen.
  • FIG. 1 shows a schematic diagram of a partial structure of a display panel. Please refer to FIG. 1.
  • a display panel 01 (taking an AMOLED display screen as an example) has a circular punched area S1 in the middle, and the punched area S1 forms a camera avoidance hole. to transmit the light for the camera to image.
  • FIG. 1 only shows the wiring situation of the vertical wiring r1.
  • the display panel 01 also has horizontal wirings (not shown in FIG. 1 ) arranged alternately with the above vertical wirings.
  • the horizontal wiring near the packaging area S2 The wires form second sub-winding areas on the upper and lower sides of the packaging area (not shown in FIG. 1, the formation method can refer to the first sub-winding area), so that the first sub-winding area S3 and the second sub-winding area S3
  • the areas together form a winding area along the entire circumferential direction of the packaging area S2, and an effective display area S4 for displaying images is provided around the winding area.
  • the border area includes the packaging area S2, the winding area area and buffer S5.
  • embodiments of the present application provide a display panel.
  • FIG. 2 shows a display panel provided by an embodiment of the present application.
  • the display panel 1 includes an effective display area 12 , and a display panel located at the circumferential edge of the effective display area 12
  • the outline of the peripheral outer edge (denoted as the first boundary k1 ) of the effective display area 12 is roughly rectangular, and specifically, the four right corners of the rectangle may be chamfered.
  • the first boundary k1 includes a first side a, a second side b, a third side c and a fourth side d, wherein the first side a and the second side b are opposite and parallel to each other ( Both are exemplarily parallel to the y-axis), the third side c and the fourth side d are oppositely arranged and parallel to each other (both are exemplarily parallel to the x-axis), and the third side c is connected to the first side a
  • the top one end in the positive direction of the y-axis
  • the top of the second side b one end in the positive direction of the y-axis
  • the fourth side d connects the bottom end of the first side a (one end in the negative direction of the y-axis) and
  • a chamfer is formed between every two adjacent side edges.
  • the punched area 11 forms a light-transmitting hole, and the light-transmitting hole can be in the form of forming a through hole penetrating the display panel 1 in the punching area 11 , or etching away the display panel 1 in the punching area 11 to remove the transparent lining
  • the perforated area 11 transmits light, so that the camera can image images through the light transmitted through the perforated area 11.
  • the light transmission holes in the perforated area 11 can be formed in the following way Known and commonly used forms will not be repeated here.
  • the punched area 11 may be circular, or may be in other forms such as an ellipse and a regular polygon. The following description will be given by taking the punched area 11 as a circle as an example.
  • FIG. 3 a shows a partial enlarged view of the part A in FIG. 2 .
  • an isolation column or an isolation groove surrounding the punched area 11 is formed on the substrate, and it may also have an isolation column and an isolation groove at the same time. Specifically, it may be formed by etching the film layer on the substrate of the display panel 1 The above-mentioned isolation column or isolation groove.
  • the effective display area 12 has a receiving area inside, the edge of the receiving area is denoted as the second boundary k2, the packaging area 13 is located in the above-mentioned receiving area, and a buffer is formed between the outer edge of the packaging area 13 and the second boundary k2 In the area (dummy area) 15, no display device is provided on the substrate in the buffer area 15.
  • the closed first boundary k1 and the closed second boundary k2 are used to define the range of the effective display area 12 .
  • the wiring distribution in the effective display area 12 will be introduced below.
  • a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a first metal layer M1 and a second metal layer are sequentially formed along the direction away from the substrate.
  • the material of M2 can be made of metal Mo
  • the material of the third metal layer M3 and the fourth metal layer M4 can be made of Ti/Al/Ti laminated structure.
  • the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 are all patterned to form patterns such as metal traces, and the first metal layer M1 and the second metal layer M2 are , between the second metal layer M2 and the third metal layer M3, and between the third metal layer M3 and the fourth metal layer M4, one or more insulating layers are formed to separate the adjacent two layers of metal from Lines are electrically isolated, and metal traces formed by different metal layers can be connected through vias.
  • a plurality of first traces (1a and 1b) extending along the first direction (y-axis direction) and arranged along the second direction (x-axis direction) are distributed, and , a plurality of second wirings (2a and 2b) extending along the second direction (x-axis direction) and arranged along the first direction (y-axis direction).
  • a plurality of second wirings (2a and 2b) extending along the second direction (x-axis direction) and arranged along the first direction (y-axis direction).
  • the above-mentioned plurality of first wirings (1a and 1b) and the above-mentioned plurality of second wirings (2a and 2b) are crossed to form a plurality of pixel units distributed in an array.
  • first traces (1a and 1b) extend along the first direction, either strictly in the first direction (y-axis direction), or there may be a certain angle error with the first direction, and the angle error can be within ⁇ Within the range of 3°; the second traces (2a and 2b) extend along the second direction (x-axis direction), and the meanings of other traces extending in a certain direction refer to the aforementioned first traces (1a and 1b).
  • first direction is the x-axis direction
  • second direction is the y-axis direction
  • first direction is strictly perpendicular to the second direction
  • first direction is perpendicular to the second direction
  • the two may not be strictly vertical, and a certain angular deviation is allowed, for example, an angular deviation of ⁇ 3°.
  • Fig. 3b shows a schematic diagram of the intersection of a first line and a second line in Fig. 3a.
  • the first line 1a and the second line 2a They are located on different metal layers, the overlapping part of the first trace 1a and the second trace 2a is narrower than the rest of the two sides of the part, and the overlapping part of the second trace 2a and the first trace 1a is also relatively
  • the other portions at both ends of the overlapping portion are narrow to reduce the parasitic capacitance between the first trace 1a and the second trace 2a.
  • the two traces extending in the same direction can also be staggered to reduce parasitic capacitance. For example, in FIG.
  • the first trace 1a and the first trace 1b are arranged in different layers, but are staggered, the orthographic projection of the first trace 1a on the substrate surface (exemplarily parallel to the xoy plane) and the second trace
  • the orthographic projections of 2b on the substrate surface are staggered to reduce parasitic capacitance.
  • Fig. 3c shows a partial enlarged view of Fig. 3a
  • Fig. 4 shows a schematic diagram of the distribution of the first wiring in Fig. 3a.
  • Fig. 3a, Fig. 3c and Fig. 4 for the extension directions of some of the first wirings (1a and 1b). Passing through the accommodating area enclosed by the second boundary k2, or in other words, the straight lines where some of the first traces (1a and 1b) are located pass through the accommodating area enclosed by the second boundary k2, and are interrupted at the second boundary k2.
  • the two segments of the wiring 1a located on both sides of the accommodation area enclosed by the second boundary k2 are connected by the first winding u1.
  • first traces (1a and 1b) are located here does not mean that the first traces (1a and 1b) extend strictly along a straight line.
  • the above is an extension of a roughly straight line, and similar situations will be understood in the same way, and will not be repeated here.
  • FIG. 5 shows a schematic diagram of the cooperation between a first trace 1a and a first winding u1 in FIG. 4 .
  • An extension direction in FIG. 4 passes through the accommodation area enclosed by the second boundary k2
  • the first trace 1a includes a sub-segment 104 and a sub-segment 105, the sub-segment 104 and the sub-segment 105 are on the same straight line, and are isolated and disconnected by the second boundary k2, and the sub-segment 104 is located in On one side of the punched area 11, the subsection 105 is located on the other side of the punched area 11;
  • the first winding u1 includes a first section 101, a second section 102 and a third section 103, wherein the first section The segment 101 extends along the first direction (y-axis direction), the second segment 102 and the third segment 103 are parallel to each other and both extend along the second direction (x-
  • One end on the y-axis of the sub-segment 104 is connected to one end in the negative direction of the y-axis
  • one end of the third segment 103 in the negative direction of the x-axis is connected to one end of the One end in the positive direction of the axis is connected with one end in the positive direction of the x-axis of the second segment 102
  • one end in the negative direction of the y-axis of the first segment 101 is connected with one end in the positive direction of the x-axis of the third segment 103;
  • the segment 102 , the first segment 101 and the third segment 103 are sequentially connected to form a "U"-shaped structure, and the opening direction of the "U"-shaped structure faces the punched area 11 .
  • the second segment 102, the first segment 101 and the third segment 103 of the first winding u1 are all located in the effective display area 12 without occupying the space in the accommodation area enclosed by the second boundary k2.
  • the area of the border area formed between k2 and the edge of the punched area 11 is small, which is beneficial to improve the display quality of the display panel 1 and improve the user experience.
  • the second segment 102, the first segment 101 and the third segment 103 all extend in the first direction or the second direction, which is conducive to regular arrangement of metal traces and avoids intersections between metal traces on the same layer. Improve the density of metal traces.
  • each of the above first windings u1 is located in the effective display area 12 is only an example, when only part of the first windings u1 are located in the effective display area 12, and another part of the first windings u1 are located in the boundary area. Compared with all the first windings u1 located in the boundary area, the effect of the area of the boundary area can also be reduced to a certain extent.
  • each first wiring 1a is disposed adjacent to a first wiring 1b, and the first wiring 1b forms the drain voltage of the electroluminescent device in the pixel circuit (full English name: electroluminescent voltage drain device; abbreviation: ELVDD) line, part of the straight line where the first trace 1b is located passes through the accommodation area enclosed by the second boundary k2, and is cut off by the second boundary k2 into sub-segments 106 and 107, and is cut off by the second boundary k2. There is an open circuit between the two parts of the trace 1b, and there is no connection by means of wire winding or the like.
  • ELVDD electroluminescent voltage drain device
  • the display panel 1 also includes lateral connecting lines ( 1c and 1c ′) arranged on both sides of the punched area 11 ;
  • the segment 106 is connected to the other continuous (unbroken) first traces 1b so that the sub-segments 106 have the same potential as the other unbroken first traces 1b;
  • the lateral connection 1c' is in the second direction (x-axis direction) connect each of the first traces 1b in turn, and connect the sub-segment 107 to the other undisconnected first traces 1b, so that the sub-segment 107 is connected to the other undisconnected first traces 1b
  • electrodes of the same potential are formed in different pixel units.
  • each first wiring 1a belongs to the third metal layer M3, and each first wiring 1b, lateral connecting lines (1c and 1c') and the first winding u1 belong to the fourth metal layer M4.
  • FIG. 6 shows a cross-sectional view at the position of BB in FIG. 5 .
  • the cross-sectional view also shows a cross-section of the film layer adjacent to the second segment 102 and the sub-segment 104. Please refer to FIG. 6 for the second segment 102 and the sub-segment.
  • the connection of 104 is exemplified.
  • an insulating layer p2, a second segment 102, a gate insulating layer (full name in English: gate insulation; abbreviation: GI) p3, and an interlayer dielectric layer (full name in English: inter layer dielectric; abbreviation: ILD) are sequentially disposed on the glass substrate p1 ) p4, the insulating layer p2 sequentially includes a polyimide (English full name: polyimide; abbreviation: PI) layer, a buffer (English full name: buffer) layer and a gate insulating layer along the direction away from the glass substrate p1, and the subsection 104 passes through The via hole passing through the gate insulating layer p3 and the interlayer dielectric layer p4 is in contact with and electrically connected to the second segment 102 to realize electrical connection with the second segment 102; wherein, the gate insulating layer p3 and the interlayer dielectric layer p4 thickness of approx.
  • the electrical connection forms of metal wiring
  • FIG. 7 shows a schematic diagram of the distribution of the second wiring in FIG. 3a.
  • the extension directions of some of the second wirings (2a and 2b) pass through the accommodation area enclosed by the second boundary k2, or in other words, the straight lines where some of the second wirings (2a and 2b) are located pass through the second
  • the accommodating area enclosed by the boundary k2 is interrupted at the second boundary k2, and the two segments of each second wiring 2a located on both sides of the accommodating area enclosed by the second boundary k2 are connected by the second winding u2.
  • FIG. 8 shows a schematic diagram of the cooperation between a second trace 2a and a second winding u2 in FIG. 7.
  • the second trace 2a includes a sub-segment 204 and a sub-segment 205 extending along the second direction, the sub-segment 204 and the sub-segment 205 are on the same straight line, and are isolated and disconnected by the second boundary k2 Connected, the sub-segment 204 is located on one side of the punched area 11, and the sub-segment 205 is located on the other side of the punched area 11;
  • the second winding u2 includes the fourth segment 201, the fifth segment 202 and the sixth segment 203 , wherein the fourth segment 201 extends along the second direction (x-axis direction), the fifth segment 202 and the sixth segment 203 are parallel to each other and both extend along the first direction (y-axis direction), and the fifth segment One end in the negative
  • each of the above second windings u2 is located in the effective display area 12 is only an example, when only part of the second windings u2 are located in the effective display area 12, and another part of the second windings u2 are located in the boundary area. Compared with all the second windings u2 located in the boundary area, the effect of the area of the boundary area can also be reduced to a certain extent.
  • the first trace 2a is located in the first metal layer M1
  • the second trace 2b and the fourth segment 201 are located in the second metal layer M2
  • the fifth segment 202 and the sixth segment 203 are located in the third metal layer M3. Since the resistivity of the material of the third metal layer M3 is lower than the resistivity of the material of the first metal layer M1, the resistances of the fifth segment 202 and the sixth segment 203 of the wiring segment increased due to the increase of the wiring are smaller, thus, Try to avoid adding more load due to winding.
  • the thickness of the second metal layer M2 and/or the third metal layer M3 can also be increased, or, by increasing the width of the second metal layer M2 or the third metal layer M3, the thickness of the first winding u1 can be increased.
  • the average resistance value per unit length of the first winding u1 can be lower than the average resistance value per unit length of the corresponding first wiring.
  • the average resistance value per unit length of the second winding segment u2 is also lower than the average resistance value per unit length of the corresponding second wire.
  • the display panel 1 includes a plurality of pixel units distributed in an array, and each pixel unit forms a pixel circuit through first wiring, second wiring, semiconductor wiring and other metal wirings passing through the pixel unit.
  • FIG. 9 shows a pixel circuit diagram of a pixel unit in the display panel 1 shown in FIG. 2 , please refer to FIG. 9 , the pixel circuit is a known and commonly used 7T1C pixel circuit, and details are not repeated here.
  • E1 represents the drain voltage line of the electroluminescent device (English full name: electroluminescent voltage drain device; abbreviation: ELVDD) line
  • the drain voltage line of the electroluminescent device can be formed by the combination of the third metal layer M3 and the fourth metal layer M4
  • E2 represents the source voltage of the electroluminescent device (English full name: electroluminescent voltage source device; abbreviation: ELVSS) line
  • EM1 and EM2 both represent the luminescent signal (English full name: eimt; referred to as EM) line
  • R1 and R2 both represent the RST line
  • V1 stands for Vinit (Chinese name: initialization voltage; English name: initial voltage) line
  • D1 stands for signal line (date line)
  • D2 stands for DTFT (Chinese name: drive transistor ; English full name: drive thin film transistor)
  • G1 and G2 both represent scan lines (English full name: scan line)
  • C1 represents Cst capacitor
  • a first metal electrode layer c11 adjacent to and electrically connected to the second wiring 2b is formed in the second metal layer M2, and a first metal electrode layer c11 opposite to the first metal electrode layer c11 is formed in the first metal layer M1.
  • the two metal electrode layers c12, the first metal electrode layer c11 and the second metal electrode layer c12 cooperate to form the Cst capacitor C1.
  • T1, T2, T3, T4, T5, T6 and T7 all represent thin film transistor switches.
  • Fig. 10 shows the circuit distribution diagram of the pixel circuit shown in Fig. 9, and Fig. 10 only shows the distribution of some circuits in Fig. 9.
  • the same reference numerals in Fig. 10 as in Fig. 9 have the same meaning, and 011, 012, 013 , 014, 015, and 016 all represent semiconductor traces.
  • the connection relationship of each wiring in the pixel circuit may be a known and commonly used connection manner.
  • the signal line D1 extends along the first direction (y-axis direction), and is located on the left side (one side in the negative x-axis direction) of the entire pixel circuit.
  • the following describes the distribution of the first winding u1 in the pixel circuit.
  • FIG. 11 shows a specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10 .
  • the first segment 101 in the first winding u1 is stacked with the signal line D1, that is, the first segment 101 is located on the side of the signal line D1 away from the substrate, or on the side of the signal line D1 facing the substrate. side.
  • the orthographic projection of the first segment 101 on the substrate surface may overlap or substantially overlap with the orthographic projection of the signal line D1 on the substrate surface.
  • FIG. 12 shows another specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10 .
  • the orthographic projection of the first segment 101 in the first winding u1 on the substrate is located in the orthographic projection of the signal line D1 on the substrate and the electroluminescent device drain voltage line E1 on the substrate surface between the orthographic projections of , the parasitic capacitance between the first segment 101 and the signal line D1 can be reduced, thereby reducing signal crosstalk.
  • FIG. 13 shows another specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10 .
  • the orthographic projection of the first segment 101 in the first winding u1 on the substrate is located to the left (one side in the negative direction of the x-axis) of the orthographic projection of the signal line D1 on the substrate, which can be reduced by The magnitude of the parasitic capacitance between the first segment 101 and the signal line D1 is small.
  • FIG. 14 shows another specific embodiment of the distribution of the first winding u1 in the pixel circuit shown in FIG. 10 .
  • the orthographic projection of the first segment 101 in a first winding u1 on the substrate is located in the orthographic projection of the signal line D1 on the substrate and the drain voltage line E1 of the electroluminescent device is on the surface of the substrate Between the orthographic projections on the substrate, the orthographic projection of the first segment 101 in the other first winding u1 on the substrate is located on the left side of the orthographic projection of the signal line D1 on the substrate (one side in the negative direction of the x-axis). ).
  • a first winding u1 can also be set at the same time.
  • the first segment 101 of the first winding u1 is stacked with the signal line D1.
  • the first winding u1 refers to the form of FIG. 11 . .
  • two first windings u1 pass through one pixel unit, one of the first windings u1 adopts the winding method of FIG. 12 , and the other first winding u1 adopts the winding method of FIG. 11 .
  • one of the first windings u1 adopts the winding method of FIG. 13
  • the other first winding u1 adopts the winding method of FIG. 11 .
  • FIG. 12 to 14 the effects of the winding forms in FIG. 12 to FIG. 14 are analyzed below, in which a signal line D1 (first trace 1 a ) whose extension direction passes through the punched area 11 is taken as an example for description.
  • Table 1 shows the simulation results using the three winding schemes shown in Figure 12 to Figure 14 respectively.
  • A1 represents the wiring scheme shown in Figure 13
  • A2 represents the wiring scheme shown in Figure 12
  • A3 represents the wiring scheme shown in Figure 14
  • B1 represents the parasitics between the first winding u1 and other traces
  • the sum of capacitances (the sum of B11 and B12)
  • B11 represents the parasitic capacitance of the second segment 102 and other wirings in the first winding u1 and the sum of the parasitic capacitances of the second segment 103 and other wirings
  • B2 represents the extension
  • B3 represents the sum of B1 and B2
  • B4 represents the extension direction that does not pass through the perforated area 11.
  • Table 1 the units of the values corresponding to B11, B12, B2, B3, B4 and B5 are all pF (picofarads).
  • the rate of change of the current in the signal line D1 (the first trace 1a) whose extending direction passes through the punched area 11 is also an important reference for selecting the routing scheme. index.
  • G15, G31, G63, G111, G127, G143 and G255 represent different grayscale values, respectively.
  • A1 represents the winding scheme shown in FIG. 13
  • a1 represents the current value of the signal line D1 whose extension direction passes through the punched area 11 in the A1 scheme
  • v1 represents the rate of change of a1 relative to a0
  • v1 (a1-a0)/a0 ;
  • A2 represents the winding scheme shown in FIG. 12
  • a2 represents the current value of the signal line D1 whose extension direction passes through the punched area 11 in the A2 scheme
  • v2 represents the rate of change of a2 relative to a0
  • v2 (a2-a0)/ a0
  • A3 represents the winding scheme shown in FIG. 14
  • a3 represents the current value of the signal line D1 whose extension direction passes through the punched area 11 in the A3 scheme
  • v3 represents the rate of change of a3 relative to a0
  • v3 (a3-a0 )/a0.
  • the arrangement positions of the fifth segment 202 and the sixth segment 203 in each second winding u2 relative to the signal line D1 may refer to the wiring manner of the first segment 101 in the first winding u1 described above.
  • FIG. 15 shows a modification of the embodiment shown in FIG. 4
  • FIG. 16 shows a schematic diagram of a first wiring 1a mating with the first winding u1 in FIG. 15 .
  • the difference between FIG. 16 and FIG. 5 is that the first winding In the line u1, both the second segment 102 and the third segment 103 are located in the second metal layer M2, while the first segment 101 is still located in the fourth metal layer M4, and the second segment 102 and the third segment 103 pass through respectively
  • the vias are electrically connected to the first segment 101
  • each of the first windings in FIG. 15 refers to the arrangement in FIG. 16 .
  • the disconnection setting can prevent the first segment 101 from interrupting the traces in the second metal layer M2 that are located between the second segment 102 and the third segment 103 and extend in the second direction. Compared with the case where the first windings u1 are all located in the fourth metal layer M4, cross short circuits can be avoided.
  • FIG. 17 shows a modification of the embodiment shown in FIG. 7
  • FIG. 18 shows a schematic diagram of the cooperation of a second wiring 2a and the second winding u2 in FIG. 17
  • the difference between FIG. 18 and FIG. 8 is that the fifth point Both the segment 202 and the sixth segment 203 are located in the fourth metal layer M4 instead of the third metal layer M3, and the fourth segment 201 is still located in the second metal layer M2.
  • the fifth segment and the sixth segment are provided in layers with the fourth segment, so as to facilitate the fourth metal layer M4 and avoid short circuits.
  • fourth, fifth and sixth sections can also be arranged on the same layer, as long as in each second winding, the fourth, fifth and sixth sections are the same as the The corresponding second traces are arranged in layers to facilitate wiring.
  • the winding position of the first winding u1 in the pixel unit refers to the form in FIG. 14 , which is denoted as scheme A4, and the data in Table 3 is obtained through simulation experiments.
  • the headers in Table 3 that are the same as those in FIG. 1 , reference may be made to the description of Table 1.
  • a4 represents the current value of the signal line D1 whose extending direction passes through the punched area 11 in the A4 scheme
  • v4 represents the change rate of a4 relative to a0
  • v4 (a4-a0)/a0.
  • the distribution of the first traces shown in FIG. 15 and the distribution of the second traces shown in FIG. 17 are combined together to obtain a graph with both the distribution of the first traces and the distribution of the second traces.
  • FIG. 19 shows a modification of the embodiment shown in FIG. 17. Please refer to FIG. 19. The difference between the embodiment shown in FIG. 19 and the embodiment shown in FIG. 17 is that all the first windings u1 are cancelled.
  • the second traces 2a can all be scan lines (refer to G1 and G2 in FIG. 9 ).
  • the length of the part located on the left side of the punched area 11 is the same as the length of the part located on the left side of the punched area 11 .
  • the lengths of the parts on the right side of the punched area 11 are the same to ensure that the parts of each scan line on both sides of the punched area 11 are driven separately with the same load and the same delay. It should be noted that the lengths of the scan lines on different sides of the punched area 11 may be the same in a strict sense, or there may be a certain error, and the error may be within 5% of the shorter portion of the scan line.
  • the second trace 2a may be a light-emitting signal line (refer to E1 and E2 in FIG. 9 ), and in the light-emitting signal line disconnected at the punched area 11, the length of the part located on the left side of the punched area 11 No matter whether the length is the same or different from that of the part located on the right side of the punched area 11 , whether the length is the same or not, the difference in delay is small.
  • the second trace 2b may be an initialization voltage line (refer to V1 in FIG. 9 ).
  • the length of the part located on the left side of the punched area 11 is the same as the length of the part located at the left of the punched area 11
  • the portion to the right of the punched area 11 is of the same length to minimize signal delay differences.
  • the first wiring 1a may be a signal line D1, and the parts of the signal line D1 on different sides of the punched area 11 are connected by the first winding u1.
  • the first trace 1b may be the drain voltage line E1 of the electroluminescence device, and the parts of the drain voltage line E1 of the electroluminescence device on different sides of the punched region 11 may be disconnected, that is, not connected by the first wire, or It can be connected through the first wire, so that the load difference of the parts of the drain voltage line E1 of the electroluminescent device located on different sides of the punched region 11 is small, and the delay difference is not obvious.
  • lateral connection lines (1c and 1c') extending along the second direction may be used to connect the different electroluminescent device drain voltage lines E1.
  • lateral connecting lines (1c and 1c') extending along the second direction may be used to connect the different electroluminescent device drain voltage lines E1.
  • each of the first wirings arranged on both sides of the punched area is partially disconnected; and /or, in order to reduce the arrangement of the second windings, at least part of the second wirings whose extending direction passes through the punched area, each of the second wirings arranged on both sides of the punched area is partially disconnected.
  • the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 are used to form each segment of wiring, and different wirings are connected together through vias, but this It is only an example, three metal layers, five layers or other layers of metal layers may also be provided, and corresponding wirings are formed by patterning each metal layer.
  • first wiring extending along the first direction and the corresponding first winding, and the second wiring extending along the second direction and the corresponding second winding have been separately introduced above, it should be noted that , with regard to the characteristics of the first routing and the corresponding first routing, and, the characteristics of the second routing and the corresponding second routing can be freely combined, for example, a specific embodiment can cover the first routing and the corresponding first routing
  • the related features of the wire, or, the related features of the second wiring and the corresponding second winding, or, have the features of the above two aspects at the same time.
  • an embodiment of the present application also provides a terminal device, and the terminal device may be a terminal device with a front camera, such as a mobile phone, a tablet computer, and a smart watch.
  • FIG. 20 shows a schematic diagram of the cooperation between the camera 2 and the display panel 1 in the terminal device provided by the embodiment of the present application. Please refer to FIG. 20 .
  • the terminal device includes the camera 2 and the display panel 1 provided in the foregoing embodiment.
  • the camera 2 is located on the display panel 1 The side away from the light-emitting surface, and the lighting window of the camera 2 is arranged opposite to the punched area 11 of the display panel 1, and the ambient light is directly transmitted to the lighting window of the camera 2 through the punched area 11, and is collected and imaged by the camera 2.
  • FIG. 21 shows a schematic diagram of the cooperation between the camera 2 and the display panel 1 in another terminal device provided by an embodiment of the present application.
  • the difference between FIG. 21 and FIG. 20 is that the side of the display panel 1 facing away from the light-emitting surface also A periscope 3 is provided, and the reflective surface of the periscope 3 is at an acute angle, such as 45°, with the light output of the display panel 1, and the optical axis of the camera 2 is exemplarily parallel to the light emitting surface of the display panel 1.
  • the hole area 11 is opposite and opposite to the lighting window of the camera 2 .
  • the ambient light from the outside is directed to the reflection surface of the periscope 3 through the perforated area 11 , and is reflected to the lighting window of the camera 2 through the reflection surface, so as to form an image in the camera 2 .
  • FIG. 20 and FIG. 21 are only exemplary, as long as the camera 2 is disposed on the side of the display panel 1 away from the light emitting surface to receive the light passing through the punched area for imaging.
  • orientation terms such as “upper” and “lower” are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative In the description and clarification of the drawings, it may change correspondingly according to the change of the orientation in which the components are placed in the drawings.

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Abstract

本申请提供了一种显示面板及终端设备，显示面板具有有效显示区域，位于有效显示区域内的打孔区域，以及围绕打孔区域的边界区域；有效显示区域设有多根沿第一方向延伸的第一走线，以及沿第二方向延伸的第二走线，第一方向垂直于第二方向；至少部分延伸方向经过打孔区域的第一走线中，每根第一走线分列于打孔区域两侧的部分通过一根第一绕线连接，确保第一走线分列于打孔区域两侧的部分连通，至少部分第一绕线位于上述有效显示区域，减小第一绕线占用边界区域的面积；和/或，至少部分延伸方向经过打孔区域的第二走线中，每根第二走线分列于打孔区域两侧的部分通过一根第二绕线连接，至少部分第二绕线位于上述有效显示区域，减少边界区域的面积。

Description

一种显示面板及终端设备
相关申请的交叉引用
本申请要求在2020年09月02日提交中国专利局、申请号为202010909030.X、申请名称为“一种显示面板及终端设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及到显示技术领域，尤其涉及到一种显示面板及终端设备。
背景技术
随着用户对手机等终端设备屏占比要求的提高，且同时兼顾前置摄像头的设计，市场上出现了水滴屏、打孔屏和刘海屏等屏占比接近于全面屏的产品。
对于打孔屏，如AMOLED(active-matrix organic light-emitting diode，主动矩阵有机发光二极管)屏，通过在显示面板的有效显示区域(active area)内开孔，为前置摄像头的布置提供空间。
而为了避免水氧使面板中材料失效，导致黑斑等不良影响，以及防止打孔时出现裂纹和减小对面板材料的热影响，通常在打孔区域周边进行封装，形成封装区；而为了使经过打孔区域的横向走线的连接，以及，纵向走线的连接，横向走线和纵向走线均在封装区周边绕线，形成绕线区，封装区和绕线区不能显示内容，导致打孔区域周边产生黑色的边界区域(border area)，该边界区域面积较大时会影响显示效果，造成不好的用户体验。
发明内容
本申请提供了一种显示面板及终端设备，用以减小打孔区域周边的边界区域面积，提高用户体验。
第一方面，提供了一种显示面板，该显示面板具有有效显示区域，位于该有效显示区域内的打孔区域，以及，围绕该打孔区域的边界区域；上述有效显示区域设有多根沿第一方向延伸的第一走线，以及，沿第二方向延伸的第二走线，其中，第一方向垂直于第二方向；至少部分延伸方向经过上述打孔区域的第一走线中，每根第一走线分列于上述打孔区域两侧的部分通过一根第一绕线连接，以确保该第一走线分列于打孔区域两侧的部分能够连通，至少部分第一绕线均位于上述有效显示区域内，以减小第一绕线占用边界区域的面积，从而，降低边界区域的面积；和/或，至少部分延伸方向经过上述打孔区域的第二走线中，每根第二走线分列于上述打孔区域两侧的部分通过一根第二绕线连接，至少部分第二绕线位于上述有效显示区域内，以减少第二绕线占用边界区域的面积，起到缩小边界区域的面积的效果。
为进一步减小边界区域的面积，在一个具体的可实施方案中，每根所述第一绕线均位于所述有效显示区域内，和/或，每根所述第二绕线均位于所述有效显示区域内。
第一绕线的形式可以有多种，只要能够绕过打孔区域即可，在一个具体的可实施方案 中，每根第一绕线包括第一分段、第二分段和第三分段，其中，第一分段沿第一方向延伸，第二分段和第三分段均沿第二方向延伸；每一组相互对应的第一走线和第一绕线中，第二分段的一端与第一走线位于打孔区域的一侧的部分连接，第三分段的一端与第一走线位于打孔区域的另一侧的部分连接，第二分段的另一端通过第一分段与第三分段的另一端连接。在确保第一绕线能够绕过打孔区域的前提下，降低金属走线短路概率。
在一个具体的可实施方案中，每根第一绕线中，第一分段、第二分段和第三分段均与对应的第一走线分层设置，以简化每层金属走线的布线复杂程度，降低短路的概率。
在一个更具体的可实施方案中，第二分段和第三分段均与第一分段分层设置，以将第一绕线的各段分布于不同金属层中，进一步降低同一金属层中短路的概率。
为减小因设置第一绕线增加的寄生电容，减少信号电容串扰，部分第一走线为信号线；至少部分信号线中，每根信号线的第二方向上的至少一侧设置一个第一分段，和/或，信号线与一个第一分段层叠设置。
与第一绕线类似地，第二绕线也可以有多种形式，每根第二绕线包括第四分段、第五分段和第六分段，其中，第四分段沿第二方向延伸，第五分段和第六分段均沿第一方向延伸；每一组相互对应的第二走线和第二绕线中，第五分段的一端与第二走线位于打孔区域的一侧的部分连接，第六分段的一端与第二走线位于打孔区域的另一侧的部分连接，第五分段的另一端通过第四分段与第六分段的另一端连接。在确保第一绕线能够绕过打孔区域的前提下，降低金属走线短路概率。
在一个具体的可实施方案中，每根第二绕线中，第四分段、第五分段和第六分段均与对应的第二走线分层设置，以简化每层金属走线的布线复杂程度，降低短路的概率。
在一个具体的可实施方案中，每根第二绕线中，第五分段和第六分段均与第四分段分层设置。以将第二绕线的各段分布于不同金属层中，进一步降低同一金属层中短路的概率。
在一个具体的可实施方案中，第一绕线的单位长度的平均电阻值低于对应的第一走线单位长度的平均电阻值；和/或，第二绕线的单位长度的平均电阻值低于对应的第二走线单位长度的平均电阻值；以降低因绕线额外增加的寄生电容。
除了采用绕线的方式，为减小边界区域的面积，一些走线也可以直接断路设置，例如，在一个具体的可实施方案中，至少部分延伸方向经过打孔区域的第一走线中，每根第一走线分列于打孔区域两侧的部分断路；和/或，至少部分延伸方向经过打孔区域的第二走线中，每根第二走线分列于打孔区域两侧的部分断路；可简化有效显示区域内的线路分布。
在一个具体的可实施方案中，部分第一走线为发光信号线，延伸方向经过打孔区域的发光信号线分列于打孔区域两侧的两部分断路；和/或，部分第一走线为扫描线，延伸方向经过打孔区域的扫描线分列于打孔区域两侧的两部分断路，且扫描线分列于打孔区域两侧的部分的长度相等；和/或，部分第一走线为初始化电压线，延伸方向经过打孔区域的初始化电压线分列于打孔区域两侧的两部分断路，且初始化电压线分列于打孔区域两侧的部分的长度相等。
在一个具体的可实施方案中，部分第二走线为电致发光器件漏极电压线；其中，延伸方向经过打孔区域的电致发光器件漏极电压线分列于打孔区域两侧的部分断路。
第二方面，提供一种终端设备，该终端设备可以是手机、平板电脑和智能手表等具有前置摄像头的终端设备，该终端设备包括：摄像头和如上述任一项技术方案提供的显示面板，摄像头设置于显示面板背离出光面的一侧，用于接收经过打孔区域的光线，以进行成 像。
由于终端设备采用了上述技术方案提供的显示面板，显示面板的边界区域较小，摄像头周围因边界区域产生的黑边较小，有利于提高终端设备的美观度，同时提升显示效果。
附图说明
图1表示出了一种显示面板的局部结构示意图；
图2表示出了本申请实施例提供的一种显示面板；
图3a表示出了图2中的A处局部放大图；
图3b表示出图3a中一条第一走线与一条第二走线交叉设置的示意图；
图3c表示出图3a的局部放大图；
图4表示出图3a中第一走线的分布示意图；
图5表示出了图4中的一条第一走线1a与第一绕线u1配合的示意图；
图6表示出了图5中B-B位置的剖面图；
图7表示出图3a中第二走线的分布示意图；
图8表示出了图7中的一条第二走线2a与第二绕线u2配合的示意图；
图9表示出了图2所示显示面板1中的一个像素单元的像素电路图；
图10表示出图9所示像素电路的线路分布图；
图11表示出第一绕线u1在图10所示像素电路中的分布的一种具体实施例；
图12表示出第一绕线u1在图10所示像素电路中的分布的另一种具体实施例；
图13表示出第一绕线u1在图10所示像素电路中的分布的另一种具体实施例；
图14表示出第一绕线u1在图10所示像素电路中的分布的另一种具体实施例；
图15表示出图4所示实施例的一种变形；
图16表示出图15中一条第一走线1a与第一绕线u1配合的示意图；
图17表示出图7所示实施例的一种变形；
图18表示出图17中一条第二走线2a与第二绕线u2配合的示意图；
图19表示出图17所示实施例的一种变形；
图20表示出了本申请实施例提供的终端设备中摄像头2与显示面板1配合的示意图；
图21表示出了本申请实施例提供的另一种终端设备中摄像头2与显示面板1配合的示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
为了方便理解本申请实施例提供的显示面板，首先说明一下其应用的场景，该显示面板可以应用于手机、平板电脑和智能手表等具有前置摄像头的终端设备中，用于输出画面信息。该显示面板可以是OLED(中文名称：有机发光二极管；英文全称：organic light-emitting diode)显示屏和microLED(中文名称：微发光二极管；英文全称：micro light emitting diode)显示屏等中的一种。其中，OLED显示屏具体可以是AMOLED(中文名称：主动矩阵有机发光二极管；英文全称：active-matrix organic light-emitting diode)显示屏。
图1表示出了一种显示面板的局部结构示意图，请参考图1，显示面板01(以AMOLED显示屏为例)中部具有圆形的打孔区域S1，该打孔区域S1形成摄像头避让孔，以透过光线供摄像头成像。环绕该打孔区域S1形成有环形的封装区S2，封装区S2内形成隔离柱和/或隔离槽，起防止水氧扩散的作用；封装区S2附近的每根纵向走线r1通过绕线r2在打孔区域S1左侧或右侧绕线，绕线r2呈开口朝向封装区S2的弧形，封装区S2附近的多根绕线r2在封装区S2左右两侧形成第一子绕线区S3。图1中仅是表示出了纵向走线r1的绕线情况，该显示面板01还具有与上述纵向走线交错设置的横向走线(图1中未示出)，封装区S2附近的横向走线在封装区的上下两侧形成第二子绕线区(图1中未示出，形成方式可参考第一子绕线区)，从而，第一子绕线区S3和第二子绕线区在封装区S2的整个圆周方向上共同形成绕线区，而绕线区周围设有用于显示画面的有效显示区域S4。绕线区与有效显示区域S4之间具有一定缓冲区(dummy area)S5，缓冲区S5内不设置显示器件。由于绕线区的存在，打孔区域S1周边不能布置显示器件而呈黑色的边界区域(border area)面积较大，影响显示效果，用户体验较差，其中，边界区域包括封装区S2、绕线区和缓冲区S5。
为了解决上述技术问题，本申请实施例提供一种显示面板。
图2表示出了本申请实施例提供的一种显示面板，参考图2，以该显示面板1应用于手机为例，该显示面板1包括有效显示区域12、位于有效显示区域12周向边缘的周边区域14和位于有效显示区域12内部的打孔区域11，其中，有效显示区域12用于显示画面，周边区域14是非显示区域。有效显示区域12的周向外边缘(记为第一边界k1)的轮廓大致呈矩形，具体可以是矩形的四个直角处形成倒角后的形状。例如，第一边界k1包括第一侧边a、第二侧边b、第三侧边c和第四侧边d，其中，第一侧边a和第二侧边b相对设置且相互平行(均示例性地平行于y轴)，第三侧边c和第四侧边d相对设置且相互平行(均示例性地平行于x轴)，且第三侧边c连接第一侧边a的顶端(y轴正方向上的一端)和第二侧边b的顶端(y轴正方向上的一端)，第四侧边d连接第一侧边a的底端(y轴负方向上的一端)和第二侧边b的底端(y轴负方向上的一端)，每相邻的两个侧边之间形成倒角。
其中，打孔区域11形成透光孔，透光孔的形式可以是在打孔区域11形成穿透显示面板1的通孔，也可以是在打孔区域11刻蚀掉显示面板1除透明衬底以外的膜层形成的沉孔，只要保证打孔区域11透光即可，以便于摄像头可以通过该打孔区域11透过的光成像，打孔区域11中透光孔的形成方式可以是已知的、常用的形式，在此不再赘述。打孔区域11可以是圆形的，也可以是椭圆和正多边形等其他形式，以下以打孔区域11为圆形为例进行说明。
图3a表示出了图2中的A处局部放大图，请结合图2和图3a，打孔区域11周围具有环形的封装区域13，该封装区域13环绕打孔区域11设置。封装区域13中，在衬底上形成有环绕打孔区域11的隔离柱或者隔离槽，也可以同时具有隔离柱和隔离槽，具体可以是通过刻蚀显示面板1的衬底上的膜层形成上述隔离柱或隔离槽。
继续参考图3a，有效显示区域12内部具有容纳区域，容纳区域的边缘记为第二边界k2，封装区域13位于上述容纳区域内，且封装区域13的外边缘与第二边界k2之间形成缓冲区(dummy区)15，该缓冲区15内的衬底上不设置显示器件。封闭的第一边界k1和封闭的第二边界k2用于界定有效显示区域12的范围。
下面对有效显示区域12内的走线分布进行介绍。
在形成有效显示区域12时，沿远离衬底的方向依次形成第一金属层M1、第二金属层M2、第三金属层M3和第四金属层M4，第一金属层M1和第二金属层M2的材质均可以采用金属Mo，第三金属层M3和第四金属层M4的材质均可采用Ti/Al/Ti层叠结构。其中，第一金属层M1、第二金属层M2、第三金属层M3和第四金属层M4均被图案化形成金属走线等图案，且第一金属层M1和第二金属层M2之间、第二金属层M2和第三金属层M3之间、以及，第三金属层M3和第四金属层M4之间均形成有一层或多层的绝缘层，以将相邻两层的金属走线电隔离，不同金属层形成的金属走线可通过过孔连接。
继续参考图3a，在有效显示区域12内，分布有多条沿第一方向(y轴方向)延伸、且沿第二方向(x轴方向)排列的第一走线(1a和1b)，以及，多条沿第二方向(x轴方向)延伸、且沿第一方向(y轴方向)排列的第二走线(2a和2b)。其中，上述多条第一走线(1a和1b)和上述多条第二走线(2a和2b)交叉设置，以围成阵列分布的多个像素单元。需要说明的是，第一走线(1a和1b)沿第一方向延伸，可以是严格按第一方向(y轴方向)延伸，也可以与第一方向有一定角度误差，角度误差可以在±3°范围内；第二走线(2a和2b)沿第二方向(x轴方向)延伸，以及，其他走线沿某一方向延伸的含义均参考前述第一走线(1a和1b)沿第一方向延伸的说明。应当说明的是，第一方向为x轴方向，第二方向为y轴方向，仅仅是为了说明第一方向严格垂直于第二方向的一种示例，当提到第一方向垂直于第二方向时，两者也可以不是严格的垂直，允许有一定的角度偏差，例如，±3°的角度偏差。
图3b表示出图3a中一条第一走线与一条第二走线交叉设置的示意图，以第一走线1a与第二走线2a交叉为例，第一走线1a和第二走线2a分别位于不同金属层，第一走线1a与第二走线2a交叉重叠的部分相对于该部分两侧的其余部分变窄，第二走线2a与第一走线1a交叉重叠的部分也相对于该重叠部分两端的其它部分较窄，以减小第一走线1a与第二走线2a之间的寄生电容。此外，对于沿同一方向延伸的两条走线，也可错开设置，以减小寄生电容。例如，图3a中第一走线1a和第一走线1b不同层设置，而错开设置，第一走线1a在衬底表面(示例性地平行于xoy面)的正投影和第二走线2b在衬底表面的正投影错开，以减小寄生电容。
图3c表示出图3a的局部放大图，图4表示出图3a中第一走线的分布示意图，请结合图3a、图3c和图4，部分第一走线(1a和1b)的延伸方向经过第二边界k2围成的容纳区域，或者说，部分第一走线(1a和1b)所在直线经过第二边界k2围成的容纳区域，而在第二边界k2处中断，每根第一走线1a位于第二边界k2围成的容纳区域两侧的两个分段通过第一绕线u1连接。应当理解，此处称部分第一走线(1a和1b)所在直线，并非指第一走线(1a和1b)严格沿着直线延伸，可以是有一定的弯折，而是在整体延伸趋势上呈大致直线的延伸，后文类似情况作相同理解，不再赘述。
图5表示出了图4中的一条第一走线1a与第一绕线u1配合的示意图，请结合图4和图5，以图4中一条延伸方向经过第二边界k2围成的容纳区域的第一走线1a为例，第一走线1a包括子段104和子段105，子段104和子段105在同一条直线上，且被第二边界k2隔离而断开连接，子段104位于打孔区域11的一侧，子段105位于打孔区域11的另一侧；第一绕线u1包括第一分段101、第二分段102和第三分段103，其中，第一分段101沿第一方向(y轴方向)延伸，第二分段102和第三分段103相互平行、且均沿第二方向(x轴方向)延伸，第二分段102的x轴负方向上的一端与子段104的y轴负方向上的一端连 接，第三分段103的x轴负方向上的一端与子段105的y轴正方向上的一端连接，第一分段101的y轴正方向上的一端与第二分段102的x轴正方向上的一端连接，第一分段101的y轴负方向上的一端与第三分段103的x轴正方向上的一端连接；第二分段102、第一分段101和第三分段103依次连接形成一个“U”字型结构，且该“U”字型结构的开口方向朝向打孔区域11。第一绕线u1的第二分段102、第一分段101和第三分段103均位于有效显示区域12内，而不占用第二边界k2围成的容纳区域内的空间，第二边界k2与打孔区域11的边缘之间形成的边界区域(border area)的面积较小，有利于提高显示面板1的显示质量，改善用户体验。第二分段102、第一分段101和第三分段103均沿第一方向或第二方向延伸，有利于有规律地排布金属走线，避免同一层的金属走线之间交叉，提高金属走线的排布密度。应当说明的是，以上每根第一绕线u1均位于有效显示区域12仅仅是示例性地，当仅部分第一绕线u1位于有效显示区域12内，另一部分第一绕线u1位于边界区域内，相对于所有第一绕线u1均位于边界区域内相比，也可以在一定程度上减小边界区域面积的作用。
示例性地，每条第一走线1a与一条第一走线1b相邻设置，第一走线1b形成像素电路中的电致发光器件漏极电压(英文全称：electroluminescent voltage drain device；简称：ELVDD)线，部分第一走线1b所在直线经过第二边界k2围成的容纳区域，而被第二边界k2断开为子段106和子段107，且被第二边界k2断开的第一走线1b的两部分之间断路，且没有通过绕线等方式连接。显示面板1还包括分列于打孔区域11两侧的横向连接线(1c和1c’)；横向连接线1c沿第二方向(x轴方向)依次连接每根第一走线1b，将子段106与其他连续(未被断开的)第一走线1b连接，以使子段106与其他未被断开的第一走线1b具有相同的电势；横向连接线1c’沿第二方向(x轴方向)依次连接每根第一走线1b，将子段107与其他未被断开的第一走线1b连接，以使子段107与其他未被断开的第一走线1b具有相同的电势，形成不同像素单元中等电势的电极。
其中，每条第一走线1a属于第三金属层M3，每条第一走线1b、横向连接线(1c和1c’)以及第一绕线u1均属于第四金属层M4。
图6表示出了图5中B-B位置的剖面图，该剖面图同时显示出与第二分段102和子段104相邻的膜层的截面，请参考图6，对第二分段102和子段104的连接进行示例性地说明。玻璃衬底p1上依次设有绝缘层p2、第二分段102、栅极绝缘层(英文全称：gate insulation；简称：GI)p3、层间介质层(英文全称：inter layer dielectric；简称：ILD)p4，绝缘层p2沿远离玻璃衬底p1的方向依次包括聚酰亚胺(英文全称：polyimide；简称：PI)层、缓冲(英文全称：buffer)层和栅极绝缘层，子段104通过贯穿栅极绝缘层p3和层间介质层p4的过孔与第二分段102接触并电连接，实现与第二分段102的电连接；其中，栅极绝缘层p3和层间介质层p4的厚度约
Figure PCTCN2021115425-appb-000001
如，
Figure PCTCN2021115425-appb-000002
至
Figure PCTCN2021115425-appb-000003
本申请实施例中不同层金属走线的电连接形式均可参考第二分段102和子段104通过过孔连接的形式。
图7表示出图3a中第二走线的分布示意图。请结合图3a和图7，部分第二走线(2a和2b)的延伸方向经过第二边界k2围成的容纳区域，或者说，部分第二走线(2a和2b)所在直线经过第二边界k2围成的容纳区域，而在第二边界k2处中断，每根第二走线2a位于第二边界k2围成的容纳区域两侧的两个分段通过第二绕线u2连接。
图8表示出了图7中的一条第二走线2a与第二绕线u2配合的示意图，请结合图7和图8，以图7中一条延伸方向经过第二边界k2围成的容纳区域的第二走线2a为例，第二 走线2a包括沿第二方向延伸的子段204和子段205，子段204和子段205在同一条直线上，且被第二边界k2隔离而断开连接，子段204位于打孔区域11的一侧，子段205位于打孔区域11的另一侧；第二绕线u2包括第四分段201、第五分段202和第六分段203，其中，第四分段201沿第二方向(x轴方向)延伸，第五分段202和第六分段203相互平行、且均沿第一方向(y轴方向)延伸，第五分段202的y轴负方向上的一端与子段204的x轴正方向上的一端连接，第六分段203的y轴负方向上的一端与子段205的x轴负方向上的一端连接，第四分段201的x轴负方向上的一端与第五分段202的y轴正方向上的一端连接，第四分段201的x轴正方向上的一端与第六分段203的y轴正方向上的一端连接；第五分段202、第四分段201和第六分段203依次连接形成一个“U”字型结构。且该“U”字型结构的开口方向朝向打孔区域11。第二绕线u2的有益效果分析可参考前文对第一绕线u1的相关说明。应当说明的是，以上每根第二绕线u2均位于有效显示区域12仅仅是示例性地，当仅部分第二绕线u2位于有效显示区域12内，另一部分第二绕线u2位于边界区域内，相对于所有第二绕线u2均位于边界区域内相比，也可以在一定程度上减小边界区域面积的作用。
其中，第一走线2a位于第一金属层M1，第二走线2b和第四分段201均位于第二金属层M2，第五分段202和第六分段203均位于第三金属层M3。由于第三金属层M3的材料的电阻率小于第一金属层M1的材料的电阻率，因此，因绕线增加的走线段第五分段202和第六分段203的电阻较小，从而，尽量避免因绕线额外增加较多负载。除此之外，还可以增加第二金属层M2和/或第三金属层M3的厚度，或者，增加第二金属层M2或第三金属层M3的宽度，均可增加第一绕线u1的横截面积，以降低单位长度上的电阻。以上均只是示例性地，只要能够使第一绕线u1单位长度的平均电阻值低于对应的第一走线的单位长度的平均电阻值即可。类似地，第二绕线段u2的单位长度的平均电阻值也低于对应的第二走线的单位长度的平均电阻值。
示例性地，显示面板1包括阵列分布的多个像素单元，每个像素单元通过经过该像素单元的第一走线、第二走线、半导体走线和其它金属走线等形成一个像素电路。图9表示出了图2所示显示面板1中的一个像素单元的像素电路图，请参考图9，该像素电路是已知的、常用的7T1C的像素电路，在此不再赘述。其中，E1表示电致发光器件漏极电压(英文全称：electroluminescent voltage drain device；简称：ELVDD)线，电致发光器件漏极电压线可以由第三金属层M3和第四金属层M4复合形成，E2表示电致发光器件源极电压(英文全称：electroluminescent voltage source device；简称：ELVSS)线，EM1和EM2均表示发光信号(英文全称：eimt；简称EM)线，R1和R2均表示RST线(中文名称：复位信号线；英文全称：reset line)，V1表示Vinit(中文名称：初始化电压；英文名称：initial voltage)线，D1表示信号线(date线)，D2表示DTFT(中文名称：驱动晶体管；英文全称：drive thin film transistor)，G1和G2均表示扫描线(英文全称：scan line)，C1表示Cst电容(中文名称：储存电容；英文全称：storage capacitor)，该Cst电容C1的形成方式可以参考图3c，第二金属层M2中形成与第二走线2b相邻设置且电连接的第一金属电极层c11，第一金属层M1中形成与第一金属电极层c11相对设置的第二金属电极层c12，第一金属电极层c11和第二金属电极层c12配合共同形成上述Cst电容C1。T1、T2、T3、T4、T5、T6和T7均表示薄膜晶体管开关。
图10表示出图9所示像素电路的线路分布图，图10中仅表示出图9中的部分线路的 分布情况，图10中与图9相同标号表示相同的含义，而011、012、013、014、015和016均表示半导体走线。需要说明的是，该像素电路中的各走线的连接关系可以是已知的、常用的连接方式。继续参考图10，信号线D1沿第一方向(y轴方向)延伸，且位于整个像素电路的左侧(x轴负方向上一侧)位置。
下面对第一绕线u1在像素电路中的分布情况进行说明。
图11表示出第一绕线u1在图10所示像素电路中的分布的一种具体实施例。请参考图11，第一绕线u1中的第一分段101与信号线D1层叠设置，即第一分段101位于信号线D1背离衬底的一侧，或者位于信号线D1朝向衬底的一侧。第一分段101在衬底表面的正投影可以与信号线D1在衬底表面的正投影重叠或基本重叠。
图12表示出第一绕线u1在图10所示像素电路中的分布的另一种具体实施例。请参考图12，第一绕线u1中的第一分段101在衬底上的正投影位于信号线D1在衬底上的正投影和电致发光器件漏极电压线E1在衬底表面上的正投影之间，可减小第一分段101与信号线D1之间的寄生电容大小，减少信号串扰。
图13表示出第一绕线u1在图10所示像素电路中的分布的另一种具体实施例。请参考图13，第一绕线u1中的第一分段101在衬底上的正投影位于信号线D1在衬底上的正投影的左侧(x轴负方向上一侧)，可减小第一分段101与信号线D1之间的寄生电容大小。
图14表示出第一绕线u1在图10所示像素电路中的分布的另一种具体实施例。请参考图14，一条第一绕线u1中的第一分段101在衬底上的正投影位于信号线D1在衬底上的正投影和电致发光器件漏极电压线E1在衬底表面上的正投影之间，另一条第一绕线u1中的第一分段101在衬底上的正投影位于信号线D1在衬底上的正投影的左侧(x轴负方向上一侧)。
还可以在图14的基础上，同时再设置一根第一绕线u1，该第一绕线u1的第一分段101与信号线D1层叠设置，该第一绕线u1参考图11的形式。
或者，一个像素单元内经过两根第一绕线u1，一根第一绕线u1采用图12的绕线方式，另一根第一绕线u1采用图11的绕线方式。或者，一根第一绕线u1采用图13的绕线方式，另一根第一绕线u1采用图11的绕线方式。
下面结合仿真实验对图12至图14的绕线形式的效果进行分析，其中，以一根延伸方向经过打孔区域11的信号线D1(第一走线1a)为例进行说明。表1给出了分别采用图12至图14三种绕线方案的仿真结果。
Figure PCTCN2021115425-appb-000004
表1
表1中，A1表示图13所示的绕线方案，A2表示图12所示的绕线方案，A3表示图14所示的绕线方案；B1表示第一绕线u1与其它走线的寄生电容之和(B11与B12之和)，B11表示第一绕线u1中第二分段102与其它走线的寄生电容和第二分段103与其它走线的寄生电容之和，B2表示延伸方向经过打孔区域11的信号线D1(不包含对应的第一绕线u1)的与其它走线产生的寄生电容，B3表示B1与B2之和，B4表示延伸方向不经过打孔区域11的信号线(第一走线1a)与其它走线产生的寄生电容之和，B5表示B3相对于B4的变化率，即B5＝(B3-B4)/B4。表1中，B11、B12、B2、B3、B4和B5对应的数值的单位均为pF(皮法)。
由表1可以看出，图14对应的绕线方案A3的B5值最小，仅为1.7％，说明选用绕线方案A3相对于不绕线的情况所额外增加的寄生电容影响最小。
但是，信号线D1不同的灰阶值下，即加载不同的电压时，延伸方向经过打孔区域11的信号线D1(第一走线1a)中电流的变化率也是选择绕线方案的重要参考指标。
Figure PCTCN2021115425-appb-000005
表2
表2中，G15、G31、G63、G111、G127、G143和G255分别表示不同的灰阶值，a0延伸方向不经过打孔区域11的信号线D1(第一走线1a)的电流值，A1表示图13所示的绕线方案，a1表示A1方案中，延伸方向经过打孔区域11的信号线D1的电流值，v1表示a1相对于a0的变化率，v1＝(a1-a0)/a0；
A2表示图12所示的绕线方案，a2表示A2方案中，延伸方向经过打孔区域11的信号线D1的电流值，v2表示a2相对于a0的变化率，v2＝(a2-a0)/a0；A3表示图14所示的绕线方案，a3表示A3方案中，延伸方向经过打孔区域11的信号线D1的电流值，v3表示a3相对于a0的变化率，v3＝(a3-a0)/a0。
观察表2可知，在G15灰阶和灰阶G255下，绕线方案A3的电流变化率较小，因此，绕线对信号线D1中电流的影响较小。而在G31灰阶下，绕线方案A1的电流变化率较小，绕线对信号线D1中电流的影响较小。在其他灰阶下绕线方案A2的电流变化率较小，绕线 对信号线D1中电流的影响较小。
此外，每根第二绕线u2中的第五分段202和第六分段203相对于信号线D1的设置位置可以参考前述第一绕线u1中第一分段101的布线方式。
图15表示出图4所示实施例的一种变形，图16表示出图15中一条第一走线1a与第一绕线u1配合的示意图，图16与图5的区别在于，第一绕线u1中，第二分段102和第三分段103均位于第二金属层M2，而第一分段101仍然位于第四金属层M4，第二分段102和第三分段103分别通过过孔与第一分段101电连接，图15中的每条第一绕线均参照图16中的设置。在第二金属层M2中，由于第二分段102和第三分段103之间相互平行(此处的“平行”允许存在一定的角度偏差，如角度误差在±3°范围内)，且断开设置，可避免第一分段101打断第二金属层M2中位于第二分段102和第三分段103之间、且沿第二方向延伸的走线。与第一绕线u1均位于第四金属层M4的情况相比，可避免交叉短路。
图17表示出图7所示实施例的一种变形，图18表示出图17中一条第二走线2a与第二绕线u2配合的示意图，图18与图8的区别在于，第五分段202和第六分段203均位于第四金属层M4，而不是第三金属层M3，第四分段201仍然位于第二金属层M2。
但这仅仅是示例性地，只要每根第二绕线中，第五分段和第六分段均与第四分段分层设置，以方便第四金属层M4，避免短路。
除此之外，第四分段、第五分段和第六分段也可以同层设置，只要每根第二绕线中，第四分段、第五分段和第六分段均与对应的第二走线分层设置，以方便布线。
下面结合仿真实验对图15的绕线形式的效果进行分析。
Figure PCTCN2021115425-appb-000006
表3
以图15所示的第一绕线u1形式为例，第一绕线u1在像素单元中的绕线位置参考图14的形式，记为方案A4，进行仿真实验得到表3数据。表3中与图1相同的表头含义可参考对表1的描述。
由表3可以看出，方案A4的B5值(寄生电容变化率)为2.7％，相对于方案A1至A3较大，但仍然具有可实施性。
Figure PCTCN2021115425-appb-000007
Figure PCTCN2021115425-appb-000008
表4
表4中，a4表示A4方案中，延伸方向经过打孔区域11的信号线D1的电流值，v4表示a4相对于a0的变化率，v4＝(a4-a0)/a0。
观察表4可知，在灰阶G111至灰阶G255下，绕线方案A4的电流变化率小于1％，因绕线对信号线D1中电流的影响较小。
图15所示的第一走线的分布和图17所示的第二走线的分布结合一起，可得到同时具有第一走线和第二走线分布的图。
图19表示出图17所示实施例的一种变形，请参考图19，图19所示实施例与图17所示实施例的区别在于，取消全部第一绕线u1。
其中，第二走线2a均可以是扫描线(参考图9中的G1和G2)，每根被打孔区域11断开的扫描线中，位于打孔区域11左侧的部分的长度与位于打孔区域11右侧的部分的长度相同，以确保每根扫描线位于打孔区域11两侧的部分被分别驱动，且负载大小相同，延迟相同。应当说明的是，扫描线位于打孔区域11不同侧的部分的长度相同可以是严格意义上的相同，也可以存在一定误差，该误差可以是该扫描线较短的部分的5％以内。对于后文涉及到的其他走线分布于打孔区域11两侧的部分的长度相同作类似理解。和/或，第二走线2a可以是发光信号线(参考图9中的E1和E2)，在打孔区域11处断开的发光信号线中，位于打孔区域11左侧的部分的长度与位于打孔区域11右侧的部分无论长度可以相同也可以不相同，无论是否相同，延迟相差较少。和/或，第二走线2b可以是初始化电压线(参考图9中的V1)，在打孔区域11处断开的初始化电压线中，位于打孔区域11左侧的部分的长度与位于打孔区域11右侧的部分长度相同，以最小化信号延迟差异。
第一走线1a可以是信号线D1，信号线D1位于打孔区域11不同侧的部分均通过第一绕线u1连接。
第一走线1b可以是电致发光器件漏极电压线E1，电致发光器件漏极电压线E1位于打孔区域11不同侧的部分可以断开设置，即不通过第一绕线连接，也可以通过第一绕线连接，电致发光器件漏极电压线E1位于打孔区域11不同侧的部分负载差异较小，延迟差异不明显。为确保不同的电致发光器件漏极电压线E1之间的电势相同，可采用沿第二方向延伸的横向连接线(1c和1c’)将不同的电致发光器件漏极电压线E1连接。具体可参考对图5中对横向连接线(1c和1c’)的相应描述。
以上仅仅是示例性地，为了减少第一绕线的设置，至少部分延伸方向经过打孔区域的第一走线中，每根第一走线分列于打孔区域两侧的部分断路；和/或，为了减少第二绕线的设置，至少部分延伸方向经过打孔区域的第二走线中，每根第二走线分列于打孔区域两侧的部分断路。
应当说明的是，以上通过第一金属层M1、第二金属层M2、第三金属层M3和第四金属层M4形成各段走线，并通过过孔将不同走线连接到一起，但这仅仅是示例性地，也可以设置三层、五层或其它层数的金属层，通过各金属层图案化形成相应的走线。
此外，以上分别单独对沿第一方向延伸的第一走线和相应第一绕线，以及，沿第二方向延伸的第二走线和相应第二绕线单独进行了介绍，应当说明的是，关于第一走线和相应第一绕线的特征，与，第二走线和相应第二绕线的特征可以自由组合，例如，一个具体实施例可以涵盖第一走线和相应第一绕线的相关特征，或者，第二走线和相应第二绕线的相关特征，或者，同时具有上述两方面的特征。
基于相同的技术构思，本申请实施例还提供了一种终端设备，该终端设备可以是手机、平板电脑和智能手表等具有前置摄像头的终端设备。
图20表示出了本申请实施例提供的终端设备中摄像头2与显示面板1配合的示意图，请参考图20，终端设备包括摄像头2和前述实施例提供的显示面板1，摄像头2位于显示面板1背离出光面的一侧，且摄像头2的采光窗口与显示面板1的打孔区域11相对设置，外界环境光线经过打孔区域11直接透射至摄像头2的采光窗口中，被摄像头2采集并成像。
图21表示出了本申请实施例提供的另一种终端设备中摄像头2与显示面板1配合的示意图，参考图21，图21与图20的区别在于，显示面板1背离出光面的一侧还设有潜望镜3，该潜望镜3的反射面与显示面板1的出光明呈锐角，例如是45°，摄像头2的光轴示例性地平行于显示面板1的出光面，潜望镜3的反射面与打孔区域11相对，且与摄像头2的采光窗口相对。外界环境光线经打孔区域11射向潜望镜3的反射面，并经该反射面反射至摄像头2的采光窗口，以在摄像头2内成像。
图20和图21所示的实施例仅仅是示例性的，只要摄像头2设置于显示面板1背离出光面的一侧，用于接收经过打孔区域的光线，以进行成像即可。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
本申请中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。本申请中，“平行”可以不是指绝对的平行，“垂直”可以不是指绝对的垂直，可以允许有一定工程上的误差。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
可以理解的是，在本申请中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。术语“第一”、“第二”等是用于分区别类似的对象，而不必用于描述特定的顺序或先后次序。
另外，本申请实施例的各附图中的部件均只为了表示显示面板和终端设备的工作原理，并不真实反映各部件的实际尺寸关系。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (13)

  1. 一种显示面板，其特征在于，所述显示面板具有有效显示区域，位于所述有效显示区域内的打孔区域，以及，围绕所述打孔区域的边界区域；
    所述有效显示区域设有多根沿第一方向延伸的第一走线，以及，沿第二方向延伸的第二走线，其中，所述第一方向垂直于所述第二方向；
    至少部分延伸方向经过所述打孔区域的第一走线中，每根所述第一走线分列于所述打孔区域两侧的部分通过一根第一绕线连接，至少部分所述第一绕线位于所述有效显示区域内；和/或，
    至少部分延伸方向经过所述打孔区域的第二走线中，每根所述第二走线分列于所述打孔区域两侧的部分通过一根第二绕线连接，至少部分所述第二绕线位于所述有效显示区域内。
  2. 根据权利要求1所述的显示面板，其特征在于，每根所述第一绕线包括第一分段、第二分段和第三分段，其中，所述第一分段沿所述第一方向延伸，所述第二分段和所述第三分段均沿所述第二方向延伸；
    每一组相互对应的所述第一走线和所述第一绕线中，所述第二分段的一端与所述第一走线位于所述打孔区域的一侧的部分连接，所述第三分段的一端与所述第一走线位于所述打孔区域的另一侧的部分连接，所述第二分段的另一端通过所述第一分段与所述第三分段的另一端连接。
  3. 根据权利要求2所述的显示面板，其特征在于，每根所述第一绕线中，所述第一分段、所述第二分段和所述第三分段均与对应的第一走线分层设置。
  4. 根据权利要求3所述的显示面板，其特征在于，所述第二分段和所述第三分段均与所述第一分段分层设置。
  5. 根据权利要求2至4任一项所述的显示面板，其特征在于，部分所述第一走线为信号线；
    至少部分所述信号线中，每根所述信号线的第二方向上的至少一侧设置一个所述第一分段，和/或，所述信号线与一个所述第一分段层叠设置。
  6. 根据权利要求1至5任一项所述的显示面板，其特征在于，每根所述第二绕线包括第四分段、第五分段和第六分段，其中，所述第四分段沿所述第二方向延伸，所述第五分段和所述第六分段均沿所述第一方向延伸；
    每一组相互对应的所述第二走线和所述第二绕线中，所述第五分段的一端与所述第二走线位于所述打孔区域的一侧的部分连接，所述第六分段的一端与所述第二走线位于所述打孔区域的另一侧的部分连接，所述第五分段的另一端通过所述第四分段与所述第六分段的另一端连接。
  7. 根据权利要求6所述的显示面板，其特征在于，每根所述第二绕线中，所述第四分段、所述第五分段和所述第六分段均与对应的第二走线分层设置。
  8. 根据权利要求7所述的显示面板，其特征在于，每根所述第二绕线中，所述第五分段和所述第六分段均与所述第四分段分层设置。
  9. 根据权利要求1至8任一项所述的显示面板，其特征在于，
    所述第一绕线的单位长度的平均电阻值低于对应的所述第一走线单位长度的平均电 阻值；和/或，
    所述第二绕线的单位长度的平均电阻值低于对应的所述第二走线单位长度的平均电阻值。
  10. 根据权利要求1至9任一项所述的显示面板，其特征在于，至少部分延伸方向经过所述打孔区域的第一走线中，每根所述第一走线分列于所述打孔区域两侧的部分断路；和/或，
    至少部分延伸方向经过所述打孔区域的第二走线中，每根所述第二走线分列于所述打孔区域两侧的部分断路。
  11. 根据权利要求10所述的显示面板，其特征在于，部分所述第一走线为发光信号线，延伸方向经过所述打孔区域的发光信号线分列于所述打孔区域两侧的两部分断路；和/或，
    部分所述第一走线为扫描线，延伸方向经过所述打孔区域的扫描线分列于所述打孔区域两侧的两部分断路，且所述扫描线分列于所述打孔区域两侧的部分的长度相等；和/或，
    部分所述第一走线为初始化电压线，延伸方向经过所述打孔区域的初始化电压线分列于所述打孔区域两侧的两部分断路，且所述初始化电压线分列于所述打孔区域两侧的部分的长度相等。
  12. 根据权利要求11所述的显示面板，其特征在于，部分所述第二走线为电致发光器件漏极电压线；其中，延伸方向经过所述打孔区域的电致发光器件漏极电压线分列于所述打孔区域两侧的部分断路。
  13. 一种终端设备，其特征在于，包括：摄像头和如权利要求1至12任一项所述的显示面板，所述摄像头设置于所述显示面板背离出光面的一侧，用于接收经过所述打孔区域的光线，以进行成像。
PCT/CN2021/115425 2020-09-02 2021-08-30 一种显示面板及终端设备 WO2022048519A1 (zh)

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