WO2022067698A1 - 显示基板、显示面板和显示装置 - Google Patents

显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2022067698A1
WO2022067698A1 PCT/CN2020/119472 CN2020119472W WO2022067698A1 WO 2022067698 A1 WO2022067698 A1 WO 2022067698A1 CN 2020119472 W CN2020119472 W CN 2020119472W WO 2022067698 A1 WO2022067698 A1 WO 2022067698A1
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Prior art keywords
layer
base substrate
transistor
gate
active layer
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PCT/CN2020/119472
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English (en)
French (fr)
Inventor
贵炳强
于洋
黄鹏
高涛
李文强
刘珂
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/310,405 priority Critical patent/US12096655B2/en
Priority to CN202080002207.6A priority patent/CN114586155A/zh
Priority to PCT/CN2020/119472 priority patent/WO2022067698A1/zh
Publication of WO2022067698A1 publication Critical patent/WO2022067698A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • An organic light emitting diode (abbreviated as OLED) display device is a type of display device that uses an OLED that emits light to display information such as images.
  • the OLED display device has characteristics such as low power consumption, high brightness, and high response speed.
  • Low Temperature Polysilicon Oxide Thin Film Transistor (Low Temperature Poly-Oxide TFT, hereinafter referred to as LTPO TFT) technology is an emerging thin film transistor technology in recent years. Theoretically, LTPO TFT can save 5-15% of power compared to the traditional low temperature polysilicon thin film transistor (Low Temperature Poly-Silicon TFT, hereinafter referred to as LTPS TFT) technology, making the power consumption of the entire display screen more efficient. Low.
  • a display substrate comprising:
  • the first transistor includes a first active layer, a first bottom gate and a first top gate, the first bottom gate is located between the base substrate and the first active layer, and the first bottom gate is located between the base substrate and the first active layer.
  • a top gate is located on a side of the first active layer away from the base substrate, and any two of the first active layer, the first bottom gate and the first top gate are located on the side of the first active layer.
  • a third gate insulating layer is arranged between the first bottom gate and the first active layer, and the first active layer includes an oxide semiconductor material, so
  • the third gate insulating layer includes a silicon oxide material, the surface of the first top gate far from the base substrate is in direct contact with the silicon oxide material, and the surface of the first active layer close to the base substrate is in contact with the silicon oxide material.
  • the silicon oxide material is in direct contact.
  • the display substrate includes:
  • the display substrate further includes a third transistor
  • the third transistor includes a third active layer and a third gate, the third active layer includes a polysilicon semiconductor material, the third active layer is located in the first semiconductor layer, the first active layer layer is located at the second semiconductor layer.
  • a distance between a surface of the first active layer close to the base substrate and a surface of the first bottom gate away from the base substrate is greater than that of the first active layer A distance between a surface away from the base substrate and a surface of the first top gate close to the base substrate.
  • a distance between a surface of the first active layer close to the base substrate and a surface of the first bottom gate away from the base substrate is greater than that of the third active layer A distance between a surface away from the base substrate and a surface of the third gate close to the base substrate.
  • the distance between the surface of the first active layer away from the base substrate and the surface of the first top gate close to the base substrate is the same as the distance between the third active layer
  • the distance between the surface away from the base substrate and the surface of the third gate close to the base substrate is approximately equal.
  • the display substrate further includes a second transistor including a second bottom gate and a second top gate, and the second bottom gate is located between the base substrate and the second transistor. between the active layers of the transistors, the second top gate is located on the side of the active layer of the second transistor away from the base substrate, the active layer of the second transistor, the second bottom gate and the orthographic projections of any two of the second top gates on the base substrate at least partially overlap each other.
  • the display substrate includes a storage capacitor including a first capacitor structure, a second capacitor structure, and a third capacitor structure disposed on the base substrate, the third capacitor structure being located at The first capacitor structure is away from the side of the base substrate, the second capacitor structure is located between the first capacitor structure and the third capacitor structure, the first capacitor structure, the second capacitor structure orthographic projections of any two of the capacitive structure and the third capacitive structure on the base substrate at least partially overlap; and
  • the first capacitive structure and the third capacitive structure are electrically connected to each other to form a first capacitive electrode of the storage capacitor, and the second capacitive structure forms a second capacitive electrode of the storage capacitor.
  • the display substrate includes a first conductive layer disposed on the base substrate, the first conductive layer being located on a side of the first semiconductor layer away from the base substrate; and the The first capacitor structure and the third gate of the third transistor are both located in the first conductive layer.
  • the display substrate includes a second conductive layer disposed on the base substrate, the second conductive layer is located between the first conductive layer and the second semiconductor layer; and the Both the first bottom gate and the second capacitor structure are located on the second conductive layer.
  • the display substrate includes a third conductive layer disposed on the base substrate, the third conductive layer being located on a side of the second semiconductor layer away from the base substrate; and The first top gate and the third capacitor structure are both located on the third conductive layer.
  • the display substrate includes a first buffer layer between the base substrate and the first semiconductor layer, the first buffer layer including silicon oxide or silicon nitride.
  • the display substrate includes a first gate insulating layer between the first semiconductor layer and the first conductive layer, the first gate insulating layer including silicon oxide.
  • the display substrate includes a second gate insulating layer between the first conductive layer and the second conductive layer, the second gate insulating layer including silicon nitride.
  • only one insulating layer is disposed between the first capacitor structure and the second capacitor structure, and the only one insulating layer includes a portion of the second gate insulating layer.
  • the display substrate includes a third gate insulating layer between the second conductive layer and the second semiconductor layer, the third gate insulating layer including silicon oxide.
  • the display substrate includes a fourth gate insulating layer between the second semiconductor layer and the third conductive layer, the fourth gate insulating layer including silicon oxide.
  • only one insulating layer is disposed between the second capacitive structure and the third capacitive structure, and the only one insulating layer includes a portion of the fourth gate insulating layer.
  • two insulating layers are disposed between the second capacitor structure and the third capacitor structure, and the two insulating layers include a part of the third gate insulating layer and the fourth insulating layer. part of the gate insulating layer.
  • the display substrate further includes a second buffer layer disposed between the second gate insulating layer and the second conductive layer; and the first capacitor structure and the second capacitor Two insulating layers are disposed between the structures, and the two insulating layers include a part of the second gate insulating layer and a part of the second buffer layer.
  • the third capacitive structure is located in the second semiconductor layer, and the third capacitive structure includes a structure formed of a conductive oxide semiconductor material.
  • the display substrate includes a third gate insulating layer between the second conductive layer and the second semiconductor layer, the third gate insulating layer including silicon oxide; and the third gate insulating layer Only one insulating layer is disposed between the second capacitor structure and the third capacitor structure, and the only one insulating layer includes a part of the third gate insulating layer.
  • the display substrate includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the base substrate; and each of the plurality of thin film transistors One includes a source electrode and a drain electrode, and the source electrode and the drain electrode of each thin film transistor are located in the fourth conductive layer.
  • the display substrate includes a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate; and the fifth conductive layer includes a light shielding layer , the orthographic projection of the light shielding layer on the base substrate at least covers the orthographic projection of the active layer of each of the first transistor and the second transistor on the base substrate.
  • the fourth conductive layer includes a first conductive sublayer and a second conductive sublayer, the first conductive sublayer is disposed on the interlayer insulating layer, and the second conductive sublayer It is disposed on the side of the first conductive sub-layer away from the base substrate, and the first conductive sub-layer and the second conductive sub-layer are in contact with each other.
  • a display panel including the display substrate as described above.
  • a display device comprising the above-mentioned display substrate or the above-mentioned display panel.
  • a method for manufacturing a display substrate includes the following steps:
  • a first semiconductor layer is prepared on the base substrate, and the first semiconductor layer includes a polycrystalline silicon semiconductor silicon island;
  • a first conductive layer is formed on the side of the first semiconductor layer away from the base substrate;
  • a second conductive layer is formed on the side of the first conductive layer away from the base substrate;
  • a second semiconductor layer is formed on the side of the second conductive layer away from the base substrate, and the second semiconductor layer includes an oxide semiconductor silicon island,
  • the display substrate includes a plurality of thin film transistors disposed on the base substrate, and the plurality of thin film transistors at least include a first transistor, a second transistor and a third transistor,
  • Each of the plurality of thin film transistors includes an active layer, the active layer of the third transistor is located on the first semiconductor layer, and at least one of the first transistor and the second transistor has an active layer. a source layer on the second semiconductor layer; and
  • the first transistor includes a first active layer, a first bottom gate and a first top gate, the first bottom gate is located between the base substrate and the first active layer, the first top gate The gate is located on the side of the first active layer away from the base substrate, and any two of the first active layer, the first bottom gate and the first top gate are on the substrate orthographic projections on the substrate at least partially overlap each other, a third gate insulating layer is disposed between the first bottom gate and the first active layer, and the first active layer includes the oxide semiconductor silicon island,
  • the third gate insulating layer includes a silicon oxide material, the surface of the first top gate far from the base substrate is in direct contact with the silicon oxide material, and the first active layer is close to the surface of the base substrate in direct contact with the silicon oxide material.
  • the manufacturing method further includes:
  • the first conductive material layer and the second conductive material layer are patterned to form the source electrodes and the drain electrodes of the plurality of thin film transistors.
  • FIG. 1 is a schematic plan view of a display device according to some embodiments of the present disclosure.
  • FIG. 2 is a schematic plan view of a display substrate included in a display device according to some embodiments of the present disclosure
  • FIG. 3 is a partial enlarged view of a display substrate at portion I in FIG. 2 according to some embodiments of the present disclosure
  • FIG. 4 is an equivalent circuit diagram of one pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 5 is a schematic diagram illustrating a planar structure of a pixel driving circuit of one sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 6 is a schematic diagram showing a planar structure of a first semiconductor layer of the pixel driving circuit shown in FIG. 5;
  • FIG. 7 is a schematic diagram illustrating a planar structure of a first conductive layer of the pixel driving circuit shown in FIG. 5;
  • FIG. 8 is a schematic diagram illustrating a planar structure of a second conductive layer of the pixel driving circuit shown in FIG. 5;
  • FIG. 9 is a schematic diagram showing a planar structure of a second semiconductor layer of the pixel driving circuit shown in FIG. 5;
  • FIG. 10 is a schematic diagram illustrating a planar structure of a third conductive layer of the pixel driving circuit shown in FIG. 5;
  • FIG. 11 is a schematic diagram showing the planar structure of the fourth conductive layer of the pixel driving circuit shown in FIG. 5;
  • FIG. 12 is a schematic diagram showing the planar structure of the fifth conductive layer of the pixel driving circuit shown in FIG. 5;
  • FIG. 13 is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line AA' and line BB' in FIG. 5 according to some exemplary embodiments of the present disclosure, and for convenience of description, it will be taken along line AA' in FIG. 5
  • the cross-sectional structure taken by line BB' is shown in the same schematic diagram;
  • FIG. 14 is a schematic diagram illustrating a planar structure of a display substrate according to some exemplary embodiments of the present disclosure, wherein a planar structure of a first electrode of a light emitting device is schematically illustrated;
  • FIG. 15 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.
  • 16 is a schematic diagram illustrating a planar structure of a pixel driving circuit of one sub-pixel of a display substrate according to other exemplary embodiments of the present disclosure
  • FIG. 17 is a schematic diagram showing a planar structure of a second semiconductor layer of the pixel driving circuit shown in FIG. 16;
  • FIG. 18 is a schematic diagram showing the planar structure of the third conductive layer of the pixel driving circuit shown in FIG. 16;
  • FIG. 19 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 20 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure
  • 21 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 22 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 23 is a flowchart of a method of manufacturing a display substrate according to some exemplary embodiments of the present disclosure.
  • FIGS. 24 to 28 are schematic diagrams of cross-sectional structures of the display substrate formed after some steps in the manufacturing method shown in FIG. 23 are performed, respectively.
  • the X axis, the Y axis and the Z axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a broader sense.
  • the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as X only, Y only, Z only, or Any combination of two or more of X, Y and Z such as XYZ, XYY, YZ and ZZ.
  • the term "and/or" includes any and all combinations of one or more of the associated listed items.
  • first the terms “first”, “second”, etc. may be used herein to describe various components, components, elements, regions, layers and/or sections, these components, components, elements, regions, layers and/or parts shall not be limited by these terms. Rather, these terms are used to distinguish one element, member, element, region, layer and/or section from another. Thus, for example, a first part, first member, first element, first region, first layer and/or first section discussed below could be termed a second part, second member, second element, second region , the second layer and/or the second portion without departing from the teachings of the present disclosure.
  • spatially relational terms eg, "upper,” “lower,” “left,” “right,” etc. may be used herein to describe one element or feature relative to another element or feature as shown in the figures relation. It should be understood that the spatially relational terms are intended to encompass other different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the expression "the same layer” refers to the formation of a film layer for forming a specific pattern using the same film forming process, and then using the same mask to pattern the film layer through a patterning process.
  • layer structure Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or sections located on the "same layer” are composed of the same material and formed by the same patterning process, typically, multiple elements, components, structures and/or sections located on the "same layer” or parts with approximately the same thickness.
  • the expression “height” or “thickness” refers to the dimension along the surface of each film layer arranged perpendicular to the display substrate, that is, along the light exit direction of the display substrate size, or the size along the normal direction of the display device.
  • Embodiments of the present disclosure provide at least one display substrate.
  • the display substrate includes: a base substrate; a first semiconductor layer disposed on the base substrate; and a second semiconductor layer disposed on a side of the first semiconductor layer away from the base substrate, wherein the The display substrate further includes a plurality of thin film transistors disposed on the base substrate, the plurality of thin film transistors including at least a first transistor, a second transistor and a third transistor, wherein each of the plurality of thin film transistors is including an active layer, the active layer of at least one of the first transistor and the second transistor includes an oxide semiconductor material, the active layer of the third transistor includes a polysilicon semiconductor material, and the third transistor an active layer is located on the first semiconductor layer, an active layer of at least one of the first transistor and the second transistor is located on the second semiconductor layer; and the first transistor and the second transistor At least one of them has a double gate structure.
  • the active layer of at least one of the first transistor and the second transistor is formed using an oxide semiconductor material such as
  • FIG. 1 is a schematic plan view of a display device according to some embodiments of the present disclosure.
  • the display device may be an OLED display device.
  • a display apparatus 1000 may include a display panel 110 , a gate driver 120 , a data driver 130 , a controller 140 and a voltage generator 150 .
  • the display device 1000 may be an OLED display device.
  • the display panel 110 may include an array substrate 100 and a plurality of pixels PX, the array substrate 100 may include a display area AA and a non-display area NA, and the plurality of pixels PX are arranged in the display area AA in an array form.
  • Signals generated by the gate driver 120 may be applied to the pixels PX through signal lines such as scan signal lines GL, and signals generated by the data driver 130 may be applied to the pixels PX through signal lines such as data lines DL.
  • a first voltage such as VDD and a second voltage such as VSS may be applied to the pixels PX.
  • the first voltage, eg, VDD may be higher than the second voltage, eg, VSS.
  • a first voltage such as VDD may be applied to the anode of the light emitting device (eg OLED) and a second voltage such as VSS may be applied to the cathode of the light emitting device so that the light emitting device may emit light.
  • each pixel PX may include a plurality of subpixels, eg, red subpixels, green subpixels, and blue subpixels, or may include white subpixels, red subpixels, green subpixels, and blue subpixels.
  • the display substrate may be an array substrate for an OLED display panel.
  • the display substrate may include a display area AA and a non-display area NA.
  • the display area AA and the non-display area NA may include multiple boundaries, such as AAS1 , AAS2 , AAS3 and AAS4 as shown in FIG. 2 .
  • the display substrate may further include a driver located in the non-display area NA.
  • the driver may be located on at least one side of the display area AA.
  • the driving circuits are located on the left and right sides of the display area AA, respectively. It should be noted that the left side and the right side may be the left side and the right side of the display substrate (screen) viewed by human eyes during display.
  • the driver can be used to drive each pixel in the display substrate to display.
  • the driver may include the gate driver 120 and the data driver 130 described above.
  • the data driver 130 is used for sequentially latching the input data according to the timing of the clock signal, converting the latched data into an analog signal, and then inputting the latched data to each data line of the display substrate.
  • the gate driver 120 is usually implemented by a shift register, and the shift register converts the clock signal into an on/off voltage, which are respectively output to each scan signal line of the display substrate.
  • FIG. 2 shows that the drivers are located on the left and right sides of the display area AA, embodiments of the present disclosure are not limited thereto, and the driving circuits may be located at any suitable positions in the non-display area NA.
  • the driver may adopt GOA technology, namely Gate Driver on Array.
  • GOA technology the gate drive circuit is directly disposed on the array substrate instead of an external drive chip.
  • Each GOA unit is used as a first-level shift register, and each level of shift register is connected to a gate line, and the turn-on voltage is output in turn through the shift registers of each level to realize the progressive scanning of pixels.
  • each stage of the shift register may also be connected to multiple gate lines. In this way, it can adapt to the development trend of high resolution and narrow borders of display substrates.
  • a left GOA circuit DA1 on the display substrate, a left GOA circuit DA1 , a plurality of pixels P located in the display area AA, and a right GOA circuit DA2 are provided.
  • the left GOA circuit DA1 and the right GOA circuit DA2 are respectively electrically connected to the display IC through signal lines, and the supply of the GOA signal is controlled by the display IC.
  • the left GOA circuit DA1 and the right GOA circuit DA2 are also electrically connected to the respective pixels through signal lines (eg, scan signal lines GL), respectively, to supply driving signals to the respective pixels.
  • FIG. 3 is a partial enlarged view of a display substrate at part I in FIG. 2 according to some embodiments of the present disclosure.
  • the figure exemplarily shows that the shape of the orthographic projection of the sub-pixel on the base substrate is a rounded rectangle.
  • the embodiments of the present disclosure are not limited to this.
  • the sub-pixel is on the base substrate.
  • the shape of the orthographic projection on it can be a rectangle, a hexagon, a pentagon, a square, a circle, or other shapes.
  • the arrangement of the three sub-pixels in one pixel unit is not limited to that shown in FIG. 3 .
  • each pixel unit PX may include a plurality of sub-pixels, eg, a first sub-pixel SP1 , a second sub-pixel SP2 and a third sub-pixel SP3 .
  • the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 may be described as a red sub-pixel, a green sub-pixel and a blue sub-pixel respectively, however, the embodiments of the present disclosure are not limited thereto .
  • the plurality of sub-pixels are arranged on the base substrate 1 in an array along the row direction X and the column direction Y. It should be noted that, although the row direction X and the column direction Y are perpendicular to each other in the illustrated embodiment, the embodiments of the present disclosure are not limited thereto.
  • each sub-pixel includes a pixel driving circuit and a light emitting device.
  • the light-emitting device may be an OLED light-emitting device, including a stacked anode, an organic light-emitting layer, and a cathode.
  • the pixel driving circuit may include a plurality of thin film transistors and at least one storage capacitor.
  • the structure of the pixel driving circuit is described in detail by taking the 7T1C pixel driving circuit as an example.
  • the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. Any driving circuit structure can be applied to the embodiments of the present disclosure.
  • the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst.
  • the pixel driving circuit is used for driving organic light emitting diodes (ie OLEDs).
  • the plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • Each transistor includes a gate, a source and a drain.
  • the display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a scan signal line 61 for transmitting the scan signal Sn, and a line for transmitting the reset control signal RESET (ie, the scan signal of the previous row).
  • the gate G1 of the first transistor T1 is electrically connected to the reset signal line 62 , and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66 .
  • the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2 and the gate G3 of the third transistor T3.
  • the drain of the first transistor T1 D1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected to the node N1.
  • the first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset signal line 62 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to switch the gate G3 of the third transistor T3 to the gate G1. Voltage initialization. That is, the first transistor T1 is also referred to as an initialization transistor.
  • the gate G2 of the second transistor T2 is electrically connected to the scan signal line 61, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1.
  • the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing diode connection of the third transistor T3.
  • the gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3.
  • the third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. That is, the third transistor T3 is also referred to as a driving transistor.
  • the gate G4 of the fourth transistor T4 is electrically connected to the scan signal line 61, the source S4 of the fourth transistor T4 is electrically connected to the data line 64, and the drain D4 of the fourth transistor T4 is electrically connected to the node N2, that is, electrically connected to the first The source S3 of the three transistors T3.
  • the fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3.
  • the gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63 , and the source S5 of the fifth transistor T5 is electrically connected to the driving voltage line 65 . And the drain D5 of the fifth transistor T5 is electrically connected to the node N2.
  • the gate G6 of the sixth transistor T6 is electrically connected to the light emission control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the OLED the anode.
  • the fifth transistor T5 and the sixth transistor T6 are turned on concurrently (eg, simultaneously) according to the light emission control signal En transmitted through the light emission control line 63 to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED.
  • the gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62 , the source S7 of the seventh transistor T7 is electrically connected to the node N4 , and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66 .
  • One end (hereinafter referred to as a first capacitance electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1 , and the other end (hereinafter referred to as a second capacitance electrode) Cst2 is electrically connected to the driving voltage line 65 .
  • the anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to the power line 67 to receive the common voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.
  • each of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 are p-channel field effect transistors, but the embodiments of the present disclosure are not limited thereto, the thin film transistors T1, T2 At least some of , T3, T4, T5, T6, and T7 may be n-channel field effect transistors.
  • the reset control signal RESET having a low level is supplied through the reset signal line 62 .
  • the first transistor T1 is turned on based on the low level of the reset control signal RESET, and the initialization voltage Vint from the initialization voltage line 66 is transferred to the gate G1 of the third transistor T3 through the first transistor T1. Therefore, the third transistor T3 is initialized due to the initialization voltage Vint.
  • the scan signal Sn having a low level is supplied through the scan signal line 61 .
  • the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal Sn. Therefore, the third transistor T3 is placed in a diode-connected state and biased in the forward direction by the turned-on second transistor T2.
  • a compensation voltage Dm+Vth (eg, Vth is a negative value) obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal Dm supplied via the data line 64 is applied to the gate G3 of the third transistor T3.
  • the driving voltage VDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to the voltage difference between the respective terminals are stored in the storage capacitor Cst.
  • the light emission control signal En from the light emission control line 63 changes from high level to low level. Subsequently, in the light emission stage, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light emission control signal En.
  • a driving current is generated based on the difference between the voltage of the gate G3 of the third transistor T3 and the driving voltage VDD.
  • the driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the sixth transistor T6.
  • the gate-source voltage of the third transistor T3 is maintained at (Dm+Vth)-VDD due to the storage capacitor Cst.
  • the drive current Id is proportional to (Dm-VDD) 2 . Therefore, the driving current Id may not be affected by the variation of the threshold voltage Vth of the third transistor T3.
  • FIG. 5 is a schematic diagram illustrating a planar structure of a pixel driving circuit of one sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram showing a planar structure of a first semiconductor layer of the pixel driving circuit shown in FIG. 5 .
  • FIG. 7 is a schematic diagram showing a planar structure of a first conductive layer of the pixel driving circuit shown in FIG. 5 .
  • FIG. 8 is a schematic diagram showing a planar structure of a second conductive layer of the pixel driving circuit shown in FIG. 5 .
  • FIG. 9 is a schematic diagram showing a planar structure of a second semiconductor layer of the pixel driving circuit shown in FIG. 5 .
  • FIG. 6 is a schematic diagram showing a planar structure of a first semiconductor layer of the pixel driving circuit shown in FIG. 5 .
  • FIG. 7 is a schematic diagram showing a planar structure of a first conductive layer of the pixel driving circuit shown in FIG.
  • FIG. 10 is a schematic diagram showing a planar structure of a third conductive layer of the pixel driving circuit shown in FIG. 5 .
  • FIG. 11 is a schematic diagram showing a planar structure of a fourth conductive layer of the pixel driving circuit shown in FIG. 5 .
  • FIG. 12 is a schematic diagram showing a planar structure of a fifth conductive layer of the pixel driving circuit shown in FIG. 5 .
  • 13 is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line AA' and line BB' in FIG. 5 according to some exemplary embodiments of the present disclosure, and for convenience of description, it will be taken along line AA' in FIG. 5 The cross-sectional structure taken along the line BB' is shown in the same schematic diagram.
  • the display substrate includes a base substrate 10 and a plurality of film layers disposed on the base substrate 10 .
  • the plurality of film layers shown include at least a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70 and the fifth conductive layer 90 .
  • the first semiconductor layer 20 , the first conductive layer 30 , the second conductive layer 40 , the second semiconductor layer 50 , the third conductive layer 60 , the fourth conductive layer 70 and the fifth conductive layer 90 are disposed away from the base substrate 10 in sequence.
  • the first semiconductor layer 20 may be formed of a semiconductor material such as low temperature polysilicon, and its film thickness may be in the range of 400-800 angstroms, for example, 500 angstroms.
  • the second semiconductor layer 50 may be formed of an oxide semiconductor material, such as a polysilicon oxide semiconductor material such as IGZO, and its film thickness may be in the range of 300-600 angstroms, for example, 400 angstroms.
  • the first conductive layer 30 may be formed of a conductive material forming the gate of the thin film transistor, for example, the conductive material may be Mo, and the film thickness thereof may be in the range of 2000-3000 angstroms, such as 2500 angstroms.
  • the second conductive layer 40 may be formed of a conductive material forming the source and drain electrodes of the thin film transistor, for example, the conductive material may include Ti, Al, etc., and the second conductive layer 40 may have a stacked layer structure formed of Ti/Al/Ti , the film thickness can be in the range of 7000-9000 angstroms.
  • the thickness of each layer of Ti/Al/Ti may be about 500 angstroms, 5500 angstroms and 500 angstroms, respectively.
  • the third conductive layer 60 may be formed of a conductive material forming the gate of the thin film transistor, for example, the conductive material may be Mo, and the thickness of the film may be in the range of 2000-3000 angstroms, such as 2500 angstroms.
  • the fourth conductive layer 70 may be formed of a conductive material forming the source and drain electrodes of the thin film transistor, for example, the conductive material may include Ti, Al, etc., and the fourth conductive layer 70 may have a stacked layer structure formed of Ti/Al/Ti , the film thickness can be in the range of 7000-9000 angstroms.
  • the thickness of each layer of Ti/Al/Ti may be about 500 angstroms, 5500 angstroms and 300 angstroms, respectively.
  • the fifth conductive layer 90 may be formed of a conductive material forming the source and drain electrodes of the thin film transistor, for example, the conductive material may include Ti, Al, etc., and the fourth conductive layer 70 may have a stacked layer structure formed of Ti/Al/Ti .
  • the display substrate includes scan signal lines 61, reset signal lines 62, light emission control lines 63, and initialization voltages arranged along the row direction to apply the scan signal Sn, the reset control signal RESET, the light emission control signal En, and the initialization voltage Vint to the sub-pixels, respectively.
  • Voltage lines 66 The display substrate may further include a data line 64 and a driving voltage line 65 crossing the scan signal line 61, the reset signal line 62, the light emission control line 63 and the initialization voltage line 66 to apply the data signal Dm and the driving voltage VDD to the sub-pixels, respectively. .
  • the pixel driving circuit of the display substrate may include: a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and The seventh transistor T7, and the storage capacitor Cst.
  • the first transistor T1 and the second transistor T2 may be formed along the second semiconductor layer as shown in FIG. 9 .
  • the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 may be formed along the first semiconductor layer 20 as shown in FIG. 6 .
  • the first semiconductor layer 20 may have a bent or bent shape, and may include a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, The fifth active layer 20e corresponding to the fifth transistor T5, the sixth active layer 20f corresponding to the sixth transistor T6, and the seventh active layer 20g corresponding to the seventh transistor T7.
  • the first semiconductor layer 20 may include polysilicon, such as a low temperature polysilicon material.
  • the active layer of each transistor may include a channel region, a source region and a drain region.
  • the channel region may be undoped or of a different type of doping than the source and drain regions, and thus have semiconductor properties.
  • the source region and the drain region are located on both sides of the channel region, respectively, and are doped with impurities and thus have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor.
  • the third transistor T3 includes a third active layer 20c and a third gate G3.
  • the third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c.
  • the third source region 203c and the third drain region 205c extend in opposite directions with respect to the third channel region 201c.
  • the fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4.
  • the fourth active layer 20d includes a fourth source region 203d, a fourth drain region 205d, and a fourth channel region 201d connecting the fourth source region 203d and the fourth drain region 205d.
  • the fourth source region 203d and the fourth drain region 205d extend in opposite directions with respect to the fourth channel region 201d.
  • the fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5.
  • the fifth active layer 20e includes a fifth source region 203e, a fifth drain region 205e, and a fifth channel region 201e connecting the fifth source region 203e and the fifth drain region 205e.
  • the fifth source region 203e and the fifth drain region 205e extend in opposite two directions with respect to the fifth channel region 201e.
  • the sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6.
  • the sixth active layer 20f includes a sixth source region 203f, a sixth drain region 205f, and a sixth channel region 201f connecting the sixth source region 203f and the sixth drain region 205f.
  • the sixth source region 203f and the sixth drain region 205f extend in opposite two directions with respect to the sixth channel region 201f.
  • the seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7.
  • the seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g connecting the seventh source region 203g and the seventh drain region 205g.
  • the seventh source region 203g and the seventh drain region 205g extend in opposite two directions with respect to the seventh channel region 201g.
  • the scan signal line 61 , the reset signal line 62 and the light emission control line 63 are all located in the first conductive layer 30 .
  • the gate structure CG1 is also located in the first conductive layer 30 .
  • the portion of the gate structure CG1 overlapping with the first semiconductor layer 20 forms the third gate G3 of the third transistor T3.
  • the portion of the scan signal line 61 overlapping the first semiconductor layer 20 forms the fourth gate G4 of the fourth transistor T4.
  • a portion of the light emission control line 63 overlapping with the first semiconductor layer 20 forms the fifth gate G5 of the fifth transistor T5.
  • Another portion of the light emission control line 63 overlapping the first semiconductor layer 20 forms the sixth gate G6 of the sixth transistor T6.
  • the portion of the reset signal line 62 overlapping the first semiconductor layer 20 forms the seventh gate G7 of the seventh transistor T7.
  • the gate structure CG1 also forms part of a first capacitive structure, eg, one capacitive electrode (eg, the first capacitive electrode Cst1 ) of the storage capacitor Cst. That is, the gate structure CG1 serves as both the gate of the third transistor T3 and one electrode of the storage capacitor Cst.
  • the second conductive layer 40 includes a first bottom gate structure BG1 , a second bottom gate structure BG2 and a second capacitor structure CP2 .
  • the initialization voltage lines 66 are also located in the second conductive layer 40 .
  • the second conductive layer 40 includes a through hole 40H formed in the second capacitor structure CP2 .
  • the second semiconductor layer 50 includes a first active layer 20a corresponding to the first transistor T1 and a second active layer 20b corresponding to the second transistor T2.
  • the first active layer 20a of the first transistor T1 and the second active layer 20b of the second transistor T2 extend in the same direction as the data line, that is, both extend in the up-down direction in the figure.
  • the second semiconductor layer 50 may include an oxide semiconductor material, such as a low temperature polysilicon oxide semiconductor material (abbreviated as LTPO).
  • the active layer of each transistor may include a channel region, a source region and a drain region.
  • the channel region may be undoped or of a different type of doping than the source and drain regions, and thus have semiconductor properties.
  • the source region and the drain region are located on both sides of the channel region, respectively, and are doped with impurities and thus have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor.
  • the first active layer 20a of the first transistor T1 includes a first source region 203a, a first drain region 205a, and a first channel region 201a connecting the first source region 203a and the first drain region 205a.
  • the first source region 203a and the first drain region 205a extend in opposite directions with respect to the first channel region 201a.
  • the second active layer 20b of the second transistor T2 includes a second source region 203b, a second drain region 205b, and a second channel region 201b connecting the second source region 203b and the second drain region 205b.
  • the second source region 203b and the second drain region 205b extend in opposite directions with respect to the second channel region 201b.
  • the orthographic projection of the first active layer 20a on the base substrate 10 at least partially overlaps with the orthographic projection of the first bottom gate structure BG1 on the base substrate 10, the first bottom gate
  • the portion of the structure BG1 overlapping the first active layer 20a constitutes the first bottom gate G11 of the first transistor T1.
  • the orthographic projection of the second active layer 20b on the base substrate 10 and the orthographic projection of the second bottom gate structure BG2 on the base substrate 10 at least partially overlap, and the second bottom gate structure BG2 overlaps with the second active layer 20b.
  • Part of the second bottom gate G21 of the second transistor T2 is formed.
  • the first bottom gate structure BG1 includes a first bottom gate body part BG11 and a first bottom gate extension part BG12 .
  • the orthographic projection of the first bottom gate body portion BG11 on the base substrate 10 is rectangular.
  • the orthographic projection of the first bottom gate body portion BG11 on the base substrate 10 at least partially overlaps with the orthographic projection of the active layer of the first transistor T1 on the base substrate 10
  • the first The bottom gate G11 includes a portion where the first bottom gate body portion BG11 overlaps with the active layer of the first transistor T1.
  • the second bottom gate structure BG2 includes a second bottom gate body portion BG21 and a second bottom gate extension portion BG22.
  • the orthographic projection of the second bottom gate body portion BG21 on the base substrate 10 has a rectangular shape.
  • the orthographic projection of the second bottom gate body portion BG21 on the base substrate 10 at least partially overlaps with the orthographic projection of the active layer of the second transistor T2 on the base substrate 10, and the second The bottom gate G21 includes a portion where the second bottom gate body portion BG21 overlaps with the active layer of the second transistor T2.
  • the first bottom gate extension part BG12 and the second bottom gate extension part BG22 both extend in the row direction, that is, in the left and right direction in the figure. That is, the extending direction of the first bottom gate extension portion BG12 and the extending direction of the second bottom gate extending portion BG22 is substantially parallel to the extending direction of the initialization voltage line 66 .
  • the second semiconductor layer 50 further includes a third capacitance structure CP3.
  • the third capacitive structure CP3 includes a portion of the conductive second semiconductor layer 50 .
  • the second semiconductor layer 50 such as IGZO is formed, it can be H-doped with SiH4 in the film-forming gas to reduce its resistivity, thereby forming a portion of the conductive second semiconductor layer 50 to form The third capacitor structure CP3.
  • the first capacitance structure CG1 , the second capacitance structure CP2 and the third capacitance structure CP3 are spaced apart and opposite to each other, and the first capacitance structure CG1 , the second capacitance structure
  • the orthographic projections of the CP2 and the third capacitive structure CP3 on the base substrate 10 at least partially overlap each other.
  • the first capacitance structure CG1 is electrically connected to the third capacitance structure CP3 through the conductive plug formed in the through hole 40H, so that the first capacitance structure CG1 and the third capacitance structure CP3 which are electrically connected to each other form the first capacitance structure of the storage capacitor.
  • the second capacitance structure CP2 is located between the first capacitance structure CG1 and the third capacitance structure CP3, and forms a second capacitance electrode Cst2 of the storage capacitor.
  • the first capacitor electrode Cst1 may be electrically connected to the node N1
  • the second capacitor electrode Cst2 may be electrically connected to VDD, so that a storage capacitor may be formed between the first capacitor electrode Cst1 and the second capacitor electrode Cst2.
  • capacitances can be formed between the first capacitance structure CG1 and the second capacitance structure CP2 and between the second capacitance structure CP2 and the third capacitance structure CP3 respectively, and the sum of the capacitance values of the two capacitances is equal to the Capacitance value of the storage capacitor. That is to say, in this way, the capacitance value of the storage capacitor can be improved, thereby improving the performance of the pixel driving circuit.
  • the third conductive layer 60 includes a first top gate structure TG1 and a second top gate structure TG2.
  • the first top gate structure TG1 extends along the horizontal direction in FIG. 10 .
  • the first top gate structure TG1 may include a first widened portion TG11, and the size of the first widened portion TG11 in the vertical direction is larger than that of the rest of the first top gate structure TG1 in the vertical direction. size.
  • the orthographic projection of the first widened portion TG11 on the base substrate 10 at least partially overlaps with the orthographic projection of the active layer 20a of the first transistor T1 on the base substrate 10
  • the first The top gate G12 includes a portion where the first widened portion TG11 overlaps with the active layer 20a of the first transistor T1.
  • each of the second active layer 20 b and the second bottom gate structure BG2 on the base substrate 10 at least partially overlaps with the orthographic projection of the second top gate structure TG2 on the base substrate 10 .
  • the overlapping portion of the second top gate structure TG2 and the second active layer 20b constitutes the second top gate G22 of the second transistor. 12 , in a direction perpendicular to the upper surface of the base substrate 10 (ie, along the vertical direction shown in FIG. 12 ), the second active layer 20 b is located between the second bottom gate G21 and the second top gate G22 between. In this way, the second transistor T2 has a double gate structure.
  • the second top gate structure TG2 extends along the horizontal direction in FIG. 10 .
  • the second top gate structure TG2 may include a second widened portion TG21, and the size of the second widened portion TG21 in the vertical direction is larger than that of the rest of the second top gate structure TG2 in the vertical direction. size.
  • the orthographic projection of the second widening portion TG21 on the base substrate 10 at least partially overlaps with the orthographic projection of the active layer 20b of the second transistor T2 on the base substrate 10, and the second The top gate G22 includes a portion where the second widened portion TG21 overlaps with the active layer 20b of the second transistor T2.
  • the fourth conductive layer 70 includes a driving voltage line 65 , a first conductive member 701 , a second conductive member 702 , a third conductive member 703 , a fourth conductive member 704 and a fifth conductive member 705 .
  • the driving voltage line 65 is electrically connected to the source region 203e of the fifth transistor T5 through the via hole VAH12. The portion of the driving voltage line 65 overlapping with the source region 203e of the fifth transistor T5 constitutes the source of the fifth transistor T5.
  • One end of the first conductive member 701 is electrically connected to the source region 203a of the first transistor T1 through the via hole VAH2.
  • a portion of the first conductive member 701 is also electrically connected to the initialization voltage line 66 through the via hole VAH3.
  • the other end of the first conductive part 701 is electrically connected to the first conductive member 401 through the via hole VAH4.
  • the source of the first transistor T1 and the drain of the seventh transistor T7 are electrically connected, and both are electrically connected to the initialization voltage line 66 .
  • the initialization voltage Vint may be applied to the source of the first transistor T1 and the drain of the seventh transistor T7.
  • One end of the second conductive member 702 is electrically connected to the drain region 205b of the second transistor T2 through the via hole VAH7, and the other end of the second conductive member 702 is electrically connected to the drain region 203a of the first transistor T1 and the third conductive member through the via hole VAH6
  • Components 703 are electrically connected.
  • One end of the third conductive member 703 is electrically connected to the second conductive member 702 through the via hole VAH6, and the other end of the third conductive member 703 is electrically connected to the gate G1 of the third transistor T3 and the first capacitor electrode Cst1 through the via hole VAH8, That is, the node N1 in FIG. 4 is formed.
  • the drain of the first transistor T1, the drain of the second transistor T2, the gate of the third transistor T3 and the first capacitor electrode Cst1 can be electrically connected to each other. Referring to FIG. 4, they are all electrically connected to the node N1. .
  • One end of the fourth conductive member 704 is electrically connected to the source region 203b of the second transistor T2 through the via hole VAH9, and the other end of the fourth conductive member 704 is electrically connected to the source region 203b of the sixth transistor T6 through the via hole VAH10. In this way, the electrical connection between the source of the second transistor T2 and the source of the sixth transistor T6 can be realized, and referring to FIG. 4 , both are electrically connected to the node N3 .
  • One end of the fifth conductive member 705 is electrically connected to the drain region 205f of the sixth transistor T6 and the source region 203g of the seventh transistor T7 through the via hole VAH13, and the other end is electrically connected to the first electrode (eg, the anode electrode) of the light emitting device through the via hole VAH14. , will be described below) electrical connection.
  • the electrical connection between the drain electrode of the sixth transistor T6, the source electrode of the seventh transistor T7 and the first electrode of the light emitting device can be realized. Referring to FIG. 4, they are all electrically connected to the node N4.
  • the fifth conductive layer 90 includes the data line 64 and the light shielding layer 902 .
  • the data line 64 is electrically connected to the source region 203d of the fourth transistor T4 through the via hole VAH1 to apply the data signal Dm to the source of the fourth transistor T4. That is, the portion of the data line 64 overlapping the source region 203d of the fourth transistor T4 constitutes the source of the fourth transistor T4.
  • the orthographic projection of the light shielding layer 902 on the base substrate 10 covers the orthographic projection of each of the first transistor T1 and the second transistor T2 on the base substrate 10 .
  • the orthographic projection of the light shielding layer 902 on the base substrate 10 covers the orthographic projection of each of the active layer 20a of the first transistor T1 and the active layer 20b of the second transistor T2 on the base substrate 10 .
  • the light-shielding layer 902 can be electrically connected to a fixed voltage to prevent the potential of the light-shielding layer from floating, so as to prevent the light-shielding layer from adversely affecting the performance of the transistor.
  • the light shielding layer 902 may be electrically connected to the second capacitor electrode Cst2 through the via hole VAH15, that is, electrically connected to the VDD voltage.
  • the active layers of the first transistor T1 and the second transistor T2 are both formed of an oxide semiconductor material such as LTPO, which can improve the voltage at the node N1 (as shown in FIG. 4 ) in the pixel driving circuit. voltage stability, thereby improving the display performance of the display panel.
  • both the first transistor T1 and the second transistor T2 have a double gate structure, so that the stability of the first transistor T1 and the second transistor T2 and the uniformity of the threshold voltage (Vth) are improved, so that the display panel can be further improved. performance.
  • the bottom gates G11 and G21 of the transistors T1 and T2 not only function as bottom gates, but also function as light shielding layers, which can prevent external light from affecting the transistors T1 and T2.
  • the interference of the source layers 20a and 20b is beneficial to further improve the performance of the transistor.
  • FIG. 14 is a schematic diagram illustrating a planar structure of a display substrate according to some exemplary embodiments of the present disclosure, in which a planar structure of a first electrode of a light emitting device is schematically illustrated.
  • FIG. 15 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.
  • the light-emitting device may be an organic light-emitting diode, which may include a first electrode, an organic light-emitting layer and a second electrode disposed on the base substrate 10, wherein the first electrode may be one of an anode and a cathode, and the first electrode may be one of an anode and a cathode.
  • the second electrode may be the other of the anode and the cathode.
  • the first electrode, the organic light-emitting layer, and the second electrode may be disposed away from the base substrate 10 in sequence.
  • the first electrode 80 may include an electrode main body part 801 and an electrode connection part 802 .
  • the electrode body portion 801 may have a substantially rectangular shape, that is, the orthographic projection of the electrode body portion 801 on the base substrate 10 is substantially rectangular.
  • the electrode body part 801 may have any suitable shape, for example, a hexagon, an octagon, and the like.
  • the electrode main body portion 801 and the electrode connection portion 802 may be connected integrally.
  • the electrode connection portion 802 is electrically connected to one end of the fifth conductive member 705 through the via hole VAH14.
  • the other end of the fifth conductive member 705 is electrically connected to the drain electrode of the sixth transistor T6 and the source electrode of the seventh transistor T7 through the via hole VAH13.
  • the first electrode 80 is electrically connected to the drain of the sixth transistor T6 and the source of the seventh transistor T7.
  • the orthographic projection of the first electrode 80 on the base substrate 10 at least covers the orthographic projection of the active layer 20 a of the first transistor T1 on the base substrate 10 .
  • the orthographic projection of the first electrode 80 on the base substrate 10 is spaced apart from the orthographic projection of the active layer 20b of the second transistor T2 on the base substrate 10 .
  • the display substrate may include a barrier layer 161 disposed on the base substrate 10 ; and a first buffer layer 162 disposed on a side of the barrier layer 161 away from the base substrate 10 .
  • the barrier layer 161 may be formed of silicon oxide with a thickness of about 5500 angstroms.
  • the first buffer layer 162 may be formed of silicon nitride with a thickness of about 1000 angstroms; alternatively, the first buffer layer 162 may be formed of a stack of silicon nitride and silicon oxide.
  • the first buffer layer 162 may include a first buffer sublayer disposed on the barrier layer 161 and a second buffer sublayer disposed on a side of the first buffer sublayer away from the base substrate 10 , and the first buffer sublayer includes nitrogen Silicon oxide material, and the second buffer sub-layer includes silicon oxide material.
  • the display substrate may include a first gate insulating layer GI1 disposed between the first semiconductor layer 20 and the first conductive layer 30 .
  • the first gate insulating layer GI1 may be formed of silicon oxide.
  • the display substrate may include a second gate insulating layer GI2 disposed between the first conductive layer 30 and the second conductive layer 40 .
  • the second gate insulating layer GI2 may be formed of silicon nitride.
  • the second gate insulating layer GI2 formed of silicon nitride can supply hydrogen (H) to the first transistor to improve the performance of the first transistor.
  • the display substrate may include a second buffer layer 163 disposed between the second gate insulating layer GI2 and the second conductive layer 40 .
  • the second buffer layer 163 may be formed of silicon nitride or silicon oxide.
  • the display substrate may include a third gate insulating layer GI3 disposed between the second conductive layer 40 and the second semiconductor layer 50 .
  • the third gate insulating layer GI3 may be formed of silicon oxide.
  • the third gate insulating layer GI3 formed of silicon oxide can block the penetration of hydrogen (H) into the oxide semiconductor transistors (ie T1 , T2 ) to improve the performance of the oxide semiconductor transistors (ie T1 , T2 ).
  • the display substrate may include a fourth gate insulating layer GI4 disposed between the second semiconductor layer 50 and the third conductive layer 60 .
  • the fourth gate insulating layer GI4 may be formed of silicon oxide.
  • the fourth gate insulating layer GI4 formed of silicon oxide can block the penetration of hydrogen (H) into the oxide semiconductor transistors (ie T1 , T2 ) to improve the performance of the oxide semiconductor transistors (ie T1 , T2 ).
  • the first active layer 20a is close to the surface of the base substrate 10 (eg, the lower surface of the first active layer 20a in FIG. 13 ) and the first bottom gate G11 is far away from all
  • the distance between the surfaces of the base substrate 10 (for example, the upper surface of the first bottom gate G11 in FIG. 13 ) is greater than the distance between the surfaces of the first active layer 20a away from the base substrate (for example, the first bottom gate G11 in FIG. 13 ).
  • the distance between the upper surface of the active layer 20 a ) and the surface of the first top gate G12 close to the base substrate 10 (eg, the lower surface of the first top gate G12 in FIG. 13 ).
  • the first active layer 20a is close to the surface of the base substrate 10 (eg, the lower surface of the first active layer 20a in FIG. 13 ) and the first bottom gate G11 is far from the base substrate 10 .
  • the distance between surfaces eg, the upper surface of the first bottom gate G11 in FIG. 13
  • the surface of the first active layer 20a far away from the base substrate eg, the upper surface of the first active layer 20a in FIG. 13
  • the surface of the first top gate G12 close to the base substrate 10 (eg, the upper surface of the first active layer 20a in FIG. 13 )
  • the distance between the lower surfaces of the first top gates G12 in FIG. 13 may be in the range of 1000 ⁇ 2000 angstroms, such as 1300 angstroms, 1500 angstroms.
  • the first active layer 20a is close to the surface of the base substrate 10 (eg, the lower surface of the first active layer 20a in FIG. 13 ) and the first bottom gate G11 is far away from all
  • the distance between the surface of the base substrate 10 (for example, the upper surface of the first bottom gate G11 in FIG. 13 ) is greater than the distance between the surface of the third active layer 20c away from the base substrate 10 and the third gate
  • the distance between the poles G3 and the surface of the base substrate 10 is close.
  • the distance between the surface of the third active layer 20c away from the base substrate 10 and the surface of the third gate G3 close to the base substrate 10 may be in the range of 1000-2000 angstroms. Such as 1300 angstroms, 1500 angstroms.
  • the surface of the first active layer 20a away from the base substrate (eg, the upper surface of the first active layer 20a in FIG. 13 ) and the first top gate G12 are close to the The distance between the surface of the base substrate 10 (for example, the lower surface of the first top gate G12 in FIG. 13 ), and the surface of the third active layer 20c away from the base substrate 10 and the third gate The distances between the surfaces of G3 close to the base substrate 10 are approximately equal.
  • the display substrate may include an interlayer insulating layer ILD disposed between the third conductive layer 60 and the fourth conductive layer 70 and between the second semiconductor layer 50 and the fourth conductive layer 70 .
  • the interlayer insulating layer ILD may be formed of a single layer of silicon oxide, or may be formed of a stacked-layer structure of silicon oxide and silicon nitride.
  • the interlayer insulating layer ILD may include a first interlayer insulating sublayer formed of silicon oxide and a second interlayer insulating sublayer formed of silicon nitride, the first interlayer insulating sublayer being closer to the liner than the second interlayer insulating sublayer base substrate 10 .
  • a third gate insulating layer GI3 is provided between the bottom gate G11 and the active layer 20a, but not provided other insulating layers. In this way, the distance between the bottom gate G11 and the active layer 20a is reduced, which is conducive to forming a good double gate drive in the first transistor, and is conducive to providing the driving capability of the transistor, thereby improving the carrier mobility and electrical conductivity of the transistor. Reliability. It should be understood that the second transistor T2 also has the same structure and effect.
  • FIG. 16 is a schematic diagram illustrating a planar structure of a pixel driving circuit of one sub-pixel of a display substrate according to other exemplary embodiments of the present disclosure.
  • FIG. 17 is a schematic diagram showing a planar structure of a second semiconductor layer of the pixel driving circuit shown in FIG. 16 .
  • FIG. 18 is a schematic diagram showing a planar structure of a third conductive layer of the pixel driving circuit shown in FIG. 16 .
  • the display substrate includes a base substrate 10 and a plurality of film layers disposed on the base substrate 10 .
  • the plurality of film layers shown include at least a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70 and the fifth conductive layer 90 .
  • the first semiconductor layer 20 , the first conductive layer 30 , the second conductive layer 40 , the second semiconductor layer 50 , the third conductive layer 60 , the fourth conductive layer 70 and the fifth conductive layer 90 are disposed away from the base substrate 10 in sequence.
  • the first semiconductor layer 20 , the first conductive layer 30 , the second conductive layer 40 , the fourth conductive layer 70 and the fifth conductive layer 90 may refer to the above description.
  • the second semiconductor layer 50' includes a first active layer 20a corresponding to the first transistor T1 and a second active layer 20b corresponding to the second transistor T2.
  • the first active layer 20a of the first transistor T1 and the second active layer 20b of the second transistor T2 extend in the same direction as the data line, that is, both extend in the up-down direction in the figure.
  • the third conductive layer 60' includes a first top gate structure TG1 and a second top gate structure TG2.
  • first active layer 20a the second active layer 20b, the first top gate structure TG1 and the second top gate structure TG2
  • the third capacitance structure CP3 is formed in the third conductive layer 60' but not in the second semiconductor layer 50'. As shown in FIG. 18, the third conductive layer 60' includes a third capacitance structure CP3.
  • FIG. 19 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure. 16 to 19 , the first capacitor structure CG1 , the second capacitor structure CP2 and the third capacitor structure CP3 are spaced apart and opposite to each other, and the first capacitor structure CG1 , the second capacitor structure CP2 and the third capacitor structure CP3 are lined with The orthographic projections on the base substrate 10 at least partially overlap each other.
  • the first capacitance structure CG1 is electrically connected to the third capacitance structure CP3 through the conductive plug formed in the through hole 40H, so that the first capacitance structure CG1 and the third capacitance structure CP3 which are electrically connected to each other form the first capacitance structure of the storage capacitor.
  • the second capacitance structure CP2 is located between the first capacitance structure CG1 and the third capacitance structure CP3, and forms a second capacitance electrode Cst2 of the storage capacitor.
  • the first capacitor electrode Cst1 may be electrically connected to the node N1, and the second capacitor electrode Cst2 may be electrically connected to VDD, so that a storage capacitor may be formed between the first capacitor electrode Cst1 and the second capacitor electrode Cst2.
  • capacitances can be formed between the first capacitance structure CG1 and the second capacitance structure CP2 and between the second capacitance structure CP2 and the third capacitance structure CP3 respectively, and the sum of the capacitance values of the two capacitances is equal to the Capacitance value of the storage capacitor.
  • a second gate insulating layer GI2 and a second buffer layer 163 are disposed between the first capacitor structure CG1 and the second capacitor structure CP2.
  • a third gate insulating layer GI3 and a fourth gate insulating layer GI4 are provided between the second capacitor structure CP2 and the third capacitor structure CP3, a third gate insulating layer GI3 and a fourth gate insulating layer GI4 are provided.
  • a storage capacitor having an increased capacitance value is formed. That is to say, in this way, the capacitance value of the storage capacitor can be improved, thereby improving the performance of the pixel driving circuit.
  • FIG. 20 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.
  • the above-mentioned second buffer layer 163 is removed.
  • a third gate insulating layer GI3 is provided between the bottom gate (eg G11 or G21) of the transistor and the active layer (20a or 20b), and the third gate insulating layer GI3 includes a silicon oxide material, which can block hydrogen (H ) into the channel region of the transistor.
  • the second gate insulating layer GI2 is disposed between the first capacitor structure CG1 and the second capacitor structure CP2. In this way, the distance between the first capacitance structure CG1 and the second capacitance structure CP2 is reduced, so the capacitance value of the capacitance formed between the first capacitance structure CG1 and the second capacitance structure CP2 is increased, so that the total capacitance can be increased. the overall capacitance value of the storage capacitor.
  • FIG. 21 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.
  • the third gate insulating layer GI3 between the second capacitance structure CP2 and the third capacitance structure CP3 is removed, that is, only between the second capacitance structure CP2 and the third capacitance structure CP3
  • a fourth gate insulating layer GI4 is provided. In this way, the distance between the second capacitance structure CP2 and the third capacitance structure CP3 is reduced, so the capacitance value of the capacitance formed between the second capacitance structure CP2 and the third capacitance structure CP3 increases, which can further increase The overall capacitance value of the storage capacitor.
  • FIG. 22 is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.
  • the fourth conductive layer 70 may have a laminated structure.
  • the fourth conductive layer 70 may include a first conductive sub-layer 70A and a second conductive sub-layer 70B.
  • the first conductive sub-layer 70A is disposed on the interlayer insulating layer ILD
  • the second conductive sub-layer 70B is disposed on the side of the first conductive sub-layer 70A away from the base substrate 10
  • the first conductive sub-layer 70A and the second conductive sub-layer 70B The layers 70B are in contact with each other.
  • the material of the first conductive sub-layer 70A may include Mo, or may include Ti, Al, or the like.
  • the material of the second conductive sub-layer 70B may include a conductive material that forms the source and drain electrodes of the thin film transistor, for example, the conductive material may include Ti, Al, and the like.
  • FIG. 23 is a flowchart of a method of manufacturing a display substrate according to some exemplary embodiments of the present disclosure.
  • FIGS. 24 to 28 are schematic diagrams of cross-sectional structures of the display substrate formed after some steps in the manufacturing method shown in FIG. 23 are performed, respectively. 22 to 28 , the manufacturing method of the display substrate may be performed according to the following steps.
  • the base substrate 10 is prepared.
  • the base substrate 10 may be, for example, polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide, polyether Organic flexible substrates formed from sulfones, etc.
  • the base substrate 10 may have a single-layer structure or a double-layer structure.
  • the substrate substrate 10 may include a first substrate, a first barrier layer, and a second substrate, and the first barrier layer is disposed between the first substrate and the second substrate.
  • the thickness of the base substrate 10 is approximately in the range of 5-20 microns.
  • a barrier layer 161 , a first buffer layer 162 , a first semiconductor layer 20 , a first gate insulating layer GI1 , a first conductive layer 30 , a second gate insulating layer GI2 , and a second conductive layer are sequentially prepared on the base substrate 10 40.
  • a plurality of via holes VA1, VA2 are formed in the interlayer insulating layer IDL, and the plurality of via holes VA1, VA2 penetrate the interlayer insulating layer IDL to expose the oxide semiconductor transistors, respectively The source region and the drain region of the active layer (ie the first transistor and the second transistor described above).
  • a first conductive material layer CL1 is deposited on a side of the interlayer insulating layer IDL away from the base substrate 10 .
  • the first conductive material layer CL1 may include Mo.
  • the first conductive material layer CL1 may be filled in the plurality of via holes VA1, VA2 to be in contact with the source region and the drain region of the active layer of the first transistor or the second transistor.
  • step S234 a plurality of via holes VA3, VA4 are formed, each of the plurality of via holes VA3, VA4 penetrating the first conductive material layer CL1, the interlayer insulating layer IDL, and the third gate insulating layer GI3 , the second gate insulating layer GI2 and the first gate insulating layer GI1 to expose source and drain regions of the active layers of the polycrystalline silicon semiconductor transistors (ie, the third to seventh transistors described above), respectively.
  • the plurality of via holes VA3 and VA4 are formed through a dry etching process, and then an etching solution needs to be used for cleaning. Under the protection of the first conductive material layer CL1, the etching solution will not damage the interlayer insulating layer IDL and the active layers of the oxide semiconductor transistor (ie, the active layers 20a and 20b).
  • a second conductive material layer CL2 is deposited on a side of the first conductive material layer CL1 away from the base substrate 10 .
  • the second conductive material layer CL2 may include Ti, Al, or the like.
  • the second conductive material layer CL2 is stacked on the first conductive material layer CL1, and is also filled in the plurality of via holes VA3, VA4 to be connected with the source region and the drain region of the active layer of the polysilicon semiconductor transistor touch.
  • step S236 the first conductive material layer CL1 and the second conductive material layer CL2 are patterned through a patterning process to form source electrodes and drain electrodes of a plurality of transistors. In this way, it is beneficial to reduce the number of patterning processes, thereby saving the number of masks.
  • the display device may include the display substrate as described above.
  • the display device may include any device or product having a display function.
  • the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio Players, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic clothing, electronic wristbands, electronic necklaces, electronic accessories, electronic tattoos, or smart watches), TV sets, etc.
  • the display panel and the display device according to the embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. For details, reference may be made to the above description, which will not be repeated here.

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Abstract

一种显示基板、显示面板(110)和显示装置(1000)。显示基板包括衬底基板(10)；设置于衬底基板(10)的第一晶体管(T1)。第一晶体管(T1)包括第一有源层(20a)、第一底栅(G11)和第一顶栅(G12)，第一底栅(G11)位于衬底基板(10)与第一有源层(20a)之间，第一顶栅(G12)位于第一有源层(20a)远离衬底基板(10)的一侧，第一有源层(20a)、第一底栅(G11)和第一顶栅(G12)中的任意两个在衬底基板(10)上的正投影彼此至少部分重叠，第一底栅(G11)和第一有源层(20a)之间设置有第三栅绝缘层(GI3)，第一有源层(20a)包括氧化物半导体材料，第三栅绝缘层(GI3)包括氧化硅材料，第一顶栅(G12)远离衬底基板(10)的表面与氧化硅材料直接接触，第一有源层(20a)靠近衬底基板(10)的表面与氧化硅材料直接接触。

Description

显示基板、显示面板和显示装置 技术领域
本公开涉及显示技术领域，并且具体地涉及一种显示基板、显示面板和显示装置。
背景技术
有机发光二极管(缩写为OLED)显示装置是一类使用发光的OLED来显示图像等信息的显示装置。OLED显示装置具有诸如低功耗、高亮度和高响应速度的特性。低温多晶硅氧化物薄膜晶体管(Low Temperature Poly-Oxide TFT，以下简称LTPO TFT)技术是近年来新兴的薄膜晶体管技术。从理论上讲，LTPO TFT相比传统的低温多晶硅薄膜晶体管(Low Temperature Poly-Silicon TFT，以下简称LTPS TFT)技术而言，可以节省5-15％的电量，让整块显示屏幕的功耗更低。
在本部分中公开的以上信息仅用于对本公开的技术构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示基板，其中，所述显示基板包括：
衬底基板；以及
设置于所述衬底基板的第一晶体管，
其中，所述第一晶体管包括第一有源层、第一底栅和第一顶栅，所述第一底栅位于所述衬底基板与所述第一有源层之间，所述第一顶栅位于所述第一有源层远离所述衬底基板的一侧，所述第一有源层、所述第一底栅和所述第一顶栅中的任意两个在所述衬底基板上的正投影彼此至少部分重叠，所述第一底栅和所述第一有源层之间设置有第三栅绝缘层，所述第一有源层包括氧化物半导体材料，所述第三栅绝缘层包括氧化硅材料，所述第一顶栅远离所述衬底基板的表面与所述氧化硅材料直接接触，所述第一有源层靠近所述衬底基板的表面与所述氧化硅材料直接接触。
根据一些示例性实施例，所述显示基板包括：
设置于所述衬底基板的第一半导体层；和
设置于所述第一半导体层远离所述衬底基板一侧的第二半导体层，
其中，所述显示基板还包括第三晶体管，
所述第三晶体管包括第三有源层和第三栅极，所述第三有源层包括多晶硅半导体材料，所述第三有源层位于所述第一半导体层，所述第一有源层位于所述第二半导体层。
根据一些示例性实施例，所述第一有源层靠近所述衬底基板的表面与所述第一底栅远离所述衬底基板的表面之间的距离，大于所述第一有源层远离所述衬底基板的表面与所述第一顶栅靠近所述衬底基板的表面之间的距离。
根据一些示例性实施例，所述第一有源层靠近所述衬底基板的表面与所述第一底栅远离所述衬底基板的表面之间的距离，大于所述第三有源层远离所述衬底基板的表面与所述第三栅极靠近所述衬底基板的表面之间的距离。
根据一些示例性实施例，所述第一有源层远离所述衬底基板的表面与所述第一顶栅靠近所述衬底基板的表面之间的距离，与所述第三有源层远离所述衬底基板的表面与所述第三栅极靠近所述衬底基板的表面之间的距离大致相等。
根据一些示例性实施例，所述显示基板还包括第二晶体管，所述第二晶体管包括第二底栅和第二顶栅，所述第二底栅位于所述衬底基板与所述第二晶体管的有源层之间，所述第二顶栅位于所述第二晶体管的有源层远离所述衬底基板的一侧，所述第二晶体管的有源层、所述第二底栅和所述第二顶栅中的任意两个在所述衬底基板上的正投影彼此至少部分重叠。
根据一些示例性实施例，所述显示基板包括存储电容器，所述存储电容器包括设置于所述衬底基板的第一电容结构、第二电容结构和第三电容结构，所述第三电容结构位于所述第一电容结构远离所述衬底基板的一侧，所述第二电容结构位于所述第一电容结构和所述第三电容结构之间，所述第一电容结构、所述第二电容结构和所述第三电容结构中的任意两者在所述衬底基板上的正投影至少部分重叠；以及
所述第一电容结构和所述第三电容结构彼此电连接，以形成所述存储电容器的第一电容电极，所述第二电容结构形成所述存储电容器的第二电容电极。
根据一些示例性实施例，所述显示基板包括设置于所述衬底基板的第一导电层，所述第一导电层位于所述第一半导体层远离所述衬底基板的一侧；以及所述第一电容结构和所述第三晶体管的第三栅极均位于所述第一导电层。
根据一些示例性实施例，所述显示基板包括设置于所述衬底基板的第二导电层，所述第二导电层位于所述第一导电层与所述第二半导体层之间；以及所述第一底栅和所述第二电容结构均位于所述第二导电层。
根据一些示例性实施例，所述显示基板包括设置于所述衬底基板的第三导电层，所述第三导电层位于所述第二半导体层远离所述衬底基板的一侧；以及所述第一顶栅和所述第三电容结构均位于所述第三导电层。
根据一些示例性实施例，所述显示基板包括位于所述衬底基板与所述第一半导体层之间的第一缓冲层，所述第一缓冲层包括氧化硅或氮化硅。
根据一些示例性实施例，所述显示基板包括位于所述第一半导体层与所述第一导电层之间的第一栅绝缘层，所述第一栅绝缘层包括氧化硅。
根据一些示例性实施例，所述显示基板包括位于所述第一导电层与所述第二导电层之间的第二栅绝缘层，所述第二栅绝缘层包括氮化硅。
根据一些示例性实施例，所述第一电容结构与所述第二电容结构之间设置有仅一层绝缘层，所述仅一层绝缘层包括所述第二栅绝缘层的一部分。
根据一些示例性实施例，所述显示基板包括位于所述第二导电层与所述第二半导体层之间的第三栅绝缘层，所述第三栅绝缘层包括氧化硅。
根据一些示例性实施例，所述显示基板包括位于所述第二半导体层与所述第三导电层之间的第四栅绝缘层，所述第四栅绝缘层包括氧化硅。
根据一些示例性实施例，所述第二电容结构与所述第三电容结构之间设置有仅一层绝缘层，所述仅一层绝缘层包括所述第四栅绝缘层的一部分。
根据一些示例性实施例，所述第二电容结构与所述第三电容结构之间设置有两层绝缘层，所述两层绝缘层包括所述第三栅绝缘层的一部分和所述第四栅绝缘层的一部分。
根据一些示例性实施例，所述显示基板还包括设置在所述第二栅绝缘层与所述第二导电层之间的第二缓冲层；以及所述第一电容结构与所述第二电容结构之间设置有两层绝缘层，所述两层绝缘层包括所述第二栅绝缘层的一部分和所述第二缓冲层的一部分。
根据一些示例性实施例，所述第三电容结构位于所述第二半导体层，所述第三电容结构包括经导体化的氧化物半导体材料形成的结构。
根据一些示例性实施例，所述显示基板包括位于所述第二导电层与所述第二半导体层之间的第三栅绝缘层，所述第三栅绝缘层包括氧化硅；以及所述第二电容结构与所述第三电容结构之间设置有仅一层绝缘层，所述仅一层绝缘层包括所述第三栅绝缘层的一部分。
根据一些示例性实施例，所述显示基板包括第四导电层，所述第四导电层位于所述第三导电层远离所述衬底基板的一侧；以及所述多个薄膜晶体管中的每一个都包括源极和漏极，每一个薄膜晶体管的源极和漏极均位于所述第四导电层。
根据一些示例性实施例，所述显示基板包括第五导电层，所述第五导电层位于所述第四导电层远离所述衬底基板的一侧；以及所述第五导电层包括遮光层，所述遮光层在所述衬底基板上的正投影至少覆盖所述第一晶体管和所述第二晶体管中的每一个的有源层在所述衬底基板上的正投影。
根据一些示例性实施例，所述第四导电层包括第一导电子层和第二导电子层，所述第一导电子层设置在所述层间绝缘层上，所述第二导电子层设置在所述第一导电子层远离所述衬底基板的一侧，并且所述第一导电子层和所述第二导电子层彼此接触。
在另一方面，提供一种显示面板，包括如上所述的显示基板。
在又一方面，提供一种显示装置，包括如上所述的显示基板或如上所述的显示面板。
在再一方面，提供一种显示基板的制造方法，其中，所述制造方法包括以下步骤：
提供衬底基板；
利用构图工艺，在所述衬底基板上制备第一半导体层，所述第一半导体层包括多晶硅半导体硅岛；
利用构图工艺，在所述第一半导体层远离所述衬底基板的一侧形成第一导电层；
利用构图工艺，在所述第一导电层远离所述衬底基板的一侧形成第二导电层；
在所述第二导电层远离所述衬底基板的一侧形成一层绝缘层；以及
利用构图工艺，在所述第二导电层远离所述衬底基板的一侧形成第二半导体层，所述第二半导体层包括氧化物半导体硅岛，
其中，所述显示基板包括设置于所述衬底基板的多个薄膜晶体管，所述多个薄膜晶体管至少包括第一晶体管、第二晶体管和第三晶体管，
所述多个薄膜晶体管中的每一个都包括有源层，所述第三晶体管的有源层位于所 述第一半导体层，所述第一晶体管和所述第二晶体管中的至少一个的有源层位于所述第二半导体层；以及
所述第一晶体管包括第一有源层、第一底栅和第一顶栅，所述第一底栅位于所述衬底基板与所述第一有源层之间，所述第一顶栅位于所述第一有源层远离所述衬底基板的一侧，所述第一有源层、所述第一底栅和所述第一顶栅中的任意两个在所述衬底基板上的正投影彼此至少部分重叠，所述第一底栅和所述第一有源层之间设置有第三栅绝缘层，所述第一有源层包括所述氧化物半导体硅岛，所述第三栅绝缘层包括氧化硅材料，所述第一顶栅远离所述衬底基板的表面与所述氧化硅材料直接接触，所述第一有源层靠近所述衬底基板的表面与所述氧化硅材料直接接触。
根据一些示例性实施例，所述制造方法还包括：
在所述第一顶栅远离所述衬底基板的一侧形成层间绝缘层；
在层间绝缘层中形成多个第一过孔，所述多个第一过孔暴露所述第一晶体管和所述第二晶体管中每一个的有源层的至少一部分；
在所述层间绝缘层远离所述衬底基板的一侧沉积第一导电材料层；
形成多个第二过孔，所述多个第二过孔暴露至少所述第三晶体管的有源层的至少一部分；
在所述第一导电材料层远离所述衬底基板的一侧沉积第二导电材料层；以及
通过一次构图工艺，图形化所述第一导电材料层和第二导电材料层，以形成所述多个薄膜晶体管的源极和漏极。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加明显。
图1是根据本公开的一些实施例的显示装置的平面示意图；
图2是根据本公开的一些实施例的显示装置包括的显示基板的平面示意图；
图3是根据本公开的一些实施例的显示基板在图2中的部分I处的局部放大图；
图4是根据本公开的一些示例性实施例的显示基板的一个像素驱动电路的等效电路图；
图5是示出根据本公开的一些示例性实施例的显示基板的一个子像素的像素驱动 电路的平面结构的示意图；
图6是示出图5所示的像素驱动电路的第一半导体层的平面结构的示意图；
图7是示出图5所示的像素驱动电路的第一导电层的平面结构的示意图；
图8是示出图5所示的像素驱动电路的第二导电层的平面结构的示意图；
图9是示出图5所示的像素驱动电路的第二半导体层的平面结构的示意图；
图10是示出图5所示的像素驱动电路的第三导电层的平面结构的示意图；
图11是示出图5所示的像素驱动电路的第四导电层的平面结构的示意图；
图12是示出图5所示的像素驱动电路的第五导电层的平面结构的示意图；
图13是示出根据本公开的一些示例性实施例的显示基板的沿图5中的线AA’和线BB’截取的截面结构的示意图，为了便于描述，将沿图5中的线AA’和线BB’截取的截面结构放在同一张示意图中示出；
图14是示出根据本公开的一些示例性实施例的显示基板的平面结构的示意图，其中示意性示出了发光器件的第一电极的平面结构；
图15是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图；
图16是示出根据本公开的另一些示例性实施例的显示基板的一个子像素的像素驱动电路的平面结构的示意图；
图17是示出图16所示的像素驱动电路的第二半导体层的平面结构的示意图；
图18是示出图16所示的像素驱动电路的第三导电层的平面结构的示意图；
图19是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图；
图20是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图；
图21是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图；
图22是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图；
图23是根据本公开的一些示例性实施例的显示基板的制造方法的流程图；以及
图24至图28分别是图23所示的制造方法中的一些步骤被执行后形成的显示基板的截面结构的示意图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部 分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在......之间”对“直接在......之间”、“相邻”对“直接相邻”或“在......上”对“直接在......上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
在本文中，术语“基本上”、“大约”、“近似”、“大致”和其它类似的术语用作近 似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±30％、±20％、±10％、±5％内。
需要说明的是，在本文中，表示“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同一层”的多个元件、部件、结构和/或部分由相同的材料构成，并且通过同一次构图工艺形成，通常，位于“同一层”的多个元件、部件、结构和/或部分具有大致相同的厚度。
本领域技术人员应该理解，在本文中，除非另有说明，表述“高度”或“厚度”指的是沿垂直于显示基板设置的各个膜层的表面的尺寸，即沿显示基板的出光方向的尺寸，或称为沿显示装置的法线方向的尺寸。
本公开的实施例至少提供一种显示基板。所述显示基板包括：衬底基板；设置于所述衬底基板的第一半导体层；和设置于所述第一半导体层远离所述衬底基板一侧的第二半导体层，其中，所述显示基板还包括设置于所述衬底基板的多个薄膜晶体管，所述多个薄膜晶体管至少包括第一晶体管、第二晶体管和第三晶体管，其中，所述多个薄膜晶体管中的每一个都包括有源层，所述第一晶体管和所述第二晶体管中的至少一个的有源层包括氧化物半导体材料，所述第三晶体管的有源层包括多晶硅半导体材料，所述第三晶体管的有源层位于所述第一半导体层，所述第一晶体管和所述第二晶体管中的至少一个的有源层位于所述第二半导体层；以及所述第一晶体管和所述第二晶体管中的至少一个具有双栅结构。在本公开的实施例中，第一晶体管和第二晶体管中的至少一个的有源层采用诸如LTPO的氧化物半导体材料形成，并且采用双栅结构，从而能够改善显示面板的显示性能。
图1是根据本公开的一些实施例的显示装置的平面示意图。例如，所述显示装置可以是OLED显示装置。参照图1，显示装置1000可以包括显示面板110、栅极驱动器120、数据驱动器130、控制器140和电压发生器150。例如，该显示装置1000可 以是OLED显示装置。显示面板110可以包括阵列基板100和多个像素PX，阵列基板100可以包括显示区AA和非显示区NA，多个像素PX以阵列形式排布在显示区AA中。栅极驱动器120产生的信号可以通过例如扫描信号线GL的信号线施加给像素PX，数据驱动器130产生的信号可以通过例如数据线DL的信号线施加给像素PX。例如VDD的第一电压和例如VSS的第二电压可以被施加至像素PX。例如VDD的第一电压可以高于例如VSS的第二电压。可选地，例如VDD的第一电压可以施加至发光器件(例如OLED)的阳极，并且例如VSS的第二电压可以施加至发光器件的阴极，使得发光器件可以发光。
例如，每一个像素PX可以包括多个子像素，例如，红色子像素、绿色子像素和蓝色子像素，或者可以包括白色子像素、红色子像素、绿色子像素和蓝色子像素。
图2是根据本公开的一些实施例的显示装置包括的显示基板的平面示意图。例如，所述显示基板可以是用于OLED显示面板的阵列基板。
参照图2，所述显示基板可以包括显示区域AA和非显示区域NA。例如，所述显示区域AA与所述非显示区域NA可以包括多个边界，如图2中所示的AAS1、AAS2、AAS3和AAS4。所述显示基板还可以包括位于所述非显示区域NA内的驱动器。例如，该驱动器可以位于显示区域AA的至少一侧。在图2所示的实施例中，驱动电路分别位于显示区域AA的左侧和右侧。需要说明的是，其中的左侧和右侧可以为在显示时，人眼观看的显示基板(屏幕)的左侧和右侧。所述驱动器可以用于驱动显示基板中的各个像素进行显示。例如，所述驱动器可以包括上述栅极驱动器120和数据驱动器130。数据驱动器130用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示基板的各条数据线上。栅极驱动器120通常由移位寄存器实现，移位寄存器将时钟信号转换成开启/关断电压，分别输出到显示基板的各条扫描信号线上。
需要说明的是，虽然图2中示出驱动器位于显示区域AA的左侧和右侧，但是，本公开的实施例不局限于此，驱动电路可以位于非显示区域NA任何合适的位置。
例如，所述驱动器可以采用GOA技术，即Gate Driver on Array。在GOA技术中，将栅极驱动电路直接设置于阵列基板上，以代替外接驱动芯片。每个GOA单元作为一级移位寄存器，每级移位寄存器与一条栅线连接，通过各级移位寄存器依序轮流输出开启电压，实现像素的逐行扫描。在一些实施例中，每级移位寄存器也可以与多条 栅线连接。这样，可以适应显示基板高分辨率、窄边框的发展趋势。
参照图2，在所述显示基板上，设置有左侧GOA电路DA1、位于显示区域AA中的多个像素P、右侧GOA电路DA2。左侧GOA电路DA1和右侧GOA电路DA2分别通过信号线电连接到显示IC上，由显示IC控制GOA信号的供给，显示IC例如设置在显示基板的下侧(人眼观看的方向)。左侧GOA电路DA1和右侧GOA电路DA2还分别通过信号线(例如扫描信号线GL)电连接到各个像素，以供应驱动信号给各个像素。
图3是根据本公开的一些实施例的显示基板在图2中的部分I处的局部放大图。需要说明的是，图中示例性的示出了子像素在衬底基板上的正投影的形状为圆角矩形，但是，本公开的实施例不局限于此，例如，子像素在衬底基板上的正投影的形状可以为矩形、六边形、五边形、正方形、圆形等其他形状。而且，一个像素单元中的3个子像素的排列方式也不局限于图3中所示的方式。
结合参照图1、图2和图3，每一个像素单元PX可以包括多个子像素，例如，第一子像素SP1、第二子像素SP2和第三子像素SP3。为了方便理解，可以将第一子像素SP1、第二子像素SP2和第三子像素SP3分别描述为红色子像素、绿色子像素和蓝色子像素，但是，本公开的实施例不局限于此。
所述多个子像素沿行方向X和列方向Y成阵列地设置于衬底基板1上。需要说明的是，虽然在图示的实施例中，行方向X和列方向Y相互垂直，但是，本公开的实施例不局限于此。
应该理解，在本公开的实施例中，每一个子像素包括像素驱动电路和发光器件。例如，所述发光器件可以为OLED发光器件，包括层叠设置的阳极、有机发光层和阴极。所述像素驱动电路可以包括多个薄膜晶体管和至少一个存储电容器。
下面，以7T1C像素驱动电路为例，对所述像素驱动电路的结构进行详细描述，但是，本公开的实施例并不局限于7T1C像素驱动电路，在不冲突的情况下，其它已知的像素驱动电路结构都可以应用于本公开的实施例中。
图4是根据本公开的一些示例性实施例的显示基板的一个像素驱动电路的等效电路图。如图4所示，所述像素驱动电路可以包括：多个薄膜晶体管以及一个存储电容器Cst。所述像素驱动电路用于驱动有机发光二极管(即OLED)。多个薄膜晶体管包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、 第六晶体管T6和第七晶体管T7。每一个晶体管均包括栅极、源极和漏极。
所述显示基板还可以包括多根信号线，例如，所述多根信号线包括：用于传输扫描信号Sn的扫描信号线61，用于传输复位控制信号RESET(即前一行的扫描信号)的复位信号线62，用于传输发光控制信号En的发光控制线63，用于传输数据信号Dm的数据线64，用于传输驱动电压VDD的驱动电压线65，用于传输初始化电压Vint的初始化电压线66，以及用于传输VSS电压的电源线67。
第一晶体管T1的栅极G1电连接至复位信号线62，第一晶体管T1的源极S1电连接至初始化电压线66。并且第一晶体管T1的漏极D1与存储电容器Cst的一端Cst1、第二晶体管T2的漏极D2以及第三晶体管T3的栅极G3电连接，如图4所示，第一晶体管T1的漏极D1、存储电容器Cst的一端Cst1、第二晶体管T2的漏极D2以及第三晶体管T3的栅极G3电连接于节点N1处。第一晶体管T1根据通过复位信号线62传输的复位控制信号RESET导通，以将初始化电压Vint传输至第三晶体管T3的栅极G1，从而执行初始化操作来将第三晶体管T3的栅极G3的电压初始化。即，第一晶体管T1也称为初始化晶体管。
第二晶体管T2的栅极G2电连接至扫描信号线61，第二晶体管T2的源极S2电连接于节点N3，并且第二晶体管T2的漏极D2电连接于节点N1。第二晶体管T2根据通过扫描信号线61传输的扫描信号Sn导通，以将第三晶体管T3的栅极G3和漏极D3彼此电连接，从而执行第三晶体管T3的二极管连接。
第三晶体管T3的栅极G3电连接至节点N1，第三晶体管T3的源极S3电连接至节点N2，第三晶体管T3的漏极D3电连接至节点N3。第三晶体管T3根据第四晶体管T4的开关操作接收数据信号Dm，以向OLED供应驱动电流Id。即，第三晶体管T3也称为驱动晶体管。
第四晶体管T4的栅极G4电连接至扫描信号线61，第四晶体管T4的源极S4电连接至数据线64，第四晶体管T4的漏极D4电连接至节点N2，即电连接至第三晶体管T3的源极S3。第四晶体管T4根据通过扫描信号线61传输的扫描信号Sn导通，以执行开关操作来将数据信号Dm传输至第三晶体管T3的源极S3。
第五晶体管T5的栅极G5电连接至发光控制线63，第五晶体管T5的源极S5电连接至驱动电压线65。并且第五晶体管T5的漏极D5电连接至节点N2。
第六晶体管T6的栅极G6电连接至发光控制线63，第六晶体管T6的源极S6电 连接至节点N3，并且第六晶体管T6的漏极D6电连接至节点N4，即电连接至OLED的阳极。第五晶体管T5和第六晶体管T6根据通过发光控制线63传输的发光控制信号En并发(例如同时)导通，以将驱动电压VDD传输至OLED，从而允许驱动电流Id流进OLED中。
第七晶体管T7的栅极G7电连接至复位信号线62，第七晶体管T7的源极S7电连接至节点N4，并且第七晶体管T7的漏极D7电连接至初始化电压线66。
存储电容器Cst的一端(下文称为第一电容电极)Cst1电连接至节点N1，另一端(下文称为第二电容电极)Cst2电连接至驱动电压线65。
OLED的阳极电连接至节点N4，阴极电连接至电源线67，以接收公共电压VSS。相应地，OLED从第三晶体管T3接收驱动电流Id来发光，从而显示图像。
需要说明的是，在图4中，各个薄膜晶体管T1、T2、T3、T4、T5、T6和T7是p沟道场效应晶体管，但是，本公开的实施例不局限于此，薄膜晶体管T1、T2、T3、T4、T5、T6和T7中的至少一些可以是n沟道场效应晶体管。
在操作中，在初始化阶段，具有低电平的复位控制信号RESET通过复位信号线62供应。随后，第一晶体管T1基于复位控制信号RESET的低电平导通，并且来自初始化电压线66的初始化电压Vint通过第一晶体管T1传送至第三晶体管T3的栅极G1。因此，第三晶体管T3由于初始化电压Vint而被初始化。
在数据编程阶段，具有低电平的扫描信号Sn通过扫描信号线61供应。随后，第四晶体管T4和第二晶体管T2基于扫描信号Sn的低电平导通。因此，第三晶体管T3通过导通的第二晶体管T2被置于二极管连接状态并且在正方向上偏置。
随后，通过从经由数据线64供应的数据信号Dm中减去第三晶体管T3的阈值电压Vth获得的补偿电压Dm+Vth(例如，Vth是负值)施加至第三晶体管T3的栅极G3。随后，驱动电压VDD和补偿电压Dm+Vth施加至存储电容器Cst的两个端子，使得与相应端子之间的电压差对应的电荷存储在存储电容器Cst中。
在发光阶段，来自发光控制线63的发光控制信号En从高电平变为低电平。随后，在发光阶段，第五晶体管T5和第六晶体管T6基于发光控制信号En的低电平导通。
随后，基于第三晶体管T3的栅极G3的电压与驱动电压VDD之间的差生成驱动电流。与驱动电流和旁路电流之间的差对应的驱动电流Id通过第六晶体管T6供应给OLED。
在发光阶段，基于第三晶体管T3的电流-电压关系，第三晶体管T3的栅源电压由于存储电容器Cst而保持在(Dm+Vth)-VDD处。驱动电流Id与(Dm-VDD) 2成比例。因此，驱动电流Id可以不受第三晶体管T3的阈值电压Vth变动的影响。
图5是示出根据本公开的一些示例性实施例的显示基板的一个子像素的像素驱动电路的平面结构的示意图。图6是示出图5所示的像素驱动电路的第一半导体层的平面结构的示意图。图7是示出图5所示的像素驱动电路的第一导电层的平面结构的示意图。图8是示出图5所示的像素驱动电路的第二导电层的平面结构的示意图。图9是示出图5所示的像素驱动电路的第二半导体层的平面结构的示意图。图10是示出图5所示的像素驱动电路的第三导电层的平面结构的示意图。图11是示出图5所示的像素驱动电路的第四导电层的平面结构的示意图。图12是示出图5所示的像素驱动电路的第五导电层的平面结构的示意图。图13是示出根据本公开的一些示例性实施例的显示基板的沿图5中的线AA’和线BB’截取的截面结构的示意图，为了便于描述，将沿图5中的线AA’和线BB’截取的截面结构放在同一张示意图中示出。
结合参照图5至图13，所述显示基板包括衬底基板10以及设置于所述衬底基板10上的多个膜层。在一些实施例中，所示多个膜层至少包括第一半导体层20、第一导电层30、第二导电层40、第二半导体层50、第三导电层60、第四导电层70和第五导电层90。第一半导体层20、第一导电层30、第二导电层40、第二半导体层50、第三导电层60、第四导电层70和第五导电层90依次远离衬底基板10设置。
例如，第一半导体层20可以由诸如低温多晶硅的半导体材料形成，其膜层厚度可以在400～800埃的范围内，例如500埃。第二半导体层50可以由氧化物半导体材料形成，例如IGZO等多晶硅氧化物半导体材料，其膜层厚度可以在300～600埃的范围内，例如400埃。第一导电层30可以由形成薄膜晶体管的栅极的导电材料形成，例如该导电材料可以为Mo，其膜层厚度可以在2000～3000埃的范围内，例如2500埃。第二导电层40可以由形成薄膜晶体管的源极和漏极的导电材料形成，例如该导电材料可以包括Ti、Al等，第二导电层40可以具有由Ti/Al/Ti形成的叠层结构，其膜层厚度可以在7000～9000埃的范围内。例如，在第二导电层40具有由Ti/Al/Ti形成的叠层结构的情况下，Ti/Al/Ti每一层的厚度可以分别为约500埃、5500埃和500埃。第三导电层60可以由形成薄膜晶体管的栅极的导电材料形成，例如该导电材料可以为Mo，其膜层厚度可以在2000～3000埃的范围内，例如2500埃。第四导电层70可以由形成薄膜晶体 管的源极和漏极的导电材料形成，例如该导电材料可以包括Ti、Al等，第四导电层70可以具有由Ti/Al/Ti形成的叠层结构，其膜层厚度可以在7000～9000埃的范围内。例如，在第四导电层70具有由Ti/Al/Ti形成的叠层结构的情况下，Ti/Al/Ti每一层的厚度可以分别为约500埃、5500埃和300埃。第五导电层90可以由形成薄膜晶体管的源极和漏极的导电材料形成，例如该导电材料可以包括Ti、Al等，第四导电层70可以具有由Ti/Al/Ti形成的叠层结构。
所述显示基板包括沿着行方向布置以向子像素分别施加扫描信号Sn、复位控制信号RESET、发光控制信号En和初始化电压Vint的扫描信号线61、复位信号线62、发光控制线63和初始化电压线66。所述显示基板还可以包括与扫描信号线61、复位信号线62、发光控制线63和初始化电压线66交叉以向子像素分别施加数据信号Dm和驱动电压VDD的数据线64以及驱动电压线65。
结合上文针对图4的描述，所述显示基板的像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7、以及存储电容器Cst。
第一晶体管T1和第二晶体管T2可沿着如图9中所示的第二半导体层形成。第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7可沿着如图6中所示的第一半导体层20形成。
如图6所示，第一半导体层20可具有弯曲或弯折形状，并且可包括对应于第三晶体管T3的第三有源层20c、对应于第四晶体管T4的第四有源层20d、对应于第五晶体管T5的第五有源层20e、对应于第六晶体管T6的第六有源层20f和对应于第七晶体管T7的第七有源层20g。
例如，第一半导体层20可以包括多晶硅，诸如低温多晶硅材料。每一个晶体管的有源层可以包括沟道区、源极区和漏极区。沟道区可不进行掺杂或掺杂类型与源极区、漏极区不同，并因此具有半导体特性。源极区和漏极区分别位于沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可根据TFT是N型还是P型晶体管而变化。
第三晶体管T3包括第三有源层20c和第三栅极G3。第三有源层20c包括第三源极区203c、第三漏极区205c以及连接第三源极区203c和第三漏极区205c的第三沟道区201c。第三源极区203c和第三漏极区205c相对于第三沟道区201c在相对的两个方向上延伸。
第四晶体管T4包括第四有源层20d和第四栅极G4。第四有源层20d包括第四源极区203d、第四漏极区205d以及连接第四源极区203d和第四漏极区205d的第四沟道区201d。第四源极区203d和第四漏极区205d相对于第四沟道区201d在相对的两个方向上延伸。
第五晶体管T5包括第五有源层20e和第五栅极G5。第五有源层20e包括第五源极区203e、第五漏极区205e以及连接第五源极区203e和第五漏极区205e的第五沟道区201e。第五源极区203e和第五漏极区205e相对于第五沟道区201e在相对的两个方向上延伸。
第六晶体管T6包括第六有源层20f和第六栅极G6。第六有源层20f包括第六源极区203f、第六漏极区205f以及连接第六源极区203f和第六漏极区205f的第六沟道区201f。第六源极区203f和第六漏极区205f相对于第六沟道区201f在相对的两个方向上延伸。
第七晶体管T7包括第七有源层20g和第七栅极G7。第七有源层20g包括第七源极区203g、第七漏极区205g以及连接第七源极区203g和第七漏极区205g的第七沟道区201g。第七源极区203g和第七漏极区205g相对于第七沟道区201g在相对的两个方向上延伸。
如图7所示，扫描信号线61、复位信号线62和发光控制线63均位于第一导电层30中。栅极结构CG1也位于第一导电层30中。栅极结构CG1与第一半导体层20重叠的部分形成第三晶体管T3的第三栅极G3。扫描信号线61与第一半导体层20重叠的部分形成第四晶体管T4的第四栅极G4。发光控制线63与第一半导体层20重叠的一部分形成第五晶体管T5的第五栅极G5。发光控制线63与第一半导体层20重叠的另一部分形成第六晶体管T6的第六栅极G6。复位信号线62与第一半导体层20重叠的部分形成第七晶体管T7的第七栅极G7。栅极结构CG1也形成第一电容结构，例如存储电容器Cst的一个电容电极(例如第一电容电极Cst1)的一部分。即，栅极结构CG1同时用作第三晶体管T3的栅极和存储电容器Cst的一个电极。
如图8所示，第二导电层40包括第一底栅结构BG1、第二底栅结构BG2和第二电容结构CP2。初始化电压线66也位于第二导电层40中。
继续参照图8，第二导电层40包括通孔40H，通孔40H形成于第二电容结构CP2中。
如图9所示，第二半导体层50包括对应于第一晶体管T1的第一有源层20a和对应于第二晶体管T2的第二有源层20b。例如，第一晶体管T1的第一有源层20a和第二晶体管T2的第二有源层20b与所述数据线的延伸方向相同，即，都沿图中的上下方向延伸。
例如，第二半导体层50可以包括氧化物半导体材料，诸如低温多晶硅氧化物半导体材料(缩写为LTPO)。每一个晶体管的有源层可以包括沟道区、源极区和漏极区。沟道区可不进行掺杂或掺杂类型与源极区、漏极区不同，并因此具有半导体特性。源极区和漏极区分别位于沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可根据TFT是N型还是P型晶体管而变化。
第一晶体管T1的第一有源层20a包括第一源极区203a、第一漏极区205a以及连接第一源极区203a和第一漏极区205a的第一沟道区201a。第一源极区203a和第一漏极区205a相对于第一沟道区201a在相对的两个方向上延伸。
第二晶体管T2的第二有源层20b包括第二源极区203b、第二漏极区205b以及连接第二源极区203b和第二漏极区205b的第二沟道区201b。第二源极区203b和第二漏极区205b相对于第二沟道区201b在相对的两个方向上延伸。
结合参照图5、图8和图9，第一有源层20a在衬底基板10上的正投影与第一底栅结构BG1在衬底基板10上的正投影至少部分重叠，第一底栅结构BG1与第一有源层20a重叠的部分构成第一晶体管T1的第一底栅G11。
第二有源层20b在衬底基板10上的正投影与第二底栅结构BG2在衬底基板10上的正投影至少部分重叠，第二底栅结构BG2与第二有源层20b重叠的部分构成第二晶体管T2的第二底栅G21。
例如，继续参照图8和图9，所述第一底栅结构BG1包括第一底栅主体部BG11和第一底栅延伸部BG12。所述第一底栅主体部BG11在所述衬底基板10上的正投影呈矩形形状。所述第一底栅主体部BG11在所述衬底基板10上的正投影与所述第一晶体管T1的有源层在所述衬底基板10上的正投影至少部分重叠，所述第一底栅G11包括所述第一底栅主体部BG11与所述第一晶体管T1的有源层重叠的部分。
所述第二底栅结构BG2包括第二底栅主体部BG21和第二底栅延伸部BG22。所述第二底栅主体部BG21在所述衬底基板10上的正投影呈矩形形状。所述第二底栅主体部BG21在所述衬底基板10上的正投影与所述第二晶体管T2的有源层在所述衬底 基板10上的正投影至少部分重叠，所述第二底栅G21包括所述第二底栅主体部BG21与所述第二晶体管T2的有源层重叠的部分。
在图中所述的实施例中，所述第一底栅延伸部BG12和所述第二底栅延伸部BG22均沿行方向延伸，即沿图中的左右方向延伸。即，所述第一底栅延伸部BG12和所述第二底栅延伸部BG22的延伸方向大致平行于初始化电压线66的延伸方向。
参照图9，第二半导体层50还包括第三电容结构CP3。第三电容结构CP3包括导体化的第二半导体层50的一部分。例如，在形成诸如IGZO的第二半导体层50后，可以利用成膜气体中的SiH 4对其进行H掺杂，降低其电阻率，从而形成导体化的第二半导体层50的一部分，以形成所述第三电容结构CP3。
结合参照图5、图7、图8和图9以及图13，第一电容结构CG1、第二电容结构CP2和第三电容结构CP3彼此间隔且相对设置，第一电容结构CG1、第二电容结构CP2和第三电容结构CP3在衬底基板10上的正投影彼此至少部分重叠。第一电容结构CG1通过形成在通孔40H中的导电插塞与第三电容结构CP3电连接，这样，彼此电连接的第一电容结构CG1和第三电容结构CP3形成所述存储电容器的第一电容电极Cst1。第二电容结构CP2位于第一电容结构CG1和第三电容结构CP3之间，形成所述存储电容器的第二电容电极Cst2。结合参照图4，第一电容电极Cst1可以电连接至节点N1，第二电容电极Cst2可以电连接至VDD，这样，可以在第一电容电极Cst1与第二电容电极Cst2之间形成存储电容。通过这样的方式，可以分别在第一电容结构CG1与第二电容结构CP2之间以及在第二电容结构CP2与第三电容结构CP3之间形成电容，两个电容的电容值之和等于所述存储电容器的电容值。也就是说，通过这样的方式，有利于提高存储电容器的电容值，从而提高像素驱动电路的性能。
如图10所示，第三导电层60包括第一顶栅结构TG1和第二顶栅结构TG2。
第一有源层20a和第一底栅结构BG1中的每一个在衬底基板10上的正投影与第一顶栅结构TG1在衬底基板10上的正投影均至少部分重叠。第一顶栅结构TG1与第一有源层20a重叠的部分构成第一晶体管T1的第一顶栅G12。结合参照图13，在垂直于衬底基板10的上表面的方向上(即沿图12所示的竖直方向)，第一有源层20a位于第一底栅G11与第一顶栅G12之间。这样，第一晶体管T1具有双栅结构。
继续参照图10，所述第一顶栅结构TG1沿图10中的水平方向延伸。所述第一顶栅结构TG1可以包括第一加宽部TG11，所述第一加宽部TG11沿竖直方向的尺寸大 于所述第一顶栅结构TG1的其余部分沿所述竖直方向的尺寸。所述第一加宽部TG11在所述衬底基板10上的正投影与所述第一晶体管T1的有源层20a在所述衬底基板10上的正投影至少部分重叠，所述第一顶栅G12包括所述第一加宽部TG11与所述第一晶体管T1的有源层20a重叠的部分。
第二有源层20b和第二底栅结构BG2中的每一个在衬底基板10上的正投影与第二顶栅结构TG2在衬底基板10上的正投影均至少部分重叠。第二顶栅结构TG2与第二有源层20b重叠的部分构成第二晶体管的第二顶栅G22。结合参照图12，在垂直于衬底基板10的上表面的方向上(即沿图12所示的竖直方向)，第二有源层20b位于第二底栅G21与第二顶栅G22之间。这样，第二晶体管T2具有双栅结构。
继续参照图10，所述第二顶栅结构TG2沿图10中的水平方向延伸。所述第二顶栅结构TG2可以包括第二加宽部TG21，所述第二加宽部TG21沿竖直方向的尺寸大于所述第二顶栅结构TG2的其余部分沿所述竖直方向的尺寸。所述第二加宽部TG21在所述衬底基板10上的正投影与所述第二晶体管T2的有源层20b在所述衬底基板10上的正投影至少部分重叠，所述第二顶栅G22包括所述第二加宽部TG21与所述第二晶体管T2的有源层20b重叠的部分。
如图11所示，第四导电层70包括驱动电压线65、第一导电部件701、第二导电部件702、第三导电部件703、第四导电部件704和第五导电部件705。
驱动电压线65通过过孔VAH12与第五晶体管T5的源极区203e电连接。驱动电压线65与第五晶体管T5的源极区203e重叠的部分构成第五晶体管T5的源极。
第一导电部件701的一端通过过孔VAH2与第一晶体管T1的源极区203a电连接。第一导电部件701的一部分还通过过孔VAH3与初始化电压线66电连接。第一导电部件701的另一端通过过孔VAH4与第一导电构件401电连接。通过这样的方式，第一晶体管T1的源极与第七晶体管T7的漏极电连接，并且二者均电连接至初始化电压线66。这样，初始化电压Vint可以施加给第一晶体管T1的源极与第七晶体管T7的漏极。
第二导电部件702的一端通过过孔VAH7与第二晶体管T2的漏极区205b电连接，第二导电部件702的另一端通过过孔VAH6与第一晶体管T1的漏极区203a以及第三导电部件703电连接。第三导电部件703的一端通过过孔VAH6与第二导电部件702电连接，第三导电部件703的另一端通过过孔VAH8与第三晶体管T3的栅极G1和第一电容电极Cst1电连接，即形成图4中的节点N1。这样，可以实现第一晶体管T1的 漏极、第二晶体管T2的漏极、第三晶体管T3的栅极以及第一电容电极Cst1相互之间的电连接，参照图4，均电连接于节点N1。
第四导电部件704的一端通过过孔VAH9与第二晶体管T2的源极区203b电连接，第四导电部件704的另一端通过过孔VAH10与第六晶体管T6的源极区203b电连接。这样，可以实现第二晶体管T2的源极与第六晶体管T6的源极之间的电连接，参照图4，均电连接于节点N3。
第五导电构件705的一端通过过孔VAH13与第六晶体管T6的漏极区205f和第七晶体管T7的源极区203g电连接，另一端通过过孔VAH14与发光器件的第一电极(例如阳极，将在下文描述)电连接。这样，可以实现第六晶体管T6的漏极、第七晶体管T7的源极和发光器件的第一电极之间的电连接，参照图4，均电连接于节点N4。
如图12所示，第五导电层90包括数据线64和遮光层902。
数据线64通过过孔VAH1与第四晶体管T4的源极区203d电连接，以将数据信号Dm施加给第四晶体管T4的源极。即，数据线64与第四晶体管T4的源极区203d重叠的部分构成第四晶体管T4的源极。
遮光层902在衬底基板10上的正投影覆盖所述第一晶体管T1和所述第二晶体管T2中每一个在衬底基板10上的正投影。例如，遮光层902在衬底基板10上的正投影覆盖所述第一晶体管T1的有源层20a和所述第二晶体管T2的有源层20b中每一个在衬底基板10上的正投影。通过设计遮光层902，可以保护所述第一晶体管T1的有源层20a和所述第二晶体管T2的有源层20b免受外界光照的影响，有利于保持第一晶体管和第二晶体管的性能稳定。
例如，遮光层902可以电连接至一固定电压，以避免其电位悬空，从而可以避免遮光层对晶体管的性能产生不良的影响。例如，遮光层902可以通过过孔VAH15电连接至第二电容电极Cst2，即电连接至VDD电压。
在本公开的实施例中，第一晶体管T1和第二晶体管T2的有源层均采用诸如LTPO的氧化物半导体材料形成，能够提高像素驱动电路中的节点N1(如图4所示)处的电压稳定性，从而改善显示面板的显示性能。并且，第一晶体管T1和第二晶体管T2均具有双栅结构，使得第一晶体管T1和第二晶体管T2的稳定性和阈值电压(Vth)的均一性都得到提升，从而能够进一步提升显示面板的性能。
还需要说明的是，在本公开的实施例中，晶体管T1、T2的底栅G11、G21既起到 底栅的作用，还起到遮光层的作用，可以避免外界光对晶体管T1、T2的有源层20a、20b的干扰，有利于进一步改善晶体管的性能。
图14是示出根据本公开的一些示例性实施例的显示基板的平面结构的示意图，其中示意性示出了发光器件的第一电极的平面结构。图15是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图。
例如，所述发光器件可以是有机发光二极管，它可以包括设置于衬底基板10上的第一电极、有机发光层和第二电极，其中，第一电极可以是阳极和阴极中的一个，第二电极可以是阳极和阴极中的另一个。第一电极、有机发光层和第二电极可以依次远离衬底基板10设置。
如图14所示，第一电极80可以包括电极主体部801和电极连接部802。在图13所示的实施例中，电极主体部801可以具有大致矩形形状，即，电极主体部801在衬底基板10上的正投影呈大致矩形。但是，本公开的实施例不限于此，电极主体部801可以具有任何合适的形状，例如，六边形、八边形等。
电极主体部801和电极连接部802可以连接成一体。电极连接部802通过过孔VAH14与第五导电部件705的一端电连接。如上所述，第五导电部件705的另一端通过过孔VAH13与第六晶体管T6的漏极和第七晶体管T7的源极电连接。这样，第一电极80与第六晶体管T6的漏极和第七晶体管T7的源极电连接。
例如，所述第一电极80在所述衬底基板10上的正投影至少覆盖所述第一晶体管T1的有源层20a在所述衬底基板10上的正投影。所述第一电极80在所述衬底基板10上的正投影与所述第二晶体管T2的有源层20b在所述衬底基板10上的正投影间隔设置。
下面，将结合图13和图15描述根据本公开实施例的显示基板的其他膜层(例如绝缘层)。
在示例性的实施例中，所述显示基板可以包括设置在衬底基板10上的阻挡层161；以及设置在阻挡层161远离衬底基板10一侧的第一缓冲层162。
例如，阻挡层161可以由氧化硅形成，具有约5500埃的厚度。第一缓冲层162可以由氮化硅形成，具有约1000埃的厚度；或者，第一缓冲层162可以由氮化硅和氧化硅的叠层构成。例如，第一缓冲层162可以包括设置在阻挡层161上的第一缓冲子层和设置在第一缓冲子层远离衬底基板10一侧的第二缓冲子层，第一缓冲子层包括氮化 硅材料，第二缓冲子层包括氧化硅材料。
所述显示基板可以包括设置在第一半导体层20与第一导电层30之间的第一栅绝缘层GI1。例如，第一栅绝缘层GI1可以由氧化硅形成。
所述显示基板可以包括设置在第一导电层30与第二导电层40之间的第二栅绝缘层GI2。例如，第二栅绝缘层GI2可以由氮化硅形成。这样，由氮化硅形成的第二栅绝缘层GI2可以给第一晶体管补氢(H)，以改善第一晶体管的性能。
所述显示基板可以包括设置在第二栅绝缘层GI2与第二导电层40之间的第二缓冲层163。例如，第二缓冲层163可以由氮化硅或氧化硅形成。
所述显示基板可以包括设置在第二导电层40与第二半导体层50之间的第三栅绝缘层GI3。例如，第三栅绝缘层GI3可以由氧化硅形成。这样，由氧化硅形成的第三栅绝缘层GI3可以阻隔氢(H)向氧化物半导体晶体管(即T1、T2)渗透，以改善氧化物半导体晶体管(即T1、T2)的性能。
所述显示基板可以包括设置在第二半导体层50与第三导电层60之间的第四栅绝缘层GI4。例如，第四栅绝缘层GI4可以由氧化硅形成。这样，由氧化硅形成的第四栅绝缘层GI4可以阻隔氢(H)向氧化物半导体晶体管(即T1、T2)渗透，以改善氧化物半导体晶体管(即T1、T2)的性能。
在本公开的实施例中，所述第一有源层20a靠近所述衬底基板10的表面(例如图13中第一有源层20a的下表面)与所述第一底栅G11远离所述衬底基板10的表面(例如图13中第一底栅G11的上表面)之间的距离，大于所述第一有源层20a远离所述衬底基板的表面(例如图13中第一有源层20a的上表面)与所述第一顶栅G12靠近所述衬底基板10的表面(例如图13中第一顶栅G12的下表面)之间的距离。
例如，所述第一有源层20a靠近所述衬底基板10的表面(例如图13中第一有源层20a的下表面)与所述第一底栅G11远离所述衬底基板10的表面(例如图13中第一底栅G11的上表面)之间的距离可以在3000～6000埃的范围内，诸如3500埃、4000埃或4500埃。所述第一有源层20a远离所述衬底基板的表面(例如图13中第一有源层20a的上表面)与所述第一顶栅G12靠近所述衬底基板10的表面(例如图13中第一顶栅G12的下表面)之间的距离可以在1000～2000埃的范围内，诸如1300埃、1500埃。
在本公开的实施例中，所述第一有源层20a靠近所述衬底基板10的表面(例如图 13中第一有源层20a的下表面)与所述第一底栅G11远离所述衬底基板10的表面(例如图13中第一底栅G11的上表面)之间的距离，大于所述第三有源层20c远离所述衬底基板10的表面与所述第三栅极G3靠近所述衬底基板10的表面之间的距离。
例如，所述第三有源层20c远离所述衬底基板10的表面与所述第三栅极G3靠近所述衬底基板10的表面之间的距离可以在1000～2000埃的范围内，诸如1300埃、1500埃。
在本公开的实施例中，所述第一有源层20a远离所述衬底基板的表面(例如图13中第一有源层20a的上表面)与所述第一顶栅G12靠近所述衬底基板10的表面(例如图13中第一顶栅G12的下表面)之间的距离，与所述第三有源层20c远离所述衬底基板10的表面与所述第三栅极G3靠近所述衬底基板10的表面之间的距离大致相等。
所述显示基板可以包括设置在第三导电层60与第四导电层70之间以及在第二半导体层50与第四导电层70之间的层间绝缘层ILD。例如，层间绝缘层ILD可以由单层氧化硅形成，或者，可以由氧化硅和氮化硅形成的叠层结构形成。例如，层间绝缘层ILD可以包括由氧化硅形成的第一层间绝缘子层和由氮化硅形成的第二层间绝缘子层，第一层间绝缘子层比第二层间绝缘子层更靠近衬底基板10。
在本公开的实施例中，在具有双栅结构的晶体管中，例如，在第一晶体管T1中，底栅G11与有源层20a之间仅设置有一层第三栅绝缘层GI3，而没有设置其他的绝缘层。这样，减小了底栅G11与有源层20a之间的距离，有利于第一晶体管中形成良好的双栅驱动，有利于提供晶体管的驱动能力，从而提高晶体管的载流子迁移率和电学信赖性。应该理解，第二晶体管T2也具有相同的结构和效果。
图16是示出根据本公开的另一些示例性实施例的显示基板的一个子像素的像素驱动电路的平面结构的示意图。图17是示出图16所示的像素驱动电路的第二半导体层的平面结构的示意图。图18是示出图16所示的像素驱动电路的第三导电层的平面结构的示意图。
需要说明的是，下面将主要描述图16所示的实施例中的显示基板不同于上述各个实施例中的显示基板的不同之处，其他结构可以参照上述各个实施例中的显示基板的结构。
同样地，如图16所示，所述显示基板包括衬底基板10以及设置于所述衬底基板 10上的多个膜层。在一些实施例中，所示多个膜层至少包括第一半导体层20、第一导电层30、第二导电层40、第二半导体层50、第三导电层60、第四导电层70和第五导电层90。第一半导体层20、第一导电层30、第二导电层40、第二半导体层50、第三导电层60、第四导电层70和第五导电层90依次远离衬底基板10设置。第一半导体层20、第一导电层30、第二导电层40、第四导电层70和第五导电层90可以参照上文的描述。
如图17所示，第二半导体层50’包括对应于第一晶体管T1的第一有源层20a和对应于第二晶体管T2的第二有源层20b。例如，第一晶体管T1的第一有源层20a和第二晶体管T2的第二有源层20b与所述数据线的延伸方向相同，即，都沿图中的上下方向延伸。
第三导电层60’包括第一顶栅结构TG1和第二顶栅结构TG2。
第一有源层20a、第二有源层20b、第一顶栅结构TG1和第二顶栅结构TG2可以参照上文的描述，在此不再赘述。
在该实施例中，第三电容结构CP3形成于第三导电层60’中，而不形成于第二半导体层50’中。如图18所示，第三导电层60’包括第三电容结构CP3。
图19是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图。结合参照图16至图19，第一电容结构CG1、第二电容结构CP2和第三电容结构CP3彼此间隔且相对设置，第一电容结构CG1、第二电容结构CP2和第三电容结构CP3在衬底基板10上的正投影彼此至少部分重叠。第一电容结构CG1通过形成在通孔40H中的导电插塞与第三电容结构CP3电连接，这样，彼此电连接的第一电容结构CG1和第三电容结构CP3形成所述存储电容器的第一电容电极Cst1。第二电容结构CP2位于第一电容结构CG1和第三电容结构CP3之间，形成所述存储电容器的第二电容电极Cst2。结合参照图4，第一电容电极Cst1可以电连接至节点N1，第二电容电极Cst2可以电连接至VDD，这样，可以在第一电容电极Cst1与第二电容电极Cst2之间形成存储电容。通过这样的方式，可以分别在第一电容结构CG1与第二电容结构CP2之间以及在第二电容结构CP2与第三电容结构CP3之间形成电容，两个电容的电容值之和等于所述存储电容器的电容值。在本公开的实施例中，在第一电容结构CG1与第二电容结构CP2之间，设置有第二栅绝缘层GI2和第二缓冲层163。在第二电容结构CP2与第三电容结构CP3之间，设置有第三栅绝缘层GI3和第四栅绝缘层GI4。以此方式，形成 具有增大的电容值的存储电容器。也就是说，通过这样的方式，有利于提高存储电容器的电容值，从而提高像素驱动电路的性能。
图20是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图。在图20所示的实施例中，上述第二缓冲层163被去除。在晶体管的底栅(例如G11或G21)与有源层(20a或20b)之间设置有第三栅绝缘层GI3，该第三栅绝缘层GI3包括氧化硅材料，可以起到阻隔氢(H)向晶体管的沟道区渗透的作用。
参照图20，在第一电容结构CG1与第二电容结构CP2之间，仅设置有第二栅绝缘层GI2。这样，第一电容结构CG1与第二电容结构CP2之间的距离被减小，所以，第一电容结构CG1与第二电容结构CP2之间形成的电容的电容值增大，从而能够增大所述存储电容器的整体电容值。
图21是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图。在图21所示的实施例中，第二电容结构CP2与第三电容结构CP3之间的第三栅绝缘层GI3被去除，即，在第二电容结构CP2与第三电容结构CP3之间仅设置有第四栅绝缘层GI4。这样，第二电容结构CP2与第三电容结构CP3之间的距离被减小，所以，第二电容结构CP2与第三电容结构CP3之间形成的电容的电容值增大，从而能够进一步增大所述存储电容器的整体电容值。
图22是示出根据本公开的一些示例性实施例的显示基板的截面结构的示意图。在图22所示的实施例中，第四导电层70可以具有叠层结构。例如，第四导电层70可以包括第一导电子层70A和第二导电子层70B。第一导电子层70A设置在层间绝缘层ILD上，第二导电子层70B设置在第一导电子层70A远离衬底基板10的一侧，并且第一导电子层70A和第二导电子层70B彼此接触。
例如，第一导电子层70A的材料可以包括Mo，也可以包括Ti、Al等。第二导电子层70B的材料可以包括由形成薄膜晶体管的源极和漏极的导电材料形成，例如该导电材料可以包括Ti、Al等。
图23是根据本公开的一些示例性实施例的显示基板的制造方法的流程图。图24至图28分别是图23所示的制造方法中的一些步骤被执行后形成的显示基板的截面结构的示意图。结合参照图22至图28，所述显示基板的制造方法可以按照以下步骤执行。
参照图24，在步骤S231中，制备衬底基板10。例如，衬底基板10可以为例如聚 酰亚胺(PI)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚碳酸酯、聚乙烯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜等形成的有机柔性衬底。衬底基板10可以为单层结构，也可以为双层结构。例如，衬底基板10可以包括第一衬底、第一阻挡层、第二衬底，第一阻挡层设置在第一衬底和第二衬底之间。所述衬底基板10的厚度大约是在5～20微米的范围内。
然后，在衬底基板10上依次制备阻挡层161、第一缓冲层162、第一半导体层20、第一栅绝缘层GI1、第一导电层30、第二栅绝缘层GI2、第二导电层40、第三栅绝缘层GI3、第二半导体层50、第四栅绝缘层GI4、第三导电层60和层间绝缘层IDL。
参照图25，在步骤S232中，在层间绝缘层IDL中形成多个过孔VA1、VA2，所述多个过孔VA1、VA2贯穿层间绝缘层IDL，以分别暴露所述氧化物半导体晶体管(即上述第一晶体管和第二晶体管)的有源层的源极区和漏极区。
参照图26，在步骤S233中，在层间绝缘层IDL远离衬底基板10的一侧沉积第一导电材料层CL1。例如，所述第一导电材料层CL1可以包括Mo。所述第一导电材料层CL1可以填充于所述多个过孔VA1、VA2中，以与第一晶体管或第二晶体管的有源层的源极区和漏极区接触。
参照图27，在步骤S234中，形成多个过孔VA3、VA4，所述多个过孔VA3、VA4中的每一个贯穿第一导电材料层CL1、层间绝缘层IDL、第三栅绝缘层GI3、第二栅绝缘层GI2和第一栅绝缘层GI1，以分别暴露多晶硅半导体晶体管(即上述第三晶体管至第七晶体管)的有源层的源极区和漏极区。
在该步骤中，通过干刻工艺形成所述多个过孔VA3、VA4，然后，需要使用刻蚀液进行清洗。在上述第一导电材料层CL1的保护作用下，所述刻蚀液不会对层间绝缘层IDL和氧化物半导体晶体管的有源层(即上述有源层20a和20b)造成破坏。
参照图28，在步骤S235中，在第一导电材料层CL1远离衬底基板10的一侧沉积第二导电材料层CL2。例如，所述第二导电材料层CL2可以包括Ti、Al等。所述第二导电材料层CL2堆叠在第一导电材料层CL1上，并且还填充于所述多个过孔VA3、VA4中，以与多晶硅半导体晶体管的有源层的源极区和漏极区接触。
参照图22，在步骤S236中，通过一次构图工艺，图形化所述第一导电材料层CL1和第二导电材料层CL2，以形成多个晶体管的源极和漏极。这样，有利于减少构图工艺的次数，从而节省了掩模板的数量。
参照图1，本公开的至少一些实施例还提供一种显示装置。该显示装置可以包括如上所述的显示基板。
所述显示装置可以包括任何具有显示功能的设备或产品。例如，所述显示装置可以是智能电话、移动电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴设备(例如头戴式设备、电子服饰、电子手环、电子项链、电子配饰、电子纹身、或智能手表)、电视机等。
应该理解，根据本公开实施例的显示面板和显示装置具有上述显示基板的所有特点和优点，具体可以参见上文的描述，在此不再赘述。
虽然本公开的总体技术构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离所述总体技术构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (22)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板；以及
    设置于所述衬底基板的第一晶体管，
    其中，所述第一晶体管包括第一有源层、第一底栅和第一顶栅，所述第一底栅位于所述衬底基板与所述第一有源层之间，所述第一顶栅位于所述第一有源层远离所述衬底基板的一侧，所述第一有源层、所述第一底栅和所述第一顶栅中的任意两个在所述衬底基板上的正投影彼此至少部分重叠，所述第一底栅和所述第一有源层之间设置有第三栅绝缘层，所述第一有源层包括氧化物半导体材料，所述第三栅绝缘层包括氧化硅材料，所述第一顶栅远离所述衬底基板的表面与所述氧化硅材料直接接触，所述第一有源层靠近所述衬底基板的表面与所述氧化硅材料直接接触。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板包括：
    设置于所述衬底基板的第一半导体层；和
    设置于所述第一半导体层远离所述衬底基板一侧的第二半导体层，
    其中，所述显示基板还包括第三晶体管，
    所述第三晶体管包括第三有源层和第三栅极，所述第三有源层包括多晶硅半导体材料，所述第三有源层位于所述第一半导体层，所述第一有源层位于所述第二半导体层。
  3. 根据权利要求2所述的显示基板，其中，所述第一有源层靠近所述衬底基板的表面与所述第一底栅远离所述衬底基板的表面之间的距离，大于所述第一有源层远离所述衬底基板的表面与所述第一顶栅靠近所述衬底基板的表面之间的距离。
  4. 根据权利要求2所述的显示基板，其中，所述第一有源层靠近所述衬底基板的表面与所述第一底栅远离所述衬底基板的表面之间的距离，大于所述第三有源层远离所述衬底基板的表面与所述第三栅极靠近所述衬底基板的表面之间的距离。
  5. 根据权利要求2所述的显示基板，其中，所述第一有源层远离所述衬底基板的 表面与所述第一顶栅靠近所述衬底基板的表面之间的距离，与所述第三有源层远离所述衬底基板的表面与所述第三栅极靠近所述衬底基板的表面之间的距离大致相等。
  6. 根据权利要求2-5任一所述的显示基板，其中，所述显示基板还包括第二晶体管，所述第二晶体管包括第二底栅和第二顶栅，所述第二底栅位于所述衬底基板与所述第二晶体管的有源层之间，所述第二顶栅位于所述第二晶体管的有源层远离所述衬底基板的一侧，所述第二晶体管的有源层、所述第二底栅和所述第二顶栅中的任意两个在所述衬底基板上的正投影彼此至少部分重叠。
  7. 根据权利要求6所述的显示基板，其中，所述显示基板包括存储电容器，所述存储电容器包括设置于所述衬底基板的第一电容结构、第二电容结构和第三电容结构，所述第三电容结构位于所述第一电容结构远离所述衬底基板的一侧，所述第二电容结构位于所述第一电容结构和所述第三电容结构之间，所述第一电容结构、所述第二电容结构和所述第三电容结构中的任意两者在所述衬底基板上的正投影至少部分重叠；以及
    所述第一电容结构和所述第三电容结构彼此电连接，以形成所述存储电容器的第一电容电极，所述第二电容结构形成所述存储电容器的第二电容电极。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板包括设置于所述衬底基板的第一导电层，所述第一导电层位于所述第一半导体层远离所述衬底基板的一侧；以及
    所述第一电容结构和所述第三晶体管的第三栅极均位于所述第一导电层。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板包括设置于所述衬底基板的第二导电层，所述第二导电层位于所述第一导电层与所述第二半导体层之间；以及
    所述第一底栅和所述第二电容结构均位于所述第二导电层。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板包括设置于所述衬底基板的第三导电层，所述第三导电层位于所述第二半导体层远离所述衬底基板的一侧； 以及
    所述第一顶栅和所述第三电容结构均位于所述第三导电层。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板包括位于所述衬底基板与所述第一半导体层之间的第一缓冲层，所述第一缓冲层包括氧化硅、氮化硅或氮氧化硅。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板包括位于所述第一半导体层与所述第一导电层之间的第一栅绝缘层，所述第一栅绝缘层包括氧化硅。
  13. 根据权利要求12所述的显示基板，其中，所述显示基板包括位于所述第一导电层与所述第二导电层之间的第二栅绝缘层，所述第二栅绝缘层包括氮化硅。
  14. 根据权利要求13所述的显示基板，其中，所述显示基板包括位于所述第二半导体层与所述第三导电层之间的第四栅绝缘层，所述第四栅绝缘层包括氧化硅。
  15. 根据权利要求13所述的显示基板，其中，所述显示基板还包括设置在所述第二栅绝缘层与所述第二导电层之间的第二缓冲层；以及
    所述第一电容结构与所述第二电容结构之间设置有两层绝缘层，所述两层绝缘层包括所述第二栅绝缘层的一部分和所述第二缓冲层的一部分。
  16. 根据权利要求10所述的显示基板，其中，所述显示基板包括第四导电层，所述第四导电层位于所述第三导电层远离所述衬底基板的一侧；以及
    所述多个薄膜晶体管中的每一个都包括源极和漏极，每一个薄膜晶体管的源极和漏极均位于所述第四导电层。
  17. 根据权利要求16所述的显示基板，其中，所述显示基板包括第五导电层，所述第五导电层位于所述第四导电层远离所述衬底基板的一侧；以及
    所述第五导电层包括遮光层，所述遮光层在所述衬底基板上的正投影至少覆盖所述第一晶体管和所述第二晶体管中的每一个的有源层在所述衬底基板上的正投影。
  18. 根据权利要求16所述的显示基板，其中，所述第四导电层包括第一导电子层和第二导电子层，所述第一导电子层设置在所述层间绝缘层上，所述第二导电子层设置在所述第一导电子层远离所述衬底基板的一侧，并且所述第一导电子层和所述第二导电子层彼此接触。
  19. 一种显示面板，包括根据权利要求1-18中任一项所述的显示基板。
  20. 一种显示装置，包括根据权利要求1-18中任一项所述的显示基板或根据权利要求19所述的显示面板。
  21. 一种显示基板的制造方法，其中，所述制造方法包括以下步骤：
    提供衬底基板；以及
    在所述衬底基板上形成第一晶体管，
    利用构图工艺，在所述衬底基板上制备第一半导体层，所述第一半导体层包括多晶硅半导体硅岛；
    利用构图工艺，在所述第一半导体层远离所述衬底基板的一侧形成第一导电层；
    利用构图工艺，在所述第一导电层远离所述衬底基板的一侧形成第二导电层；
    在所述第二导电层远离所述衬底基板的一侧形成一层绝缘层；以及
    利用构图工艺，在所述第二导电层远离所述衬底基板的一侧形成第二半导体层，所述第二半导体层包括氧化物半导体硅岛，
    其中，所述显示基板包括设置于所述衬底基板的多个薄膜晶体管，所述多个薄膜晶体管至少包括第一晶体管、第二晶体管和第三晶体管，
    所述多个薄膜晶体管中的每一个都包括有源层，所述第三晶体管的有源层位于所述第一半导体层，所述第一晶体管和所述第二晶体管中的至少一个的有源层位于所述第二半导体层；以及
    所述第一晶体管包括第一有源层、第一底栅和第一顶栅，所述第一底栅位于所述衬底基板与所述第一有源层之间，所述第一顶栅位于所述第一有源层远离所述衬底基板的一侧，所述第一有源层、所述第一底栅和所述第一顶栅中的任意两个在所述衬底基板上的正投影彼此至少部分重叠，所述第一底栅和所述第一有源层之间设置有第三 栅绝缘层，所述第一有源层包括所述氧化物半导体硅岛，所述第三栅绝缘层包括氧化硅材料，所述第一顶栅远离所述衬底基板的表面与所述氧化硅材料直接接触，所述第一有源层靠近所述衬底基板的表面与所述氧化硅材料直接接触。
  22. 根据权利要求21所述的显示基板的制造方法，其中，所述制造方法还包括：
    在所述第一顶栅远离所述衬底基板的一侧形成层间绝缘层；
    在层间绝缘层中形成多个第一过孔，所述多个第一过孔暴露所述第一晶体管和所述第二晶体管中每一个的有源层的至少一部分；
    在所述层间绝缘层远离所述衬底基板的一侧沉积第一导电材料层；
    形成多个第二过孔，所述多个第二过孔暴露至少所述第三晶体管的有源层的至少一部分；
    在所述第一导电材料层远离所述衬底基板的一侧沉积第二导电材料层；以及
    通过一次构图工艺，图形化所述第一导电材料层和第二导电材料层，以形成所述多个薄膜晶体管的源极和漏极。
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