WO2023051109A1 - 显示基板、显示面板和显示装置 - Google Patents

显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2023051109A1
WO2023051109A1 PCT/CN2022/114510 CN2022114510W WO2023051109A1 WO 2023051109 A1 WO2023051109 A1 WO 2023051109A1 CN 2022114510 W CN2022114510 W CN 2022114510W WO 2023051109 A1 WO2023051109 A1 WO 2023051109A1
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Prior art keywords
capacitor
plate
base substrate
substrate
transistor
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PCT/CN2022/114510
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English (en)
French (fr)
Inventor
单真真
刘利宾
卢江楠
史世明
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/262,598 priority Critical patent/US20240112636A1/en
Priority to GB2314962.8A priority patent/GB2619676A/en
Publication of WO2023051109A1 publication Critical patent/WO2023051109A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • OLED display device is a type of display device that uses light-emitting OLEDs to display information such as images.
  • OLED display devices have characteristics such as low power consumption, high brightness, and high response speed.
  • Low Temperature Polysilicon Oxide Thin Film Transistor (Low Temperature Poly-Oxide TFT, hereinafter referred to as LTPO TFT) technology is an emerging thin film transistor technology in recent years. Theoretically speaking, LTPO TFT can save 5-15% of power compared with traditional low temperature polysilicon TFT (LTPS TFT for short) technology, making the power consumption of the whole display screen more efficient. Low.
  • a display substrate includes: a base substrate;
  • the display substrate further includes a pixel driving circuit disposed on the base substrate, the pixel driving circuit includes a driving circuit, a storage circuit and a reset circuit, and the reset circuit is connected to the first terminal of the driving circuit or the
  • the second terminal of the driving circuit is electrically connected to initialize the potential of the first terminal of the driving circuit or the potential of the second terminal of the driving circuit during the initialization phase, and the driving circuit is used for Under the control of the potential, the first terminal of the driving circuit is controlled to communicate with the second terminal of the driving circuit, and the energy storage circuit is electrically connected to the control terminal of the driving circuit for storing electric energy;
  • the reset circuit includes a first capacitor, the storage circuit includes a second capacitor, the first capacitor includes a first plate and a second plate opposite to each other, and the second capacitor includes a first plate opposite to each other and the second plate, the first plate of the first capacitor and the first plate of the second capacitor are located on the first conductive layer, the second plate of the first capacitor and the second The second pole plate of the capacitor is located on the second conductive layer, and the orthographic projections of the first pole plate of the first capacitor and the first pole plate of the second capacitor on the base substrate are arranged at intervals, and the The second pole plate of the first capacitor and the orthographic projection of the second pole plate of the second capacitor on the substrate are arranged at intervals, and the first pole plate of the first capacitor and the second pole plate of the first capacitor are arranged at intervals.
  • the orthographic projections of the two plates on the base substrate are at least partially overlapped, and the orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate are at least partially overlapped.
  • overlapping the area of the overlapping portion of the orthographic projection of the first plate of the first capacitor and the second plate of the first capacitor on the substrate substrate is smaller than the first plate of the second capacitor and the first plate of the second capacitor.
  • the area of the overlapping portion of the orthographic projection of the second plate of the second capacitor on the substrate, the first plate of the second capacitor and the second plate of the second capacitor on the substrate The ratio of the area of the overlapping portion of the orthographic projection on the substrate to the area of the overlapping portion of the orthographic projection of the first plate of the first capacitor and the second plate of the first capacitor on the base substrate is between 5 and 20 range.
  • the display substrate further includes a first light emission control line disposed on the base substrate, and the first light emission control line is used to supply a first light emission control signal to the pixel driving circuit;
  • the first light emission control line is located in the first conductive layer, and the overlapping part of the first light emission control line and the second plate of the first capacitor constitutes the first plate of the first capacitor.
  • the pixel driving circuit includes a first light emission control circuit and a second light emission control circuit
  • the first light emission control circuit includes a fifth transistor
  • the second light emission control circuit includes a sixth transistor
  • the fifth transistor includes a fifth gate
  • the sixth transistor includes a sixth gate
  • the first light emission control line applies a first light emission control signal to the fifth gate, the sixth gate, and the sixth gate.
  • the first plate of the first capacitor is not limited to one of the first capacitor.
  • a part of the first light emission control line that overlaps with the first semiconductor layer constitutes the fifth gate, and a portion of the first light emission control line that overlaps with the first semiconductor layer Another part of the sixth gate constitutes the sixth gate, the first light emission control line further includes a widened portion, and the widened portion is located between the fifth gate and the sixth gate along the first direction, A dimension of the widened portion along a second direction is greater than a dimension of each of the fifth gate and the sixth gate along the second direction, wherein the first light emission control line extends in a direction, the second direction intersects the first direction; and at least a portion of the widened portion constitutes a first plate of the first capacitor.
  • the orthographic projection of the second plate of the first capacitor on the substrate covers the orthographic projection of the widening portion on the substrate;
  • the area of the orthographic projection of the first plate of the second capacitor on the base substrate is larger than the area of the orthographic projection of the widened portion on the base substrate; and/or,
  • the area of the orthographic projection of the second pole plate of the second capacitor on the base substrate is larger than the area of the orthographic projection of the second pole plate of the first capacitor on the base substrate.
  • the area of the overlapping portion of the orthographic projection of the first plate of the second capacitor and the second plate of the second capacitor on the base substrate is equal to that of the first capacitor
  • the ratio of the area of the overlapping portion of the orthographic projection of the first pole plate and the second pole plate of the first capacitor on the base substrate is in the range of 8-10.
  • the second plate of the second capacitor includes a through hole exposing at least a part of the first plate of the second capacitor, and the second plate of the first capacitor
  • the ratio of the area of the orthographic projection of the plate on the base substrate to the area of the orthographic projection of the through hole on the base substrate is in the range of 1.1-5.
  • the display substrate further includes a light emitting element reset line located in the first conductive layer and a light emitting element disposed on the base substrate
  • the pixel driving circuit includes a second initialization circuit
  • the second initialization circuit is used to initialize the first pole of the light emitting element under the control of the signal provided by the reset line of the light emitting element.
  • the display substrate further includes a reset control line located in the first conductive layer, the pixel driving circuit includes a first initialization circuit, and the first initialization circuit is used for The drive circuit is initialized under the control of a reset control signal provided by the control line; and the frequency of the signal provided by the reset line of the light-emitting element is higher than the frequency of the reset control signal provided by the reset control line.
  • the display substrate further includes a light emitting element reset line located in the first conductive layer and a light emitting element disposed on the base substrate
  • the pixel driving circuit includes a second initialization circuit
  • the second initialization circuit includes a seventh transistor, the overlapping part of the reset line of the light-emitting element and the first semiconductor layer constitutes the seventh gate of the seventh transistor; and the first plate of the first capacitor
  • the orthographic projection of the first plate of the second capacitor on the base substrate is located in the second direction on the base substrate and the reset line of the light-emitting element is on the base substrate between the orthographic projections of .
  • the pixel driving circuit includes a first transistor, and the portion where the reset control line overlaps with the first semiconductor layer constitutes a first gate of the first transistor; and the first A distance in the first direction between the gate and the first plate of the first capacitor is smaller than a distance in the first direction between the seventh gate and the first plate of the first capacitor.
  • the display substrate further includes a second light emission control line located in the second conductive layer, the second light emission control line, the second plate of the second capacitor and The orthographic projection of the second pole plate of the first capacitor on the base substrate is arranged at intervals along the second direction; and the orthographic projection of the second pole plate of the first capacitor on the base substrate and the The orthographic projection of the one second light emission control line on the substrate is respectively located on both sides of the orthographic projection of the second plate of the second capacitor on the substrate in the second direction.
  • the display substrate further includes: a second semiconductor layer disposed on a side of the second conductive layer away from the base substrate; and a second semiconductor layer disposed on a side far away from the substrate.
  • a third conductive layer on one side of the base substrate, the second semiconductor layer includes an oxide semiconductor material;
  • the display substrate includes another second light-emitting control line in the third conductive layer, and the second light-emitting control line
  • the control line is electrically connected to the other second light emission control line;
  • the pixel drive circuit includes an on-off control circuit, the on-off control circuit includes an eighth transistor, and the second light emission control line is connected to the second light emission control line.
  • the overlapping part of the semiconductor layer forms the bottom gate of the eighth transistor, and the overlapping part of the second light emission control line and the second semiconductor layer forms the top gate of the eighth transistor.
  • the display substrate further includes a fourth conductive layer disposed on a side of the third conductive layer away from the base substrate, the driving circuit includes a third transistor; and the display substrate It includes a fifth conductive component located in the fourth conductive layer, one end of the fifth conductive component is electrically connected to the second plate of the first capacitor through the first via hole, and the other end of the fifth conductive component is connected through the The second via hole is electrically connected to the first electrode of the third transistor.
  • the display substrate includes a sixth conductive part located in the fourth conductive layer, the sixth conductive part includes a first part, a second part and a third part; and the sixth The first part of the conductive component is electrically connected to the first electrode of the fifth transistor through the third via hole, and the second part of the sixth conductive component is electrically connected to the second plate of the second capacitor through the fourth via hole.
  • the display substrate further includes a fifth conductive layer disposed on the side of the fourth conductive layer away from the base substrate, and the display substrate further includes a fifth conductive layer disposed on the fifth conductive layer.
  • the first voltage line; and the third part of the sixth conductive component is electrically connected to the first voltage line through the fifth via hole.
  • the display substrate includes a seventh conductive component located in the fourth conductive layer, the seventh conductive component is electrically connected to the first electrode of the sixth transistor; and the first The orthographic projection of the first electrode plate of a capacitor on the base substrate is located in the first direction, and the orthographic projection of the sixth conductive component on the substrate is the same as that of the seventh conductive component on the substrate. between the orthographic projections on the base substrate, and the orthographic projection of the first plate of the first capacitor on the base substrate, the orthographic projection of the sixth conductive component on the base substrate, and the Any two of the seventh conductive components in the orthographic projection on the base substrate are arranged at intervals.
  • the orthographic projection of the second plate of the first capacitor on the base substrate partially overlaps the orthographic projection of the seventh conductive component on the base substrate.
  • the display substrate includes a fourth conductive component located in the fourth conductive layer, one end of the fourth conductive component is electrically connected to the first electrode of the eighth transistor through a sixth via hole , the other end of the fourth conductive component is electrically connected to the third gate of the third transistor through the seventh via hole and the via hole.
  • the orthographic projection of the first voltage line on the base substrate covers the orthographic projection of the fourth conductive component on the base substrate; and/or, the first The orthographic projection of the voltage line on the base substrate covers the orthographic projection of the active layer of the eighth transistor on the base substrate.
  • a display panel including the above-mentioned display substrate.
  • a display device including the above-mentioned display substrate or the above-mentioned display panel.
  • FIG. 1 is a schematic plan view of a display device according to some embodiments of the present disclosure
  • FIG. 2 is a schematic plan view of a display substrate included in a display device according to some embodiments of the present disclosure
  • FIG. 3 is a structural block diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 5 is a working timing diagram of at least one embodiment of the pixel driving circuit shown in FIG. 4;
  • 6A and 6B are schematic diagrams of signals provided by reset lines of light emitting elements according to some exemplary embodiments of the present disclosure
  • FIG. 7 is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 9 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer and a first conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 10 is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 11 is a schematic diagram illustrating a planar structure of a second semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 12 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 13 is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 14 is a schematic diagram illustrating a combined planar structure of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 15 is a schematic diagram illustrating vias in an insulating layer formed on the structure of FIG. 14;
  • FIG. 16 is a schematic diagram illustrating vias in an insulating layer formed on the structure of FIG. 15;
  • FIG. 17 is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 18 is a diagram illustrating a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG. 20 is a diagram showing a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • 21 is a plan view schematically showing the relative areas of the first capacitor and the second capacitor
  • FIG. 22 is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line AA' in FIG. 20 according to some exemplary embodiments of the present disclosure.
  • Fig. 23 is a diagram showing the light emitting effect of the light emitting element when the high frequency signal shown in Fig. 6B is used.
  • connection may refer to a physical connection, an electrical connection, a communicative connection, and/or a fluid connection.
  • the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a wider sense.
  • the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as meaning only X, only Y, only Z, or Any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • first means for describing various components, components, elements, regions, layers and/or sections
  • these components, components, elements, regions, layers and/or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, component, element, region, layer and/or section from another.
  • a first component, first member, first element, first region, first layer, and/or first portion discussed below could be termed a second component, second member, second element, second region , the second layer and/or the second portion, without departing from the teachings of the present disclosure.
  • spatially relative terms such as “upper,” “lower,” “left,” “right,” etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. relation. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the expression “the same layer” refers to the formation of a film layer for forming a specific pattern using the same film-forming process, and then using the same mask to pattern the film layer through a patterning process.
  • layer structure Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or parts located on the "same layer” are made of the same material and formed by the same patterning process. Usually, multiple elements, components, structures and/or parts located on the "same layer” Or parts have approximately the same thickness.
  • the expression “height” or “thickness” refers to the dimension along the surface of each film layer perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate. Size, or called the size along the normal direction of the display device.
  • the expression "transistor” may refer to a triode, a thin film transistor or a field effect transistor or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • Embodiments of the present disclosure at least provide a display substrate.
  • the display substrate includes: a base substrate; a first semiconductor layer disposed on the base substrate; a first conductive layer disposed on the side of the first semiconductor layer away from the base substrate; and disposed on the The first conductive layer is away from the second conductive layer on the side of the base substrate; wherein, the display substrate further includes a pixel driving circuit disposed on the base substrate, and the pixel driving circuit includes a driving circuit, a storage circuit and A reset circuit, the reset circuit is electrically connected to the first terminal of the driving circuit or the second terminal of the driving circuit, and is used to adjust the potential of the first terminal of the driving circuit or the potential of the driving circuit during the initialization phase.
  • the potential of the second terminal of the drive circuit is initialized, and the drive circuit is used to control the communication between the first terminal of the drive circuit and the second terminal of the drive circuit under the control of the potential of the control terminal, and the energy storage circuit It is electrically connected with the control terminal of the drive circuit, and is used to store electric energy;
  • the reset circuit includes a first capacitor
  • the storage circuit includes a second capacitor
  • the first capacitor includes a first plate and a second plate oppositely arranged
  • the second capacitor includes a first pole plate and a second pole plate oppositely arranged, and the first pole plate of the first capacitor and the first pole plate of the second capacitor are located on the first conductive layer , the second pole plate of the first capacitor and the second pole plate of the second capacitor are located on the second conductive layer, the first pole plate of the first capacitor and the first pole of the second capacitor
  • the orthographic projections of the plates on the base substrate are arranged at intervals, and the orthographic projections of the second polar plate of the first capacitor and the second polar plate of the
  • the orthographic projections of the second polar plate on the base substrate are at least partially overlapped, and the orthographic projections of the first polar plate of the first capacitor and the second polar plate of the first capacitor on the substrate substrate are overlapped.
  • the area of the part is smaller than the area of the overlapping portion of the orthographic projection of the first plate of the second capacitor and the second plate of the second capacitor on the base substrate.
  • FIG. 1 is a schematic plan view of a display device according to some embodiments of the present disclosure.
  • the display device may be an OLED display device.
  • a display device 1000 may include a display panel 1100 , a gate driver 1200 , a data driver 1300 , a controller 1400 and a voltage generator 1500 .
  • the display panel 1100 may include an array substrate 1000 and a plurality of pixels PX, the array substrate 1000 may include a display area AA and a non-display area NA, and the plurality of pixels PX are arranged in an array in the display area AA.
  • a signal generated by the gate driver 1200 may be applied to the pixel PX through a signal line such as a scan signal line GL, and a signal generated by the data driver 1300 may be applied to the pixel PX through a signal line such as a data line DL.
  • a first voltage such as VDD and a second voltage such as VSS may be applied to the pixel PX.
  • a first voltage such as VDD may be higher than a second voltage such as VSS.
  • a first voltage such as VDD may be applied to the anode of the light emitting element (eg OLED), and a second voltage such as VSS may be applied to the cathode of the light emitting element such that the light emitting element can emit light.
  • each pixel PX may include a plurality of sub-pixels, eg, a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • FIG. 2 is a schematic plan view of a display substrate included in a display device according to some embodiments of the present disclosure.
  • the display substrate may be an array substrate for an OLED display panel.
  • the display substrate may include a display area AA and a non-display area NA.
  • the display area AA and the non-display area NA may include multiple borders, such as AAS1, AAS2, AAS3 and AAS4 shown in FIG. 2 .
  • the display substrate may further include a driver located in the non-display area NA.
  • the driver may be located on at least one side of the display area AA.
  • the drivers are respectively located on the left and right sides of the display area AA.
  • the left side and the right side may be the left side and the right side of the display substrate (screen) viewed by human eyes during display.
  • the driver can be used to drive each pixel in the display substrate to display.
  • the driver may include the above-mentioned gate driver 1200 and data driver 1300 .
  • the data driver 1300 is used for sequentially latching the input data according to the timing of the clock signal and converting the latched data into an analog signal and inputting it to each data line of the display substrate.
  • the gate driver 1200 is generally implemented by a shift register, which converts the clock signal into an on/off voltage, which is respectively output to each scanning signal line of the display substrate.
  • the drivers are located on the left and right sides of the display area AA, embodiments of the present disclosure are not limited thereto, and the drive circuits may be located at any suitable position in the non-display area NA.
  • the driver can adopt GOA technology, that is, Gate Driver on Array.
  • GOA technology the gate driving circuit is directly disposed on the array substrate instead of an external driving chip.
  • Each GOA unit is used as a first-level shift register, and each level of shift register is connected to a gate line, and the turn-on voltage is sequentially output through each level of shift register to realize progressive scanning of pixels.
  • each stage of the shift register can also be connected to multiple gate lines. In this way, it can adapt to the development trend of display substrates with high resolution and narrow borders.
  • the display substrate is provided with a left GOA circuit DA1 , a plurality of pixels P located in the display area AA, and a right GOA circuit DA2 .
  • the left GOA circuit DA1 and the right GOA circuit DA2 are respectively electrically connected to the display IC through signal lines, and the supply of GOA signals is controlled by the display IC.
  • the left GOA circuit DA1 and the right GOA circuit DA2 are also electrically connected to respective pixels through signal lines (eg, scanning signal lines GL) to supply driving signals to the respective pixels.
  • the figure exemplarily shows that the shape of the orthographic projection of the sub-pixel on the base substrate is a rounded rectangle, but embodiments of the present disclosure are not limited thereto.
  • the sub-pixel on the base substrate The shape of the orthographic projection on can be rectangle, hexagon, pentagon, square, circle and other shapes.
  • the arrangement of the three sub-pixels in one pixel unit is not limited to the ones shown in FIG. 1 and FIG. 2 .
  • each pixel unit PX may include a plurality of sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.
  • first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 may be described as red sub-pixels, green sub-pixels and blue sub-pixels respectively, however, embodiments of the present disclosure are not limited thereto .
  • the plurality of sub-pixels are arranged in an array along the row direction X and the column direction Y on the base substrate 1 . It should be noted that although in the illustrated embodiment, the row direction X and the column direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited thereto.
  • each sub-pixel includes a pixel driving circuit and a light emitting element.
  • the light-emitting element may be an OLED light-emitting element, including an anode, a light-emitting layer, and a cathode that are stacked.
  • the pixel driving circuit may include a plurality of thin film transistors and at least one storage capacitor.
  • FIG. 3 is a structural block diagram of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • the 8T2C pixel driving circuit is taken as an example to describe the structure of the pixel driving circuit in detail.
  • the embodiments of the present disclosure are not limited to the 8T2C pixel driving circuit. In the case of , other known pixel driving circuit structures can be applied to the embodiments of the present disclosure.
  • the pixel driving circuit is used to drive the light-emitting element 100, and the pixel driving circuit includes a driving circuit 110 and a reset circuit 220;
  • the terminal is electrically connected, and is used for initializing the potential of the first terminal of the driving circuit 110 in the initialization phase.
  • the driving circuit 110 is used to control the communication between the first terminal of the driving circuit 110 and the second terminal of the driving circuit 110 under the control of the potential of the control terminal.
  • the reset circuit controls the potential of the first terminal of the drive circuit or the potential of the second terminal of the drive circuit.
  • the potential of the terminal is initialized to improve the hysteresis phenomenon of the driving transistor, and solve the afterimage and flickering phenomenon caused by the hysteresis of the driving transistor in a low frequency state.
  • the pixel driving circuit further includes a first light emission control circuit 310 and a second light emission control circuit 320 .
  • the first light emission control circuit 310 is electrically connected to the first light emission control line E1, the first end of the driving circuit 11 and the first voltage line V1 respectively, and is used for the first light emission provided on the first light emission control line E1. Under the control of the light emission control signal, the connection between the first end of the driving circuit 11 and the first voltage line V1 is controlled.
  • the second light emission control circuit 320 is electrically connected to the second light emission control line E2, and the second end of the driving circuit 11 is electrically connected to the first pole of the light emitting element 100, for the second light emission control line E2 Under the control of the provided second light-emitting control signal, the communication between the second end of the driving circuit 110 and the first pole of the light-emitting element 100 is controlled.
  • the second pole of the light emitting element 100 is electrically connected to the second voltage line V2.
  • the first light-emitting control circuit 310 controls the first terminal of the driving circuit 110 to The first voltage line V1 is connected, and the second light emission control circuit 320 controls the connection between the second terminal of the driving circuit 110 and the first pole of the light emitting element 100 under the control of the second light emission control signal. connection between.
  • the pixel driving circuit further includes a reset circuit 20, and the reset circuit 20 may include a first capacitor C1, and the first capacitor C1 may include a first plate C1a and a second plate C1b.
  • the first plate of the first capacitor C1 is electrically connected to the first lighting control line E1
  • the second plate of the first capacitor C1 is electrically connected to the first end of the driving circuit 11 .
  • the first node labeled N1 is electrically connected to the control terminal of the driving circuit 11
  • the second node labeled N2 is electrically connected to the first terminal of the driving circuit 11
  • the labeled N3 is the driving node.
  • the second end of the circuit 11 is electrically connected to the third node.
  • the potential of the light emission control signal provided by E1 changes from a low voltage Vgl to a high voltage Vgh
  • N2 is in a floating state
  • the potential of N2 increases with
  • the potential of the first plate of the first capacitor C1 varies
  • the potential of N2 becomes V1+Vgh-Vgl.
  • the gate-source voltage of the driving transistor in the driving circuit 110 is less than Vth (Vth is the threshold voltage of the driving transistor. ), the driving transistor is in the conduction bias state, reducing the hysteresis caused by N2 floating.
  • the driving transistor when the pixel driving circuit is working, the driving transistor is in the on-bias state before data writing, so as to ensure that the driving transistor in each pixel driving circuit is from the on-bias state Starting to charge and compensate, without being affected by the data voltage of the previous frame, can eliminate the influence of hysteresis of the driving transistor, and improve afterimage and response time.
  • the pixel driving circuit may further include an energy storage circuit 210 , a data writing circuit 530 , a compensation control circuit 520 , an on-off control circuit 510 , a first initialization circuit 410 and a second initialization circuit 420 .
  • the energy storage circuit 210 is electrically connected to the control terminal of the driving circuit 11 for storing electric energy.
  • the data writing circuit 530 is electrically connected to the scanning line S1, the data line D1 and the first end of the driving circuit 110, and is used to control the data line D1 under the control of the scanning signal provided by the scanning line S1. The data voltage above is written into the first terminal of the driving circuit 110 .
  • the on-off control circuit 510 is electrically connected to the scanning line S1, the control terminal of the driving circuit 110 and the connection node N0, and is used to control the control terminal of the driving circuit 110 to connect to the connecting node N0 under the control of the scanning signal. Nodes N0 are connected.
  • the compensation control circuit 520 is electrically connected to the scanning line S1, the connection node N0 and the second end of the driving circuit 110, and is used to control the connection node N0 under the control of the scanning signal provided by the scanning line S1. It communicates with the second end of the driving circuit 110 .
  • the first initialization circuit 410 is electrically connected to the reset control line R1, the first initial voltage line Vi1 and the connection node N0 respectively, and is used to set the first initial voltage to The first initial voltage provided by the line is written into the connection node N0.
  • the second initialization circuit 420 is electrically connected to the light-emitting element reset line R2, the second initial voltage line Vi2, and the first pole of the light-emitting element 100 respectively, and is used for the reset control signal provided on the light-emitting element reset line R2. Under control, the second initial voltage provided by the second initial voltage line is written into the first electrode of the light emitting element 10 .
  • a display cycle when the pixel driving circuit is in operation, may include an initialization phase, a data writing phase and a light emitting phase which are arranged successively.
  • the on-off control circuit 510 controls the connection between the control terminal of the driving circuit 110 and the connection node N0 under the control of the scan signal
  • the first initialization circuit 410 controls the connection between the control terminal of the reset control signal
  • write the first initial voltage into the connection node N0 so as to write the first initial voltage into the control terminal of the driving circuit 110
  • the reset provided by the second initialization circuit 420 on the light emitting element reset line R2 Under the control of the control signal, write the second initial voltage provided by the second initial voltage line Vi2 into the first pole of the light emitting element 100, so as to control the light emitting element 100 not to emit light, and clear the first pole of the light emitting element 100 residual charge.
  • the data writing circuit 530 controls to write the data voltage on the data line D1 into the first end of the driving circuit 110 under the control of the scan signal, and the compensation control circuit 520 Under the control of the scanning signal, the connection between the connection node N0 and the second end of the driving circuit 110 is controlled.
  • the driving transistor in the driving circuit 110 is turned on, so as to charge the energy storage circuit with the data voltage, and change the potential of the control terminal of the driving circuit 110 until the driving transistor is turned off.
  • the first light-emitting control circuit 310 controls the communication between the first terminal of the driving circuit 110 and the first voltage line V1 under the control of the first light-emitting control signal, and the second light-emitting control circuit Under the control of the second light emission control signal, the circuit 320 controls the connection between the second terminal of the driving circuit 110 and the first pole of the light emitting element 100 , and the driving circuit 110 drives the light emitting element 100 to emit light.
  • the reset circuit 220 includes a first capacitor C1; the first light emission control circuit 310 includes a fifth transistor T5, and the second light emission control circuit 320 includes a sixth transistor T6
  • the on-off control circuit 510 includes an eighth transistor T8; the second initialization circuit 420 includes a seventh transistor T7; the first initialization circuit 410 includes a first transistor T1, and the compensation control circuit 520 includes a second transistor T2, the data writing circuit 530 includes a fourth transistor T4, the driving circuit 110 includes a driving transistor T3, and the energy storage circuit 210 includes a second capacitor C2;
  • the light emitting element is an organic light emitting diode 100 .
  • the first plate of the first capacitor C1 is electrically connected to the light emission control line E1, and the second plate of the first capacitor C1 is electrically connected to the node N2, that is, the second plate of the first capacitor C1 is connected to the fifth transistor T5
  • the second pole of the transistor T3 is electrically connected to the first pole of the third transistor T3.
  • the first plate of the second capacitor C2 is electrically connected to the node N1, and the second plate of the second capacitor C2 is electrically connected to the first voltage line.
  • the gate of the first transistor T1 is electrically connected to the reset control line R1, the first pole of the first transistor T1 is electrically connected to the first initial voltage line Vi1, and the second pole of the first transistor T1 is electrically connected to the node N0.
  • the first initial voltage line Vi1 is used to provide a first initial voltage.
  • the gate of the second transistor T2 is electrically connected to the scan line S1, the second pole of the second transistor T2 is electrically connected to the node N3, and the first pole of the second transistor T2 is electrically connected to the node N0, that is, the second pole of the second transistor T2 is electrically connected to the node N0.
  • One pole is electrically connected to the second pole of the first transistor T1 and the first pole of the eighth transistor T8.
  • the gate of the third transistor T3 is electrically connected to the node N1
  • the first electrode of the third transistor T3 is electrically connected to the node N2
  • the second electrode of the third transistor T3 is electrically connected to the node N3.
  • the gate of the fourth transistor T4 is electrically connected to the scan line S1
  • the first electrode of the fourth transistor T4 is electrically connected to the data line D1
  • the second electrode of the fourth transistor T4 is electrically connected to the node N2.
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the first pole of the fifth transistor T5 is electrically connected to the first voltage line V1, and the second pole of the fifth transistor T5 is electrically connected to the first pole of the third transistor T3. connect.
  • the first voltage line is used to provide a high voltage VDD.
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1; the first pole of the sixth transistor T6 is electrically connected to the node N3, that is, the first pole of the sixth transistor T6 is connected to the second pole of the third transistor T3, the second pole of the sixth transistor T6
  • the second poles of the second transistor T2 are electrically connected; the second pole of the sixth transistor T6 is electrically connected with the anode of the organic light emitting diode 100 .
  • the gate of the seventh transistor T7 is electrically connected to the light-emitting element reset line R2, the first pole of the seventh transistor T7 is electrically connected to the second initial voltage line Vi2, and the second pole of the seventh transistor T7 is electrically connected to the node N4, that is, The second pole of the seventh transistor T7 is electrically connected with the first pole of the sixth transistor T6 and the anode of the organic light emitting diode 100 .
  • the second initial voltage line Vi2 is used to provide a second initial voltage.
  • the signal provided by the reset line R2 of the light emitting element will be further described in detail below.
  • the gate of the eighth transistor T8 is electrically connected to the second light emission control line E2, the first pole of the eighth transistor T8 is electrically connected to the node N0, and the second pole of the eighth transistor T8 is electrically connected to the node N1.
  • the anode of the OLED 100 is electrically connected to the node N4, and the cathode of the OLED 100 is electrically connected to the second voltage line for providing a low voltage VSS.
  • the first light emission control line E1 applies a first light emission control signal to the gate of the fifth transistor T5, the gate of the sixth transistor T6 and the first plate C1a of the first capacitor C1.
  • Vi2 may be the same as Vi1 or different from Vi2.
  • the eighth transistor T8 may be an oxide thin film transistor, and the other transistors T1 - T7 may be low temperature polysilicon thin film transistors. But the embodiments of the present disclosure are not limited thereto.
  • the voltage value of Vi1 may be greater than or equal to -6V and less than or equal to -2V, for example, the voltage value of Vi1 may be -2V, -3V, -4V, -5V or -6V, etc., but not limited to this;
  • the threshold voltage Vth of the transistor can be greater than or equal to -5V and less than or equal to -0.5V; for example, Vth can be -2.5V or -3V, etc.;
  • the voltage value of the high voltage VDD provided by the first voltage line may be greater than or equal to 3V and less than or equal to 6V, for example, the voltage value of VDD may be 4.6V; but not limited thereto;
  • the absolute value of the voltage value of the high voltage VDD may be greater than 1.5 times the absolute value of Vth, for example, the absolute value of the voltage value of VDD may be 1.6 times, 1.8 times, or 2 times the absolute value of Vth.
  • the voltage value of the low voltage VSS provided by the second voltage line may be greater than or equal to -6V and less than or equal to -3V; for example, the voltage value of VSS may be -5V, -4V or -3V.
  • the voltage value of Vi2 may be greater than or equal to -7V and less than or equal to 0V.
  • the voltage value of the second initialization voltage may be -6V, -5V, -4V, -3V or -2V; but not limited thereto.
  • the voltage difference between the voltage value of Vi2 and the voltage value of VSS needs to be smaller than the turn-on voltage of the light-emitting element, so that when the first pole of the light-emitting element is connected to Vi2, the light-emitting element does not emit light.
  • FIG. 5 is a working timing diagram of at least one embodiment of the pixel driving circuit shown in FIG. 4 .
  • the display cycle may include an initialization phase t1 , a data writing phase t2 and a light emitting phase t3 which are set successively.
  • the potential of the light emission control signal provided by the first light emission control line E1 is converted from the low voltage Vgl to the high voltage Vgh, the reset control line R1 provides a low voltage signal, the second light emission control line E2 provides a high voltage signal, and the scanning line S1 provides a high-voltage signal, transistors T6 and T4 are turned on, and Vi1 is written into node N1, and the potential of node N2 becomes VDD+(Vgh-Vgl).
  • the gate-source voltage of transistor T3 is less than the threshold voltage Vth of transistor T3, and transistor T3 In the conduction bias state; the transistor T5 is turned on, Vi2 is written into the anode of the OLED 100 , the OLED 100 does not emit light, and the residual charge of the anode of the OLED 100 is removed.
  • the reset control line R1 provides a high-voltage signal
  • the second light-emitting control line E2 provides a high-voltage signal
  • the scanning line S1 provides a low-voltage signal
  • the first light-emitting control line E1 provides a high-voltage signal
  • the transistors T2 and T4 and T8 are turned on, the data voltage Vdata on the data line D1 is written into the node N2, the nodes N1 and N3 are connected, and the second capacitor C2 is charged through Vdata to change the potential of the gate of the transistor T3 until the transistor T3 is turned off, The potential of the gate of the transistor T3 becomes Vdata+Vth.
  • the reset control line R1 provides a high-voltage signal
  • the second light-emitting control line E2 provides a low-voltage signal
  • the scanning line S1 provides a high-voltage signal
  • the first light-emitting control line E1 provides a low-voltage signal
  • the transistors T3, T5 and T6 When the transistor T3 is turned on, the organic light emitting diode 100 is driven to emit light. At this time, the light emitting current of the organic light emitting diode 100 is 0.5K (Vdata-VDD) 2 ; where, K is the current coefficient of the transistor T3.
  • the pulse width of the first light emission control signal provided by the first light emission control line E1 may be the same as the pulse width of the second light emission control signal provided by the second light emission control line E2, or the first light emission control signal
  • the pulse width of the first light emission control signal provided by the line E1 may be longer than the pulse width of the second light emission control signal provided by the second light emission control line E2 by a predetermined time.
  • the pulse width of the first light emission control signal provided by the first light emission control line E1 can be the same as the pulse width of the second light emission control signal provided by the second light emission control line E2, it may occur in the initialization stage that the transistors T5 and T6 cannot correct shutdown conditions. Based on this, in at least one embodiment of the present disclosure, the pulse width of the first light emission control signal provided by the first light emission control line E1 may be longer than the pulse width of the second light emission control signal provided by the second light emission control line E2 by a predetermined time, The predetermined time may be less than or equal to 0.5H, and 1H is a line scanning time.
  • the transistors T5 and T6 are turned off, so as to disconnect the connection between the first voltage line and the first pole of the transistor T3, and turn off the transistor T3
  • the connection between the second pole of the organic light emitting diode 100 and the anode of the organic light emitting diode 100 makes the organic light emitting diode 100 not emit light so as not to affect the light emission.
  • the transistor T8 included in the on-off control circuit may be an oxide thin film transistor. In this way, the leakage current of the control terminal of the driving circuit can be reduced, and the stability of the voltage of the control terminal of the driving circuit can be ensured during low-frequency operation, which is beneficial to improving display quality, improving display uniformity, and reducing flicker (flicker).
  • the transistor T7 can be controlled by a separate GOA, which is electrically connected to the reset line R2 of the light emitting element, so that the organic light emitting diode 100 can be reset at a frequency of 60 Hz.
  • the signal provided by the light emitting element reset line R2 may be a high frequency signal.
  • the frequency of the signal provided by the light emitting element reset line R2 may be higher than the frequency of the reset control signal provided by the reset control line R1.
  • the frequency of the signal supplied from the light emitting element reset line R2 shown in FIG. 6B is higher than the frequency of the signal supplied from the light emitting element reset line R2 shown in FIG. 6A .
  • the frequency of the signal provided by the reset line R2 of the light emitting element is substantially equal to the frequency of the reset control signal provided by the reset control line R1 .
  • Fig. 23 is a diagram showing the light emitting effect of the light emitting element when the high frequency signal shown in Fig. 6B is used.
  • the refresh frequency of the anode reset of the light-emitting element can be increased, so that the brightness establishment time of the refresh phase and the hold phase of the light-emitting element are consistent.
  • the low component of the luminous maintenance stage can be reduced, the brightness change visible to the naked eye can be reduced, and the flicker level can be improved.
  • the load can be reduced to reduce power consumption.
  • each thin film transistor T1, T2, T3, T4, T5, T6, T7 and T8 may be a p-channel field effect transistor, but the embodiment of the present disclosure is not limited thereto , at least some of the respective thin film transistors T1, T2, T3, T4, T5, T6, T7 and T8 may be n-channel field effect transistors.
  • FIG. 7 is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • 9 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer and a first conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram illustrating a planar structure of a second semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • 12 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram illustrating via holes in an insulating layer formed on the structure of FIG. 14 .
  • FIG. 16 is a schematic diagram illustrating vias in an insulating layer formed on the structure of FIG. 15 .
  • FIG. 17 is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 18 is a diagram illustrating a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • 20 is a diagram showing a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 21 is a plan view schematically showing the relative areas of the first capacitor and the second capacitor.
  • FIG. 22 is a schematic diagram illustrating a cross-sectional structure of a display substrate taken along line AA' in FIG. 20 according to some exemplary embodiments of the present disclosure.
  • the display substrate includes a base substrate 1 and a plurality of film layers disposed on the base substrate 1 .
  • the multiple film layers shown at least include a first semiconductor layer 2, a first conductive layer 3, a second conductive layer 4, a second semiconductor layer 5, a third conductive layer 6, a fourth conductive layer 7 and The fifth conductive layer 8 .
  • the first semiconductor layer 2 , the first conductive layer 3 , the second conductive layer 4 , the second semiconductor layer 5 , the third conductive layer 6 , the fourth conductive layer 7 and the fifth conductive layer 8 are arranged away from the base substrate 1 in sequence.
  • the first semiconductor layer 2 may be formed of a semiconductor material such as low-temperature polysilicon, and its film thickness may be in the range of 400-800 angstroms, for example, 500 angstroms.
  • the second semiconductor layer 5 may be formed of an oxide semiconductor material, such as polysilicon oxide semiconductor material such as IGZO, and its film thickness may be in the range of 300 ⁇ 600 angstroms, for example, 400 angstroms.
  • the first conductive layer 3, the second conductive layer 4 and the third conductive layer 6 can be formed by the conductive material forming the gate of the thin film transistor, for example, the conductive material can be Mo, and its film thickness can be in the range of 2000-3000 angstroms within, for example, 2500 Angstroms.
  • the fourth conductive layer 7 and the fifth conductive layer 8 can be formed by the conductive material forming the source and drain electrodes of the thin film transistor, for example, the conductive material can include Ti, Al, etc., the fourth conductive layer 7 and the fifth conductive layer 8 can be It has a laminated structure formed of Ti/Al/Ti, and its film thickness can be in the range of 7000-9000 angstroms. For example, in the case where the fourth conductive layer 7 and the fifth conductive layer 8 have a laminated structure formed of Ti/Al/Ti, the thickness of each layer of Ti/Al/Ti can be about 500 angstroms, 5500 angstroms and 500 Angstroms.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be arranged along the The first semiconductor layer 2 shown is formed.
  • the eighth transistor T8 may be formed along the second semiconductor layer 5 as shown in FIG. 12 .
  • the first semiconductor layer 2 may have a bent or bent shape, and may include a first active layer 20a corresponding to the first transistor T1, a second active layer 20b corresponding to the second transistor T2, The third active layer 20c corresponding to the third transistor T3, the fourth active layer 20d corresponding to the fourth transistor T4, the fifth active layer 20e corresponding to the fifth transistor T5, the fourth active layer 20e corresponding to the sixth transistor T6 Six active layers 20f and a seventh active layer 20g corresponding to the seventh transistor T7.
  • the first semiconductor layer 2 may comprise polysilicon, such as a low temperature polysilicon material.
  • the active layer of each transistor may include a channel region, a source region and a drain region.
  • the channel region may not be doped or the doping type is different from that of the source region and the drain region, and thus has semiconductor characteristics.
  • the source region and the drain region are located on both sides of the channel region, respectively, and are doped with impurities, and thus have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor.
  • the first transistor T1 includes a first active layer 20a and a first gate G1.
  • the first active layer 20a includes a first source region 203a, a first drain region 205a, and a first channel region 201a connecting the first source region 203a and the first drain region 205a.
  • the first source region 203a and the first drain region 205a extend in two opposite directions with respect to the first channel region 201a.
  • the second transistor T2 includes a second active layer 20b and a second gate G2.
  • the second active layer 20b includes a second source region 203b, a second drain region 205b, and a second channel region 201b connecting the second source region 203b and the second drain region 205b.
  • the second source region 203b and the second drain region 205b extend in two opposite directions with respect to the second channel region 201b.
  • the third transistor T3 includes a third active layer 20c and a third gate G3.
  • the third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c.
  • the third source region 203c and the third drain region 205c extend in two opposite directions with respect to the third channel region 201c.
  • the fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4.
  • the fourth active layer 20d includes a fourth source region 203d, a fourth drain region 205d, and a fourth channel region 201d connecting the fourth source region 203d and the fourth drain region 205d.
  • the fourth source region 203d and the fourth drain region 205d extend in two opposite directions with respect to the fourth channel region 201d.
  • the fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5.
  • the fifth active layer 20e includes a fifth source region 203e, a fifth drain region 205e, and a fifth channel region 201e connecting the fifth source region 203e and the fifth drain region 205e.
  • the fifth source region 203e and the fifth drain region 205e extend in two opposite directions with respect to the fifth channel region 201e.
  • the sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6.
  • the sixth active layer 20f includes a sixth source region 203f, a sixth drain region 205f, and a sixth channel region 201f connecting the sixth source region 203f and the sixth drain region 205f.
  • the sixth source region 203f and the sixth drain region 205f extend in two opposite directions with respect to the sixth channel region 201f.
  • the seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7.
  • the seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g connecting the seventh source region 203g and the seventh drain region 205g.
  • the seventh source region 203g and the seventh drain region 205g extend in two opposite directions with respect to the seventh channel region 201g.
  • the structures 21 and 22 located in the first semiconductor layer 2 are part of the active layer of adjacent sub-pixels, that is to say, what is mainly shown in FIG. 7 is the part of the active layer of one sub-pixel.
  • the reset control line R1 , the scan line S1 , the first light emission control line E1 and the light emitting element reset line R2 are all located in the first conductive layer 3 .
  • the first conductive structure CG1 is also located in the first conductive layer 3 .
  • the overlapping portion of the first conductive structure CG1 and the first semiconductor layer 2 forms the third gate G3 of the third transistor T3.
  • the overlapping portion of the reset control line R1 and the first semiconductor layer 2 forms the first gate G1 of the first transistor T1.
  • a part of the scanning line S1 overlapping the first semiconductor layer 2 forms the second gate G2 of the second transistor T2, and another part of the scanning line S1 overlapping the first semiconductor layer 2 forms the fourth gate G4 of the fourth transistor T4.
  • a portion of the first light emission control line E1 overlapping with the first semiconductor layer 2 forms a fifth gate G5 of the fifth transistor T5.
  • Another part of the first light emission control line E1 overlapping with the first semiconductor layer 2 forms the sixth gate G6 of the sixth transistor T6.
  • the overlapping portion of the reset line R2 of the light emitting element and the first semiconductor layer 2 forms the seventh gate G7 of the seventh transistor T7.
  • the first conductive structure CG1 also forms a plate of the second capacitor C2, such as the first plate C2a. That is, the first conductive structure CG1 serves as the gate of the third transistor T3 and a plate of the second capacitor C2 at the same time.
  • the first light emission control line E1 has a widened portion E1W, and the widened portion E1W is located between the fifth grid G5 and the sixth grid G6. As shown in FIG. 9 , in the extension direction of the first light emission control line E1 , that is, in the first direction X, the widened portion E1W is located between the fifth grid G5 and the sixth grid G6 . The size of the widened part E1W along the second direction Y is greater than the size of other parts of the first light emission control line E1 along the second direction Y.
  • the dimension of the widened portion E1W along the second direction Y is greater than the dimension of each of the fifth grid G5 and the sixth grid G6 along the second direction Y, wherein the first light emission control line E1 extends along the first direction X, and the second direction Y intersects the first direction X.
  • the second direction Y is perpendicular to the first direction X.
  • the orthographic projection of the first plate C1a of the first capacitor on the substrate in the second direction Y is located at the orthographic projection of the first plate C2a of the second capacitor on the substrate. Between the projection and the orthographic projection of the light emitting element reset line R2 on the base substrate.
  • the distance PD1 between the first grid G1 and the first plate C1a of the first capacitor in the first direction X is smaller than that between the seventh grid G7 and the first capacitor.
  • the distance PD1 in the first direction X between the first grid G1 and the first plate C1a of the first capacitor can be set by the first grid G1 in the first direction X
  • the distance between the midline above and the midline of the first plate C1a of the first capacitor in the first direction X indicates that, similarly, the distance between the seventh grid G7 and the first plate C1a of the first capacitor is
  • the pitch PD2 in the first direction X can be represented by the distance between the centerline of the seventh grid G7 in the first direction X and the centerline of the first plate C1a of the first capacitor in the first direction X.
  • the second light emission control line E2 is located in the second conductive layer 4 .
  • the second plate C1b of the first capacitor C1 and the second plate C2b of the second capacitor C2 are also located in the second conductive layer 4 .
  • the orthographic projection of the second plate C1b of the first capacitor C1 and the widened part E1W of the first light emission control line E1 on the base substrate at least partially overlaps, and the first light emission control line E1 and the first light emission control line E1 of the first capacitor C1
  • the overlapping portion of the second plate C1b forms the first plate C1a of the first capacitor C1. That is to say, at least a part of the widened portion E1W constitutes the first plate C1a of the first capacitor C1.
  • the orthographic projection of the second plate C2b of the second capacitor C2 and the first conductive structure CG1 on the substrate at least partially overlaps, and the first conductive structure CG1 overlaps with the second plate C2b of the second capacitor C2.
  • the second plate C2a of the second capacitor C2 is partially formed.
  • FIG 21 it schematically shows the orthographic projection of the overlapping portion of the first plate C1a and the second plate C1b of the first capacitor C1 on the substrate, and the first plate C2a of the second capacitor C2 The orthographic projection of the overlapping part with the second plate C2b on the base substrate.
  • the orthographic projection of the second plate C1b of the first capacitor on the substrate substantially covers the orthographic projection of the widened portion E1W on the substrate, the The area of the orthographic projection of the first plate C2a of the second capacitor on the substrate is larger than the area of the orthographic projection of the widened portion E1W on the substrate.
  • the first pole plate C1a located in the first conductive layer 3 and the second pole plate C1b located in the second conductive layer 4 are oppositely arranged. It should be understood that an insulating layer or a dielectric layer is formed between the first conductive layer 3 and the second conductive layer 4 . In this way, a first capacitance C1 is formed between the first plate C1 a located in the first conductive layer 3 and the second plate C1 b located in the second conductive layer 4 . Likewise, a second capacitor C2 is formed between the first plate C2 a located in the first conductive layer 3 and the second plate C2 b located in the second conductive layer 4 .
  • the area of the orthographic projection of the overlapping portion of the first plate C1a and the second plate C1b of the first capacitor C1 on the substrate is smaller than that of the first plate C2a and the second plate of the second capacitor C2.
  • the capacitance value of the first capacitor C1 is smaller than the capacitance value of the second capacitor C2.
  • the ratio of the capacitance value of the second capacitor C2 to the capacitance value of the first capacitor C1 may be in the range of 5-20, for example, in the range of 5-10, or, in the range of 8-10, in the range of 8 ⁇ 9 range.
  • the first capacitor by setting the capacitance value of the first capacitor, the first capacitor can maintain the potential at the node N2 constant, so that even when the frequency of the driving signal changes, the first capacitor of the driving transistor can be controlled. extreme voltage to prevent flicker and/or ghosting.
  • the capacitance value of the second capacitor C2 is set to be larger, which can improve the performance of the display panel and reduce the power consumption of the display panel.
  • the display device by setting the ratio of the capacitance value of the second capacitor C2 to the capacitance value of the first capacitor C1 in the range of 5-20, especially in the range of 8-10, it is beneficial to improve the driving Transistor stability, when the driving frequency is changed, the display device can prevent flicker and/or ghosting by controlling the voltage at the first pole of the driving transistor.
  • the second plate C2b includes a through hole 4H exposing a part of the first conductive structure CG1 to facilitate the electrical connection between the third gate G3 of the third transistor T3 and other components.
  • the through hole 4H exposes at least a part of the first plate C2a of the second capacitor.
  • the ratio of the area of the orthographic projection of the second plate C1b of the first capacitor on the substrate to the area of the orthographic projection of the through hole 4H on the substrate is between 1.1 and 5. within range. That is, the area of the orthographic projection of the second plate C1b of the first capacitor on the substrate is slightly larger than the area of the orthographic projection of the through hole 4H on the substrate.
  • the orthographic projection of the widened portion E1W of the first light emission control line E1 forming the first plate C1a on the substrate has a substantially rectangular shape
  • the second plate C1b is formed on the substrate.
  • the orthographic projection on the substrate has a roughly rectangular shape.
  • “approximately rectangular” includes shapes such as a rectangle, a rectangle with at least one chamfered corner, and a rectangle with at least one rounded corner.
  • a second light emission control line 42 is located in the second conductive layer 4 .
  • the orthographic projections of the one second lighting control line 42, the second plate C2b of the second capacitor, and the second plate C1b of the first capacitor on the base substrate are along the second direction Y interval setting.
  • the orthographic projection of the second plate C1b of the first capacitor on the substrate and the orthographic projection of the one second light emission control line 42 on the substrate are respectively located in the second direction on the substrate.
  • the second plate C2b of the second capacitor is on both sides of the orthographic projection on the base substrate.
  • the second semiconductor layer 5 includes an eighth active layer 20h corresponding to the eighth transistor T8.
  • the eighth active layer 20h of the eighth transistor T8 extends substantially along the second direction Y in the drawing.
  • the eighth active layer 20h includes an eighth source region 203h, an eighth drain region 205h, and an eighth channel region 201h connecting the eighth source region 203h and the eighth drain region 205h.
  • the eighth source region 203h and the eighth drain region 205h extend in two opposite directions with respect to the eighth channel region 201h.
  • the second semiconductor layer 5 may include an oxide semiconductor material such as a low temperature polysilicon oxide semiconductor material (abbreviated as LTPO).
  • the active layer of each transistor may include a channel region, a source region and a drain region.
  • the channel region may not be doped or the doping type is different from that of the source region and the drain region, and thus has semiconductor characteristics.
  • the source region and the drain region are located on both sides of the channel region, respectively, and are doped with impurities, and thus have conductivity. Impurities may vary depending on whether the TFT is an N-type or P-type transistor.
  • another second light emission control line 62 is located in the third conductive layer 6 .
  • one second light emission control line 42 and another second light emission control line 62 can both transmit the second light emission control signal.
  • one second light emission control line 42 and another second light emission control line 62 may be electrically connected in the peripheral area of the display substrate, thereby forming the second light emission control line E2 as shown.
  • the part where one second light emission control line 42 overlaps with the second conductive layer 4 forms the bottom gate G81 of the eighth transistor T8, and the part where the other second light emission control line 62 overlaps with the second conductive layer 4 forms the eighth transistor T8.
  • the eighth transistor T8 is configured as an oxide semiconductor transistor, and the eighth transistor T8 has a double-gate structure, which is beneficial to reduce the leakage current of the node N1, thereby facilitating the stability of the potential of the node N1.
  • the first initial voltage line Vi1 is located in the third conductive layer 6 . That is, a part of the second light emission control line E2 and the first initial voltage line Vi1 are located in the same layer.
  • a separate light emission control signal can be provided for the eighth transistor T8.
  • the display substrate further includes a second initial voltage line Vi2 located in the fourth conductive layer 7 and a plurality of conductive components, for example, the plurality of conductive components may include a first conductive component 71, a second conductive component 72 , the third conductive component 73 , the fourth conductive component 74 , the fifth conductive component 75 , the sixth conductive component 76 and the seventh conductive component 77 .
  • the plurality of conductive components may include a first conductive component 71, a second conductive component 72 , the third conductive component 73 , the fourth conductive component 74 , the fifth conductive component 75 , the sixth conductive component 76 and the seventh conductive component 77 .
  • the display substrate further includes a data line D1 , a first voltage line V1 and a first conductive member 81 located in the fifth conductive layer 8 .
  • One end of the first conductive member 71 is electrically connected to the source region 203 a of the first transistor T1 through the via hole VH2 .
  • the other end of the first conductive component 71 is electrically connected to the first initial voltage line Vi1 through the via hole VH1 .
  • the source of the first transistor T1 is electrically connected to the first initial voltage line Vi1.
  • the first initial voltage can be applied to the source of the first transistor T1.
  • One end of the second conductive member 72 is electrically connected to the source region 203d of the fourth transistor T4 through the via hole VH3, and the other end of the second conductive member 72 is electrically connected to the data line D1 through the via hole VH4. In this way, the source of the fourth transistor T4 is electrically connected to the data line D1. In this way, the data signal can be applied to the source of the fourth transistor T4.
  • One end of the third conductive member 73 is electrically connected to the source region 203b of the second transistor T2 through the via hole VH5, and the other end of the third conductive member 73 is electrically connected to the drain region 205h of the eighth transistor T8 through the via hole VH6. In this way, the source of the second transistor T2 and the drain of the eighth transistor T8 can be electrically connected.
  • One end of the fourth conductive member 74 is electrically connected to the source region 203h of the eighth transistor T8 through the via hole VH7, and the other end of the fourth conductive member 74 is electrically connected to the third gate G3 through the via hole VH8 and the via hole 4H.
  • the node N1 shown in FIG. 4 is formed, which electrically connects the source of the eighth transistor T8, the third gate G3, and a plate C2a of the second capacitor C2.
  • the orthographic projection of the via hole VH8 on the base substrate falls within the orthographic projection of the via hole 4H on the substrate substrate, so that a part of the lower third grid G3 is exposed through the via hole VH8 and the via hole 4H, thereby It is beneficial to realize the electrical connection between the third gate G3 and the source of the eighth transistor T8.
  • One end of the fifth conductive member 75 is electrically connected to a plate C1b of the first capacitor through the via hole VH10, and the other end of the fifth conductive member 75 is connected to the drain region 205d of the fourth transistor T4 and the third transistor T3 through the via hole VH9.
  • the drain region 205c is electrically connected.
  • the node N2 shown in FIG. 4 is formed, which electrically connects the drain of the fourth transistor T4, the drain of the third transistor T3 and a plate C1b of the first capacitor C1.
  • the first part of the sixth conductive part 76 is electrically connected to the drain region 205e of the fifth transistor T5 through the via hole VH11, and the second part of the sixth conductive part 76 is electrically connected to a plate C2b of the second capacitor C2 through the via hole VH12. , the third portion of the sixth conductive member 76 is electrically connected to the first voltage line V1 through the via hole VH13. In this way, the high voltage VDD can be applied to the drain of the fifth transistor T5 and the plate C2b of the second capacitor C2.
  • the orthographic projection of the fifth conductive component 75 on the base substrate is located between the orthographic projection of the fourth conductive component 74 on the base substrate and the orthographic projection of the sixth conductive component 76 on the base substrate.
  • the sixth conductive member 76 may include a first part and a second part, the orthographic projection of the first part on the base substrate has a reverse L shape, and the orthographic projection of the second part on the base substrate has an approximate rectangle, Hexagonal or octagonal shape.
  • the first portion and the second portion of the sixth conductive member 76 are connected to each other to form an integral structure.
  • the orthographic projection of the fifth conductive member 75 on the base substrate and the orthographic projection of the first plate and the second plate of the second capacitor C2 on the base substrate both overlap.
  • one plate of the second capacitor C2 is connected to a low potential, so that the potential of the N1 node can be further pulled down, which is beneficial for light-emitting display.
  • the seventh conductive member 77 is electrically connected to the source region 203f of the sixth transistor T6 and the drain region 205g of the seventh transistor T7 through the via hole VH14 , that is, the node N4 in FIG. 4 is drawn upward.
  • the seventh conductive member 77 located in the fourth conductive layer 7 and the first conductive member 81 located in the fifth conductive layer 8 are electrically connected through via holes.
  • An anode of the organic light emitting diode 100 may be electrically connected to the first conductive member 81 through a via hole. In this way, the source of the sixth transistor T6 and the drain of the seventh transistor T7 can be electrically connected to the anode of the organic light emitting diode 100 .
  • the orthographic projection of the first plate C1a of the first capacitor on the base substrate is located in the first direction X in the same direction as the orthographic projection of the sixth conductive member 76 on the base substrate.
  • the sixth conductive component 76 is between Any two of the orthographic projection on the base substrate and the orthographic projection of the seventh conductive member 77 on the base substrate are arranged at intervals.
  • the orthographic projection of the second plate C1b of the first capacitor on the substrate partially overlaps the orthographic projection of the seventh conductive member 77 on the substrate.
  • the orthographic projection of the first voltage line V1 on the substrate covers the orthographic projection of the fourth conductive member 74 on the substrate; and/or, the first voltage line V1 is
  • the orthographic projection on the base substrate covers the orthographic projection of the active layer of the eighth transistor T8 on the base substrate.
  • the display substrate may include a first semiconductor layer 2 disposed on the base substrate 1 and a first gate insulating layer 107 disposed on a side of the first semiconductor layer 2 away from the base substrate 1 .
  • the first gate insulating layer 107 may be formed of silicon oxide and have a thickness of about 1000 ⁇ 2000 angstroms.
  • the display substrate may include a first conductive layer 3 disposed on the side of the first gate insulating layer 107 away from the base substrate 1 and a first interlayer dielectric layer 108 disposed on the side of the first conductive layer 3 away from the base substrate 1 .
  • the first insulating interlayer 108 may be formed of silicon nitride and have a thickness of about 1000 ⁇ 2000 angstroms.
  • the display substrate may include a second conductive layer 4 disposed on the side of the first interlayer dielectric layer 108 away from the base substrate 1 and a second interlayer dielectric layer disposed on the side of the second conductive layer 4 away from the base substrate 1 109.
  • the second interlayer dielectric layer 109 may be formed of insulating materials such as silicon nitride.
  • the display substrate may include a buffer layer 110 disposed on the side of the second interlayer dielectric layer 109 away from the base substrate 1; a second semiconductor layer 5 disposed on the side of the buffer layer 110 away from the base substrate 1; The second semiconductor layer 5 is away from the second gate insulating layer 116 on the side of the substrate 1 .
  • the display substrate may include a third conductive layer 6 disposed on the side of the second gate insulating layer 116 away from the base substrate 1; a third interlayer dielectric layer 111 disposed on the side of the third conductive layer 6 away from the base substrate 1 ; the fourth conductive layer 7 arranged on the side of the third interlayer dielectric layer 111 away from the substrate 1; the first planarization layer 112 arranged on the side of the fourth conductive layer 7 away from the substrate 1; arranged on the first The planarization layer 112 is away from the fifth conductive layer 8 on the side of the base substrate 1; the second planarization layer 113 arranged on the side of the fifth conductive layer 8 away from the base substrate 1; the second planarization layer 113 is arranged on the side away from the substrate an anode layer 208 on one side of the substrate 1 ; and a pixel defining layer 114 disposed on a side of the anode layer 208 away from the base substrate 1 .
  • the planarization layer may be formed of polyimide (PI).
  • PI polyimide
  • At least some embodiments of the present disclosure also provide a display panel including the display substrate as described above.
  • the display panel may be an OLED display panel.
  • the display device may include the display substrate as described above.
  • the display device may include any device or product with a display function.
  • the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio Players, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic clothing, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smart watches), televisions, etc.

Abstract

提供一种显示基板、显示面板和显示装置。所述显示基板包括：设置于衬底基板的第一半导体层；设置于第一半导体层远离衬底基板一侧的第一导电层；和设置于第一导电层远离衬底基板一侧的第二导电层。显示基板还包括设置于衬底基板的像素驱动电路，像素驱动电路包括驱动电路、存储电路和复位电路，复位电路与驱动电路的第一端电连接，用于在初始化阶段，对驱动电路的第一端的电位进行初始化，驱动电路用于在其控制端的电位的控制下，控制驱动电路的第一端与驱动电路的第二端之间连通，储能电路与驱动电路的控制端电连接，用于储存电能；复位电路包括第一电容，存储电路包括第二电容，第一电容的第一极板和第一电容的第二极板在衬底基板上的正投影重叠部分的面积小于第二电容的第一极板和第二电容的第二极板在衬底基板上的正投影重叠部分的面积。

Description

显示基板、显示面板和显示装置 技术领域
本公开涉及显示技术领域，并且具体地涉及一种显示基板、显示面板和显示装置。
背景技术
有机发光二极管(缩写为OLED)显示装置是一类使用发光的OLED来显示图像等信息的显示装置。OLED显示装置具有诸如低功耗、高亮度和高响应速度的特性。低温多晶硅氧化物薄膜晶体管(Low Temperature Poly-Oxide TFT，以下简称LTPO TFT)技术是近年来新兴的薄膜晶体管技术。从理论上讲，LTPO TFT相比传统的低温多晶硅薄膜晶体管(Low Temperature Poly-Silicon TFT，以下简称LTPS TFT)技术而言，可以节省5-15％的电量，让整块显示屏幕的功耗更低。
在本部分中公开的以上信息仅用于对本公开的技术构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示基板，其中，所述显示基板包括：衬底基板；
设置于所述衬底基板的第一半导体层；
设置于所述第一半导体层远离所述衬底基板一侧的第一导电层；和
设置于所述第一导电层远离所述衬底基板一侧的第二导电层；
其中，所述显示基板还包括设置于所述衬底基板的像素驱动电路，所述像素驱动电路包括驱动电路、存储电路和复位电路，所述复位电路与所述驱动电路的第一端或所述驱动电路的第二端电连接，用于在初始化阶段，对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化，所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，所述储能电路与所述驱动电路的控制端电连接，用于储存电能；
所述复位电路包括第一电容，所述存储电路包括第二电容，所述第一电容包括相对设置的第一极板和第二极板，所述第二电容包括相对设置的第一极板和第二极板， 所述第一电容的第一极板和所述第二电容的第一极板位于所述第一导电层，所述第一电容的第二极板和所述第二电容的第二极板位于所述第二导电层，所述第一电容的第一极板和所述第二电容的第一极板在所述衬底基板上的正投影间隔设置，所述第一电容的第二极板和所述第二电容的第二极板在所述衬底基板上的正投影间隔设置，所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影至少部分重叠，所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影至少部分重叠，所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影重叠部分的面积小于所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影重叠部分的面积，所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影重叠部分的面积与所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影重叠部分的面积的比值在5～20的范围内。
根据一些示例性的实施例，所述显示基板还包括设置于所述衬底基板的第一发光控制线，所述第一发光控制线用于给所述像素驱动电路供给第一发光控制信号；所述第一发光控制线位于所述第一导电层中，所述第一发光控制线与所述第一电容的第二极板重叠的部分构成所述第一电容的第一极板。
根据一些示例性的实施例，所述像素驱动电路包括第一发光控制电路和第二发光控制电路，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管，所述第五晶体管包括第五栅极，所述第六晶体管包括第六栅极，所述第一发光控制线施加第一发光控制信号给所述第五栅极、所述第六栅极和所述第一电容的第一极板。
根据一些示例性的实施例，所述第一发光控制线的与所述第一半导体层重叠的一部分构成所述第五栅极，所述第一发光控制线的与所述第一半导体层重叠的另一部分构成所述第六栅极，所述第一发光控制线还包括加宽部，所述加宽部沿第一方向位于所述第五栅极和所述第六栅极之间，所述加宽部沿第二方向的尺寸大于所述第五栅极和所述第六栅极中的每一个沿第二方向的尺寸，其中，所述第一发光控制线沿所述第一方向延伸，所述第二方向与所述第一方向相交；以及所述加宽部的至少一部分构成所述第一电容的第一极板。
根据一些示例性的实施例，所述第一电容的第二极板在所述衬底基板上的正投影 覆盖所述加宽部在所述衬底基板上的正投影；和/或
所述第二电容的第一极板在所述衬底基板上的正投影的面积大于所述加宽部在所述衬底基板上的正投影的面积；和/或，
所述第二电容的第二极板在所述衬底基板上的正投影的面积大于所述第一电容的第二极板在所述衬底基板上的正投影的面积。
根据一些示例性的实施例，所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影重叠部分的面积与所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影重叠部分的面积的比值在8～10的范围内。
根据一些示例性的实施例，所述第二电容的第二极板包括通孔，所述通孔暴露所述第二电容的第一极板的至少一部分，所述第一电容的第二极板在所述衬底基板上的正投影的面积与所述通孔在所述衬底基板上的正投影的面积的比值在1.1～5的范围内。
根据一些示例性的实施例，所述显示基板还包括位于所述第一导电层中的发光元件复位线和设置于所述衬底基板的发光元件，所述像素驱动电路包括第二初始化电路，所述第二初始化电路用于在所述发光元件复位线提供的信号的控制下，对所述发光元件的第一极进行初始化。
根据一些示例性的实施例，所述显示基板还包括位于所述第一导电层中的复位控制线，所述像素驱动电路包括第一初始化电路，所述第一初始化电路用于在所述复位控制线提供的复位控制信号的控制下，对所述驱动电路进行初始化；以及所述发光元件复位线提供的信号的频率高于所述复位控制线提供的复位控制信号的频率。
根据一些示例性的实施例，所述显示基板还包括位于所述第一导电层中的发光元件复位线和设置于所述衬底基板的发光元件，所述像素驱动电路包括第二初始化电路，所述第二初始化电路包括第七晶体管，所述发光元件复位线与所述第一半导体层重叠的部分构成所述第七晶体管的第七栅极；以及所述第一电容的第一极板在所述衬底基板上的正投影在第二方向上位于所述第二电容的第一极板在所述衬底基板上的正投影与所述发光元件复位线在所述衬底基板上的正投影之间。
根据一些示例性的实施例，所述像素驱动电路包括第一晶体管，所述复位控制线与所述第一半导体层重叠的部分构成所述第一晶体管的第一栅极；以及所述第一栅极与所述第一电容的第一极板之间在第一方向上的间距小于所述第七栅极与所述第一电容的第一极板之间在第一方向上的间距。
根据一些示例性的实施例，所述显示基板还包括位于所述第二导电层中的一条第二发光控制线，所述一条第二发光控制线、所述第二电容的第二极板和所述第一电容的第二极板在所述衬底基板上的正投影沿第二方向间隔设置；以及所述第一电容的第二极板在所述衬底基板上的正投影与所述一条第二发光控制线在所述衬底基板上的正投影在第二方向上分别位于所述第二电容的第二极板在所述衬底基板上的正投影的两侧。
根据一些示例性的实施例，所述显示基板还包括：设置于所述第二导电层远离所述衬底基板一侧的第二半导体层；以及设置于所述第二半导体层远离所述衬底基板一侧的第三导电层，所述第二半导体层包括氧化物半导体材料；所述显示基板包括位于所述第三导电层中的另一条第二发光控制线，所述一条第二发光控制线和所述另一条第二发光控制线电连接；所述像素驱动电路包括通断控制电路，所述通断控制电路包括第八晶体管，所述一条第二发光控制线与所述第二半导体层重叠的部分构成所述第八晶体管的底栅，所述另一条第二发光控制线与所述第二半导体层重叠的部分构成所述第八晶体管的顶栅。
根据一些示例性的实施例，所述显示基板还包括设置于所述第三导电层远离所述衬底基板一侧的第四导电层，所述驱动电路包括第三晶体管；以及所述显示基板包括位于所述第四导电层中的第五导电部件，所述第五导电部件的一端通过第一过孔与第一电容的第二极板电连接，所述第五导电部件的另一端通过第二过孔与所述第三晶体管的第一极电连接。
根据一些示例性的实施例，所述显示基板包括位于所述第四导电层中的第六导电部件，所述第六导电部件包括第一部分、第二部分和第三部分；以及所述第六导电部件的第一部分通过第三过孔与第五晶体管的第一极电连接，所述第六导电部件的第二部分通过第四过孔与第二电容的第二极板电连接。
根据一些示例性的实施例，所述显示基板还包括设置于所述第四导电层远离所述衬底基板一侧的第五导电层，所述显示基板还包括设置于所述第五导电层中的第一电压线；以及所述第六导电部件的第三部分通过第五过孔与第一电压线电连接。
根据一些示例性的实施例，所述显示基板包括位于所述第四导电层中的第七导电部件，所述第七导电部件与所述第六晶体管的第一极电连接；以及所述第一电容的第一极板在所述衬底基板上的正投影在第一方向上位于所述第六导电部件在所述衬底基 板上的正投影与所述第七导电部件在所述衬底基板上的正投影之间，并且，所述第一电容的第一极板在所述衬底基板上的正投影、所述第六导电部件在所述衬底基板上的正投影和所述第七导电部件在所述衬底基板上的正投影中的任意两者均间隔设置。
根据一些示例性的实施例，所述第一电容的第二极板在所述衬底基板上的正投影与所述第七导电部件在所述衬底基板上的正投影部分重叠。
根据一些示例性的实施例，所述显示基板包括位于所述第四导电层中的第四导电部件，所述第四导电部件的一端通过第六过孔与第八晶体管的第一极电连接，所述第四导电部件的另一端通过第七过孔和通孔与第三晶体管的第三栅极电连接。
根据一些示例性的实施例，所述第一电压线在所述衬底基板上的正投影覆盖所述第四导电部件在所述衬底基板上的正投影；和/或，所述第一电压线在所述衬底基板上的正投影覆盖第八晶体管的有源层在所述衬底基板上的正投影。
在另一方面，提供一种显示面板，包括如上所述的显示基板。
在又一方面，提供一种显示装置，包括如上所述的显示基板或如上所述的显示面板。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加明显。
图1是根据本公开的一些实施例的显示装置的平面示意图；
图2是根据本公开的一些实施例的显示装置包括的显示基板的平面示意图；
图3是根据本公开的一些实施例的像素驱动电路的结构框图；
图4是根据本公开的一些实施例的像素驱动电路的等效电路图；
图5是图4所示的像素驱动电路的至少一实施例的工作时序图；
图6A和图6B分别是根据本公开的一些示例性实施例的发光元件复位线提供的信号的示意图；
图7是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层的平面结构的示意图；
图8是示出根据本公开的示例性实施例的像素驱动电路的第一导电层的平面结构的示意图；
图9是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层和第一导电层的组合的平面结构的示意图；
图10是示出根据本公开的示例性实施例的像素驱动电路的第二导电层的平面结构的示意图；
图11是示出根据本公开的示例性实施例的像素驱动电路的第二半导体层的平面结构的示意图；
图12是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层和第二半导体层的组合的平面结构的示意图；
图13是示出根据本公开的示例性实施例的像素驱动电路的第三导电层的平面结构的示意图；
图14是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层的组合的平面结构的示意图；
图15是示出在图14的结构上形成的绝缘层中的过孔的示意图；
图16是示出在图15的结构上形成的绝缘层中的过孔的示意图；
图17是示出根据本公开的示例性实施例的像素驱动电路的第四导电层的平面结构的示意图；
图18是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层和第四导电层的组合的平面结构的示意图；
图19是示出根据本公开的示例性实施例的像素驱动电路的第五导电层的平面结构的示意图；
图20是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层的组合的平面结构的示意图；
图21是示意性示出第一电容和第二电容的相对面积的平面图；
图22是示出根据本公开的一些示例性实施例的显示基板的沿图20中的线AA’截取的截面结构的示意图；以及
图23是使用图6B所示的高频信号时发光元件的发光效果图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在......之间”对“直接在......之间”、“相邻”对“直接相邻”或“在......上”对“直接在......上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果 图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
在本文中，术语“基本上”、“大约”、“近似”、“大致”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±30％、±20％、±10％、±5％内。
需要说明的是，在本文中，表示“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同一层”的多个元件、部件、结构和/或部分由相同的材料构成，并且通过同一次构图工艺形成，通常，位于“同一层”的多个元件、部件、结构和/或部分具有大致相同的厚度。
本领域技术人员应该理解，在本文中，除非另有说明，表述“高度”或“厚度”指的是沿垂直于显示基板设置的各个膜层的表面的尺寸，即沿显示基板的出光方向的尺寸，或称为沿显示装置的法线方向的尺寸。
在本文中，表述“晶体管”可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开的实施例至少提供一种显示基板。所述显示基板包括：衬底基板；设置于所述衬底基板的第一半导体层；设置于所述第一半导体层远离所述衬底基板一侧的第一导电层；和设置于所述第一导电层远离所述衬底基板一侧的第二导电层；其中，所述显示基板还包括设置于所述衬底基板的像素驱动电路，所述像素驱动电路包括驱动电路、存储电路和复位电路，所述复位电路与所述驱动电路的第一端或所述驱动电路的第二端电连接，用于在初始化阶段，对所述驱动电路的第一端的电位或所述驱动电 路的第二端的电位进行初始化，所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，所述储能电路与所述驱动电路的控制端电连接，用于储存电能；所述复位电路包括第一电容，所述存储电路包括第二电容，所述第一电容包括相对设置的第一极板和第二极板，所述第二电容包括相对设置的第一极板和第二极板，所述第一电容的第一极板和所述第二电容的第一极板位于所述第一导电层，所述第一电容的第二极板和所述第二电容的第二极板位于所述第二导电层，所述第一电容的第一极板和所述第二电容的第一极板在所述衬底基板上的正投影间隔设置，所述第一电容的第二极板和所述第二电容的第二极板在所述衬底基板上的正投影间隔设置，所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影至少部分重叠，所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影至少部分重叠，所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影重叠部分的面积小于所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影重叠部分的面积。在本公开的实施例中，所述像素驱动电路在工作时，在数据电压写入驱动电路之前，在初始化阶段，复位电路对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化，能够改善所述驱动电路的磁滞现象，解决低频状态下，因驱动晶体管磁滞导致的残像、闪烁等现象。
图1是根据本公开的一些实施例的显示装置的平面示意图。例如，所述显示装置可以是OLED显示装置。参照图1，显示装置1000可以包括显示面板1100、栅极驱动器1200、数据驱动器1300、控制器1400和电压发生器1500。显示面板1100可以包括阵列基板1000和多个像素PX，阵列基板1000可以包括显示区AA和非显示区NA，多个像素PX以阵列形式排布在显示区AA中。栅极驱动器1200产生的信号可以通过例如扫描信号线GL的信号线施加给像素PX，数据驱动器1300产生的信号可以通过例如数据线DL的信号线施加给像素PX。例如VDD的第一电压和例如VSS的第二电压可以被施加至像素PX。例如VDD的第一电压可以高于例如VSS的第二电压。可选地，例如VDD的第一电压可以施加至发光元件(例如OLED)的阳极，并且例如VSS的第二电压可以施加至发光元件的阴极，使得发光元件可以发光。
例如，每一个像素PX可以包括多个子像素，例如，红色子像素、绿色子像素和蓝色子像素，或者可以包括白色子像素、红色子像素、绿色子像素和蓝色子像素。
图2是根据本公开的一些实施例的显示装置包括的显示基板的平面示意图。例如，所述显示基板可以是用于OLED显示面板的阵列基板。
参照图2，所述显示基板可以包括显示区域AA和非显示区域NA。例如，所述显示区域AA与所述非显示区域NA可以包括多个边界，如图2中所示的AAS1、AAS2、AAS3和AAS4。所述显示基板还可以包括位于所述非显示区域NA内的驱动器。例如，该驱动器可以位于显示区域AA的至少一侧。在图2所示的实施例中，驱动器分别位于显示区域AA的左侧和右侧。需要说明的是，其中的左侧和右侧可以为在显示时，人眼观看的显示基板(屏幕)的左侧和右侧。所述驱动器可以用于驱动显示基板中的各个像素进行显示。例如，所述驱动器可以包括上述栅极驱动器1200和数据驱动器1300。数据驱动器1300用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示基板的各条数据线上。栅极驱动器1200通常由移位寄存器实现，移位寄存器将时钟信号转换成开启/关断电压，分别输出到显示基板的各条扫描信号线上。
需要说明的是，虽然图2中示出驱动器位于显示区域AA的左侧和右侧，但是，本公开的实施例不局限于此，驱动电路可以位于非显示区域NA任何合适的位置。
例如，所述驱动器可以采用GOA技术，即Gate Driver on Array。在GOA技术中，将栅极驱动电路直接设置于阵列基板上，以代替外接驱动芯片。每个GOA单元作为一级移位寄存器，每级移位寄存器与一条栅线连接，通过各级移位寄存器依序轮流输出开启电压，实现像素的逐行扫描。在一些实施例中，每级移位寄存器也可以与多条栅线连接。这样，可以适应显示基板高分辨率、窄边框的发展趋势。
参照图2，在所述显示基板上，设置有左侧GOA电路DA1、位于显示区域AA中的多个像素P、右侧GOA电路DA2。左侧GOA电路DA1和右侧GOA电路DA2分别通过信号线电连接到显示IC上，由显示IC控制GOA信号的供给，显示IC例如设置在显示基板的下侧(人眼观看的方向)。左侧GOA电路DA1和右侧GOA电路DA2还分别通过信号线(例如扫描信号线GL)电连接到各个像素，以供应驱动信号给各个像素。
需要说明的是，图中示例性的示出了子像素在衬底基板上的正投影的形状为圆角矩形，但是，本公开的实施例不局限于此，例如，子像素在衬底基板上的正投影的形状可以为矩形、六边形、五边形、正方形、圆形等其他形状。而且，一个像素单元中 的3个子像素的排列方式也不局限于图1和图2中所示的方式。
结合参照图1和图2，每一个像素单元PX可以包括多个子像素，例如，第一子像素SP1、第二子像素SP2和第三子像素SP3。为了方便理解，可以将第一子像素SP1、第二子像素SP2和第三子像素SP3分别描述为红色子像素、绿色子像素和蓝色子像素，但是，本公开的实施例不局限于此。
所述多个子像素沿行方向X和列方向Y成阵列地设置于衬底基板1上。需要说明的是，虽然在图示的实施例中，行方向X和列方向Y相互垂直，但是，本公开的实施例不局限于此。
应该理解，在本公开的实施例中，每一个子像素包括像素驱动电路和发光元件。例如，所述发光元件可以为OLED发光元件，包括层叠设置的阳极、发光层和阴极。所述像素驱动电路可以包括多个薄膜晶体管和至少一个存储电容器。
图3是根据本公开的一些实施例的像素驱动电路的结构框图，图4是根据本公开的一些实施例的像素驱动电路的等效电路图。需要说明的是，在下面的说明中，以8T2C像素驱动电路为例，对所述像素驱动电路的结构进行详细描述，但是，本公开的实施例并不局限于8T2C像素驱动电路，在不冲突的情况下，其它已知的像素驱动电路结构都可以应用于本公开的实施例中。
如图3所示，根据本公开实施例的像素驱动电路用于驱动发光元件100，所述像素驱动电路包括驱动电路110和复位电路220；所述复位电路220与所述驱动电路110的第一端电连接，用于在初始化阶段，对所述驱动电路110的第一端的电位进行初始化。所述驱动电路110用于在其控制端的电位的控制下，控制所述驱动电路110的第一端与所述驱动电路110的第二端之间连通。
在本公开实施例中，所述像素驱动电路在工作时，在数据电压写入驱动电路之前，在初始化阶段，复位电路对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化，以能够改善所述驱动晶体管的磁滞现象，解决低频状态下，因驱动晶体管磁滞导致的残像、闪烁等现象。
继续参照图3，所述像素驱动电路还包括第一发光控制电路310和第二发光控制电路320。
所述第一发光控制电路310分别与第一发光控制线E1、所述驱动电路11的第一端和第一电压线V1电连接，用于在所述第一发光控制线E1提供的第一发光控制信号 的控制下，控制所述驱动电路11的第一端与所述第一电压线V1之间连通。
所述第二发光控制电路320与第二发光控制线E2、所述驱动电路11的第二端与所述的所述发光元件100的第一极电连接，用于在第二发光控制线E2提供的第二发光控制信号的控制下，控制所述驱动电路110的第二端与所述发光元件100的第一极之间连通。
所述发光元件100的第二极与第二电压线V2电连接。
在本公开的实施例中，所述像素驱动电路在工作时，在发光阶段，所述第一发光控制电路310在第一发光控制信号的控制下，控制所述驱动电路110的第一端与所述第一电压线V1之间连通，所述第二发光控制电路320在第二发光控制信号的控制下，控制所述驱动电路110的第二端与所述发光元件100的第一极之间连通。
参照图3和图4，所述像素驱动电路还包括复位电路20，所述复位电路20可以包括第一电容C1，第一电容C1可以包括第一极板C1a和第二极板C1b。
第一电容C1的第一极板与第一发光控制线E1电连接，第一电容C1的第二极板与所述驱动电路11的第一端电连接。
在图4中，标号为N1的为与驱动电路11的控制端电连接的第一节点，标号为N2的为与驱动电路11的第一端电连接的第二节点，标号为N3的为驱动电路11的第二端电连接的第三节点。
在本公开的实施例中，所述像素驱动电路在工作时，在初始化阶段，E1提供的发光控制信号的电位由低电压Vgl变为高电压Vgh，N2处于浮空状态，N2的电位随着第一电容C1的第一极板的电位的变化而变化，N2的电位变为V1+Vgh-Vgl，此时驱动电路110中的驱动晶体管的栅源电压小于Vth(Vth为驱动晶体管的阈值电压)，所述驱动晶体管处于导通偏置状态，减少N2因浮空造成的磁滞。
在本公开的实施例中，所述像素驱动电路在工作时，在数据写入之前，驱动晶体管处于导通偏置状态，确保每个像素驱动电路中的驱动晶体管都是从导通偏置状态开始充电和补偿的，而不受上一帧数据电压的影响，可以消除驱动晶体管的磁滞的影响，改善残像和响应时间。
继续参照图3和图4，所述像素驱动电路还可以包括储能电路210、数据写入电路530、补偿控制电路520、通断控制电路510、第一初始化电路410和第二初始化电路420。所述储能电路210与所述驱动电路11的控制端电连接，用于储存电能。所述数 据写入电路530分别与扫描线S1、数据线D1和所述驱动电路110的第一端电连接，用于在扫描线S1提供的扫描信号的控制下，控制将所述数据线D1上的数据电压写入所述驱动电路110的第一端。所述通断控制电路510分别与扫描线S1、所述驱动电路110的控制端和连接节点N0电连接，用于在扫描信号的控制下，控制所述驱动电路110的控制端与所述连接节点N0之间连通。所述补偿控制电路520分别与扫描线S1、所述连接节点N0与所述驱动电路110的第二端电连接，用于在扫描线S1提供的扫描信号的控制下，控制所述连接节点N0与所述驱动电路110的第二端之间连通。所述第一初始化电路410分别与复位控制线R1、第一初始电压线Vi1和所述连接节点N0电连接，用于在复位控制线R1提供的复位控制信号的控制下，将第一初始电压线提供的第一初始电压写入所述连接节点N0。所述第二初始化电路420分别与发光元件复位线R2、第二初始电压线Vi2和所述发光元件100的第一极电连接，用于在所述发光元件复位线R2提供的复位控制信号的控制下，将第二初始电压线提供的第二初始电压写入所述发光元件10的第一极。
在本公开的实施例中，所述像素驱动电路在工作时，显示周期可以包括先后设置的初始化阶段、数据写入阶段和发光阶段。
在初始化阶段，所述通断控制电路510在扫描信号的控制下，控制所述驱动电路110的控制端与所述连接节点N0之间连通，所述第一初始化电路410在复位控制信号的控制下，将第一初始电压写入所述连接节点N0，以将第一初始电压写入所述驱动电路110的控制端；所述第二初始化电路420在所述发光元件复位线R2提供的复位控制信号的控制下，将第二初始电压线Vi2提供的第二初始电压写入所述发光元件100的第一极，以控制发光元件100不发光，并清除所述发光元件100的第一极残留的电荷。
在数据写入阶段，所述数据写入电路530在扫描信号的控制下，控制将所述数据线D1上的数据电压写入所述驱动电路110的第一端，所述补偿控制电路520在扫描信号的控制下，控制所述连接节点N0与所述驱动电路110的第二端之间连通。在数据写入阶段开始时，驱动电路110中的驱动晶体管打开，以通过所述数据电压为储能电路充电，改变驱动电路110的控制端的电位，直至驱动晶体管关断。
在发光阶段，所述第一发光控制电路310在第一发光控制信号的控制下，控制所述驱动电路110的第一端与所述第一电压线V1之间连通，所述第二发光控制电路320在第二发光控制信号的控制下，控制所述驱动电路110的第二端与所述发光元件100 的第一极之间连通，驱动电路110驱动发光元件100发光。
例如，在图4所示的实施例中，所述复位电路220包括第一电容C1；所述第一发光控制电路310包括第五晶体管T5，所述第二发光控制电路320包括第六晶体管T6；所述通断控制电路510包括第八晶体管T8；所述第二初始化电路420包括第七晶体管T7；所述第一初始化电路410包括第一晶体管T1，所述补偿控制电路520包括第二晶体管T2，所述数据写入电路530包括第四晶体管T4，所述驱动电路110包括驱动晶体管T3，所述储能电路210包括第二电容C2；所述发光元件为有机发光二极管100。
第一电容C1的第一极板与所述发光控制线E1电连接，第一电容C1的第二极板与节点N2电连接，即，第一电容C1的第二极板与第五晶体管T5的第二极、第三晶体管T3的第一极电连接。
第二电容C2的第一极板与节点N1电连接，第二电容C2的第二极板与所述第一电压线电连接。
第一晶体管T1的栅极与复位控制线R1电连接，第一晶体管T1的第一极与第一初始电压线Vi1电连接，第一晶体管T1的第二极与节点N0电连接。例如，所述第一初始电压线Vi1用于提供第一初始电压。
第二晶体管T2的栅极与扫描线S1电连接，第二晶体管T2的第二极与节点N3电连接，第二晶体管T2的第一极与节点N0电连接，即，第二晶体管T2的第一极与第一晶体管T1的第二极、第八晶体管T8的第一极电连接。
第三晶体管T3的栅极与节点N1电连接，第三晶体管T3的第一极与节点N2电连接，第三晶体管T3的第二极与节点N3电连接。
第四晶体管T4的栅极与扫描线S1电连接，第四晶体管T4的第一极与数据线D1电连接，第四晶体管T4的第二极与节点N2电连接。
第五晶体管T5的栅极与发光控制线E1电连接，第五晶体管T5的第一极与第一电压线V1电连接，第五晶体管T5的第二极与第三晶体管T3的第一极电连接。流入，所述第一电压线用于提供高电压VDD。
第六晶体管T6的栅极与发光控制线E1电连接；第六晶体管T6的第一极与节点N3电连接，即，第六晶体管T6的第一极与第三晶体管T3的第二极、第二晶体管T2的第二极电连接；第六晶体管T6的第二极与有机发光二极管100的阳极电连接。
第七晶体管T7的栅极与发光元件复位线R2电连接，第七晶体管T7的第一极与 第二初始电压线Vi2电连接，第七晶体管T7的第二极与节点N4电连接，即，第七晶体管T7的第二极与第六晶体管T6的第一极、有机发光二极管100的阳极电连接。例如，所述第二初始电压线Vi2用于提供第二初始电压。关于发光元件复位线R2提供的信号，将在下文中进一步详细描述。
第八晶体管T8的栅极与第二发光控制线E2电连接，第八晶体管T8的第一极与节点N0电连接，第八晶体管T8的第二极与节点N1电连接。
有机发光二极管100的阳极与节点N4电连接，有机发光二极管100的阴极与第二电压线电连接，所述第二电压线用于提供低电压VSS。
在本公开的实施例中，第一发光控制线E1施加第一发光控制信号给第五晶体管T5的栅极、第六晶体管T6的栅极和所述第一电容C1的第一极板C1a。
在本公开的实施例中，Vi2可以与Vi1相同，也可以与Vi2不同。
在本公开的实施例中，第八晶体管T8可以为氧化物薄膜晶体管，其他晶体管T1～T7可以为低温多晶硅薄膜晶体管。但本公开的实施例不以此为限。
在本公开所述的像素驱动电路的至少一实施例中，Vi1的电压值可以大于或等于-6V而小于或等于-2V，例如，Vi1的电压值可以为-2V、-3V、-4V、-5V或-6V等，但不以此为限；
晶体管的阈值电压Vth可以大于或等于-5V而小于或等于-0.5V；例如，Vth可以为-2.5V或-3V等；
第一电压线提供的高电压VDD的电压值可以大于或等于3V而小于或等于6V，例如，VDD的电压值可以为4.6V；但不以此为限；
高电压VDD的电压值的绝对值可以大于Vth的绝对值的1.5倍，例如，VDD的电压值的绝对值可以为Vth的绝对值的1.6倍、1.8倍、2倍等。
可选的，第二电压线提供的低电压VSS的电压值可以大于或等于-6V而小于或等于-3V；例如，VSS的电压值可以为-5V、-4V或-3V。
在本公开至少一实施例中，Vi2的电压值可以大于或等于-7V而小于或等于0V。例如，所述第二初始化电压的电压值可以为-6V、-5V、-4V、-3V或-2V；但不以此为限。
可选的，Vi2的电压值与VSS的电压值之间的电压差值需要小于发光元件的启亮电压，以使得当发光元件的第一极接入Vi2时，发光元件不发光。
图5是图4所示的像素驱动电路的至少一实施例的工作时序图。结合参照图3至图5，根据本公开实施例的像素驱动电路在工作时，显示周期可以包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3。
在初始化阶段t1，第一发光控制线E1提供的发光控制信号的电位由低电压Vgl转换为高电压Vgh，复位控制线R1提供低电压信号，第二发光控制线E2提供高电压信号，扫描线S1提供高电压信号，晶体管T6和T4打开，将Vi1写入节点N1，节点N2的电位变为VDD+(Vgh-Vgl)，此时晶体管T3的栅源电压小于晶体管T3的阈值电压Vth，晶体管T3处于导通偏置状态；晶体管T5打开，Vi2写入有机发光二极管100的阳极，有机发光二极管100不发光，并清除有机发光二极管100的阳极残留的电荷。
在数据写入阶段t2，复位控制线R1提供高电压信号，第二发光控制线E2提供高电压信号，扫描线S1提供低电压信号，第一发光控制线E1提供高电压信号，晶体管T2、T4和T8打开，数据线D1上的数据电压Vdata写入节点N2，节点N1与N3之间连通，通过Vdata为第二电容C2充电，以改变晶体管T3的栅极的电位，直至晶体管T3关断，晶体管T3的栅极的电位变为Vdata+Vth。
在发光阶段t3，复位控制线R1提供高电压信号，第二发光控制线E2提供低电压信号，扫描线S1提供高电压信号，第一发光控制线E1提供低电压信号，晶体管T3、T5和T6打开，晶体管T3驱动有机发光二极管100发光，此时有机发光二极管100的发光电流为0.5K(Vdata-VDD) 2；其中，K为晶体管T3的电流系数。
在本公开的实施例中，第一发光控制线E1提供的第一发光控制信号的脉宽可以与第二发光控制线E2提供的第二发光控制信号的脉宽相同，或者，第一发光控制线E1提供的第一发光控制信号的脉宽可以比第二发光控制线E2提供的第二发光控制信号的脉宽多预定时间。
当第一发光控制线E1提供的第一发光控制信号的脉宽可以与第二发光控制线E2提供的第二发光控制信号的脉宽相同时，可能会出现在初始化阶段，晶体管T5和T6不能正确的关断的情况。基于此，在本公开至少一实施例中，第一发光控制线E1提供的第一发光控制信号的脉宽可以比第二发光控制线E2提供的第二发光控制信号的脉宽多预定时间，所述预定时间可以小于或等于0.5H，1H为一行扫描时间。这样，在进行初始化时，在所述第一发光控制信号的控制下，晶体管T5和T6关断，以断开第 一电压线与晶体管T3的第一极之间的连接，并断开晶体管T3的第二极与有机发光二极管100的阳极之间的连接，使得有机发光二极管100不发光，以不影响发光。
在本公开的实施例中，所述通断控制电路包括的晶体管T8可以为氧化物薄膜晶体管。这样，可以减少驱动电路的控制端的漏电，能够在低频工作时保证驱动电路的控制端的电压的稳定性，利于提升显示质量，提升显示均一性，减轻Flicker(闪烁)。
在本公开的实施例中，晶体管T7可以由单独的GOA控制，该单独的GOA与所述发光元件复位线R2电连接，使得有机发光二极管100可以按照60Hz的频率复位。
图6A和图6B分别是根据本公开的一些示例性实施例的发光元件复位线提供的信号的示意图。结合参照图6A和图6B，在本公开的实施例中，所述发光元件复位线R2提供的信号可以是高频信号。例如，所述发光元件复位线R2提供的信号的频率可以高于所述复位控制线R1提供的复位控制信号的频率。图6B中所示的发光元件复位线R2提供的信号的频率高于图6A中所示的发光元件复位线R2提供的信号的频率。在图6A所示的实施例中，发光元件复位线R2提供的信号的频率基本等于所述复位控制线R1提供的复位控制信号的频率。
图23是使用图6B所示的高频信号时发光元件的发光效果图。参照图23，通过提高发光元件复位线R2提供的信号的频率，可以增加发光元件的阳极复位的刷新频率，使得发光元件的刷新阶段和保持阶段的亮度建立时间保持一致。这样，可以减少发光保持阶段的低分量，减少肉眼可见的亮度变化，改善闪烁水平，同时，可以减少负载降低功耗。
需要说明的是，在本公开的实施例中，各个薄膜晶体管T1、T2、T3、T4、T5、T6、T7和T8可以是p沟道场效应晶体管，但是，本公开的实施例不局限于此，各个薄膜晶体管T1、T2、T3、T4、T5、T6、T7和T8中的至少一些可以是n沟道场效应晶体管。
图7是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层的平面结构的示意图。图8是示出根据本公开的示例性实施例的像素驱动电路的第一导电层的平面结构的示意图。图9是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层和第一导电层的组合的平面结构的示意图。图10是示出根据本公开的示例性实施例的像素驱动电路的第二导电层的平面结构的示意图。图11是示出根据本公开的示例性实施例的像素驱动电路的第二半导体层的平面结构的示意图。图12是示出根据本 公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层和第二半导体层的组合的平面结构的示意图。图13是示出根据本公开的示例性实施例的像素驱动电路的第三导电层的平面结构的示意图。图14是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层的组合的平面结构的示意图。图15是示出在图14的结构上形成的绝缘层中的过孔的示意图。图16是示出在图15的结构上形成的绝缘层中的过孔的示意图。图17是示出根据本公开的示例性实施例的像素驱动电路的第四导电层的平面结构的示意图。图18是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层和第四导电层的组合的平面结构的示意图。图19是示出根据本公开的示例性实施例的像素驱动电路的第五导电层的平面结构的示意图。图20是示出根据本公开的示例性实施例的像素驱动电路的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层的组合的平面结构的示意图。图21是示意性示出第一电容和第二电容的相对面积的平面图。图22是示出根据本公开的一些示例性实施例的显示基板的沿图20中的线AA’截取的截面结构的示意图。
结合参照图7至图22，所述显示基板包括衬底基板1以及设置于所述衬底基板1上的多个膜层。在一些实施例中，所示多个膜层至少包括第一半导体层2、第一导电层3、第二导电层4、第二半导体层5、第三导电层6、第四导电层7和第五导电层8。第一半导体层2、第一导电层3、第二导电层4、第二半导体层5、第三导电层6、第四导电层7和第五导电层8依次远离衬底基板1设置。
例如，第一半导体层2可以由诸如低温多晶硅的半导体材料形成，其膜层厚度可以在400～800埃的范围内，例如500埃。第二半导体层5可以由氧化物半导体材料形成，例如IGZO等多晶硅氧化物半导体材料，其膜层厚度可以在300～600埃的范围内，例如400埃。第一导电层3、第二导电层4和第三导电层6可以由形成薄膜晶体管的栅极的导电材料形成，例如该导电材料可以为Mo，其膜层厚度可以在2000～3000埃的范围内，例如2500埃。第四导电层7和第五导电层8可以由形成薄膜晶体管的源极和漏极的导电材料形成，例如该导电材料可以包括Ti、Al等，第四导电层7和第五导电层8可以具有由Ti/Al/Ti形成的叠层结构，其膜层厚度可以在7000～9000埃的范围内。例如，在第四导电层7和第五导电层8具有由Ti/Al/Ti形成的叠层结构的情况下， Ti/Al/Ti每一层的厚度可以分别为约500埃、5500埃和500埃。
在本公开的实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7可沿着如图7中所示的第一半导体层2形成。第八晶体管T8可沿着如图12中所示的第二半导体层5形成。
如图7所示，第一半导体层2可具有弯曲或弯折形状，并且可包括对应于第一晶体管T1的第一有源层20a、对应于第二晶体管T2的第二有源层20b、对应于第三晶体管T3的第三有源层20c、对应于第四晶体管T4的第四有源层20d、对应于第五晶体管T5的第五有源层20e、对应于第六晶体管T6的第六有源层20f和对应于第七晶体管T7的第七有源层20g。
例如，第一半导体层2可以包括多晶硅，诸如低温多晶硅材料。每一个晶体管的有源层可以包括沟道区、源极区和漏极区。沟道区可不进行掺杂或掺杂类型与源极区、漏极区不同，并因此具有半导体特性。源极区和漏极区分别位于沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可根据TFT是N型还是P型晶体管而变化。
第一晶体管T1包括第一有源层20a和第一栅极G1。第一有源层20a包括第一源极区203a、第一漏极区205a以及连接第一源极区203a和第一漏极区205a的第一沟道区201a。第一源极区203a和第一漏极区205a相对于第一沟道区201a在相对的两个方向上延伸。
第二晶体管T2包括第二有源层20b和第二栅极G2。第二有源层20b包括第二源极区203b、第二漏极区205b以及连接第二源极区203b和第二漏极区205b的第二沟道区201b。第二源极区203b和第二漏极区205b相对于第二沟道区201b在相对的两个方向上延伸。
第三晶体管T3包括第三有源层20c和第三栅极G3。第三有源层20c包括第三源极区203c、第三漏极区205c以及连接第三源极区203c和第三漏极区205c的第三沟道区201c。第三源极区203c和第三漏极区205c相对于第三沟道区201c在相对的两个方向上延伸。
第四晶体管T4包括第四有源层20d和第四栅极G4。第四有源层20d包括第四源极区203d、第四漏极区205d以及连接第四源极区203d和第四漏极区205d的第四沟道区201d。第四源极区203d和第四漏极区205d相对于第四沟道区201d在相对的两个方向上延伸。
第五晶体管T5包括第五有源层20e和第五栅极G5。第五有源层20e包括第五源极区203e、第五漏极区205e以及连接第五源极区203e和第五漏极区205e的第五沟道区201e。第五源极区203e和第五漏极区205e相对于第五沟道区201e在相对的两个方向上延伸。
第六晶体管T6包括第六有源层20f和第六栅极G6。第六有源层20f包括第六源极区203f、第六漏极区205f以及连接第六源极区203f和第六漏极区205f的第六沟道区201f。第六源极区203f和第六漏极区205f相对于第六沟道区201f在相对的两个方向上延伸。
第七晶体管T7包括第七有源层20g和第七栅极G7。第七有源层20g包括第七源极区203g、第七漏极区205g以及连接第七源极区203g和第七漏极区205g的第七沟道区201g。第七源极区203g和第七漏极区205g相对于第七沟道区201g在相对的两个方向上延伸。
参照图7，位于第一半导体层2中的结构21、22为相邻子像素的有源层的部分，也就是说，图7中主要示出的是一个子像素的有源层的部分。
如图8和图9所示，复位控制线R1、扫描线S1、第一发光控制线E1和发光元件复位线R2均位于第一导电层3中。第一导电结构CG1也位于第一导电层3中。第一导电结构CG1与第一半导体层2重叠的部分形成第三晶体管T3的第三栅极G3。复位控制线R1与第一半导体层2重叠的部分形成第一晶体管T1的第一栅极G1。扫描线S1与第一半导体层2重叠的一部分形成第二晶体管T2的第二栅极G2，扫描线S1与第一半导体层2重叠的另一部分形成第四晶体管T4的第四栅极G4。第一发光控制线E1与第一半导体层2重叠的一部分形成第五晶体管T5的第五栅极G5。第一发光控制线E1与第一半导体层2重叠的另一部分形成第六晶体管T6的第六栅极G6。发光元件复位线R2与第一半导体层2重叠的部分形成第七晶体管T7的第七栅极G7。
第一导电结构CG1也形成第二电容C2的一个极板，例如第一极板C2a。即，第一导电结构CG1同时用作第三晶体管T3的栅极和第二电容C2的一个极板。
第一发光控制线E1具有加宽部E1W，该加宽部E1W位于第五栅极G5与第六栅极G6之间。如图9所示，在第一发光控制线E1的延伸方向上，即，在第一方向X上，该加宽部E1W位于第五栅极G5与第六栅极G6之间。加宽部E1W沿第二方向Y的尺寸大于第一发光控制线E1的其他部分沿第二方向Y的尺寸。所述加宽部E1W沿第 二方向Y的尺寸大于所述第五栅极G5和所述第六栅极G6中的每一个沿第二方向Y的尺寸，其中，所述第一发光控制线E1沿所述第一方向X延伸，所述第二方向Y与所述第一方向X相交。例如，所述第二方向Y垂直于所述第一方向X。
例如，所述第一电容的第一极板C1a在所述衬底基板上的正投影在第二方向Y上位于所述第二电容的第一极板C2a在所述衬底基板上的正投影与所述发光元件复位线R2在所述衬底基板上的正投影之间。
如图9所示，所述第一栅极G1与所述第一电容的第一极板C1a之间在第一方向X上的间距PD1小于所述第七栅极G7与所述第一电容的第一极板C1a之间在第一方向X上的间距PD2。需要说明的是，此处的所述第一栅极G1与所述第一电容的第一极板C1a之间在第一方向X上的间距PD1可以用第一栅极G1在第一方向X上的中线与第一电容的第一极板C1a在第一方向X上的中线之间的距离表示，同样地，第七栅极G7与所述第一电容的第一极板C1a之间在第一方向X上的间距PD2可以用第七栅极G7在第一方向X上的中线与所述第一电容的第一极板C1a在第一方向X上的中线之间的距离表示。
如图10所示，第二发光控制线E2位于第二导电层4中。第一电容C1的第二极板C1b和第二电容C2的第二极板C2b也位于第二导电层4中。
例如，第一电容C1的第二极板C1b和第一发光控制线E1的加宽部E1W在衬底基板上的正投影至少部分重叠，所述第一发光控制线E1与第一电容C1的第二极板C1b重叠的部分形成第一电容C1的第一极板C1a。也就是说，所述加宽部E1W的至少一部分构成第一电容C1的第一极板C1a。
例如，第二电容C2的第二极板C2b和第一导电结构CG1在衬底基板上的正投影至少部分重叠，所述第一导电结构CG1与第二电容C2的第二极板C2b重叠的部分形成第二电容C2的第二极板C2a。
如图21所示，示意性示出了第一电容C1的第一极板C1a和第二极板C1b的重叠部分在衬底基板上的正投影，以及第二电容C2的第一极板C2a和第二极板C2b的重叠部分在衬底基板上的正投影。
在本公开的实施例中，所述第一电容的第二极板C1b在所述衬底基板上的正投影基本覆盖所述加宽部E1W在所述衬底基板上的正投影，所述第二电容的第一极板C2a在所述衬底基板上的正投影的面积大于所述加宽部E1W在所述衬底基板上的正投影 的面积。
在本公开的实施例中，位于第一导电层3中的第一极板C1a和位于第二导电层4中的第二极板C1b相对设置。应该理解，在第一导电层3与第二导电层4之间形成有绝缘层或介电层。这样，在位于第一导电层3中的第一极板C1a和位于第二导电层4中的第二极板C1b之间形成第一电容C1。同样地，在位于第一导电层3中的第一极板C2a和位于第二导电层4中的第二极板C2b之间形成第二电容C2。
如图21所示，第一电容C1的第一极板C1a和第二极板C1b的重叠部分在衬底基板上的正投影的面积小于第二电容C2的第一极板C2a和第二极板C2b的重叠部分在衬底基板上的正投影的面积。这样，第一电容C1的电容值小于第二电容C2的电容值。例如，第二电容C2的电容值与第一电容C1的电容值的比值可以在5～20的范围内，例如，在5～10的范围内，或者，在8～10的范围内，在8～9的范围内。在本公开的实施例中，通过设置第一电容的电容值，使得第一电容可以维持节点N2处的电位恒定，这样，即使当驱动信号的频率改变时，也可以通过控制驱动晶体管的第一极处的电压来防止闪烁和/或重影。同时，第二电容C2的电容值设置得较大，能够提高显示面板的性能，降低显示面板的功耗。在本公开的实施例中，通过将第二电容C2的电容值与第一电容C1的电容值的比值可以在5～20的范围内，特别是在8～10的范围内，有利于提高驱动晶体管的稳定性，当驱动频率改变时，显示装置可以通过控制驱动晶体管的第一极处的电压来防止闪烁和/或重影。
参照图10和图12，第二极板C2b包括通孔4H，通孔4H暴露第一导电结构CG1的一部分，以有利于第三晶体管T3的第三栅极G3与其他部件的电连接。
例如，通孔4H暴露所述第二电容的第一极板C2a的至少一部分。例如，所述第一电容的第二极板C1b在所述衬底基板上的正投影的面积与所述通孔4H在所述衬底基板上的正投影的面积的比值在1.1～5的范围内。即，所述第一电容的第二极板C1b在所述衬底基板上的正投影的面积略大于所述通孔4H在所述衬底基板上的正投影的面积。
如图9至图12所示，形成第一极板C1a的第一发光控制线E1的加宽部E1W在衬底基板上的正投影具有大致矩形的形状，第二极板C 1b在衬底基板上的正投影具有大致矩形的形状。此处的“大致矩形”包括矩形、具有至少一个倒角的矩形、具有至少一个圆角的矩形等形状。
如图10所示，一条第二发光控制线42位于第二导电层4中。
例如，所述一条第二发光控制线42、所述第二电容的第二极板C2b和所述第一电容的第二极板C1b在所述衬底基板上的正投影沿第二方向Y间隔设置。所述第一电容的第二极板C1b在所述衬底基板上的正投影与所述一条第二发光控制线42在所述衬底基板上的正投影在第二方向上分别位于所述第二电容的第二极板C2b在所述衬底基板上的正投影的两侧。
如图11所示，第二半导体层5包括对应于第八晶体管T8的第八有源层20h。例如，第八晶体管T8的第八有源层20h基本沿图中的第二方向Y延伸。第八有源层20h包括第八源极区203h、第八漏极区205h以及连接第八源极区203h和第八漏极区205h的第八沟道区201h。第八源极区203h和第八漏极区205h相对于第八沟道区201h在相对的两个方向上延伸。
例如，第二半导体层5可以包括氧化物半导体材料，诸如低温多晶硅氧化物半导体材料(缩写为LTPO)。每一个晶体管的有源层可以包括沟道区、源极区和漏极区。沟道区可不进行掺杂或掺杂类型与源极区、漏极区不同，并因此具有半导体特性。源极区和漏极区分别位于沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可根据TFT是N型还是P型晶体管而变化。
如图13所示，另一条第二发光控制线62位于第三导电层6中。例如，一条第二发光控制线42和另一条第二发光控制线62均可以传输第二发光控制信号。在一些示例中，一条第二发光控制线42和另一条第二发光控制线62可以在显示基板的周边区域中电连接，从而形成所示第二发光控制线E2。
参照图12，一条第二发光控制线42与第二导电层4重叠的部分形成第八晶体管T8的底栅G81，另一条第二发光控制线62与第二导电层4重叠的部分形成第八晶体管T8的顶栅G82。即，第八晶体管T8具有双栅结构。在本公开的实施例中，将第八晶体管T8设置为氧化物半导体晶体管，且第八晶体管T8具有双栅结构，有利于降低节点N1的漏电流，从而有利于节点N1的电位稳定。
参照图13，第一初始电压线Vi1位于第三导电层6中。即，第二发光控制线E2的一部分和第一初始电压线Vi1位于同一层中。在本公开的实施例中，通过在第三导电层6中设置第二发光控制线E2，可以为第八晶体管T8提供单独的发光控制信号。
参照图17，所述显示基板还包括位于第四导电层7中的第二初始电压线Vi2和多 个导电部件，例如，所述多个导电部件可以包括第一导电部件71、第二导电部件72、第三导电部件73、第四导电部件74、第五导电部件75、第六导电部件76和第七导电部件77。
参照图19，所述显示基板还包括位于第五导电层8中的数据线D1、第一电压线V1和第一导电构件81。
参照图15至图20，示意性示出了多个过孔。第一导电部件71的一端通过过孔VH2与第一晶体管T1的源极区203a电连接。第一导电部件71的另一端通过过孔VH1与第一初始电压线Vi1电连接。通过这样的方式，第一晶体管T1的源极电连接至第一初始电压线Vi1。这样，第一初始电压可以施加给第一晶体管T1的源极。
第二导电部件72的一端通过过孔VH3与第四晶体管T4的源极区203d电连接，第二导电部件72的另一端通过过孔VH4与数据线D1电连接。通过这样的方式，第四晶体管T4的源极电连接至数据线D1。这样，数据信号可以施加给第四晶体管T4的源极。
第三导电部件73的一端通过过孔VH5与第二晶体管T2的源极区203b电连接，第三导电部件73的另一端通过过孔VH6与第八晶体管T8的漏极区205h电连接。通过这样的方式，可以将第二晶体管T2的源极和第八晶体管T8的漏极电连接。
第四导电部件74的一端通过过孔VH7与第八晶体管T8的源极区203h电连接，第四导电部件74的另一端通过过孔VH8和通孔4H与第三栅极G3电连接。通过这样的方式，形成图4中所示的节点N1，将第八晶体管T8的源极、第三栅极G3和第二电容C2的一个极板C2a电连接。
例如，过孔VH8在衬底基板上的正投影落入通孔4H在衬底基板上的正投影内，这样，通过过孔VH8和通孔4H暴露下方的第三栅极G3的一部分，从而有利于实现第三栅极G3与第八晶体管T8的源极的电连接。
第五导电部件75的一端通过过孔VH10与第一电容的一个极板C1b电连接，第五导电部件75的另一端通过过孔VH9与第四晶体管T4的漏极区205d和第三晶体管T3的漏极区205c电连接。通过这样的方式，形成图4中所示的节点N2，将第四晶体管T4的漏极、第三晶体管T3的漏极和第一电容C1的一个极板C1b电连接。第六导电部件76的第一部分通过过孔VH11与第五晶体管T5的漏极区205e电连接，第六导电部件76的第二部分通过过孔VH12与第二电容C2的一个极板C2b电连接，第六导电 部件76的第三部分通过过孔VH13与第一电压线V1电连接。通过这样的方式，可以将高电压VDD施加给第五晶体管T5的漏极和第二电容C2的极板C2b。
参照图17，第五导电部件75在衬底基板上的正投影位于第四导电部件74在衬底基板上的正投影与第六导电部件76在衬底基板上的正投影之间。
例如，第六导电部件76可以包括第一部分和第二部分，所述第一部分在衬底基板上的正投影具有反L形状，所述第二部分在衬底基板上的正投影具有近似矩形、六边形或八边形的形状。第六导电部件76的第一部分和第二部分相互连接形成一个整体结构。
例如，第五导电部件75在衬底基板上的正投影和第二电容C2的第一极板和第二极板在衬底基板上的正投影均重叠。这样，在发光阶段，第二电容C2的一个极板连接低电位，使得N1节点的电位可以进一步拉低，有利于发光显示。
在本公开的实施例中，第七导电部件77通过过孔VH14与第六晶体管T6的源极区203f和第七晶体管T7的漏极区205g电连接，即将图4中的节点N4向上引出。位于第四导电层7中的第七导电部件77和位于第五导电层8中的第一导电构件81通过过孔电连接。有机发光二极管100的阳极可以通过过孔与第一导电构件81电连接。通过这样的方式，可以将第六晶体管T6的源极和第七晶体管T7的漏极与有机发光二极管100的阳极电连接。
例如，所述第一电容的第一极板C1a在所述衬底基板上的正投影在第一方向X上位于所述第六导电部件76在所述衬底基板上的正投影与所述第七导电部件77在所述衬底基板上的正投影之间，并且，所述第一电容的第一极板C1a在所述衬底基板上的正投影、所述第六导电部件76在所述衬底基板上的正投影和所述第七导电部件77在所述衬底基板上的正投影中的任意两者均间隔设置。所述第一电容的第二极板C1b在所述衬底基板上的正投影与所述第七导电部件77在所述衬底基板上的正投影部分重叠。
例如，所述第一电压线V1在所述衬底基板上的正投影覆盖所述第四导电部件74在所述衬底基板上的正投影；和/或，所述第一电压线V1在所述衬底基板上的正投影覆盖第八晶体管T8的有源层在所述衬底基板上的正投影。
下面，将结合平面图(例如图7至图20)和截面图(图22)描述根据本公开实施例的显示基板的其他膜层(例如绝缘层)。
在示例性的实施例中，所述显示基板可以包括设置在衬底基板1上的第一半导体层2和设置在第一半导体层2远离衬底基板1一侧的第一栅绝缘层107。例如，第一栅绝缘层107可以由氧化硅形成，具有约1000～2000埃的厚度。
所述显示基板可以包括设置在第一栅绝缘层107远离衬底基板1一侧的第一导电层3和设置在第一导电层3远离衬底基板1一侧的第一层间介质层108。例如，第一层间绝缘层108可以由氮化硅形成，具有约1000～2000埃的厚度。
所述显示基板可以包括设置在第一层间介质层108远离衬底基板1一侧的第二导电层4和设置在第二导电层4远离衬底基板1一侧的第二层间介质层109。例如，第二层间介质层109可以由氮化硅等绝缘材料形成。
所述显示基板可以包括设置在第二层间介质层109远离衬底基板1一侧的缓冲层110；设置在缓冲层110远离衬底基板1一侧的第二半导体层5；和设置在第二半导体层5远离衬底基板1一侧的第二栅绝缘层116。
所述显示基板可以包括设置在第二栅绝缘层116远离衬底基板1一侧的第三导电层6；设置在第三导电层6远离衬底基板1一侧的第三层间介质层111；设置在第三层间介质层111远离衬底基板1一侧的第四导电层7；设置在第四导电层7远离衬底基板1一侧的第一平坦化层112；设置在第一平坦化层112远离衬底基板1一侧的第五导电层8；设置在第五导电层8远离衬底基板1一侧的第二平坦层113；设置在第二平坦化层113远离衬底基板1一侧的阳极层208；和设置在阳极层208远离衬底基板1一侧的像素界定层114。
例如，所述平坦化层可以由聚酰亚胺(PI)形成。
本公开的至少一些实施例还提供一种显示面板，所述显示面板包括如上所述的显示基板。例如，所述显示面板可以是OLED显示面板。
参照图1，本公开的至少一些实施例还提供一种显示装置。该显示装置可以包括如上所述的显示基板。
所述显示装置可以包括任何具有显示功能的设备或产品。例如，所述显示装置可以是智能电话、移动电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴设备(例如头戴式设备、电子服饰、电子手环、电子项链、电子配饰、电子纹身、或智能手表)、电视机等。
应该理解，根据本公开实施例的显示面板和显示装置具有上述显示基板的所有特点和优点，具体可以参见上文的描述，在此不再赘述。
虽然本公开的总体技术构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离所述总体技术构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (22)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板；
    设置于所述衬底基板的第一半导体层；
    设置于所述第一半导体层远离所述衬底基板一侧的第一导电层；和
    设置于所述第一导电层远离所述衬底基板一侧的第二导电层；
    其中，所述显示基板还包括设置于所述衬底基板的像素驱动电路，所述像素驱动电路包括驱动电路、存储电路和复位电路，所述复位电路与所述驱动电路的第一端或所述驱动电路的第二端电连接，用于在初始化阶段，对所述驱动电路的第一端的电位或所述驱动电路的第二端的电位进行初始化，所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，所述储能电路与所述驱动电路的控制端电连接，用于储存电能；
    所述复位电路包括第一电容，所述存储电路包括第二电容，所述第一电容包括相对设置的第一极板和第二极板，所述第二电容包括相对设置的第一极板和第二极板，所述第一电容的第一极板和所述第二电容的第一极板位于所述第一导电层，所述第一电容的第二极板和所述第二电容的第二极板位于所述第二导电层，所述第一电容的第一极板和所述第二电容的第一极板在所述衬底基板上的正投影间隔设置，所述第一电容的第二极板和所述第二电容的第二极板在所述衬底基板上的正投影间隔设置，所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影至少部分重叠，所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影至少部分重叠，所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影重叠部分的面积小于所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影重叠部分的面积，所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影重叠部分的面积与所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影重叠部分的面积的比值在5～20的范围内。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还包括设置于所述衬底基板的第一发光控制线，所述第一发光控制线用于给所述像素驱动电路供给第一发光 控制信号；
    所述第一发光控制线位于所述第一导电层中，所述第一发光控制线与所述第一电容的第二极板重叠的部分构成所述第一电容的第一极板。
  3. 根据权利要求2所述的显示基板，其中，所述像素驱动电路包括第一发光控制电路和第二发光控制电路，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管，所述第五晶体管包括第五栅极，所述第六晶体管包括第六栅极，所述第一发光控制线施加第一发光控制信号给所述第五栅极、所述第六栅极和所述第一电容的第一极板。
  4. 根据权利要求3所述的显示基板，其中，所述第一发光控制线的与所述第一半导体层重叠的一部分构成所述第五栅极，所述第一发光控制线的与所述第一半导体层重叠的另一部分构成所述第六栅极，所述第一发光控制线还包括加宽部，所述加宽部沿第一方向位于所述第五栅极和所述第六栅极之间，所述加宽部沿第二方向的尺寸大于所述第五栅极和所述第六栅极中的每一个沿第二方向的尺寸，其中，所述第一发光控制线沿所述第一方向延伸，所述第二方向与所述第一方向相交；以及
    所述加宽部的至少一部分构成所述第一电容的第一极板。
  5. 根据权利要求4所述的显示基板，其中，所述第一电容的第二极板在所述衬底基板上的正投影覆盖所述加宽部在所述衬底基板上的正投影；和/或
    所述第二电容的第一极板在所述衬底基板上的正投影的面积大于所述加宽部在所述衬底基板上的正投影的面积；和/或，
    所述第二电容的第二极板在所述衬底基板上的正投影的面积大于所述第一电容的第二极板在所述衬底基板上的正投影的面积。
  6. 根据权利要求1-5中任一项所述的显示基板，其中，所述第二电容的第一极板和所述第二电容的第二极板在所述衬底基板上的正投影重叠部分的面积与所述第一电容的第一极板和所述第一电容的第二极板在所述衬底基板上的正投影重叠部分的面积的比值在8～10的范围内。
  7. 根据权利要求6所述的显示基板，其中，所述第二电容的第二极板包括通孔，所述通孔暴露所述第二电容的第一极板的至少一部分，所述第一电容的第二极板在所述衬底基板上的正投影的面积与所述通孔在所述衬底基板上的正投影的面积的比值在1.1～5的范围内。
  8. 根据权利要求1-5中任一项所述的显示基板，其中，所述显示基板还包括位于所述第一导电层中的发光元件复位线和设置于所述衬底基板的发光元件，所述像素驱动电路包括第二初始化电路，所述第二初始化电路用于在所述发光元件复位线提供的信号的控制下，对所述发光元件的第一极进行初始化。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板还包括位于所述第一导电层中的复位控制线，所述像素驱动电路包括第一初始化电路，所述第一初始化电路用于在所述复位控制线提供的复位控制信号的控制下，对所述驱动电路进行初始化；以及
    所述发光元件复位线提供的信号的频率高于所述复位控制线提供的复位控制信号的频率。
  10. 根据权利要求1-5中任一项所述的显示基板，其中，所述显示基板还包括位于所述第一导电层中的发光元件复位线和设置于所述衬底基板的发光元件，所述像素驱动电路包括第二初始化电路，所述第二初始化电路包括第七晶体管，所述发光元件复位线与所述第一半导体层重叠的部分构成所述第七晶体管的第七栅极；以及
    所述第一电容的第一极板在所述衬底基板上的正投影在第二方向上位于所述第二电容的第一极板在所述衬底基板上的正投影与所述发光元件复位线在所述衬底基板上的正投影之间。
  11. 根据权利要求10所述的显示基板，其中，所述像素驱动电路包括第一晶体管，所述复位控制线与所述第一半导体层重叠的部分构成所述第一晶体管的第一栅极；以及
    所述第一栅极与所述第一电容的第一极板之间在第一方向上的间距小于所述第七栅极与所述第一电容的第一极板之间在第一方向上的间距。
  12. 根据权利要求1-5中任一项所述的显示基板，其中，所述显示基板还包括位于所述第二导电层中的一条第二发光控制线，所述一条第二发光控制线、所述第二电容的第二极板和所述第一电容的第二极板在所述衬底基板上的正投影沿第二方向间隔设置；以及
    所述第一电容的第二极板在所述衬底基板上的正投影与所述一条第二发光控制线在所述衬底基板上的正投影在第二方向上分别位于所述第二电容的第二极板在所述衬底基板上的正投影的两侧。
  13. 根据权利要求12所述的显示基板，其中，所述显示基板还包括：设置于所述第二导电层远离所述衬底基板一侧的第二半导体层；以及设置于所述第二半导体层远离所述衬底基板一侧的第三导电层，所述第二半导体层包括氧化物半导体材料；
    所述显示基板包括位于所述第三导电层中的另一条第二发光控制线，所述一条第二发光控制线和所述另一条第二发光控制线电连接；
    所述像素驱动电路包括通断控制电路，所述通断控制电路包括第八晶体管，所述一条第二发光控制线与所述第二半导体层重叠的部分构成所述第八晶体管的底栅，所述另一条第二发光控制线与所述第二半导体层重叠的部分构成所述第八晶体管的顶栅。
  14. 根据权利要求13所述的显示基板，其中，所述显示基板还包括设置于所述第三导电层远离所述衬底基板一侧的第四导电层，所述驱动电路包括第三晶体管；以及
    所述显示基板包括位于所述第四导电层中的第五导电部件，所述第五导电部件的一端通过第一过孔与第一电容的第二极板电连接，所述第五导电部件的另一端通过第二过孔与所述第三晶体管的第一极电连接。
  15. 根据权利要求13所述的显示基板，其中，所述显示基板包括位于所述第四导电层中的第六导电部件，所述第六导电部件包括第一部分、第二部分和第三部分；以及
    所述第六导电部件的第一部分通过第三过孔与第五晶体管的第一极电连接，所述第六导电部件的第二部分通过第四过孔与第二电容的第二极板电连接。
  16. 根据权利要求15所述的显示基板，其中，所述显示基板还包括设置于所述第四导电层远离所述衬底基板一侧的第五导电层，所述显示基板还包括设置于所述第五导电层中的第一电压线；以及
    所述第六导电部件的第三部分通过第五过孔与第一电压线电连接。
  17. 根据权利要求13所述的显示基板，其中，所述显示基板包括位于所述第四导电层中的第七导电部件，所述第七导电部件与所述第六晶体管的第一极电连接；以及
    所述第一电容的第一极板在所述衬底基板上的正投影在第一方向上位于所述第六导电部件在所述衬底基板上的正投影与所述第七导电部件在所述衬底基板上的正投影之间，并且，所述第一电容的第一极板在所述衬底基板上的正投影、所述第六导电部件在所述衬底基板上的正投影和所述第七导电部件在所述衬底基板上的正投影中的任意两者均间隔设置。
  18. 根据权利要求17所述的显示基板，其中，所述第一电容的第二极板在所述衬底基板上的正投影与所述第七导电部件在所述衬底基板上的正投影部分重叠。
  19. 根据权利要求13所述的显示基板，其中，所述显示基板包括位于所述第四导电层中的第四导电部件，所述第四导电部件的一端通过第六过孔与第八晶体管的第一极电连接，所述第四导电部件的另一端通过第七过孔和通孔与第三晶体管的第三栅极电连接。
  20. 根据权利要求19所述的显示基板，其中，所述第一电压线在所述衬底基板上的正投影覆盖所述第四导电部件在所述衬底基板上的正投影；和/或，
    所述第一电压线在所述衬底基板上的正投影覆盖第八晶体管的有源层在所述衬底基板上的正投影。
  21. 一种显示面板，包括根据权利要求1-20中任一项所述的显示基板。
  22. 一种显示装置，包括根据权利要求1-20中任一项所述的显示基板或根据权利要求21所述的显示面板。
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