WO2022059482A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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WO2022059482A1
WO2022059482A1 PCT/JP2021/032045 JP2021032045W WO2022059482A1 WO 2022059482 A1 WO2022059482 A1 WO 2022059482A1 JP 2021032045 W JP2021032045 W JP 2021032045W WO 2022059482 A1 WO2022059482 A1 WO 2022059482A1
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Prior art keywords
dielectric film
metal
semiconductor device
manufacturing
film
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English (en)
French (fr)
Japanese (ja)
Inventor
浩二 秋山
知大 田村
フィリップ ゴベール
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to KR1020237007330A priority Critical patent/KR102893655B1/ko
Priority to CN202180061683.XA priority patent/CN116075924A/zh
Priority to JP2022550446A priority patent/JP7550868B2/ja
Priority to KR1020257039751A priority patent/KR20250174993A/ko
Priority to US18/024,971 priority patent/US12349434B2/en
Publication of WO2022059482A1 publication Critical patent/WO2022059482A1/ja
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    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
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    • H10P14/69391—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H10P14/69392—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing hafnium, e.g. HfO2
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Definitions

  • This disclosure relates to a method for manufacturing a semiconductor device.
  • Patent Documents 1 and 2 describe an insulating metal by the ALD (Atomic Layer Deposition) method on a dielectric film serving as a capacitive insulating film or a gate insulating film between a lower electrode and an upper electrode in a semiconductor device manufacturing process.
  • a technique for forming an oxide film is disclosed.
  • the insulating metal oxide film can reduce the leakage current of the dielectric film.
  • the present disclosure provides a technique capable of reducing the leakage current without increasing the capacitance equivalent film thickness (CET) of the dielectric film.
  • the method for manufacturing a semiconductor device includes a step of forming a dielectric film on a semiconductor substrate or a lower electrode formed on the semiconductor substrate, and selectively metal in a predetermined region on the surface of the dielectric film.
  • FIG. 1 is a diagram showing an example of the structure of the semiconductor device according to the embodiment.
  • FIG. 2 is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 3 is a cross-sectional view showing an example of the state of the object to be processed in each step of the method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 4 is a cross-sectional view showing an example of the state of the object to be processed in each step of the method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 5 is a cross-sectional view showing an example of the state of the object to be processed in each step of the method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 6 is a cross-sectional view showing an example of the state of the object to be processed in each step of the method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 7 is a diagram for explaining the details of the metal adhesion step in one embodiment.
  • FIG. 8 is a diagram showing an example of measurement results of CET and leakage current of the dielectric film.
  • FIG. 9 is a diagram showing an example of the structure of the semiconductor device according to the modified example of the embodiment.
  • the present disclosure provides a technique capable of reducing the leakage current without increasing the CET of the dielectric film.
  • FIG. 1 is a diagram showing an example of the structure of a semiconductor device according to an embodiment.
  • the semiconductor device 100 shown in FIG. 1 is a semiconductor device having a MIM (Metal-Insulator-Metal) structure.
  • the semiconductor device 100 includes a semiconductor substrate 101, a lower electrode 203 formed on the semiconductor substrate 101, a dielectric film 102 formed on the lower electrode 203, and an upper electrode 103 formed on the dielectric film 102.
  • the dielectric film 102 is used as a capacitive insulating film between the upper electrode 103 and the lower electrode 203.
  • An insulating metal oxide film 104 is locally formed in a predetermined region on the surface of the dielectric film 102.
  • FIG. 2 is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment.
  • 3 to 6 are cross-sectional views showing an example of the state of the object to be processed in each step of the method for manufacturing a semiconductor device according to an embodiment.
  • the semiconductor substrate 101 on which the lower electrode 203 is formed is provided (step S101).
  • the semiconductor substrate 101 is, for example, a silicon substrate or the like.
  • the lower electrode 203 is, for example, titanium nitride (TiN).
  • the dielectric film 102 is formed on the lower electrode 203 (step S102, see FIG. 3).
  • the dielectric film 102 contains, for example, hafnium oxide (HfO2) or zirconium oxide (ZrO2).
  • the metal 104a is selectively attached to a predetermined region on the surface of the dielectric film 102 (step S103, metal attachment step, see FIG. 4).
  • the metal 104a contains, for example, aluminum (Al) or a pentavalent transition metal.
  • the pentavalent transition metal includes, for example, niobium (Nb) or tantalum (Ta).
  • FIG. 7 is a diagram for explaining the details of the metal adhesion step in one embodiment.
  • the dielectric film 102 includes a crystallized portion C, which is a crystallized portion, and an amorphous portion ⁇ , which is a non-crystallized portion.
  • a crystallized portion C which is a crystallized portion
  • amorphous portion ⁇ which is a non-crystallized portion.
  • At the grain boundaries, which are the boundary surfaces of the crystal portion C an aggregate in which a plurality of oxygen defect Vos are aggregated is formed. A part of the crystal grain boundaries is exposed on the surface of the dielectric film 102.
  • the metal 104a is selectively adhered to the region including the peripheral edge of the crystal grain boundary exposed on the surface of the dielectric film 102 (hereinafter referred to as “grain boundary peripheral region”).
  • the metal adhesion step by performing a plating treatment using electrons conducted through the grain boundaries existing in the dielectric film 102 (for example, electrolytic plating treatment), the grain boundary periphery on the surface of the dielectric film 102 is performed.
  • Metal 104a is selectively attached to the region. That is, at the crystal grain boundaries existing in the dielectric film 102, a path for conducting electrons from the lower electrode 203 to the surface of the dielectric film 102 is formed by an aggregate of oxygen defects Vo.
  • the metal ions in the electrolytic solution are reduced by electrons supplied to the crystal grain boundaries on the surface of the dielectric film 102 by conducting such a path, so that the grain boundaries on the surface of the dielectric film 102 are reduced.
  • Metal 104a is selectively attached to the peripheral region.
  • an insulating metal oxide film 104 is formed in a predetermined region (that is, a grain boundary peripheral region) on the surface of the dielectric film 102 (step S104, see FIG. 5).
  • the metal oxide film 104 is, for example, aluminum oxide (Al2O3), niobium oxide (Nb2O5) or tantalum pentoxide (Ta2O5). From the viewpoint of appropriately growing the metal oxide film 104, the step S104 is preferably performed at a temperature of, for example, 300 ° C. or lower.
  • step S104 for example, when the dielectric film 102 is hafnium oxide (HfO2) and the metal oxide film 104 is niobium oxide (Nb2O5), the following chemical reaction formulas (1) and (2) are used. The chemical reaction to proceed proceeds.
  • HfO2 hafnium oxide
  • Nb2O5 niobium oxide
  • Nb2O5 Nb atoms of niobium oxide
  • HfO2O4 hafnium oxide
  • O atoms of niobium oxide are oxidized. Enter the site of the O atom in the hafnium crystal.
  • two electrons and one O atom are left over.
  • the surplus two electrons and one O atom enter the oxygen defect Vo at the grain boundary on the surface of the hafnium oxide (dielectric film 102).
  • the oxygen defect Vo which is an electron path, disappears near the surface of hafnium oxide (HfO2), and the peripheral edge of the crystal grain boundary on the surface of hafnium oxide is electrically sealed by the metal oxide film 104.
  • the leakage current of the dielectric film 102 can be reduced.
  • the metal oxide film 104 is tantalum oxide (Ta2O5), and as a result, the leakage current of the dielectric film 102 can be reduced.
  • the metal oxide film 104 is aluminum oxide (Al2O3), the covalent bond of the Al—O bond of aluminum oxide is strong and the band gap is large, so that electron tunneling is suppressed, and as a result, the dielectric film 102. Leakage current can be reduced.
  • step S104 unlike the conventional technique of forming a metal oxide film on the entire surface of the dielectric film 102 by the ALD method, metal oxidation is selectively performed only on the grain boundary peripheral region on the surface of the dielectric film 102.
  • the film 104 is formed. This makes it possible to suppress an increase in the CET of the dielectric film 102.
  • the upper electrode 103 is formed on the dielectric film 102 (step S105, see FIG. 6), and the process is completed.
  • the upper electrode 103 is, for example, titanium nitride (TiN).
  • FIG. 8 is a diagram showing an example of the measurement results of the CET and the leak current of the dielectric film 102.
  • FIG. 8 shows the measurement results when the upper electrode 103 of titanium nitride (TiN) is formed on the dielectric film 102 of zirconium oxide (ZrO2).
  • Comparative Example 1 of FIG. 8 shows the result of directly forming the upper electrode 103 on the dielectric film 102 without forming the metal oxide film 104.
  • the result of forming the upper electrode 103 after forming the metal oxide film 104 is shown.
  • the result of forming the upper electrode 103 after forming the metal oxide film 104 is shown.
  • the metal oxide film 104 when the metal oxide film 104 is formed, the increase in CET of the dielectric film 102 is suppressed and the leakage current is reduced as compared with the case where the metal oxide film 104 is not formed. That is, according to the method for manufacturing a semiconductor device according to the embodiment in which the metal oxide film 104 is formed in the grain boundary peripheral region on the surface of the dielectric film 102 prior to the formation of the upper electrode 103, the dielectric film 102 is formed. The leakage current can be reduced without increasing the CET. Further, as can be seen from the result of FIG. 8, when the metal oxide film 104 is formed, the CET of the dielectric film 102 is reduced as compared with the case where the metal oxide film 104 is not formed.
  • the dielectric film 102 is formed. CET can also be reduced.
  • the reason why the CET of the dielectric film 102 is reduced is that the plating treatment forms irregularities based on the oxide of the plated material on the surface of the dielectric film 102 (ZrO2 film), and the effective surface area of the dielectric film 102 is increased. It is considered that the capacity increased with this.
  • FIG. 9 is a diagram showing an example of the structure of the semiconductor device 100A according to the modified example of the embodiment.
  • the semiconductor device 100A shown in FIG. 9 is a semiconductor device having a MOS structure.
  • the semiconductor device 100A has a semiconductor substrate 101, a dielectric film 102 formed on the semiconductor substrate 101, and an upper electrode 103 formed on the dielectric film 102.
  • the dielectric film 102 is used as a gate insulating film.
  • An insulating metal oxide film 104 is locally formed in a predetermined region (that is, a grain boundary peripheral region) on the surface of the dielectric film 102.
  • the upper electrode 103 is used as a gate electrode.
  • the method for manufacturing the semiconductor device 100A according to the modified example provides the semiconductor substrate 101 in the step S101 of the embodiment. Further, in the method for manufacturing the semiconductor device 100A, the dielectric film 102 is formed on the semiconductor substrate 101 in the step S102 of one embodiment. In the method for manufacturing the semiconductor device 100A according to the modified example, the processes from the attachment of the metal 104a (step S103) to the formation of the upper electrode 103 (step S105) are the same as those in one embodiment.
  • the metal oxide film 104 is formed in the grain boundary peripheral region on the surface of the dielectric film 102 prior to the formation of the upper electrode 103. As a result, the leakage current can be reduced without increasing the CET of the dielectric film 102.
  • the method for manufacturing a semiconductor device includes a step of forming a dielectric film on a semiconductor substrate or a lower electrode formed on the semiconductor substrate, and selectively forming a metal in a predetermined region on the surface of the dielectric film.
  • the step of forming an upper electrode on the dielectric film is included. Therefore, according to the embodiment, the leakage current can be reduced without increasing the CET of the dielectric film.
  • the metal in the step of adhering the metal, the metal may be selectively adhered to the region including the peripheral edge of the crystal grain boundary exposed on the surface of the dielectric film. Therefore, according to the embodiment, it is possible to suppress the generation of leakage current on the surface of the dielectric film.
  • the crystal grains exposed on the surface of the dielectric film are subjected to a plating process using electrons conducted through the grain boundaries existing in the dielectric film.
  • Metals may be selectively attached to the region including the periphery of the boundary. Therefore, according to the embodiment, the metal can be accurately adhered only to the peripheral edge of the crystal grain boundary exposed on the surface of the dielectric film.
  • the metal may contain aluminum (Al) or a pentavalent transition metal.
  • the pentavalent transition metal may contain niobium (Nb) or tantalum (Ta).
  • the dielectric film may contain hafnium oxide (HfO2) or zirconium oxide (ZrO2). Therefore, according to the embodiment, the leakage current can be reduced without increasing the CET of the dielectric film by using an insulating metal oxide film formed of aluminum (Al) or a pentavalent transition metal. ..
  • the step of forming the metal oxide film may be performed at a temperature of 300 ° C. or lower. Therefore, according to the embodiment, the metal oxide film can be appropriately grown on the surface of the dielectric film.
  • a step of annealing the metal oxide film under an inert atmosphere is further performed between the step of forming the metal oxide film (step S104) and the step of forming the lower electrode (step S105). It may be included. Further, in this case, the step of annealing the metal oxide film is preferably performed at a temperature of 500 ° C. or lower. As a result, the metal oxide film can be appropriately grown up to the crystal grain boundaries existing in the dielectric film, and as a result, the leakage current can be further reduced.
  • the step of annealing the dielectric film under an inert atmosphere is further included between the step of forming the dielectric film (step S102) and the step of adhering the metal (step S103). But it may be. Further, in this case, the step of annealing the dielectric film is preferably performed at a temperature of 500 ° C. or lower. As a result, the dielectric film can be appropriately crystallized.

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  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
PCT/JP2021/032045 2020-09-15 2021-09-01 半導体装置の製造方法 Ceased WO2022059482A1 (ja)

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JP2022550446A JP7550868B2 (ja) 2020-09-15 2021-09-01 半導体装置の製造方法
KR1020257039751A KR20250174993A (ko) 2020-09-15 2021-09-01 반도체 장치의 제조 방법
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KR20230066333A (ko) 2023-05-15
CN116075924A (zh) 2023-05-05
TW202223988A (zh) 2022-06-16
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US12349434B2 (en) 2025-07-01
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