WO2022048003A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022048003A1
WO2022048003A1 PCT/CN2020/126343 CN2020126343W WO2022048003A1 WO 2022048003 A1 WO2022048003 A1 WO 2022048003A1 CN 2020126343 W CN2020126343 W CN 2020126343W WO 2022048003 A1 WO2022048003 A1 WO 2022048003A1
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Prior art keywords
channel
sub
electrode
film transistor
thin film
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PCT/CN2020/126343
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English (en)
French (fr)
Inventor
卢景怡
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to US15/734,813 priority Critical patent/US11404580B2/en
Publication of WO2022048003A1 publication Critical patent/WO2022048003A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

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  • the present invention relates to the field of display technology, and in particular, to a display panel and a display device.
  • the main pixel electrode needs to be processed by the main pixel thin film transistor.
  • Charge and maintain the potential charge the sub-pixel electrode through the sub-pixel thin film transistor, and at the same time share the thin-film transistor to pull down the potential to ensure that the potential of the sub-pixel is lower than the potential of the main pixel, so as to obtain good transmittance and viewing angle.
  • the brightness of the sub-pixel is proportional to the potential of the sub-pixel. The higher the potential of the sub-pixel, the greater the transmittance of the sub-pixel, and the higher the brightness of the sub-pixel.
  • the potential of the sub-pixel is determined by the impedance ratio of the shared TFT to the sub-TFT.
  • the impedance ratio of the shared TFT to the sub-pixel TFT is the channel width to length ratio of the shared TFT and the sub-TFT.
  • the metal layer needs to be patterned through processes such as exposure, development, and etching to form a source electrode, a drain electrode, and a channel between the source electrode and the drain electrode.
  • a Nikon exposure machine with a multi-lens splicing structure is often used to expose the photoresist, as shown in FIG.
  • the exposure amount of A1 is less than the exposure amount of the non-splicing area A2 of the lens 101, so that the width of both ends of the channel of the sub-thin film transistor and the shared thin-film transistor corresponding to the splicing area A1 produces a change of ⁇ W along the Y-axis direction.
  • Equation 1 (Wb/Lb)/(Wa/La)
  • Equation 2 ((Wb+2 ⁇ W)/(Lb+ ⁇ L))/((Wa+2 ⁇ W)/(La+ ⁇ L))
  • Wa is the width of the channel of the sub-TFT
  • La is the length of the channel
  • Wb is the width of the channel of the shared TFT
  • Lb is the length of the channel.
  • Equation 3 Wb/Wa
  • Equation 4 (Wb+2 ⁇ W)/(Wa+2 ⁇ W).
  • the impedance ratio of the shared TFT corresponding to the splicing area A1 to the sub-TFT is Compared with the non-splicing area A2, it is reduced by 9.2%, which means that the potential of the shared thin film transistor corresponding to the splicing area A1 is less than that of the non-splicing area A2, and the sub-pixels in the sub-pixel unit corresponding to the splicing area A1 The potential of the sub-pixel is higher than the potential of the sub-pixel corresponding to the non-splicing area A2, so that the brightness of the sub-pixel corresponding to the question.
  • the impedance ratio of the shared thin film transistor and the sub-thin film transistor corresponding to the splicing area of the exposure machine lens in the existing display panel is quite different from the impedance ratio of the shared thin film transistor and the sub-thin film transistor corresponding to the non-splicing area, resulting in a large difference in the display panel.
  • the embodiments of the present application provide a display panel and a display device, which are used to solve the problem of the impedance ratio between the shared thin film transistor and the sub-thin film transistor in the pixel structure corresponding to the splicing area of the exposure machine lens in the existing display panel and the pixels corresponding to the non-splicing area.
  • the impedance ratio of the shared thin film transistor and the sub-thin film transistor is quite different, which leads to the problem of uneven brightness of the display panel.
  • An embodiment of the present application provides a display panel, comprising a plurality of sub-pixel units arranged in an array in the display panel, each of the sub-pixel units at least includes a main pixel electrode, a sub-pixel electrode, and is connected to the sub-pixel electrode a first thin film transistor, a second thin film transistor connected to the first thin film transistor, and a third thin film transistor connected to the main pixel electrode, the first thin film transistor includes a first source electrode, a first drain electrode and a a first channel partially located between the first source electrode and the first drain electrode, the second thin film transistor includes a second source electrode, a second drain electrode, and a first channel located between the second source electrode and the first drain electrode a second channel between the second drains;
  • the first sub-channel includes a first sub-channel and a second sub-channel, the first sub-channel is located between the first source electrode and the first drain electrode, and the second sub-channel is located between the first source electrode and the first drain electrode.
  • a channel is located between the first thin film transistor and the second thin film transistor.
  • the sub-pixel unit further includes an auxiliary electrode, the auxiliary electrode is connected to the first source electrode, the second source electrode is connected to the first drain electrode, and the second sub-pixel is connected to the first drain electrode.
  • a channel is located between the auxiliary electrode and the second source electrode.
  • the third thin film transistor includes a third source electrode, a third drain electrode, and a third channel located between the third source electrode and the third drain electrode, and the first Both the sub-channel and the third channel are U-shaped channels, and the opening directions of the first sub-channel and the third channel are opposite to each other.
  • the second sub-channel is a linear channel
  • the auxiliary electrode is arranged in parallel with the second source electrode, and is located at the second source electrode away from the second drain electrode side.
  • the second sub-channel is a U-shaped channel, and the opening direction of the second sub-channel is the same as the opening direction of the first sub-channel.
  • the length of the third channel is equal to the lengths of the first sub-channel and the second sub-channel, and the first sub-channel and the second sub-channel The sum of the widths is less than or equal to the width of the third channel.
  • the length of the second sub-channel is equal to the length of the second sub-channel, and the sum of the widths of the first sub-channel and the second sub-channel is greater than that of the first sub-channel The width of the second channel.
  • the auxiliary electrode is made of the same layer of metal as the first source electrode and the first drain electrode.
  • both the main pixel electrode and the sub-pixel electrode have a 4-domain structure.
  • An embodiment of the present application provides a display device, including a device body and a display panel disposed on the device body, the display panel including a plurality of sub-pixel units arranged in an array in the display panel, each of the sub-pixel units
  • the pixel unit includes at least a main pixel electrode, a sub-pixel electrode, a first thin film transistor connected to the sub-pixel electrode, a second thin film transistor connected to the first thin film transistor, and a third thin film connected to the main pixel electrode transistor
  • the first thin film transistor includes a first source electrode, a first drain electrode and a first channel partially located between the first source electrode and the first drain electrode
  • the second thin film transistor includes a first channel two sources, a second drain, and a second channel between the second source and the second drain;
  • the first sub-channel includes a first sub-channel and a second sub-channel, the first sub-channel is located between the first source electrode and the first drain electrode, and the second sub-channel is located between the first source electrode and the first drain electrode.
  • a channel is located between the first thin film transistor and the second thin film transistor.
  • the sub-pixel unit further includes an auxiliary electrode, the auxiliary electrode is connected to the first source electrode, the second source electrode is connected to the first drain electrode, and the second sub-pixel is connected to the first drain electrode.
  • a channel is located between the auxiliary electrode and the second source electrode.
  • the third thin film transistor includes a third source electrode, a third drain electrode, and a third channel located between the third source electrode and the third drain electrode, and the first Both the sub-channel and the third channel are U-shaped channels, and the opening directions of the first sub-channel and the third channel are opposite to each other.
  • the second sub-channel is a linear channel
  • the auxiliary electrode is arranged in parallel with the second source electrode, and is located at the second source electrode away from the second drain electrode side.
  • the second sub-channel is a U-shaped channel, and the opening direction of the second sub-channel is the same as the opening direction of the first sub-channel.
  • the length of the third channel is equal to the lengths of the first sub-channel and the second sub-channel, and the first sub-channel and the second sub-channel The sum of the widths is less than or equal to the width of the third channel.
  • the length of the second sub-channel is equal to the length of the second sub-channel, and the sum of the widths of the first sub-channel and the second sub-channel is greater than that of the first sub-channel The width of the second channel.
  • the auxiliary electrode is made of the same layer of metal as the first source electrode and the first drain electrode.
  • both the main pixel electrode and the sub-pixel electrode have a 4-domain structure.
  • Embodiments of the present application further provide a display device, including a device body and a display panel disposed on the device body, the display panel including a plurality of sub-pixel units arranged in an array in the display panel, each of the The sub-pixel unit includes at least a main pixel electrode, a sub-pixel electrode, a first thin film transistor connected to the sub-pixel electrode, a second thin film transistor connected to the first thin film transistor, and a third thin film transistor connected to the main pixel electrode a thin film transistor, the first thin film transistor includes a first source electrode, a first drain electrode and a first channel partially located between the first source electrode and the first drain electrode, the second thin film transistor includes a second source, a second drain, and a second channel between the second source and the second drain;
  • the sub-pixel unit further includes an auxiliary electrode, the auxiliary electrode is arranged in parallel with the second source electrode, the first channel includes a first sub-channel and a second sub-channel, the first sub-channel A sub-channel is located between the first source electrode and the first drain electrode, and the second sub-channel is located between the auxiliary electrode and the second source electrode.
  • the third thin film transistor includes a third source electrode, a third drain electrode, and a third channel located between the third source electrode and the third drain electrode, and the first Both the sub-channel and the third channel are U-shaped channels, and the opening directions of the first sub-channel and the third channel are opposite to each other.
  • the first channel of the first thin film transistor is divided into a first sub-channel and a second sub-channel, so that the sub-pixel unit corresponding to the splicing area of the exposure machine lens
  • the variation of the channel width of the first thin film transistor is greater than the variation of the channel width of the second thin film transistor, thereby reducing the variation of the impedance ratio between the second thin film transistor and the first thin film transistor, so that the second thin film transistor corresponding to the splicing area is
  • the difference between the potential of the pixel electrode and the potential of the sub-pixel electrode corresponding to the non-splicing area is reduced, thereby reducing the sub-pixel in the sub-pixel unit corresponding to the splicing area and the sub-pixel in the sub-pixel unit corresponding to the non-splicing area.
  • the difference in brightness improves the problem of uneven brightness of the display panel.
  • Fig. 1 is the structure schematic diagram of exposure machine lens splicing
  • FIG. 2 is a schematic diagram of a first structure of a sub-pixel unit provided by an embodiment of the present application
  • Fig. 3 is the enlarged schematic diagram of part a in Fig. 2;
  • FIG. 4 is a schematic diagram of a second structure of a sub-pixel unit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a sub-pixel unit provided by an embodiment of the present application.
  • the display panel includes a plurality of sub-pixel units 10 arranged in an array in the display panel, each of the sub-pixel units 10 includes a main pixel and a sub-pixel, the main pixel includes a main pixel electrode 11, the sub-pixel includes a sub-pixel electrode 12, and the The main pixel electrode 11 and the sub-pixel electrode 12 are both 4-domain structures, and the sub-pixel unit 10 further includes at least a first thin film transistor 13 connected to the sub pixel electrode 12 and a second thin film transistor 13 connected to the first thin film transistor 13. The thin film transistor 14 and the third thin film transistor 15 connected to the main pixel electrode 11 .
  • the first thin film transistor 13 includes a first source electrode 131 , a first drain electrode 132 , and at least partially located at the first source electrode 131 and the first drain electrode 132 .
  • the first channel 133 between the second thin film transistor 14 includes a second source electrode 141, a second drain electrode 142 and a second channel 143 between the second source electrode 141 and the second drain electrode 142, the second A second semiconductor layer (not shown in the figure) is provided at the channel 143 .
  • the first sub-channel 133 includes a first sub-channel 1331 and a second sub-channel 1332, the first sub-channel 1331 is located between the first source electrode 131 and the first drain electrode 132, and the first sub-channel 1331 is provided with
  • the first sub-semiconductor layer and the second sub-channel 1332 are located between the first thin film transistor 13 and the second thin film transistor 14, and a second sub-semiconductor layer (not shown in the figure) is disposed at the second sub-channel 1332.
  • the first channel 133 is composed of two parts: a first sub-channel 1331 and a second sub-channel 1332, and both the first sub-channel 1331 and the second sub-channel 1332 have an edge along the
  • the two openings extending in the Y-axis direction make the width W4 of the first sub-channel 1331 and the width W5 of the second sub-channel 1332 of the first thin film transistor 13 corresponding to the splicing area A1 of the exposure machine lens along the Y-axis direction
  • the total variation is 2 ⁇ W.
  • the total change of the width W1 of the first channel 133 of the first thin film transistor 13 corresponding to the splicing area A1 along the Y-axis direction is changed from 2 ⁇ W to 4 ⁇ W, and the second thin film transistor 14
  • the variation of the width W2 of the second channel 143 along the Y-axis direction is still 2 ⁇ W.
  • the impedance ratio of the second thin film transistor 14 and the first thin film transistor 13 corresponding to the non-splicing area A2 is: W2/W1
  • the impedance ratio between the second thin film transistor 14 and the first thin film transistor 13 corresponding to the splicing area A1 is: (W2+2 ⁇ W)/(W1+4 ⁇ W).
  • the thin film transistor structure of the display panel Compared with the thin film transistor structure of the existing display panel, the thin film transistor structure of the display panel provided by the embodiment of the present application maintains the original variation of the width W2 of the second channel 143 of the second thin film transistor 14 by increasing the first The variation of the width W1 of the first channel 133 of a thin film transistor 13 can reduce the variation of the channel width ratio of the second thin film transistor 14 and the first thin film transistor 13 corresponding to the lens splicing area A1, thereby reducing the The potential of the sub-pixel electrode 12 corresponding to the splicing area A1 and the sub-pixel electrode 12 corresponding to the non-splicing area A2 are reduced due to the influence of the less exposure in the splicing area A1 on the impedance ratio of the second thin film transistor 14 and the first thin film transistor 13 Therefore, the difference between the brightness of the sub-pixels corresponding to the splicing area A1 and the brightness of the sub-pixels corresponding to the non-splicing area A2 is reduced, and
  • the sub-pixel unit 10 further includes an auxiliary electrode 134, the auxiliary electrode 134 is connected to the first source electrode 131, the second source electrode 141 is connected to the first drain electrode 132, and the second source electrode 141 is connected to the first drain electrode 132.
  • Two sub-channels 1332 are located between the auxiliary electrode 134 and the second source electrode 141 .
  • the third thin film transistor 15 includes a third source electrode 151 , a third drain electrode 152 , a third channel 153 located between the third source electrode 151 and the third drain electrode 152 , and a third channel 153 disposed at the third channel 153 .
  • the third semiconductor layer, the third source electrode 151 is connected to the first source electrode 131 of the first thin film transistor 13, and the third drain electrode 152 is connected to the main pixel electrode 11 for charging the main pixel electrode 11 and maintaining a potential
  • the first drain 132 of the first thin film transistor 13 is connected to the sub-pixel electrode 12 for charging the sub-pixel electrode 12
  • the shared electrode 16 is connected to the second drain 142 of the second thin-film transistor 14 for pulling down the sub-pixel electrode 12 to ensure that the potential of the sub-pixel electrode 12 is lower than the potential of the main pixel electrode 11 .
  • the first thin film transistor 13 , the second thin film transistor 14 and the third thin film transistor 15 are all bottom gate structures, and the gates of the first thin film transistor 13 , the second thin film transistor 14 and the third thin film transistor 15
  • the auxiliary electrodes 134 and the first source electrode 131 , the first drain electrode 132 of the first thin film transistor 13 and the shared electrode 16 connected to the second drain electrode 142 are all arranged in the second metal layer.
  • the first thin film transistor 13 , the second thin film transistor 14 and the third thin film transistor 15 may also be in other forms such as a top gate structure, which is not limited here.
  • the first sub-channel 1331 and the third channel 153 are both U-shaped channels, and the opening directions of the first sub-channel 1331 and the third channel 153 are opposite, and the U-shaped opening of the first sub-channel 1331 faces the sub-pixels For the electrode 12 , the opening of the third channel 153 faces the main pixel electrode 11 .
  • the second sub-channel 1332 is a linear channel, the auxiliary electrode 134 and the second source electrode 141 are arranged in parallel with respect to the Y-axis direction, and the second sub-channel 1332 is located at the second source electrode 141 away from the first One side of the two drains 142 .
  • the length L4 of the first sub-channel 1331 is equal to the length L5 of the second sub-channel 1332, and the sum of the width W4 of the first sub-channel 1331 and the width W5 of the second sub-channel 1332 is the first channel 133 channel width W1.
  • the length L2 of the second channel 143 and the length L3 of the third channel 153 are equal to the lengths of the first sub-channel 1331 and the second sub-channel 1332 .
  • the sum of the widths of the sub-channel 1331 and the second sub-channel 1332 is equal to the width W3 of the third channel 153 .
  • the sum of the widths of the first sub-channel 1331 and the second sub-channel 1332 should be greater than the width W2 of the second channel 143 .
  • the second sub-channel 1332 may also be a U-shaped channel, in this case, the first sub-channel 1332 can be a U-shaped channel.
  • the channel 1331 and the third channel 153 are also U-shaped channels, and the opening directions of the first sub-channel 1331 and the third channel 153 are opposite, and the opening of the first sub-channel 1331 faces the sub-pixel electrode 12.
  • the opening of the triple channel 153 faces the main pixel electrode 11 .
  • the film thickness of the first metal layer where the gate electrode is located may be appropriately increased to increase the resistance of the gate electrode, thereby increasing the resistance of the gate electrode. The influence of the capacitive load in the sub-pixel unit 10 is reduced, and the charging rate of the sub-pixel electrode 12 is guaranteed.
  • the splicing area The impedance ratio between the second thin film transistor 14 and the first thin film transistor 13 corresponding to A1 is reduced by 4.3% compared with the impedance ratio between the second thin film transistor 14 and the first thin film transistor 13 corresponding to the non-splicing area A2, and its impedance ratio
  • the reduction percentage is significantly smaller than the reduction percentage of the impedance ratio of the prior art display panel in the background art.
  • the potential of the sub-pixel in the sub-pixel unit 10 corresponding to the splicing area A1 in the display panel provided by the embodiment of the present application is the same as that of the non-
  • the difference between the potentials of the sub-pixels in the sub-pixel unit 10 corresponding to the splicing area A2 is smaller, which can improve the problem of uneven brightness of the display panel.
  • Table 1 is an electrical simulation table provided by the embodiment of the present application, and provides the electrical simulation results of the display panel before and after the improvement provided by the embodiment of the present application.
  • the data in Table 1 are: actual measurement data.
  • the first channel of the first thin film transistor of the display panel before improvement includes only one channel
  • the first channel 133 of the first thin film transistor 13 of the display panel after improvement includes the first sub-channel 1331 and the first channel
  • the two sub-channels 1332 are divided into two parts, and compared with before the improvement, the preset values of the width W1 and the length L1 of the first channel 133 of the first thin film transistor 13 remain unchanged, and the second channel of the second thin film transistor 14
  • the preset value of the length L2 of 143 remains unchanged, the preset value of the width W2 is increased from 5 ⁇ m to 6 ⁇ m, and the film thickness of the first metal layer where the gate is located is increased from 0.33 ⁇ m to 0.48 ⁇ m.
  • the impedance ratio of 14 to the first thin film transistor 13 is reduced by 7.12%; the impedance ratio of the second thin film transistor 14 to the first thin film transistor 13 corresponding to the splicing area A1 in the improved display panel is compared with that of the non-splicing area A2
  • the corresponding impedance ratio between the second thin film transistor 14 and the first thin film transistor 13 is reduced by 5.47%, and the change in the potential of the sub-pixel electrode 12 in the display panel after the improvement is reduced from 0.1186V before the improvement to 0.09061V, which is the same as that before the improvement.
  • the degree of uneven brightness of the display panel is reduced by 23.8%; at 128 gray scales, the change of the potential of the sub-pixel electrode 12 after the improvement is reduced from 0.06095V before the improvement to 0.04938V, and the brightness of the display panel is not uniform.
  • the degree of averaging was reduced by 19%.
  • the change in the impedance ratio between the second thin film transistor 14 and the first thin film transistor 13 in the sub-pixel unit 10 corresponding to the splicing area A1 in the improved display panel is smaller than the change in the impedance ratio before the improvement, so that the improved
  • the difference between the brightness of the sub-pixels in the sub-pixel unit 10 corresponding to the splicing area A1 in the rear display panel and the brightness of the sub-pixels in the sub-pixel unit 10 corresponding to the non-splicing area A2 is smaller, so that the display panel display can be improved.
  • the problem of uneven brightness is smaller.
  • the first channel of the first thin film transistor is divided into a first sub-channel and a second sub-channel, so that the sub-pixel units corresponding to the splicing area of the lens of the exposure machine are
  • the variation of the channel width of the first thin film transistor is greater than the variation of the channel width of the second thin film transistor, thereby reducing the variation of the impedance ratio between the second thin film transistor and the first thin film transistor, so that the second thin film transistor corresponding to the splicing area is
  • the difference between the potential of the pixel electrode and the potential of the sub-pixel electrode corresponding to the non-splicing area is reduced, thereby reducing the sub-pixel in the sub-pixel unit corresponding to the splicing area and the sub-pixel in the sub-pixel unit corresponding to the non-splicing area.
  • the difference in brightness improves the problem of uneven brightness of the display panel.
  • the embodiment of the present application further provides a display device, as shown in FIG. 5 , which is a schematic structural diagram of the display device provided by the embodiment of the present application.
  • the display device includes a device main body 21 and The display panel 22 arranged on the device main body 21, the device main body 21 includes a processor, a power supply, a main board, a camera, and a frame assembly for carrying the display panel 22 and other components (not shown in the figure),
  • the display panel 22 is the display panel provided in the above embodiment.
  • the display device provided by the embodiment of the present application can achieve the same technical effect as the above-mentioned embodiment, which will not be repeated here.

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Abstract

一种显示面板及显示装置，显示面板通过将第一沟道（133）划分为第一子沟道（1331）和第二子沟道（1332），使得第一薄膜晶体管（13）沟道宽度的变化量大于第二薄膜晶体管（14）沟道宽度的变化量，以此减小第二薄膜晶体管（14）与第一薄膜晶体管（13）的阻抗比的变化量，从而减小与拼接区（A1）和非拼接区（A2）对应的次像素亮度的差异，改善显示面板亮度不均的问题。

Description

显示面板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的发展，对于显示面板中薄膜晶体管的结构尺寸的精确度要求越来越高，尤其在包含主像素和次像素的子像素单元中，需要通过主像素薄膜晶体管对主像素电极进行充电并保持电位，通过次像素薄膜晶体管对次像素电极进行充电，同时通过共享薄膜晶体管下拉电位，保证次像素的电位低于主像素的电位，从而获得良好的穿透率和可视视角。次像素的亮度与次像素的电位成正比，次像素的电位越高，次像素的穿透率就越大，次像素的亮度也就越高。次像素的电位由共享薄膜晶体管与次薄膜晶体管的阻抗比决定，在其他参数不变的前提下，共享薄膜晶体管与次像素薄膜晶体管的阻抗比即为共享薄膜晶体管的沟道宽长比与次薄膜晶体管的沟道宽长比的比值。
技术问题
在次像素薄膜晶体管和共享薄膜晶体管的制作过程中，需要通过曝光、显影、刻蚀等工艺图案化金属层，形成源极、漏极以及位于源极和漏极之间的沟道。目前，在曝光等工艺中常采用例如多镜片拼接结构的Nikon曝光机对光阻进行曝光，如图1所示，图1为曝光机镜片拼接的结构示意图，由于各镜片101之间重合的拼接区A1的曝光量小于镜片101的非拼接区A2的曝光量，使得与拼接区A1对应的次薄膜晶体管和共享薄膜晶体管的沟道两端的宽度沿Y轴方向均产生△W的变化量，沟道的长度沿X轴方向均产生△L的变化量，导致次薄膜晶体管和共享薄膜晶体管各自沟道的总宽度均产生2△W的变化量，此时与非拼接区A2和拼接区A1对应的共享薄膜晶体管与次薄膜晶体管的阻抗比分别如式1和式2所示：式1：(Wb/Lb)/(Wa/La)，式2：((Wb+2△W)/(Lb+△L))/((Wa+2△W)/(La+△L))，其中Wa为次薄膜晶体管的沟道的宽度，La为沟道的长度，Wb为共享薄膜晶体管的沟道的宽度，Lb为沟道的长度。由于次薄膜晶体管和共享薄膜晶体管的沟道的设计长度相等，且沟道长度沿X 轴方向的变化量也相等，因此与非拼接区A2和拼接区A1对应的共享薄膜晶体管与次薄膜晶体管的阻抗比可分别简化为式3和式4所示：式3：Wb/Wa，式4：(Wb+2△W)/(Wa+2△W)。以预设宽度：△W＝-0.3μm、Wa＝20μm、Wb＝5μm为例，与非拼接区A2对应的共享薄膜晶体管与次薄膜晶体管的阻抗比为：5/20＝0.25，与拼接区A1对应的共享薄膜晶体管与次薄膜晶体管的阻抗比为：(5-0.6)/(20-0.6)＝0.227，由此可见，与拼接区A1对应的共享薄膜晶体管与次薄膜晶体管的阻抗比相较于非拼接区A2减小了9.2％，意味着与拼接区A1对应的共享薄膜晶体管分走的电位相较于非拼接区A2的更少，与拼接区A1对应的子像素单元中次像素的电位高于与非拼接区A2对应的次像素的电位，使得与拼接区A1对应的次像素的亮度与非拼接区A2对应的次像素的亮度差异较大，导致显示面板出现亮度不均的问题。
综上，现有显示面板中与曝光机镜片拼接区对应的共享薄膜晶体管与次薄膜晶体管的阻抗比和与非拼接区对应的共享薄膜晶体管与次薄膜晶体管的阻抗比差异较大，导致显示面板出现亮度不均的问题。故，有必要提供一种显示面板及显示装置来改善这一缺陷。
技术解决方案
本申请实施例提供一种显示面板及显示装置，用于解决现有显示面板中与曝光机镜片拼接区对应的像素结构中共享薄膜晶体管与次薄膜晶体管的阻抗比和与非拼接区对应的像素结构中共享薄膜晶体管与次薄膜晶体管的阻抗比差异较大，导致的显示面板出现亮度不均的问题。
本申请实施例提供一种显示面板，包括阵列排布于所述显示面板内的多个子像素单元，每一所述子像素单元至少包括主像素电极、次像素电极、与所述次像素电极连接的第一薄膜晶体管、与所述第一薄膜晶体管连接的第二薄膜晶体管以及与所述主像素电极连接的第三薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和部分位于所述第一源极与所述第一漏极之间的第一沟道，所述第二薄膜晶体管包括第二源极、第二漏极和位于所述第二源极与所述第二漏极之间的第二沟道；
其中，所述第一沟道包括第一子沟道和第二子沟道，所述第一子沟道位于所述第一源极和所述第一漏极之间，所述第二子沟道位于所述第一薄膜晶体管 与所述第二薄膜晶体管之间。
根据本申请一实施例，所述子像素单元还包括辅助电极，所述辅助电极与所述第一源极连接，所述第二源极与所述第一漏极连接，所述第二子沟道位于所述辅助电极与所述第二源极之间。
根据本申请一实施例，所述第三薄膜晶体管包括第三源极、第三漏极和位于所述第三源极与所述第三漏极之间的第三沟道，所述第一子沟道与所述第三沟道均为U型沟道，且所述第一子沟道与所述第三沟道的开口方向相反。
根据本申请一实施例，所述第二子沟道为直线型沟道，所述辅助电极与所述第二源极相对平行设置，并位于所述第二源极远离所述第二漏极的一侧。
根据本申请一实施例，所述第二子沟道为U型沟道，且所述第二子沟道的开口方向与所述第一子沟道的开口方向相同。
根据本申请一实施例，所述第三沟道的长度与所述第一子沟道以及所述第二子沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和小于或等于所述第三沟道的宽度。
根据本申请一实施例，所述第二子沟道的长度与所述第二沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和大于所述第二沟道的宽度。
根据本申请一实施例，所述辅助电极与所述第一源极和所述第一漏极由同层金属制成。
根据本申请一实施例，所述主像素电极和所述次像素电极均为4畴结构。
本申请实施例提供一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括阵列排布于所述显示面板内的多个子像素单元，每一所述子像素单元至少包括主像素电极、次像素电极、与所述次像素电极连接的第一薄膜晶体管、与所述第一薄膜晶体管连接的第二薄膜晶体管以及与所述主像素电极连接的第三薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和部分位于所述第一源极与所述第一漏极之间的第一沟道，所述第二薄膜晶体管包括第二源极、第二漏极和位于所述第二源极与所述第二漏极之间的第二沟道；
其中，所述第一沟道包括第一子沟道和第二子沟道，所述第一子沟道位于所述第一源极和所述第一漏极之间，所述第二子沟道位于所述第一薄膜晶体管 与所述第二薄膜晶体管之间。
根据本申请一实施例，所述子像素单元还包括辅助电极，所述辅助电极与所述第一源极连接，所述第二源极与所述第一漏极连接，所述第二子沟道位于所述辅助电极与所述第二源极之间。
根据本申请一实施例，所述第三薄膜晶体管包括第三源极、第三漏极和位于所述第三源极与所述第三漏极之间的第三沟道，所述第一子沟道与所述第三沟道均为U型沟道，且所述第一子沟道与所述第三沟道的开口方向相反。
根据本申请一实施例，所述第二子沟道为直线型沟道，所述辅助电极与所述第二源极相对平行设置，并位于所述第二源极远离所述第二漏极的一侧。
根据本申请一实施例，所述第二子沟道为U型沟道，且所述第二子沟道的开口方向与所述第一子沟道的开口方向相同。
根据本申请一实施例，所述第三沟道的长度与所述第一子沟道以及所述第二子沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和小于或等于所述第三沟道的宽度。
根据本申请一实施例，所述第二子沟道的长度与所述第二沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和大于所述第二沟道的宽度。
根据本申请一实施例，所述辅助电极与所述第一源极和所述第一漏极由同层金属制成。
根据本申请一实施例，所述主像素电极和所述次像素电极均为4畴结构。
本申请实施例还提供一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括阵列排布于所述显示面板内的多个子像素单元，每一所述子像素单元至少包括主像素电极、次像素电极、与所述次像素电极连接的第一薄膜晶体管、与所述第一薄膜晶体管连接的第二薄膜晶体管以及与所述主像素电极连接的第三薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和部分位于所述第一源极与所述第一漏极之间的第一沟道，所述第二薄膜晶体管包括第二源极、第二漏极和位于所述第二源极与所述第二漏极之间的第二沟道；
其中，所述子像素单元还包括辅助电极，所述辅助电极与所述第二源极相对平行设置，所述第一沟道包括第一子沟道和第二子沟道，所述第一子沟道位 于所述第一源极和所述第一漏极之间，所述第二子沟道位于所述辅助电极与所述第二源极之间。
根据本申请一实施例，所述第三薄膜晶体管包括第三源极、第三漏极和位于所述第三源极与所述第三漏极之间的第三沟道，所述第一子沟道与所述第三沟道均为U型沟道，且所述第一子沟道与所述第三沟道的开口方向相反。
有益效果
本揭示实施例的有益效果：本申请实施例通过将第一薄膜晶体管的第一沟道划分为第一子沟道和第二子沟道，使得与曝光机镜片拼接区对应的子像素单元中的第一薄膜晶体管的沟道宽度变化量大于第二薄膜晶体管的沟道宽度的变化量，从而减小第二薄膜晶体管与第一薄膜晶体管的阻抗比的变化量，使得与拼接区对应的次像素电极的电位和与非拼接区对应的次像素电极的电位之间的差异减小，进而减小与拼接区对应的子像素单元中次像素和与非拼接区对应的子像素单元中次像素亮度的差异，改善显示面板亮度不均的问题。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为曝光机镜片拼接的结构示意图；
图2为本申请实施例提供的子像素单元的第一种结构示意图；
图3为图2中a部分的放大示意图；
图4为本申请实施例提供的子像素单元的第二种结构示意图；以及
图5为本申请实施例提供的显示装置的结构示意图。
本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用 以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供了一种显示面板，如图2所示，图2为本申请实施例提供的子像素单元的结构示意图。显示面板包括阵列排布于显示面板内的多个子像素单元10，每一所述子像素单元10包括主像素和次像素，主像素包括主像素电极11、次像素包括次像素电极12，且所述主像素电极11和所述次像素电极12均为4畴结构，所述子像素单元10至少还包括与次像素电极12连接的第一薄膜晶体管13、与第一薄膜晶体管13连接的第二薄膜晶体管14以及与主像素电极11连接的第三薄膜晶体管15。
如图3所示，图3为图2中a部分的放大示意图，第一薄膜晶体管13包括第一源极131、第一漏极132和至少部分位于第一源极131与第一漏极132之间的第一沟道133，第二薄膜晶体管14包括第二源极141、第二漏极142和位于第二源极141与第二漏极142之间的第二沟道143，第二沟道143处设有第二半导体层(图中未示出)。第一沟道133包括第一子沟道1331和第二子沟道1332，第一子沟道1331位于第一源极131与第一漏极132之间，第一子沟道1331处设有第一子半导体层，第二子沟道1332位于第一薄膜晶体管13与第二薄膜晶体管14之间，第二子沟道1332处设有第二子半导体层(图中未示出)。
本申请实施例所提供的显示面板中，第一沟道133由第一子沟道1331和第二子沟道1332两部分组成，第一子沟道1331和第二子沟道1332均具有沿Y轴方向延伸的两个开口，使得与曝光机镜片的拼接区A1对应的第一薄膜晶体管13的第一子沟道1331的宽度W4和第二子沟道1332的宽度W5沿Y轴方向的总变化量均为2△W。与现有技术的薄膜晶体管结构相比，与拼接区A1对应的第一薄膜晶体管13的第一沟道133的宽度W1沿Y轴方向的总变化量由2ΔW变为4ΔW，第二薄膜晶体管14的第二沟道143的宽度W2沿Y轴方向的变化量仍为2ΔW，此时与非拼接区A2对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比为：W2/W1，与拼接区A1对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比为：(W2+2△W)/(W1+4△W)。相较于现 有显示面板的薄膜晶体管结构，本申请实施例提供的显示面板的薄膜晶体管结构中保持第二薄膜晶体管14的第二沟道143的宽度W2原有的变化量，通过增大第一薄膜晶体管13的第一沟道133的宽度W1的变化量，可减小与镜片拼接区A1对应的第二薄膜晶体管14与第一薄膜晶体管13的沟道宽度比的变化量，以此减少由拼接区A1曝光量较少对第二薄膜晶体管14和第一薄膜晶体管13阻抗比的影响，减小与拼接区A1对应的次像素电极12的电位与非拼接区A2对应的次像素电极12的电位之间的差异，从而减小与拼接区A1对应的次像素的亮度和与非拼接区A2对应的次像素亮度的差异，改善显示面板亮度不均的问题。
在本申请实施例中，所述子像素单元10还包括辅助电极134，辅助电极134与所述第一源极131连接，所述第二源极141与所述第一漏极132连接，第二子沟道1332位于所述辅助电极134与所述第二源极141之间。
具体的，第三薄膜晶体管15包括第三源极151、第三漏极152、位于第三源极151和第三漏极152之间的第三沟道153以及设置于第三沟道153处的第三半导体层，第三源极151与第一薄膜晶体管13的第一源极131连接，第三漏极152与主像素电极11连接，用于给主像素电极11充电并维持一电位，第一薄膜晶体管13的第一漏极132与次像素电极12连接，用于给次像素电极12充电，共享电极16与第二薄膜晶体管14的第二漏极142连接，用于下拉次像素电极12的电位，保证次像素电极12的电位低于主像素电极11的电位。
在本申请实施例中，第一薄膜晶体管13、第二薄膜晶体管14以及第三薄膜晶体管15均为底栅结构，第一薄膜晶体管13和第二薄膜晶体管14以及第三薄膜晶体管15的栅极均设置于第一金属层，辅助电极134则与第一薄膜晶体管13的第一源极131、第一漏极132以及与第二漏极142连接的共享电极16均设置于第二金属层。当然，在一些实施例中，第一薄膜晶体管13、第二薄膜晶体管14以及第三薄膜晶体管15还可以是例如顶栅结构等其他形式，此处不做限制。
第一子沟道1331与第三沟道153均为U型沟道，且第一子沟道1331与第三沟道153的开口方向相反，第一子沟道1331的U型开口朝向次像素电极12，第三沟道153的开口朝向主像素电极11。第二子沟道1332为直线型沟道， 辅助电极134与所述第二源极141均相对于Y轴方向平行设置，第二子沟道1332位于所述第二源极141远离所述第二漏极142的一侧。
其中，第一子沟道1331的长度L4与第二子沟道1332的长度L5相等，第一子沟道1331的宽度W4与第二子沟道1332的宽度W5之和即为第一沟道133的沟道宽度W1。同时，为简化制程的难度、便于制程的监控，第二沟道143的长度L2、第三沟道153的长度L3与第一子沟道1331和第二子沟道1332的长度相等，第一子沟道1331与第二子沟道1332的宽度之和与第三沟道153的宽度W3相等。此外，为使第二薄膜晶体管14不过多下拉次像素电极12的电位，第一子沟道1331和第二子沟道1332的宽度之和应大于第二沟道143的宽度W2。
在一些实施例中，如图4所示，图4为本申请实施例提供的子像素单元的第二种结构示意图，第二子沟道1332也可以为U型沟道，此时第一子沟道1331和第三沟道153也均为U型沟道，且第一子沟道1331与第三沟道153的开口方向相反，第一子沟道1331的开口朝向次像素电极12，第三沟道153的开口朝向主像素电极11。为保证第二子沟道1332宽度的变化量与第一子沟道1331宽度的变化量相同，第二子沟道1332与第一子沟道1331的开口方向相同。
在一些实施例中，为避免由于增加的辅助电极而增加电容负载导致次像素电极12的充电率降低，可以适当增加栅极所在的第一金属层的膜层厚度来增加栅极的电阻，从而减小子像素单元10中电容负载的影响，保证次像素电极12的充电率。
以预设宽度：△W＝-0.3μm、W1＝20μm、W2＝6μm为例，与非拼接区A2对应的子像素单元10中第二薄膜晶体管14与第一薄膜晶体管13的阻抗比为：6/20＝0.3，与拼接区A1对应的子像素单元10中第二薄膜晶体管14与第一薄膜晶体管13的阻抗比为：(6-0.6)/(20-1.2)＝0.287，与拼接区A1对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比相较于与非拼接区A2对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比减小了4.3％，其阻抗比减小的百分比明显小于背景技术中现有技术显示面板的阻抗比减小的百分比，因此本申请实施例所提供的显示面板中与拼接区A1对应的子像素单元10中次像素的电位与非拼接区A2对应的子像素单元10中次像素的电位之间的差异 更小，可以改善显示面板亮度不均的问题。
Figure PCTCN2020126343-appb-000001
表1.显示面板改善前后的电性模拟
如表1所示，表1为本申请实施例所提供的电性模拟表，分别提供了本申请实施例所提供的显示面板改善前和改善后的电性模拟结果，表1中各数据为实际测量所得数据。其中，改善前的显示面板的第一薄膜晶体管的第一沟道仅包含一条沟道，改善后的显示面板的第一薄膜晶体管13的第一沟道133则包含第一子沟道1331和第二子沟道1332两部分，且与改善前相比，第一薄膜晶体管13的第一沟道133的宽度W1和长度L1的预设值保持不变，第二薄膜晶体管14的第二沟道143的长度L2的预设值保持不变，宽度W2的预设值由5μm增加至6μm，栅极所在的第一金属层的膜层厚度由0.33μm增加至0.48μm。
由表1中实际测得数据可知，改善前的显示面板中与拼接区A1对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比相较于与非拼接区A2对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比减小了7.12％；改善后的显示面板中与拼接区A1对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比相较于与非拼接区A2对应的第二薄膜晶体管14与第一薄膜晶体管13的阻抗比减小了5.47％，改善后的显示面板中次像素电极12电位的变化量由改善前的0.1186V降低为0.09061V，与改善前相比，显示面板的亮度不均的程度减小了23.8％；在128灰阶下，改善后的次像素电极12电位的变化量由改善前的0.06095V降低为0.04938V，显示面板的亮度不均的程度减小了19％。由此可见，改善后的显示面板中与拼接区A1对应的子像素单元10中第二薄膜晶体管14与第一薄膜晶体管13的阻抗比的变化量小于改善前的阻抗比的变化量，使得改善后的显示面板中与拼接区A1对应的子像素单元10中次像素的亮度和与非拼接区A2对应的子像素单元10中次像素的亮度之间的差异更小，从而可以改善显示面板显示亮度不均的问题。
本申请实施例的有益效果：本申请实施例通过将第一薄膜晶体管的第一沟道划分为第一子沟道和第二子沟道，使得与曝光机镜片拼接区对应的子像素单元中的第一薄膜晶体管的沟道宽度变化量大于第二薄膜晶体管的沟道宽度的变化量，从而减小第二薄膜晶体管与第一薄膜晶体管的阻抗比的变化量，使得与拼接区对应的次像素电极的电位和与非拼接区对应的次像素电极的电位之间的差异减小，进而减小与拼接区对应的子像素单元中次像素和与非拼接区对应的子像素单元中次像素亮度的差异，改善显示面板亮度不均的问题。
基于上述实施例所提供的显示面板，本申请实施例还提供一种显示装置，如图5所示，图5为本申请实施例所提供的显示装置的结构示意图，显示装置包括装置主体21以及设置于所述装置主体21上的显示面板22，所述装置主体21包括处理器、电源、主板、摄像头、以及用于承载显示面板22的框架总成等零部件(图中未示出)，所述显示面板22为上述实施例所提供的显示面板。本申请实施例所提供的显示装置能够实现与上述实施例相同的技术效果，此处不再赘述。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种显示面板，包括阵列排布于所述显示面板内的多个子像素单元，每一所述子像素单元至少包括主像素电极、次像素电极、与所述次像素电极连接的第一薄膜晶体管、与所述第一薄膜晶体管连接的第二薄膜晶体管以及与所述主像素电极连接的第三薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和部分位于所述第一源极与所述第一漏极之间的第一沟道，所述第二薄膜晶体管包括第二源极、第二漏极和位于所述第二源极与所述第二漏极之间的第二沟道；
    其中，所述第一沟道包括第一子沟道和第二子沟道，所述第一子沟道位于所述第一源极和所述第一漏极之间，所述第二子沟道位于所述第一薄膜晶体管与所述第二薄膜晶体管之间。
  2. 如权利要求1所述的显示面板，其中，所述子像素单元还包括辅助电极，所述辅助电极与所述第一源极连接，所述第二源极与所述第一漏极连接，所述第二子沟道位于所述辅助电极与所述第二源极之间。
  3. 如权利要求2所述的显示面板，其中，所述第三薄膜晶体管包括第三源极、第三漏极和位于所述第三源极与所述第三漏极之间的第三沟道，所述第一子沟道与所述第三沟道均为U型沟道，且所述第一子沟道与所述第三沟道的开口方向相反。
  4. 如权利要求3所述的显示面板，其中，所述第二子沟道为直线型沟道，所述辅助电极与所述第二源极相对平行设置，并位于所述第二源极远离所述第二漏极的一侧。
  5. 如权利要求3所述的显示面板，其中，所述第二子沟道为U型沟道，且所述第二子沟道的开口方向与所述第一子沟道的开口方向相同。
  6. 如权利要求3所述的显示面板，其中，所述第三沟道的长度与所述第一子沟道以及所述第二子沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和小于或等于所述第三沟道的宽度。
  7. 如权利要求6所述的显示面板，其中，所述第二子沟道的长度与所述第二沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和大于所述第二沟道的宽度。
  8. 如权利要求2所述的显示面板，其中，所述辅助电极与所述第一源极和所述第一漏极由同层金属制成。
  9. 如权利要求1所述的显示面板，其中，所述主像素电极和所述次像素电极均为4畴结构。
  10. 一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括阵列排布于所述显示面板内的多个子像素单元，每一所述子像素单元至少包括主像素电极、次像素电极、与所述次像素电极连接的第一薄膜晶体管、与所述第一薄膜晶体管连接的第二薄膜晶体管以及与所述主像素电极连接的第三薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和部分位于所述第一源极与所述第一漏极之间的第一沟道，所述第二薄膜晶体管包括第二源极、第二漏极和位于所述第二源极与所述第二漏极之间的第二沟道；
    其中，所述第一沟道包括第一子沟道和第二子沟道，所述第一子沟道位于所述第一源极和所述第一漏极之间，所述第二子沟道位于所述第一薄膜晶体管与所述第二薄膜晶体管之间。
  11. 如权利要求10所述的显示装置，其中，所述子像素单元还包括辅助电极，所述辅助电极与所述第一源极连接，所述第二源极与所述第一漏极连接，所述第二子沟道位于所述辅助电极与所述第二源极之间。
  12. 如权利要求11所述的显示装置，其中，所述第三薄膜晶体管包括第三源极、第三漏极和位于所述第三源极与所述第三漏极之间的第三沟道，所述第一子沟道与所述第三沟道均为U型沟道，且所述第一子沟道与所述第三沟道的开口方向相反。
  13. 如权利要求12所述的显示装置，其中，所述第二子沟道为直线型沟道，所述辅助电极与所述第二源极相对平行设置，并位于所述第二源极远离所述第二漏极的一侧。
  14. 如权利要求12所述的显示装置，其中，所述第二子沟道为U型沟道，且所述第二子沟道的开口方向与所述第一子沟道的开口方向相同。
  15. 如权利要求12所述的显示装置，其中，所述第三沟道的长度与所述第一子沟道以及所述第二子沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和小于或等于所述第三沟道的宽度。
  16. 如权利要求15所述的显示装置，其中，所述第二子沟道的长度与所述第二沟道的长度相等，所述第一子沟道与所述第二子沟道的宽度之和大于所述第二沟道的宽度。
  17. 如权利要求11所述的显示装置，其中，所述辅助电极与所述第一源极和所述第一漏极由同层金属制成。
  18. 如权利要求10所述的显示装置，其中，所述主像素电极和所述次像素电极均为4畴结构。
  19. 一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括阵列排布于所述显示面板内的多个子像素单元，每一所述子像素单元至少包括主像素电极、次像素电极、与所述次像素电极连接的第一薄膜晶体管、与所述第一薄膜晶体管连接的第二薄膜晶体管以及与所述主像素电极连接的第三薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和部分位于所述第一源极与所述第一漏极之间的第一沟道，所述第二薄膜晶体管包括第二源极、第二漏极和位于所述第二源极与所述第二漏极之间的第二沟道；
    其中，所述子像素单元还包括辅助电极，所述辅助电极与所述第二源极相对平行设置，所述第一沟道包括第一子沟道和第二子沟道，所述第一子沟道位于所述第一源极和所述第一漏极之间，所述第二子沟道位于所述辅助电极与所述第二源极之间。
  20. 如权利要求19所述的显示装置，其中，所述第三薄膜晶体管包括第三源极、第三漏极和位于所述第三源极与所述第三漏极之间的第三沟道，所述第一子沟道与所述第三沟道均为U型沟道，且所述第一子沟道与所述第三沟道的开口方向相反。
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