WO2022016935A1 - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
WO2022016935A1
WO2022016935A1 PCT/CN2021/089671 CN2021089671W WO2022016935A1 WO 2022016935 A1 WO2022016935 A1 WO 2022016935A1 CN 2021089671 W CN2021089671 W CN 2021089671W WO 2022016935 A1 WO2022016935 A1 WO 2022016935A1
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region
deep well
well
layer
field oxide
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French (fr)
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冒义祥
张兰
周俊芳
韩晨彬
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
  • the current design method of ultra-high voltage resistors is generally to make polycrystalline resistors on a very thick field oxide layer (FOX, Field Oxide), which requires that the thickness of the field oxide layer can withstand the withstand voltage requirement of 700V or more.
  • FOX Field Oxide
  • the withstand voltage test of the resistance of this structure belongs to the thermoelectric breakdown of the field oxide layer.
  • the field oxide layer will be damaged after the breakdown, and it is an irreversible damage; in addition, the sudden short circuit after the damage of the field oxide layer under high voltage It is easy to burn the test pin card, which will cause excessive consumption of the test pin card.
  • the present invention has been made to solve at least one of the above-mentioned problems. Specifically, one aspect of the present invention provides a semiconductor device, which includes:
  • the semiconductor substrate on which a field oxide layer is formed, the semiconductor substrate having a first conductivity type
  • the resistance layer is formed on the field oxide layer, and the resistance layer has a high-potential connection terminal and a low-potential connection terminal;
  • the deep well is formed in the semiconductor substrate, the resistance layer is located in a region above the deep well, the deep well has a second conductivity type, the second conductivity type is the same as the first conductivity type - Opposite conductivity type;
  • the deep well termination being formed in the deep well
  • the substrate terminal is formed in the semiconductor substrate and located outside the deep well;
  • the high-potential connection terminal and the deep well lead-out terminal are connected to a high-potential pad
  • the low-potential connection terminal and the substrate lead-out terminal are connected to a low-potential pad.
  • the semiconductor device of the present invention by adding a deep well with an opposite conductivity type to that of the substrate, and shorting the deep well with the high-potential connection terminal of the resistance layer, the substrate and the low-potential connection terminal of the resistance layer are connected.
  • Still another aspect of the present invention provides an electronic device, which includes the semiconductor device as described above and an electronic component connected to the semiconductor device.
  • the electronic device proposed by the present invention has similar advantages because it has the above-mentioned semiconductor device.
  • Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:
  • the semiconductor substrate has a first conductivity type and the deep well has a second conductivity type opposite to the first conductivity type;
  • the active region includes a deep well lead end and a substrate lead end, the deep well lead end is formed in the deep well, the substrate lead end is formed in the semiconductor substrate, and outside said deep well;
  • the polysilicon layer includes a resistance layer above the field oxide layer, and the resistance layer has a high-potential connection terminal and a low-potential connection terminal;
  • the high-potential connection terminal and the deep well lead-out terminal are connected to a high-potential pad
  • the low-potential connection terminal and the substrate lead-out terminal are connected to a low-potential pad
  • the manufacturing method also forms a BCD device at the same time
  • the semiconductor device includes a transistor region and a resistance region
  • the BCD device is formed in the transistor region.
  • FIG. 1 shows a schematic cross-sectional view of a current high-voltage resistor structure
  • FIG. 2 shows a schematic layout of the high-voltage resistor structure shown in FIG. 1;
  • FIG. 3 shows a schematic cross-sectional view of a high-voltage resistor structure according to an embodiment of the present invention
  • FIG. 4 shows a schematic layout of a high voltage resistor structure according to an embodiment of the present invention.
  • the current structure of a high voltage divider resistor in a device such as a BCD process includes a substrate 100 , a field oxide layer 101 formed on the substrate 100 and a resistance layer located on the field oxide layer 101 102 (for example, a polysilicon layer), the two ends of the resistance layer 102 are led out to the interconnection line 104 through the contact hole 103, and are respectively connected to the high-potential pad and the low-potential pad through the interconnection line 104, so as to apply a high voltage to the two resistors. end.
  • a resistance layer located on the field oxide layer 101 102 for example, a polysilicon layer
  • the resistance layer 102 adopts a ring-shaped design, the high-potential port (the end connected to the high-potential contact hole) is arranged inside the ring, and the low-potential port (connected to the low-potential contact hole) is arranged inside the ring. one end of the hole) is arranged in the ring on the outside.
  • the high-potential port of the high-voltage divider resistor needs to be able to withstand voltages of 700V or more.
  • the field oxide layer 101 needs to withstand a very large longitudinal electric field (because the lining The bottom 100 is generally connected to a low potential), and the thinner the field oxide layer 101, the greater the electric field.
  • the thickness of the field oxide layer 101 under the resistance layer 102 needs to be thickened in the process. photolithography steps to grow this very thick oxide layer.
  • the current basic flow of this process includes: the first step, making a deep N well; the second step, making a sacrificial oxide layer and a silicon nitride layer (used as a thick FOX shielding layer); the third step, making a thick field oxide layer lithography process, and the etching of the silicon nitride layer in this area; the fourth step is to grow a thick field oxide layer (such as a wet oxygen oxidation process) ); the fifth step, making the N well/P well; the sixth step, making the active region (or SDG layer); the seventh step, making the N-type field injection layer; the eighth step, making the normal field oxide layer; The ninth step is to fabricate the gate oxide layer; the tenth step is to fabricate the polysilicon layer.
  • the second to fourth steps are the process steps for increasing the thick field oxide layer required to form the high voltage divider resistor, and it can be seen that the complexity of the current process is greatly increased.
  • the existing structure also has significant shortcomings in the test of withstand voltage, because the voltage of the field oxide layer is almost all borne by the field oxide layer when the potential is increased, and the field oxide layer after reaching the breakdown field strength of the field oxide layer. Pyroelectric damage occurs, resulting in a permanent current path from the high potential terminal to the substrate, so a module can fail completely after breakdown.
  • the impedance of the field oxide layer will suddenly decrease to very small or even zero after the breakdown. Since the high potential end of the polysilicon resistor still has a very high voltage, this will cause a very large current to flow through the test pin card, which is easy to Damage to the test pin card.
  • the present invention proposes a semiconductor device and a manufacturing method thereof, so as to overcome at least some of the above-mentioned disadvantages.
  • FIG. 3 shows a schematic cross-sectional view of a high-voltage resistor structure according to an embodiment of the present invention
  • FIG. 4 shows a schematic layout of a high-voltage resistor structure according to an embodiment of the present invention.
  • the high-voltage resistor structure according to the embodiment of the present invention will be described in detail below with reference to FIGS. 3 to 4 .
  • the high-voltage resistance structure of this embodiment includes a substrate 200 , a deep well 201 , a first well region 202 , a second well region 203 , a deep well lead-out end 204 , a substrate lead-out end 205 , and a field oxide layer 206 , a resistive layer 207 , a conductive plug 208 and an interconnect layer 209 .
  • the semiconductor substrate 200 can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes many of these semiconductors.
  • the layer structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like.
  • the constituent material of the semiconductor substrate 200 is single crystal silicon.
  • the semiconductor substrate 200 has a first conductivity type, and the first conductivity type is, for example, a P-type, that is, the semiconductor substrate 200 is a P-type semiconductor substrate. It should be understood that, in other embodiments, the semiconductor substrate 200 may also be an N-type substrate.
  • a deep well 201 is formed in the semiconductor substrate 200, the deep well 201 has a second conductivity type opposite to the first conductivity type.
  • the deep well 201 is an N-type, that is, the deep well 201 is a deep N-well.
  • the deep in the deep wells in this document indicates that the implantation depth is deeper than other well regions, and does not indicate the specific implantation depth.
  • the deep well 201 may be formed by implanting dopant ions required by design into the substrate 200 , for example, implanting N-type dopant ions of phosphorus.
  • the specific implantation depth and doping concentration of the deep well 201 are determined according to specific design requirements, and are not specifically limited herein.
  • the first well region 202 is formed in the deep well 201 and has the second conductivity type, and the deep well extraction terminal 204 is formed in the first well region 202 .
  • the first well region 202 and the deep well lead-out terminal 204 are used to realize electrical connection between the deep well 201 and the outside.
  • the first well region 202 is an N well
  • the deep well leading end 204 is an N+ implantation region.
  • the first well region 202 and the deep well lead-out end 204 may be formed by ion implantation, and the specific implantation depth and doping concentration are determined according to specific design requirements, and are not specifically limited herein.
  • the second well region 203 includes a first region formed in the deep well 201 and a second region formed outside the deep well 201, the first region and the second region are electrically connected, so The second well region 203 has a first conductivity type, and the substrate terminal 205 is formed in the second region.
  • the second well region 203 is a P well
  • the substrate lead-out end 205 is a P+ implantation region.
  • the second well region 203 and the substrate lead-out end 205 may be formed by ion implantation, and the specific implantation depth and doping concentration are determined according to specific design requirements, and are not specifically limited herein.
  • a field oxide layer 206 is formed over the substrate 200, and the field oxide layer 206 is used to achieve isolation of each active region or transistor.
  • the field oxide layer 206 can be formed by common methods, such as thermal oxidation, wet oxygen oxidation, and the like.
  • the resistive layer 207 is formed over the field oxide layer 206 and in the region over the deep well 201 , that is, the resistive layer 207 is formed over the semiconductor substrate where the deep well 201 is located.
  • the resistance layer 207 can be made of polysilicon, in other words, the resistance layer 207 is a polysilicon layer, which can be formed by a common polysilicon deposition process, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition) ) process.
  • the thickness of the resistance layer 207 is determined according to design requirements, and is not specifically limited herein.
  • the resistance layer 207 has a high-potential connection terminal 2071 and a low-potential connection terminal 2072 (see FIG. 4 ) for connecting with the high-potential pad and the low-potential pad.
  • Conductive plugs 208 are formed on the deep well terminal 204 , the substrate terminal 205 , and the resistance layer 207 to connect the resistance layer 207 , the deep well 201 and the substrate 200 to the outside for electrical connection.
  • the interconnection layer 209 is used to realize the electrical connection of each device structure.
  • the interconnection layer 209 is used to realize the deep well lead-out terminal 204, the substrate lead-out terminal 205, the resistance layer 207 and the high potential pad or low potential Electrical connections to the pads.
  • the conductive plugs 208 and the interconnect layer 209 are formed in an interlayer dielectric layer, which is not shown in FIG. 3 for brevity.
  • one end of the resistive layer 207 is connected to the high-potential pad through the high-potential connection terminal 2071 , the conductive plug 208 , and the interconnection layer 209 to connect to the high-voltage pad;
  • the connection terminal 2072, the conductive plug 208, and the interconnect layer 209 are connected to the low potential pad for connection to a low voltage (eg, ground).
  • a low voltage eg, ground
  • a high voltage can be applied to the resistance layer 207.
  • a deep well 201 is formed, and the first well region 202 and the deep well lead-out terminal are formed.
  • the conductive plug 208 and the interconnect layer 209 connect the deep well 201 to the high potential pad, in other words, short the high voltage terminal of the resistive layer 207 into the deep well.
  • the substrate 20 and the second well region 203 are connected to the low-potential pad through the substrate lead-out terminal 205 , the conductive plug 208 and the interconnect layer 209 , so that a high voltage is connected in parallel at both ends of the resistance layer 207 PN diode, and the cathode is connected to the high voltage, and the anode is connected to the low voltage (ie, the reverse-connected high-voltage PN diode).
  • the resistance layer 207 When the resistance layer 207 is subjected to high voltage, the high voltage is mainly borne by the deep well 201 (deep N well) and the depletion layer of the substrate 200 (P-SUB) and the second well region 203 (PW), while the resistance layer 207 and The underlying silicon surface (the surface of the deep well 201) is substantially equipotential, and the longitudinal electric field applied to the field oxide layer 206 is very small, so there is no need to increase the thickness of the field oxide layer.
  • the high-voltage resistance structure of this embodiment realizes the transfer of the high-voltage electric field from the field oxide layer to the depletion region of the PN junction, so that the field oxide layer under the resistance layer can use a normal thickness, and there is no need to increase the process steps to make a thicker field oxide layer.
  • the resistance layer 207 has a ring structure, which includes multiple turns of resistance wires connected end to end in sequence. That is, the resistance layer 207 is composed of a circle of polysilicon wires connected to each other, wherein the end of the inner circle is used as the high potential connection terminal 2071 , and the end of the outer circle is connected to the substrate lead end 205 as the low potential connection end 2072 .
  • the high-potential connection end 2071 is located on the side of the resistance line near the center of the ring structure
  • the low-potential connection end 2072 is located on the side of the resistance line near the edge of the ring structure.
  • the deep well lead-out end 204 (ie, the N+ injection region) is formed in the central region of the annular structure, and exemplarily, the deep well lead-out end 204 is circular.
  • the substrate lead-out end 205 has a ring structure and is arranged around the deep well 201 .
  • the high-voltage resistor structure adopts a circular layout, the high-voltage end is located in the central area, and the low-voltage end is located in the edge area, which is more conducive to charge balance and withstand voltage stability in the PN junction.
  • the withstand voltage of the high-voltage resistance structure in this embodiment is mainly borne by the depletion layers of Deep-NW (deep well 201 ), P-SUB (substrate 200 ) & PW (second well region 203 ), so only Adjusting the length of the Deep-NW (deep well 201) can meet the requirements of high voltage resistance in different gears.
  • the new structure deep well 201 adopts a circular layout, the high voltage terminal is located in the center, the low voltage terminal is located at the edge, and the new substrate leads out The terminal is used as the anode of the P/N junction. This structure is better in the balance of N and P charges, and it is also better in the stability of withstand voltage.
  • the breakdown of the high-voltage resistance structure in this embodiment belongs to avalanche breakdown, which is not only a reversible process, and the current of avalanche breakdown is smaller than that of thermoelectric breakdown, so the test pin card will not be damaged.
  • the basic process of fabricating the high-voltage resistor structure of this embodiment includes: the first step is to fabricate a deep N well (that is, on the substrate 200, a deep well 201 is formed); the second step, the NW/PW layer is formed (that is, the first well region 202 and the second well region 203 are formed); the third step, the active region is formed (that is, the deep well lead-out 204 and The substrate terminal 205 and the source and drain regions of other regions are implanted); the fourth step is to make an N-type field implantation layer (that is, ion implantation is performed on the field region); layer 207 and the field oxide layer in other regions); the sixth step, making the gate oxide layer; the seventh step, making the polysilicon layer (forming the resistance layer 207 and the gate layer in other regions).
  • the fabrication of the high-voltage resistor structure of the present embodiment can be realized by the conventional steps of the current BCD process, and the additional steps of fabricating the thickened field oxide layer do not need to be added. Therefore, compared with the current fabrication process of the high-voltage resistor , reducing process steps, reducing process difficulty and cost.
  • the semiconductor device includes: a semiconductor substrate, on which a field oxide layer is formed, the semiconductor substrate has a first conductivity type; a resistance layer, the resistance layer is formed on the field oxide layer , the resistance layer has a high potential connection terminal and a low potential connection terminal; a deep well, the deep well is formed in the semiconductor substrate, the resistance layer is located in the region above the deep well, the deep well having a second conductivity type opposite to the first conductivity type; a deep well lead-out end formed in the deep well; a substrate lead-out end, the substrate lead-out a terminal is formed in the semiconductor substrate and is located outside the deep well; wherein the high potential connection terminal and the deep well extraction terminal are connected to a high potential pad, the low potential connection terminal and the liner The bottom terminal is connected to the low potential pad.
  • the semiconductor device further includes: a first well region, the first well region is formed in the deep well and has a second conductivity type, and the deep well lead-out terminal is formed in the first well region .
  • the semiconductor device further includes: a second well region, the second well region includes a first region formed in the deep well and a second region formed outside the deep well, the first region A region is electrically connected to the second region, the second well region has a first conductivity type, and the substrate extraction terminal is formed in the second region.
  • the electronic component can be any electronic component such as a discrete device, an integrated circuit, or the like.
  • the included ESD protection device can increase the sustain voltage while increasing the ESD robustness and the current discharge capability, it can achieve a better ESD protection effect. Therefore, the electronic device also has similar advantages.

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Abstract

一种半导体器件，该半导体器件包括：半导体衬底(200)，其上形成有场氧化层(206)，半导体衬底(200)具有第一导电类型；电阻层(207)，形成在场氧化层(206)之上，具有高电位连接端(2071)和低电位连接端(2072)；深阱(201)，形成在所述半导体衬底(200)中，电阻层(207)位于所述深阱(201)之上的区域，深阱(201)具有第二导电类型，第二导电类型与第一导电类型相反；深阱引出端(204)，形成在所述深阱(201)中；衬底引出端(205)，形成在所述半导体衬底(200)中，并且位于所述深阱(201)之外；高电位连接端(2071)和深阱引出端(204)连接至高电位焊盘，低电位连接端(2072)和衬底引出端(205)连接至低电位焊盘。

Description

半导体器件
相关申请的交叉引用
本申请要求于2020年07月20日提交中国专利局、申请号为2020106990369、发明名称为“半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件及其制造方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
目前在BCD(Bipolar-CMOS-DMOS)工艺中实现超高压分压电阻的应用需求越来越广泛。目前的超高压电阻的设计方法一般是在一层很厚的场氧化层(FOX，Field Oxide)上做多晶电阻，其要求场氧化层的厚度能够承受700V甚至以上的耐压需求。为了实现这个目的，工艺上需要多做一层光刻，用湿氧氧化来生长一层
Figure PCTCN2021089671-appb-000001
以上的场氧化层。这种方法不仅使得工艺成本和流通时间都增加了不少，而且对场氧化层的厚度和绝缘性都提出了很高的要求。另外这种结构的电阻的耐压测试属于场氧化层的热电击穿，而一般击穿后场氧化层会被损坏，且是一种不可逆的损伤；另外高电压下场氧化层损伤后的突然短路很容易烧毁测试针卡，这将造成测试针卡的过度消耗。
发明内容
为了解决上述问题中的至少一个而提出了本发明。具体地，本发明一方面提供一种半导体器件，其包括：
半导体衬底，所述半导体衬底上形成有场氧化层，所述半导体衬底具有第一导电类型；
电阻层，所述电阻层形成在所述场氧化层之上，所述电阻层具有高电位 连接端和低电位连接端；
深阱，所述深阱形成在所述半导体衬底中，所述电阻层位于所述深阱之上的区域，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反；
深阱引出端，所述深阱引出端形成在所述深阱中；及
衬底引出端，所述衬底引出端形成在所述半导体衬底中，并且位于所述深阱之外；
其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低电位连接端和所述衬底引出端连接至低电位焊盘。
根据本发明的半导体器件，通过增加一个与衬底导电类型相反的深阱，并将深阱与电阻层的高电位连接端短接，将所述衬底与所述电阻层的低电位连接端连接至低电位，这样相当于在电阻方向上并联的了高压PN二极管，将高电电阻下的场氧化层承受的高电场和耐压转移到了深阱和衬底的耗尽层内，因此无需使用厚度很多的场氧化层，减少了之前形成厚场氧化层的工艺步骤，并且由于新结构的PN结雪崩击穿属于可逆过程，与目前的场氧化层热击穿相比，不会烧毁测试针卡。
本发明再一方面提供一种电子装置，其包括如上所述的半导体器件以及与所述半导体器件相连接的电子组件。
本发明提出的电子装置，由于具有上述半导体器件，因而具有类似的优点。
本发明另一方面提供一种半导体器件的制造方法，包括：
在半导体衬底中形成深阱；所述半导体衬底具有第一导电类型，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反；
形成有源区；所述有源区包括深阱引出端和衬底引出端，所述深阱引出端形成在所述深阱中，所述衬底引出端形成在所述半导体衬底中、且位于所述深阱之外；
在所述半导体衬底上形成场氧化层；及
形成多晶硅层；所述多晶硅层包括所述场氧化层之上的电阻层，所述电阻层具有高电位连接端和低电位连接端；
其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低 电位连接端和所述衬底引出端连接至低电位焊盘，所述制造方法还同时形成BCD器件，所述半导体器件包括晶体管区域和电阻区域，所述BCD器件形成于所述晶体管区域。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出目前一种高压电阻结构的示意性剖面图；
图2示出图1所示高压电阻结构的示意性布图；
图3示出根据本发明一实施例的高压电阻结构的示意性剖面图；
图4示出根据本发明一实施例的高压电阻结构的示意性布图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
为了彻底理解本发明，将在下列的描述中提出详细的结构，以便阐释本发明提出的技术方案。本发明的可选实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
首先，结合图1至图2对目前的高压分压电阻结构进行描述。如图1所示，目前在诸如BCD工艺制作的器件中的高压分压电阻的结构包括衬底100，形成在衬底100之上的场氧化层101和位于场氧化层101之上的电阻层102(例如多晶硅层)，电阻层102的两端通过接触孔103引出至互连线104，并通过互连线104分别连接至高电位焊盘和低电位焊盘，以将高电压施加在电阻两端。如图2所示，在目前的高压分压电阻结构中，电阻层102采用环状设计，高电位端口(连接高电位接触孔的一端)设置在环状内侧，低电位端口(连接低电位接触孔的一端)设置在环状在外侧。
在很多应用中，高压分压电阻的高电位端口需要能承受700V甚至以上电压，当高电压加在电阻层102(多晶硅层)上时，场氧化层101需要承受 非常大的纵向电场(因为衬底100一般接低电位)，且场氧化层101越薄，电场就会越大。为了不让场氧化层101承受的电场达到击穿场强，在工艺上就需要加厚电阻层102下面的场氧化层101的厚度，为了实现这个目的，目前工艺上采取的方法是增加一次单独的光刻步骤来生长这个非常厚的氧化层。目前这种工艺的基本流程包括：第一步，制作深N阱；第二步，制作牺牲氧化层和氮化硅层(用作厚FOX的遮蔽层)；第三步，进行厚场氧化层的光刻工艺，以及该区域氮化硅层的腐蚀；第四步，通过湿氧氧化工艺生长厚场氧化层(例如
Figure PCTCN2021089671-appb-000002
)；第五步，制作N阱/P阱；第六步，制作有源区(或SDG层)；第七步，制作N型场注入层；第八步，制作正常的场氧化层；第九步，制作栅极氧化层；第十步，制作多晶硅层。其中，第二至第四步是为了形成高压分压电阻所需的厚场氧化层增加的工艺步骤，可见目前这种工艺的复杂性大大增加。且除工艺上复杂外，现有结构在测试耐压上也有显著的缺点，因为加高电位时其电压几乎全部由场氧化层来承受，在达到场氧化层的击穿场强后场氧化层发生热电损伤，造成高电位端到衬底的永久电流通路，所以一个模块在击穿后会彻底失效。而且场氧化层在击穿后其阻抗会突然降低为很小甚至为零，由于多晶硅电阻的高电位端仍然有很高的电压，这会导致一个非常大的电流流过测试针卡，很容易造成测试针卡的损坏。
本发明基于此提出一种半导体器件及其制作方法，以至少克服上述部分缺点。
图3示出根据本发明一实施例的高压电阻结构的示意性剖面图；图4示出根据本发明一实施例的高压电阻结构的示意性布图。下面结合图3至图4对根据本发明实施例的高压电阻结构进行详细描述。
如图3所示，本实施例的高压电阻结构包括衬底200、深阱201、第一阱区202、第二阱区203、深阱引出端204、衬底引出端205、场氧化层206、电阻层207、导电插塞208和互连层209。
其中，半导体衬底200可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底200的构成材料选用单晶硅。示例性地，在本实施例中，半导体衬底200具有第一导电类型，所述第一导电类型例如为P型，即半导体衬底200为P型半导体衬 底。应该理解，在其它实施例中，半导体衬底200也可以为N型衬底。
深阱201形成在所述半导体衬底200中，所述深阱201具有第二导电类型，所述第二导电类型与所述第一导电类型相反。示例性地，在本实施例中，深阱201为N型，即深阱201为深N阱。在本文中深阱中的深表示其注入深度比其他阱区更深，而不表示具体注入深度。深阱201可以通过向衬底200中注入设计要求的掺杂离子形成，例如注入磷的N型掺杂离子形成。深阱201的具体注入深度、掺杂浓度等根据具体设计要求确定，在此不做具体限定。
所述第一阱区202形成在所述深阱201中，并且具有第二导电类型，所述深阱引出端204形成在所述第一阱区202中。所述第一阱区202和所述深阱引出端204用于实现深阱201与外部的电连接。示例性地，所述第一阱区202为N阱，所述深阱引出端204为N+注入区。所述第一阱区202和所述深阱引出端204可以通过离子注入形成，具体注入深度、掺杂浓度等根据具体设计要求确定，在此不做具体限定。
所述第二阱区203包括形成在所述深阱201中的第一区域和形成在所述深阱201之外的第二区域，所述第一区域和所述第二区域电连接，所述第二阱区203具有第一导电类型，所述衬底引出端205形成在所述第二区域中。示例性地，在本实施例中，第二阱区203为P阱，衬底引出端205为P+注入区。所述第二阱区203和所述衬底引出端205可以通过离子注入形成，具体注入深度、掺杂浓度等根据具体设计要求确定，在此不做具体限定。
场氧化层206形成在衬底200之上，场氧化层206用于实现各有源区或晶体管的隔离。场氧化层206可以通过常用方法形成，比如热氧化法、湿氧氧化法等。
电阻层207形成在场氧化层206之上，并且位于深阱201之上的区域中，即电阻层207形成在深阱201所在的半导体衬底之上。示例性地，电阻层207可以采用多晶硅制作，换言之电阻层207是多晶硅层，其可以通过常用的多晶硅沉积工艺形成，例如PVD(物理气相沉积)、CVD(化学气相沉积)、ALD(原子层沉积)工艺。电阻层207的厚度根据设计要求确定，在此不做具体限定。所述电阻层207具有高电位连接端2071和低电位连接端2072(参见图4)，用于与高电位焊盘和低电位焊盘连接。
导电插塞208形成在深阱引出端204、衬底引出端205、电阻层207之上， 以将电阻层207、深阱201和衬底200引出与外部进行电连接。
互连层209用于实现各器件结构的电连接，在本实施例中，互连层209用于实现深阱引出端204、衬底引出端205、电阻层207与高电位焊盘或低电位焊盘的电连接。应当理解，导电插塞208和互连层209形成在层间介电层中，图3中出于简洁目的并未示出。
如图3所示，在本实施例中，电阻层207的一端通过高电位连接端2071、导电插塞208、互连层209与高电位焊盘连接，以连接高电压；另一端通过低电位连接端2072、导电插塞208、互连层209与低电位焊盘连接，以连接至低电压(例如接地)。这样就可以将高电压施加在电阻层207上，同时，在本实施例中，为了不需要制作很厚的场氧化层，制作了深阱201，并且通过第一阱区202、深阱引出端204、导电插塞208和互连层209将深阱201连接至高电位焊盘，换言之，将电阻层207的高压端短接到深阱内。同时，通过衬底引出端205、导电插塞208和互连层209将衬底20和第二阱区203连接至低电位焊盘，这样，相当于在电阻层207的两端并联了一个高压PN二极管，并且是阴极连接高电压，阳极连接低电压(即反接的高压PN二极管)。当电阻层207承受高压时，其高压主要由深阱201(深N阱)与衬底200(P-SUB)和第二阱区203(PW)的耗尽层来承担，而电阻层207和下方硅表面(深阱201表面)基本等电位，所施加在场氧化层206上的纵向电场很小，因此不需要额外的加厚场氧化层的厚度。换言之，本实施例的高压电阻结构实现了高压电场从场氧化层向PN结耗尽区的转移，这样电阻层下方的场氧化层使用正常的厚度即可，无需增加工艺步骤制作加厚的场氧化层。
请参阅图4，在本实施例中，电阻层207呈环状结构，其包括依次首尾相接的多圈电阻线。即电阻层207由一圈又一圈彼此连接的多晶硅线构成，其中内圈的端点作为高电位连接端2071，外圈的端点与衬底引出端205连接，作为低电位连接端2072。换言之，所述高电位连接端2071位于所述电阻线处于靠近所述环状结构中心的一侧，所述低电位连接端2072位于所述电阻线处于靠近所述环状结构边缘的一侧。相应地，在本实施例中，所述深阱引出端204(即N+注入区)形成在所述环状结构的中心区域，并且示例性地，深阱引出端204呈圆形。所述衬底引出端205呈环状结构，且环绕所述深阱201设置。
如图4所示，在本实施例中，高压电阻结构采用圆形布局，高压端位于中心区域，低压端位于边缘区域，这样更有利于PN结中电荷平衡和耐压的稳定性。
如上所述，本实施例的高压电阻结构耐压主要由Deep-NW(深阱201)与P-SUB(衬底200)&PW(第二阱区203)的耗尽层来承担，因此只需调整Deep-NW(深阱201)的长度就能实现不同档位高压电阻的需求，另外新结构深阱201采用圆形的布局，高压端位于中心，低压端位于边缘，新增的衬底引出端作为P/N结的阳极，此结构在N、P电荷平衡上更好，其在耐压的稳定性上也更好。另外本实施例的高压电阻结构的击穿属于雪崩击穿，其不仅属于可逆过程，且雪崩击穿的电流相比热电击穿很小，因此不会损伤测试针卡。
如上所述，本实施例的高压电阻结构，无需增加工艺步骤制作加厚的场氧化层，因此制作本实施例的高压电阻结构基本流程包括：第一步，制作深N阱(即在衬底200中形成深阱201)；第二步，制作NW/PW层(即形成第一阱区202和第二阱区203)；第三步，制作有源区(即形成深阱引出端204和衬底引出端205以及其他区域的源漏区注入)；第四步，制作N型场注入层(即对场区进行离子注入)；第五步，制作正常的场氧化层(即制作场氧化层207和其他区域的场氧化层)；第六步，制作栅极氧化层；第七步，制作多晶硅层(形成电阻层207和其他区域的栅极层)。通过与前述对比可知，制作本实施例的高压电阻结构，工艺步骤以目前BCD工艺的常规步骤即可实现，无需增加前述制作加厚场氧化层的额外步骤，因此目前的高压电阻制作工艺相比，减少了工艺步骤，降低了工艺难度和成本。
本发明的另一个方面还提供一种电子装置，包括半导体器件以及与所述半导体器件相连的电子组件。其中，该半导体器件包括：半导体衬底，所述半导体衬底上形成有场氧化层，所述半导体衬底具有第一导电类型；电阻层，所述电阻层形成在所述场氧化层之上，所述电阻层具有高电位连接端和低电位连接端；深阱，所述深阱形成在所述半导体衬底中，所述电阻层位于所述深阱之上的区域，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反；深阱引出端，所述深阱引出端形成在所述深阱中；衬底引出端，所述衬底引出端形成在所述半导体衬底中，并且位于所述深阱之外； 其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低电位连接端和所述衬底引出端连接至低电位焊盘。
进一步地，该半导体器件还包括：第一阱区，所述第一阱区形成在所述深阱中，并且具有第二导电类型，所述深阱引出端形成在所述第一阱区中。
进一步地，该半导体器件还包括：第二阱区，所述第二阱区包括形成在所述深阱中的第一区域和形成在所述深阱之外的第二区域，所述第一区域和所述第二区域电连接，所述第二阱区具有第一导电类型，所述衬底引出端形成在所述第二区域中。
其中，该电子组件，可以为分立器件、集成电路等任何电子组件。
本发明实施例的电子装置，由于所包含的ESD保护器件可以在增加维持电压同时增大ESD鲁棒性，增加了电流泄放能力，因此可以实现更好的ESD防护效果。因此该电子装置同样具有类似的优点。
尽管这里已经参考附图描述了示例实施例，应理解上述示例实施例仅仅是示例性的，并且不意图将本发明的范围限制于此。本领域普通技术人员可以在其中进行各种改变和修改，而不偏离本发明的范围和精神。所有这些改变和修改意在被包括在所附权利要求所要求的本发明的范围之内。

Claims (15)

  1. 一种半导体器件，包括：
    半导体衬底，具有第一导电类型；
    场氧化层，形成在所述半导体衬底上；
    电阻层，形成在所述场氧化层之上，所述电阻层具有高电位连接端和低电位连接端；
    深阱，形成在所述半导体衬底中，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反，所述电阻层位于所述深阱之上的区域；
    深阱引出端形成在所述深阱中；及
    衬底引出端形成在所述半导体衬底中，并且位于所述深阱之外；
    其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低电位连接端和所述衬底引出端连接至低电位焊盘。
  2. 根据权利要求1所述的半导体器件，其特征在于，还包括：
    第一阱区，所述第一阱区形成在所述深阱中，并且具有第二导电类型，所述深阱引出端形成在所述第一阱区中。
  3. 根据权利要求2所述的半导体器件，其特征在于，还包括：
    第二阱区，所述第二阱区包括形成在所述深阱中的第一区域和形成在所述深阱之外的第二区域，所述第一区域和所述第二区域电连接，所述第二阱区具有第一导电类型，所述衬底引出端形成在所述第二区域中。
  4. 根据权利要求1所述的半导体器件，其特征在于，所述电阻层呈环状结构。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述电阻层包括依次首尾相接的多圈电阻线。
  6. 根据权利要求4所述的半导体器件，其特征在于，所述深阱引出端形成在所述环状结构的中心区域。
  7. 根据权利要求4所述的半导体器件，其特征在于，所述高电位连接端位于所述电阻线处于靠近所述环状结构中心的一侧，所述低电位连接端位于所述电阻线处于靠近所述环状结构边缘的一侧。
  8. 根据权利要求4所述的半导体器件，其特征在于，所述衬底引出端呈 环状结构，且环绕所述深阱设置。
  9. 根据权利要求1所述的半导体器件，其特征在于，所述场氧化层的厚度为
    Figure PCTCN2021089671-appb-100001
  10. 根据权利要求9所述的半导体器件，其特征在于，所述半导体衬底包括晶体管区域和电阻区域，所述晶体管区域中的所述场氧化层的厚度与所述电阻区域中的所述场氧化层的厚度相同。
  11. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件形成有与所述电阻层的两端并联的二极管，所述二极管的阴极连接至所述高电位焊盘，所述二极管的阳极连接至所述低电压焊盘，所述二极管的阴极包括所述深阱，所述二极管的阳极包括所述半导体衬底。
  12. 根据权利要求1所述的半导体器件，其特征在于，所述电阻层采用多晶硅制作。
  13. 一种半导体器件的制造方法，包括：
    在半导体衬底中形成深阱；所述半导体衬底具有第一导电类型，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反；
    形成有源区；所述有源区包括深阱引出端和衬底引出端，所述深阱引出端形成在所述深阱中，所述衬底引出端形成在所述半导体衬底中、且位于所述深阱之外；
    在所述半导体衬底上形成场氧化层；及
    形成多晶硅层；所述多晶硅层包括所述场氧化层之上的电阻层，所述电阻层具有高电位连接端和低电位连接端；
    其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低电位连接端和所述衬底引出端连接至低电位焊盘，所述制造方法还同时形成BCD器件，所述半导体器件包括晶体管区域和电阻区域，所述BCD器件形成于所述晶体管区域。
  14. 根据权利要求13所述的制造方法，所述在半导体衬底中形成深阱的步骤之后、所述形成有源区的步骤之前，还包括形成第一导电类型阱区和第二导电类型阱区的步骤；所述第一导电类型阱区包括第二阱区，所述第二阱区包括形成在所述深阱中的第一区域和形成在所述深阱之外的第二区域，所述第一区域和所述第二区域电连接，所述衬底引出端形成在所述第二区域中； 所述第二导电类型阱区包括第一阱区，所述第一阱区形成在所述深阱中，所述深阱引出端形成在所述第一阱区中；
    所述所述半导体衬底上形成场氧化层的步骤之后、所述形成多晶硅层的步骤之前，还包括形成栅极氧化层的步骤；所述多晶硅层还包括栅极层，所述栅极层形成于晶体管区域；
    所述形成有源区的步骤还包括形成源区和漏区，所述源区和漏区形成于晶体管区域。
  15. 根据权利要求13所述的制造方法，其特征在于，所述在所述半导体衬底上形成场氧化层的步骤包括同时在晶体管区域和电阻区域形成场氧化层，且晶体管区域的场氧化层和电阻区域的场氧化层厚度相同。
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