CN104064600B - 一种上拉双扩散金属氧化物半导体及其制作方法 - Google Patents

一种上拉双扩散金属氧化物半导体及其制作方法 Download PDF

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CN104064600B
CN104064600B CN201410283101.4A CN201410283101A CN104064600B CN 104064600 B CN104064600 B CN 104064600B CN 201410283101 A CN201410283101 A CN 201410283101A CN 104064600 B CN104064600 B CN 104064600B
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CN104064600A (zh
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吉扬永
张磊
傅达平
连延杰
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本申请公开了一种上拉双扩散金属氧化物半导体及其制作方法。所述上拉双扩散金属氧化物半导体包括：衬底、外延层、第一阱区、第二阱区、基区、体接触区、源接触区、漏接触区、场氧、栅氧、厚栅氧、多晶硅栅、源极电极、漏极电极、栅极电极，所述多晶硅栅包括终端部分和普通部分，所述终端部分包括有源多晶硅、在栅氧和厚栅氧上的第一延伸多晶硅、以及在厚栅氧和场氧上的第二延伸多晶硅。所述上拉双扩散金属氧化物半导体在小的终端面积情况下具有更高的击穿电压。

Description

一种上拉双扩散金属氧化物半导体及其制作方法
技术领域
本发明涉及一种半导体器件，更具体地说，本发明涉及一种上拉DMOS(双扩散金属氧化物半导体)器件及其制作方法。
背景技术
DMOS被广泛应用于电路中。典型地，对于下拉(low-side)DMOS而言，由于其源极电势通常为零电势，其终端(in termination)的源极和体区均连接至隔离环。因此，无需额外的层来执行下拉DMOS与其他器件之间的隔离或者来提高其击穿电压。因此，其终端面积(termination area)可以非常小。但是，对上拉(high-side)DMOS而言，由于其特殊的工作环境(如：上拉DMOS源漏间的电压降很高，且其源极电势为浮着的电位)，通常需要完全的隔离措施。一种现行的实现完全隔离的做法为将上拉DMOS的N型阱区进行延伸，如图1a所示，使得上拉DMOS的源极和体区均被该N型阱区环绕。然而，这可能会降低终端P型基区和N型阱区之间的击穿电压。
一种改进的做法为在终端N型阱区中插入P型阱区。如图1b所示，部分环绕P型基区12的P型阱区11植入在N型阱区10内。其中，P型基区12作为体区。这种方法将P型基区和N型阱区直接的击穿电压转移为P型阱区与N型阱区之间的击穿电压。而通常情况下，在DMOS中，P型阱区与N型阱区之间的击穿电压远远高于P型基区与N型阱区之间的击穿电压。然而，插入的P型阱区需要消耗大的面积，从而增大了器件的尺寸。
发明内容
因此本发明的目的在于解决现有技术的上述技术问题，提出一种改进的上拉双扩散金属氧化物半导体。
根据上述目的，本发明提出了一种上拉双扩散金属氧化物半导体,包括：具有第一掺杂类型的衬底；形成在衬底内的具有第二掺杂类型的掩埋层；形成在衬底上的外延层；形成在外延层内具有第二掺杂类型的第一阱区；形成在外延层内具有第一掺杂类型的第二阱区，所述第二阱区毗邻第一阱区；形成在第一阱区内具有第一掺杂类型的基区，所述基区和第一阱区形成体-阱结；形成在基区内的具有第一掺杂类型的体接触区；形成在基区内的具有第二掺杂类型的源接触区，所述源接触区毗邻体接触区；形成在第一阱区内的具有第二掺杂类型的漏接触区；形成在外延层上的场氧；形成在外延层上的栅氧；厚栅氧，所述厚栅氧部分形成在栅氧上，部分形成在外延层上，部分形成在场氧上；形成在场氧、栅氧和厚栅氧上的多晶硅栅，所述多晶硅栅包括终端部分和普通部分，所述终端部分包括在体-阱结上的有源多晶硅、在栅氧和厚栅氧上的第一延伸多晶硅、以及在厚栅氧和场氧上的第二延伸多晶硅；与体接触区和源接触区接触的源极电极；与漏接触区接触的漏极电极；以及与多晶硅栅的普通部分接触的栅极电极。
根据上述目的，本发明还提出了一种制作上拉双扩散氧化物半导体的方法，包括：在衬底上形成N型掩埋层；在衬底上形成外延层；在外延层内形成N型阱区和P型阱区；在外延层上形成场氧，所述外延层的部分区域被所述场氧所覆盖；在外延层上形成栅氧，在部分场氧、部分外延层和部分栅氧上形成厚栅氧，其中外延层未被场氧覆盖的区域被栅氧和厚栅氧覆盖；在场氧、栅氧和厚栅氧上形成多晶硅栅，所述多晶硅栅包括终端部分和普通部分，所述终端部分包括有源多晶硅、形成在栅氧和厚栅氧上的第一延伸多晶硅，以及形成在厚栅氧和场氧上的第二延伸多晶硅；在N型阱区内形成P型基区，所述P型基区和N型阱区形成体-阱结，所述体-阱结在有源多晶硅的下方；在P型基区内形成体接触区和源接触区，在N型阱区内形成漏接触区；形成与体接触区和源接触区接触的源极电极、与漏接触区接触的源极电极、以及与多晶硅栅的普通部分接触的栅极电极。
根据本发明各方面的上述上拉双扩散金属氧化物半导体及其制作方法在小的终端面积情况下具有更高的击穿电压。
附图说明
图1a和图1b示意性地示出了两种现有上拉DMOS的剖视图；
图2示意性地示出了根据本发明一实施例的上拉DMOS 100的剖面图；
图3示意性地示出了根据本发明另一实施例的上拉DMOS 200的剖面图；
图4示意性地示出了根据本发明另一实施例的上拉DMOS 300的剖面图；
图5-13示意性地示出了根据本发明又一实施例的上拉DMOS的制作流程图。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。应当理解，当称元件“耦接到”或“连接到”另一元件时，它可以是直接耦接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接耦接到”或“直接连接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图2示意性地示出了根据本发明一实施例的上拉DMOS 100的剖面图。在图2所示实施例中，上拉DMOS 100包括：具有第一掺杂类型的衬底101；形成在衬底101内的具有第二掺杂类型的掩埋层102；形成在衬底101上的外延层120；形成在外延层120内具有第二掺杂类型的第一阱区103；形成在外延层120内具有第一掺杂类型的第二阱区104，其中第二阱区104毗邻第一阱区103；形成在第一阱区103内具有第一掺杂类型的基区105，所述基区105和第一阱区103形成体-阱结31；形成在基区105内的具有第一掺杂类型的体接触(pickup)区51；形成在基区105内的具有第二掺杂类型的源接触区52，所述源接触区52毗邻体接触区51；形成在第一阱区103内的具有第二掺杂类型的漏接触区53；形成在外延层120上的场氧106；形成在外延层120上的栅氧107；厚栅氧108，所述厚栅氧108部分形成在栅氧107上、部分形成在外延层120上、部分形成在场氧106上；形成在场氧106、栅氧107和厚栅氧108上的多晶硅栅，所述多晶硅栅包括终端部分109-1和普通部分109-2，所述终端部分109-1包括在体-阱结31上的有源多晶硅81、在栅氧107和厚栅氧108上的第一延伸多晶硅82、以及在厚栅氧108和场氧106上的第二延伸多晶硅83；与体接触区51和源接触区52接触的源极电极110；与漏接触区53接触的漏极电极111；以及与多晶硅栅的普通部分109-2接触的栅极电极112。
在一个实施例中，第一掺杂类型为P型掺杂，第二掺杂类型为N型掺杂。
在一个实施例中，所述有源多晶硅81、第一延伸多晶硅82和第二延伸多晶硅83包括阶梯场板(stair-field plate)。
在图2所示实施例中，场氧106不具有浅沟道(shallow-trench isolation)结构。但本领域的技术人员应该意识到，场氧107可具有浅沟道结构，如图3所示。
图3示意性地示出了根据本发明一实施例的上拉DMOS 200的剖面图。图3所示上拉DMOS 200与图2所示上拉DMOS 100相似，与图2所示上拉DMOS 100不同的是，图3所示上拉DMOS 200的场氧106具有浅沟道结构。
在一个实施例中，上拉DMOS可进一步包括环绕第一阱区的轻掺杂阱区。图4示意性地示出了根据本发明又一实施例的上拉DMOS300的剖面图。图4所示上拉DMOS 300与图2所示上拉DMOS 100相似。与图2所示上拉DMOS 100不同的是，图4所示上拉DMOS 300还包括：形成在外延层120内的具有第二掺杂类型的轻掺杂阱区113。所述第一阱区103被轻掺杂阱区113环绕。
图5-13示意性地示出了根据本发明又一个实施例的上拉DMOS的制作流程图。
如图5所示，所述制作流程包括在衬底101上形成N型掩埋层102。
如图6所示，所述制作流程包括在衬底101上形成外延层120。在一个实施例中，所述外延层120采用淀积技术，如化学气相沉积技术、等离子增强化学气相沉积技术、原子层沉积技术、液相外延技术或者其他合适的淀积技术。在一个实施例中，外延层120为P型掺杂。在其他一些实施例中，外延层120可为N型掺杂。在一个实施例中，在形成外延层120的过程中以及下文所要介绍的步骤中，掩埋层102可向上扩散至外延层120。如图6所示，掩埋层102向上扩散至外延层120。
如图7所示，所述制作流程包括在外延层120内形成N型阱区103和P型阱区104。在一个实施例中，N型阱区103和P型阱区104可通过注入技术或者扩散技术形成。
如图8所示，所述制作流程包括在外延层120上形成场氧106，所述外延层120的部分区域被所述场氧106所覆盖。在一个实施例中，场氧106通过湿法氧化技术形成。在图8所示实施例中，场氧102未被制作成浅沟道隔离结构。但在其他一些实施例中，场氧106可被制作成浅沟道隔离结构。
如图9a所示，所述制作流程包括在外延层120上形成栅氧107，在部分场氧106、部分外延层120和部分栅氧107上形成厚栅氧108，其中外延层120未被场氧106覆盖的区域被栅氧107和厚栅氧108覆盖。在一个实施例中，栅氧107通过干法氧化技术形成，厚栅氧108通过淀积技术形成。在其他实施例中，厚栅氧108可通过热氧化技术形成。由于厚栅氧108的厚度很薄，在图示中可能比较模糊，如图9b所示。
如图10所示，所述制作流程包括在场氧106、栅氧107和厚栅氧108上形成多晶硅栅，所述多晶硅栅包括终端部分109-1和普通部分109-2，所述终端部分109-1包括有源多晶硅81、形成在栅氧107和厚栅氧108上的第一延伸多晶硅82，以及形成在厚栅氧108和场氧106上的第二延伸多晶硅83。在一个实施例中，所述有源多晶硅81、第一延伸多晶硅82和第二延伸多晶硅83呈现为阶梯结构。
如图11所示，所述制作流程包括在N型阱区103内形成P型基区105。所述P型基区105和N型阱区103形成体-阱结31，所述体-阱结31在有源多晶硅81的下方。在一个实施例中，所述P型基区通过注入或者扩散技术形成。
如图12所示，所述制作流程包括在P型基区105内形成体接触区51和源接触区52，在N型阱区103内形成漏接触区53。其中体接触区51为P型掺杂，源接触区52和漏接触区53为N型掺杂，源接触区52毗邻体接触区51。在一个实施例中，部分栅氧107在体接触区51和源接触区52形成前被移除。在一个实施例中，体接触区51、源接触区52和漏接触区53通过注入技术形成。
如图13所示，所述制作流程包括形成与体接触区51和源接触区52接触的源极电极110、与漏接触区53接触的漏极电极111、以及与多晶硅栅的普通部分109-2接触的栅极电极112。
在一个实施例中，所述制作流程还包括：在N型阱区103形成之前，在外延层120内形成N型轻掺杂阱区，其中N型阱区103在之后的制作过程中形成在N型轻掺杂阱区内，如N型阱区103为N型轻掺杂阱区的一部分。在一个实施例中，N型轻掺杂阱区通过扩散技术或者注入技术形成。
与现有上拉DMOS相比，前述各实施例的上拉DMOS在小的终端面积情况下具有更高的击穿电压。不同于现有技术，前述各实施例的上拉DMOS在多晶硅栅的终端部分具有3个部分。此外，多晶硅栅终端部分的3个部分包括阶梯场板，以在小的终端面积条件下增大基-阱之间的击穿电压。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (10)

1.一种上拉双扩散金属氧化物半导体，包括：
具有第一掺杂类型的衬底；
形成在衬底上的外延层；
形成在外延层内具有第二掺杂类型的第一阱区；
形成在外延层内具有第一掺杂类型的第二阱区，所述第二阱区毗邻第一阱区；
形成在第一阱区内具有第一掺杂类型的基区，所述基区和第一阱区形成体-阱结；
形成在基区内的具有第一掺杂类型的体接触区；
形成在基区内的具有第二掺杂类型的源接触区，所述源接触区毗邻体接触区；
形成在第一阱区内的具有第二掺杂类型的漏接触区；
形成在外延层上的场氧；
形成在外延层上的栅氧；
厚栅氧，所述厚栅氧部分形成在栅氧上、部分形成在外延层上、部分形成在场氧上；
形成在场氧、栅氧和厚栅氧上的多晶硅栅，所述多晶硅栅包括终端部分和普通部分，所述终端部分包括在体-阱结上的有源多晶硅、在栅氧和厚栅氧上的第一延伸多晶硅、以及在厚栅氧和场氧上的第二延伸多晶硅。
2.如权利要求1所述的上拉双扩散金属氧化物半导体，其中所述有源多晶硅、第一延伸多晶硅和第二延伸多晶硅呈现为阶梯结构。
3.如权利要求1所述的上拉双扩散金属氧化物半导体，其中所述场氧具有浅沟道结构。
4.如权利要求1所述的上拉双扩散金属氧化物半导体，还包括：
与体接触区和源接触区接触的源极电极；
与漏接触区接触的漏极电极；以及
与多晶硅栅的普通部分接触的栅极电极。
5.如权利要求1所述的上拉双扩散金属氧化物半导体，还包括：形成在外延层内具有第二掺杂类型的轻掺杂区，所述第一阱区被所述轻掺杂阱区环绕。
6.如权利要求1所述的上拉双扩散金属氧化物半导体，还包括：形成在衬底内的具有第二掺杂类型的掩埋层。
7.一种制作上拉双扩散氧化物半导体的方法，包括：
在衬底上形成N型掩埋层；
在衬底上形成外延层；
在外延层内形成N型阱区和P型阱区；
在外延层上形成场氧，所述外延层的部分区域被所述场氧所覆盖；
在外延层上形成栅氧，在部分场氧、部分外延层和部分栅氧上形成厚栅氧，其中外延层未被场氧覆盖的区域被栅氧和厚栅氧覆盖；
在场氧、栅氧和厚栅氧上形成多晶硅栅，所述多晶硅栅包括终端部分和普通部分，所述终端部分包括有源多晶硅、形成在栅氧和厚栅氧上的第一延伸多晶硅，以及形成在厚栅氧和场氧上的第二延伸多晶硅；
在N型阱区内形成P型基区，所述P型基区和N型阱区形成体-阱结，所述体-阱结在有源多晶硅的下方；
在P型基区内形成体接触区和源接触区，在N型阱区内形成漏接触区；
形成与体接触区和源接触区接触的源极电极、与漏接触区接触的源极电极、以及与多晶硅栅的普通部分接触的栅极电极。
8.如权利要求7所述的制作方法，进一步包括：在N型阱区形成之前，在外延层内形成N型轻掺杂阱区，其中N型阱区在之后的制作过程中形成在所述N型轻掺杂阱区内。
9.如权利要求7所述的制作方法，其中所述有源多晶硅、第一延伸多晶硅和第二延伸多晶硅呈现为阶梯结构。
10.如权利要求7所述的制作方法，其中体接触区为P型掺杂，源接触区和漏接触区为N型掺杂，源接触区毗邻体接触区。
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