CN103094337B - Ldnmos结构及其制造方法 - Google Patents

Ldnmos结构及其制造方法 Download PDF

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CN103094337B
CN103094337B CN201110332290.6A CN201110332290A CN103094337B CN 103094337 B CN103094337 B CN 103094337B CN 201110332290 A CN201110332290 A CN 201110332290A CN 103094337 B CN103094337 B CN 103094337B
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凌龙
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

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Abstract

本发明提供了一种LDNMOS结构及其制造方法，通过在现有LDNMOS结构的N-漂移区刻蚀出沟槽，并外延生成SiC用以提高击穿电压，可使得N-漂移区的长度缩小，达到缩小LDNMOS尺寸，提高击穿电压的目的。

Description

LDNMOS结构及其制造方法
技术领域
本发明涉及半导体器件及其制造领域，尤其涉及一种LDNMOS(横向扩散N型金属氧化物半导体晶体管)结构及其制造方法。
背景技术
横向扩散N型金属氧化物半导体晶体管(Laterally Diffused N type MetalOxide semiconductor，LDNMOS)在集成电路设计与制造中有着重要地位。例如高压横向扩散N型金属氧化物半导体晶体管(HV LDNMOS)便被广泛使用在薄膜晶体管液晶显示屏的驱动芯片中。
现有的LDNMOS结构如图1所示，LDNMOS包括P型单晶Si基底1以及在基底1上形成的栅氧化层2和多晶硅栅极3。在P型单晶Si基底中具有包括形成了源区5的P阱4，P阱4可通过诸如硼的任何P型元素的离子注入或扩散来形成，源区5通过诸如砷的任何N型元素的离子注入或扩散来形成。在P型单晶Si基底1中还具有包括形成了漏区7的N-漂移区6，N-漂移区6是通过类似砷元素轻度掺杂扩散形成的，漏区7是通过类似的砷注入形成的，N-漂移区6还包括在多晶硅栅极3与漏区7之间设置的STI8。多晶硅栅极3对应的设置在N-漂移区6和P阱4上方。
当预制的栅极电压施加在多晶硅栅极3上时，P阱4中存在的少数载流子(电子)被吸引向栅极3，因而形成沟道区，沟道区将源区5连接到N-漂移区6。当源漏电压施加与LDNMOS时，源区5中存在的电子通过沟道区和N-漂移区途径STI的下方区域到达漏区7，使得LDNMOS导通。
因此，LDNMOS的基本结构构成即是在普通MOS结构基础上拉开漏极区到沟道区的距离，一般的是通过在漏极区到沟道区之间设置STI(ShallowTrench Isolation，浅沟槽隔离)以增大漏极区到沟道区以及漏极到源极的击穿电压，以实现能够承载高压的目的
由于LDNMOS多用于高于50V的工作电压下，击穿(berakdown)是非常重要的特性，为了提高器件的击穿特性，一般采取的手段是将漏极和栅极区之间的STI宽度尺寸变大，以确保器件不被击穿，这也使得LDNMOS的尺寸变得难以缩小，一般现有LDNMOS的制程多在0.18μm以上。鉴于集成电路日趋小型化的趋势，制造小尺寸LDNMOS，尤其是制造出90nm及以下的LDNMOS是目前亟待解决的问题。
发明内容
本发明提供了一种LDNMOS结构及其制造方法，在保证横向扩散金属氧化物半导体晶体管的击穿特性的同时，解决了横向扩散金属氧化物半导体晶体管小型化的问题。
本发明采用的技术手段如下：一种LDNMOS结构，包括P型单晶Si基底以及在P型基底上依次形成的栅氧化层及多晶硅栅极；所述P型基底包括P阱和N-漂移区，所述P阱中设置有源区，所述N-漂移区中设置有漏区；在所述N-漂移区中、漏区与多晶硅栅极之间设置有STI，其特征在于，所述N-漂移区的部分或全部由N-掺杂的SiC区构成。
进一步，所述N-掺杂的SiC区为圆弧型、梯形或矩形。
进一步，所述SiC中C原子的浓度为10％至20％。
本发明还提供了一种LDNMOS的制造方法，包括：
提供单晶Si基片；
掺杂单晶Si基片形成P型单晶Si基底；
在P型单晶Si基底上沉积一层氮化物；
在P型单晶Si基底上对应N-漂移区的位置刻蚀生成沟槽；
在所述沟槽中沉积SiC；
对所述P型单晶Si基片进行化学机械研磨去除多余SiC后，去除氮化物；
对所述SiC进行N-离子注入并扩散形成N-漂移区；
通过离子注入并扩散形成P阱；
在所述SiC中进行N+掺杂形成漏区；
在所述P阱中进行N+掺杂形成源区；
在所述N-漂移区形成STI；
在所述P型单晶Si基片上对应覆盖部分N-漂移区和部分P阱的位置形成栅氧化层和多晶硅栅极。
进一步，利用干法刻蚀生成所述沟槽，所述沟槽的形状为圆弧型、梯形或矩形。
进一步，沉积的所述SiC中C原子的浓度为10％至20％。
采用本发明的方法制作的LDNMOS，通过在N-漂移区刻蚀出沟槽，并外延生成SiC用以提高击穿电压，可使得N-漂移区的长度缩小，达到缩小LDNMOS尺寸，提高击穿电压的目的。
附图说明
图1为现有技术LDNMOS结构示意图；
图2为本发明LDNMOS结构示意图；
图3为本发明LDNMOS制造方法流程图。
具体实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
本发明提供的LDNMOS结构，如图2所示，包括P型单晶Si基底11以及在P型基底11上依次形成的栅氧化层12及多晶硅栅极13；P型基底11包括P阱14和N-漂移区16，P阱14中设置有源区15，N-漂移区16中设置有漏区17；在N-漂移区16中、漏区17与多晶硅栅极13之间设置有STI18。其中，N-漂移区16的部分由N-掺杂的SiC区19构成，N-掺杂的SiC区为圆弧型、梯形或矩形，优选的，SiC中C原子的浓度为10％至20％。作为本领域人员可知的，N-漂移区16的全部也可以由N-掺杂的SiC区19构成。
本发明还提供了一种LDNMOS的制造方法，如图3的流程图所示，包括步骤：
提供单晶Si基片；
掺杂单晶Si基片形成P型单晶Si基底；
在P型单晶Si基底上沉积一层氮化物；
在P型单晶Si基底上对应N-漂移区的位置刻蚀生成沟槽，优选的通过干法刻蚀形成沟槽，沟槽形状可以是圆弧型、梯形或矩形；
在沟槽中沉积SiC，优选SiC中C的原子浓度为10％至20％；
对P型单晶Si基片进行化学机械研磨去除多余SiC后，去除氮化物；
对SiC进行N-离子注入并扩散形成N-漂移区；
通过离子注入并扩散形成P阱；
在SiC中进行N+掺杂形成漏区；
在P阱中进行N+掺杂形成源区；
在N-漂移区形成STI；
在P型单晶Si基片上对应覆盖部分N-漂移区和部分P阱的位置形成栅氧化层和多晶硅栅极。
采用本发明的方法制作的LDNMOS，通过在N-漂移区刻蚀出沟槽，并外延生成SiC用以提高击穿电压，可使得N-漂移区的长度缩小，达到缩小LDNMOS尺寸，提高击穿电压的目的。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。

Claims (3)

1.一种LDNMOS的制造方法，包括：
提供单晶Si基片；
掺杂单晶Si基片形成P型单晶Si基底；
在P型单晶Si基底上沉积一层氮化物；
在P型单晶Si基底上对应N-漂移区的位置刻蚀生成沟槽；
在所述沟槽中沉积SiC；
对所述P型单晶Si基片进行化学机械研磨去除多余SiC后，去除氮化物；
对所述SiC进行N-离子注入并扩散形成N-漂移区；
通过离子注入并扩散形成P阱；
在所述SiC中进行N+掺杂形成漏区；
在所述P阱中进行N+掺杂形成源区；
在所述N-漂移区形成STI；
在所述P型单晶Si基片上对应覆盖部分N-漂移区和部分P阱的位置形成栅氧化层和多晶硅栅极。
2.根据权利要求1所述的方法，其特征在于，利用干法刻蚀生成所述沟槽，所述沟槽的形状为圆弧型、梯形或矩形。
3.根据权利要求1或2所述的方法，其特征在于，沉积的所述SiC中C原子的浓度为10％至20％。
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EP4272240A4 (en) * 2020-12-29 2024-02-21 Texas Instruments Inc HYBRID SEMICONDUCTOR COMPONENT

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CN101872786A (zh) * 2010-06-11 2010-10-27 东南大学 带浮置埋层的碳化硅高压n型金属氧化物半导体管及方法

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