CN102130162A - Ldmos及其制造方法 - Google Patents
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Abstract
本发明公开了一种LDMOS，与传统的LDMOS相比，本发明的创新之处在于，在n阱(12)中、且仅在源极(181)和漏极(182)之间的隔离结构(13)靠近漏极(182)一侧的侧壁和/或底部处新增p型离子注入区(20)。新增加的p型离子注入区20可改变电荷分布及耗尽区的形貌，提高LDMOS器件的击穿电压，同时保持了LDMOS器件的导通电阻基本不受影响，实现了击穿电压BV与导通电阻Rdson之间的较好平衡。
Description
技术领域
本发明涉及一种半导体集成电路器件，特别是涉及一种LDMOS(laterally diffused MOSFET，横向扩散MOS晶体管)器件。
背景技术
请参阅图1，这是传统的LDMOS器件的剖面示意图。在p型硅衬底10上具有p型外延层11和n阱12。由于n阱12较深，通常也称为深n阱12。在n阱12中具有隔离结构13和低压p阱14。n阱12之上为栅氧化层15和栅极16，栅极16的四周都被介质包围而成为浮栅。栅极16的一端在低压p阱14之上，另一端在隔离结构13之上。低压p阱14中具有n型轻掺杂漏注入区17和n型重掺杂漏注入区181，n型重掺杂漏注入区181作为LDMOS器件的源极。n阱12中也具有一个n型重掺杂漏注入区182，作为LDMOS器件的漏极。
图1所示的LDMOS器件，将各部分掺杂类型相反，也是可行的。
击穿电压对LDMOS器件而言是一个很重要的指标，击穿电压的调整一般都是通过改变漂移区的掺杂浓度、或是调整漂移区的宽度来实现的。这些改变或者对器件的导通电阻Rdson、饱和电流等参数影响比较大，或者会引起器件的面积增大。图1所示的LDMOS器件的漂移区为深n阱12。
发明内容
本发明所要解决的技术问题是提供一种LDMOS器件，可以具有较高的击穿电压。为此，本发明还要提供所述LDMOS器件的制造方法。
为解决上述技术问题，本发明LDMOS器件为：在硅衬底10上具有外延层11和阱12；阱12中具有隔离结构13和阱14；阱12中、且仅在源极和漏极之间的隔离结构13靠近漏极182一侧的侧壁和/或底部处具有离子注入区20；所述离子注入区20与阱12的掺杂类型相反；阱12之上为栅氧化层15和栅极16，栅极16的一端在阱14之上，另一端在隔离结构13之上；阱14中具有轻掺杂漏注入区17和重掺杂漏注入区181，重掺杂漏注入区181作为LDMOS器件的源极；阱12中也具有一个重掺杂漏注入区182，作为LDMOS器件的漏极。
本发明LDMOS器件的制造方法包括如下步骤：
第1步，在硅衬底10上制造外延层11和阱12；
第2步，在阱12的表面刻蚀沟槽，填充所述沟槽形成隔离结构13；
第3步，采用光刻和离子注入工艺，在阱12中，且仅在源极和漏极之间的隔离结构13靠近漏极一侧的侧壁和/或底部处形成与阱12掺杂类型相反的离子注入区20；
第4步，在阱12中形成阱14，在硅片表面制造栅氧化层15和多晶硅栅极16；
第5步，在阱14中形成轻掺杂漏注入区17和重掺杂漏注入区181，所述重掺杂漏注入区181作为LDMOS器件的源极；
在阱12中形成重掺杂漏注入区182，作为LDMOS器件的漏极。
本发明LDMOS器件在源极和漏极之间的隔离结构13靠近漏极一侧的侧壁和/或底部形成了一个与漂移区(即阱12)掺杂类型相反的离子注入区20，改变了LDMOS器件的电荷分布及耗尽区形貌，提高了LDMOS的击穿电压，同时保持了LDMOS器件的导通电阻基本不受影响，实现了击穿电压BV与导通电阻Rdson之间的较好平衡。
附图说明
图1是现有的LDMOS器件的剖面示意图；
图2是本发明LDMOS器件的剖面示意图；
图3是本发明LDMOS器件的制造方法的示意图。
图中附图标记说明：
10为p型衬底；11为p型外延层；12为n阱；13为隔离结构；14为低压p阱；15为栅氧化层；16为多晶硅栅极；17为n型轻掺杂漏注入区；181、182为n型重掺杂漏注入区；20为p型离子注入区；30为光刻胶。
具体实施方式
请参阅图2，本发明LDMOS器件为：在p型硅衬底10上具有p型外延层11和n阱12。由于n阱12较深，通常也称为深n阱12。在n阱12中具有隔离结构13和低压p阱14。n阱12之上为栅氧化层15和栅极16，栅极16的四周都被介质包围而成为浮栅。栅极16的一端在低压p阱14之上，另一端在隔离结构13之上。低压p阱14中具有n型轻掺杂漏注入区17和n型重掺杂漏注入区181，n型重掺杂漏注入区181作为LDMOS器件的源极。n阱12中也具有一个n型重掺杂漏注入区182，作为LDMOS器件的漏极。
与传统的LDMOS器件相比，本发明的创新之处在于，在n阱12中、且仅在源极181和漏极182之间的隔离结构13靠近漏极182一侧的侧壁和/或底部处新增p型离子注入区20(如图2所示)。新增加的p型离子注入区20可改变电荷分布及耗尽区的形貌，提高LDMOS器件的击穿电压。
在n阱12中、且在隔离结构13临近源极181一侧的侧壁和/或底部处没有p型离子注入区。这是由于隔离结构与源端181之间为主要导电通道，若该主要导电通道也增加p型离子注入区，则该主要导电通道会变夹窄，使得导通电阻被明显提高。本发明对p型离子注入区20的位置进行了巧妙地设置，既可以提高击穿电压，同时又尽可能维持导通电阻不变。通过TCAD软件仿真表明，本发明将碰撞电离从LDMOS器件的表面往内部推，增强了LDMOS器件的可靠性，同时可将击穿电压提高至少3V。
图2所示的LDMOS器件，将各部分掺杂类型相反，则为本发明的另一实施例。
本发明LDMOS器件的制造方法包括如下步骤(以n型LDMOS为例进行介绍，p型LDMOS只需将各步骤的离子注入类型相反，各部分结构的掺杂类型相反即可)：
第1步，在p型硅衬底10上外延生长一层p型外延层11(即淀积一层p型单晶硅)，然后在p型外延层11中进行n型杂质的离子注入，常见的n型杂质如磷、砷、锑等，然后进行退火工艺，在p型外延层11的表面形成n阱12。
第2步，在n阱12的表面刻蚀沟槽，在沟槽的侧壁和底部氧化生长一层衬垫氧化层(未图示)，再在硅片表面淀积一层介质，所述介质例如氧化硅、氮化硅、氮氧化硅等。该层介质至少将沟槽完全填充，再将所淀积的介质研磨至与n阱12的上表面齐平，形成隔离结构13。
第3步，请参阅图3，在硅片表面旋涂光刻胶30，曝光、显影后仅暴露出源极和漏极之间的隔离结构13靠近漏极一侧的区域，在该区域进行p型杂质注入，常见的p型杂质如硼等，然后进行退火工艺，从而在n阱12中、且靠近隔离结构13临近漏极一侧的侧壁和/或底部处形成p型离子注入区20，最后去除光刻胶30。
这一步离子注入的能量为80～120KeV，剂量为1×1013～5×1013原子每平方厘米(或离子每平方厘米)。
第4步，在n阱12中进行p型杂质注入形成低压p阱14，在硅片表面生长一层氧化硅，再淀积一层多晶硅，刻蚀该层多晶硅和氧化硅从而形成多晶硅栅极16和栅氧化层15；多晶硅栅极16的一侧在隔离结构13之上，另一侧在低压p阱14之上。
第5步，在多晶硅栅极16靠近源端的一侧进行n型杂质的轻掺杂漏注入(LDD)，从而在低压p阱14中形成n型轻掺杂漏注入区17。在栅氧化层15和栅极16的两侧制造侧墙。然后在所述侧墙外侧进行n型杂质的源漏注入，从而在低压p阱14中形成n型重掺杂漏注入区181，作为LDMOS器件的源极。
在n阱12中也进行n型杂质的源漏注入，从而在n阱12中形成n型重掺杂漏注入区182，作为LDMOS器件的漏极。
所述方法第4步和第5步中，离子注入的阻挡层均为光刻胶；即均先用光刻工艺定义离子注入区域。
与传统LDMOS器件的制造方法相比，本发明仅新增了第3步，其余各步骤工艺均为传统LDMOS器件的制造工艺。
上述实施例中的结构、步骤、数值等均为示意，在不违反本发明思想的前提下，本领域的一般技术人员可以进行等同替换，这些都仍属于本发明的保护范围之内。
Claims (5)
1.一种LDMOS，其特征是，所述LDMOS为：在硅衬底(10)上具有外延层(11)和阱(12)；阱(12)中具有隔离结构(13)和阱(14)；阱(12)中、且仅在源极和漏极之间的隔离结构(13)靠近漏极(182)一侧的侧壁和/或底部处具有离子注入区(20)；所述离子注入区(20)与阱(12)的掺杂类型相反；阱(12)之上为栅氧化层(15)和栅极(16)，栅极(16)的一端在阱(14)之上，另一端在隔离结构(13)之上；阱(14)中具有轻掺杂漏注入区(17)和重掺杂漏注入区(181)，重掺杂漏注入区(181)作为LDMOS器件的源极；阱(12)中也具有一个重掺杂漏注入区(182)，作为LDMOS器件的漏极。
2.根据权利要求1所述的LDMOS，其特征是，所述硅衬底(10)、外延层(11)、阱(14)为p型；阱(12)、轻掺杂漏注入区(17)、重掺杂漏注入区(181)、重掺杂漏注入区(182)为n型。
3.根据权利要求1所述的LDMOS，其特征是，所述硅衬底(10)、外延层(11)、阱(14)为n型；阱(12)、轻掺杂漏注入区(17)、重掺杂漏注入区(181)、重掺杂漏注入区(182)为p型。
4.如权利要求1所述的LDMOS的制造方法，其特征是，包括如下步骤：
第1步，在硅衬底(10)上制造外延层(11)和阱(12)；
第2步，在阱(12)的表面刻蚀沟槽，填充所述沟槽形成隔离结构(13)；
第3步，采用光刻和离子注入工艺，在阱(12)中，且仅在源极和漏极之间的隔离结构(13)靠近漏极一侧的侧壁和/或底部处形成与阱(12)掺杂类型相反的离子注入区(20)；
第4步，在阱(12)中形成阱(14)，在硅片表面制造栅氧化层(15)和多晶硅栅极(16)；
第5步，在阱(14)中形成轻掺杂漏注入区(17)和重掺杂漏注入区(181)，所述重掺杂漏注入区(181)作为LDMOS器件的源极；
在阱(12)中形成重掺杂漏注入区(182)，作为LDMOS器件的漏极。
5.根据权利要求4所述的LDMOS的制造方法，其特征是，所述方法第3步中，离子注入的能量为80～120KeV，剂量为1×1013～5×1013原子每平方厘米。
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094337A (zh) * | 2011-10-27 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Ldnmos结构及其制造方法 |
| CN104282563A (zh) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Ldmos器件及其形成方法 |
| CN108288645A (zh) * | 2017-01-09 | 2018-07-17 | 立锜科技股份有限公司 | 高压元件及其制造方法 |
| CN113764502A (zh) * | 2020-06-02 | 2021-12-07 | 芯恩（青岛）集成电路有限公司 | 一种ldmos半导体器件及其制造方法 |
| CN113764502B (zh) * | 2020-06-02 | 2024-05-31 | 芯恩（青岛）集成电路有限公司 | 一种ldmos半导体器件及其制造方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1046823C (zh) * | 1995-10-24 | 1999-11-24 | 台湾茂矽电子股份有限公司 | 具有倒t型栅极mos晶体管的低度掺杂漏极的制造方法及其结构 |
| US6903421B1 (en) * | 2004-01-16 | 2005-06-07 | System General Corp. | Isolated high-voltage LDMOS transistor having a split well structure |
| KR100840667B1 (ko) * | 2007-06-26 | 2008-06-24 | 주식회사 동부하이텍 | 수평형 디모스 소자 및 그 제조방법 |
| KR100877674B1 (ko) * | 2007-09-12 | 2009-01-08 | 주식회사 동부하이텍 | Ｌｄｍｏｓ 소자 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094337A (zh) * | 2011-10-27 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Ldnmos结构及其制造方法 |
| CN103094337B (zh) * | 2011-10-27 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Ldnmos结构及其制造方法 |
| CN104282563A (zh) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Ldmos器件及其形成方法 |
| CN108288645A (zh) * | 2017-01-09 | 2018-07-17 | 立锜科技股份有限公司 | 高压元件及其制造方法 |
| CN113764502A (zh) * | 2020-06-02 | 2021-12-07 | 芯恩（青岛）集成电路有限公司 | 一种ldmos半导体器件及其制造方法 |
| CN113764502B (zh) * | 2020-06-02 | 2024-05-31 | 芯恩（青岛）集成电路有限公司 | 一种ldmos半导体器件及其制造方法 |
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