CN113964118A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN113964118A
CN113964118A CN202010699036.9A CN202010699036A CN113964118A CN 113964118 A CN113964118 A CN 113964118A CN 202010699036 A CN202010699036 A CN 202010699036A CN 113964118 A CN113964118 A CN 113964118A
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deep well
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field oxide
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layer
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CN113964118B (zh
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冒义祥
张兰
周俊芳
韩晨彬
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Abstract

本发明公开了一种半导体器件，该半导体器件包括：半导体衬底，其上形成有场氧化层，半导体衬底具有第一导电类型；电阻层，形成在场氧化层之上，具有高电位连接端和低电位连接端；深阱，形成在所述半导体衬底中，电阻层位于所述深阱之上的区域，深阱具有第二导电类型，第二导电类型与第一导电类型相反；深阱引出端，形成在所述深阱中；衬底引出端，形成在所述半导体衬底中，并且位于所述深阱之外；高电位连接端和深阱引出端连接至高电位焊盘，低电位连接端和衬底引出端连接至低电位焊盘。根据本发明实施例高压分压电阻无需额外加厚的场氧化层，因此减少了相应的工艺步骤，并且耐压测试可重复，且不会导致场氧化层损坏或者测试针卡烧毁。

Description

半导体器件
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件。
背景技术
目前在BCD(Bipolar-CMOS-DMOS)工艺中实现超高压分压电阻的应用需求越来越广泛。目前的超高压电阻的设计方法一般是在一层很厚的场氧化层(FOX，Field Oxide)上做多晶电阻，其要求场氧化层的厚度能够承受700V甚至以上的耐压需求。为了实现这个目的，工艺上需要多做一层光刻，用湿氧氧化来生长一层
Figure BDA0002592332940000011
以上的场氧化层。这种方法不仅使得工艺成本和流通时间都增加了不少，而且对场氧化层的厚度和绝缘性都提出了很高的要求。另外这种结构的电阻的耐压测试属于场氧化层的热电击穿，而一般击穿后场氧化层会被损坏，且是一种不可逆的损伤；另外高电压下场氧化层损伤后的突然短路很容易烧毁测试针卡，这将造成测试针卡的过度消耗。
发明内容
为了解决上述问题中的至少一个而提出了本发明。具体地，本发明一方面提供一种半导体器件，其包括：
半导体衬底，所述半导体衬底上形成有场氧化层，所述半导体衬底具有第一导电类型；
电阻层，所述电阻层形成在所述场氧化层之上，所述电阻层具有高电位连接端和低电位连接端；
深阱，所述深阱形成在所述半导体衬底中，所述电阻层位于所述深阱之上的区域，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反；
深阱引出端，所述深阱引出端形成在所述深阱中；
衬底引出端，所述衬底引出端形成在所述半导体衬底中，并且位于所述深阱之外；
其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低电位连接端和所述衬底引出端连接至低电位焊盘。
在本发明一实施例中，还包括：
第一阱区，所述第一阱区形成在所述深阱中，并且具有第二导电类型，所述深阱引出端形成在所述第一阱区中。
在本发明一实施例中，还包括：
第二阱区，所述第二阱区包括形成在所述深阱中的第一区域和形成在所述深阱之外的第二区域，所述第一区域和所述第二区域电连接，所述第二阱区具有第一导电类型，所述衬底引出端形成在所述第二区域中。
在本发明一实施例中，所述电阻层呈环状结构。
在本发明一实施例中，所述电阻层包括依次首尾相接的多圈电阻线。
在本发明一实施例中，所述深阱引出端形成在所述环状结构的中心区域。
在本发明一实施例中，所述高电位连接端位于所述电阻线处于靠近所述环状结构中心的一侧，所述低电位连接端位于所述电阻线处于靠近所述环状结构边缘的一侧。
在本发明一实施例中，所述衬底引出端呈环状结构，且环绕所述深阱设置。
在本发明一实施例中，所述第一导电类型为P型，所述第二导电类型为N型。
在本发明一实施例中，所述深阱引出端为N+注入区，所述衬底引出端为P+注入区。
在本发明一实施例中，所述电阻层采用多晶硅制作。
在本发明一实施例中，，所述场氧化层的厚度为
Figure BDA0002592332940000021
所述半导体衬底包括晶体管区域和电阻区域，所述晶体管区域中的所述场氧化层的厚度与所述电阻区域中的所述场氧化层的厚度相同。
根据本发明的半导体器件，通过增加一个与衬底导电类型相反的深阱，并将深阱与电阻层的高电位连接端短接，将所述衬底与所述电阻层的低电位连接端连接至低电位，这样相当于在电阻方向上并联的了高压PN二极管，将高电电阻下的场氧化层承受的高电场和耐压转移到了深阱和衬底的耗尽层内，因此无需使用厚度很多的场氧化层，减少了之前形成厚场氧化层的工艺步骤，并且由于新结构的PN结雪崩击穿属于可逆过程，与目前的场氧化层热击穿相比，不会烧毁测试针卡。
本发明再一方面提供一种电子装置，其包括如上所述的半导体器件以及与所述半导体器件相连接的电子组件。
本发明提出的电子装置，由于具有上述半导体器件，因而具有类似的优点。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出目前一种高压电阻结构的示意性剖面图；
图2示出图1所示高压电阻结构的示意性布图；
图3示出根据本发明一实施例的高压电阻结构的示意性剖面图；
图4示出根据本发明一实施例的高压电阻结构的示意性布图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的结构，以便阐释本发明提出的技术方案。本发明的可选实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
首先，结合图1至图2对目前的高压分压电阻结构进行描述。如图1所示，目前在诸如BCD工艺制作的器件中的高压分压电阻的结构包括衬底100，形成在衬底100之上的场氧化层101和位于场氧化层101之上的电阻层102(例如多晶硅层)，电阻层102的两端通过接触孔103引出至互连线104，并通过互连线104分别连接至高电位焊盘和低电位焊盘，以将高电压施加在电阻两端。如图2所示，在目前的高压分压电阻结构中，电阻层102采用环状设计，高电位端口(连接高电位接触孔的一端)设置在环状内侧，低电位端口(连接低电位接触孔的一端)设置在环状在外侧。
在很多应用中，高压分压电阻的高电位端口需要能承受700V甚至以上电压，当高电压加在电阻层102(多晶硅层)上时，场氧化层101需要承受非常大的纵向电场(因为衬底100一般接低电位)，且场氧化层101越薄，电场就会越大。为了不让场氧化层101承受的电场达到击穿场强，在工艺上就需要加厚电阻层102下面的场氧化层101的厚度，为了实现这个目的，目前工艺上采取的方法是增加一次单独的光刻步骤来生长这个非常厚的氧化层。目前这种工艺的基本流程包括：第一步，制作深N阱；第二步，制作牺牲氧化层和氮化硅层(用作厚FOX的遮蔽层)；第三步，进行厚场氧化层的光刻工艺，以及该区域氮化硅层的腐蚀；第四步，通过湿氧氧化工艺生长厚场氧化层(例如
Figure BDA0002592332940000051
)；第五步，制作N阱/P阱；第六步，制作有源区(或SDG层)；第七步，制作N型场注入层；第八步，制作正常的场氧化层；第九步，制作栅极氧化层；第十步，制作多晶硅层。其中，第二至第四步是为了形成高压分压电阻所需的厚场氧化层增加的工艺步骤，可见目前这种工艺的复杂性大大增加。且除工艺上复杂外，现有结构在测试耐压上也有显著的缺点，因为加高电位时其电压几乎全部由场氧化层来承受，在达到场氧化层的击穿场强后场氧化层发生热电损伤，造成高电位端到衬底的永久电流通路，所以一个模块在击穿后会彻底失效。而且场氧化层在击穿后其阻抗会突然降低为很小甚至为零，由于多晶硅电阻的高电位端仍然有很高的电压，这会导致一个非常大的电流流过测试针卡，很容易造成测试针卡的损坏。
本发明基于此提出一种半导体器件及其制作方法，以至少克服上述部分缺点。
图3示出根据本发明一实施例的高压电阻结构的示意性剖面图；图4示出根据本发明一实施例的高压电阻结构的示意性布图。下面结合图3至图4对根据本发明实施例的高压电阻结构进行详细描述。
如图3所示，本实施例的高压电阻结构包括衬底200、深阱201、第一阱区202、第二阱区203、深阱引出端204、衬底引出端205、场氧化层206、电阻层207、导电插塞208和互连层209。
其中，半导体衬底200可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底200的构成材料选用单晶硅。示例性地，在本实施例中，半导体衬底200具有第一导电类型，所述第一导电类型例如为P型，即半导体衬底200为P型半导体衬底。应该理解，在其它实施例中，半导体衬底衬底200也可以为N形成衬底。
深阱201形成在所述半导体衬底200中，所述深阱201具有第二导电类型，所述第二导电类型与所述第一导电类型相反。示例性地，在本实施例中，深阱201为N型，即深阱201为深N阱。在本文中深阱中的深表示其注入深度比其他阱区更深，而不表示具体注入深度。深阱201可以通过向衬底200中注入设计要求的掺杂离子形成，例如注入注入磷的N型掺杂离子形成。深阱201的具体注入深度、掺杂浓度等根据具体设计要求确定，在此不做具体限定。
所述第一阱区202形成在所述深阱201中，并且具有第二导电类型，所述深阱引出端204形成在所述第一阱区202中。所述第一阱区202和所述深阱引出端204用于实现深阱201与外部的电连接。示例性地，所述第一阱区202为N阱，所述深阱引出端204为N+注入区。所述第一阱区202和所述深阱引出端204可以通过离子注入形成，具体注入深度、掺杂浓度等根据具体设计要求确定，在此不做具体限定。
所述第二阱区203包括形成在所述深阱210中的第一区域和形成在所述深阱201之外的第二区域，所述第一区域和所述第二区域电连接，所述第二阱区203具有第一导电类型，所述衬底引出端205形成在所述第二区域中。示例性地，在本实施例中，第二阱区203为P阱，衬底引出端205为P+注入区。所述第二阱区203和所述衬底引出端205可以通过离子注入形成，具体注入深度、掺杂浓度等根据具体设计要求确定，在此不做具体限定。
场氧化层206形成在衬底200之上，场氧化层206用于实现各有源区或晶体管的隔离。场氧化层206可以通过常用方法形成，比如热氧化法、湿氧氧化法等。
电阻层207形成在场氧化层206之上，并且位于深阱201之上的区域中，即电阻层207形成在深阱201所在的半导体衬底之上。示例性地，电阻层207可以采用多晶硅制作，换言之电阻层207是多晶硅层，其可以通过常用的多晶硅沉积工艺形成，例如PVD(物理气相沉积)、CVD(化学气相沉积)、ALD(原子层沉积)工艺。电阻层207的厚度根据设计要求确定，在此不做具体限定。所述电阻层207具有高电位连接端2071和低电位连接端2072(参见图4)，用于与高电位焊盘和低电位焊盘连接。
导电插塞208形成在深阱引出端204、衬底引出端205、电阻层207之上，以将电阻层207、深阱201和衬底200引出与外部进行电连接。
互连层209用于实现各器件结构的电连接，在本实施例中，互连层209用于实现深阱引出端204、衬底引出端205、电阻层207与高电位焊盘或低电位焊盘的电连接。应当理解，导电插塞208和互连层209形成在层间介电层中，图3中出于简洁目的并未示出。
如图3所示，在本实施例中，电阻层207的一端通过高电位连接端2071、导电插塞208、互连层209与高电位焊盘连接，以连接高电压；另一端通过低电位连接端2072、导电插塞208、互连层209与低电位焊盘连接，以连接至低电压(例如接地)。这样就可以将高电压施加在电阻层207上，同时，在本实施例中，为了不需要制作很厚的场氧化层，制作了深阱201，并且通过第一阱区202、深阱引出端204、导电插塞208和互连层209将深阱201连接至高电位焊盘，换言之，将电阻层207的高压端短接到深阱内。同时，通过衬底引出端205、导电插塞208和互连层209将衬底20和第二阱区203连接至低电位焊盘，这样，将相当于在电阻层207的两端并联了一个高压PN二极管，并且是阴极连接高电压，阳极连接低电压(即反接的高压PN二极管)。当电阻层207承受高压时，其高压主要由深阱201(深N阱)与衬底200(P-SUB)和第二阱区203(PW)的耗尽层来承担，而电阻层207和下方硅表面(深阱201表面)基本等电位，所施加在场氧化层206上的纵向电场很小，因此不需要额外的加厚场氧化层的厚度。换言之，本实施例的高压电阻结构实现了高压电场从场氧化层向PN结耗尽区的转移，这样电阻层下方的场氧化层使用正常的厚度即可，无需增加工艺步骤制作加厚的场氧化层。
请参阅图4，在本实施例中，电阻层207呈环状结构，其包括依次首尾相接的多圈电阻线。即电阻层207由一圈又一圈彼此连接的多晶硅线构成，其中内圈的端点作为高电位连接端2071，外圈的端点与衬底引出端205连接，作为低电位连接端2072。换言之，所述高电位连接端2071位于所述电阻线处于靠近所述环状结构中心的一侧，所述低电位连接端2072位于所述电阻线处于靠近所述环状结构边缘的一侧。相应地，在本实施例中，所述深阱引出端204(即N+注入区)形成在所述环状结构的中心区域，并且示例性地，深阱引出端204呈圆形。所述衬底引出端205呈环状结构，且环绕所述深阱201设置。
如图4所示，在本实施例中，高压电阻结构采用圆形布局，高压端位于中心区域，低压端位于边缘区域，这样更有利于PN结中电荷平衡和耐压的稳定性。
如上所述，本实施例的高压电阻结构耐压主要由Deep-NW(深阱201)与P-SUB(衬底200)&PW(第二阱区203)的耗尽层来承担，因此只需调整Deep-NW(深阱201)的长度就能实现不同档位高压电阻的需求，另外新结构深阱201采用圆形的布局，高压端位于中心，低压端位于边缘，新增的衬底引出端作为P/N结的阳极，此结构在N、P电荷平衡上更好，其在耐压的稳定性上也更好。另外本实施例的高压电阻结构的击穿属于雪崩击穿，其不仅属于可逆过程，且雪崩击穿的电流相比热电击穿很小，因此不会损伤测试针卡。
如上所述，本实施例的高压电阻结构，无需增加工艺步骤制作加厚的场氧化层，因此制作本实施例的高压电阻结构基本流程包括：第一步，制作深N阱(即在衬底200中形成深阱201)；第二步，制作NW/PW层(即形成第一阱区202和第二阱区203)；第三步，制作有源区(即形成深阱引出端204和衬底引出端205以及其他区域的源漏区注入)；第四步，制作N型场注入层(即对场区进行离子注入)；第五步，制作正常的场氧化层(即制作场氧化层207和其他区域的场氧化层)；第六步，制作栅极氧化层；第七步，制作多晶硅层(形成电阻层207和其他区域的栅极层)。通过与前述对比可知，制作本实施例的高压电阻结构，工艺步骤可以目前BCD工艺的常规步骤即可实现，无需增加前述制作加厚场氧化层的额外步骤，因此目前的高压电阻制作工艺相比，减少了工艺步骤，降低了工艺难度和成本。
本发明的另一个方面还提供一种电子装置，包括半导体器件以及与所述半导体器件相连的电子组件。其中，该半导体器件包括：半导体衬底，所述半导体衬底上形成有场氧化层，所述半导体衬底具有第一导电类型；电阻层，所述电阻层形成在所述场氧化层之上，所述电阻层具有高电位连接端和低电位连接端；深阱，所述深阱形成在所述半导体衬底中，所述电阻层位于所述深阱之上的区域，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反；深阱引出端，所述深阱引出端形成在所述深阱中；衬底引出端，所述衬底引出端形成在所述半导体衬底中，并且位于所述深阱之外；其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低电位连接端和所述衬底引出端连接至低电位焊盘。
进一步地，该半导体器件还包括：第一阱区，所述第一阱区形成在所述深阱中，并且具有第二导电类型，所述深阱引出端形成在所述第一阱区中。
进一步地，该半导体器件还包括：第二阱区，所述第二阱区包括形成在所述深阱中的第一区域和形成在所述深阱之外的第二区域，所述第一区域和所述第二区域电连接，所述第二阱区具有第一导电类型，所述衬底引出端形成在所述第二区域中。
其中，该电子组件，可以为分立器件、集成电路等任何电子组件。
本发明实施例的电子装置，由于所包含的ESD保护器件可以在增加维持电压同时增大ESD鲁棒性，增加了电流泄放能力，因此可以实现更好的ESD防护效果。因此该电子装置同样具有类似的优点。
尽管这里已经参考附图描述了示例实施例，应理解上述示例实施例仅仅是示例性的，并且不意图将本发明的范围限制于此。本领域普通技术人员可以在其中进行各种改变和修改，而不偏离本发明的范围和精神。所有这些改变和修改意在被包括在所附权利要求所要求的本发明的范围之内。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本发明并帮助理解各个发明方面中的一个或多个，在对本发明的示例性实施例的描述中，本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该本发明的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如相应的权利要求书所反映的那样，其发明点在于可以用少于某个公开的单个实施例的所有特征的特征来解决相应的技术问题。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本发明的单独实施例。
本领域的技术人员可以理解，除了特征之间相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本发明的范围之内并且形成不同的实施例。例如，在权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。

Claims (10)

1.一种半导体器件，其特征在于，包括：
半导体衬底，所述半导体衬底上形成有场氧化层，所述半导体衬底具有第一导电类型；
电阻层，所述电阻层形成在所述场氧化层之上，所述电阻层具有高电位连接端和低电位连接端；
深阱，所述深阱形成在所述半导体衬底中，所述电阻层位于所述深阱之上的区域，所述深阱具有第二导电类型，所述第二导电类型与所述第一导电类型相反；
深阱引出端，所述深阱引出端形成在所述深阱中；
衬底引出端，所述衬底引出端形成在所述半导体衬底中，并且位于所述深阱之外；
其中，所述高电位连接端和所述深阱引出端连接至高电位焊盘，所述低电位连接端和所述衬底引出端连接至低电位焊盘。
2.根据权利要求1所述的半导体器件，其特征在于，还包括：
第一阱区，所述第一阱区形成在所述深阱中，并且具有第二导电类型，所述深阱引出端形成在所述第一阱区中。
3.根据权利要求2所述的半导体器件，其特征在于，还包括：
第二阱区，所述第二阱区包括形成在所述深阱中的第一区域和形成在所述深阱之外的第二区域，所述第一区域和所述第二区域电连接，所述第二阱区具有第一导电类型，所述衬底引出端形成在所述第二区域中。
4.根据权利要求1-3中的任一项所述的半导体器件，其特征在于，所述电阻层呈环状结构。
5.根据权利要求4所述的半导体器件，其特征在于，所述电阻层包括依次首尾相接的多圈电阻线。
6.根据权利要求4所述的半导体器件，其特征在于，所述深阱引出端形成在所述环状结构的中心区域。
7.根据权利要求4所述的半导体器件，其特征在于，所述高电位连接端位于所述电阻线处于靠近所述环状结构中心的一侧，所述低电位连接端位于所述电阻线处于靠近所述环状结构边缘的一侧。
8.根据权利要求4所述的半导体器件，其特征在于，所述衬底引出端呈环状结构，且环绕所述深阱设置。
9.根据权利要求1所述的半导体器件，其特征在于，所述场氧化层的厚度为
Figure FDA0002592332930000021
所述半导体衬底包括晶体管区域和电阻区域，所述晶体管区域中的所述场氧化层的厚度与所述电阻区域中的所述场氧化层的厚度相同。
10.根据权利要求1所述的半导体器件，其特征在于，所述电阻层采用多晶硅制作。
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CN109216176A (zh) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 高压电阻器件
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