WO2022012255A1 - 半导体芯片的测试方法、测试系统及测试设备 - Google Patents

半导体芯片的测试方法、测试系统及测试设备 Download PDF

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WO2022012255A1
WO2022012255A1 PCT/CN2021/100358 CN2021100358W WO2022012255A1 WO 2022012255 A1 WO2022012255 A1 WO 2022012255A1 CN 2021100358 W CN2021100358 W CN 2021100358W WO 2022012255 A1 WO2022012255 A1 WO 2022012255A1
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abnormal
chip
read
test
write function
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French (fr)
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杨正杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1206—Location of test circuitry on chip or wafer

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a semiconductor chip testing method, testing system and testing equipment.
  • failure modes include column, row, block, single bit, double bit and other failure modes.
  • One aspect of the present application provides a method for testing a semiconductor chip, including: obtaining a target chip; obtaining an abnormal chip after performing a read-write function test on a preset number of memory cells in an edge area of the target chip; recording each read-write function The location information of the abnormal storage unit on the abnormal chip; according to the location information, determine whether the abnormal read-write function of the abnormal chip is a block abnormality; wherein, the abnormal chip refers to the storage device including the abnormal read-write function The target chip of the unit.
  • a semiconductor chip testing system for testing a target chip, comprising: a setting module for setting a preset number of storage units in an edge area of the target chip as test units; The setting module is connected to obtain test data after the read-write function test is performed on the test unit; the processing module is connected to the test module and is used to obtain an abnormal chip with abnormal read-write function according to the test data, and Location information on the abnormal chip of each storage unit with abnormal read/write function in the abnormal chip, and the processing module is further configured to determine whether the abnormal read/write function of the abnormal chip is a block abnormality according to the location information ; wherein, the abnormal chip refers to a target chip including a storage unit with abnormal read and write functions.
  • Another aspect of the present application provides a testing device for a semiconductor chip, the testing device being the above-mentioned testing system.
  • FIG. 1 is a flowchart of a method for testing a semiconductor chip in an embodiment
  • FIG. 2 is a schematic diagram of selecting a predetermined number of memory cells in an edge region of a target chip in an embodiment
  • FIG. 3 is a schematic diagram of selecting a preset number of memory cells in an edge region of a target chip in another embodiment
  • FIG. 4 is a structural block diagram of a semiconductor chip testing system in an embodiment.
  • a wafer will be designed with several chips. After the manufacturing process is completed, the chips fabricated on the wafer will be split into single chips and then packaged into products, and then the obtained products will be tested to detect Defective products.
  • processes such as thinning, transportation, splitting, and packaging may cause slight chipping, cracks and other abnormalities on the edge of the chip.
  • a stacked memory chip formed by stacking thin chips if a chip in the middle layer of the memory chip has chipped corners and cracks, it is difficult to find that those test abnormalities are caused by chip chip corners and cracks during packaged chip testing.
  • a method for testing a semiconductor chip including:
  • a plurality of encapsulated chips are obtained, and any one encapsulated chip is selected as a target chip, and subsequent steps are performed.
  • the storage unit for reading and writing function test is a preset number of storage units calculated from the edge of the target chip to the inside of the target chip, such as 4, 6, 8, 16, 32, 64, etc.
  • the target chip includes storage units in multiple storage areas (banks).
  • the target chip includes 4 storage areas and 16 storage areas, and the storage units whose storage areas are located in the edge area of the target chip are selected for read-write function test.
  • the distribution of the storage units with abnormal read/write function on the abnormal chip can be obtained, and then it can be determined whether the read/write function of the abnormal chip is abnormal or not. is a blocky exception.
  • the target chip includes a stacked memory chip, for example, the target chip includes a single die formed by stacking a plurality of thinned chips. In other embodiments, the target chip includes a single die formed from a single thinned chip.
  • the preset number of memory cells includes memory cells in row A and column B of the edge region of the target chip, where A and B are both integers.
  • the preset number of memory cells are memory cells in row A in one edge region of the target chip and/or memory cells in column B in another edge region of the target chip. In other embodiments, the preset number of memory cells is the memory cells of row A in the sum of two opposite edges of the target chip and/or the memory cells of column B in the other two opposite edges of the target chip.
  • the preset number of memory cells includes memory cells in C rows and C columns in the edge region of the target chip, where C is an integer.
  • m rows of memory cells are taken at the upper and lower edges of the target chip (in other embodiments, m1 rows of storage cells and m2 rows of storage cells may be taken at the upper and lower edges of the target chip, m1 ⁇ m2), take n columns of storage cells at the left and right edges of the target chip (in other embodiments, n1 rows of storage cells and n2 rows of storage cells can be taken at the left and right edges of the target chip, n1 ⁇ n2), Test the read and write functions of the 2m rows and 2n columns of memory cells in the edge area of the target chip respectively. If the read and write functions of the memory cells are normal, the target chip is a normal chip.
  • the target chip is an abnormal chip, and records the location information of the memory cells with abnormal read and write functions on the abnormal chip. If the memory cells with abnormal read and write functions are consecutive columns or rows of memory cells on the abnormal chip, it is considered that the abnormal chip
  • the abnormal read and write function of the chip is a block abnormality, otherwise, the abnormal read and write function of the abnormal chip is considered to be a non-block abnormality.
  • the target chip includes four storage areas, bank0, bank1, bank2, and bank3.
  • the storage unit in column b is selected in the edge area of bank0 and bank2 of the storage area, and the storage unit in row a is selected in the edge area of bank2 and bank3.
  • the storage unit with abnormal read/write function is several consecutive columns or rows of storage cells on the abnormal chip, it is considered that the read/write function on the abnormal chip is
  • the function abnormality is a block abnormality, otherwise, the abnormal read and write function of the abnormal chip is considered to be a non-block abnormality.
  • only the storage cells in column b in the edge regions of bank0 and bank2, or the storage cells in row a in the edge regions of bank2 and bank3 can be selected for read and write function test, and the determination method remains unchanged.
  • the step of judging whether the abnormal read-write function of the abnormal chip is a block abnormality according to the location information includes:
  • the memory cell with abnormal read/write function is a multi-row or multi-column memory cell on the abnormal chip, it is determined that the abnormal read/write function of the abnormal chip is a block abnormality; otherwise, it is determined that the abnormal read/write function of the abnormal chip is abnormal
  • the write function abnormality is a non-block abnormality; wherein, the multi-row or multi-column memory cells refer to memory cells with no less than 2 rows or no less than 2 columns on the abnormal chip.
  • the testing method is performed during crash testing, for example, the test can be performed in a pre-test stage during crash testing, or in a pre- crash testing stage or crash testing during crash testing. should be carried out in the testing phase.
  • the memory cells with abnormal read and write functions are multiple rows or columns of memory cells in the edge region of the abnormal chip, it is determined that the abnormal chip has a missing corner or abnormal crack; wherein, the Multi-row or multi-column memory cells refer to memory cells with no less than 2 rows or no less than 2 columns of abnormal chips.
  • the method for testing a semiconductor chip as described above includes obtaining a target chip; after performing a read-write function test on a preset number of memory cells in the edge region of each target chip, obtaining an abnormal chip; recording the abnormal read-write function of each memory cell in the The location information on the abnormal chip is determined; according to the location information, it is judged whether the abnormal read and write function of the abnormal chip is a block abnormality; wherein, the abnormal chip refers to a target chip including a storage unit with abnormal read and write functions.
  • the present application confirms whether the target chip is abnormal by performing a read-write function test on a preset number of memory cells in the edge area of the target chip.
  • the memory cell has abnormal read-write function, it is determined that the target chip is an abnormal chip and records There is position information of the abnormal storage unit on the target chip, and then according to the recorded position information, it is judged whether the abnormal read and write function of the abnormal chip is a block abnormality, and the present application confirms whether the abnormal read and write function of the abnormal chip is block.
  • Abnormal test cycle is short and low cost.
  • a testing system for semiconductor chips for testing a target chip, including:
  • the setting module 102 is used for setting a preset number of storage units in the edge area of the target chip as test units.
  • the target chip includes storage units in a plurality of storage areas (banks), for example, the target chip includes 4 storage areas and 16 storage areas, and the setting module 102 is used for each storage area in the target chip edge area. Write functional tests.
  • the test module 104 is connected to the setting module 102, and is used for obtaining test data after performing a read-write function test on the test unit.
  • the processing module 106 is connected to the test module 104, and is used to obtain the abnormal chip with abnormal read and write function according to the test data, and the position of each storage unit with abnormal read and write function in the abnormal chip on the abnormal chip information, the processing module 106 is further configured to determine whether the abnormal read-write function of the abnormal chip is a block abnormality according to the position information; wherein, the abnormal chip refers to a target chip including a storage unit with abnormal read-write function .
  • the setting module 102 is configured to set the memory cells in row A and column B of the target chip edge region as test cells, where A and B are both integers.
  • the setting module 102 is configured to set the memory cells in row A and column B of the target chip edge region as test cells, where A and B are both integers.
  • the setting module 102 is configured to set the memory cells in row A in one edge region of the target chip and/or the memory cells in column B in another edge region of the target chip as test cells. In other embodiments, the setting module 102 is configured to set the memory cell whose sum is taken by two opposite edges of the target chip as row A and/or the memory cell whose sum is taken by the other two opposite edges of the target chip is column B for the test unit.
  • the preset number of memory cells includes memory cells in C rows and C columns in the edge region of the target chip, where C is an integer.
  • the processing module is configured to obtain, according to the location information, the distribution of the storage units with abnormal read and write functions on the abnormal chip. If the edge of the abnormal chip is toward the center of the abnormal chip with multiple rows or columns of memory cells, it is determined that the abnormal chip has a missing corner or an abnormal crack;
  • the multi-row or multi-column memory cells refer to memory cells with no less than 2 rows or no less than 2 columns.
  • the processing module 106 is configured to obtain the distribution of the storage units with abnormal read/write functions on the abnormal chip according to the location information, if the storage units with abnormal read/write functions are all If the multi-row or multi-column storage cells in the edge region of the abnormal chip are obtained, the abnormality of the read-write function of the abnormal chip is obtained as block abnormality, otherwise, the abnormality of the read-write function of the abnormal chip is obtained as non-block abnormality;
  • the multi-row or multi-column memory cells refer to memory cells with no less than 2 rows or no less than 2 columns.
  • the test system further includes a storage module 108, which is connected to the processing module 106 and is used for storing the location information of each storage unit with abnormal read-write function on the abnormal chip,
  • the storage module 108 is further configured to store the location information of each storage unit on the target chip.
  • a semiconductor chip testing equipment is provided, the testing equipment includes the testing system described in any one of the above.
  • the above-mentioned semiconductor chip testing system and testing equipment used for testing a target chip, include: a setting module for setting a preset number of storage units in the edge area of the target chip as a test unit; a testing module, which is connected to the setting module is used to obtain test data after performing a read-write function test on the test unit; a processing module, connected to the test module, is used to obtain an abnormal chip with abnormal read-write function according to the test data, and the abnormal chip
  • the position information on the abnormal chip of each storage unit with abnormal read and write function in the above, and the processing module is further configured to determine whether the abnormal read and write function of the abnormal chip is block abnormal according to the position information;
  • the abnormal chip refers to a target chip including memory cells with abnormal read and write functions.
  • the present application confirms whether the target chip is abnormal by performing a read-write function test on the memory cells in the edge area of the target chip, and then judges whether the abnormal chip is abnormal according to the location information of the memory cells with abnormal read-write functions on the abnormal chip on the target chip. Whether the read-write function abnormality is a block abnormality, the present application confirms whether the read-write function abnormality of the abnormal chip is a block abnormality, and the test cycle is short and the cost is low.

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Abstract

本发明涉及一种半导体芯片的测试方法、测试系统及测试设备。该方法包括：获取目标芯片；分别对目标芯片的边缘区域预设数量的存储单元进行读写功能测试后，获取异常芯片；记录各个读写功能异常的存储单元在异常芯片上的位置信息；根据位置信息判断异常芯片的读写功能异常是否为块状异常；其中，异常芯片是指包括读写功能异常的存储单元的目标芯片。

Description

半导体芯片的测试方法、测试系统及测试设备
本申请要求于2020年7月13日提交的申请号为202010667480.2、名称为“半导体芯片的测试方法、测试系统及测试设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种半导体芯片的测试方法、测试系统及测试设备。
背景技术
电子组件(产品)系经过多道的加工程序所制造完成，因此为了确保产品质量，电子组件(产品)制造完成后，均会进行检测作业，以检测电子组件于制作过程中，是否损坏，进而检测出不良品。即所谓的崩应测试(BURN-IN TEST或称为烧机测试)，崩应测试大都于一加热炉体内将待测物置于较高温的环境下执行测试作业，而以较严苛的测试条件预先检测出濒临损坏或质量欠佳的产品，并期以产品提早通过前期测试而进入稳定期，于消费者使用时便可获得稳定的产品特性。
崩应测试完成后，会取若干失效芯片(异常芯片)送电性分析(EFA)，用以确认芯片失效的问题根源，失效模式包含column,row,block,single bit,double bit等失效模式种类，透过电性分析测试产生block fail块状的失效模式时，测试周期长，并且当分析样品较少时，无法即时了解所述崩应测试的失效是否为块状失效。
发明内容
本申请一方面提供一种半导体芯片的测试方法，包括：获取目标芯片；分别 对所述目标芯片的边缘区域预设数量的存储单元进行读写功能测试后，获取异常芯片；记录各个读写功能异常的存储单元在所述异常芯片上的位置信息；根据所述位置信息判断所述异常芯片的读写功能异常是否为块状异常；其中，所述异常芯片是指包括读写功能异常的存储单元的目标芯片。
本申请另一方面提供一种半导体芯片的测试系统，用于测试目标芯片，包括：设置模块，用于设置所述目标芯片的边缘区域预设数量的存储单元为测试单元；测试模块，与所述设置模块相连，用于对所述测试单元进行读写功能测试后，得到测试数据；处理模块，与所述测试模块相连，用于根据所述测试数据得到读写功能异常的异常芯片，以及所述异常芯片中各个读写功能异常的存储单元在所述异常芯片上的位置信息，所述处理模块还用于根据所述位置信息判定所述异常芯片的读写功能异常是否为块状异常；其中，所述异常芯片是指包括读写功能异常的存储单元的目标芯片。
本申请另一方面提供一种半导体芯片的测试设备，所述测试设备上述测试系统。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍。用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为一实施例中半导体芯片的测试方法的流程图；
图2为一实施例中目标芯片边缘区域选取预设数量的存储单元的示意图；
图3为另一实施例中目标芯片边缘区域选取预设数量的存储单元的示意图；
图4为一实施例中半导体芯片的测试系统的结构框图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
在制造过程中，一片晶圆上会设计有若干个芯片，在制造工艺完成后，会将晶圆上制造的芯片裂片成单颗芯片后封装成产品，然后对得到的产品进行测试，检测出不良品。从芯片生产到封装成产品过程中，减薄、运输、裂片、封装等工艺过程中都可能会使芯片边缘出现轻微缺角、裂痕等异常，这些异常有时很难察觉，尤其对于由多个减薄芯片堆叠而成的堆叠型的存储芯片，若存储芯片的中间层芯片出现缺角、裂痕，在封装芯片测试时很难发现那些测试异常是由芯片缺角、 裂痕引起的。
在后续进行失效芯片电性分析(EFA)时，发现芯片缺角导致芯片裂痕的块状失效的周期长，并且当进行电性分析的样品较少时，不能确认是否为块状失效，无法即时了解崩应失效问题的根本原因。
如图1所示，在其中一个实施例中，提供一种半导体芯片的测试方法，包括：
S102，获取目标芯片。
对晶圆上的芯片进行裂片、封装后得到多个封装芯片，选取任意一个封装芯片作为目标芯片，进行后续的步骤。
S104，对所述目标芯片边缘区域预设数量的存储单元进行读写功能的测试。
分别对所述目标芯片的边缘区域预设数量的各个存储单元进行读写功能测试，得到具有读写功能异常的存储单元的异常芯片，即异常芯片是包括读写功能异常的存储单元的目标芯片，进行读写功能测试的存储单元是由目标芯片的边缘向目标芯片内部计算预设数量的存储单元，例如4个、6个、8个、16个、32个、64个等。通过对目标芯片边缘区域预设数量的存储单元进行读写功能测试，可以找出边缘区域功能异常的目标芯片，进而根据边缘区域读写功能异常的存储单元的位置得出该读写功能异常是否是块状异常，缩短了目标芯片上块状异常的确认周期。
目标芯片(chip)包括多个存储区域(bank)中的存储单元，例如目标芯片包括4个存储区域、16个存储区域，选取各个存储区域位于目标芯片边缘区域的存储单元进行读写功能测试。
S106，获取读写功能异常的存储单元在异常芯片上的位置信息。
记录各个读写功能异常的存储单元在所述异常芯片上的位置信息，即确认 异常芯片边缘区域的存储单元中读写功能异常的存储单元的分布情况。
S108，根据所述位置信息判断所述异常芯片是否为块状异常。
根据记录的各个读写功能异常的存储单元在所述异常芯片上的位置信息，可以得到读写功能异常的存储单元在异常芯片上的分布情况，进而判断所述异常芯片的读写功能异常是否为块状异常。
在其中一个实施例中，所述目标芯片包括堆叠型存储芯片，例如目标芯片包括由多个减薄芯片堆叠形成的单颗晶粒。在其他实施例中，目标芯片包括由单个减薄芯片形成的单颗晶粒。
在其中一个实施例中，所述预设数量的存储单元包括所述目标芯片边缘区域的A行、B列的存储单元，其中，A与B均为整数。
在其中一个实施例中，预设数量的存储单元为所述目标芯片一个边缘区域的A行存储单元和/或另一个边缘区域的B列存储单元。在其他实施例中，预设数量的存储单元为在目标芯片的两个相对边缘取总和为A行的存储单元和/或在目标芯片的另外两个相对边缘取总和为B列的存储单元。
在其中一个实施例中，所述预设数量的存储单元包括所述目标芯片边缘区域的C行、C列的存储单元，C为整数。
如图2所示，在目标芯片的上下两个边缘各取m行存储单元(在其他实施例中，可以在目标芯片的上下两个边缘分别取m1行存储单元和m2行存储单元，m1≠m2)，在目标芯片的左右两个边缘各取n列存储单元(在其他实施例中，可以在目标芯片的左右两个边缘分别取n1行存储单元和n2行存储单元，n1≠n2)，分别对目标芯片边缘区域的2m行和2n列存储单元进行读写功能测试，若存储单元的读写功能均正常，则该目标芯片为正常芯片，若有部分存储单元的读写功能异常，则该目标芯片为异常芯片，记录读写功能异常的存储单元在异常芯片上 的位置信息，若读写功能异常的存储单元为异常芯片上连续几列或几行存储单元，则认为该异常芯片上的读写功能异常为块状异常，否则，认为异常芯片的读写功能异常为非块状异常。
如图3所示，目标芯片包括bank0、bank1、bank2、bank3四个存储区域，在存储区域bank0、bank2边缘区域选取b列储存单元，在存储区域bank2、bank3边缘区域选取a行存储存单元，分别对选取的a行和b列存储单元进行读写功能测试，若存储单元的读写功能均正常，则该目标芯片为正常芯片，若有部分存储单元的读写功能异常，则该目标芯片为异常芯片，记录读写功能异常的存储单元在异常芯片上的位置信息，若读写功能异常的存储单元为异常芯片上连续几列或几行存储单元，则认为该异常芯片上的读写功能异常为块状异常，否则，认为异常芯片的读写功能异常为非块状异常。在其他实施例中，也可以仅选取存储区域bank0、bank2边缘区域b列储存单元，或存储区域bank2、bank3边缘区域a行存储存单元进行读写功能测试，判定方式不变。
在其中一个实施例中，所述根据所述位置信息判断所述异常芯片的读写功能异常是否为块状异常的步骤包括：
若所述读写功能异常的存储单元为所述异常芯片上的多行或多列存储单元，则判定所述异常芯片的读写功能异常为块状异常，否则，判定所述异常芯片的读写功能异常为非块状异常；其中，所述多行或多列存储单元是指异常芯片上不小于2行或不小于2列的存储单元。
在其中一个实施例中，所述测试方法是在崩应测试时进行的，例如该测试可以在崩应测试过程中的预测试阶段进行，或崩应测试过程中的崩应前测试阶段或崩应测试阶段进行。
在其中一个实施例中，若所述读写功能异常的存储单元为所述异常芯片边 缘区域的多行或多列存储单元，则判定所述异常芯片具有缺角或裂痕异常；其中，所述多行或多列存储单元是指异常芯片不小于2行或不小于2列的存储单元。
上述半导体芯片的测试方法，包括获取目标芯片；分别对各个所述目标芯片的边缘区域预设数量的存储单元进行读写功能测试后，获取异常芯片；记录各个读写功能异常的存储单元在所述异常芯片上的位置信息；根据所述位置信息判断所述异常芯片的读写功能异常是否为块状异常；其中，所述异常芯片是指包括读写功能异常的存储单元的目标芯片。本申请通过对目标芯片边缘区域预设数量的存储单元进行读写功能测试来确认目标芯片是否有异常，若所述存储单元具有读写功能异常，则判定所述目标芯片为异常芯片，并记录具有异常的存储单元在目标芯片上的位置信息，然后根据记录的位置信息来判断所述异常芯片的读写功能异常是否为块状异常，本申请确认异常芯片的读写功能异常是否为块状异常的测试周期短，成本低。
如图4所示，在其中一个实施例中，提供一种半导体芯片的测试系统，用于测试目标芯片，包括：
设置模块102，用于设置所述目标芯片的边缘区域预设数量的存储单元为测试单元。
目标芯片(chip)包括多个存储区域(bank)中的存储单元，例如目标芯片包括4个存储区域、16个存储区域，设置模块102用于各个存储区域位于目标芯片边缘区域的存储单元进行读写功能测试。
测试模块104，与所述设置模块102相连，用于对所述测试单元进行读写功能测试后，得到测试数据。
处理模块106，与所述测试模块104相连，用于根据所述测试数据得到读写功能异常的异常芯片，以及所述异常芯片中各个读写功能异常的存储单元在所 述异常芯片上的位置信息，所述处理模块106还用于根据所述位置信息判定所述异常芯片的读写功能异常是否为块状异常；其中，所述异常芯片是指包括读写功能异常的存储单元的目标芯片。
在其中一个实施例中，所述设置模块102用于设置所述目标芯片边缘区域A行、B列存储单元为测试单元，其中，A与B均为整数。
在其中一个实施例中，所述设置模块102用于设置所述目标芯片边缘区域A行、B列存储单元为测试单元，其中，A与B均为整数。
在其中一个实施例中，所述设置模块102用于设置所述目标芯片一个边缘区域的A行存储单元和/或另一个边缘区域的B列存储单元为测试单元。在其他实施例中，所述设置模块102用于设置所述目标芯片两个相对边缘取总和为A行的存储单元和/或在目标芯片的另外两个相对边缘取总和为B列的存储单元为测试单元。
在其中一个实施例中，所述预设数量的存储单元包括所述目标芯片边缘区域的C行、C列的存储单元，C为整数。
在其中一个实施例中，所述处理模块用于根据所述位置信息得到所述读写功能异常的存储单元在所述异常芯片上的分布，若所述读写功能异常的存储单元为从所述异常芯片边缘向所述异常芯片中心的多行或多列存储单元，则判定所述异常芯片具有缺角或裂痕异常；
其中，所述多行或多列存储单元是指不小于2行或不小于2列的存储单元。
在其中一个实施例中，所述处理模块106用于根据所述位置信息得到所述读写功能异常的存储单元在所述异常芯片上的分布，若所述读写功能异常的存储单元为所述异常芯片边缘区域的多行或多列存储单元，则得到所述异常芯片的读写功能异常为块状异常，否则，得到所述异常芯片的读写功能异常为非块状 异常；
其中，所述多行或多列存储单元是指不小于2行或不小于2列的存储单元。
在其中一个实施例中，所述测试系统还包括存储模块108，所述存储模块108与所述处理模块106相连，用于存储所述异常芯片上各个读写功能异常的存储单元的位置信息，所述存储模块108还用于存储所述目标芯片上各个存储单元的位置信息。
在其中一个实施例中，提供一种半导体芯片的测试设备，所述测试设备包括上述任一项所述的测试系统。
上述半导体芯片的测试系统及测试设备，用于测试目标芯片，包括：设置模块，用于设置所述目标芯片的边缘区域预设数量的存储单元为测试单元；测试模块，与所述设置模块相连，用于对所述测试单元进行读写功能测试后，得到测试数据；处理模块，与所述测试模块相连，用于根据所述测试数据得到读写功能异常的异常芯片，以及所述异常芯片中各个读写功能异常的存储单元在所述异常芯片上的位置信息，所述处理模块还用于根据所述位置信息判定所述异常芯片的读写功能异常是否为块状异常；其中，所述异常芯片是指包括读写功能异常的存储单元的目标芯片。本申请通过对目标芯片边缘区域的存储单元进行读写功能测试来确认目标芯片是否有异常，然后根据异常芯片上读写功能异常的存储单元在目标芯片上的位置信息来判断所述异常芯片的读写功能异常是否为块状异常，本申请确认异常芯片的读写功能异常是否为块状异常的测试周期短，成本低。
上述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (13)

  1. 一种半导体芯片的测试方法，包括：
    获取目标芯片；
    分别对所述目标芯片的边缘区域预设数量的存储单元进行读写功能测试后，获取异常芯片；
    记录各个读写功能异常的存储单元在所述异常芯片上的位置信息；
    根据所述位置信息判断所述异常芯片的读写功能异常是否为块状异常；
    其中，所述异常芯片是指包括读写功能异常的存储单元的目标芯片。
  2. 根据权利要求1所述的方法，其中，所述目标芯片包括堆叠型存储芯片。
  3. 根据权利要求1所述的方法，其中，所述预设数量的存储单元包括所述目标芯片边缘区域的A行、B列的存储单元，其中，A与B均为整数。
  4. 根据权利要求1所述的方法，其中，所述根据所述位置信息判断所述异常芯片的读写功能异常是否为块状异常的步骤包括：
    若所述读写功能异常的存储单元为所述异常芯片上的多行或多列存储单元，则判定所述异常芯片的读写功能异常为块状异常，否则，判定所述异常芯片的读写功能异常为非块状异常；
    其中，所述多行或多列存储单元是指不小于2行或不小于2列的存储单元。
  5. 根据权利要求1所述的方法，其中，所述根据所述位置信息判断所述异常芯片的读写功能异常是否为块状异常的步骤包括：
    若所述读写功能异常的存储单元为所述异常芯片上的连续两行以上或两列以上存储单元，则判定所述异常芯片的读写功能异常为块状异常。
  6. 根据权利要求1所述的方法，其中，所述测试方法是在崩应测试时进行的。
  7. 根据权利要求1所述的方法，其中，若所述读写功能异常的存储单元为从所述异常芯片边缘向所述异常芯片中心的多行或多列存储单元，则判定所述异常芯片具有缺角或裂痕异常；
    其中，所述多行或多列存储单元是指不小于2行或不小于2列的存储单元。
  8. 一种半导体芯片的测试系统，用于测试目标芯片，包括：
    设置模块，用于设置所述目标芯片的边缘区域预设数量的存储单元为测试单元；
    测试模块，与所述设置模块相连，用于对所述测试单元进行读写功能测试后，得到测试数据；
    处理模块，与所述测试模块相连，用于根据所述测试数据得到读写功能异常的异常芯片，以及所述异常芯片中各个读写功能异常的存储单元在所述异常芯片上的位置信息，所述处理模块还用于根据所述位置信息判定所述异常芯片的读写功能异常是否为块状异常；
    其中，所述异常芯片是指包括读写功能异常的存储单元的目标芯片。
  9. 根据权利要求8所述的测试系统，其中，所述设置模块用于设置所述目标芯片边缘区域A行、B列存储单元为测试单元，其中，A与B均为整数。
  10. 根据权利要求8所述的测试系统，其中，所述处理模块用于根据所述位置信息得到所述读写功能异常的存储单元在所述异常芯片上的分布，若所述读写功能异常的存储单元为所述异常芯片边缘区域的多行或多列存储单元，则得到所述异常芯片的读写功能异常为块状异常，否则，得到所述异常芯片的读写功能异常为非块状异常；
    其中，所述多行或多列存储单元是指不小于2行或不小于2列的存储单元。
  11. 根据权利要求8所述的测试系统，其中，所述处理模块用于根据所述位 置信息得到所述读写功能异常的存储单元在所述异常芯片上的分布，若所述读写功能异常的存储单元为所述异常芯片上的连续两行以上或两列以上存储单元，则判定所述异常芯片的读写功能异常为块状异常。
  12. 根据权利要求8所述的测试系统，其中，所述测试系统还包括存储模块，所述存储模块与所述处理模块相连，用于存储所述异常芯片上各个读写功能异常的存储单元的位置信息，所述存储模块还用于存储所述目标芯片上各个存储单元的位置信息。
  13. 一种半导体芯片的测试设备，所述测试设备包括权利要求8所述的测试系统。
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