WO2022011821A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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WO2022011821A1
WO2022011821A1 PCT/CN2020/115739 CN2020115739W WO2022011821A1 WO 2022011821 A1 WO2022011821 A1 WO 2022011821A1 CN 2020115739 W CN2020115739 W CN 2020115739W WO 2022011821 A1 WO2022011821 A1 WO 2022011821A1
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potential
transistor
output signal
gate output
signal
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PCT/CN2020/115739
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English (en)
French (fr)
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曹海明
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武汉华星光电技术有限公司
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Priority to US17/057,667 priority Critical patent/US11749223B2/en
Publication of WO2022011821A1 publication Critical patent/WO2022011821A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel driving circuit and a display panel.
  • the current display technology is required to be suitable for both high frequency and low frequency, so that the display panel not only has the advantages of smooth picture quality brought by high frequency, but also has the advantage of low power consumption brought by low frequency. Therefore, the dynamic frame rate technology As the times require, this technology can adjust the refresh frequency of the display panel in real time, thereby meeting the display needs of ultra-low frequency and ultra-high frequency at the same time.
  • the display panel For low-frequency display requirements, since the holding time of each frame of picture in the low-frequency state is extended by dozens of times of the original, the display panel is required to have strong picture holding ability; for high-frequency display requirements, due to the extremely short charging time of each row of pixels, Therefore, the display panel needs to have a strong charging capability, and if a static or low-speed object image is displayed with a high refresh rate, it will cause the problem of excessive logic power consumption of the display panel.
  • the traditional backplane technologies include A-Si, LTPS, and IGZO technologies.
  • LTPS low temperature polysilicon
  • IGZO indium gallium zinc oxide
  • LTPS technology has higher mobility and smaller component area than IGZO technology, it has stronger charging capacity and is more suitable for high-frequency applications;
  • IGZO technology has better uniformity and leakage current than LTPS technology. Smaller, so it saves more power and has stronger picture holding ability, which is more suitable for applications at low frequencies. It can be understood that the traditional backplane technology cannot meet the requirements of dynamic frame rate due to the singleness of technology, resulting in the singleness of performance advantages.
  • the composite LTPO (low temperature polycrystalline oxide) technology combines the advantages of LTPS and IGZO technology, so that the display panel has the characteristics of strong charging capacity and low power consumption at the same time, while meeting the needs of high frequency and low frequency use, Therefore, the LTPO technology is suitable for the requirements of the dynamic frame rate technology, which can achieve the purpose of improving the user's visual experience and optimizing the power consumption.
  • IGZO has a lower mobility than LTPO, at high frequency, due to the short charging time, IGZO often has the problem of insufficient charging level. Therefore, it is necessary to increase the charging current of IGZO.
  • the charging level is reached within the charging time.
  • the first is to increase the aspect ratio of the thin film transistor TFT, but this method will make the thin film transistor TFT larger in size and occupy too much space, resulting in a display panel.
  • the problem of reducing the aperture ratio; the second is to increase the gate-source voltage difference Vgs of all thin film transistors TFT of the display panel, but this method will increase the stress on all thin film transistors TFT and make the thin film transistor TFT easy to age, thus It affects the overall stability of the drive circuit, that is, not only affects the stability of the peripheral drive circuit, but also affects the stability of the drive circuit in the AA area.
  • FIG. 1 is a diagram of a pixel driving circuit of an existing 2T1C structure.
  • the circuit adopts a 1T2C circuit, including a driving switch T10, a storage capacitor Cst, and a liquid crystal capacitor Clc, wherein the input of the gate of the driving switch T10 is the current row gate
  • the electrode outputs a signal G(n)
  • the drain electrode is electrically connected to one end of the storage capacitor Cst and the liquid crystal capacitor Clc
  • the source electrode is electrically connected to the data line.
  • the gate output signal G(n) of the current row is sent to the signal to control the switch of the drive switch T10.
  • the data line charges the liquid crystal capacitor Clc and the storage capacitor Cst to the required voltage, and then T10 is turned off, and the storage capacitor Cst discharges to The voltage of the liquid crystal capacitor Clc is maintained until the next update.
  • the driving switch T10 can only be a single type of TFT, and each TFT has its own advantages and disadvantages, if it is applied to both LTPS and IGZO in the dynamic frame rate technology, the high It is very likely that the charging current of the IGZO cannot be met at high frequency.
  • the present application provides a pixel driving circuit, comprising: a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a storage capacitor and A liquid crystal capacitor, wherein the first transistor, the second transistor, and the third transistor include a source electrode, a gate electrode, and a drain electrode, respectively, and the first capacitor, the second capacitor, and the storage capacitor and the liquid crystal capacitor respectively include a first end and a second end.
  • the gate of the first transistor is electrically connected to the first node, the source is electrically connected to the first terminal of the second capacitor, and the drain is electrically connected to the first terminal of the storage capacitor and the liquid crystal capacitor respectively.
  • the first end; the gate of the second transistor is connected to the gate output signal G(n-1) of the previous row, the source is electrically connected to the data signal, and the drain is electrically connected to the first node; the third transistor
  • the gate of the next row is connected to the gate output signal G(n+1), the source is electrically connected to the first node, the drain is electrically connected to the constant voltage low potential VGL;
  • the first end of the first capacitor is electrically connected the first node, the second terminal is connected to the current row gate output signal G(n); the first terminal of the second capacitor is electrically connected to the data signal, and the second terminal is electrically connected to the first node;
  • the storage capacitor The second end of the liquid crystal capacitor and the first end of the liquid crystal capacitor are respectively electrically connected to the drain of the first transistor
  • the pixel driver circuit has a precharge phase, a first boost phase, a second boost phase, a transition phase, and a hold phase.
  • the first transistor, the second transistor and the third transistor are all N-type thin film transistors, in the pre-charging stage B0, the second transistor is turned on, the third transistor is turned off, and the current row
  • the gate output signal G(n) charges the potential of the first node to the first potential V1 through the second transistor.
  • the second transistor and the third transistor are turned off, the data signal sends out a first high-level signal S1, and the data signal converts the first voltage through the first capacitor
  • the potential of the node is raised from the first potential V1 to the second potential V2.
  • the second transistor and the third transistor are turned off, the data signal sends out a second high potential signal S2, and the potential of the first node is changed by the second capacitor from The second potential V2 is raised to a third potential V3 and a second high potential signal S2 is written into the liquid crystal capacitor; wherein, the third potential V3 is higher than the high potential V0 of the gate output signal.
  • the first transistor, the second transistor and the third transistor are all turned off, and the current row gate output signal G(n) connects the first node to the first node through the first capacitor.
  • the gate output signal G(n+1) of the next row reduces the potential of the first node from the fourth potential V4 to the constant voltage low potential VGL.
  • the first transistor and the second transistor are turned off, the third transistor is turned on, and the gate output signal G(n+1) of the next row keeps the potential of the first node It is a constant voltage low potential VGL.
  • the first transistor, the second transistor and the third transistor are all oxide semiconductor thin film transistors.
  • the first transistor is an oxide semiconductor thin film transistor
  • the second transistor and the third transistor are both low temperature polysilicon thin film transistors.
  • the upper row gate output signal G(n-1) in the precharge phase B0, is at a high level V0 before an initial period A0 and transitions to a low level at the beginning of the initial period A0 .
  • the gate output signal G(n) of the current row is at a low potential
  • the gate output signal G(n+1) of the next row is at a low potential
  • the data signal is at the first level before the first period A1
  • the high potential signal S1 is converted to a low potential at the beginning of the first period A1; wherein, the first high potential signal S1 has the same potential as the first potential V1.
  • the gate output signal G(n-1) of the previous row is at a low potential
  • the gate output signal G(n) of the current row is at a high potential V0
  • the gate of the next row is at a high potential V0.
  • the pole output signal G(n+1) is at a low level
  • the data signal is at a low level.
  • the gate output signal G(n-1) of the previous row is at a low potential
  • the gate output signal G(n) of the current row is at a high potential V0
  • the gate of the next row is at a high potential V0.
  • the pole output signal G(n+1) is at a low level
  • the data signal is a second high level signal S2.
  • the gate output signal G(n-1) of the previous row, the gate output signal G(n) of the current row are at a low level, and the gate output signal G(n) of the current row is at a low level Both are low level, the data signal maintains the second high level signal S2 before the second period A2 and is converted to a low level during the second period A2.
  • the gate output signal G(n-1) of the previous row and the gate output signal G(n) of the current row are at low level, and the gate output signal G(n+ of the next row) 1) is a pulse of high potential V0.
  • the relationship between the first potential V1 and the second potential V2 is formula 1:
  • V 1 is the potential value of a first potential V1
  • V 2 is the potential value of the second potential V2
  • C 1 is the capacitance of the first capacitor
  • V 0 is the value of the high voltage
  • V0 is an output signal of the gate
  • C 2 is the capacitance of the second capacitor
  • C gs1 unilateral parasitic capacitance of the first transistor
  • C gs2 one side of the parasitic capacitance of the second transistor
  • C gs3 unilateral third transistor Parasitic capacitance value.
  • the relationship between the second potential V2 and the third potential V3 is formula 2:
  • V 2 is the potential value of the second potential V2
  • V 3 is the voltage value of the second voltage V3
  • C 1 is the capacitance of the first capacitor
  • C 2 for the first the potential value of the capacitance values of two capacitors
  • V COM of a common signal C gs1 one side of the parasitic capacitance of the first transistor
  • C gs2 one side of the parasitic capacitance of the second transistor
  • C gs3 one side of the third transistor Parasitic capacitance value.
  • the third potential V3 is higher than the high potential V0 of the gate output signal based on the formula 1 and the formula 2, according to the first high potential signal, the second high potential signal
  • the potential signal, the high potential V0 of the gate output signal, the constant voltage low potential VGL and the voltage value V COM of the common signal are realized by adjusting the capacitance value of the first capacitor and the capacitance value of the second capacitor of.
  • the data signal in the holding phase B4, maintains a low level during a third period A3, and changes from a low level to a third high level signal S3 after the third period A3;
  • the gate output signal G(n+1) of the next row is replaced by the enable signal EMn, and the enable signal EMn is in the pre-charging stage B0, the first boosting stage B1, and the second boosting stage B2 and the transition phase B3 are low potential, and the holding phase B4 is high potential.
  • the data signal is held at a low level.
  • the present application further provides a display panel, the display panel includes the above pixel driving circuit, the pixel driving circuit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a storage capacitor and a liquid crystal capacitor, wherein the first transistor, the second transistor, and the third transistor all include a source, a gate, and a drain, respectively, and the first capacitor, the second capacitor, the storage Both the capacitor and the liquid crystal capacitor respectively include a first end and a second end.
  • the gate of the first transistor is electrically connected to the first node, the source is electrically connected to the first terminal of the second capacitor, and the drain is electrically connected to the first terminal of the storage capacitor and the liquid crystal capacitor respectively.
  • the first end; the gate of the second transistor is connected to the gate output signal G(n-1) of the previous row, the source is electrically connected to the data signal, and the drain is electrically connected to the first node; the third transistor
  • the gate of the next row is connected to the gate output signal G(n+1), the source is electrically connected to the first node, the drain is electrically connected to the constant voltage low potential VGL;
  • the first end of the first capacitor is electrically connected the first node, the second terminal is connected to the current row gate output signal G(n); the first terminal of the second capacitor is electrically connected to the data signal, and the second terminal is electrically connected to the first node;
  • the storage capacitor The second end of the liquid crystal capacitor and the first end of the liquid crystal capacitor are respectively electrically connected to the drain of the first transistor
  • the pixel driving circuit has a pre-charging stage B0, a first boosting stage B1, a second boosting stage B2, a transition stage (B3), and a holding stage B4; Both the second transistor and the third transistor are N-type thin film transistors.
  • the second transistor In the precharge phase B0, the second transistor is turned on, the third transistor is turned off, and the current row gate output signal G(n) charges the potential of the first node to the first node through the second transistor potential V1.
  • the second transistor and the third transistor are turned off, the data signal sends out a first high-level signal S1, and the data signal converts the first voltage through the first capacitor
  • the potential of the node is raised from the first potential V1 to the second potential V2.
  • the second transistor and the third transistor are turned off, the data signal sends out a second high potential signal S2, and the potential of the first node is changed by the second capacitor from The second potential V2 is raised to a third potential V3 and a second high potential signal S2 is written into the liquid crystal capacitor; wherein, the third potential V3 is higher than the high potential V0 of the gate output signal.
  • the first transistor, the second transistor and the third transistor are all turned off, and the current row gate output signal G(n) connects the first node to the first node through the first capacitor.
  • the gate output signal G(n+1) of the next row reduces the potential of the first node from the fourth potential V4 to the constant voltage low potential VGL.
  • the first transistor and the second transistor are turned off, the third transistor is turned on, and the gate output signal G(n+1) of the next row keeps the potential of the first node It is a constant voltage low potential VGL.
  • the first transistor, the second transistor and the third transistor are all oxide semiconductor thin film transistors.
  • the first transistor is an oxide semiconductor thin film transistor
  • the second transistor and the third transistor are both low temperature polysilicon thin film transistors.
  • the upper row gate output signal G(n-1) in the precharge phase B0, is at a high level V0 before an initial period A0 and transitions to a low level at the beginning of the initial period A0 .
  • the gate output signal G(n) of the current row is at a low potential
  • the gate output signal G(n+1) of the next row is at a low potential
  • the data signal is at the first level before the first period A1
  • the high potential signal S1 is at a low potential during the first period A1; wherein, the first high potential signal S1 has the same potential as the first potential V1.
  • the gate output signal G(n-1) of the previous row is at a low potential
  • the gate output signal G(n) of the current row is at a high potential V0
  • the gate of the next row is at a high potential V0.
  • the pole output signal G(n+1) is at a low level
  • the data signal is at a low level;
  • the gate output signal G(n-1) of the previous row is at a low potential
  • the gate output signal G(n) of the current row is at a high potential V0
  • the lower row gate output signal G(n) is at a high potential V0.
  • the gate output signal G(n+1) of one row is at a low level
  • the data signal is a second high level signal S2.
  • the gate output signal G(n-1) of the previous row, the gate output signal G(n) of the current row are at a low level, and the gate output signal G(n) of the current row is at a low level Both are at a low level, the data signal maintains the second high level signal S2 before the second period A2 and transitions to a low level at the beginning of the second period A2.
  • the gate output signal G(n-1) of the previous row and the gate output signal G(n) of the current row are at low level, and the gate output signal G(n+ of the next row) 1) is a pulse of high potential V0.
  • the relationship between the first potential V1 and the second potential V2 is formula 1:
  • V 1 is the potential value of a first potential V1
  • V 2 is the voltage value V2 of the second potential
  • C. 1 is a first capacitance of the capacitor C1
  • C 2 is the capacitance of the second capacitor
  • VGL down to a constant potential
  • C gs1 one side of the parasitic capacitance of the first transistor
  • C gs2 one side of the parasitic capacitance of the second transistor
  • C gs3 single third transistor side parasitic capacitance.
  • the relationship between the second potential V2 and the third potential V3 is formula 2:
  • V 2 is the potential value of the second potential V2
  • V 3 is the voltage value of the second voltage V3
  • C 1 is the capacitance of the first capacitor
  • C 2 for the first the potential value of the capacitance values of two capacitors
  • V COM of a common signal C gs1 one side of the parasitic capacitance of the first transistor
  • C gs2 one side of the parasitic capacitance of the second transistor
  • C gs3 one side of the third transistor Parasitic capacitance value.
  • the third potential V3 is higher than the high potential V0 of the gate output signal based on the formula 1 and the formula 2, according to the first high potential signal, the second high potential signal
  • the potential signal, the high potential V0 of the gate output signal, the constant voltage low potential VGL and the potential value V COM of the common signal are realized by adjusting the capacitance value of the first capacitor and the capacitance value of the second capacitor of.
  • the data signal in the holding phase B4, maintains a low level during the third period A3, and transitions from a low level to a third high level signal S3 after the third period A3.
  • the gate output signal G(n+1) of the next row is replaced by the enable signal EMn, and the enable signal EMn is in the pre-charging stage B0, the first boosting stage B1, and the second boosting stage B2 and the transition phase B3 are low potential, and the holding phase B4 is high potential.
  • the data signal is held at a low level.
  • the pixel driving circuit adopts a 3T2C structure.
  • the current row gate output signal G(n) is used to pass through
  • the first capacitor C1 increases the potential of the first node Pn from the first potential V1 to the second potential V2, and then uses the data signal data to increase the potential of the first node Pn from the second potential V2 to the third potential through the second capacitor C2.
  • potential V3, and the third potential V3 is greater than the high potential V0 of the current row gate output signal G(n) to turn on the first transistor T1 and write data to the liquid crystal capacitor Clc.
  • the pixel driving circuit can raise the gate potential of the first transistor T1 to a potential higher than the high potential V0 of the current row gate output signal G(n), the original gate level is raised, so that the gate potential of the first transistor T1 is raised.
  • the driving ability is stronger, and it can be applied to the requirement of fast charging at high frequency, even if the first transistor T1 adopts an IGZO transistor, so the pixel driving circuit can be applied to the dynamic frame rate technology.
  • FIG. 1 is a diagram of a pixel driving circuit of a conventional 2T1C structure.
  • FIG. 2 is a pixel driving circuit according to an embodiment of the present application.
  • FIG. 3 is a timing diagram of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 4 is another timing diagram of the pixel driving circuit according to the embodiment of the application.
  • FIG. 5 is another pixel driving circuit according to an embodiment of the present application.
  • FIG. 6 is a timing diagram of another pixel driving circuit according to an embodiment of the present application.
  • the transistors used in all the embodiments of the present application may include both P-type and/or N-type transistors, wherein the P-type transistor is turned on when the gate is at a low potential, and is turned off when the gate is at a high potential; the N-type transistor is at a gate of Turns on when the gate is high and turns off when the gate is low.
  • FIG. 2 is a pixel driving circuit according to an embodiment of the present application.
  • An embodiment of the present application provides a pixel driving circuit, including: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a Two capacitors C2, storage capacitors Cst, and liquid crystal capacitors Clc, wherein the first transistor T1, the second transistor T2, and the third transistor T3 include a source, a gate, and a drain, respectively.
  • the first capacitor C1, the second capacitor C2 Both the storage capacitor Cst and the liquid crystal capacitor Clc include a first end and a second end, respectively.
  • the gate of the first transistor T1 is electrically connected to the first node Pn, the source is electrically connected to the first terminal of the second capacitor C2, and the drain is electrically connected to the first terminal of the storage capacitor Cst and the first terminal of the liquid crystal capacitor Clc, respectively. .
  • the gate of the second transistor T2 is connected to the gate output signal G(n-1) of the previous row, the source is electrically connected to the data signal Data, and the drain is electrically connected to the first node Pn.
  • the gate of the third transistor T3 is connected to the gate output signal G(n+1) of the next row, the source is electrically connected to the first node Pn, and the drain is electrically connected to the constant voltage low potential VGL.
  • the first terminal of the first capacitor C1 is electrically connected to the first node Pn, and the second terminal is connected to the current row gate output signal G(n).
  • the first terminal of the second capacitor C2 is electrically connected to the data signal Data, and the second terminal is electrically connected to the first node Pn.
  • the second end of the storage capacitor Cst and the first end of the liquid crystal capacitor Clc are respectively electrically connected to the drain of the first transistor T1, and the second ends are respectively electrically connected to the common signal Com.
  • the main function of the pixel driving circuit provided in this application is to improve the pixel charging capability at high frequencies. Therefore, according to the characteristics of low temperature polysilicon (LTPS) thin film transistors with strong charging capability but high leakage current, and oxide semiconductors (IGZO) thin film transistor has the characteristics of low leakage current but weak charging capability, this pixel drive circuit is mainly suitable for two types of pixel drive circuits.
  • LTPS low temperature polysilicon
  • IGZO oxide semiconductors
  • the first type is a pixel driving circuit using all IGZO thin film transistors, that is, the first transistor T1, the second transistor T2 and the third transistor T3 are all IGZO transistors.
  • the other is a display panel using LTPO technology, that is, a pixel drive circuit of a display panel prepared by combining LTPS and IGZO thin film transistors.
  • LTPO technology that is, a pixel drive circuit of a display panel prepared by combining LTPS and IGZO thin film transistors.
  • the first transistor T1 since the leakage current of the first transistor T1 directly affects the voltage of the liquid crystal capacitor Clc, the first transistor T1 adopts an IGZO thin film transistor to reduce the leakage current, while the second transistor T2 and the third transistor T3 adopt LTPS thin film transistors. Improve charging and driving capabilities.
  • the pixel driving circuit can actually also be applied to a pixel driving circuit in which the first transistor T1, the second transistor T2 and the third transistor T3 are all LTPS thin film transistors, but the charging capability of the LTPS thin film transistor itself is relatively strong. , so the practical significance is not as great as that of the above two types of pixel driving circuits.
  • FIG. 3 is a timing diagram of a pixel driving circuit according to an embodiment of the present application.
  • the first transistor T1 , the second transistor T2 and the third transistor T3 are all N-type thin film transistors as an example. The work flow of the drive circuit is described in detail.
  • the gate output signal G(n-1) of the previous row, the gate output signal G(n) of the current row, the gate output signal G(n+1) of the next row and the low potential of the first node Pn are constant voltage low Potential VGL;
  • the high potential of the gate output signal G(n-1) of the previous row, the gate output signal G(n) of the current row and the gate output signal G(n+1) of the next row is V0;
  • the potential is the potential value V COM of the common signal Com.
  • the pixel driving circuit has a precharge phase B0, a first boost phase B1, a second boost phase B2, a transition phase B3, and a hold phase B4.
  • the gate output signal G(n-1) of the previous row is at a high potential V0 before the initial period A0 and is at a low potential after the initial period A0, and the current row gate output signal G(n) is at a low potential , the gate output signal G(n+1) of the next row is a low level
  • the data signal Data is a first high level signal S1 before the first period A1 and is converted to a low level at the beginning of the first period A1; wherein, the first The high potential signal S1 is the first potential V1, wherein the potential of the first high potential signal S1 is the same as the first potential V1.
  • the second transistor T2 Before the initial period A0, the second transistor T2 is turned on, the first transistor T1 and the third transistor T3 are turned off, and the data signal Data sends out a first high potential signal S1 to change the potential of the first node Pn from low through the second transistor T2
  • the potential is charged to the first potential V1, that is, the first high potential signal S1, and the first capacitor C1 is also charged; at the beginning of the initial period A0, the second transistor T2 is turned off, and the first capacitor C1 is in the initial period A0 and the first period A1
  • the potential of the first node Pn is kept at the first potential V1.
  • the gate output signal G(n-1) of the previous row is at a low potential, so that the second transistor T2 is turned off; the gate output signal G(n+1) of the next row is at a low potential, so that the third The transistor T3 is turned off; the data signal Data is at a low potential and no data is sent; the current row gate output signal G(n) is at a high potential V0.
  • the current row gate output signal G(n) will be The potential of the first node Pn is raised from the first potential V1 to the second potential V2 through the first capacitor C1, wherein the second potential V2 is raised higher than the first potential V1 and the high potential of the gate output signal G(n) V0 is related to the difference between the constant voltage low potential VGL.
  • the gate output signal G(n-1) of the upper row is at a low level, and the second transistor T2 is turned off; the gate output signal G(n+1) of the next row is at a low level, and the third transistor T3 OFF; the gate output signal G(n) of the current row maintains a high level V0, and the data signal Data sends out a second high level signal S2. It is the same as the principle that the current row gate output signal G(n) raises the potential of the first node Pn from the first potential V1 to the second potential V2 through the first capacitor C1 in the first boosting stage B1.
  • the data signal Data The potential of the first node Pn is raised from the second potential V2 to the third potential V3 through the second capacitor C2, and the third potential V3 is higher than the high potential V0 of the gate output signal, so the data signal Data passes through the second capacitor C2.
  • the potential of a node Pn is raised from the second potential V2 to the third potential V3 and the second high potential signal S2 is written to the storage capacitor Cst, thereby completing one data writing, wherein the third potential V3 is higher than the second potential V2
  • the degree of boosting is related to the difference between the potential values V COM of the second high potential signal S2 and the common signal Com.
  • the third potential V3 is higher than the high potential V0 of the gate output signal G(n), which is set according to the circuit components and each driving signal. Specifically, the third potential V3 is higher than the gate output signal.
  • the high potential of V0 is based on formula 1 and formula 2, according to the first high potential signal S1, the second high potential signal S2, the high potential of the gate output signal G(n), the constant voltage low potential VGL and the common signal Com voltage VCOM , which is achieved by adjusting the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2.
  • formula 1 and formula 2 are detailed below.
  • the gate output signal G(n-1) of the previous row, the gate output signal G(n) of the current row and the gate output signal G(n) of the current row are all low.
  • the transistor T1, the second transistor T2 and the third transistor T3 are all turned off.
  • the data signal Data maintains the second high level signal S2 before the second period A2 and transitions to the low level at the beginning of the second period A2. Therefore, when the front row gate output signal G(n) changes to a low potential, the potential of the first node Pn is lowered from the third potential V3 to the fourth potential V4 through the first capacitor C1.
  • the gate output signal G(n-1) of the previous row and the gate output signal G(n) of the current row are at a low potential, and the gate output signal G(n+1) of the next row is a pulse of a high potential V0 .
  • the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the gate output signal G(n+1) of the next row keeps the potential of the first node Pn at the constant voltage low potential VGL.
  • the current row gate output signal G(n) is used to change the potential of the first node Pn from the first potential through the first capacitor C1.
  • V1 is raised to the second potential V2
  • the data signal Data is used to raise the potential of the first node Pn from the second potential V2 to the third potential V3 through the second capacitor C2
  • the third potential V3 is made greater than the current row gate output signal
  • the high potential V0 of G(n) turns on the first transistor T1 and writes data to the liquid crystal capacitor Clc.
  • the pixel driving circuit can raise the gate level of the first transistor T1 to a potential higher than the high level V0 of the current row gate output signal G(n), the original gate level is raised, so that the first transistor T1
  • the driving ability of the pixel is stronger, so it can be applied to the requirement of fast charging at high frequency, even if the first transistor T1 adopts an IGZO transistor, so the pixel driving circuit can be applied to the dynamic frame rate technology.
  • V 1 is the potential value of a first potential V1
  • V 2 is the voltage value V2 of the second potential
  • C. 1 is a first capacitance of the capacitor C1
  • C 2 is the capacitance of the second capacitor
  • VGL down to a constant potential
  • C gs1 one side of the parasitic capacitance of the first transistor
  • C gs2 one side of the parasitic capacitance of the second transistor
  • C gs3 single third transistor side parasitic capacitance.
  • the relationship between the second potential V2 and the third potential V3 is formula 2:
  • V 2 is the potential value of the second potential V2
  • V 3 is the voltage value of the second voltage V3
  • C 1 is the capacitance of the first capacitor
  • C 2 for the first two capacitance value of capacitor V COM to the potential value of the common signal Com
  • C gs1 one side of the parasitic capacitance of the first transistor
  • C gs2 one side of the parasitic capacitance of the second transistor
  • C gs3 single third transistor side parasitic capacitance
  • the potential of the first node Pn is pulled down to a low level after the gate output signal G(n+1) of the next row is a high level and a constant voltage low level VGL is introduced.
  • the jump of the data signal Data will cause the voltage of the liquid crystal capacitor Clc to decrease due to the influence of the second capacitor C2, parasitic capacitance and leakage current, that is, due to the jump of the data signal Data, the pixel driving circuit may cause clock feedthrough or Crosstalk phenomenon, which leads to the deterioration of the picture holding ability, that is, the shortening of the holding time.
  • FIG. 4 is another timing diagram of the pixel driving circuit according to the embodiment of the present application.
  • the data signal Data introduces a constant voltage low potential to the gate output signal G(n+1) of the next row
  • the third high-potential signal S3 is issued after the third period A3 of VGL. Due to the one-side parasitic capacitance of the first transistor T1, the second transistor T2 and the third transistor T3, the first transistor T1 will move from the drain electrode, that is, the pixel electrode, to the pixel electrode.
  • the source, that is, the data signal Data generates a leakage current, which reduces the voltage of the liquid crystal capacitor Clc, resulting in inaccurate display of the screen corresponding to the second high-potential signal S2.
  • FIG. 5 is another pixel driving circuit according to an embodiment of the application
  • FIG. 6 is a timing diagram of another pixel driving circuit according to an embodiment of the application.
  • the data signal Data is in the next row
  • the gate output signal G(n+1) changes to a high level, it changes from a low level to a third high level signal S3;
  • the gate output signal G(n+1) of the next row is replaced by the enable signal EMn, enabling
  • the signal EMn is low in the precharge phase B0, the first boost phase B1, the second boost phase B2, and the transition phase B3, and is high in the hold phase B4, so that the first node Pn is in the hold phase B4. It can be stably maintained at a low level and will not be affected by the jump of the data signal Data, so that the picture corresponding to the second high level signal S2 is kept stable in the holding stage B4, which effectively improves the picture holding capability.
  • keeping the data signal Data at a low level can also avoid the influence of its transition on the first node Pn, thereby improving the picture holding capability.
  • the present application also provides a display panel including the above pixel driving circuit.
  • the display panel has the same structure and beneficial effects as the pixel driving circuit provided in the foregoing embodiments. Since the structure and beneficial effects of the pixel driving circuit have been described in detail in the foregoing embodiments, they will not be repeated here.

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Abstract

提供了一种像素驱动电路及显示面板，第一节点(Pn)预充电为第一电位(V1)后，利用当前行栅极输出信号(G(n))通过第一电容(C1)提升为第二电位(V2)，再利用数据信号(Data)通过第二电容(C2)提升至第三电位(V3)即大于当前行栅极输出信号(G(n))的高电位(V0)而使第一晶体管(T1)打开并写入数据(Data)。由于能使第一晶体管(T1)的栅极准位提升至大于当前行栅极输出信号(G(n))，因此提升了原栅极准位，驱动能力更强。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种一种像素驱动电路及显示面板。
背景技术
目前的显示技术要求同时适用于高频和低频的情况，以使显示面板不仅具有高频带来的画质流畅的优点，还具有低频带来的低功耗的优点，因此，动态帧频技术应运而生，该技术可以实时调节显示面板的刷新频率，由此同时满足超低频和超高频的显示需求。对于低频的显示需求，由于低频状态每帧画面的holding时间延长为原先的数十倍，因此要求显示面板的画面Holding能力强；对于高频的显示需求，由于每行像素的充电时间极短，因此需要显示面板的充电能力强，并且，如果用高刷新率显示静止或速度较低的物体影像，反而会造成显示面板逻辑功耗过高的问题。
传统的背板技术有A-Si、LTPS、IGZO技术，与a-Si(非晶硅)技术相比，LTPS(低温多晶硅)和IGZO(氧化铟镓锌)两种技术由于迁移率较高而被广泛应用。其中，由于LTPS技术比IGZO技术的迁移率更高、件所占面积更小，因此充电能力更强，更适合于高频时的应用；而IGZO技术比LTPS技术的均匀性更好、漏电流较小，因此更加省电、画面holding能力更强，更适合于低频时的应用。可以理解的是，传统的背板技术由于技术的单一性，导致性能优点的单一性，无法满足动态帧频的需求。
而复合型的LTPO(低温多晶氧化物)技术由于结合了LTPS和IGZO两种技术的优点，使得显示面板同时具有强充电能力和低功耗的特点，同时满足高频和低频的使用需求，因此LTPO技术适用于动态帧频技术的需求，能达到提升用户视觉体验并且优化功耗的目的。
但是如前所述，由于IGZO较LTPO的迁移率低，因此在高频时由于充电时间较短，IGZO往往会存在充电准位不够的问题，所以需 要将IGZO的充电电流提升，在较短的充电时间内达到充电准位。目前在IGZO有源层上提升充电电流有两种方式：第一种是增加薄膜晶体管TFT的宽长比，但是这种方法会使薄膜晶体管TFT的尺寸较大、占用空间过多，导致显示面板开口率降低的问题；第二种是增加显示面板的所有薄膜晶体管TFT的栅源极电压差Vgs，但是这种方法会使得所有薄膜晶体管TFT受到的应力Stress增而使得薄膜晶体管TFT容易老化，从而影响驱动电路整体的稳定性，即不仅影响外围驱动电路的稳定性，还影响AA区驱动电路的稳定性。
参考图1，图1为现有的2T1C结构的像素驱动电路图，该电路采用1T2C电路，包括驱动开关T10、存储电容Cst、液晶电容Clc，其中，驱动开关T10的栅极的输入为当前行栅极输出信号G(n)，漏极与存储电容Cst和液晶电容Clc的一端电性连接，源极与数据线电性连接。当前行栅极输出信号G(n)送入信号控制驱动开关T10的开关，当T10打开时数据线将液晶电容Clc和存储电容Cst充电到所需要的的电压后T10关闭，存储电容Cst放电来维持液晶电容Clc的电压保持到下一次更新。该1T2C电路工作时，由于驱动开关T10只能是单一类型的TFT，而每种TFT都有其优点和缺点，在动态帧频技术中如果将其既应用于LTPS又应用于IGZO，则在高频时很可能不能满足需要提高IGZO的充电电流的要求。
技术问题
因此，如何用较高的电压驱动IGZO来提高IGZO的充电电流，同时保证显示面板的驱动电路整体的稳定性，成为目前亟待解决的问题。
技术解决方案
为了解决目前的GOA电路在下拉维持阶段电路不稳定的问题，本申请提供一种像素驱动电路，包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容、存储电容和液晶电容，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管均分别包括源极、栅 极和漏极，所述第一电容、所述第二电容、所述存储电容和所述液晶电容均分别包括第一端和第二端。
所述第一晶体管的栅极电性连接第一节点，源极电性连接所述第二电容的第一端，漏极分别电性连接所述存储电容的第一端和所述液晶电容的第一端；所述第二晶体管的栅极接入上一行栅极输出信号G(n-1)，源极电性接入数据信号，漏极电性连接第一节点；所述第三晶体管的栅极接入下一行栅极输出信号G(n+1)，源极电性连接第一节点，漏极电性连接恒压低电位VGL；所述第一电容的第一端电性连接第一节点，第二端接入当前行栅极输出信号G(n)；所述第二电容的第一端电性接入数据信号，第二端电性连接第一节点；所述存储电容的第二端和所述液晶电容的第一端分别电性连接所述第一晶体管的漏极，第二端分别电性接入公共信号。
在一些实施例中，所述像素驱动电路具有预充电阶段、第一升压阶段、第二升压阶段、过渡阶段和保持阶段。
若所述第一晶体管、所述第二晶体管和所述第三晶体管均为N型薄膜晶体管，则在所述预充电阶段B0，所述第二晶体管打开，所述第三晶体管关闭，当前行栅极输出信号G(n)通过所述第二晶体管将所述第一节点的电位充电至第一电位V1。
在所述第一升压阶段B1，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第一高电位信号S1，所述数据信号通过所述第一电容将所述第一节点的电位由所述第一电位V1提升至第二电位V2。
在所述第二升压阶段B2，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第二高电位信号S2，通过所述第二电容将所述第一节点的电位由所述第二电位V2提升至第三电位V3并向所述液晶电容写入第二高电位信号S2；其中，所述第三电位V3高于所述栅极输出信号的高电位V0。
在所述过渡阶段B3，所述第一晶体管、所述第二晶体管关闭和所述第三晶体管均关闭，所述当前行栅极输出信号G(n)通过第一 电容将所述第一节点的电位由第三电位V3降至第四电位V4后，所述下一行栅极输出信号G(n+1)将所述第一节点的电位由第四电位V4降至恒压低电位VGL。
在所述保持阶段B4，所述第一晶体管和所述第二晶体管关闭，所述第三晶体管打开，所述下一行栅极输出信号G(n+1)将所述第一节点的电位保持为恒压低电位VGL。
在一些实施例中，所述第一晶体管、所述第二晶体管和所述第三晶体管均为氧化物半导体薄膜晶体管。
在一些实施例中，所述第一晶体管为氧化物半导体薄膜晶体管，所述第二晶体管和所述第三晶体管均为低温多晶硅薄膜晶体管。
在一些实施例中，在所述预充电阶段B0，所述上一行栅极输出信号G(n-1)在初始时段A0之前为高电位V0且在所述初始时段A0开始时转换为低电位、所述当前行栅极输出信号G(n)为低电位，所述下一行栅极输出信号G(n+1)为低电位，所述数据信号在所述第一时段A1之前为第一高电位信号S1且在所述第一时段A1开始时转换为低电位；其中，所述第一高电位信号S1与所述第一电位V1的电位相同。
在所述第一升压阶段B1，所述上一行栅极输出信号G(n-1)为低电位、所述当前行栅极输出信号G(n)为高电位V0，所述下一行栅极输出信号G(n+1)为低电位，所述数据信号为低电位。
在所述第二升压阶段B2，所述上一行栅极输出信号G(n-1)为低电位、所述当前行栅极输出信号G(n)为高电位V0，所述下一行栅极输出信号G(n+1)为低电位，所述数据信号为第二高电位信号S2。
在所述过渡阶段B3，所述上一行栅极输出信号G(n-1)、所述当前行栅极输出信号G(n)为低电位和所述当前行栅极输出信号G(n)均为低电位，所述数据信号在第二时段A2之前保持所述第二高电位信号S2且在所述第二时段A2内转换为低电位。
在所述保持阶段B4，所述上一行栅极输出信号G(n-1)和所述 当前行栅极输出信号G(n)为低电位、所述下一行栅极输出信号G(n+1)为高电位V0的脉冲。
在一些实施例中，所述第一电位V1与所述第二电位V2之间的关系为公式一：
Figure PCTCN2020115739-appb-000001
其中，V 1为第一电位V1的电位值，V 2为第二电位V2的电位值，C 1为第一电容的电容值，V 0为栅极输出信号的高电位V0的值，C 2为第二电容的电容值，VGL为恒压低电位，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
在一些实施例中，所述第二电位V2与所述第三电位V3之间的关系为公式二：
Figure PCTCN2020115739-appb-000002
其中，V 2为第二电位V2的电位值，V 3为第二电位V3的电位值，C 1为第一电容的电容值，S 2为第二高电位S2的电位值，C 2为第二电容的电容值，V COM为公共信号的电位值，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
在一些实施例中，所述第三电位V3高于所述栅极输出信号的高电位V0是基于所述公式一及所述公式二，根据所述第一高电位信号、所述第二高电位信号、栅极输出信号的高电位V0、所述恒压低电位VGL和所述公共信号的电压值V COM，通过调节所述第一电容的电容值和所述第二电容的电容值实现的。
在一些实施例中，在所述保持阶段B4，所述数据信号在第三时段A3内保持低电平，并在所述第三时段A3之后由低电平转变为第三高电位信号S3；下一行栅极输出信号G(n+1)由使能信号EMn替换，所述使能信号EMn在所述预充电阶段B0、所述第一升压阶段 B1、所述第二升压阶段B2和所述过渡阶段B3均为低电位，且在所述保持阶段B4为高电位。
在一些实施例中，在所述保持阶段B4，所述数据信号保持低电平。
本申请还提供一种显示面板，该显示面板包括如上所述的像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容、存储电容和液晶电容，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管均分别包括源极、栅极和漏极，所述第一电容、所述第二电容、所述存储电容和所述液晶电容均分别包括第一端和第二端。
所述第一晶体管的栅极电性连接第一节点，源极电性连接所述第二电容的第一端，漏极分别电性连接所述存储电容的第一端和所述液晶电容的第一端；所述第二晶体管的栅极接入上一行栅极输出信号G(n-1)，源极电性接入数据信号，漏极电性连接第一节点；所述第三晶体管的栅极接入下一行栅极输出信号G(n+1)，源极电性连接第一节点，漏极电性连接恒压低电位VGL；所述第一电容的第一端电性连接第一节点，第二端接入当前行栅极输出信号G(n)；所述第二电容的第一端电性接入数据信号，第二端电性连接第一节点；所述存储电容的第二端和所述液晶电容的第一端分别电性连接所述第一晶体管的漏极，第二端分别电性接入公共信号。
在一些实施例中，所述像素驱动电路具有预充电阶段B0、第一升压阶段B1、第二升压阶段B2、过渡阶段(B3)和保持阶段B4；所述第一晶体管、所述第二晶体管和所述第三晶体管均为N型薄膜晶体管。
在所述预充电阶段B0，所述第二晶体管打开，所述第三晶体管关闭，当前行栅极输出信号G(n)通过所述第二晶体管将所述第一节点的电位充电至第一电位V1。
在所述第一升压阶段B1，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第一高电位信号S1，所述数据信号通过所述 第一电容将所述第一节点的电位由所述第一电位V1提升至第二电位V2。
在所述第二升压阶段B2，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第二高电位信号S2，通过所述第二电容将所述第一节点的电位由所述第二电位V2提升至第三电位V3并向所述液晶电容写入第二高电位信号S2；其中，所述第三电位V3高于所述栅极输出信号的高电位V0。
在所述过渡阶段B3，所述第一晶体管、所述第二晶体管关闭和所述第三晶体管均关闭，所述当前行栅极输出信号G(n)通过第一电容将所述第一节点的电位由第三电位V3降至第四电位V4后，所述下一行栅极输出信号G(n+1)将所述第一节点的电位由第四电位V4降至恒压低电位VGL。
在所述保持阶段B4，所述第一晶体管和所述第二晶体管关闭，所述第三晶体管打开，所述下一行栅极输出信号G(n+1)将所述第一节点的电位保持为恒压低电位VGL。
在一些实施例中，所述第一晶体管、所述第二晶体管和所述第三晶体管均为氧化物半导体薄膜晶体管。
在一些实施例中，所述第一晶体管为氧化物半导体薄膜晶体管，所述第二晶体管和所述第三晶体管均为低温多晶硅薄膜晶体管。
在一些实施例中，在所述预充电阶段B0，所述上一行栅极输出信号G(n-1)在初始时段A0之前为高电位V0且在所述初始时段A0开始时转换为低电位、所述当前行栅极输出信号G(n)为低电位，所述下一行栅极输出信号G(n+1)为低电位，所述数据信号在所述第一时段A1之前为第一高电位信号S1且在所述第一时段A1内为低电位；其中，所述第一高电位信号S1与所述第一电位V1的电位相同。
在所述第一升压阶段B1，所述上一行栅极输出信号G(n-1)为低电位、所述当前行栅极输出信号G(n)为高电位V0，所述下一行栅极输出信号G(n+1)为低电位，所述数据信号为低电位；
在所述第二升压阶段(B2)，所述上一行栅极输出信号G(n-1)为低电位、所述当前行栅极输出信号G(n)为高电位V0，所述下一行栅极输出信号G(n+1)为低电位，所述数据信号为第二高电位信号S2。
在所述过渡阶段B3，所述上一行栅极输出信号G(n-1)、所述当前行栅极输出信号G(n)为低电位和所述当前行栅极输出信号G(n)均为低电位，所述数据信号在第二时段A2之前保持所述第二高电位信号S2且在所述第二时段A2开始时转换为低电位。
在所述保持阶段B4，所述上一行栅极输出信号G(n-1)和所述当前行栅极输出信号G(n)为低电位、所述下一行栅极输出信号G(n+1)为高电位V0的脉冲。
在一些实施例中，所述第一电位V1与所述第二电位V2之间的关系为公式一：
Figure PCTCN2020115739-appb-000003
其中，V 1为第一电位V1的电位值，V 2为第二电位V2的电位值，C 1为第一电容C1的电容值，V 0为栅极输出信号的高电位V0的值，C 2为第二电容的电容值，VGL为恒压低电位，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
在一些实施例中，所述第二电位V2与所述第三电位V3之间的关系为公式二：
Figure PCTCN2020115739-appb-000004
其中，V 2为第二电位V2的电位值，V 3为第二电位V3的电位值，C 1为第一电容的电容值，S 2为第二高电位S2的电位值，C 2为第二电容的电容值，V COM为公共信号的电位值，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
在一些实施例中，所述第三电位V3高于所述栅极输出信号的高电位V0是基于所述公式一及所述公式二，根据所述第一高电位信号、所述第二高电位信号、栅极输出信号的高电位V0、所述恒压低电位VGL和所述公共信号的电位值V COM，通过调节所述第一电容的电容值和所述第二电容的电容值实现的。
在一些实施例中，在所述保持阶段B4，所述数据信号在第三时段A3内保持低电平，并在所述第三时段A3之后由低电平转变为第三高电位信号S3。
下一行栅极输出信号G(n+1)由使能信号EMn替换，所述使能信号EMn在所述预充电阶段B0、所述第一升压阶段B1、所述第二升压阶段B2和所述过渡阶段B3均为低电位，且在所述保持阶段B4为高电位。
在一些实施例中，在所述保持阶段B4，所述数据信号保持低电平。
有益效果
本申请提供的像素驱动电路及显示面板中，该像素驱动电路采用3T2C结构，在对第一节点Pn预充电将其电位置为第一电位后，利用当前行栅极输出信号G(n)通过第一电容C1将第一节点Pn的电位为从第一电位V1提升为第二电位V2，再利用数据信号data通过第二电容C2将第一节点Pn的电位从第二电位V2提升至第三电位V3，并且使第三电位V3大于当前行栅极输出信号G(n)的高电位V0而使第一晶体管T1打开并向液晶电容Clc写入数据。由于该像素驱动电路可以使第一晶体管T1的栅极电位提升至大于当前行栅极输出信号G(n)的高电位V0的电位，因此提升了原栅极准位，使第一晶体管T1的驱动能力更强，能够适用于高频时需要快速充电的要求，即使第一晶体管T1采用IGZO晶体管，因此该像素驱动电路能适用于动态帧频技术。
附图说明
图1为现有的2T1C结构的像素驱动电路图。
图2为本申请实施例的的像素驱动电路。
图3为本申请实施例的像素驱动电路的时序图。
图4为本申请实施例的像素驱动电路的另一种时序图，
图5为本申请实施例的另一种像素驱动电路。
图6为本申请实施例的另一种像素驱动电路的时序图。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请所有实施例为区分晶体管处栅极之外的两极，将其中一极称为源极，另一极称为漏极。由于晶体管的源极和漏极是对称的，因此其源极和漏极是可以互换的。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本申请所有实施例采用的晶体管可以包括P型和/或N型晶体管两种，其中，P型晶体管在栅极为低电位时打开，在栅极为高电位时关闭；N型晶体管在栅极为高电位时打开，在栅极为低电位时关闭。
参考图2，图2为本申请实施例的像素驱动电路，本申请实施例提供一种像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第一电容C1、第二电容C2、存储电容Cst和液晶电容Clc，其中，第一晶体管T1、第二晶体管T2、第三晶体管T3均分别包括源极、栅极和漏极，第一电容C1、第二电容C2、存储电容Cst和液晶电容Clc均分别包括第一端和第二端。
第一晶体管T1的栅极电性连接第一节点Pn，源极电性连接第二电容C2的第一端，漏极分别电性连接存储电容Cst的第一端和液晶电容Clc的第一端。
第二晶体管T2的栅极接入上一行栅极输出信号G(n-1)，源极 电性接入数据信号Data，漏极电性连接第一节点Pn。
第三晶体管T3的栅极接入下一行栅极输出信号G(n+1)，源极电性连接第一节点Pn，漏极电性连接恒压低电位VGL。
第一电容C1的第一端电性连接第一节点Pn，第二端接入当前行栅极输出信号G(n)。
第二电容C2的第一端电性接入数据信号Data，第二端电性连接第一节点Pn。
存储电容Cst的第二端和液晶电容Clc的第一端分别电性连接第一晶体管T1的漏极，第二端分别电性接入公共信号Com。
需要说明的是，本申请提供的像素驱动电路的主要作用是提高高频时的像素充电能力，因此根据低温多晶硅(LTPS)薄膜晶体管充电能力强但漏电流较高的特点，以及氧化物半导体(IGZO)薄膜晶体管漏电流较低但充电能力弱的特点，该像素驱动电路主要适用于两种类型的像素驱动电路。
第一种是全部采用IGZO薄膜晶体管的像素驱动电路，即第一晶体管T1、第二晶体管T2和第三晶体管T3均为IGZO晶体管。
另一种是采用LTPO技术的显示面板，即结合了LTPS和IGZO两种薄膜晶体管制备而成的显示面板的像素驱动电路。其中，由于第一晶体管T1的漏电流大小直接影响液晶电容Clc的电压大小，因此第一晶体管T1采用IGZO薄膜晶体管，减小漏电流，而第二晶体管T2和第三晶体管T3采用LTPS薄膜晶体管，提高充电能力和驱动能力。
可以理解的是，该像素驱动电路实际上也可以适用于第一晶体管T1、第二晶体管T2和第三晶体管T3均为LTPS薄膜晶体管的像素驱动电路，只是由于LTPS薄膜晶体管的充电能力本身较强，因此实际意义没有上述两种类型的像素驱动电路的实际意义大。
图3为本申请实施例的像素驱动电路的时序图，结合图2和图3，下面以第一晶体管T1、第二晶体管T2和第三晶体管T3均为N型薄膜晶体管为例，对该像素驱动电路的工作流程进行详细说明。其中， 上一行栅极输出信号G(n-1)、当前行栅极输出信号G(n)、下一行栅极输出信号G(n+1)和第一节点Pn的低电位为恒压低电位VGL；上一行栅极输出信号G(n-1)、当前行栅极输出信号G(n)和下一行栅极输出信号G(n+1)的高电位为V0；数据信号Data的低电位为公共信号Com的电位值V COM。
该像素驱动电路具有预充电阶段B0、第一升压阶段B1、第二升压阶段B2、过渡阶段B3和保持阶段B4。
在预充电阶段B0，上一行栅极输出信号G(n-1)在初始时段A0之前为高电位V0且在初始时段A0之后为低电位、当前行栅极输出信号G(n)为低电位，下一行栅极输出信号G(n+1)为低电位，数据信号Data在第一时段A1之前为第一高电位信号S1且在第一时段A1开始时转换为低电位；其中，第一高电位信号S1为第一电位V1，其中，第一高电位信号S1的电位与第一电位V1相同。
具体地，在初始时段A0之前，第二晶体管T2打开，第一晶体管T1和第三晶体管T3关闭，数据信号Data发出第一高电位信号S1通过第二晶体管T2将第一节点Pn的电位从低电位充电至第一电位V1即第一高电位信号S1，同时第一电容C1也被充电；在初始时段A0开始时，第二晶体管T2关闭，第一电容C1在初始时段A0和第一时段A1保持第一节点Pn的电位为第一电位V1。
在第一升压阶段B1，上一行栅极输出信号G(n-1)为低电位，使第二晶体管T2关闭；下一行栅极输出信号G(n+1)为低电位，使第三晶体管T3关闭；数据信号Data为低电位不发出数据；当前行栅极输出信号G(n)为高电位V0，由于电容两端的是共同作用的，因此当前行栅极输出信号G(n)会通过第一电容C1将第一节点Pn的电位由第一电位V1提升至第二电位V2，其中，第二电位V2比第一电位V1提升的程度与栅极输出信号G(n)的高电位V0和恒压低电位VGL之差有关。
在第二升压阶段B2，上一行栅极输出信号G(n-1)为低电位，第二晶体管T2关闭；下一行栅极输出信号G(n+1)为低电位，第三 晶体管T3关闭；当前行栅极输出信号G(n)保持高电位V0，数据信号Data发出第二高电位信号S2。与第一升压阶段B1中当前行栅极输出信号G(n)通过第一电容C1将第一节点Pn的电位从第一电位V1提升到第二电位V2的原理相同，此时数据信号Data通过第二电容C2将第一节点Pn的电位由第二电位V2提升至第三电位V3，第三电位V3高于栅极输出信号的高电位V0，因此数据信号Data通过第二电容C2将第一节点Pn的电位由第二电位V2提升至第三电位V3并向存储电容Cst写入第二高电位信号S2，由此，一次数据写入完成，其中，第三电位V3比第二电位V2提升的程度与第二高电位信号S2和公共信号Com的电位值V COM之差有关。
需要说明的是，第三电位V3高于栅极输出信号G(n)的高电位V0为根据电路元器件和各驱动信号设定的，具体而言，第三电位V3高于栅极输出信号V0的高电位是基于公式一及公式二，根据第一高电位信号S1、第二高电位信号S2、栅极输出信号G(n)的高电位、恒压低电位VGL和公共信号Com电压VCOM，通过调节第一电容C1的电容值和第二电容C2的电容值实现的。其中，公式一及公式二详见下文。
在过渡阶段B3，上一行栅极输出信号G(n-1)、当前行栅极输出信号G(n)为低电位和当前行栅极输出信号G(n)均为低电位，因此第一晶体管T1、第二晶体管T2和第三晶体管T3均关闭。数据信号Data在第二时段A2之前保持第二高电位信号S2且在第二时段A2开始时转换为低电位。因此，当前行栅极输出信号G(n)转变为低电位时会通过第一电容C1将第一节点Pn的电位由第三电位V3降至第四电位V4。
在保持阶段B4，上一行栅极输出信号G(n-1)和当前行栅极输出信号G(n)为低电位、下一行栅极输出信号G(n+1)为高电位V0的脉冲。此时，第一晶体管T1和第二晶体管T2关闭，第三晶体管T3打开，下一行栅极输出信号G(n+1)将第一节点Pn的电位保持为恒压低电位VGL。
本申请实施例在对第一节点Pn预充电将其电位置为第一电位后，利用当前行栅极输出信号G(n)通过第一电容C1将第一节点Pn的电位为从第一电位V1提升为第二电位V2，再利用数据信号Data通过第二电容C2将第一节点Pn的电位从第二电位V2提升至第三电位V3，并且使第三电位V3大于当前行栅极输出信号G(n)的高电位V0而使第一晶体管T1打开并向液晶电容Clc写入数据。由于该像素驱动电路可以使第一晶体管T1的栅极准位提升至大于当前行栅极输出信号G(n)的高电位V0的电位，因此提升了原栅极准位，使第一晶体管T1的驱动能力更强，因此能够适用于高频时需要快速充电的要求，即使第一晶体管T1采用IGZO晶体管，因此该像素驱动电路能适用于动态帧频技术。
基于上述实施例，第一电位V1与第二电位V2之间的关系为公式一：
Figure PCTCN2020115739-appb-000005
其中，V 1为第一电位V1的电位值，V 2为第二电位V2的电位值，C 1为第一电容C1的电容值，V 0为栅极输出信号的高电位V0的值，C 2为第二电容的电容值，VGL为恒压低电位，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
在一些实施例中，第二电位V2与第三电位V3之间的关系为公式二：
Figure PCTCN2020115739-appb-000006
其中，V 2为第二电位V2的电位值，V 3为第二电位V3的电位值，C 1为第一电容的电容值，S 2为第二高电位S2的电位值，C 2为第二电容的电容值，V COM为公共信号Com的电位值，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
另外，还需要注意的是，在数据写入后，原则上第一节点Pn的电位在下一行栅极输出信号G(n+1)为高电位而引入恒压低电位VGL后被拉低为低电位，但是数据信号Data的跳变会因为第二电容C2、寄生电容和漏电流的影响导致液晶电容Clc的电压降低，即由于数据信号Data的跳变可能导致该像素驱动电路发生时钟馈通或串扰现象，由此导致画面holding能力变差，即holding时间变短。
例如，图4为本申请实施例的像素驱动电路的另一种时序图，参考图4，在保持阶段B4，如果数据信号Data在下一行栅极输出信号G(n+1)引入恒压低电位VGL的第三时段A3之后发出第三高电位信号S3，由于第一晶体管T1、第二晶体管T2和第三晶体管T3的单侧寄生电容，会使第一晶体管T1中从漏电极即像素电极向源极即数据信号Data产生漏电流，使液晶电容Clc的电压降低，导致第二高电位信号S2对应的画面显示不准确。
甚至，数据信号Data跳变为第三高电位信号时若通过第二电容使得Pn节点的电位升高而使第一晶体管T1导通，则液晶电容会通过第一晶体管T1漏电，从而使得第二高电位信号S2对应的画面holding时间变短。
针对上述问题，本申请实施例还作了进一步改进。图5为本申请实施例的另一种像素驱动电路，图6为本申请实施例的另一种像素驱动电路的时序图，参考图5和图6，在保持阶段B4，数据信号Data在下一行栅极输出信号G(n+1)转变为高电位之后，由低电平转变为第三高电位信号S3；下一行栅极输出信号G(n+1)由使能信号EMn替换，使能信号EMn在预充电阶段B0、第一升压阶段B1、第二升压阶段B2和过渡阶段B3均为低电位，且在保持阶段B4为高电位，由此使得第一节点Pn在保持阶段B4能稳定地保持为低电位，不会受到数据信号Data跳变的影响，从而使第二高电位信号S2对应的画面在保持阶段B4保持稳定，有效提升了画面holding能力。
或者直接如图1所示，在保持阶段B4，使数据信号Data保持低电平，也可避免其跳变对第一节点Pn的影响，从而提升画面holding 能力。
本申请还提供一种显示面板，包括上述像素驱动电路。该显示面板具有与前述实施例提供的像素驱动电路相同的结构和有益效果。由于前述实施例已经对该像素驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素驱动电路，其包括：
    第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容、存储电容和液晶电容，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管均分别包括源极、栅极和漏极，所述第一电容、所述第二电容、所述存储电容和所述液晶电容均分别包括第一端和第二端；
    所述第一晶体管的栅极电性连接第一节点，源极电性连接所述第二电容的第一端，漏极分别电性连接所述存储电容的第一端和所述液晶电容的第一端；
    所述第二晶体管的栅极接入上一行栅极输出信号(G(n-1))，源极电性接入数据信号，漏极电性连接第一节点；
    所述第三晶体管的栅极接入下一行栅极输出信号(G(n+1))，源极电性连接第一节点，漏极电性连接恒压低电位(VGL)；
    所述第一电容的第一端电性连接第一节点，第二端接入当前行栅极输出信号(G(n))；
    所述第二电容的第一端电性接入数据信号，第二端电性连接第一节点；
    所述存储电容的第二端和所述液晶电容的第一端分别电性连接所述第一晶体管的漏极，第二端分别电性接入公共信号。
  2. 如权利要求1所述的像素驱动电路，其中，所述像素驱动电路具有预充电阶段(B0)、第一升压阶段(B1)、第二升压阶段(B2)、过渡阶段(B3)和保持阶段(B4)；所述第一晶体管、所述第二晶体管和所述第三晶体管均为N型薄膜晶体管；
    在所述预充电阶段(B0)，所述第二晶体管打开，所述第三晶体管关闭，当前行栅极输出信号(G(n))通过所述第二晶体管将所述第一节点的电位充电至第一电位(V1)；
    在所述第一升压阶段(B1)，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第一高电位信号(S1)，所述数据信号通过 所述第一电容将所述第一节点的电位由所述第一电位(V1)提升至第二电位(V2)；
    在所述第二升压阶段(B2)，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第二高电位信号(S2)，通过所述第二电容将所述第一节点的电位由所述第二电位(V2)提升至第三电位(V3)并向所述液晶电容写入第二高电位信号(S2)；其中，所述第三电位(V3)高于所述栅极输出信号的高电位(V0)；
    在所述过渡阶段(B3)，所述第一晶体管、所述第二晶体管关闭和所述第三晶体管均关闭，所述当前行栅极输出信号(G(n))通过第一电容将所述第一节点的电位由第三电位(V3)降至第四电位(V4)后，所述下一行栅极输出信号(G(n+1))将所述第一节点的电位由第四电位(V4)降至恒压低电位(VGL)；
    在所述保持阶段(B4)，所述第一晶体管和所述第二晶体管关闭，所述第三晶体管打开，所述下一行栅极输出信号(G(n+1))将所述第一节点的电位保持为恒压低电位(VGL)。
  3. 如权利要求1所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管和所述第三晶体管均为氧化物半导体薄膜晶体管。
  4. 如权利要求1所述的像素驱动电路，其中，所述第一晶体管为氧化物半导体薄膜晶体管，所述第二晶体管和所述第三晶体管均为低温多晶硅薄膜晶体管。
  5. 如权利要求2所述的像素驱动电路，其中，
    在所述预充电阶段(B0)，所述上一行栅极输出信号(G(n-1))在初始时段(A0)之前为高电位V0且在所述初始时段(A0)开始时转换为低电位、所述当前行栅极输出信号(G(n))为低电位，所述下一行栅极输出信号(G(n+1))为低电位，所述数据信号在第一时段(A1)之前为第一高电位信号(S1)且在所述第一时段(A1)内为低电位；其中，所述第一高电位信号(S1)与所述第一电位(V1)的电位相同；
    在所述第一升压阶段(B1)，所述上一行栅极输出信号(G(n-1)) 为低电位、所述当前行栅极输出信号(G(n))为高电位V0，所述下一行栅极输出信号(G(n+1))为低电位，所述数据信号为低电位；
    在所述第二升压阶段(B2)，所述上一行栅极输出信号(G(n-1))为低电位、所述当前行栅极输出信号(G(n))为高电位V0，所述下一行栅极输出信号(G(n+1))为低电位，所述数据信号为第二高电位信号(S2)；
    在所述过渡阶段(B3)，所述上一行栅极输出信号(G(n-1))、所述当前行栅极输出信号(G(n))为低电位和所述当前行栅极输出信号(G(n))均为低电位，所述数据信号在第二时段(A2)之前保持所述第二高电位信号(S2)且在所述第二时段(A2)开始时转换为低电位；
    在所述保持阶段(B4)，所述上一行栅极输出信号(G(n-1))和所述当前行栅极输出信号(G(n))为低电位、所述下一行栅极输出信号(G(n+1))为高电位V0的脉冲。
  6. 如权利要求5所述的像素驱动电路，其中，所述第一电位(V1)与所述第二电位(V2)之间的关系为公式一：
    Figure PCTCN2020115739-appb-100001
    其中，V1为第一电位V1的电位值，V2为第二电位V2的电位值，C 1为第一电容的电容值，V 0为栅极输出信号的高电位V0的值，C 2为第二电容的电容值，VGL为恒压低电位，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
  7. 如权利要求6所述的像素驱动电路，其中，所述第二电位(V2)与所述第三电位(V3)之间的关系为公式二：
    Figure PCTCN2020115739-appb-100002
    其中，V 2为第二电位V2的电位值，V3为第二电位V3的电位值，C 1为第一电容的电容值，S 2为第二高电位S2的电位值，C 2为第二电 容的电容值，V COM为公共信号的电位值，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
  8. 如权利要求7所述的像素驱动电路，其中，所述第三电位(V3)高于所述栅极输出信号的高电位(V0)是基于所述公式一及所述公式二，根据所述第一高电位信号、所述第二高电位信号、栅极输出信号的高电位(V0)、所述恒压低电位(VGL)和所述公共信号的电位值(V COM)，通过调节所述第一电容的电容值和所述第二电容的电容值实现的。
  9. 如权利要求5所述的像素驱动电路，其中，在所述保持阶段(B4)，所述数据信号在第三时段(A3)内保持低电平，并在所述第三时段(A3)之后由低电平转变为第三高电位信号(S3)；
    下一行栅极输出信号(G(n+1))由使能信号(EMn)替换，所述使能信号(EMn)在所述预充电阶段(B0)、所述第一升压阶段(B1)、所述第二升压阶段(B2)和所述过渡阶段(B3)均为低电位，且在所述保持阶段(B4)为高电位。
  10. 如权利要求5所述的像素驱动电路，其中，在所述保持阶段(B4)，所述数据信号保持低电平。
  11. 一种显示面板，其包括像素驱动电路，所述像素驱动电路包括：
    第一晶体管、第二晶体管、第三晶体管、第一电容、第二电容、存储电容和液晶电容，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管均分别包括源极、栅极和漏极，所述第一电容、所述第二电容、所述存储电容和所述液晶电容均分别包括第一端和第二端；
    所述第一晶体管的栅极电性连接第一节点，源极电性连接所述第二电容的第一端，漏极分别电性连接所述存储电容的第一端和所述液晶电容的第一端；
    所述第二晶体管的栅极接入上一行栅极输出信号(G(n-1))，源极电性接入数据信号，漏极电性连接第一节点；
    所述第三晶体管的栅极接入下一行栅极输出信号(G(n+1))，源极电性连接第一节点，漏极电性连接恒压低电位(VGL)；
    所述第一电容的第一端电性连接第一节点，第二端接入当前行栅极输出信号(G(n))；
    所述第二电容的第一端电性接入数据信号，第二端电性连接第一节点；
    所述存储电容的第二端和所述液晶电容的第一端分别电性连接所述第一晶体管的漏极，第二端分别电性接入公共信号。
  12. 如权利要求11所述的显示面板，其中，所述像素驱动电路具有预充电阶段(B0)、第一升压阶段(B1)、第二升压阶段(B2)、过渡阶段(B3)和保持阶段(B4)；所述第一晶体管、所述第二晶体管和所述第三晶体管均为N型薄膜晶体管；
    在所述预充电阶段(B0)，所述第二晶体管打开，所述第三晶体管关闭，当前行栅极输出信号(G(n))通过所述第二晶体管将所述第一节点的电位充电至第一电位(V1)；
    在所述第一升压阶段(B1)，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第一高电位信号(S1)，所述数据信号通过所述第一电容将所述第一节点的电位由所述第一电位(V1)提升至第二电位(V2)；
    在所述第二升压阶段(B2)，所述第二晶体管和所述第三晶体管关闭，所述数据信号发出第二高电位信号(S2)，通过所述第二电容将所述第一节点的电位由所述第二电位(V2)提升至第三电位(V3)并向所述液晶电容写入第二高电位信号(S2)；其中，所述第三电位(V3)高于所述栅极输出信号的高电位(V0)；
    在所述过渡阶段(B3)，所述第一晶体管、所述第二晶体管关闭和所述第三晶体管均关闭，所述当前行栅极输出信号(G(n))通过第一电容将所述第一节点的电位由第三电位(V3)降至第四电位(V4)后，所述下一行栅极输出信号(G(n+1))将所述第一节点的电位由第四电位(V4)降至恒压低电位(VGL)；
    在所述保持阶段(B4)，所述第一晶体管和所述第二晶体管关闭，所述第三晶体管打开，所述下一行栅极输出信号(G(n+1))将所述第一节点的电位保持为恒压低电位(VGL)。
  13. 如权利要求11所述的显示面板，其中，所述第一晶体管、所述第二晶体管和所述第三晶体管均为氧化物半导体薄膜晶体管。
  14. 如权利要求11所述的显示面板，其中，所述第一晶体管为氧化物半导体薄膜晶体管，所述第二晶体管和所述第三晶体管均为低温多晶硅薄膜晶体管。
  15. 如权利要求12所述的显示面板，其中，
    在所述预充电阶段(B0)，所述上一行栅极输出信号(G(n-1))在初始时段(A0)之前为高电位V0且在所述初始时段(A0)开始时转换为低电位、所述当前行栅极输出信号(G(n))为低电位，所述下一行栅极输出信号(G(n+1))为低电位，所述数据信号在第一时段(A1)之前为第一高电位信号(S1)且在所述第一时段(A1)内为低电位；其中，所述第一高电位信号(S1)与所述第一电位(V1)的电位相同；
    在所述第一升压阶段(B1)，所述上一行栅极输出信号(G(n-1))为低电位、所述当前行栅极输出信号(G(n))为高电位V0，所述下一行栅极输出信号(G(n+1))为低电位，所述数据信号为低电位；
    在所述第二升压阶段(B2)，所述上一行栅极输出信号(G(n-1))为低电位、所述当前行栅极输出信号(G(n))为高电位V0，所述下一行栅极输出信号(G(n+1))为低电位，所述数据信号为第二高电位信号(S2)；
    在所述过渡阶段(B3)，所述上一行栅极输出信号(G(n-1))、所述当前行栅极输出信号(G(n))为低电位和所述当前行栅极输出信号(G(n))均为低电位，所述数据信号在第二时段(A2)之前保持所述第二高电位信号(S2)且在所述第二时段(A2)开始时转换为低电位；
    在所述保持阶段(B4)，所述上一行栅极输出信号(G(n-1)) 和所述当前行栅极输出信号(G(n))为低电位、所述下一行栅极输出信号(G(n+1))为高电位V0的脉冲。
  16. 如权利要求15所述的显示面板，其中，所述第一电位(V1)与所述第二电位(V2)之间的关系为公式一：
    Figure PCTCN2020115739-appb-100003
    其中，V1为第一电位V1的电位值，V2为第二电位V2的电位值，C 1为第一电容C1的电容值，V 0为栅极输出信号的高电位V0的值，C 2为第二电容的电容值，VGL为恒压低电位，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
  17. 如权利要求16所述的显示面板，其中，所述第二电位(V2)与所述第三电位(V3)之间的关系为公式二：
    Figure PCTCN2020115739-appb-100004
    其中，V 2为第二电位V2的电位值，V3为第二电位V3的电位值，C 1为第一电容的电容值，S 2为第二高电位S2的电位值，C 2为第二电容的电容值，V COM为公共信号的电位值，C gs1为第一晶体管的单侧寄生电容值，C gs2为第二晶体管的单侧寄生电容值，C gs3为第三晶体管的单侧寄生电容值。
  18. 如权利要求17所述的显示面板，其中，所述第三电位(V3)高于所述栅极输出信号的高电位(V0)是基于所述公式一及所述公式二，根据所述第一高电位信号、所述第二高电位信号、栅极输出信号的高电位(V0)、所述恒压低电位(VGL)和所述公共信号的电位值(V COM)，通过调节所述第一电容的电容值和所述第二电容的电容值实现的。
  19. 如权利要求15所述的显示面板，其中，在所述保持阶段(B4)，所述数据信号在第三时段(A3)内保持低电平，并在所述第三时段(A3)之后由低电平转变为第三高电位信号(S3)；
    下一行栅极输出信号(G(n+1))由使能信号(EMn)替换，所述使能信号(EMn)在所述预充电阶段(B0)、所述第一升压阶段(B1)、所述第二升压阶段(B2)和所述过渡阶段(B3)均为低电位，且在所述保持阶段(B4)为高电位。
  20. 如权利要求15所述的显示面板，其中，在所述保持阶段(B4)，所述数据信号保持低电平。
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