WO2021164092A1 - 像素驱动电路及其驱动方法、显示面板 - Google Patents

像素驱动电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2021164092A1
WO2021164092A1 PCT/CN2020/080621 CN2020080621W WO2021164092A1 WO 2021164092 A1 WO2021164092 A1 WO 2021164092A1 CN 2020080621 W CN2020080621 W CN 2020080621W WO 2021164092 A1 WO2021164092 A1 WO 2021164092A1
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Prior art keywords
transistor
node
light
driving circuit
voltage
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PCT/CN2020/080621
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English (en)
French (fr)
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薛炎
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/757,402 priority Critical patent/US11315516B2/en
Publication of WO2021164092A1 publication Critical patent/WO2021164092A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • This application relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel.
  • Blue-phase liquid crystal has the advantages of sub-millimeter response time, simple preparation process and wide viewing angle, and has attracted more and more researchers' attention worldwide.
  • the most important feature of blue phase liquid crystal is that it requires a high voltage to drive the liquid crystal molecules, and the voltage is greater than 30V.
  • the current blue phase liquid crystal panel pixel circuit generally adopts the 3T1C structure.
  • This circuit has a poor effect of compensating the threshold voltage Vth, and the threshold voltage Vth will be negative.
  • the data voltage is difficult to stably store in the storage capacitor, and the data signal will gradually be lost.
  • the screen flickers caused by the above, the product quality is affected.
  • the purpose of the present invention is to provide a pixel driving circuit, a driving method thereof, and a display panel to solve the technical problems of high power consumption of blue phase liquid crystal panels and poor compensation effect of threshold voltage Vth leading to serious data signal loss.
  • the present invention provides a pixel driving circuit, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a bootstrap capacitor Cbt, a storage capacitor Cst, and a light emitting element D; specifically
  • the gate of the first transistor T1 is connected to the first node G, the source of the first transistor T1 is connected to the second node S, and the drain of the first transistor T1 is connected to the power supply voltage VDD;
  • the gate of the second transistor T2 is connected to the first scan signal Scan1, the source of the second transistor T2 is connected to the data signal Data1, and the drain of the second transistor T2 is connected to the first node G;
  • the third The gate of the transistor T3 is connected to the first scan signal Scan1, the source of the three transistor T3 is connected to the sensing signal Ref, and the drain of the three transistor T3 is connected to the second node S;
  • the fourth The gate of the transistor T4 is connected to the second scan signal Scan2, the source of
  • first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are any one of a low-temperature polysilicon transistor, an oxide semiconductor transistor, or an amorphous silicon transistor.
  • first scan signal Scan1 and the second scan signal Scan2 are both provided by an external timing controller.
  • the fourth transistor T4 is turned off, and the storage capacitor Cst provides a constant driving current for the light emitting element D.
  • the present invention also provides a driving method, which includes the following steps:
  • the pixel driving circuit is initialized
  • the threshold voltage Vth of the first transistor T1 is detected and the threshold voltage Vth is stored on the storage capacitor Cst;
  • the storage capacitor Cst In the light-emitting phase, the storage capacitor Cst generates a driving current and supplies it to the light-emitting element D for driving the light-emitting display of the light-emitting element D.
  • the data input stage includes the steps:
  • the first scan signal Scan1, the power supply voltage VDD, the data signal Data1, and the sensing signal Ref acquire a high potential
  • the first transistor T1, the second transistor T2, and the The third transistors T3 are all turned on, and the bootstrap capacitor Cbt is charged;
  • the first scan signal Scan1 drops from a high level to a low level
  • the second scan signal Scan2 acquires a high level
  • the second transistor T2 and the third transistor T3 are turned off
  • the fourth The transistor T4 is turned on
  • the potentials of the first node G, the second node S, and the third node M are raised to a driving voltage
  • the storage capacitor Cst is charged.
  • the voltage of the data signal Data1 is 1V-10V; and/or, the voltage of the sensing signal Ref is 1V; and/or, the power supply voltage VDD is 30V; and/or, the driving voltage It is 30V.
  • the second scan signal Scan2 drops from a high level to a low level
  • the fourth transistor T4 is turned off
  • the storage capacitor Cst is the light-emitting element D
  • a constant driving current is provided, and the light-emitting element D continues to emit light.
  • the first scan signal Scan1, the second scan signal Scan2, and the data signal Data1 all acquire a low potential, and the light-emitting element D emits light.
  • a display panel includes the pixel driving circuit as described above.
  • the technical effect of the present invention is to provide a pixel driving circuit and a driving method thereof, and a display panel.
  • the power supply voltage VDD is transmitted to the third node N and stored in the storage capacitor Cst.
  • the fourth transistor T4 is turned off, the storage capacitor Cst provides a constant driving current for the light-emitting element D, which can significantly reduce the voltage of the data signal Data1, thereby achieving the purpose of low power consumption.
  • the pixel driving circuit With the threshold voltage Vth compensation effect, the Vdata voltage only needs to be maintained at 10V, which is beneficial to improve the brightness uniformity.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit in an embodiment of the present invention
  • FIG. 2 is a timing diagram of input source signals of the pixel driving circuit according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of output waveforms of the pixel driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a driving timing diagram of the pixel driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a compensation timing diagram of the pixel driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of detecting a negative threshold voltage ( ⁇ Vth) of the pixel driving circuit according to an embodiment of the present invention.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • this embodiment provides a pixel driving circuit with a 4T2C structure, which includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a bootstrap capacitor Cbt, a storage capacitor Cst, and Light emitting element D; specifically, the gate of the first transistor T1 is connected to the first node G, the source of the first transistor T1 is connected to the second node S, and the drain of the first transistor T1 is connected to the power supply voltage VDD; the gate of the second transistor T2 is connected to the first scan signal Scan1, the source of the second transistor T2 is connected to the data signal Data1, and the drain of the second transistor T2 is connected to the first node G;
  • the gate of the third transistor T3 is connected to the first scan signal Scan1, the source of the three transistor T3 is connected to the sensing signal Ref, and the drain of the three transistor T3 is connected to the second node S
  • the gate of the fourth transistor T4 is connected to the second scan signal Scan2, the source of the
  • the power supply voltage VDD is a high potential
  • the ground voltage VSS is a low potential
  • the first transistor T1 is a driving transistor and provides a constant driving current for the light-emitting element D.
  • the second transistor T2 is a switching transistor, which has a first scan signal Scan1, a controlled gate, a source accessed by the data signal Data1, and a drain connected to the first node G, and is electrically connected to the first scan signal Scan1.
  • the first scan signal Scan1 is provided by an external timing controller.
  • the bootstrap capacitor Cbt is connected between the first node G and the second node S, and is used to maintain a predetermined voltage within one frame.
  • the light-emitting element D is liquid crystal.
  • the fourth transistor T4 and the storage capacitor Cst are added reasonably, the power supply voltage VDD is transmitted to the third node N and stored in the storage capacitor Cst, and then the fourth transistor T4 is turned off.
  • the capacitor Cst provides a constant driving current for the light-emitting element D, which can significantly reduce the voltage of the data signal Data1, thereby achieving the purpose of low power consumption.
  • the method also has a threshold voltage Vth compensation effect, which is beneficial to improve brightness uniformity.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are any one of a low-temperature polysilicon transistor, an oxide semiconductor transistor, or an amorphous silicon transistor.
  • the first scan signal Scan1 and the second scan signal Scan2 are both provided by an external timing controller.
  • FIG. 2 is a timing diagram of the input source signal of the pixel driving circuit of this embodiment.
  • FIG. 3 is a schematic diagram of the output waveform of the pixel driving circuit of this embodiment.
  • FIG. 4 is a driving timing diagram of the pixel driving circuit of this embodiment.
  • FIG. 5 is a compensation timing diagram of the pixel driving circuit of this embodiment.
  • the driving method includes the following steps:
  • the pixel driving circuit is initialized
  • the threshold voltage Vth of the first transistor T1 is detected and the threshold voltage Vth is stored on the storage capacitor Cst;
  • the storage capacitor Cst In the light-emitting phase N3, the storage capacitor Cst generates a driving current and supplies it to the light-emitting element D for driving the light-emitting element D to emit light.
  • the detected threshold voltage of the first transistor T1 is V data1 -Vth.
  • the negative bias ( ⁇ Vth) of the threshold voltage Vth is simulated to be 0, 2V, respectively.
  • the voltage detected by the sensing signal Ref is shown in FIG. 6 specifically, which is a schematic diagram of detecting a negative threshold voltage ( ⁇ Vth) of the pixel driving circuit of this embodiment.
  • the first scan signal Scan1, the second scan signal Scan2, the data signal Data1, and the sensing signal Ref acquire a high potential
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on, and the bootstrap capacitor Cbt is charged.
  • the data input stage N1 and N2 include the following steps:
  • the first scan signal Scan1 the power supply voltage VDD, the data signal Data1, the sensing signal Ref acquire a high potential
  • the first scan signal Scan1 drops from a high potential to a low potential
  • the second scan signal Scan2 acquires a high potential
  • the second transistor T2 and the third transistor T3 are turned off, and at the same time the first scan signal Scan1 is turned off.
  • the four transistor T4 is turned on, the potentials of the first node G, the second node S, and the third node M are raised to a driving voltage, and the storage capacitor Cst is charged.
  • the voltage of the data signal Data1 is 1V-10V; and/or, the voltage of the sensing signal Ref is 1V; and/or, the power supply voltage VDD is 30V; and/or, The driving voltage is 30V.
  • each signal in the pixel drive circuit may be as shown in Table 1 below.
  • the fourth transistor T4 is turned off, and the storage capacitor Cst A constant driving current is provided for the light-emitting element D, and the light-emitting element D continues to emit light.
  • the first scan signal Scan1, the second scan signal Scan2, and the data signal Data1 all acquire a low potential, and the light-emitting element D emits light.
  • FIG. 6 is a schematic diagram of the detection of the negative threshold voltage ( ⁇ Vth) of the pixel driving circuit of the embodiment, which mainly reflects the output waveform of the negative bias ( ⁇ Vth) of the threshold voltage of the first transistor T1 on the current flowing through the light-emitting element D Schematic.
  • ⁇ Vth negative threshold voltage
  • the bootstrap capacitor Cbt discharges to compensate for the negative threshold voltage ( ⁇ Vth), and the threshold voltage Vth is raised to a stable high voltage.
  • the fourth transistor T4 and the storage capacitor Cst are added reasonably to transmit the power supply voltage VDD to the third node N and store it in the storage capacitor Cst, and then turn off the fourth transistor T4.
  • the capacitor Cst provides a constant driving current for the light-emitting element D, which can significantly reduce the voltage of the data signal Data1, thereby achieving the purpose of low power consumption.
  • the method also has a threshold voltage Vth compensation effect, which is beneficial to improve brightness uniformity.
  • Vdata1 is the voltage of the data signal Data1, which is 10V
  • the voltage of Vdata is 30V
  • the power consumption is very different. Therefore, the present invention achieves the purpose of low power consumption.
  • An embodiment of the present invention also provides a display panel including the pixel driving circuit described above.
  • the technical effect of the present invention is to provide a pixel driving circuit and a driving method thereof, and a display panel.
  • the power supply voltage VDD is transmitted to the third node N and stored in the storage capacitor Cst.
  • the fourth transistor T4 is turned off, the storage capacitor Cst provides a constant driving current for the light-emitting element D, which can significantly reduce the voltage of the data signal Data1, thereby achieving the purpose of low power consumption.
  • the pixel driving circuit With the threshold voltage Vth compensation effect, the Vdata voltage only needs to be maintained at 10V, which is beneficial to improve the brightness uniformity.

Abstract

一种像素驱动电路及其驱动方法、显示面板，像素驱动电路包括第一晶体管（T1）、第二晶体管（T2）、第三晶体管（T3）、第四晶体管（T4）、自举电容（Cbt）、储存电容（Cst）以及发光元件（D）。

Description

像素驱动电路及其驱动方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板。
背景技术
蓝相液晶具有亚毫米级的响应时间，以及制备工艺简单，视角广的优点，在全球范围内受到越来越多研究人员的关注。然而蓝相液晶的最主要特点是需要高的电压才能驱动液晶分子，电压大于30V，根据面板的动态功耗计算公式p＝fcV 2，动态功耗随着数据电压呈指数变化趋势。因此传统蓝相液晶像素电路需要的数据线输入较高电压，即VData1>30V，蓝相液晶面板的功耗较大。
同时，目前蓝相液晶面板像素电路普遍采用3T1C结构，该电路补偿阈值电压Vth的效果较差，会出现阈值电压Vth偏负，数据电压难以稳定存储于存储电容中，数据信号会逐渐丢失，宏观上造成画面闪烁现象，产品品质受到影响。
技术问题
本发明的目的在于，提供一种像素驱动电路及其驱动方法、显示面板以解决蓝相液晶面板的功耗较大，以及阈值电压Vth补偿效果差导致数据信号损失严重的技术问题。
技术解决方案
为实现上述目的，本发明提供一种像素驱动电路，包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、自举电容Cbt、储存电容Cst以及发光元件D；具体的，所述第一晶体管T1的栅极连接第一节点G，所述第一晶体管T1的源极连接第二节点S，所述第一晶体管T1的漏极接入电源电压VDD；所述第二晶体管T2的栅极接入第一扫描信号Scan1，所述第二晶体管T2的源极接入数据信号Data1，所述第二晶体管T2的漏极连接所述第一节点G；所述第三晶体管T3的栅极接入所述第一扫描信号Scan1，所述三晶体管T3的源极接入感测信号Ref，所述三晶体管T3的漏极连接所述第二节点S；所述第 四晶体管T4的栅极接入第二扫描信号Scan2，所述第四晶体管T4的源极连接所述第二节点S，所述第二晶体管T4的漏极连接第三节点M；所述自举电容Cbt的一端连接所述第一节点G，另一端连接所述第二节点S；所述储存电容Cst的一端连接所述第三节点M，另一端连接接地电压VSS；所述发光元件D的阳极连接所述第三节点M，其阴极连接公共电压信号Tcom。
进一步地，所述第一晶体管T1、第二晶体管T2、第三晶体管T3、所述第四晶体管T4均为低温多晶硅晶体管、氧化物半导体晶体管、或非晶硅晶体管中的任一种。
进一步地，所述第一扫描信号Scan1、所述第二扫描信号Scan2均由外部时序控制器提供。
进一步地，当所述第二扫描信号Scan2由高压降为低压时，所述第四晶体管T4关闭，所述储存电容Cst为所述发光元件D提供恒定的驱动电流。
为实现上述目的，本发明还提供一种驱动方法，所述驱动方法包括如下步骤：
初始化阶段，所述像素驱动电路被初始化；
数据输入检测阶段，所述第一晶体管T1的阈值电压Vth被检测出并将所述阈值电压Vth存储至所述存储电容Cst上；以及
发光阶段，所述存储电容Cst产生驱动电流并提供至所述发光元件D，用于驱动所述发光元件D的发光显示。
进一步地，在所述数据输入阶段包括步骤：
第一阶段，所述第一扫描信号Scan1、所述电源电压VDD、所述数据信号Data1、所述感测信号Ref获取高电位，所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3均打开，所述自举电容Cbt被充电；以及
第二阶段，所述第一扫描信号Scan1由高电位降为低电位，所述第二扫描信号Scan2获取高电位，所述第二晶体管T2及所述第三晶体管T3关闭，同时所述第四晶体管T4打开，所述第一节点G、所述第二节点S及所述第三节点M的电位被抬升至一驱动电压，所述存储电容Cst被充电。
进一步地，所述数据信号Data1的电压为1V-10V；和/或，所述感测信号Ref的电压为1V；和/或，所述电源电压VDD为30V；和/或，所述驱动电压为 30V。
进一步地，当所述数据输入阶段进入所述发光阶段时，所述第二扫描信号Scan2由高电位降为低电位，所述第四晶体管T4关闭，所述储存电容Cst为所述发光元件D提供恒定的驱动电流，所述发光元件D持续发光。
进一步地，在所述发光阶段，所述第一扫描信号Scan1、所述第二扫描信号Scan2、所述数据信号Data1均获取低电位，所述发光元件D发光。
一种显示面板，包括如前文所述的像素驱动电路。
有益效果
本发明的技术效果在于，提供一种像素驱动电路及其驱动方法、显示面板，通过合理的增加第四晶体管T4和存储电容Cst，将电源电压VDD输送至第三节点N并储存于存储电容Cst中，再关闭第四晶体管T4，所述储存电容Cst为所述发光元件D提供恒定的驱动电流，能够显著降低数据信号Data1的电压，从而实现低功耗的目的，此外，所述像素驱动电路兼具阈值电压Vth补偿效果，Vdata电压仅需维持在10V，利于提升亮度均匀性。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本发明实施例中一种像素驱动电路的结构示意图；
图2为本发明实施例的所述像素驱动电路的输入源信号时序图；
图3为本发明实施例的所述像素驱动电路的输出波形示意图；
图4为本发明实施例的所述像素驱动电路的驱动时序图；
图5为本发明实施例的所述像素驱动电路的补偿时序图；
图6为本发明实施例的所述像素驱动电路的阈值电压负偏(△Vth)探测示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳 动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
如图1所示，本实施提供一种像素驱动电路，为4T2C结构，其包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、自举电容Cbt、储存电容Cst以及发光元件D；具体的，所述第一晶体管T1的栅极连接第一节点G，所述第一晶体管T1的源极连接第二节点S，所述第一晶体管T1的漏极接入电源电压VDD；所述第二晶体管T2的栅极接入第一扫描信号Scan1，所述第二晶体管T2的源极接入数据信号Data1，所述第二晶体管T2的漏极连接所述第一节点G；所述第三晶体管T3的栅极接入所述第一扫描信号Scan1，所述三晶体管T3的源极接入感测信号Ref，所述三晶体管T3的漏极连接所述第二节点S；所述第四晶体管T4的栅极接入第二扫描信号Scan2，所述第四晶体管T4的源极连接所述第二节点S，所述第二晶体管T4的漏极连接第三节点M；所述自举电容Cbt的一端连接所述第一节点G，另一端连接所述第二节点S；所述储存电容Cst的一端连接所述第三节点M，另一端连接接地电压VSS；所述发光元件D的阳极连接所述第三节点M，其阴极连接公共电压信号Tcom。
具体地，所述电源电压VDD为高电位，所述接地电压VSS为低电位。
所述第一晶体管T1为驱动晶体管，为所述发光元件D提供恒定的驱动电流。
所述第二晶体管T2为开关晶体管，其具有受的第一扫描信号Scan1，控制的栅极及受数据信号Data1接入的源极和第一节点G连接的漏极，并且电连接所述第一晶体管T1、所述自举电容Cbt。其中，所述第一扫描信号Scan1由外部时序控制器提供。
所述自举电容Cbt连接在第一节点G和第二节点S之间，用于在一帧时间内维持预定电压。
所述发光元件D为液晶。
本实施例通过合理的增加第四晶体管T4和存储电容Cst，将所述电源电压VDD输送至第三节点N并储存于所述存储电容Cst中，再关闭所述第四晶体管T4，所述储存电容Cst为所述发光元件D提供恒定的驱动电流，能够显著降低数据信号Data1的电压，从而实现低功耗的目的，此外，该方法兼具阈值电压Vth补偿效果，利于提升亮度均匀性。
本实施例中，所述第一晶体管T1、第二晶体管T2、第三晶体管T3、所述第四晶体管T4为低温多晶硅晶体管、氧化物半导体晶体管或非晶硅晶体管中的任一种。所述第一扫描信号Scan1、所述第二扫描信号Scan2均由外部时序控制器提供。
本实施例还提供一种驱动方法，包括如前文所述的像素驱动电路。图2为本实施例的所述像素驱动电路的输入源信号时序图。图3为本实施例的所述像素驱动电路的输出波形示意图。图4为本实施例的所述像素驱动电路的驱动时序图。图5为本实施例的所述像素驱动电路的补偿时序图。
具体的，结合图2-图5，所述驱动方法包括如下步骤：
初始化阶段N0，所述像素驱动电路被初始化；
数据输入检测阶段，所述第一晶体管T1的阈值电压Vth被检测出并将所述阈值电压Vth存储至所述存储电容Cst上；以及
发光阶段N3，所述存储电容Cst产生驱动电流并提供至所述发光元件D，用于驱动所述发光元件D的发光显示。
其中，被检测出的所述第一晶体管T1的阈值电压为V data1-Vth，在图5所示的补偿时序图基础上，模拟了阈值电压Vth的负偏(△Vth)分别为0，2V，4V时，所述感测信号Ref探测得到的电压，具体见图6所示，为本实施例的所述像素驱动电路的阈值电压负偏(△Vth)探测示意图。
本实施例中，在所述数据输入阶段N1、N2，所述第一扫描信号Scan1、所述第二扫描信号Scan2、所述数据信号Data1、感测信号Ref获取高电位，所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3均被导通，所述自举电容Cbt被充电。
本实施例中，在所述数据输入阶段N1、N2包括步骤：
第一阶段N1，所述第一扫描信号Scan1、所述电源电压VDD、所述数据信号Data1、所述感测信号Ref获取高电位，所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3均打开，所述自举电容Cbt被充电；此时所述第一晶体管T1工作于饱和区，其栅极电压Vgs＝9V；以及
第二阶段N2，所述第一扫描信号Scan1由高电位降为低电位，所述第二扫描信号Scan2获取高电位，所述第二晶体管T2及所述第三晶体管T3关闭，同时所述第四晶体管T4打开，所述第一节点G、所述第二节点S及所述第三节点M的电位被抬升至一驱动电压，所述存储电容Cst被充电。
其中由I＝1/2*C*μ*W/L*(Vgs-Vref) 2，可知所述第二节点S升高的电位与阈值电压Vth无关。
本实施例中，所述数据信号Data1的电压为1V-10V；和/或，所述感测信号Ref的电压为1V；和/或，所述电源电压VDD为30V；和/或，所述驱动电压为30V。
具体的，所述像素驱动电路中各信号具体的波形与电位关系可以如下表1所示。
Figure PCTCN2020080621-appb-000001
表1
其中在开机之时，所述第一扫描信号Scan1升为高电位，所述数据信号Data1的电压变为Vdata+Vth，即从1V变为10V，其变换量为所述第一晶体管 T1工作于饱和区的最高栅极电压Vgs＝9V。
本实施例中，当所述数据输入阶段N1、N2进入所述发光阶段N3时，所述第二扫描信号Scan2由高电位降为低电位，所述第四晶体管T4关闭，所述储存电容Cst为所述发光元件D提供恒定的驱动电流，所述发光元件D持续发光。
进一步地，在所述发光阶段，所述第一扫描信号Scan1、所述第二扫描信号Scan2、所述数据信号Data1均获取低电位，所述发光元件D发光。
图6为本实施例的所述像素驱动电路的阈值电压负偏(△Vth)探测示意图，主要体现所述第一晶体管T1阈值电压负偏(△Vth)对流经发光元件D电流影响的输出波形示意图。在K1阶段出现阈值电压负偏(△Vth)，在K2阶段所述自举电容Cbt放电补偿阈值电压负偏(△Vth)，阈值电压Vth被拉升抬高为一稳定高压。由此可知，本实施例通过合理的增加第四晶体管T4和存储电容Cst，将所述电源电压VDD输送至第三节点N并储存于存储电容Cst中，再关闭第四晶体管T4，所述储存电容Cst为所述发光元件D提供恒定的驱动电流，能够显著降低数据信号Data1的电压，从而实现低功耗的目的，此外，该方法兼具阈值电压Vth补偿效果，利于提升亮度均匀性。
采用本发明实施例，其数据线的动态功耗为p＝fcVdata1 2，Vdata1是所述数据信号Data1的电压，为10V；如采用传统液晶显示器1T1C的像素结构，则数据线的动态功耗为p＝fcVdata 2，Vdata电压为30V，其功耗相差悬殊，因此本发明实现了低功耗的目的。
本发明实施例还提供一种显示面板，包括如前文所述的像素驱动电路。
本发明的技术效果在于，提供一种像素驱动电路及其驱动方法、显示面板，通过合理的增加第四晶体管T4和存储电容Cst，将电源电压VDD输送至第三节点N并储存于存储电容Cst中，再关闭第四晶体管T4，所述储存电容Cst为所述发光元件D提供恒定的驱动电流，能够显著降低数据信号Data1的电压，从而实现低功耗的目的，此外，所述像素驱动电路兼具阈值电压Vth补偿效果，Vdata电压仅需维持在10V，利于提升亮度均匀性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的进行了一种像素驱动电路及其驱动方法、显 示面板的详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (10)

  1. 一种像素驱动电路，其包括：
    第一晶体管，所述第一晶体管的栅极连接第一节点，所述第一晶体管的源极连接第二节点，所述第一晶体管的漏极接入电源电压；
    第二晶体管，所述第二晶体管的栅极接入第一扫描信号，所述第二晶体管的源极接入数据信号，所述第二晶体管的漏极连接所述第一节点；
    第三晶体管，所述第三晶体管的栅极接入所述第一扫描信号，所述第三晶体管的源极接入感测信号，所述第三晶体管的漏极连接所述第二节点；
    第四晶体管，所述第四晶体管的栅极接入第二扫描信号，所述第四晶体管的源极连接所述第二节点，所述第四晶体管的漏极连接第三节点；
    自举电容，其一端连接所述第一节点，另一端连接所述第二节点；
    储存电容，其一端连接所述第三节点，另一端连接接地电压；以及
    发光元件，其阳极连接所述第三节点，其阴极连接公共电压信号。
  2. 如权利要求1所述的像素驱动电路，其中，
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管为低温多晶硅晶体管、氧化物半导体晶体管或非晶硅晶体管中的任一种。
  3. 如权利要求1所述的像素驱动电路，其中，
    所述第一扫描信号、所述第二扫描信号均由外部时序控制器提供。
  4. 如权利要求1所述的像素驱动电路，其中，
    当所述第二扫描信号由高压降为低压时，所述第四晶体管关闭，所述储存电容为所述发光元件提供恒定的驱动电流。
  5. 一种像素驱动电路的驱动方法，包括权利要求1中的一种像素驱动电路，其包括如下步骤：
    初始化阶段，所述像素驱动电路被初始化；
    数据输入检测阶段，所述第一晶体管的阈值电压被检测出并将所述阈值电压存储至所述存储电容上；以及
    发光阶段，所述存储电容产生驱动电流并提供至所述发光元件，用于驱动所述发光元件的发光显示。
  6. 如权利要求5所述的一种像素驱动电路的驱动方法，其中，在所述数 据输入阶段包括步骤：
    第一阶段，所述第一扫描信号、所述数据信号、所述电源电压、所述感测信号获取高电位，所述第一晶体管、所述第二晶体管、所述第三晶体管均打开，所述自举电容被充电；以及
    第二阶段，所述第一扫描信号由高电位降为低电位，所述第二扫描信号获取高电位，所述第二晶体管及所述第三晶体管关闭，同时所述第四晶体管打开，所述第一节点、所述第二节点及所述第三节点的电位被抬升至一驱动电压，所述存储电容被充电。
  7. 如权利要求6所述的一种像素驱动电路的驱动方法，其中，
    所述数据信号的电压为1V-10V；和/或，
    所述感测信号的电压为1V；和/或，
    所述电源电压为30V；和/或，
    所述驱动电压为30V。
  8. 如权利要求5所述的一种像素驱动电路的驱动方法，其中，
    当所述数据输入阶段进入所述发光阶段时，所述第二扫描信号由高电位降为低电位，所述第四晶体管关闭，所述储存电容为所述发光元件提供恒定的驱动电流，所述发光元件持续发光。
  9. 如权利要求6所述的一种像素驱动电路的驱动方法，其中，
    在所述发光阶段，所述第一扫描信号、所述第二扫描信号、所述数据信号均获取低电位，所述发光元件发光。
  10. 一种显示面板，包括如权利要求1所述的像素驱动电路。
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