CN108877685A - 一种oled像素驱动电路及oled显示装置 - Google Patents
一种oled像素驱动电路及oled显示装置 Download PDFInfo
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Abstract
本发明揭露一种OLED像素驱动电路及OLED显示装置,采用3T1C结构,通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段;同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k,在显示模式下进行相应的数据补偿,能够提高显示的均匀性,提高发光效率。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种OLED像素驱动电路及OLED显示装置。
背景技术
近年来OLED(Organic Light Emitting Diode,有机发光二极管)显示技术的快速发展,推动曲面和柔性显示触控产品迅速进入市场,相关领域技术更新也是日新月异。OLED是指利用有机半导体材料和发光材料在电场驱动下,通过载流子注入和复合导致发光的二极管。OLED显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽,可实现柔性显示与大面积全色显示等诸多优点,被业界公认为是最有发展潜力的显示装置。
OLED是电流驱动器件,当有电流流经时OLED发光,且发光亮度由流经OLED自身的电流决定。大部分已有的IC(Integrated Circuit,集成电路)都只传输电压信号,故OLED的像素驱动电路需要完成将电压信号转变为电流信号的任务。现有技术中的OLED像素驱动电路通常为2T1C(2transistor 1capacitance,即两个薄膜晶体管加一个电容的结构),以将电压变换为电流。
参考图1,现有技术中的用于OLED的2T1C像素驱动电路架构图。如图1所示,现有2T1C像素驱动电路包括:第一薄膜晶体管T1、第二薄膜晶体管T2、及电容Cs,其中第一薄膜晶体管T1为驱动TFT,第二薄膜晶体管T2为开关TFT,电容Cs为存储电容。具体地,第一薄膜晶体管T1的源极电性连接有机发光二极管D0的阳极、漏极接入电源电压OVDD、栅极电性连接于第一节点G;有机发光二极管D0的阴极接入公共接地电压OVSS;第二薄膜晶体管T2的源极电性连接于第一节点G、栅极接入扫描信号Scan,漏极接入数据信号Data;电容Cs的一端电性连接第一薄膜晶体管T1的栅极,另一端电性连接第一薄膜晶体管T1的源极。OLED显示时,扫描信号Scan控制T2导通,数据信号Data经过T2进入到T1的栅极及电容Cs,然后T2关断,由于电容Cs的存储作用,T1的栅极电压仍可继续保持数据信号电压,使得T1处于导通状态,驱动电流通过T1进入有机发光二极管D0,驱动有机发光二极管D0发光。
根据晶体管I-V方程:
Ids,sat=k·(VGS-Vth,T1)2=k·(VG-VS-Vth,T1)2 (1)
式(1)中K为本征导电因子,Ids,sat的大小与驱动TFT即T1的阈值电压Vth有关。
由于面板制程的不稳定性等原因,使得面板内每个子像素的驱动TFT的阈值电压Vth会有差别。因此,即使数据信号Data的电压Vdata相等的施加到各像素的驱动TFT,也会出现流入有机发光二极管的电流不一致的情况,导致显示图像质量的均一性难以实现。
另外,随着驱动TFT驱动时间的推移,会造成TFT材料老化、变异,导致驱动TFT的阈值电压Vth会漂移等问题。并且面板内TFT材料的老化程度不同,导致面板内各驱动TFT的阈值电压Vth漂移量不同,也会造成面板显示的不均匀现象,并且随着驱动时间的推移,TFT材料的老化变得更严重。即使驱动电压相同,流经有机发光二极管的发光电流也很可能不同,造成亮度不均匀。加之发光晶体管器件的老化,会使发光晶体管的开启电压上升,流入有机发光二极管的电流逐渐减小,导致面板亮度降低、发光效率下降等问题。
参考图2,现有技术中的用于OLED的3T1C像素驱动电路架构图。如图2所示,现有3T1C像素驱动电路包括:第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、电容Cs、电容COLED及电容Cp,其中第一薄膜晶体管T1为驱动TFT。与图1所示2T1C像素驱动电路相比,现有3T1C像素驱动电路增设了如下组件:电性连接于有机发光二极管D0的阳极与阴极之间的电容COLED,源极电性连接第一薄膜晶体管T1的源极、漏极接入感测控制信号Sense,栅极接入扫描信号Scan的第三薄膜晶体管T3,一端接入第三薄膜晶体管T3漏极另一端接地的电容Cp,接入感测控制信号Sense的参考电压Vref,通过开关SW0接入感测控制信号Sense的模数转换器ADC0。现有3T1C像素驱动电路通过感测到驱动薄膜晶体管即T1的阈值电压Vth,以对阈值电压Vth进行补偿,但其只能补偿驱动薄膜晶体管的阈值电压Vth,无法补偿OLED老化对亮度的影响。当OLED老化时k值会漂移,且各子像素的OLED器件随时间的漂移老化程度不一致,导致面板显示的亮度、发光效率下降,亮度不均匀等问题。
因此,可补偿驱动薄膜晶体管的阈值电压Vth漂移以及补偿OLED老化后k值的漂移,提升OLED面板亮度的均匀性成为亟待解决的技术问题。
发明内容
本发明的目的在于,提供一种OLED像素驱动电路及OLED显示装置,可补偿驱动薄膜晶体管的阈值电压Vth漂移以及补偿OLED老化后k值的漂移,提升OLED面板亮度的均匀性。
为实现上述目的,本发明提供了一种OLED像素驱动电路,所述驱动电路工作状态包括显示模式和感测模式,所述驱动电路包括:第一薄膜晶体管,栅极电性连接第一节点,源极电性连接第二节点,漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压;第二薄膜晶体管,栅极接入扫描信号,源极电性连接所述第一节点,漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器;第三薄膜晶体管,栅极接入扫描信号,源极电性连接所述第二节点,漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器;电容,一端电性连接所述第一节点,另一端电性连接所述第二节点;有机发光二极管,阳极电性连接所述第二节点,阴极接入公共接地电压;在显示模式下,所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通;显示模式分为数据写入阶段与发光阶段,所述扫描信号在数据写入阶段为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通,所述数据电压与所述参考电压接入电路,所述扫描信号在发光阶段为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断,所述电容存储的电荷使得所述有机发光二极管发光;在感测模式下,所述第五开关管、第三开关管先在相应的电平控制信号控制下导通,然后所述第五开关管、第三开关管在相应的电平控制信号控制下关断,同时所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通;感测模式分为电平初始化阶段与感测阶段,所述扫描信号始终为高电平,在电位初始化阶段所述第二薄膜晶体管与所述第三薄膜晶体管导通,所述初始化电压与所述参考电压接入电路,在感测阶段所述数据电流接入电路,通过输入不同数据电流使得所述第一模数转换器与所述第二模数转换器感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
为实现上述目的,本发明还提供了一种OLED显示装置,包括本发明所述的OLED像素驱动电路。
本发明的优点在于,本发明提供的OLED像素驱动电路及OLED显示装置,采用3T1C结构,通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段;同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k,在显示模式下进行相应的数据补偿,能够提高显示的均匀性,提高发光效率。
附图说明
图1,现有技术中的用于OLED的2T1C像素驱动电路架构图;
图2,现有技术中的用于OLED的3T1C像素驱动电路架构图;
图3,本发明所述的OLED像素驱动电路第一实施例所示架构图;
图4为图3所述的OLED像素驱动电路显示模式时序图;
图5为图3所述的OLED像素驱动电路感测模式时序图;
图6,本发明所述的OLED像素驱动电路第二实施例所示架构图;
图7为图6所述的OLED像素驱动电路显示模式时序图;
图8为图6所述的OLED像素驱动电路感测模式时序图。
具体实施方式
下面结合附图以及实施例,对本发明提供的OLED像素驱动电路及OLED显示装置作详细说明。显然,所描述的实施例仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
参考图3-5,其中图3为本发明所述的OLED像素驱动电路第一实施例所示架构图,图4为图3所述的OLED像素驱动电路显示模式时序图,图5为图3所述的OLED像素驱动电路感测模式时序图。所述驱动电路包括:第一至第三薄膜晶体管T1-T3、第一至第六开关管S1-S6、电容Cs、有机发光二极管D0、以及第一、第二模数转换器ADC1、ADC2;所述驱动电路工作状态包括显示模式和感测模式。
本实施例中,第一至第六开关管S1-S6、第一模数转换器ADC1以及第二模数转换器ADC2均设置在驱动IC30内,以提高电路的集成度。其它实施例中,上述元件也可以直接设置在面板上。
第一薄膜晶体管T1,栅极电性连接第一节点g,源极电性连接第二节点s,漏极通过第一开关管S1接入数据电流Idata、同时通过第二开关管S1接入电源电压OVDD。其中第一薄膜晶体管T1为对有机发光二极管D0进行驱动的驱动薄膜晶体管。
第二薄膜晶体管T2,栅极接入扫描信号Scan,源极电性连接第一节点g,漏极分别接入数据信号Data、通过第五开关管S5在显示模式下接入数据电压Vdata及在感测模式下接入初始化电压Vini、以及通过第六开关管S6接入第一模数转换器ADC1。
第三薄膜晶体管T3,栅极接入扫描信号Scan,源极电性连接第二节点s,漏极通过第三开关管S3接入参考电压Vref、同时通过第四开关管S4接入第二模数转换器ADC2。
电容Cs,一端电性连接第一节点g,另一端电性连接第二节点s。
有机发光二极管D0,阳极电性连接第二节点s,阴极接入公共接地电压OVSS。
在显示模式下,第二开关管S2、第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下导通。显示模式分为数据写入阶段t1与发光阶段t2,所述扫描信号Scan在数据写入阶段t1为高电平使得第二薄膜晶体管T2与第三薄膜晶体管T3导通,数据电压Vdata与参考电压Vref接入电路,扫描信号Scan在发光阶段t2为低电平使得第二薄膜晶体管T2与第三薄膜晶体管T3关断,电容Cs存储的电荷使得有机发光二极管D0发光。
具体的,在显示模式的数据写入阶段t1:所述扫描信号Scan为高电平使得第二薄膜晶体管T2与第三薄膜晶体管T3导通,第二开关管S2、第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下导通,第一节点g通过第二薄膜晶体管T2与第五开关管S5写入数据电压Vdata(获取补偿数据后则写入补偿后的数据电压),第二节点s通过第三薄膜晶体管T3与第三开关管S3写入参考电压Vref,此阶段OLED不发光。在显示模式的发光阶段t2:所述扫描信号Scan为低电平使得第二薄膜晶体管T2与第三薄膜晶体管T3关断,电容Cs存储的电荷为数据电压Vdata与参考电压Vref的差值(即Cs存储的电荷与上一阶段保持一致),有机发光二极管D0发光。
在感测模式下,第五开关管S5、第三开关管S3先在相应的电平控制信号SW控制下导通,然后第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下关断,同时第一开关管S1、第六开关管S6、第四开关管S4在相应的电平控制信号SW控制下导通。感测模式分为电位初始化阶段t1与感测阶段t2,所述扫描信号Scan始终为高电平,在电位初始化阶段t1第二薄膜晶体管T2与第三薄膜晶体管T3导通,初始化电压Vini与参考电压Vref接入电路,在感测阶段t2数据电流Idata接入电路,通过输入不同数据电流Idata使得第一模数转换器ADC1与第二模数转换器ADC2感测到第一薄膜晶体管T1的阈值电压Vth以及本征导电因子值k。根据感测的驱动薄膜晶体管(即第一薄膜晶体管T1)的阈值电压Vth以及本征导电因子值k,即可在显示模式下进行相应的数据补偿。
具体的,在感测模式的电位初始化阶段t1:所述扫描信号Scan为高电平使得第二薄膜晶体管T2与第三薄膜晶体管T3导通,第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下导通,第一节点g通过第二薄膜晶体管T2与第五开关管S5写入初始化电压Vini,第二节点s通过第三薄膜晶体管T3与第三开关管S3写入参考电压Vref。在感测模式的感测阶段t2:所述扫描信号Scan为高电平,第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下关断,同时第一开关管S1、第六开关管S6、第四开关管S4在相应的电平控制信号SW控制下导通,输入不同数据电流Idata通过第一薄膜晶体管T1对第二节点s充放电,电流稳定后第一模数转换器ADC1通过第二薄膜晶体管T2与第六开关管S6感测第一节点g电位,第二模数转换器ADC2通过第三薄膜晶体管T3与第四开关管S4感测第二节点s电位,从而感测到第一薄膜晶体管T1的阈值电压Vth以及本征导电因子值k。
优选的,在感测模式的感测阶段t2:输入第一数据电流Idata1通过第一薄膜晶体管T1对第二节点s充放电,电流稳定后,第一模数转换器ADC1通过第二薄膜晶体管T2与第六开关管S6感测第一节点g电位,第二模数转换器ADC2通过第三薄膜晶体管T3与第四开关管S4感测第二节点s电位,从而获取第一薄膜晶体管的栅极与源极之间的第一电压差Vgs1。输入第二数据电流Idata2通过第一薄膜晶体管T1对第二节点s充放电,电流稳定后,第一模数转换器ADC1通过第二薄膜晶体管T2与第六开关管S6感测第一节点g电位,第二模数转换器ADC2通过第三薄膜晶体管T3与第四开关管S4感测第二节点s电位,从而获取第一薄膜晶体管的栅极与源极之间的第二电压差Vgs2。联立方程组Idata1=k(Vgs1-Vth)和Idata2=k(Vgs2-Vth),获取第一薄膜晶体管T1的阈值电压Vth以及本征导电因子值k。其中,Idata1为第一数据电流、Vgs1为所述第一电压差、Idata2为第二数据电流、Vgs2为所述第二电压差、Vth为第一薄膜晶体管的阈值电压、k为本征导电因子值。
也即,S1打开后,数据电流Idata通过T1对s点充放电,稳定后流经OLED的电流为Idata。此时ADC1通过T2、S6感测g点电位,ADC2通过T3、S4感测s点电位。改变Idata的值再次感测g、s点电位,并联立方程组I1=k(Vgs1-Vth)和I2=k(Vgs2-Vth),即可获取k和Vth值。根据k和Vth值,即可在显示模式下进行相应的数据补偿。
本发明所述的OLED像素驱动电路,采用3T1C结构,通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段;同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k,在显示模式下进行相应的数据补偿。即,在显示模式下,驱动薄膜晶体管的阈值电压Vth以及OLED老化后本征导电因子值k的漂移均可以得到补偿,能够提高显示的均匀性,提高发光效率。
在本实施例中,第一至第六开关管S1-S6均为开关元件。第一开关管S1与第二开关管S2的控制端用于分别接收相应的电平控制信号SW1、SW2,第一开关管S1与第二开关管S2的第一接入点短接后电性连接第一薄膜晶体管T1的漏极,第一开关管S1的第二接入点接入数据电流Idata,第二开关管S2的第二接入点接入电源电压OVDD。第三开关管S3与第四开关管S4的控制端用于分别接收相应的电平控制信号SW3、SW4,第三开关管S3与第四开关管S4的第一接入点短接后电性连接第三薄膜晶体管T3的漏极,第三开关管S3的第二接入点接入参考电压Vref,第四开关管S4的第二接入点接入第二模数转换器ADC2。第五开关管S5与第六开关管S6的控制端用于分别接收相应的电平控制信号SW5、SW6,第五开关管S5与第六开关管S6的第一接入点短接后电性连接第二薄膜晶体管T2的漏极,第五开关管S5的第二接入点在显示模式下接入数据电压Vdata、在感测模式下接入初始化电压Vini,第六开关管S6的第二接入点接入第一模数转换器ADC1。
进一步,在显示模式的数据写入阶段t1:所述扫描信号Scan为高电平,第一、第四、第六开关管S1、S4、S6的控制端接收低电平(即SW1、SW4、SW6为低电平信号),第二、第三、第五开关管S2、S3、S5的控制端接收高电平(即SW2、SW3、SW5为高电平信号)。在显示模式的发光阶段t2:所述扫描信号Scan为低电平,第一、第四、第六开关管S1、S4、S6的控制端接收低电平,第二、第三、第五开关管S2、S3、S5的控制端接收高电平。也即,在显示模式下,第二、第三、第五开关管S2、S3、S5始终导通,第一、第四、第六开关管S1、S4、S6始终关断。
进一步,在感测模式的电位初始化阶段t1:所述扫描信号Scan为高电平,第一、第二、第四、第六开关管S1、S2、S4、S6的控制端接收低电平,第三、第五开关管S3、S5的控制端接收高电平。在感测模式的感测阶段t2:所述扫描信号Scan为高电平,第一、第四、第六开关管S1、S4、S6的控制端接收高电平,第二、第三、第五开关管S2、S3、S5的控制端接收低电平。
参考图6-8,其中图6为本发明所述的OLED像素驱动电路第二实施例所示架构图,图7为图6所述的OLED像素驱动电路显示模式时序图,图8为图6所述的OLED像素驱动电路感测模式时序图。与图3所示实施例的不同之处在于,本实施例中第一至第六开关管S1-S6均为MOS管。第一开关管S1与第二开关管S2的栅极短接用于接收相应的电平控制信号SW1/2,第一开关管S1与第二开关管S2的源极短接后电性连接第一薄膜晶体管T1的漏极,第一开关管S1的源极接入数据电流Idata,第二开关管S2的源极接入电源电压OVDD。第三开关管S3与第四开关管S4的栅极短接用于接收相应的电平控制信号SW3/4,第三开关管S3与第四开关管S4的源极短接后电性连接第三薄膜晶体管T3的漏极,第三开关管S3的漏极接入参考电压Vref,第四开关管S4的漏极接入第二模数转换器ADC2。第五开关管S5与第六开关管S6的栅极短接用于接收相应的电平控制信号SW5/6,第五开关管S5与第六开关管S6的源极短接后电性连接第二薄膜晶体管T2的漏极,第五开关管S5的漏极在显示模式下接入数据电压Vdata、在感测模式下接入初始化电压Vini,第六开关管S6的漏极接入第一模数转换器ADC1。
进一步,在显示模式的数据写入阶段t1:所述扫描信号Scan为高电平,第一、第二开关管S1、S2的栅极接收低电平(即SW1/2为低电平信号),第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收高电平(即SW3/4、SW5/6均为高电平信号)。在显示模式的发光阶段t2:所述扫描信号Scan为低电平,第一、第二开关管S1、S2的栅极接收低电平,第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收高电平。也即,在显示模式下,第二、第三、第五开关管S2、S3、S5始终导通,第一、第四、第六开关管S1、S4、S6始终关断。
进一步,在感测模式的电位初始化阶段t1:所述扫描信号Scan为高电平,第一、第二开关管S1、S2的栅极接收低电平,第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收高电平;在感测模式的感测阶段t2:所述扫描信号Scan为高电平,第一、第二开关管S1、S2的栅极接收高电平,第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收低电平。
本发明还提供一种OLED显示装置,包括上述的OLED像素驱动电路,此处不再对该OLED像素驱动电路的结构及功能进行重复性描述。
本发明提供的OLED像素驱动电路及OLED显示装置,采用3T1C结构,通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段;同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k,在显示模式下进行相应的数据补偿,能够提高显示的均匀性,提高发光效率。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (9)
1.一种OLED像素驱动电路,所述驱动电路工作状态包括显示模式和感测模式,其特征在于,所述驱动电路包括:
第一薄膜晶体管,栅极电性连接第一节点,源极电性连接第二节点,漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压;
第二薄膜晶体管,栅极接入扫描信号,源极电性连接所述第一节点,漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器;
第三薄膜晶体管,栅极接入扫描信号,源极电性连接所述第二节点,漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器;
电容,一端电性连接所述第一节点,另一端电性连接所述第二节点;
有机发光二极管,阳极电性连接所述第二节点,阴极接入公共接地电压;
在显示模式下,所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通;显示模式分为数据写入阶段与发光阶段,所述扫描信号在数据写入阶段为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通,所述数据电压与所述参考电压接入电路,所述扫描信号在发光阶段为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断,所述电容存储的电荷使得所述有机发光二极管发光;
在感测模式下,所述第五开关管、第三开关管先在相应的电平控制信号控制下导通,然后所述第五开关管、第三开关管在相应的电平控制信号控制下关断,同时所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通;感测模式分为电平初始化阶段与感测阶段,所述扫描信号始终为高电平,在电位初始化阶段所述第二薄膜晶体管与所述第三薄膜晶体管导通,所述初始化电压与所述参考电压接入电路,在感测阶段所述数据电流接入电路,通过输入不同数据电流使得所述第一模数转换器与所述第二模数转换器感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
2.如权利要求1所述的驱动电路,其特征在于,
在显示模式的数据写入阶段:所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通,所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通,所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述数据电压,所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压;在显示模式的发光阶段:所述扫描信号为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断,所述电容存储的电荷为所述数据电压与所述参考电压的差值,所述有机发光二极管发光;
在感测模式的电位初始化阶段:所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通,所述第五开关管、第三开关管在相应的电平控制信号控制下导通,所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述初始化电压,所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压;在感测模式的感测阶段:所述扫描信号为高电平,所述第五开关管、第三开关管在相应的电平控制信号控制下关断,所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通,输入不同数据电流通过所述第一薄膜晶体管对所述第二节点充放电,电流稳定后所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位,所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位,从而感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
3.如权利要求2所述的驱动电路,其特征在于,在感测模式的感测阶段:输入第一数据电流通过所述第一薄膜晶体管对所述第二节点充放电,电流稳定后,所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位,所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位,从而获取所述第一薄膜晶体管的栅极与源极之间的第一电压差;输入第二数据电流通过所述第一薄膜晶体管对所述第二节点充放电,电流稳定后,所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测第一节点电位,所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位,从而获取所述第一薄膜晶体管的栅极与源极之间的第二电压差;联立方程组Idata1=k(Vgs1-Vth)和Idata2=k(Vgs2-Vth),获取所述第一薄膜晶体管的阈值电压以及本征导电因子值;其中,Idata1为所述第一数据电流、Vgs1为所述第一电压差、Idata2为所述第二数据电流、Vgs2为所述第二电压差、Vth为所述第一薄膜晶体管的阈值电压、k为本征导电因子值。
4.如权利要求1所述的驱动电路,其特征在于,第一至第六开关管均为开关元件;
所述第一开关管与所述第二开关管的控制端用于分别接收相应的电平控制信号,所述第一开关管与所述第二开关管的第一接入点短接后电性连接所述第一薄膜晶体管的漏极,所述第一开关管的第二接入点接入所述数据电流,所述第二开关管的第二接入点接入所述电源电压;所述第三开关管与所述第四开关管的控制端用于分别接收相应的电平控制信号,所述第三开关管与所述第四开关管的第一接入点短接后电性连接所述第三薄膜晶体管的漏极,所述第三开关管的第二接入点接入所述参考电压,所述第四开关管的第二接入点接入所述第二模数转换器;
所述第五开关管与所述第六开关管的控制端用于分别接收相应的电平控制信号,所述第五开关管与所述第六开关管的第一接入点短接后电性连接所述第二薄膜晶体管的漏极,所述第五开关管的第二接入点在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压,所述第六开关管的第二接入点接入所述第一模数转换器。
5.如权利要求4所述的驱动电路,其特征在于,在显示模式的数据写入阶段:所述扫描信号为高电平,第一、第四、第六开关管的控制端接收低电平,第二、第三、第五开关管的控制端接收高电平;在显示模式的发光阶段:所述扫描信号为低电平,第一、第四、第六开关管的控制端接收低电平,第二、第三、第五开关管的控制端接收高电平;
在感测模式的电平初始化阶段:所述扫描信号为高电平,第一、第二、第四、第六开关管的控制端接收低电平,第三、第五开关管的控制端接收高电平;在感测模式的感测阶段:所述扫描信号为高电平,第一、第四、第六开关管的控制端接收高电平,第二、第三、第五开关管的控制端接收低电平。
6.如权利要求1所述的驱动电路,其特征在于,第一至第六开关管均为MOS管;
所述第一开关管与所述第二开关管的栅极短接用于接收相应的电平控制信号,所述第一开关管与所述第二开关管的源极短接后电性连接所述第一薄膜晶体管的漏极,所述第一开关管的源极接入所述数据电流,所述第二开关管的源极接入所述电源电压;
所述第三开关管与所述第四开关管的栅极短接用于接收相应的电平控制信号,所述第三开关管与所述第四开关管的源极短接后电性连接所述第三薄膜晶体管的漏极,所述第三开关管的漏极接入所述参考电压,所述第四开关管的漏极接入所述第二模数转换器;
所述第五开关管与所述第六开关管的栅极短接用于接收相应的电平控制信号,所述第五开关管与所述第六开关管的源极短接后电性连接所述第二薄膜晶体管的漏极,所述第五开关管的漏极在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压,所述第六开关管的漏极接入所述第一模数转换器。
7.如权利要求6所述的驱动电路,其特征在于,在显示模式的数据写入阶段:所述扫描信号为高电平,第一、第二开关管的栅极接收低电平,第三、第四、第五、第六开关管的栅极接收高电平;在显示模式的发光阶段:所述扫描信号为低电平,第一、第二开关管的栅极接收低电平,第三、第四、第五、第六开关管的栅极接收高电平;
在感测模式的电位初始化阶段:所述扫描信号为高电平,第一、第二开关管的栅极接收低电平,第三、第四、第五、第六开关管的栅极接收高电平;在感测模式的感测阶段:所述扫描信号为高电平,第一、第二开关管的栅极接收高电平,第三、第四、第五、第六开关管的栅极接收低电平。
8.如权利要求1所述的驱动电路,其特征在于,第一至第六开关管、所述第一模数转换器以及所述第二模数转换器均设置在驱动IC内。
9.一种OLED显示装置,其特征在于,包括权利要求1-8任意一项所述的OLED像素驱动电路。
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US10685602B2 (en) | 2020-06-16 |
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