WO2021023302A1 - 一种像素电路及其驱动方法、显示装置 - Google Patents

一种像素电路及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2021023302A1
WO2021023302A1 PCT/CN2020/107835 CN2020107835W WO2021023302A1 WO 2021023302 A1 WO2021023302 A1 WO 2021023302A1 CN 2020107835 W CN2020107835 W CN 2020107835W WO 2021023302 A1 WO2021023302 A1 WO 2021023302A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
terminal
signal
control
electrically connected
Prior art date
Application number
PCT/CN2020/107835
Other languages
English (en)
French (fr)
Inventor
袁志东
冯雪欢
李永谦
袁粲
李蒙
韩东旭
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/294,676 priority Critical patent/US11335264B2/en
Publication of WO2021023302A1 publication Critical patent/WO2021023302A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to but not limited to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device.
  • OLED displays are one of the hot spots in the field of display research today.
  • OLED displays have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed.
  • Each pixel in the OLED display includes a pixel circuit, and the pixel circuit includes a driving transistor to output a driving current to the OLED. Due to the limitation of the manufacturing process of the driving transistor, the parameters of different driving transistors are different, so that the driving current flowing through the OLED is different. In order to ensure the display effect, the OLED display compensates the pixel circuit.
  • the present disclosure provides a pixel circuit configured to drive a light-emitting element, including: a node control sub-circuit, a driving sub-circuit, a storage sub-circuit, and a reading sub-circuit;
  • the node control sub-circuit is electrically connected to the first scan terminal, the first node, the second node, the data signal terminal and the control signal terminal, and is configured to provide the data signal terminal to the first node under the control of the first scan terminal.
  • Signal which provides the signal of the control signal terminal to the second node;
  • the driving sub-circuit is electrically connected to the first node, the first power terminal and the second node, respectively, and is configured to provide a driving current to the second node under the control of the first node and the second node;
  • the storage sub-circuit is electrically connected to the first node and the second node, and is configured to store the charge between the first node and the second node;
  • the reading sub-circuit is electrically connected to the second scan terminal, the second node, and the control signal terminal, and is configured to provide the control signal terminal signal to the second node or to the control signal terminal under the control of the second scan terminal The signal of the second node;
  • the light-emitting elements are electrically connected to the second node and the second power terminal respectively.
  • the node control sub-circuit includes: a first node control sub-circuit and a second node control sub-circuit;
  • the first node control sub-circuit is electrically connected to the first scan terminal, the data signal terminal and the first node respectively, and is configured to provide a signal of the data signal terminal to the first node under the control of the first scan terminal;
  • the second node control sub-circuit is electrically connected to the first scan terminal, the second node and the control signal terminal, respectively, and is configured to provide the control signal terminal signal to the second node under the control of the first scan terminal.
  • the first node control sub-circuit includes: a first switch transistor
  • the control electrode of the first switch transistor is electrically connected to the first scan terminal, the first electrode of the first switch transistor is electrically connected to the data signal terminal, and the second electrode of the first switch transistor is electrically connected to the first node.
  • the second node control sub-circuit includes: a second switch transistor
  • the control electrode of the second switch transistor is electrically connected to the first scan terminal, the first electrode of the second switch transistor is electrically connected to the control signal terminal, and the second electrode of the second switch transistor is electrically connected to the second node.
  • the driving sub-circuit includes: a driving transistor
  • the control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first power terminal, and the second electrode of the driving transistor is electrically connected to the second node.
  • the storage sub-circuit includes: a storage capacitor
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the second node.
  • the reading sub-circuit includes: a third switch transistor
  • the control electrode of the third switch transistor is electrically connected to the second scanning terminal, the first electrode of the third switch transistor is electrically connected to the control signal terminal, and the second electrode of the third switch transistor is electrically connected to the second node.
  • the node control sub-circuit includes: a first switching transistor and a second switching transistor
  • the storage sub-circuit includes: a storage capacitor
  • the reading sub-circuit includes: a third switching transistor.
  • the driving sub-circuit includes: a driving transistor;
  • the control electrode of the first switch transistor is electrically connected to the first scan terminal, the first electrode of the first switch transistor is electrically connected to the data signal terminal, and the second electrode of the first switch transistor is electrically connected to the first node;
  • the control electrode of the second switch transistor is electrically connected to the first scan terminal, the first electrode of the second switch transistor is electrically connected to the control signal terminal, and the second electrode of the second switch transistor is electrically connected to the second node;
  • the control electrode of the third switch transistor is electrically connected to the second scan terminal, the first electrode of the third switch transistor is electrically connected to the control signal terminal, and the second electrode of the third switch transistor is electrically connected to the second node;
  • the control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first power terminal, and the second electrode of the driving transistor is electrically connected to the second node;
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the second node.
  • the signal at the second scan terminal when the signal of the first scan terminal is at an effective level, the signal at the second scan terminal is at an inactive level, and when the signal at the second scan terminal is at an effective level, the first The signal at the scan end is at an invalid level.
  • the present disclosure also provides a display device, including: P rows and Q columns of pixel circuits, where P and Q are positive integers greater than 1;
  • the pixel circuit is the aforementioned pixel circuit.
  • the second scanning terminal of the pixel circuit in the i-th row is electrically connected to the first scanning terminal of the pixel circuit in the i+1-th row, and 1 ⁇ i ⁇ P-1.
  • the display device further includes: a gate driving circuit
  • the gate driving circuit includes: a P-stage shift register, the output terminal of the i-th stage shift register is electrically connected to the first scanning terminal of the i-th row of pixel circuits, 1 ⁇ i ⁇ P.
  • the present disclosure also provides a method for driving a pixel circuit, which is applied to the above-mentioned pixel circuit.
  • the driving timing of the pixel circuit includes: a scanning phase and a sensing phase.
  • the methods include:
  • the node control sub-circuit Under the control of the first scan terminal, the node control sub-circuit provides the signal of the data signal terminal to the first node and the signal of the control signal terminal to the second node, and the storage sub-circuit stores the charge between the first node and the second node;
  • the driving sub-circuit Under the control of the first node and the second node, the driving sub-circuit provides a driving current to the second node;
  • the reading sub-circuit Under the control of the second scanning terminal, the reading sub-circuit provides the signal of the second node to the control signal terminal;
  • the reading sub-circuit Under the control of the second scanning terminal, the reading sub-circuit provides the signal of the control signal terminal to the second node.
  • the method includes:
  • the node control sub-circuit Under the control of the first scan terminal, the node control sub-circuit provides the signal of the data signal terminal to the first node and the signal of the control signal terminal to the second node, and the storage sub-circuit stores the charge between the first node and the second node;
  • the driving sub-circuit Under the control of the first node and the second node, the driving sub-circuit provides a driving current to the second node.
  • the signal at the second scan terminal when the signal of the first scan terminal is at an effective level, the signal at the second scan terminal is at an inactive level, and when the signal at the second scan terminal is at an effective level, the first The signal at the scanning end is at an invalid level;
  • the signal of the control signal terminal is a reference signal.
  • the voltage value of the reference signal is smaller than the voltage value of the signal at the second power terminal.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure
  • Fig. 2 is a schematic structural diagram of a pixel circuit provided by an exemplary embodiment
  • Fig. 3 is an equivalent circuit diagram of a first node control sub-circuit provided by an exemplary embodiment
  • FIG. 4 is an equivalent circuit diagram of a second node control sub-circuit provided by an exemplary embodiment
  • Fig. 5 is an equivalent circuit diagram of a driving sub-circuit provided by an exemplary embodiment
  • Fig. 6 is an equivalent circuit diagram of a storage sub-circuit provided by an exemplary embodiment
  • FIG. 7 is an equivalent circuit diagram of a reading sub-circuit provided by an embodiment of the disclosure.
  • FIG. 8 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment
  • FIG. 9 is a timing diagram of a pixel circuit in a scanning phase according to an exemplary embodiment
  • FIG. 10 is a working state diagram of a pixel circuit provided by an exemplary embodiment in a scanning phase
  • FIG. 11 is a timing diagram of the pixel circuit in the Nth row and the N+1th row in the sensing phase according to an exemplary embodiment
  • 12A is a working state diagram of the pixel circuit of the Nth row in the first stage provided by an exemplary embodiment
  • FIG. 12B is a working state diagram of the pixel circuit of the N+1th row in the first stage according to an exemplary embodiment
  • FIG. 13A is a working state diagram of the pixel circuit of the Nth row in the second stage provided by an exemplary embodiment
  • FIG. 13B is a working state diagram of the pixel circuit of the N+1th row in the second stage according to an exemplary embodiment
  • FIG. 14A is a working state diagram of the pixel circuit of the Nth row in the third stage according to an exemplary embodiment
  • FIG. 14B is a working state diagram of the pixel circuit of the N+1th row in the third stage provided by an exemplary embodiment
  • 15A is a working state diagram of the pixel circuit of the Nth row in the fourth stage according to an exemplary embodiment
  • 15B is a working state diagram of the pixel circuit in the N+1th row provided by an exemplary embodiment in the fourth stage;
  • 16A is a working state diagram of the pixel circuit of the Nth row in the fifth stage provided by an exemplary embodiment
  • 16B is a working state diagram of the pixel circuit in the N+1th row provided by an exemplary embodiment in the fifth stage;
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 18 is a timing diagram of a pixel circuit in a scanning phase and a sensing phase according to an exemplary embodiment.
  • Both the switching transistor and the driving transistor used in the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the thin film transistor used in the present disclosure may be an oxide semiconductor transistor. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchanged. In this disclosure, in order to distinguish the two poles of the switching transistor except the gate, one of the electrodes is called the first pole, and the other is called the second pole.
  • the first pole can be a source or a drain, and the second pole It can be drain or source.
  • each pixel circuit includes: 1 drive transistor DTFT, 2 switch transistors are respectively composed of T1 and T2, and 1 capacitor C.
  • the pixel circuit of the Nth row is connected to the Nth scanning signal terminal SCAN( N), the N+1th scan signal terminal SCAN(N+1), the data signal terminal DATA, the control signal terminal SENSE, the first power terminal VDD and the second power terminal VSS are electrically connected.
  • the display stage of the pixel circuit includes a scanning stage and a sensing stage.
  • the scanning stage is set to write data signals to each row of pixel circuits by controlling each row of pixel circuits to connect to the scanning signal
  • the sensing stage is set to sense a certain row of pixel circuits.
  • All OLEDs emit light during the sensing phase.
  • a certain row of pixel circuits is sensed by controlling the scanning signal connected to the row of pixel circuits and the next row of pixel circuits.
  • the data signals of the row of pixel circuits and the next row of pixel circuits are rewritten.
  • the sensing stage includes: the first stage, the signals of the Nth scan signal terminal SCAN(N) and the N+1th scan signal terminal SCAN(N+1) are effective levels, The two switching transistors T1 and T2 are both turned on. At this time, the data signal of the data signal terminal DATA is not only written to the node of the pixel circuit of the Nth row, but also written to the node of the pixel circuit of the N+1th row.
  • the N+2 scan signal terminal SCAN(N+2) provides an invalid level, and the node in the pixel circuit of the N+1 row is in a floating state.
  • the Nth scan signal terminal SCAN(N) provides an invalid level
  • the N+1th scan signal terminal SCAN(N+1) continuously provides an effective level signal
  • the control signal terminal SENSE reads the Nth pixel The signal of the node of the circuit.
  • the data signal is rewritten to the pixel circuit of the Nth row and the pixel circuit of the N+1th row to ensure the Nth pixel circuit. Row pixels and N+1th row pixels are displayed normally.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure.
  • the pixel circuit provided by the embodiment of the present disclosure is configured to drive a light-emitting element.
  • the pixel circuit includes: a node control sub-circuit, a driving sub-circuit, a storage sub-circuit, and a reading sub-circuit.
  • the node control sub-circuit is electrically connected to the first scan terminal G1, the first node N1, the second node N2, the data signal terminal DATA, and the control signal terminal SENSE, respectively, and is set to transmit to the first scan terminal G1 under the control of the first scan terminal G1.
  • the node N1 provides the signal of the data signal terminal DATA
  • the second node N2 provides the signal of the control signal terminal SENSE.
  • the driving sub-circuit is electrically connected to the first node N1, the first power supply terminal VDD, and the second node N2, and is configured to provide a driving current to the second node N2 under the control of the first node N1 and the second node N2.
  • the storage sub-circuit is electrically connected to the first node N1 and the second node N2 respectively, and is configured to store the charge between the first node N1 and the second node N2.
  • the reading sub-circuit is electrically connected to the second scan terminal G2, the second node N2, and the control signal terminal SENSE, respectively, and is configured to provide the second node N2 with the signal of the control signal terminal SENSE under the control of the second scan terminal G2, Or provide the signal of the second node N2 to the control signal terminal SENSE.
  • the light-emitting elements are electrically connected to the second node N2 and the second power supply terminal VSS, respectively.
  • the light emitting element may be an organic light emitting diode OLED.
  • the anode of the OLED is electrically connected to the second node N2, and the cathode of the OLED is electrically connected to the second power terminal VSS.
  • the signal of the first power supply terminal VDD may continue to be a high-level signal.
  • the voltage value of the signal of the first power supply terminal VDD may be greater than or equal to 5 volts.
  • the signal of the second power supply terminal VSS may continue to be a low level signal.
  • the voltage value of the signal of the second power terminal VSS may be less than the voltage value of the signal of the first power terminal VDD.
  • control signal terminal SENSE can provide a signal, and can also read the signal of the second node N2.
  • the signal read by the control signal terminal SENSE is set to obtain the parameters of the transistor in the driving sub-circuit, so as to externally compensate the data signal terminal DATA, which can reduce the difference in the driving current flowing to the light emitting element.
  • the signal of the control signal terminal SENSE is a reference signal.
  • the voltage value of the reference signal is smaller than the voltage value of the signal at the second power terminal VSS.
  • control signal terminals SENSE connected to different pixel circuits are the same signal terminal.
  • the pixel circuit provided by the embodiment of the present disclosure is configured to drive the light-emitting element.
  • the pixel circuit includes: a node control sub-circuit, a driving sub-circuit, a storage sub-circuit, and a reading sub-circuit;
  • the node control sub-circuit is connected to the first scanning terminal and the first The node, the second node, the data signal terminal, and the control signal terminal are electrically connected, and are arranged to provide the first node with the signal of the data signal terminal and the second node with the signal of the control signal terminal under the control of the first scanning terminal;
  • the driving sub-circuit Are respectively electrically connected to the first node, the first power terminal and the second node, and are configured to provide a driving current to the second node under the control of the first node and the second node;
  • the storage sub-circuit is respectively connected to the first node and the second node The two nodes are electrically connected and set to store the charge between the first node and the second node;
  • the node control sub-circuit provided by the embodiment of the present disclosure provides the signal of the control signal terminal to the second node through the first scanning terminal, which can ensure that the data signal of the next row of pixel circuits is normally written after the pixel circuit of a certain row is sensed in the sensing phase, and ensures that The display is normal, and the display effect is improved.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an exemplary embodiment.
  • the node control sub-circuit in the pixel circuit provided by the embodiment of the present disclosure includes: a first node control sub-circuit and a second node control sub-circuit.
  • the first node control sub-circuit is electrically connected to the first scan terminal G1, the data signal terminal DATA and the first node N1, and is configured to provide the data signal terminal DATA to the first node N1 under the control of the first scan terminal G1 signal.
  • the second node control sub-circuit is electrically connected to the first scan terminal G1, the second node N2, and the control signal terminal SENSE, and is configured to provide the control signal terminal SENSE to the second node N2 under the control of the first scan terminal G1 signal.
  • the first node control sub-circuit may control the signal of the first node N1.
  • the second node control sub-circuit can control the signal of the second node N2.
  • Fig. 3 is an equivalent circuit diagram of a first node control sub-circuit provided by an exemplary embodiment.
  • the first node control sub-circuit provided by an exemplary embodiment includes: a first switch transistor M1.
  • the control electrode of the first switch transistor M1 is electrically connected to the first scan terminal G1, the first electrode of the first switch transistor M1 is electrically connected to the data signal terminal DATA, and the second electrode of the first switch transistor M1 is electrically connected to the first node N1 .
  • FIG. 3 An exemplary structure of the first node control sub-circuit is shown in FIG. 3.
  • the implementation of the first node control sub-circuit is not limited to this.
  • Fig. 4 is an equivalent circuit diagram of a second node control sub-circuit provided by an exemplary embodiment.
  • the second node control sub-circuit provided by an exemplary embodiment includes: a second switch transistor M2.
  • the control electrode of the second switch transistor M2 is electrically connected to the first scan terminal G1, the first electrode of the second switch transistor M2 is electrically connected to the control signal terminal SENSE, and the second electrode of the second switch transistor M2 is electrically connected to the second node N2 .
  • FIG. 4 An exemplary structure of the second node control sub-circuit is shown in FIG. 4.
  • the implementation of the second node control sub-circuit is not limited to this.
  • Fig. 5 is an equivalent circuit diagram of a driving sub-circuit provided by an exemplary embodiment. As shown in FIG. 5, the driving sub-circuit provided by an exemplary embodiment includes a driving transistor DTFT.
  • the control electrode of the driving transistor DTFT is electrically connected to the first node N1, the first electrode of the driving transistor DTFT is electrically connected to the first power supply terminal VDD, and the second electrode of the driving transistor DTFT is electrically connected to the second node N2.
  • FIG. 5 An exemplary structure of the driving sub-circuit is shown in FIG. 5.
  • the implementation of the driver sub-circuit is not limited to this.
  • FIG. 6 is an equivalent circuit diagram of a storage sub-circuit provided by an exemplary embodiment. As shown in FIG. 6, the storage sub-circuit provided by an exemplary embodiment includes a storage capacitor C.
  • the first end of the storage capacitor C is electrically connected to the first node N1, and the second end of the storage capacitor C is electrically connected to the second node N2.
  • FIG. 6 An exemplary structure of the storage sub-circuit is shown in FIG. 6. The implementation of the storage sub-circuit is not limited to this.
  • FIG. 7 is an equivalent circuit diagram of a reading sub-circuit provided by an embodiment of the disclosure.
  • the reading sub-circuit provided by an exemplary embodiment includes: a third switch transistor M3.
  • the control electrode of the third switch transistor M3 is electrically connected to the second scan terminal G2, the first electrode of the third switch transistor M3 is electrically connected to the control signal terminal SENSE, and the second electrode of the third switch transistor M3 is electrically connected to the second node N2 .
  • FIG. 7 An exemplary structure of the reading sub-circuit is shown in FIG. 7. The implementation of the reading sub-circuit is not limited to this.
  • FIG. 8 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment.
  • the node control sub-circuit includes: a first switching transistor M1 and a second switching transistor M2, the storage sub-circuit includes: a storage capacitor C, and the reading sub-circuit includes : The third switching transistor M3, the driving sub-circuit includes: the driving transistor DTFT.
  • the control electrode of the first switch transistor M1 is electrically connected to the first scan terminal G1, the first electrode of the first switch transistor M1 is electrically connected to the data signal terminal DATA, and the second electrode of the first switch transistor M1 is electrically connected to the first node N1 .
  • the control electrode of the second switch transistor M2 is electrically connected to the first scan terminal G1, the first electrode of the second switch transistor M2 is electrically connected to the control signal terminal SENSE, and the second electrode of the second switch transistor M2 is electrically connected to the second node N2 .
  • the control electrode of the third switch transistor M3 is electrically connected to the second scan terminal G2, the first electrode of the third switch transistor M3 is electrically connected to the control signal terminal SENSE, and the second electrode of the third switch transistor M3 is electrically connected to the second node N2 .
  • the control electrode of the driving transistor DTFT is electrically connected to the first node N1, the first electrode of the driving transistor DTFT is electrically connected to the first power supply terminal VDD, and the second electrode of the driving transistor DTFT is electrically connected to the second node N2.
  • the first end of the storage capacitor C is electrically connected to the first node N1, and the second end of the storage capacitor C is electrically connected to the second node N2.
  • the first scanning terminal G1 and the second scanning terminal G2 do not provide valid level signals at the same time.
  • the signal of the first scanning terminal G1 is at an active level
  • the signal of the second scanning terminal G2 is at an inactive level
  • the signal of the first scanning terminal G1 is at an inactive level.
  • the signal at the second scanning terminal G2 when the signal of the first scanning terminal G1 is at an inactive level, the signal at the second scanning terminal G2 will also be at an inactive level.
  • the signal at the second scanning terminal G2 when the signal at the second scanning terminal G2 is at an inactive level, the first The signal of a scanning terminal G1 will also be at an invalid level.
  • the effective level refers to the level at which the transistor can be turned on, and the invalid level refers to the level at which the transistor can be turned off.
  • the transistor is a P-type transistor, the effective level is low, and the ineffective level is high.
  • the transistor is an N-type transistor, the effective level is high and the ineffective level is low.
  • the driving transistor DTFT, the first switching transistor M1, the second switching transistor M2, and the third switching transistor M3 may be N-type thin film transistors, or may be P-type thin film transistors.
  • the transistor types of the driving transistor DTFT, the first switching transistor M1, the second switching transistor M2 and the third switching transistor M3 are the same, the process flow can be unified, the process process of the OLED display can be reduced, and the product yield of the OLED display can be improved. .
  • FIG. 9 is a timing diagram of a pixel circuit provided by an exemplary embodiment in the scanning phase;
  • FIG. 10 is a working state diagram of a pixel circuit provided by an exemplary embodiment in the scanning phase;
  • FIG. 11 is an exemplary embodiment The timing diagram of the pixel circuit in the Nth row and the N+1 row provided in the sensing phase;
  • FIG. 12A is a working state diagram of the pixel circuit in the Nth row provided by an exemplary embodiment in the first phase;
  • FIG. 12B is a The working state diagram of the pixel circuit in the N+1 row provided by an exemplary embodiment in the first stage;
  • FIG. 13A is a working state diagram of the pixel circuit in the N row provided by an exemplary embodiment in the second stage;
  • FIG. 13B is An exemplary embodiment provides a working state diagram of the N+1th row pixel circuit in the second stage;
  • FIG. 14A is a working state diagram of the Nth row pixel circuit provided by an exemplary embodiment in the third stage;
  • 14B is a working state diagram of the pixel circuit in the N+1th row provided by an exemplary embodiment in the third stage;
  • FIG. 15A is a working state diagram of the pixel circuit in the Nth row provided by an exemplary embodiment in the fourth stage 15B is a diagram of the working state of the pixel circuit in the N+1 row provided by an exemplary embodiment in the fourth stage;
  • FIG. 16A is a working state diagram of the pixel circuit in the Nth row provided by an exemplary embodiment in the fifth stage State diagram;
  • FIG. 16B is a working state diagram of the pixel circuit in the N+1th row provided by an exemplary embodiment in the fifth stage. As shown in FIGS.
  • the pixel circuit involved in an exemplary embodiment includes: 3 switch transistors (M1 to M3), 1 drive transistor (DTFT), 1 capacitor unit (C), 6 Input terminals (DATA, G1, G2, SENSE, VDD, and VSS), where Gi(j) is the i-th scanning terminal of the pixel circuit of the j-th row.
  • the first power terminal VDD continuously provides a high level signal.
  • the second power terminal VSS continuously provides a low-level signal.
  • the signal input from the control signal terminal SENSE is a reference signal, and the voltage value of the reference signal is smaller than the voltage value of the signal at the second power terminal VSS.
  • the working process of the pixel circuit includes: as shown in FIGS. 9 and 10, the input signal of the first scanning terminal G1 is at a high level, the first switching transistor M1 is turned on, and the A node N1 provides the signal input from the data signal terminal DATA.
  • V n is the data signal required by the pixel in the scanning phase.
  • the second switch transistor M2 is turned on to provide the signal input from the control signal terminal SENSE to the second node N2.
  • the signal input from the control signal terminal SENSE is the reference signal, and the voltage value of the reference signal is V ref ,
  • the storage capacitor C stores the charge between the first node N1 and the second node N2. Since V n -V ref >V th , V th is the threshold voltage of the driving transistor DTFT. At this time, the driving transistor DTFT is turned on to provide a driving current to the OLED.
  • the input signal of the second scanning terminal G2 is low, and the control signal terminal SENSE does not read the signal of the second node N2.
  • the signal input from the data signal terminal DATA is a data signal after external compensation.
  • the working process of each row of pixel circuits is the same.
  • the sensing stage includes: the first stage S1, the second stage S2, the third stage S3, the fourth stage S4, and the fifth stage S5.
  • the working process of the pixel circuit in the Nth row and the N+1th row includes:
  • the input signal of the first scanning terminal G1(N) is at a high level, and the first switching transistor M1 is turned on to
  • the node N1 provides the signal input by the data signal terminal DATA.
  • the two switch transistors M2 are turned on to provide the signal input from the control signal terminal SENSE to the second node N2.
  • the signal input from the control signal terminal SENSE is the reference signal.
  • the voltage value of the reference signal is V ref and the voltage of the second node N2
  • the storage capacitor C stores the charge between the first node N1 and the second node N2. Since V c -V ref >V th , at this time, the driving transistor DTFT is turned on. At this time, The input signal of the first scanning terminal G1 (N+1) of the pixel circuit in the N+1 row is low, and the pixel circuit in the N+1 row still outputs a driving current under the action of the data signal input in the scanning phase.
  • the voltage value of the signal input from the data signal terminal DATA is V c .
  • the input signal of the first scanning terminal G1(N) is low, the first switching transistor M1 and the second switching transistor M2
  • the driving transistor DTFT is turned off.
  • the input signal of the second scanning terminal G2(N) is at a high level, the third switch transistor M3 is turned on, but the control signal terminal SENSE does not input a signal, and the second node N2 is in a floating state.
  • the input signal of the first scan terminal G1 (N+1) is at a high level, and the first transistor M1 and the second transistor M2 are turned on.
  • the input signal of the second scanning terminal G2(N) continues to be at a high level, and the third switch transistor M3 is continuously turned on to control
  • the signal terminal SENSE reads the signal of the second node N2 to complete the sensing of the pixel circuit of the Nth row.
  • the input signal of the first scan terminal G1 (N+1) is at a high level, and the first transistor M1 and the second transistor M2 are turned on.
  • the input signal of the second scan terminal G2(N) continues to be high, and the third switch transistor M3 is continuously turned on,
  • the second node N2 provides the signal input from the control signal terminal SENSE.
  • the signal input from the control signal terminal SENSE is a reference signal
  • the voltage value of the reference signal is Vref
  • the fifth stage S5 as shown in FIGS. 11, 16A and 16B, in the pixel circuit of the Nth row, the input signal of the second scanning terminal G2(N) is low, the third switching transistor M3 is turned off, and the first scanning terminal The input signal of G1(N) is at a high level, and the first switch transistor M1 is turned on to provide the first node N1 with the signal input from the data signal terminal DATA.
  • the second switch transistor M2 is turned on, and provides the second node N2 with the signal input from the control signal terminal SENSE
  • the signal is a reference signal
  • the voltage value of the reference signal is Vref
  • the data signal is written to the pixel circuit of the Nth row, so that the pixel circuit of the Nth row is output and driven again Current to ensure the display effect.
  • the input signal of the first scan terminal G1(N+1) is low, and no data signal is written to the pixel circuit of the N+1th row.
  • the sequence of the fourth stage S4 and the fifth stage S5 can be interchanged.
  • the pixel circuit provided by an exemplary embodiment controls the signals of the first node and the second node through the first scanning terminal, so that data signals can be rewritten to the pixel circuit, and when the data signals are written , The input signal of the second scanning terminal is low level.
  • the pixel circuit provided by an exemplary embodiment can ensure that the data signal of the next row of pixel circuits is normally written after the pixel circuit of a certain row is sensed in the sensing phase, which ensures normal display and improves the display effect.
  • FIG. 17 is a schematic structural diagram of the display device provided by the embodiment of the disclosure. As shown in FIG. 17, the display device provided by the embodiment of the present disclosure includes: P rows and Q columns pixel circuits.
  • both P and Q are positive integers greater than one.
  • FIG. 18 illustrates a column of pixel circuits as an example. Among them, X(N-1) represents the N-1th row of pixel circuits in a column of pixel circuits, X(N) represents the Nth row of pixel circuits in a column of pixel circuits, and so on.
  • the second scanning terminal G2 of the pixel circuit X(i) in the i-th row and the first scanning terminal G1 of the pixel circuit X(i+1) in the i+1-th row are Electrical connection, 1 ⁇ i ⁇ P-1.
  • FIG. 18 is a timing diagram of a pixel circuit in a scanning phase and a sensing phase according to an exemplary embodiment.
  • G1(i) refers to the first scanning end of the pixel circuit of the i-th row.
  • FIG. 19 is an example of randomly selecting pixel circuits in the N-1th row.
  • the first scanning terminal G1(N-1) of the pixel circuit in the N-1th row and the first scanning terminal G1(N) of the pixel circuit in the Nth row do not continuously provide low-level signals.
  • Other pixel circuits, such as the Nth The first scanning terminal G1 (N+1) of the pixel circuit of the +1 row continuously provides a low-level signal.
  • the pixel circuit is the pixel circuit provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and will not be repeated here.
  • the display device provided by an exemplary embodiment may further include: a gate driving circuit.
  • the gate driving circuit includes a P-stage shift register, and the output terminal of the i-th stage shift register is electrically connected to the first scanning terminal of the i-th row of pixel circuits.
  • the data signal terminals electrically connected to the pixel circuits of the same column are the same signal terminal
  • the control signal terminals electrically connected to the pixel circuits of the same column are the same signal terminal
  • control signals of the first scan terminal and the second scan terminal are both provided by the gate drive circuit, which can reduce the use of signal lines, simplify the wiring of the pixel circuit, realize a narrow frame, and increase the pixel area per unit area. Display of quantity.
  • the embodiment of the present disclosure also provides a method for driving the pixel circuit, which is applied to the pixel circuit.
  • the driving timing of the pixel circuit includes: a scanning phase and a sensing phase.
  • the sensing phase the The driving method of the pixel circuit includes the following steps:
  • Step 100 Under the control of the first scanning terminal, the node control sub-circuit provides the signal of the data signal terminal to the first node and the signal of the control signal terminal to the second node, and the storage sub-circuit stores the data between the first node and the second node. Charge.
  • Step 200 Under the control of the first node and the second node, the driving sub-circuit provides a driving current to the second node.
  • Step 300 Under the control of the second scanning terminal, the reading sub-circuit provides the signal of the second node to the control signal terminal.
  • Step 400 Under the control of the second scan terminal, the reading sub-circuit provides the signal of the control signal terminal to the second node.
  • the pixel circuit is the pixel circuit provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and will not be repeated here.
  • the driving method of the pixel circuit includes: under the control of the first scanning terminal, the node control sub-circuit provides the signal of the data signal terminal to the first node and provides control to the second node
  • the storage sub-circuit stores the charge between the first node and the second node
  • the driving sub-circuit provides a driving current to the second node.
  • the signal at the second scanning terminal when the signal of the first scanning terminal is at an active level, the signal at the second scanning terminal is at an inactive level, and when the signal at the second scanning terminal is at an active level, the signal at the first scanning terminal is at an inactive level .
  • the signal of the first scanning terminal in step S100, is at an effective level, and in steps S200 to S400, the signal of the first scanning terminal is at an inactive level.
  • the signal at the first scan terminal is at an inactive level
  • steps S200 to S400 the signal at the second scan terminal is at an active level.
  • the signal of the control signal terminal is a reference signal.
  • the signal at the control signal terminal is a reference signal.
  • the voltage value of the reference signal is less than the voltage value of the signal of the second power terminal, which can ensure the display effect of the display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路及其驱动方法、显示装置，像素电路设置为驱动发光元件，包括：节点控制子电路设置为在第一扫描端的控制下，向第一节点提供数据信号端的信号，向第二节点提供控制信号端的信号；驱动子电路设置为在第一节点和第二节点的控制下，向第二节点提供驱动电流；存储子电路设置为存储第一节点和第二节点之间的电荷；读取子电路设置为在第二扫描端的控制下，向控制信号端提供第二节点的信号或者向第二节点提供控制信号端的信号；发光元件，分别与第二节点和第二电源端电连接。

Description

一种像素电路及其驱动方法、显示装置
本申请要求于2019年8月8日提交中国专利局、申请号为201910730854.8、发明名称为“一种像素电路及其驱动方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，特别涉及一种像素电路及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)显示器是当今显示器研究领域的热点之一，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快的优点。OLED显示器中每个像素均包括像素电路，像素电路中包括驱动晶体管以向OLED输出驱动电流。由于驱动晶体管的制造工艺的局限性，不同的驱动晶体管的参数存在差异，使得流经OLED的驱动电流不同。为了保证显示效果，OLED显示器对像素电路进行补偿。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种像素电路，设置为驱动发光元件，包括：节点控制子电路、驱动子电路、存储子电路和读取子电路；
所述节点控制子电路，分别与第一扫描端、第一节点、第二节点、数据信号端和控制信号端电连接，设置为在第一扫描端的控制下，向第一节点提供数据信号端的信号，向第二节点提供控制信号端的信号；
所述驱动子电路，分别与第一节点、第一电源端和第二节点电连接，设置为在第一节点和第二节点的控制下，向第二节点提供驱动电流；
所述存储子电路，分别与第一节点和第二节点电连接，设置为存储第一节点和第二节点之间的电荷；
所述读取子电路，分别与第二扫描端、第二节点和控制信号端电连接，设置为在第二扫描端的控制下，向第二节点提供控制信号端的信号，或者向控制信号端提供第二节点的信号；
所述发光元件，分别与第二节点和第二电源端电连接。
在一些可能的实现方式中，所述节点控制子电路包括：第一节点控制子电路和第二节点控制子电路；
所述第一节点控制子电路，分别与第一扫描端、数据信号端和第一节点电连接，设置为在第一扫描端的控制下，向第一节点提供数据信号端的信号；
所述第二节点控制子电路，分别与第一扫描端、第二节点和控制信号端电连接，设置为在第一扫描端的控制下，向第二节点提供控制信号端的信号。
在一些可能的实现方式中，所述第一节点控制子电路包括：第一开关晶体管；
第一开关晶体管的控制极与第一扫描端电连接，第一开关晶体管的第一极与数据信号端电连接，第一开关晶体管的第二极与第一节点电连接。
在一些可能的实现方式中，所述第二节点控制子电路包括：第二开关晶体管；
第二开关晶体管的控制极与第一扫描端电连接，第二开关晶体管的第一极与控制信号端电连接，第二开关晶体管的第二极与第二节点电连接。
在一些可能的实现方式中，所述驱动子电路包括：驱动晶体管；
驱动晶体管的控制极与第一节点电连接，驱动晶体管的第一极与第一电源端电连接，驱动晶体管的第二极与第二节点电连接。
在一些可能的实现方式中，所述存储子电路包括：存储电容；
存储电容的第一端与第一节点电连接，存储电容的第二端与第二节点电连接。
在一些可能的实现方式中，所述读取子电路包括：第三开关晶体管；
第三开关晶体管的控制极与第二扫描端电连接，第三开关晶体管的第一极与控制信号端电连接，第三开关晶体管的第二极与第二节点电连接。
在一些可能的实现方式中，所述节点控制子电路包括：第一开关晶体管和第二开关晶体管，所述存储子电路包括：存储电容，所述读取子电路包括：第三开关晶体管，所述驱动子电路包括：驱动晶体管；
第一开关晶体管的控制极与第一扫描端电连接，第一开关晶体管的第一极与数据信号端电连接，第一开关晶体管的第二极与第一节点电连接；
第二开关晶体管的控制极与第一扫描端电连接，第二开关晶体管的第一极与控制信号端电连接，第二开关晶体管的第二极与第二节点电连接；
第三开关晶体管的控制极与第二扫描端电连接，第三开关晶体管的第一极与控制信号端电连接，第三开关晶体管的第二极与第二节点电连接；
驱动晶体管的控制极与第一节点电连接，驱动晶体管的第一极与第一电源端电连接，驱动晶体管的第二极与第二节点电连接；
存储电容的第一端与第一节点电连接，存储电容的第二端与第二节点电连接。
在一些可能的实现方式中，当所述第一扫描端的信号为有效电平时，所述第二扫描端的信号为无效电平，当所述第二扫描端的信号为有效电平时，所述第一扫描端的信号为无效电平。
第二方面，本公开还提供了一种显示装置，包括：P行Q列像素电路，其中，P，Q为大于1的正整数；
所述像素电路为上述像素电路。
在一些可能的实现方式中，第i行像素电路的第二扫描端与第i+1行像素电路的第一扫描端电连接，1≤i≤P-1。
在一些可能的实现方式中，所述显示装置还包括：栅极驱动电路；
所述栅极驱动电路包括：P级移位寄存器，第i级移位寄存器的输出端与第i行像素电路的第一扫描端电连接，1≤i≤P。
第三方面，本公开还提供了一种像素电路的驱动方法，应用于上述像素 电路中，在驱动显示时，所述像素电路的驱动时序包括：扫描阶段和感应阶段，在感应阶段中，所述方法包括：
在第一扫描端的控制下，节点控制子电路向第一节点提供数据信号端的信号，并向第二节点提供控制信号端的信号，存储子电路存储第一节点和第二节点之间的电荷；
在第一节点和第二节点的控制下，驱动子电路向第二节点提供驱动电流；
在第二扫描端的控制下，读取子电路向控制信号端提供第二节点的信号；
在第二扫描端的控制下，读取子电路向第二节点提供控制信号端的信号。
在一些可能的实现方式中，在扫描阶段中，所述方法包括：
在第一扫描端的控制下，节点控制子电路向第一节点提供数据信号端的信号，并向第二节点提供控制信号端的信号，存储子电路存储第一节点和第二节点之间的电荷；
在第一节点和第二节点的控制下，驱动子电路向第二节点提供驱动电流。
在一些可能的实现方式中，当所述第一扫描端的信号为有效电平时，所述第二扫描端的信号为无效电平，当所述第二扫描端的信号为有效电平时，所述第一扫描端的信号为无效电平；
在读取子电路不向所述控制信号端提供所述第二节点的信号时，所述控制信号端的信号为参考信号。
在一些可能的实现方式中，所述参考信号的电压值小于第二电源端的信号的电压值。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起设置为解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的像素电路的结构示意图；
图2为一种示例性实施例提供的像素电路的结构示意图；
图3为一种示例性实施例提供的第一节点控制子电路的等效电路图；
图4为一种示例性实施例提供的第二节点控制子电路的等效电路图；
图5为一种示例性实施例提供的驱动子电路的等效电路图；
图6为一种示例性实施例提供的存储子电路的等效电路图；
图7为本公开实施例提供的读取子电路的等效电路图；
图8为一种示例性实施例提供的像素电路的等效电路图；
图9为一种示例性实施例提供的像素电路在扫描阶段的时序图；
图10为一种示例性实施例提供的像素电路在扫描阶段的工作状态图；
图11为一种示例性实施例提供的第N行和第N+1行像素电路在感应阶段的时序图；
图12A为一种示例性实施例提供的第N行像素电路在第一阶段的工作状态图；
图12B为一种示例性实施例提供的第N+1行像素电路在第一阶段的工作状态图；
图13A为一种示例性实施例提供的第N行像素电路在第二阶段的工作状态图；
图13B为一种示例性实施例提供的第N+1行像素电路在第二阶段的工作状态图；
图14A为一种示例性实施例提供的第N行像素电路在第三阶段的工作状态图；
图14B为一种示例性实施例提供的第N+1行像素电路在第三阶段的工作状态图；
图15A为一种示例性实施例提供的第N行像素电路在第四阶段的工作状态图；
图15B为一种示例性实施例提供的第N+1行像素电路在第四阶段的工作状态图；
图16A为一种示例性实施例提供的第N行像素电路在第五阶段的工作状态图；
图16B为一种示例性实施例提供的第N+1行像素电路在第五阶段的工作状态图；
图17为本公开实施例提供的显示装置的结构示意图；
图18为一种示例性实施例提供的像素电路在扫描阶段和感应阶段的时序图。
详述
下文中将结合附图对本公开的实施例进行详细说明。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详述中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、 “第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
本公开中采用的开关晶体管和驱动晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。本公开中使用的薄膜晶体管可以是氧化物半导体晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开中，为区分开关晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或者源极。
在一种显示装置中，每个像素电路包括：1个驱动晶体管DTFT，2个开关晶体管分别为T1和T2以及1个电容C组成，第N行像素电路分别与第N个扫描信号端SCAN(N)、第N+1个扫描信号端SCAN(N+1)、数据信号端DATA、控制信号端SENSE、第一电源端VDD和第二电源端VSS电连接。
像素电路的显示阶段包括：扫描阶段和感应阶段，扫描阶段设置为通过控制每一行像素电路连接扫描信号，以向每一行像素电路写入数据信号，感应阶段设置为对某行像素电路进行感应，以对像素电路进行外部补偿。在感应阶段中所有OLED发光。在对某行像素电路进行感应时，通过控制该行像素电路和下一行像素电路所连接的扫描信号以对某行像素电路进行感应。为了保证显示画面的连续性，在感应阶段对某行像素电路进行感应之后，重新写入该行像素电路和下一行像素电路的数据信号。
随机选中第N行像素电路进行感应，感应阶段包括：第一阶段，第N个扫描信号端SCAN(N)和第N+1个扫描信号端SCAN(N+1)的信号为有效电平，使得2个开关晶体管T1和T2均导通，此时，数据信号端DATA的数据信号不仅写入到了第N行像素电路的节点，还写入到了第N+1行像素电路的节点中。第N+2个扫描信号端SCAN(N+2)提供无效电平，第N+1行像素电路中的节点处于浮接状态。第二阶段，第N个扫描信号端SCAN(N) 提供无效电平，第N+1个扫描信号端SCAN(N+1)持续提供有效电平信号，控制信号端SENSE读取第N个像素电路的节点的信号。为了保证显示画面的连续性，在控制信号端SENSE读取第N个像素电路的节点的信号之后，向第N行像素电路和第N+1行像素电路重新写入数据信号，以保证第N行像素和第N+1行像素正常显示。在向第N行像素电路写入数据信号时，已经将第N行像素电路所需的数据信号端DATA的信号写入至第N+1行像素电路中的节点中，且由于第N+2个扫描信号端SCAN(N+2)提供无效电平，第N+1行像素电路中的节点处于浮接状态，使得第N+1行像素电路无法正常写入数据信号，导致第N+1行像素电路驱动的OLED无法正常发光，影响了显示效果。
图1为本公开实施例提供的像素电路的结构示意图。如图1所示，本公开实施例提供的像素电路，设置为驱动发光元件，像素电路包括：节点控制子电路、驱动子电路、存储子电路和读取子电路。
节点控制子电路，分别与第一扫描端G1、第一节点N1、第二节点N2、数据信号端DATA和控制信号端SENSE电连接，设置为在第一扫描端G1的控制下，向第一节点N1提供数据信号端DATA的信号，向第二节点N2提供控制信号端SENSE的信号。驱动子电路，分别与第一节点N1、第一电源端VDD和第二节点N2电连接，设置为在第一节点N1和第二节点N2的控制下，向第二节点N2提供驱动电流。存储子电路，分别与第一节点N1和第二节点N2电连接，设置为存储第一节点N1和第二节点N2之间的电荷。读取子电路，分别与第二扫描端G2、第二节点N2和控制信号端SENSE电连接，设置为在第二扫描端G2的控制下，向第二节点N2提供控制信号端SENSE的信号，或者向控制信号端SENSE提供第二节点N2的信号。
在一种示例性实施例中，发光元件，分别与第二节点N2和第二电源端VSS电连接。
在一种示例性实施例中，发光元件可以为有机发光二极管OLED。其中，OLED的阳极与第二节点N2电连接，OLED的阴极与第二电源端VSS电连接。
在一种示例性实施例中，第一电源端VDD的信号可以持续为高电平信 号。第一电源端VDD的信号的电压值可以大于或者等于5伏特。
在一种示例性实施例中，第二电源端VSS的信号可以持续为低电平信号。第二电源端VSS的信号的电压值可以小于第一电源端VDD的信号的电压值。
在一种示例性实施例中，控制信号端SENSE可以提供信号，还可以读取第二节点N2的信号。控制信号端SENSE读取到的信号设置为获取驱动子电路中晶体管的参数，以对数据信号端DATA进行外部补偿，可以减小流向发光元件的驱动电流的差异。
在一种示例性实施例中，控制信号端SENSE的信号为参考信号。参考信号的电压值小于第二电源端VSS的信号的电压值。
在一种示例性实施例中，不同像素电路连接的控制信号端SENSE为同一信号端。
本公开实施例提供的像素电路设置为驱动发光元件，像素电路包括：节点控制子电路、驱动子电路、存储子电路和读取子电路；节点控制子电路，分别与第一扫描端、第一节点、第二节点、数据信号端和控制信号端电连接，设置为在第一扫描端的控制下，向第一节点提供数据信号端的信号，向第二节点提供控制信号端的信号；驱动子电路，分别与第一节点、第一电源端和第二节点电连接，设置为在第一节点和第二节点的控制下，向第二节点提供驱动电流；存储子电路，分别与第一节点和第二节点电连接，设置为存储第一节点和第二节点之间的电荷；读取子电路，分别与第二扫描端、第二节点和控制信号端电连接，设置为在第二扫描端的控制下，向第二节点提供控制信号端的信号，或者向控制信号端提供第二节点的信号；发光元件，分别与第二节点和第二电源端电连接。本公开实施例提供的节点控制子电路通过第一扫描端向第二节点提供控制信号端的信号，可以保证在感应阶段对某行像素电路进行感应之后下一行像素电路的数据信号正常写入，保证了显示正常，提升了显示效果。
图2为一种示例性实施例提供的像素电路的结构示意图。如图2所示，本公开实施例提供的像素电路中节点控制子电路包括：第一节点控制子电路和第二节点控制子电路。
第一节点控制子电路，分别与第一扫描端G1、数据信号端DATA和第 一节点N1电连接，设置为在第一扫描端G1的控制下，向第一节点N1提供数据信号端DATA的信号。第二节点控制子电路，分别与第一扫描端G1、第二节点N2和控制信号端SENSE电连接，设置为在第一扫描端G1的控制下，向第二节点N2提供控制信号端SENSE的信号。
在一种示例性实施中，第一节点控制子电路可以控制第一节点N1的信号。第二节点控制子电路可以控制第二节点N2的信号。
图3为一种示例性实施例提供的第一节点控制子电路的等效电路图。如图3所示，一种示例性实施例提供的第一节点控制子电路包括：第一开关晶体管M1。
第一开关晶体管M1的控制极与第一扫描端G1电连接，第一开关晶体管M1的第一极与数据信号端DATA电连接，第一开关晶体管M1的第二极与第一节点N1电连接。
图3中示出了第一节点控制子电路的示例性结构。第一节点控制子电路的实现方式不限于此。
图4为一种示例性实施例提供的第二节点控制子电路的等效电路图。如图4所示，一种示例性实施例提供的第二节点控制子电路包括：第二开关晶体管M2。
第二开关晶体管M2的控制极与第一扫描端G1电连接，第二开关晶体管M2的第一极与控制信号端SENSE电连接，第二开关晶体管M2的第二极与第二节点N2电连接。
图4中示出了第二节点控制子电路的示例性结构。第二节点控制子电路的实现方式不限于此。
图5为一种示例性实施例提供的驱动子电路的等效电路图。如图5所示，一种示例性实施例提供的驱动子电路包括：驱动晶体管DTFT。
驱动晶体管DTFT的控制极与第一节点N1电连接，驱动晶体管DTFT的第一极与第一电源端VDD电连接，驱动晶体管DTFT的第二极与第二节点N2电连接。
图5中示出了驱动子电路的示例性结构。驱动子电路的实现方式不限于 此。
图6为一种示例性实施例提供的存储子电路的等效电路图。如图6所示，一种示例性实施例提供的存储子电路包括：存储电容C。
存储电容C的第一端与第一节点N1电连接，存储电容C的第二端与第二节点N2电连接。
图6中示出了存储子电路的示例性结构。存储子电路的实现方式不限于此。
图7为本公开实施例提供的读取子电路的等效电路图。如图7所示，一种示例性实施例提供的读取子电路包括：第三开关晶体管M3。
第三开关晶体管M3的控制极与第二扫描端G2电连接，第三开关晶体管M3的第一极与控制信号端SENSE电连接，第三开关晶体管M3的第二极与第二节点N2电连接。
图7中示出了读取子电路的示例性结构。读取子电路的实现方式不限于此。
图8为一种示例性实施例提供的像素电路的等效电路图。如图8所示，一种示例性实施例提供的像素电路中，节点控制子电路包括：第一开关晶体管M1和第二开关晶体管M2，存储子电路包括：存储电容C，读取子电路包括：第三开关晶体管M3，驱动子电路包括：驱动晶体管DTFT。
第一开关晶体管M1的控制极与第一扫描端G1电连接，第一开关晶体管M1的第一极与数据信号端DATA电连接，第一开关晶体管M1的第二极与第一节点N1电连接。第二开关晶体管M2的控制极与第一扫描端G1电连接，第二开关晶体管M2的第一极与控制信号端SENSE电连接，第二开关晶体管M2的第二极与第二节点N2电连接。第三开关晶体管M3的控制极与第二扫描端G2电连接，第三开关晶体管M3的第一极与控制信号端SENSE电连接，第三开关晶体管M3的第二极与第二节点N2电连接。驱动晶体管DTFT的控制极与第一节点N1电连接，驱动晶体管DTFT的第一极与第一电源端VDD电连接，驱动晶体管DTFT的第二极与第二节点N2电连接。存储电容C的第一端与第一节点N1电连接，存储电容C的第二端与第二节点N2电 连接。
在一种示例性实施例中，第一扫描端G1和第二扫描端G2不同时提供有效电平信号。当第一扫描端G1的信号为有效电平时，第二扫描端G2的信号为无效电平，当第二扫描端G2的信号为有效电平时，第一扫描端G1的信号为无效电平。
在一种示例性实施例中，当第一扫描端G1的信号为无效电平时，第二扫描端G2的信号也会为无效电平，当第二扫描端G2的信号为无效电平时，第一扫描端G1的信号也会为无效电平。
有效电平指的是可以导通晶体管的电平，无效电平指的是可以使晶体管截止的电平。当晶体管为P型晶体管时，有效电平为低电平，无效电平为高电平。当晶体管为N型晶体管时，有效电平为高电平，无效电平为低电平。
在一种示例性实施例中，驱动晶体管DTFT、第一开关晶体管M1、第二开关晶体管M2和第三开关晶体管M3可以为N型薄膜晶体管，或者可以为P型薄膜晶体管。当驱动晶体管DTFT、第一开关晶体管M1、第二开关晶体管M2和第三开关晶体管M3的晶体管类型相同时，可以统一工艺流程，减少OLED显示器的工艺制程，有助于提高OLED显示器的产品良率。
以一种示例性实施例提供的像素电路中的开关晶体管M1至M3均为N型薄膜晶体管，且对第N行像素电路进行感应为例。图9为一种示例性实施例提供的像素电路在扫描阶段的时序图；图10为一种示例性实施例提供的像素电路在扫描阶段的工作状态图；图11为一种示例性实施例提供的第N行和第N+1行像素电路在感应阶段的时序图；图12A为一种示例性实施例提供的第N行像素电路在第一阶段的工作状态图；图12B为一种示例性实施例提供的第N+1行像素电路在第一阶段的工作状态图；图13A为一种示例性实施例提供的第N行像素电路在第二阶段的工作状态图；图13B为一种示例性实施例提供的第N+1行像素电路在第二阶段的工作状态图；图14A为一种示例性实施例提供的第N行像素电路在第三阶段的工作状态图；图14B为一种示例性实施例提供的第N+1行像素电路在第三阶段的工作状态图；图15A为一种示例性实施例提供的第N行像素电路在第四阶段的工作状态图；图15B为一种示例性实施例提供的第N+1行像素电路在第四阶段的工作状态 图；图16A为一种示例性实施例提供的第N行像素电路在第五阶段的工作状态图；图16B为一种示例性实施例提供的第N+1行像素电路在第五阶段的工作状态图。如图8至图16所示，一种示例性实施例中涉及的像素电路包括：3个开关晶体管(M1至M3)，1个驱动晶体管(DTFT)、1个电容单元(C)，6个输入端(DATA、G1、G2、SENSE、VDD和VSS)，其中，Gi(j)为第j行像素电路的第i扫描端。
第一电源端VDD持续提供高电平信号。第二电源端VSS持续提供低电平信号。控制信号端SENSE输入的信号为参考信号，参考信号的电压值小于第二电源端VSS的信号的电压值。
在扫描阶段，一种示例性实施例提供的像素电路的工作过程包括：如图9和10所示，第一扫描端G1的输入信号为高电平，第一开关晶体管M1导通，向第一节点N1提供数据信号端DATA输入的信号，此时，数据信号端DATA输入的信号的电压值V d满足V d＝V n，V n为像素在扫描阶段所需的数据信号，第一节点N1的电压值V 1满足V 1＝V n。第二开关晶体管M2导通，向第二节点N2提供控制信号端SENSE输入的信号，此时，控制信号端SENSE输入的信号为参考信号，参考信号的电压值为V ref，第二节点N2的电压值V 2满足V 2＝V ref。存储电容C存储第一节点N1和第二节点N2之间的电荷。由于V n-V ref>V th，V th为驱动晶体管DTFT的阈值电压，此时，驱动晶体管DTFT导通，向OLED提供驱动电流。第二扫描端G2的输入信号为低电平，控制信号端SENSE不读取第二节点N2的信号。
数据信号端DATA输入的信号是经过外部补偿后的数据信号。在扫描阶段，每行像素电路的工作过程均相同。
在感应阶段中，除了第N行像素电路的第一扫描端G1(N)和第二扫描端G2(N)以及第N+1行像素电路的第一扫描端G1(N+1)之外，第N+1行像素电路的第二扫描端G2(N+1)以及其他像素电路的第一扫描端和第二扫描端持续提供低电平信号，在扫描阶段输入的数据信号的作用下，输出驱动电流。感应阶段包括：第一阶段S1、第二阶段S2、第三阶段S3、第四阶段S4和第五阶段S5。
在感应阶段，一种示例性实施例提供的第N行和第N+1行像素电路的 工作过程包括：
第一阶段S1，如图11、12A和12B所示，在第N行像素电路中，第一扫描端G1(N)的输入信号为高电平，第一开关晶体管M1导通，向第一节点N1提供数据信号端DATA输入的信号，此时，数据信号端DATA输入的信号的电压值V d满足V d＝V c，第一节点N1的电压值V 1满足V 1＝V c，第二开关晶体管M2导通，向第二节点N2提供控制信号端SENSE输入的信号，此时，控制信号端SENSE输入的信号为参考信号，参考信号的电压值为V ref，第二节点N2的电压值V 2满足V 2＝V ref，存储电容C存储第一节点N1和第二节点N2之间的电荷，由于V c-V ref>V th，此时，驱动晶体管DTFT导通，此时，第N+1行像素电路的第一扫描端G1(N+1)的输入信号为低电平，第N+1行像素电路在扫描阶段输入的数据信号的作用下，仍输出驱动电流。
无论随机选中哪一行像素电路进行感应，在第一阶段，数据信号端DATA输入的信号的电压值均为V c。
第二阶段S2，如图11、13A和13B所示，在第N行像素电路中，第一扫描端G1(N)的输入信号为低电平，第一开关晶体管M1和第二开关晶体管M2截止，由于驱动晶体管DTFT导通，第一电源端VDD向第二节点N2充电，直至第二节点N2的电压值V 2满足V 2＝V c-V th，此时，驱动晶体管DTFT截止，第二扫描端G2(N)的输入信号为高电平，第三开关晶体管M3导通，但控制信号端SENSE并未输入信号，第二节点N2处于浮接状态。在第N+1行像素电路中，第一扫描端G1(N+1)的输入信号为高电平，第一晶体管M1和第二晶体管M2导通，此时，数据信号端DATA的信号的电压值V d满足V d＝V ref，且控制信号端SENSE并未输入信号，第N+1行像素电路中的第二节点N2处于浮接状态，第N+1行像素电路无法输出驱动电流。
第三阶段S3，如图11、14A和14B所示，在第N行像素电路中，第二扫描端G2(N)的输入信号持续为高电平，第三开关晶体管M3持续导通，控制信号端SENSE读取第二节点N2的信号，以完成对第N行像素电路的感应。在第N+1行像素电路中，第一扫描端G1(N+1)的输入信号为高电平，第一晶体管M1和第二晶体管M2导通，此时，数据信号端DATA的信号的电压值V d满足V d＝V ref，且控制信号端SENSE并未输入信号，第N+1行像 素电路中的第二节点N2处于浮接状态，第N+1行像素电路无法输出驱动电流。
第四阶段S4，如图11、15A和15B所示，在第N行像素电路中，第二扫描端G2(N)的输入信号持续为高电平，第三开关晶体管M3持续导通，向第二节点N2提供控制信号端SENSE输入的信号，此时，控制信号端SENSE输入的信号为参考信号，参考信号的电压值为Vref，第二节点N2的电压值V 2满足V 2＝V ref，但是由于第一扫描端G1(N)的数据信号为低电平，第一晶体管M1和第二晶体管M2截止。在第N+1行像素电路中，第一扫描端G1(N+1)的输入信号为高电平，第一开关晶体管M1和第二开关晶体管M2导通，数据信号端DATA输入的信号的电压值V d满足V d＝V n+1，第一节点N1的电压值V1满足V1＝V n+1，第二节点N2的电压值V 2满足V 2＝V ref，可以实现向第N+1行像素电路写入数据信号，以使得第N+1行像素电路重新输出驱动电流，保证了显示效果。
第五阶段S5，如图11、16A和16B所示，在第N行像素电路中，第二扫描端G2(N)的输入信号为低电平，第三开关晶体管M3截止，第一扫描端G1(N)的输入信号为高电平，第一开关晶体管M1导通，向第一节点N1提供数据信号端DATA输入的信号，此时，数据信号端DATA输入的信号的电压值V d满足V d＝V n，第一节点N1的电压值V 1满足V 1＝V n，第二开关晶体管M2导通，向第二节点N2提供控制信号端SENSE输入的信号，控制信号端SENSE输入的信号为参考信号，参考信号的电压值为Vref，第二节点N2的电压值V 2满足V 2＝V ref，向第N行像素电路写入数据信号，以使得第N行像素电路重新输出驱动电流，以保证显示效果。第N+1行像素电路中，第一扫描端G1(N+1)的输入信号为低电平，不再向第N+1行像素电路写入数据信号。
在第一阶段S1至第三阶段S3完成对第N行像素电路的感应之后，第四阶段S4和第五阶段S5的顺序可以互换。
根据上述分析可知，一种示例性实施例提供的像素电路通过第一扫描端控制第一节点和第二节点的信号，可以实现向像素电路重新写入数据信号，且在写入数据信号的时候，第二扫描端的输入信号为低电平。一种示例性实 施例提供的像素电路可以保证在感应阶段对某行像素电路进行感应之后下一行像素电路的数据信号正常写入，保证了显示正常，提升了显示效果。
本公开实施例还提供了一种显示装置，图17为本公开实施例提供的显示装置的结构示意图。如图17所示，本公开实施例提供的显示装置包括：P行Q列像素电路。
在一种示例性实施例中，P和Q均为大于1的正整数。图18是以一列像素电路为例进行说明的。其中，X(N-1)表示一列像素电路中第N-1行像素电路，X(N)表示一列像素电路中第N行像素电路，依次类推。
如图17所示，在一种示例性实施例中，第i行像素电路X(i)的第二扫描端G2与第i+1行像素电路X(i+1)的第一扫描端G1电连接，1≤i≤P-1。
图18为一种示例性实施例提供的像素电路在扫描阶段和感应阶段的时序图。G1(i)指的是第i行像素电路的第一扫描端。图19是以随机选中第N-1行像素电路为例进行说明的。第N-1行像素电路的第一扫描端G1(N-1)和第N行像素电路的第一扫描端G1(N)的信号并不是持续提供低电平信号，其他像素电路例如第N+1行像素电路的第一扫描端G1(N+1)持续提供低电平信号。
像素电路为前述任一个实施例提供的像素电路，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，一种示例性实施例提供的显示装置还可以包括：栅极驱动电路。栅极驱动电路包括：P级移位寄存器，第i级移位寄存器的输出端与第i行像素电路的第一扫描端电连接。
在一种示例性实施例中，同一列像素电路电连接的数据信号端为同一信号端，同一列像素电路电连接的控制信号端为同一信号端。
在一种示例性实施例中，第一扫描端和第二扫描端的控制信号均由栅极驱动电路提供，可以减少信号线的使用，简化像素电路的布线，可以实现窄边框，提高单位面积像素数量的显示。
本公开实施例还提供了一种像素电路的驱动方法，应用于像素电路中，在驱动显示时，像素电路的驱动时序包括：扫描阶段和感应阶段，在感应阶 段中，本公开实施例提供的像素电路的驱动方法包括以下步骤：
步骤100、在第一扫描端的控制下，节点控制子电路向第一节点提供数据信号端的信号，并向第二节点提供控制信号端的信号，存储子电路存储第一节点和第二节点之间的电荷。
步骤200、在第一节点和第二节点的控制下，驱动子电路向第二节点提供驱动电流。
步骤300、在第二扫描端的控制下，读取子电路向控制信号端提供第二节点的信号。
步骤400、在第二扫描端的控制下，读取子电路向第二节点提供控制信号端的信号。
像素电路为前述任一个实施例提供的像素电路，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，在扫描阶段中，像素电路的驱动方法包括：在第一扫描端的控制下，节点控制子电路向第一节点提供数据信号端的信号，并向第二节点提供控制信号端的信号，存储子电路存储第一节点和第二节点之间的电荷；在第一节点和第二节点的控制下，驱动子电路向第二节点提供驱动电流。
在一种示例性实施例中，当第一扫描端的信号为有效电平时，第二扫描端的信号为无效电平，当第二扫描端的信号为有效电平时，第一扫描端的信号为无效电平。其中，在步骤S100中，第一扫描端的信号为有效电平，在步骤S200至S400中，第一扫描端的信号为无效电平。在步骤S100中，第一扫描端的信号为无效电平，在步骤S200至S400中，第二扫描端的信号为有效电平。
在一种示例性实施例中，在读取子电路不向所述控制信号端提供所述第二节点的信号时，所述控制信号端的信号为参考信号。其中，在步骤S100和步骤S400中，控制信号端的信号为参考信号。
在一种示例性实施例中，参考信号的电压值小于第二电源端的信号的电压值，可以保证显示器的显示效果。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种像素电路，设置为驱动发光元件，包括：节点控制子电路、驱动子电路、存储子电路和读取子电路；
    所述节点控制子电路，分别与第一扫描端、第一节点、第二节点、数据信号端和控制信号端电连接，设置为在第一扫描端的控制下，向第一节点提供数据信号端的信号，向第二节点提供控制信号端的信号；
    所述驱动子电路，分别与第一节点、第一电源端和第二节点电连接，设置为在第一节点和第二节点的控制下，向第二节点提供驱动电流；
    所述存储子电路，分别与第一节点和第二节点电连接，设置为存储第一节点和第二节点之间的电荷；
    所述读取子电路，分别与第二扫描端、第二节点和控制信号端电连接，设置为在第二扫描端的控制下，向第二节点提供控制信号端的信号，或者向控制信号端提供第二节点的信号；
    所述发光元件，分别与第二节点和第二电源端电连接。
  2. 根据权利要求1所述的像素电路，其中，所述节点控制子电路包括：第一节点控制子电路和第二节点控制子电路；
    所述第一节点控制子电路，分别与第一扫描端、数据信号端和第一节点电连接，设置为在第一扫描端的控制下，向第一节点提供数据信号端的信号；
    所述第二节点控制子电路，分别与第一扫描端、第二节点和控制信号端电连接，设置为在第一扫描端的控制下，向第二节点提供控制信号端的信号。
  3. 根据权利要求2所述的像素电路，其中，所述第一节点控制子电路包括：第一开关晶体管；
    第一开关晶体管的控制极与第一扫描端电连接，第一开关晶体管的第一极与数据信号端电连接，第一开关晶体管的第二极与第一节点电连接。
  4. 根据权利要求2所述的像素电路，其中，所述第二节点控制子电路包括：第二开关晶体管；
    第二开关晶体管的控制极与第一扫描端电连接，第二开关晶体管的第一 极与控制信号端电连接，第二开关晶体管的第二极与第二节点电连接。
  5. 根据权利要求1所述的像素电路，其中，所述驱动子电路包括：驱动晶体管；
    驱动晶体管的控制极与第一节点电连接，驱动晶体管的第一极与第一电源端电连接，驱动晶体管的第二极与第二节点电连接。
  6. 根据权利要求1所述的像素电路，其中，所述存储子电路包括：存储电容；
    存储电容的第一端与第一节点电连接，存储电容的第二端与第二节点电连接。
  7. 根据权利要求1所述的像素电路，其中，所述读取子电路包括：第三开关晶体管；
    第三开关晶体管的控制极与第二扫描端电连接，第三开关晶体管的第一极与控制信号端电连接，第三开关晶体管的第二极与第二节点电连接。
  8. 根据权利要求1所述的像素电路，其中，所述节点控制子电路包括：第一开关晶体管和第二开关晶体管，所述存储子电路包括：存储电容，所述读取子电路包括：第三开关晶体管，所述驱动子电路包括：驱动晶体管；
    第一开关晶体管的控制极与第一扫描端电连接，第一开关晶体管的第一极与数据信号端电连接，第一开关晶体管的第二极与第一节点电连接；
    第二开关晶体管的控制极与第一扫描端电连接，第二开关晶体管的第一极与控制信号端电连接，第二开关晶体管的第二极与第二节点电连接；
    第三开关晶体管的控制极与第二扫描端电连接，第三开关晶体管的第一极与控制信号端电连接，第三开关晶体管的第二极与第二节点电连接；
    驱动晶体管的控制极与第一节点电连接，驱动晶体管的第一极与第一电源端电连接，驱动晶体管的第二极与第二节点电连接；
    存储电容的第一端与第一节点电连接，存储电容的第二端与第二节点电连接。
  9. 根据权利要求1至8任一项所述的像素电路，其中，当所述第一扫描 端的信号有效电平时，所述第二扫描端的信号为无效电平，当所述第二扫描端的信号为有效电平时，所述第一扫描端的信号为无效电平。
  10. 一种显示装置，包括：P行Q列像素电路，其中，P，Q为大于1的正整数；
    所述像素电路为如权利要求1至9任一项所述的像素电路。
  11. 根据权利要求10所述的显示装置，其中，第i行像素电路的第二扫描端与第i+1行像素电路的第一扫描端电连接，1≤i≤P-1。
  12. 根据权利要求10所述的显示装置，其中，所述显示装置还包括：栅极驱动电路；
    所述栅极驱动电路包括：P级移位寄存器，第i级移位寄存器的输出端与第i行像素电路的第一扫描端电连接，1≤i≤P。
  13. 一种像素电路的驱动方法，应用于如权利要求1至9任一项所述的像素电路中，在驱动显示时，所述像素电路的驱动时序包括：扫描阶段和感应阶段，在感应阶段中，所述方法包括：
    在第一扫描端的控制下，节点控制子电路向第一节点提供数据信号端的信号，并向第二节点提供控制信号端的信号，存储子电路存储第一节点和第二节点之间的电荷；
    在第一节点和第二节点的控制下，驱动子电路向第二节点提供驱动电流；
    在第二扫描端的控制下，读取子电路向控制信号端提供第二节点的信号；
    在第二扫描端的控制下，读取子电路向第二节点提供控制信号端的信号。
  14. 根据权利要求13所述的方法，其中，在扫描阶段中，所述方法包括：
    在第一扫描端的控制下，节点控制子电路向第一节点提供数据信号端的信号，并向第二节点提供控制信号端的信号，存储子电路存储第一节点和第二节点之间的电荷；
    在第一节点和第二节点的控制下，驱动子电路向第二节点提供驱动电流。
  15. 根据权利要求13或14所述的方法，其中，当所述第一扫描端的信号为有效电平时，所述第二扫描端的信号为无效电平，当所述第二扫描端的 信号为有效电平时，所述第一扫描端的信号为无效电平；
    在读取子电路不向所述控制信号端提供所述第二节点的信号时，所述控制信号端的信号为参考信号。
  16. 根据权利要求15所述的方法，其中，所述参考信号的电压值小于第二电源端的信号的电压值。
PCT/CN2020/107835 2019-08-08 2020-08-07 一种像素电路及其驱动方法、显示装置 WO2021023302A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/294,676 US11335264B2 (en) 2019-08-08 2020-08-07 Pixel circuit and driving method thereof, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910730854.8A CN110288949B (zh) 2019-08-08 2019-08-08 一种像素电路及其驱动方法、显示装置
CN201910730854.8 2019-08-08

Publications (1)

Publication Number Publication Date
WO2021023302A1 true WO2021023302A1 (zh) 2021-02-11

Family

ID=68025035

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/107835 WO2021023302A1 (zh) 2019-08-08 2020-08-07 一种像素电路及其驱动方法、显示装置

Country Status (3)

Country Link
US (1) US11335264B2 (zh)
CN (1) CN110288949B (zh)
WO (1) WO2021023302A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110288949B (zh) 2019-08-08 2021-01-26 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN111261101A (zh) * 2020-02-28 2020-06-09 合肥京东方卓印科技有限公司 像素电路及其驱动方法、显示面板
CN111445861A (zh) 2020-05-06 2020-07-24 合肥京东方卓印科技有限公司 像素驱动电路及驱动方法、移位寄存器电路、显示装置
CN114783373B (zh) * 2022-04-11 2023-06-27 深圳市华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN117859167A (zh) * 2022-06-21 2024-04-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150033915A (ko) * 2013-09-25 2015-04-02 엘지디스플레이 주식회사 유기발광다이오드 표시장치 및 그 구동방법
CN108269527A (zh) * 2016-12-30 2018-07-10 乐金显示有限公司 有机发光二极管显示装置
CN108597449A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 像素电路的检测方法、显示面板的驱动方法和显示面板
CN108877685A (zh) * 2018-07-20 2018-11-23 深圳市华星光电半导体显示技术有限公司 一种oled像素驱动电路及oled显示装置
CN109192142A (zh) * 2018-09-19 2019-01-11 深圳市华星光电技术有限公司 Oled像素驱动电路及驱动方法
CN110288949A (zh) * 2019-08-08 2019-09-27 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2503237A1 (en) * 2005-04-08 2006-10-08 Ignis Innovation Inc. Step calibration driving method and circuit for amoled displays
KR101452210B1 (ko) * 2008-11-17 2014-10-23 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR101073226B1 (ko) * 2010-03-17 2011-10-12 삼성모바일디스플레이주식회사 유기전계발광 표시장치
US9351368B2 (en) * 2013-03-08 2016-05-24 Ignis Innovation Inc. Pixel circuits for AMOLED displays
KR101528148B1 (ko) * 2012-07-19 2015-06-12 엘지디스플레이 주식회사 화소 전류 측정을 위한 유기 발광 다이오드 표시 장치 및 그의 화소 전류 측정 방법
KR20140066830A (ko) * 2012-11-22 2014-06-02 엘지디스플레이 주식회사 유기 발광 표시 장치
KR101968116B1 (ko) * 2012-12-10 2019-08-13 엘지디스플레이 주식회사 유기 전기발광 표시장치 및 그 구동방법
KR102024828B1 (ko) * 2013-11-13 2019-09-24 엘지디스플레이 주식회사 유기발광표시장치
KR102068589B1 (ko) * 2013-12-30 2020-01-21 엘지디스플레이 주식회사 유기 발광 표시 장치 및 그의 구동 방법
KR102270460B1 (ko) * 2014-09-19 2021-06-29 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 열화 보상 방법
US9607549B2 (en) * 2014-12-24 2017-03-28 Lg Display Co., Ltd. Organic light emitting diode display panel and organic light emitting diode display device
CN106935192B (zh) 2017-05-12 2019-04-02 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN106991967A (zh) * 2017-05-27 2017-07-28 深圳市华星光电技术有限公司 像素驱动电路及其修复方法与显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150033915A (ko) * 2013-09-25 2015-04-02 엘지디스플레이 주식회사 유기발광다이오드 표시장치 및 그 구동방법
CN108269527A (zh) * 2016-12-30 2018-07-10 乐金显示有限公司 有机发光二极管显示装置
CN108597449A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 像素电路的检测方法、显示面板的驱动方法和显示面板
CN108877685A (zh) * 2018-07-20 2018-11-23 深圳市华星光电半导体显示技术有限公司 一种oled像素驱动电路及oled显示装置
CN109192142A (zh) * 2018-09-19 2019-01-11 深圳市华星光电技术有限公司 Oled像素驱动电路及驱动方法
CN110288949A (zh) * 2019-08-08 2019-09-27 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置

Also Published As

Publication number Publication date
CN110288949A (zh) 2019-09-27
US20220005413A1 (en) 2022-01-06
US11335264B2 (en) 2022-05-17
CN110288949B (zh) 2021-01-26

Similar Documents

Publication Publication Date Title
WO2021023302A1 (zh) 一种像素电路及其驱动方法、显示装置
CN110660360B (zh) 像素电路及其驱动方法、显示面板
WO2020146978A1 (zh) 像素电路、显示面板及像素电路的驱动方法
JP7159182B2 (ja) 画素回路及びその駆動方法、表示パネル
CN113707080B (zh) 显示面板和显示装置
WO2020052287A1 (zh) 像素电路及其驱动方法、显示装置
US20240038161A1 (en) Pixel circuit and display device and method of driving same
CN111951733B (zh) 像素驱动电路、其驱动方法、显示面板及显示装置
WO2019227989A1 (zh) 像素驱动电路及方法、显示装置
WO2021169570A1 (zh) 像素电路及其驱动方法、显示面板
WO2020177258A1 (zh) 像素驱动电路及显示面板
WO2020252913A1 (zh) 像素驱动电路及显示面板
TWI254266B (en) Active matrix type display apparatus
US20220199040A1 (en) Display device
CN216793268U (zh) 显示面板以及显示装置
WO2022226727A1 (zh) 像素电路、像素驱动方法和显示装置
CN113823226A (zh) 像素电路及其驱动方法、显示基板和显示装置
WO2020177253A1 (zh) 像素驱动电路及显示面板
WO2020224072A1 (zh) 像素驱动电路及显示面板
WO2020173033A1 (zh) 像素驱动电路及显示面板
WO2020199405A1 (zh) 像素驱动电路及显示面板
WO2020173035A1 (zh) 像素驱动电路及显示面板
WO2020211161A1 (zh) 像素驱动电路及显示面板
US12002414B2 (en) Display panel and display device
TWI780635B (zh) 顯示面板以及畫素電路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20851169

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20851169

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20851169

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 13.02.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20851169

Country of ref document: EP

Kind code of ref document: A1