WO2023245432A1 - 像素电路及其驱动方法、显示基板、显示装置 - Google Patents

像素电路及其驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2023245432A1
WO2023245432A1 PCT/CN2022/100175 CN2022100175W WO2023245432A1 WO 2023245432 A1 WO2023245432 A1 WO 2023245432A1 CN 2022100175 W CN2022100175 W CN 2022100175W WO 2023245432 A1 WO2023245432 A1 WO 2023245432A1
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WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
electrode
signal terminal
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PCT/CN2022/100175
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English (en)
French (fr)
Inventor
牛晋飞
玄明花
张粲
王灿
丛宁
张晶晶
白枭
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001846.XA priority Critical patent/CN117859167A/zh
Priority to PCT/CN2022/100175 priority patent/WO2023245432A1/zh
Publication of WO2023245432A1 publication Critical patent/WO2023245432A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and specifically to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • Silicon-based light-emitting diode display devices are also called silicon-based LED display devices.
  • Silicon-based LED display devices are manufactured using the mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit process. They have the advantages of small size, high resolution (Pixels Per Inch, referred to as PPI), and high refresh rate. They are widely used. It is used in various fields such as medicine, military, aerospace and consumer electronics, especially in the fields of wearable devices, virtual reality (VR) or augmented reality (AR) near-eye display.
  • CMOS Complementary Metal Oxide Semiconductor
  • the present disclosure provides a pixel circuit, including: a driving circuit and a light-emitting element, the driving circuit and the light-emitting element are connected in series between a first power terminal and a third power terminal; the driving circuit is used to Provide a driving current and control the conduction time of the current path between the first power terminal and the third power terminal; the light-emitting element is used to receive the driving current in the current path and emit light; the driving The circuit includes: drive control sub-circuit, lighting control sub-circuit and duration control sub-circuit;
  • the drive control sub-circuit is electrically connected to the first scanning signal terminal, the first data signal terminal, the first node and the second node respectively, and is arranged between the first scanning signal terminal, the first data signal terminal and the second node. Under control, provide driving current to the first node;
  • the light-emitting control sub-circuit is electrically connected to the light-emitting signal terminal, the first power terminal and the second node respectively, and is configured to provide the signal of the first power terminal to the second node under the control of the light-emitting signal terminal;
  • the duration control sub-circuit is electrically connected to the second scan signal end, the second data signal end, the second power end, the first node and the third node respectively, and is configured to be between the second scan signal end and the second data signal end. Under control, provide the signal of the first node to the third node;
  • the light-emitting element is electrically connected to the third node and the third power terminal respectively.
  • the signal at the first scanning signal terminal is a valid level signal
  • the signal at the second scanning signal terminal is a valid level signal
  • the light emitting signal terminal is an invalid level signal
  • the signals at the first scanning signal terminal and the second scanning signal terminal are invalid level signals.
  • the drive control sub-circuit is also electrically connected to the third scan signal terminal and is configured to be between the first scan signal terminal, the third scan signal terminal, the first data signal terminal and the second node. Under control, provide driving current to the first node;
  • the signal at the third scanning signal terminal is a valid level signal
  • the signal at the light-emitting signal terminal is a valid level signal
  • the signal at the third scanning signal terminal is an invalid level signal
  • it also includes: a reset subcircuit and/or a node control subcircuit;
  • the reset subcircuit is electrically connected to the reset signal terminal, the initial signal terminal and the third node respectively, and is configured to provide the signal of the initial signal terminal to the third node under the control of the reset signal terminal;
  • the node control subcircuit is electrically connected to the first scanning signal terminal, the control signal terminal and the first node respectively, and is configured to provide the signal of the control signal terminal to the first node under the control of the first scanning signal terminal, or to provide the first node with the signal of the control signal terminal.
  • the signal of the node is read to the control signal terminal, where the voltage value of the signal at the control signal terminal is constant.
  • the signal at the reset signal terminal is a valid level signal
  • the first scanning signal terminal, the second scanning signal terminal and the light emitting signal terminal are invalid level signals
  • the signal at the reset signal terminal is an invalid level signal
  • the signal at the light-emitting signal terminal is a valid level signal
  • the signal at the reset signal terminal is an invalid level signal
  • the drive control subcircuit includes: a first transistor, a second transistor, and a first capacitor;
  • the control electrode of the first transistor is electrically connected to the fourth node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • One plate of the first capacitor is electrically connected to the fourth node, and the other plate of the first capacitor is electrically connected to the fourth power terminal or the first node.
  • the drive control sub-circuit includes: a first transistor, a second transistor, a third transistor and a first capacitor;
  • the control electrode of the first transistor is electrically connected to the fourth node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the control electrode of the third transistor is electrically connected to the third scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the fourth node;
  • One plate of the first capacitor is electrically connected to the fourth node, and the other plate of the first capacitor is electrically connected to the fourth power supply terminal or the first node;
  • the second transistor and the third transistor are of different transistor types.
  • the light emission control sub-circuit includes: a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the second node.
  • the duration control subcircuit includes: a fifth transistor, a sixth transistor, and a second capacitor;
  • the control electrode of the fifth transistor is electrically connected to the fifth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node;
  • the control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;
  • One plate of the second capacitor is electrically connected to the fifth node, and the other plate of the second capacitor is electrically connected to the second power terminal.
  • the reset subcircuit includes: a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node.
  • the node control subcircuit includes: an eighth transistor;
  • the control electrode of the eighth transistor is electrically connected to the first scan signal terminal, the first electrode of the eighth transistor is electrically connected to the control signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node.
  • the driving control subcircuit includes: a first transistor, a second transistor and a first capacitor
  • the lighting control subcircuit includes: a fourth transistor
  • the duration control subcircuit includes: a fifth a transistor, a sixth transistor and a second capacitor
  • the control electrode of the first transistor is electrically connected to the fourth node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the fifth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node;
  • the control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;
  • One plate of the first capacitor is electrically connected to the fourth node, and the other plate of the first capacitor is electrically connected to the fourth power supply terminal or the first node;
  • One plate of the second capacitor is electrically connected to the fifth node, and the other plate of the second capacitor is electrically connected to the second power terminal.
  • the driving control subcircuit includes: a first transistor, a second transistor, a third transistor, and a first capacitor; the lighting control subcircuit includes: a fourth transistor; and the duration control subcircuit Including: a fifth transistor, a sixth transistor and a second capacitor;
  • the control electrode of the first transistor is electrically connected to the fourth node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the control electrode of the third transistor is electrically connected to the third scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the fourth node;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the fifth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node;
  • the control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;
  • One plate of the first capacitor is electrically connected to the fourth node, and the other plate of the first capacitor is electrically connected to the fourth power supply terminal or the first node;
  • One plate of the second capacitor is electrically connected to the fifth node, and the other plate of the second capacitor is electrically connected to the second power terminal;
  • the second transistor and the third transistor are of opposite transistor types.
  • it also includes: a reset subcircuit and/or a node control subcircuit
  • the driving control subcircuit includes: a first transistor, a second transistor, and a first capacitor
  • the lighting control subcircuit includes: The fourth transistor
  • the duration control sub-circuit includes: a fifth transistor, a sixth transistor and a second capacitor
  • the reset sub-circuit includes: a seventh transistor
  • the node control sub-circuit includes: an eighth transistor
  • the control electrode of the first transistor is electrically connected to the fourth node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the fifth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node;
  • the control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;
  • the control electrode of the seventh transistor is electrically connected to the reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node;
  • the control electrode of the eighth transistor is electrically connected to the first scan signal terminal, the first electrode of the eighth transistor is electrically connected to the control signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node;
  • One plate of the first capacitor is electrically connected to the fourth node, and the other plate of the first capacitor is electrically connected to the fourth power supply terminal or the first node; when the pixel circuit includes a node control subcircuit, the first capacitor The other plate is electrically connected to the first node;
  • One plate of the second capacitor is electrically connected to the fifth node, and the other plate of the second capacitor is electrically connected to the second power terminal.
  • it also includes: a reset subcircuit and/or a node control subcircuit
  • the driving control subcircuit includes: a first transistor, a second transistor, a third transistor and a first capacitor
  • the lighting control subcircuit includes a fourth transistor
  • the duration control sub-circuit includes a fifth transistor, a sixth transistor and a second capacitor
  • the reset sub-circuit includes a seventh transistor
  • the node control sub-circuit includes an eighth transistor.
  • the control electrode of the first transistor is electrically connected to the fourth node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first data signal terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the control electrode of the third transistor is electrically connected to the third scan signal terminal, the first electrode of the third transistor is electrically connected to the first data signal terminal, and the second electrode of the third transistor is electrically connected to the fourth node;
  • the control electrode of the fourth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the fifth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node;
  • the control electrode of the sixth transistor is electrically connected to the second scan signal terminal, the first electrode of the sixth transistor is electrically connected to the second data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;
  • the control electrode of the seventh transistor is electrically connected to the reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the third node;
  • the control electrode of the eighth transistor is electrically connected to the first scan signal terminal, the first electrode of the eighth transistor is electrically connected to the control signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node;
  • One plate of the first capacitor is electrically connected to the fourth node, and the other plate of the first capacitor is electrically connected to the fourth power supply terminal or the first node; when the pixel circuit includes a node control subcircuit, the first capacitor The other plate is electrically connected to the first node;
  • One plate of the second capacitor is electrically connected to the fifth node, and the other plate of the second capacitor is electrically connected to the second power terminal;
  • the second transistor and the third transistor are of opposite transistor types.
  • the light-emitting element includes: a micro light-emitting diode or a mini light-emitting diode.
  • the present disclosure also provides a display substrate, including: a display area and a non-display area surrounding at least one side of the display area, the display area is provided with a plurality of pixels, and the pixels are provided with The above pixel circuit.
  • the pixel circuit includes: a node control sub-circuit, and the display substrate further includes: a first chip connected to a control signal terminal and a second chip connected to the first data signal terminal;
  • the first chip is configured to provide a signal to the control signal terminal during the display phase, read the signal from the control signal terminal during the non-display phase, and is also configured to obtain the threshold voltage of the first transistor based on the signal from the control signal terminal. threshold voltage, generate a control signal, and send the control signal to the second chip;
  • the second chip provides a signal to the first data signal terminal according to the control signal.
  • the present disclosure also provides a display device, including: the above display substrate.
  • the present disclosure also provides a driving method of a pixel circuit, configured to drive the above-mentioned pixel circuit, the pixel circuit is located in a display substrate, the display substrate includes: a display stage, the display stage includes: a plurality of display frames , the display frame includes: at least one display subframe; the display subframe includes: a light-emitting data writing stage and a light-emitting stage, and the method includes:
  • the drive control subcircuit provides drive current to the first node under the control of the first scan signal terminal, the first data signal terminal and the second node, and the duration control subcircuit provides drive current to the first node under the control of the second scan signal terminal and the second scan signal terminal. Under the control of the second data signal terminal, provide the signal of the first node to the third node;
  • the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the light-emitting signal terminal.
  • the pixel circuit further includes a reset subcircuit
  • the display subframe further includes a reset phase
  • the method further includes:
  • the reset subcircuit provides the signal of the initial signal terminal to the third node under the control of the reset signal terminal.
  • the pixel circuit further includes: a node control sub-circuit
  • the display substrate further includes: a non-display stage
  • the non-display stage includes: a compensation data writing stage and a compensation stage
  • the method Also includes:
  • the node control subcircuit provides the signal of the control signal terminal to the first node under the control of the first scanning signal terminal;
  • the node control subcircuit reads the signal of the first node to the control signal terminal under the control of the first scan signal terminal.
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a pixel circuit provided in an exemplary embodiment
  • Figure 3 is a schematic structural diagram of a pixel circuit provided by another exemplary embodiment
  • Figure 4 is a schematic structural diagram of a pixel circuit provided by yet another exemplary embodiment
  • Figure 5 is a schematic structural diagram of a pixel circuit provided by yet another exemplary embodiment
  • Figure 6A is an equivalent circuit diagram of a drive control subcircuit provided by an exemplary embodiment
  • Figure 6B is an equivalent circuit diagram of a drive control subcircuit provided by another exemplary embodiment
  • Figure 7 is an equivalent circuit diagram of a lighting control subcircuit provided by an exemplary embodiment
  • Figure 8 is an equivalent circuit diagram of a duration control subcircuit provided by an exemplary embodiment
  • Figure 9 is an equivalent circuit diagram of a reset subcircuit provided by an exemplary embodiment
  • Figure 10 is an equivalent circuit diagram of a node control subcircuit provided by an exemplary embodiment
  • Figure 11 is an equivalent circuit diagram 1 of a pixel circuit provided by an exemplary embodiment
  • Figure 12 is an equivalent circuit diagram 2 of a pixel circuit provided by an exemplary embodiment
  • Figure 13 is an equivalent circuit diagram 3 of a pixel circuit provided by an exemplary embodiment.
  • Figure 14 is an equivalent circuit diagram 4 of a pixel circuit provided by an exemplary embodiment
  • Figure 15 is an equivalent circuit diagram 5 of a pixel circuit provided by an exemplary embodiment
  • Figure 16 is an equivalent circuit diagram 6 of a pixel circuit provided by an exemplary embodiment
  • Figure 17 is an equivalent circuit diagram 7 of a pixel circuit provided by an exemplary embodiment
  • Figure 18 is an equivalent circuit diagram 8 of a pixel circuit provided by an exemplary embodiment
  • Figure 19 is a working timing diagram of the pixel circuit provided in Figure 11 in the display stage
  • Figure 20 is a working timing diagram of the pixel circuit provided in Figure 12 during the display stage
  • Figure 21 is a working timing diagram of the pixel circuit provided in Figure 13 during the display stage
  • Figure 22 is a working timing diagram of the pixel circuit provided in Figure 14 in the display stage
  • Figure 23 is a working timing diagram of the pixel circuit provided in Figure 15 in the display stage
  • Figure 24 is a working timing diagram of the pixel circuit provided in Figure 16 in the display stage
  • Figure 25 is a working timing diagram of the pixel circuit provided in Figure 17 in the display stage
  • Figure 26 is a working timing diagram of the pixel circuit provided in Figure 18 in the display stage
  • Figure 27 is a working timing diagram of the pixel circuit provided in Figures 15 and 17 during the non-display stage;
  • FIG. 28 is an operating timing diagram of the pixel circuit provided in FIGS. 16 and 18 during the non-display stage.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • the lighting voltages of different light-emitting diode elements are inconsistent.
  • the electro-optical conversion characteristics (including efficiency, uniformity, color coordinates, etc.) of self-luminous elements change with the current, making the light-emitting diodes including
  • the display of component display products is uneven and the luminous efficiency is low, which reduces the display effect of the display products.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit provided by the embodiment of the present disclosure includes: a driving circuit and a light-emitting element.
  • the driving circuit and the light-emitting element are connected in series between the first power terminal VDD and the third power terminal VSS; the driving circuit is used to provide a driving current. , and controls the conduction time of the current path between the first power terminal VDD and the third power terminal VSS; the light-emitting element is used to receive the driving current in the current path and emit light;
  • the driving circuit includes: a driving control subcircuit , lighting control sub-circuit and duration control sub-circuit.
  • the driving control subcircuit is electrically connected to the first scanning signal terminal Gate1, the first data signal terminal Data1, the first node N1 and the second node N2 respectively, and is configured to operate between the first scanning signal terminal Gate1 and the first data signal terminal Data1. Under the control of a data signal terminal Data1 and the second node N2, a driving current is provided to the first node N1.
  • the light-emitting control subcircuit is electrically connected to the light-emitting signal terminal EM, the first power supply terminal VDD and the second node N2 respectively, and is configured to provide the signal of the first power supply terminal VDD to the second node N2 under the control of the light-emitting signal terminal EM.
  • the duration control subcircuit is electrically connected to the second scanning signal terminal Gate2, the second data signal terminal Data2, the second power supply terminal Vcom1, the first node N1 and the third node N3 respectively, and is configured to connect between the second scanning signal terminal Gate2 and the third node N3. Under the control of the second data signal terminal Data2, the signal of the first node N1 is provided to the third node N3.
  • the light-emitting element is electrically connected to the third node N3 and the third power supply terminal VSS respectively.
  • the first power terminal VDD continuously provides a high-level signal
  • the second power terminal Vcom1 and the third power terminal VSS continuously provide low-level signals.
  • the voltage value of the signal at the second power supply terminal Vcom1 may be 0V
  • the voltage value of the signal at the third power supply terminal VSS may be a negative value, for example, it may be -2V.
  • a light emitting element includes a first pole and a second pole.
  • the first electrode of the light-emitting element is electrically connected to the third node N3, and the second electrode of the light-emitting element is electrically connected to the third power supply terminal VSS.
  • the light emitting element may be a micro light emitting diode or a mini light emitting diode.
  • Typical dimensions (eg, length) of micro-LEDs may be less than 80 ⁇ m, such as 10 ⁇ m to 50 ⁇ m, and do not include a growth substrate (eg, sapphire); typical dimensions (eg, length) of mini-LEDs may be approximately 80 ⁇ m to 350 ⁇ m, such as 100 ⁇ m to 50 ⁇ m. 220 ⁇ m.
  • the pixel circuit in the present disclosure can control the light-emitting duration of the light-emitting element through the duration control sub-circuit and the light-emitting control sub-circuit in an interval where the photoelectric parameters of the light-emitting element are relatively stable.
  • the pixel circuit in the present disclosure may be disposed on a silicon-based substrate.
  • the pixel circuit in the present disclosure is arranged on a silicon-based substrate, which can improve the electrical stability of the pixel circuit. Since the electrical stability of the pixel circuit provided on the silicon-based substrate is good, the drive circuit in the pixel circuit provided on the silicon-based substrate does not need to be provided with an internal compensation circuit, which can reduce the area occupied by the drive circuit. Improving the PPI of the display product where the pixel circuit is located avoids the "screen door effect" and can improve the display effect of the display product where the pixel circuit is located.
  • the pixel circuit provided by the embodiment of the present disclosure includes: a driving circuit and a light-emitting element, the driving circuit and the light-emitting element are connected in series between the first power terminal and the third power terminal; the driving circuit is used to provide a driving current, and Control the conduction time of the current path between the first power terminal and the third power terminal; the light-emitting element is used to receive the drive current in the current path and emit light; the drive circuit includes: drive control sub-circuit, lighting control sub-circuit and duration control sub-circuit; the driving control sub-circuit is electrically connected to the first scanning signal terminal, the first data signal terminal, the first node and the second node respectively, and is configured to operate at the first scanning signal terminal , provide driving current to the first node under the control of the first data signal terminal and the second node; the lighting control sub-circuit is electrically connected to the lighting signal terminal, the first power supply terminal and the second node respectively, and is set to be at the lighting signal terminal.
  • the duration control subcircuit is electrically connected to the second scanning signal terminal, the second data signal terminal, the second power supply terminal, the first node and the third node respectively, and is set to Under the control of the second scan signal terminal and the second data signal terminal, the signal of the first node is provided to the third node; the light-emitting element is electrically connected to the third node and the third power terminal respectively.
  • the present disclosure can control the light-emitting time of the light-emitting element, improve the uniformity and luminous efficiency of the light-emitting element in low gray scale, and improve the display effect of the display product.
  • the signal of the first scanning signal terminal Gate1 when the signal of the first scanning signal terminal Gate1 is a valid level signal, the signal of the second scanning signal terminal Gate2 is a valid level signal, and the light emitting signal terminal EM is an invalid level signal; when the signal of the light-emitting signal terminal EM is a valid level signal, the signals of the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 are invalid level signals.
  • the pixel circuit is disposed in a display substrate, and the display substrate includes: a display phase and a non-display phase.
  • the display stage may include: a plurality of display frames, the display frame includes: at least one display subframe; the display subframe includes: a light-emitting data writing stage and a light-emitting stage.
  • the display frame in this disclosure includes: at least one display sub-frame can realize multiple scans in one frame, which realizes flexible control of the lighting duration of the light-emitting element, improves the uniformity of the pixel circuit at low gray scale, improves the contrast, and improves the display Product display effect.
  • the non-display phase may include: a power-on phase, a power-off phase, and a blank phase located between the display phases.
  • the duration of the lighting phase of different display subframes may be the same, or may be different.
  • the duration of the lighting phase of different display subframes is different, the duration of the lighting phase of the display subframe that occurs later is shorter than the duration of the lighting phase of the display subframe that occurs earlier, and the duration of the lighting phase of the display subframe that occurs later is The duration of the light-emitting phase of the display sub-frame that occurs earlier can be controlled more accurately.
  • the signal of the first scanning signal terminal Gate1 and the signal of the second scanning signal terminal Gate2 are valid level signals, and the signal of the luminescence signal terminal EM is an invalid level signal.
  • the signal of the first scanning signal terminal Gate1 and the signal of the second scanning signal terminal Gate2 are invalid level signals, and the signal of the light-emitting signal terminal EM is a valid level signal.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided in an exemplary embodiment.
  • the driving control sub-circuit is also electrically connected to the third scanning signal terminal Gate3, and is configured to operate between the first scanning signal terminal Gate1, the third scanning signal terminal Gate3, and the first scanning signal terminal Gate3. Under the control of the data signal terminal Data1 and the second node N2, a driving current is provided to the first node N1.
  • the signal of the third scanning signal terminal Gate3 when the signal of the first scanning signal terminal Gate1 is a valid level signal, the signal of the third scanning signal terminal Gate3 is a valid level signal; when the signal of the light emitting signal terminal EM is a valid level signal When the signal is generated, the signal at the third scanning signal terminal Gate3 is an invalid level signal.
  • the signal of the third scanning signal terminal Gate3 is a valid level signal, and during the lighting phase, the signal of the third scanning signal terminal Gate3 is an invalid level signal.
  • FIG. 3 is a schematic structural diagram of a pixel circuit provided by another exemplary embodiment.
  • FIG. 4 is a schematic structural diagram of a pixel circuit provided by yet another exemplary embodiment.
  • FIG. 5 is a schematic structural diagram of a pixel circuit provided by yet another exemplary embodiment.
  • the pixel circuit may further include: a reset subcircuit and/or a node control subcircuit.
  • Figure 3 is an example of a pixel circuit that also includes a reset subcircuit.
  • Figure 4 is an example of a pixel circuit that also includes a node control subcircuit.
  • Figure 5 is an example of a pixel circuit that also includes a reset subcircuit and a node control subcircuit.
  • FIG. 3 to 5 all illustrate by taking the driving control subcircuit electrically connected to the first scanning signal terminal Gate1, the first data signal terminal Data1, the first node N1 and the second node N2 respectively as an example.
  • the drive control subcircuit can also be electrically connected to the third scanning signal terminal Gate3.
  • the reset subcircuit is electrically connected to the reset signal terminal Reset, the initial signal terminal INIT and the third node N3 respectively, and is configured to provide initialization to the third node N3 under the control of the reset signal terminal Reset.
  • the signal of the signal terminal INIT is electrically connected to the reset signal terminal Reset, the initial signal terminal INIT and the third node N3 respectively, and is configured to provide initialization to the third node N3 under the control of the reset signal terminal Reset.
  • the signal of the signal terminal INIT is electrically connected to the reset signal terminal Reset, the initial signal terminal INIT and the third node N3 respectively, and is configured to provide initialization to the third node N3 under the control of the reset signal terminal Reset.
  • the present disclosure can ensure the uniformity of light emission of the light-emitting elements and improve the display effect of the display product.
  • the node control subcircuit is electrically connected to the first scanning signal terminal Gate1, the control signal terminal S and the first node N1 respectively, and is configured to control the first scanning signal terminal Gate1 to the first node N1.
  • a node N1 provides a signal of the control signal terminal S, or reads the signal of the first node N1 to the control signal terminal S.
  • the voltage value of the signal at the control signal terminal S is constant, and the voltage value of the signal at the control signal terminal S may be 0V.
  • the present disclosure can reset the first node in the display phase by setting the node control sub-circuit, and can also obtain the signal of the first node N1 in the non-display phase to externally compensate the signal of the first data signal terminal Data1 in the display phase. Improve the display effect of display products.
  • the signal of the reset signal terminal Reset when the signal of the reset signal terminal Reset is a valid level signal, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2 and the light-emitting signal terminal EM are invalid level signals; when the first scanning signal terminal Gate1, the second scanning signal terminal Gate2 and the light emitting signal terminal EM are invalid level signals; When the signal of the scanning signal terminal Gate1 is a valid level signal, the signal of the reset signal terminal Reset is an invalid level signal; when the signal of the light-emitting signal terminal EM is a valid level signal, the signal of the reset signal terminal Reset is an invalid level signal. .
  • the display subframe may further include a reset phase.
  • the reset phase occurs before the luminous data write phase.
  • the signal of the reset signal terminal Reset is a valid level signal
  • the signals of the first scanning signal terminal Gate1, the second scanning signal terminal Gate2 and the light-emitting signal terminal EM are invalid level signals; in the data writing phase and During the light-emitting phase, the signal of the reset signal terminal Reset is an invalid level signal.
  • the driving control subcircuit may also be electrically connected to the fourth power supply terminal.
  • the third power terminal and the fourth power terminal may be the same power terminal, or may be different power terminals, and this disclosure does not place any limitation on this.
  • FIG. 6A is an equivalent circuit diagram of a driving control subcircuit provided by an exemplary embodiment.
  • the driving control subcircuit may include: a first transistor T1, a second transistor T2, and a first capacitor C1.
  • control electrode of the first transistor T1 is electrically connected to the fourth node N4, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4;
  • One plate of the first capacitor C1 is electrically connected to the fourth node N4, and the other plate of the first capacitor C1 is electrically connected to the fourth power terminal Vcom2 or the first node N1.
  • FIG. 6B is an equivalent circuit diagram of a driving control subcircuit provided by another exemplary embodiment.
  • the driving control subcircuit may include: a first transistor T1 , a second transistor T2 , a third transistor T3 and a first capacitor C1 .
  • control electrode of the first transistor T1 is electrically connected to the fourth node N4, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4;
  • the control electrode of the third transistor T3 is electrically connected to the third scanning signal terminal Gate3, the first electrode of the third transistor T3 is electrically connected to the first data signal terminal Data1, and the second electrode T3 of the third transistor T3 is electrically connected to the fourth node N4. Connection; one plate of the first capacitor C1 is electrically connected to the fourth node N4, and the other plate of the first capacitor C1 is electrically connected to the fourth power terminal Vcom2 or the first node N1.
  • the second transistor T2 and the third transistor T3 have different transistor types.
  • the second transistor T2 and the third transistor T3 are equivalent to transmission gates, which can increase the writing range of the data signal at the first data signal terminal Data1 and improve the reliability of the pixel circuit.
  • FIG. 7 is an equivalent circuit diagram of a lighting control subcircuit provided by an exemplary embodiment.
  • the light emission control sub-circuit may include: a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is electrically connected to the light emitting signal terminal EM
  • the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VDD
  • the second electrode of the fourth transistor T4 is electrically connected to the second node N2.
  • FIG. 7 illustrates an example in which the driving control subcircuit is electrically connected to the first scanning signal terminal Gate1, the first data signal terminal Data1, the first node N1 and the second node N2 respectively.
  • the drive control sub-circuit may also be electrically connected to the third scanning signal terminal Gate3 and/or the fourth power supply terminal Vcom2.
  • FIG. 7 An exemplary structure of the lighting control subcircuit is shown in FIG. 7 . Those skilled in the art can easily understand that the implementation of the lighting control sub-circuit is not limited to this.
  • FIG. 8 is an equivalent circuit diagram of a duration control subcircuit provided by an exemplary embodiment.
  • the duration control sub-circuit may include: a fifth transistor T5 , a sixth transistor T6 and a second capacitor C2 .
  • control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3;
  • the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal Gate2, the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5;
  • One plate of the second capacitor C2 is electrically connected to the fifth node N5, and the other plate of the second capacitor C2 is electrically connected to the second power terminal Vcom1.
  • FIG. 8 illustrates an example of a driving control subcircuit that is electrically connected to the first scanning signal terminal Gate1, the first data signal terminal Data1, the first node N1, and the second node N2.
  • the drive control sub-circuit may also be electrically connected to the third scanning signal terminal Gate3 and/or the fourth power supply terminal Vcom2.
  • FIG. 8 An exemplary structure of the duration control subcircuit is shown in FIG. 8 . Those skilled in the art can easily understand that the implementation manner of the duration control sub-circuit is not limited to this.
  • FIG. 9 is an equivalent circuit diagram of a reset subcircuit provided by an exemplary embodiment.
  • the reset sub-circuit may include: a seventh transistor T7.
  • the control electrode of the seventh transistor T7 is electrically connected to the reset signal terminal Reset
  • the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT
  • the second electrode of the seventh transistor T7 is electrically connected to the third node N3.
  • FIG. 9 illustrates an example in which the driving control subcircuit is electrically connected to the first scanning signal terminal Gate1, the first data signal terminal Data1, the first node N1 and the second node N2 respectively.
  • the drive control sub-circuit may also be electrically connected to the third scanning signal terminal Gate3 and/or the fourth power supply terminal Vcom2.
  • FIG. 9 An exemplary structure of the reset subcircuit is shown in FIG. 9 . Those skilled in the art can easily understand that the implementation of the reset subcircuit is not limited to this.
  • FIG. 10 is an equivalent circuit diagram of a node control subcircuit provided by an exemplary embodiment.
  • the node control sub-circuit may include an eighth transistor T8.
  • the control electrode of the eighth transistor T8 is electrically connected to the first scanning signal terminal Gate1
  • the first electrode of the eighth transistor T8 is electrically connected to the control signal terminal S
  • the second electrode of the eighth transistor T8 is electrically connected to the first node N1. .
  • FIG. 10 illustrates an example of a driving control subcircuit that is electrically connected to the first scanning signal terminal Gate1, the first data signal terminal Data1, the first node N1, and the second node N2.
  • the drive control subcircuit can also be electrically connected to the third scanning signal terminal Gate3.
  • FIG. 10 An exemplary structure of the node control subcircuit is shown in FIG. 10 . Those skilled in the art can easily understand that the implementation of the node control subcircuit is not limited to this.
  • FIG. 11 is an equivalent circuit diagram 1 of a pixel circuit provided by an exemplary embodiment.
  • the driving control subcircuit may include: a first transistor T1, a second transistor T2, and a first capacitor C1;
  • the lighting control subcircuit may include: a fourth transistor T4.
  • the control subcircuit may include: a fifth transistor T5, a sixth transistor T6, and a second capacitor C2.
  • control electrode of the first transistor T1 is electrically connected to the fourth node N4, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the first node N1. Electrically connected; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the fourth node.
  • N4 is electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.
  • the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3;
  • the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal Gate2, the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5;
  • One plate of the first capacitor C1 is electrically connected to the fourth node N4, the other plate of the first capacitor C1 is electrically connected to the fourth power supply terminal Vcom2 or the first node N1;
  • one plate of the second capacitor C2 is electrically connected to the fifth node N4.
  • the node N5 is electrically connected, and the other plate of the second capacitor C2 is electrically connected to the second power terminal Vcom1.
  • the transistor types of the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6 may be the same, or may be different, and this disclosure does not impose any limitation on this.
  • FIG. 11 illustrates an example in which the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are N-type transistors, and the fourth transistor T4 is a P-type transistor.
  • the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6 are all metal oxide semiconductor transistors.
  • Metal oxide semiconductor transistors can reduce leakage current, improve the performance of pixel circuits, and reduce the power consumption of pixel circuits.
  • FIG. 12 is an equivalent circuit diagram 2 of a pixel circuit provided by an exemplary embodiment.
  • the driving control sub-circuit may include: a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1;
  • the light-emitting control sub-circuit may include: a The four-transistor T4,
  • the duration control sub-circuit may include: a fifth transistor T5, a sixth transistor T6 and a second capacitor C2.
  • control electrode of the first transistor T1 is electrically connected to the fourth node N4, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the first node N1. Electrical connection; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the second electrode of the second transistor T2 is electrically connected to the fourth node.
  • N4 is electrically connected; the control electrode of the third transistor T3 is electrically connected to the third scanning signal terminal Gate3, the first electrode of the third transistor T3 is electrically connected to the first data signal terminal Data1, and the second electrode T3 of the third transistor T3 is electrically connected to the third scanning signal terminal Gate3.
  • the four nodes N4 are electrically connected; the control electrode of the fourth transistor T4 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node.
  • N2 is electrically connected; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3. ;
  • the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal Gate2, the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.
  • one plate of the first capacitor C1 is electrically connected to the fourth node N4, and the other plate of the first capacitor C1 is electrically connected to the fourth power supply terminal Vcom2 or the first node N1; one plate of the second capacitor C2 is electrically connected to The fifth node N5 is electrically connected, and the other plate of the second capacitor C2 is electrically connected with the second power terminal Vcom1.
  • the second transistor T2 and the third transistor T3 have opposite transistor types.
  • the transistor types of the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6 may be the same, or may be different, and this disclosure does not impose any limitation on this.
  • FIG. 12 illustrates an example in which the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors.
  • the first to sixth transistors T1 to T6 are all metal oxide semiconductor transistors.
  • Metal oxide semiconductor transistors can reduce leakage current, improve the performance of pixel circuits, and reduce the power consumption of pixel circuits.
  • Figure 13 is an equivalent circuit diagram 3 of a pixel circuit provided by an exemplary embodiment.
  • Figure 14 is an equivalent circuit diagram 4 of a pixel circuit provided by an exemplary embodiment.
  • Figure 15 is a pixel circuit diagram provided by an exemplary embodiment.
  • Figure 16 is an equivalent circuit diagram 6 of a pixel circuit provided by an exemplary embodiment.
  • Figure 17 is an equivalent circuit diagram 7 of a pixel circuit provided by an exemplary embodiment.
  • Figure 18 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment.
  • the equivalent circuit diagram of the pixel circuit provided by the exemplary embodiment is shown in Figure 8.
  • the pixel circuit may further include: a reset subcircuit and/or a node control subcircuit.
  • Figures 13 and 14 illustrate using the pixel circuit including a reset subcircuit as an example
  • Figures 15 and 16 illustrate using the pixel circuit including a node control subcircuit as an example
  • Figures 17 and 18 illustrate the pixel circuit including a node control subcircuit and a reset subcircuit as an example.
  • the driving control sub-circuit may include: a first transistor T1, a second transistor T2 and a first capacitor C1; the light-emitting control sub-circuit includes: a fourth The transistor T4, the duration control subcircuit may include a fifth transistor T5, a sixth transistor T6 and a second capacitor C2, the reset subcircuit may include a seventh transistor T7, and the node control subcircuit may include an eighth transistor T8.
  • the control electrode of the first transistor T1 is electrically connected to the fourth node N4, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4.
  • the control electrode of the second transistor T2 is electrically connected to the first scanning signal terminal Gate1
  • the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1
  • the control electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1.
  • the two poles are electrically connected to the fourth node N4; the control pole of the fourth transistor T4 is electrically connected to the light emitting signal terminal EM, the first pole of the fourth transistor T4 is electrically connected to the first power supply terminal VDD, and the second pole of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the third node N2.
  • the node N3 is electrically connected; the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal Gate2, the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal Gate2.
  • the five nodes N5 are electrically connected; the control electrode of the seventh transistor T7 is electrically connected to the reset signal terminal Reset, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3 Electrically connected; the control electrode of the eighth transistor T8 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the eighth transistor T8 is electrically connected to the control signal terminal S, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.
  • one plate of the first capacitor C1 is electrically connected to the fourth node N4, and the other plate of the first capacitor C1 is electrically connected to the fourth power supply terminal Vcom2 or the first node N1; one plate of the second capacitor C2 is electrically connected to The fifth node N5 is electrically connected, and the other plate of the second capacitor C2 is electrically connected with the second power terminal Vcom1.
  • the other plate of the first capacitor C1 when the pixel circuit includes a node control sub-circuit, the other plate of the first capacitor C1 is electrically connected to the first node N1.
  • the first capacitor C1 When the pixel circuit does not include a node control sub-circuit, the first capacitor C1 The other plate of C1 may be electrically connected to the fourth power terminal Vcom2 or the first node N1.
  • the transistor types of the first transistor T1, the second transistor T2, the fourth transistor T4 to the eighth transistor T8 may be the same, or may be different, and this disclosure does not impose any limitation on this.
  • 13 , 15 and 17 take the example that the first transistor T1 , the second transistor T2 , the fifth transistor T5 to the eighth transistor T8 are N-type transistors, and the fourth transistor T4 is a P-type transistor.
  • the first transistor T1, the second transistor T2, the fourth transistor T4 to the eighth transistor T8 are all metal oxide semiconductor transistors.
  • Metal oxide semiconductor transistors can reduce leakage current, improve the performance of pixel circuits, and reduce the power consumption of pixel circuits.
  • the driving control sub-circuit may include: first to third transistors T1 to T3 and a first capacitor C1, and the light-emitting control sub-circuit includes: a fourth The transistor T4, the duration control subcircuit may include a fifth transistor T5, a sixth transistor T6 and a second capacitor C2, the reset subcircuit may include a seventh transistor T7, and the node control subcircuit may include an eighth transistor T8.
  • the control electrode of the first transistor T1 is electrically connected to the fourth node N4, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the second node N2.
  • the control electrode of the second transistor T2 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1, and the control electrode of the second transistor T2 is electrically connected to the first data signal terminal Data1.
  • the two poles are electrically connected to the fourth node N4; the control pole of the third transistor T3 is electrically connected to the third scanning signal terminal Gate3, the first pole of the third transistor T3 is electrically connected to the first data signal terminal Data1, and the third transistor T3
  • the second electrode T3 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VDD, and the third electrode of the fourth transistor T4 is electrically connected.
  • the two poles are electrically connected to the second node N2; the control pole of the fifth transistor T5 is electrically connected to the fifth node N5; the first pole of the fifth transistor T5 is electrically connected to the first node N1; the second pole of the fifth transistor T5 is electrically connected to The third node N3 is electrically connected; the control electrode of the sixth transistor T6 is electrically connected to the second scan signal terminal Gate2, the first electrode of the sixth transistor T6 is electrically connected to the second data signal terminal Data2, and the second electrode of the sixth transistor T6 is electrically connected.
  • the control electrode of the seventh transistor T7 is electrically connected to the reset signal terminal Reset, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, the second electrode of the seventh transistor T7 is electrically connected to the third The node N3 is electrically connected; the control electrode of the eighth transistor T8 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the eighth transistor T8 is electrically connected to the control signal terminal S, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1 is electrically connected; one plate of the first capacitor C1 is electrically connected to the fourth node N4, and the other plate of the first capacitor C1 is electrically connected to the fourth power supply terminal Vcom2 or the first node N1; one pole of the second capacitor C2 The plate is electrically connected to the fifth node N5, and the other plate of the second capacitor C2 is electrically connected to the second power terminal Vcom1.
  • the other plate of the first capacitor C1 when the pixel circuit includes a node control sub-circuit, the other plate of the first capacitor C1 is electrically connected to the first node N1.
  • the first capacitor C1 When the pixel circuit does not include a node control sub-circuit, the first capacitor C1 The other plate of C1 may be electrically connected to the fourth power terminal Vcom2 or to the first node N1.
  • the second transistor T2 and the third transistor T3 have opposite transistor types.
  • the transistor types of the first to eighth transistors T1 to T8 may be the same or may be different, and the present disclosure does not impose any limitation on this.
  • Figure 14, Figure 16 and Figure 18 are performed based on the example that the first transistor T1, the second transistor T2, the fifth transistor T5 to the eighth transistor T8 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors. explained.
  • the first to eighth transistors T1 to T8 are all metal oxide semiconductor transistors.
  • Metal oxide semiconductor transistors can reduce leakage current, improve the performance of pixel circuits, and reduce the power consumption of pixel circuits.
  • the first transistor T1 may be called a driving transistor.
  • the first transistor T1 determines the flow between the second node N2 and the first node N1 based on the potential difference between its control electrode and the first electrode. through the drive current.
  • the light-emitting element in the present disclosure may be a silicon-based LED, that is, the light-emitting element is disposed on a silicon-based substrate.
  • all transistors in the present disclosure may be disposed on a silicon-based substrate, and may be metal oxide semiconductor transistors, and the width-to-length ratio of the active layer of the metal oxide semiconductor transistor is in (sub) Micron level, i.e. smaller in size. Therefore, the pixel circuit in the present disclosure may also be called a silicon-based circuit.
  • the display substrate where the pixel circuit is located can achieve high PPI, usually above 2000-3000PPI, avoiding the "screen door effect". Since the electrical performance of metal oxide semiconductor transistors is relatively stable, the electrical performance stability of silicon-based circuits is better. While pursuing high PPI, there is no need for excessive internal threshold compensation.
  • FIG. 19 is a working timing diagram of the pixel circuit provided in FIG. 11 in the display stage.
  • FIG. 19 illustrates an example in which the first transistor T1 , the second transistor T2 , the fifth transistor T5 to the sixth transistor T6 are N-type transistors, and the fourth transistor T4 is a P-type transistor.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 is turned on, the first data signal terminal Data1 outputs the data voltage
  • the signal of the first data signal terminal Data1 passes through the turned-on
  • the second transistor T2 writes to the fourth node N4
  • the signal of the second scanning signal terminal Gate2 is a high level signal
  • the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs the data voltage
  • the signal of the second data signal terminal Data2 The fifth node N5 is written through the turned-on sixth transistor T6.
  • the fifth transistor T5 is turned on.
  • the fifth node N5 is written to the fifth node N5.
  • the signal is flat, the fifth transistor T5 is turned off, the signal at the light-emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light-emitting element L does not emit light.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4.
  • the signal of the scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 is turned off
  • the fourth node N4 maintains the signal of the previous stage
  • the first transistor T1 is turned on
  • the signal of the second scanning signal terminal Gate2 is a low-level signal.
  • the sixth transistor T6 is turned off, the fifth node N5 maintains the signal of the previous stage, and the fifth transistor T5 maintains the on or off state of the previous stage.
  • the fifth transistor T5 When the fifth transistor T5 is turned on, the first power supply terminal VDD to the third power supply The current path between the terminals VSS is turned on, and the light-emitting element L emits light. When the fifth transistor T5 is turned off, the current path between the first power terminal VDD and the third power terminal VSS is turned off, and the light-emitting element L does not emit light.
  • FIG. 20 is a working timing diagram of the pixel circuit provided in FIG. 12 in the display stage.
  • FIG. 20 illustrates an example in which the first transistor T1 , the second transistor T2 , the fifth transistor T5 to the sixth transistor T6 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 is turned on
  • the signal of the third scanning signal terminal Gate3 is a low-level signal
  • the third transistor T3 is turned on
  • the third transistor T3 is turned on
  • the third transistor T3 is turned on.
  • a data signal terminal Data1 outputs a data voltage.
  • the signal of the first data signal terminal Data1 is written into the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3.
  • the signal of the second scanning signal terminal Gate2 is high. level signal
  • the sixth transistor T6 is turned on
  • the second data signal terminal Data2 outputs the data voltage
  • the signal of the second data signal terminal Data2 is written into the fifth node N5 through the turned-on sixth transistor T6.
  • the fifth transistor T5 When the second data signal terminal When the signal of Data2 is a high-level signal, the fifth transistor T5 is turned on. When the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, and the signal of the light-emitting signal terminal EM is a high-level signal. , the fourth transistor T4 is turned off, and the light-emitting element L does not emit light.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4.
  • the signal of the scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 is turned off
  • the signal of the third scanning signal terminal Gate3 is a high-level signal
  • the third transistor T3 is turned off
  • the fourth node N4 maintains the signal of the previous stage.
  • One transistor T1 is turned on, the signal of the second scanning signal terminal Gate2 is a low level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains the signal of the previous stage, and the fifth transistor T5 maintains the on or off state of the previous stage. state, when the fifth transistor T5 is turned on, the current path between the first power terminal VDD and the third power terminal VSS is turned on, and the light-emitting element L emits light.
  • the fifth transistor T5 is turned off, the first power terminal VDD to the third power terminal VSS is turned on. The current path between the three power terminals VSS is turned off, and the light-emitting element L does not emit light.
  • FIG. 21 is a working timing diagram of the pixel circuit provided in FIG. 13 in the display stage.
  • FIG. 21 illustrates an example in which the first transistor T1 , the second transistor T2 , the fifth transistor T5 to the seventh transistor T7 are N-type transistors, and the fourth transistor T4 is a P-type transistor.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the reset signal terminal Reset is a high-level signal
  • the seventh transistor T7 is turned on, and the signal of the initial signal terminal INIT is written into the third node N3 through the turned-on seventh transistor T7, and the first signal of the light-emitting element is pole to reset
  • the signal of the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 is turned off
  • the signal of the second scanning signal terminal Gate2 is a low-level signal
  • the sixth transistor T6 is turned off
  • the signal of the light-emitting signal terminal EM is a high-level signal
  • the fourth transistor T4 is turned off, and the light-emitting element L does not emit light.
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 is turned on, the first data signal terminal Data1 outputs the data voltage
  • the signal of the first data signal terminal Data1 passes through the turned-on
  • the second transistor T2 writes to the fourth node N4
  • the signal of the second scanning signal terminal Gate2 is a high level signal
  • the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs the data voltage
  • the signal of the second data signal terminal Data2 The fifth node N5 is written through the turned-on sixth transistor T6.
  • the fifth transistor T5 is turned on.
  • the fifth node N5 is written to the fifth node N5.
  • the fifth transistor T5 is turned off, the signal of the light-emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, the signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, and the light-emitting element L is not glow.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4, and the reset signal
  • the signal at terminal Reset is a low-level signal
  • the seventh transistor T7 is turned off
  • the signal at the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 is turned off
  • the fourth node N4 maintains the signal of the previous stage
  • the first transistor T1 is turned on
  • the signal of the second scanning signal terminal Gate2 is a low-level signal
  • the sixth transistor T6 is turned off
  • the fifth node N5 maintains the signal of the previous stage
  • the fifth transistor T5 maintains the on or off state of the previous stage.
  • the fifth transistor T5 When the fifth transistor T5 is turned on, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light-emitting element L emits light.
  • the fifth transistor T5 When the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on. The current path between the terminals VSS is turned off, and the light-emitting element L does not emit light.
  • FIG. 22 is a working timing diagram of the pixel circuit provided in FIG. 14 in the display stage.
  • FIG. 22 illustrates an example in which the first transistor T1, the second transistor T2, the fifth transistor T5 to the seventh transistor T7 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the reset signal terminal Reset is a high-level signal
  • the seventh transistor T7 is turned on, and the signal of the initial signal terminal INIT is written into the third stage N3 through the turned-on seventh transistor T7, and the first signal of the light-emitting element is pole to reset
  • the signal of the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 is turned off
  • the signal of the third scanning signal terminal Gate3 is a high-level signal
  • the third transistor T3 is turned off
  • the second scanning signal terminal Gate2 The signal of is a low-level signal
  • the sixth transistor T6 is turned off
  • the signal of the light-emitting signal terminal EM is a high-level signal
  • the fourth transistor T4 is turned off, and the light-emitting element L does not emit light.
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 is turned on
  • the signal of the third scanning signal terminal Gate3 is a low-level signal
  • the third transistor T3 is turned on
  • the third transistor T3 is turned on
  • the third transistor T3 is turned on.
  • a data signal terminal Data1 outputs a data voltage.
  • the signal of the first data signal terminal Data1 is written into the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3.
  • the signal of the second scanning signal terminal Gate2 is high. level signal
  • the sixth transistor T6 is turned on
  • the second data signal terminal Data2 outputs the data voltage
  • the signal of the second data signal terminal Data2 is written into the fifth node N5 through the turned-on sixth transistor T6.
  • the fifth transistor T5 When the second data signal terminal When the signal of Data2 is a high-level signal, the fifth transistor T5 is turned on. When the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, and the signal of the light-emitting signal terminal EM is a high-level signal. , the fourth transistor T4 is turned off, the signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, and the light-emitting element L does not emit light.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4, and the reset signal
  • the signal at terminal Reset is a low-level signal
  • the seventh transistor T7 is turned off
  • the signal at the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 is turned off
  • the signal at the third scanning signal terminal Gate3 is a high-level signal.
  • the third transistor T3 is turned off, the fourth node N4 maintains the signal of the previous stage, the first transistor T1 is turned on, the signal of the second scanning signal terminal Gate2 is a low level signal, the sixth transistor T6 is turned off, and the fifth node N5 remains on.
  • the fifth transistor T5 maintains the on or off state of the previous stage.
  • the fifth transistor T5 is turned on, the current path between the first power terminal VDD and the third power terminal VSS is turned on, and the light-emitting element L emits light.
  • the fifth transistor T5 is turned off, the current path between the first power terminal VDD and the third power terminal VSS is turned off, and the light-emitting element L does not emit light.
  • FIG. 23 is a working timing diagram of the pixel circuit provided in FIG. 15 in the display stage.
  • FIG. 23 illustrates an example in which the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are N-type transistors, and the fourth transistor T4 is a P-type transistor.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 and the eighth transistor T8 are turned on, the first data signal terminal Data1 outputs the data voltage
  • the first data signal terminal Data1 The signal is written into the fourth node N4 through the turned-on second transistor T2
  • the signal from the control signal terminal S is written into the first node N1 through the turned-on eighth transistor T8, and the signal from the second scanning signal terminal Gate2 is a high level signal.
  • the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs the data voltage
  • the signal of the second data signal terminal Data2 is written into the fifth node N5 through the turned-on sixth transistor T6.
  • the fifth transistor T5 When the signal of the second data signal terminal Data2 When it is a high-level signal, the fifth transistor T5 is turned on. When the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, and the signal of the light-emitting signal terminal EM is a high-level signal. The transistor T4 is turned off, and the light-emitting element L does not emit light.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4.
  • the signal of the scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 and the eighth transistor T8 are turned off
  • the fourth node N4 maintains the signal of the previous stage
  • the first transistor T1 is turned on
  • the signal of the second scanning signal terminal Gate2 is Low level signal
  • the sixth transistor T6 is turned off
  • the fifth node N5 maintains the signal of the previous stage
  • the fifth transistor T5 maintains the on or off state of the previous stage
  • the fifth transistor T5 maintains the on or off state of the previous stage
  • the fifth transistor T5 maintains the on or off state of the previous stage
  • the fifth transistor T5 maintains the on or off state of the previous stage
  • the fifth transistor T5 is turned on
  • the first power terminal The current path between VDD and the third power terminal VSS is turned on, and the light-emitting element L emits light.
  • the fifth transistor T5 is turned off
  • the current path between the first power terminal VDD and the third power terminal VSS is turned off, and the light
  • FIG. 24 is a working timing diagram of the pixel circuit provided in FIG. 16 in the display stage.
  • FIG. 24 illustrates an example in which the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors. of.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 and the eighth transistor T8 are turned on
  • the signal of the third scanning signal terminal Gate3 is a low-level signal
  • the third transistor T3 is turned on
  • the first data signal terminal Data1 outputs a data voltage
  • the signal of the first data signal terminal Data1 is written into the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3, and the control signal terminal S
  • the signal is written into the first node N1 through the eighth transistor T8 that is turned on.
  • the signal at the second scanning signal terminal Gate2 is a high level signal.
  • the sixth transistor T6 is turned on.
  • the second data signal terminal Data2 outputs the data voltage.
  • the second data The signal of the signal terminal Data2 is written into the fifth node N5 through the turned-on sixth transistor T6.
  • the fifth transistor T5 When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on.
  • the second data signal terminal Data2 When the signal of EM is a low-level signal, the fifth transistor T5 is turned off, the signal of the light-emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light-emitting element L does not emit light.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4.
  • the signal at the scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 and the eighth transistor T8 are turned off
  • the signal at the third scanning signal terminal Gate3 is a high-level signal
  • the third transistor T3 is turned off
  • the fourth node N4 maintains the previous state.
  • the first transistor T1 is turned on, the signal of the second scanning signal terminal Gate2 is a low level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains the signal of the previous stage, and the fifth transistor T5 maintains the previous stage signal.
  • the fifth transistor T5 On or off state, when the fifth transistor T5 is turned on, the current path between the first power terminal VDD and the third power terminal VSS is turned on, and the light-emitting element L emits light.
  • the fifth transistor T5 is turned off, the first The current path between the power terminal VDD and the third power terminal VSS is turned off, and the light-emitting element L does not emit light.
  • FIG. 25 is a working timing diagram of the pixel circuit provided in FIG. 17 in the display stage.
  • FIG. 25 illustrates an example in which the first transistor T1 , the second transistor T2 , the fifth transistor T5 to the eighth transistor T8 are N-type transistors, and the fourth transistor T4 is a P-type transistor.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the reset signal terminal Reset is a high-level signal
  • the seventh transistor T7 is turned on, and the signal of the initial signal terminal INIT is written into the third node N3 through the turned-on seventh transistor T7, and the first signal of the light-emitting element is pole to reset
  • the signal of the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 and the eighth transistor T8 are turned off
  • the signal of the second scanning signal terminal Gate2 is a low-level signal
  • the sixth transistor T6 is turned off, and emits light.
  • the signal at the signal terminal EM is a high-level signal
  • the fourth transistor T4 is turned off, and the light-emitting element L does not emit light.
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 and the eighth transistor T8 are turned on, the first data signal terminal Data1 outputs the data voltage
  • the first data signal terminal Data1 The signal is written into the fourth node N4 through the turned-on second transistor T2
  • the signal from the control signal terminal S is written into the first node N1 through the turned-on eighth transistor T8, and the signal from the second scanning signal terminal Gate2 is a high level signal.
  • the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs the data voltage
  • the signal of the second data signal terminal Data2 is written into the fifth node N5 through the turned-on sixth transistor T6.
  • the fifth transistor T5 When the signal of the second data signal terminal Data2 When it is a high-level signal, the fifth transistor T5 is turned on. When the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, and the signal of the light-emitting signal terminal EM is a high-level signal. The transistor T4 is turned off, the signal at the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, and the light-emitting element L does not emit light.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4, and the reset signal
  • the signal at terminal Reset is a low-level signal
  • the seventh transistor T7 is turned off
  • the signal at the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 and the eighth transistor T8 are turned off
  • the fourth node N4 maintains the previous stage.
  • the first transistor T1 is turned on
  • the signal of the second scanning signal terminal Gate2 is a low-level signal
  • the sixth transistor T6 is turned off
  • the fifth node N5 maintains the signal of the previous stage
  • the fifth transistor T5 maintains the conduction of the previous stage.
  • the fifth transistor T5 is turned on
  • the current path between the first power terminal VDD and the third power terminal VSS is turned on, and the light-emitting element L emits light.
  • the fifth transistor T5 is turned off
  • the first power terminal The current path between VDD and the third power supply terminal VSS is turned off, and the light-emitting element L does not emit light.
  • FIG. 26 is a working timing diagram of the pixel circuit provided in FIG. 18 in the display stage.
  • FIG. 26 illustrates an example in which the first transistor T1, the second transistor T2, the fifth transistor T5 to the eighth transistor T8 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors.
  • the working process of the pixel circuit in a display subframe may include:
  • the signal of the reset signal terminal Reset is a high-level signal
  • the seventh transistor T7 is turned on
  • the signal of the initial signal terminal INIT is written into the third stage N3 through the turned-on seventh transistor T7
  • the first signal of the light-emitting element is pole to reset
  • the signal of the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 and the eighth transistor T8 are turned off
  • the signal of the third scanning signal terminal Gate3 is a high-level signal
  • the third transistor T3 is turned off
  • the third transistor T3 is turned off.
  • the signal of the second scanning signal terminal Gate2 is a low-level signal
  • the sixth transistor T6 is turned off
  • the signal of the light-emitting signal terminal EM is a high-level signal
  • the fourth transistor T4 is turned off
  • the light-emitting element L does not emit light.
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the second transistor T2 and the eighth transistor T8 are turned on
  • the signal of the third scanning signal terminal Gate3 is a low-level signal
  • the third transistor T3 is turned on
  • the first data signal terminal Data1 outputs a data voltage
  • the signal of the first data signal terminal Data1 is written into the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3, and the control signal terminal S
  • the signal is written into the first node N1 through the eighth transistor T8 that is turned on.
  • the signal at the second scanning signal terminal Gate2 is a high level signal.
  • the sixth transistor T6 is turned on.
  • the second data signal terminal Data2 outputs the data voltage.
  • the second data The signal of the signal terminal Data2 is written into the fifth node N5 through the turned-on sixth transistor T6.
  • the fifth transistor T5 When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on.
  • the second data signal terminal Data2 When the signal of is a low-level signal, the fifth transistor T5 is turned off, the signal of the light-emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, the signal of the reset signal terminal Reset is a low-level signal, and the seventh transistor T7 is turned off. , the light-emitting element L does not emit light.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4, and the reset signal
  • the signal at terminal Reset is a low-level signal
  • the seventh transistor T7 is turned off
  • the signal at the first scanning signal terminal Gate1 is a low-level signal
  • the second transistor T2 and the eighth transistor T8 are turned off
  • the signal at the third scanning signal terminal Gate3 is A high level signal
  • the third transistor T3 is turned off
  • the fourth node N4 maintains the signal of the previous stage
  • the first transistor T1 is turned on
  • the signal of the second scanning signal terminal Gate2 is a low level signal
  • the sixth transistor T6 is turned off
  • the The fifth node N5 maintains the signal of the previous stage
  • the fifth transistor T5 maintains the on or off state of the previous stage.
  • the fifth transistor T5 When the fifth transistor T5 is turned on, the current path between the first power supply terminal VDD and the third power supply terminal VSS When the fifth transistor T5 is turned on, the light-emitting element L emits light. When the fifth transistor T5 is turned off, the current path between the first power terminal VDD and the third power terminal VSS is turned off, and the light-emitting element L does not emit light.
  • the present disclosure controls the fifth transistor T5 to be turned on or off in at least one display subframe within a display frame according to the signal of the second data signal terminal Data2.
  • the current path between the first power supply terminal VDD and the third power supply terminal VSS is Under the same driving current, the light-emitting elements emit light for different durations, thereby achieving different brightness and grayscale effects.
  • FIG. 19 to FIG. 26 use one display frame including: three display subframes, and the duration of the lighting phase P2 of the display subframe S1, the duration of the lighting phase P2 of the display subframe S2, and The ratio of the duration of the lighting phase P2 of the display subframe S3 may be 4:2:1 as an example for illustration.
  • the drive control sub-circuit and the light-emitting control sub-circuit in the present disclosure are configured to control the voltage amplitude of the control electrode of the first transistor, which can control the light-emitting brightness amplitude of the light-emitting element L; the time control sub-circuit controls the current path length of the pixel circuit, The total brightness of the light-emitting element L within a display frame is controlled.
  • FIG. 27 is an operating timing diagram of the pixel circuit provided in FIGS. 15 and 17 during the non-display stage.
  • the working process of the pixel circuit in the non-display stage may include:
  • the signal of the light-emitting signal terminal EM is a high-level signal
  • the fourth transistor T4 is turned off
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the first data signal terminal Data1 outputs the data voltage.
  • the second transistor T2 and the eighth transistor T8 are turned on, and the signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2.
  • the first transistor T1 is turned on, and the signal of the control signal terminal S passes through the turned-on second transistor T2.
  • the passed eighth transistor T8 writes to the first node N1.
  • the signal of the second scanning signal terminal Gate2 is a high-level signal
  • the second data signal terminal Data2 outputs a low-level data voltage
  • the sixth transistor T6 is turned on, and the signal of the second data signal terminal Data2 passes through the turned-on sixth transistor T6
  • the fifth node N5 is written, and the fifth transistor T5 is turned off.
  • the signal of the second scanning signal terminal Gate2 is a low-level signal
  • the sixth transistor T6 is turned off
  • the fifth node N5 maintains the signal of the previous stage
  • the fifth transistor T5 is turned off.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4
  • the signal of the first scanning signal terminal Gate1 is A high level signal
  • the first data signal terminal Data1 outputs a data voltage
  • the second transistor T2 and the eighth transistor T8 continue to be turned on
  • the signal of the first data signal terminal Data1 is written to the fourth node through the turned on second transistor T2 N4, the first transistor T1 is turned on, and the signal from the first power supply terminal VDD is charged to the first node N1 through the turned-on fourth transistor T4, the second node N2 and the turned-on first transistor T1 until the first node N
  • FIG. 28 is an operating timing diagram of the pixel circuit provided in FIGS. 16 and 18 during the non-display stage.
  • the working process of the pixel circuit in the non-display stage may include:
  • the signal of the light-emitting signal terminal EM is a high-level signal
  • the fourth transistor T4 is turned off
  • the signal of the first scanning signal terminal Gate1 is a high-level signal
  • the first data signal terminal Data1 outputs the data voltage.
  • the second transistor T2 and the eighth transistor T8 are turned on
  • the signal of the third scanning signal terminal Gate3 is a low-level signal
  • the third transistor T3 is turned on
  • the signal of the first data signal terminal Data1 passes through the turned-on second transistor T2 and the third transistor T8.
  • the three transistors T3 are written to the fourth node N4, the first transistor T1 is turned on, and the signal of the control signal terminal S is written to the first node N1 through the eighth transistor T8 that is turned on.
  • the signal of the second scanning signal terminal Gate2 is a high-level signal
  • the second data signal terminal Data2 outputs a low-level data voltage
  • the sixth transistor T6 is turned on, and the signal of the second data signal terminal Data2 passes through the turned-on sixth transistor T6
  • the fifth node N5 is written, and the fifth transistor T5 is turned off.
  • the signal of the second scanning signal terminal Gate2 is a low-level signal
  • the sixth transistor T6 is turned off
  • the fifth node N5 maintains the signal of the previous stage
  • the fifth transistor T5 is turned off.
  • the signal of the light-emitting signal terminal EM is a low-level signal
  • the fourth transistor T4 is turned on
  • the signal of the first power supply terminal VDD is written into the second node N2 through the turned-on fourth transistor T4
  • the signal of the first scanning signal terminal Gate1 is A high-level signal
  • the first data signal terminal Data1 outputs a data voltage
  • the second transistor T2 and the eighth transistor T8 continue to be turned on
  • the signal of the third scanning signal terminal Gate3 is a low-level signal
  • the third transistor T3 is turned on
  • the third transistor T3 is turned on.
  • the signal of a data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2 and the third transistor T3.
  • the first transistor T1 is turned on, and the signal of the first power supply terminal VDD passes through the turned-on fourth transistor T4.
  • the second node N2 and the turned-on first transistor T1 charge the first node N1 until the voltage value of the signal at the first node N1 is Vdata1-Vth1, and Vdata1 is the voltage value of the signal at the first data signal terminal Data1, Vth1 is the threshold voltage of the first transistor.
  • the voltage difference across the first capacitor C1 is Vth1
  • the first transistor T1 is turned off, and the signal of the first node N1 can be read to the control signal terminal through the eighth transistor T8 that is turned on. S.
  • the threshold voltage Vth1 of the first transistor can be obtained according to the signal of the control signal terminal S, and the first data signal terminal can be obtained according to the threshold voltage Vth1 of the first transistor.
  • Data1 performs external compensation on the data signal in the display stage.
  • Embodiments of the present disclosure also provide a driving method for a pixel circuit, which is configured to drive the pixel circuit.
  • the pixel circuit is located in a display substrate.
  • the display substrate includes: a display stage, the display stage includes: a plurality of display frames, and the display frame includes: at least one Display sub-frame; the display sub-frame includes: a light-emitting data writing stage and a light-emitting stage.
  • the driving method of the pixel circuit provided by the embodiment of the present disclosure may include the following steps:
  • Step 100 During the luminous data writing phase, the drive control subcircuit provides a drive current to the first node under the control of the first scan signal terminal, the first data signal terminal and the second node, and the duration control subcircuit provides a drive current to the first node during the second scan. Under the control of the signal terminal and the second data signal terminal, the signal of the first node is provided to the third node.
  • Step 200 In the light-emitting stage, the light-emitting control subcircuit provides the signal of the first power terminal to the second node under the control of the light-emitting signal terminal.
  • the pixel circuit is a pixel circuit provided in any of the foregoing embodiments. The implementation principles and effects are similar and will not be described again here.
  • the pixel circuit may further include a reset subcircuit, and the display subframe may further include a reset phase.
  • the driving method of the pixel circuit provided in an exemplary embodiment may further include the following steps:
  • the reset subcircuit provides the signal of the initial signal terminal to the third node under the control of the reset signal terminal.
  • the pixel circuit may further include: a node control sub-circuit; the display substrate further includes: a non-display stage; the non-display stage includes: a compensation data writing stage and a compensation stage.
  • the driving method of the pixel circuit provided in may also include the following steps:
  • the node control subcircuit provides the signal of the control signal terminal to the first node under the control of the first scanning signal terminal;
  • the node control subcircuit reads the signal of the first node to the control signal terminal under the control of the first scan signal terminal.
  • An embodiment of the present disclosure also provides a display substrate, including: a display area and a non-display area surrounding at least one side of the display area.
  • the display area is provided with a plurality of pixels, and pixel circuits are provided in the pixels.
  • the pixel circuit is the pixel circuit provided in any of the aforementioned embodiments.
  • the implementation principles and implementation effects are similar and will not be described again here.
  • the display substrate adopted in the embodiments of the present disclosure can be applied to display products with any resolution.
  • the display substrate when the pixel circuit includes a node control subcircuit, the display substrate further includes: a first chip connected to the control signal terminal and a second chip connected to the first data signal terminal.
  • the first chip is configured to provide a signal to the control signal terminal during the display phase, read the signal from the control signal terminal during the non-display phase, and is also configured to obtain the threshold voltage of the first transistor based on the signal from the control signal terminal. threshold voltage, generate a control signal, and send the control signal to the second chip; the second chip provides a signal to the first data signal terminal according to the control signal.
  • the present disclosure can perform external compensation on the first data signal terminal based on the first chip, which can extend the life of the display substrate and improve the display effect of the display substrate.
  • An embodiment of the present disclosure also provides a display device, including: a display substrate.
  • the display substrate is the display substrate provided in any of the foregoing embodiments.
  • the implementation principles and implementation effects are similar and will not be described again here.
  • the display device may be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED for short) panel, a mobile phone, a tablet computer, a television , monitors, laptops, digital photo frames, navigators and other products or components with display functions.
  • AMOLED active-matrix organic light emitting diode

Abstract

一种像素电路及其驱动方法、显示基板、显示装置，像素电路包括：驱动电路和发光元件。驱动电路和发光元件串联于第一电源端（VDD）和第三电源端（VSS）之间；驱动电路用于提供驱动电流，并控制第一电源端（VDD）和第三电源端（VSS）之间电流通路的导通时长；发光元件用于在电流通路中接收驱动电流，并发光；驱动电路包括驱动控制子电路、发光控制子电路和时长控制子电路；驱动控制子电路设置为在第一扫描信号端（Gate1）、第一数据信号端（Data1）和第二节点（N2）的控制下，向第一节点（N1）提供驱动电流；发光控制子电路设置为在发光信号端（EM）的控制下，向第二节点（N2）提供第一电源端（VDD）的信号；时长控制子电路设置为在第二扫描信号端（Gate2）和第二数据信号端（Data2）的控制下，向第三节点（N3）提供第一节点（N1）的信号。

Description

像素电路及其驱动方法、显示基板、显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种像素电路及其驱动方法、显示基板、显示装置。
背景技术
硅基发光二极管显示器件又称为硅基LED显示器件。硅基LED显示器件采用成熟的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)集成电路工艺制备，具有体积小、高分辨率(Pixels Per Inch，简称PPI)、高刷新率等优点，广泛应用在医学、军事、航空航天和消费电子等各个领域，特别是穿戴器件、虚拟现实(Virtual Reality，简称VR)或增强现实(Augmented Reality，简称AR)近眼显示领域中。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种像素电路，包括：驱动电路和发光元件，所述驱动电路和所述发光元件串联于第一电源端和第三电源端之间；所述驱动电路用于提供驱动电流，并控制所述第一电源端和第三电源端之间电流通路的导通时长；所述发光元件用于在所述电流通路中接收所述驱动电流，并发光；所述驱动电路包括：驱动控制子电路、发光控制子电路和时长控制子电路；
所述驱动控制子电路，分别与第一扫描信号端、第一数据信号端、第一节点和第二节点电连接，设置为在第一扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流；
所述发光控制子电路，分别与发光信号端、第一电源端和第二节点电连接，设置为在发光信号端的控制下，向第二节点提供第一电源端的信号；
所述时长控制子电路，分别与第二扫描信号端、第二数据信号端、第二电源端、第一节点和第三节点电连接，设置为在第二扫描信号端和第二数据信号端的控制下，向第三节点提供第一节点的信号；
所述发光元件，分别与第三节点和第三电源端电连接。
在一些可能的实现方式中，当所述第一扫描信号端的信号为有效电平信号时，所述第二扫描信号端的信号为有效电平信号，所述发光信号端为无效电平信号；
当所述发光信号端的信号为有效电平信号时，所述第一扫描信号端和所述第二扫描信号端的信号为无效电平信号。
在一些可能的实现方式中，所述驱动控制子电路，还与第三扫描信号端电连接，设置为在第一扫描信号端、第三扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流；
当所述第一扫描信号端的信号为有效电平信号时，第三扫描信号端的信号为有效电平信号；
当所述发光信号端的信号为有效电平信号时，第三扫描信号端的信号为无效电平信号。
在一些可能的实现方式中，还包括：复位子电路和/或节点控制子电路；
所述复位子电路，分别与复位信号端、初始信号端和第三节点电连接，设置为在复位信号端的控制下，向第三节点提供初始信号端的信号；
所述节点控制子电路，分别与第一扫描信号端、控制信号端和第一节点电连接，设置为在第一扫描信号端的控制下，向第一节点提供控制信号端的信号，或者将第一节点的信号读取至控制信号端，其中，控制信号端的信号的电压值恒定。
在一些可能的实现方式中，当复位信号端的信号为有效电平信号时，所述第一扫描信号端、所述第二扫描信号端和所述发光信号端为无效电平信号；
当所述第一扫描信号端的信号为有效电平信号时，所述复位信号端的信号为无效电平信号；
当所述发光信号端的信号为有效电平信号时，所述复位信号端的信号为 无效电平信号。
在一些可能的实现方式中，所述驱动控制子电路包括：第一晶体管、第二晶体管和第一电容；
第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接。
在一些可能的实现方式中，所述驱动控制子电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容；
第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
第三晶体管的控制极与第三扫描信号端电连接，第三晶体管的第一极与第一数据信号端电连接，第三晶体管的第二极与第四节点电连接；
第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；
所述第二晶体管和所述第三晶体管的晶体管类型不同。
在一些可能的实现方式中，所述发光控制子电路包括：第四晶体管；
第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接。
在一些可能的实现方式中，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容；
第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接。
在一些可能的实现方式中，所述复位子电路包括：第七晶体管；
第七晶体管的控制极与复位信号端电连接，第七晶体管的第一极与初始信号端电连接，第七晶体管的第二极与第三节点电连接。
在一些可能的实现方式中，节点控制子电路包括：第八晶体管；
第八晶体管的控制极与第一扫描信号端电连接，第八晶体管的第一极与控制信号端电连接，第八晶体管的第二极与第一节点电连接。
在一些可能的实现方式中，所述驱动控制子电路包括：第一晶体管、第二晶体管和第一电容，所述发光控制子电路包括：第四晶体管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容；
第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接；
第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；
第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接。
在一些可能的实现方式中，所述驱动控制子电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容，所述发光控制子电路包括：第四晶体管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容；
第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
第三晶体管的控制极与第三扫描信号端电连接，第三晶体管的第一极与第一数据信号端电连接，第三晶体管的第二极与第四节点电连接；
第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接；
第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；
第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接；
所述第二晶体管和所述第三晶体管的晶体管类型相反。
在一些可能的实现方式中，还包括：复位子电路和/或节点控制子电路，所述驱动控制子电路包括：第一晶体管、第二晶体管和第一电容，所述发光控制子电路包括：第四晶体管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容，所述复位子电路包括：第七晶体管，所述节点控制子电路包括：第八晶体管；
第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与 第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接；
第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
第七晶体管的控制极与复位信号端电连接，第七晶体管的第一极与初始信号端电连接，第七晶体管的第二极与第三节点电连接；
第八晶体管的控制极与第一扫描信号端电连接，第八晶体管的第一极与控制信号端电连接，第八晶体管的第二极与第一节点电连接；
第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；当所述像素电路包括节点控制子电路时，第一电容的另一个极板与第一节点电连接；
第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接。
在一些可能的实现方式中，还包括：复位子电路和/或节点控制子电路，所述驱动控制子电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容，所述发光控制子电路包括：第四晶体管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容，所述复位子电路包括：第七晶体管，所述节点控制子电路包括：第八晶体管；
第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
第三晶体管的控制极与第三扫描信号端电连接，第三晶体管的第一极与第一数据信号端电连接，第三晶体管的第二极与第四节点电连接；
第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一 电源端电连接，第四晶体管的第二极与第二节点电连接；
第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
第七晶体管的控制极与复位信号端电连接，第七晶体管的第一极与初始信号端电连接，第七晶体管的第二极与第三节点电连接；
第八晶体管的控制极与第一扫描信号端电连接，第八晶体管的第一极与控制信号端电连接，第八晶体管的第二极与第一节点电连接；
第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；当所述像素电路包括节点控制子电路时，第一电容的另一个极板与第一节点电连接；
第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接；
所述第二晶体管和所述第三晶体管的晶体管类型相反。
在一些可能的实现方式中，所述发光元件包括：微型发光二极管或者迷你发光二极管。
第二方面，本公开还提供了一种显示基板，包括：显示区域和围设在所述显示区域至少一侧的非显示区域，所述显示区域设置有多个像素，所述像素内设置有上述像素电路。
在一些可能的实现方式中，所述像素电路包括：节点控制子电路，所述显示基板还包括：与控制信号端连接的第一芯片和与第一数据信号端连接的第二芯片；
所述第一芯片设置为在显示阶段向控制信号端提供信号，在非显示阶段读取控制信号端的信号，还设置在根据控制信号端的信号，获得第一晶体管的阈值电压，根据第一晶体管的阈值电压，生成控制信号，并将控制信号发送至所述第二芯片；
所述第二芯片根据所述控制信号，向第一数据信号端提供信号。
第三方面，本公开还提供了一种显示装置，包括：上述显示基板。
第四方面，本公开还提供了一种像素电路的驱动方法，设置为驱动上述像素电路，所述像素电路位于显示基板中，显示基板包括：显示阶段，所述显示阶段包括：多个显示帧，所述显示帧包括：至少一个显示子帧；所述显示子帧包括：发光数据写入阶段和发光阶段，所述方法包括：
在发光数据写入阶段，驱动控制子电路在第一扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流，时长控制子电路在第二扫描信号端和第二数据信号端的控制下，向第三节点提供第一节点的信号；
在发光阶段，发光控制子电路在发光信号端的控制下，向第二节点提供第一电源端的信号。
在一些可能的实现方式中，所述像素电路还包括：复位子电路，所述显示子帧还包括：复位阶段，所述方法还包括：
在复位阶段，复位子电路在复位信号端的控制下，向第三节点提供初始信号端的信号。
在一些可能的实现方式中，所述像素电路还包括：节点控制子电路，所述显示基板还包括：非显示阶段，所述非显示阶段包括：补偿数据写入阶段和补偿阶段，所述方法还包括：
在发光数据写入阶段和补偿数据写入阶段，节点控制子电路在第一扫描信号端的控制下，向第一节点提供控制信号端的信号；
在补偿阶段，节点控制子电路在第一扫描信号端的控制下，将第一节点的信号读取至控制信号端。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的像素电路的结构示意图；
图2为一种示例性实施例提供的像素电路的结构示意图；
图3为另一示例性实施例提供的像素电路的结构示意图；
图4为又一示例性实施例提供的像素电路的结构示意图；
图5为再一示例性实施例提供的像素电路的结构示意图；
图6A为一种示例性实施例提供的驱动控制子电路的等效电路图；
图6B为另一示例性实施例提供的驱动控制子电路的等效电路图；
图7为一种示例性实施例提供的发光控制子电路的等效电路图；
图8为一种示例性实施例提供的时长控制子电路的等效电路图；
图9为一种示例性实施例提供的复位子电路的等效电路图；
图10为一种示例性实施例提供的节点控制子电路的等效电路图；
图11为一种示例性实施例提供的像素电路的等效电路图一；
图12为一种示例性实施例提供的像素电路的等效电路图二；
图13为一种示例性实施例提供的像素电路的等效电路图三，
图14为一种示例性实施例提供的像素电路的等效电路图四；
图15为一种示例性实施例提供的像素电路的等效电路图五；
图16为一种示例性实施例提供的像素电路的等效电路图六；
图17为一种示例性实施例提供的像素电路的等效电路图七；
图18为一种示例性实施例提供的像素电路的等效电路图八；
图19为图11提供的像素电路在显示阶段的工作时序图；
图20为图12提供的像素电路在显示阶段的工作时序图；
图21为图13提供的像素电路在显示阶段的工作时序图；
图22为图14提供的像素电路在显示阶段的工作时序图；
图23为图15提供的像素电路在显示阶段的工作时序图；
图24为图16提供的像素电路在显示阶段的工作时序图；
图25为图17提供的像素电路在显示阶段的工作时序图；
图26为图18提供的像素电路在显示阶段的工作时序图；
图27为图15和图17提供的像素电路在非显示阶段的工作时序图；
图28为图16和图18提供的像素电路在非显示阶段的工作时序图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连 接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
由于发光二极管元件制作工艺不均一，使得不同发光二极管元件的起亮电压不一致，另外，自发光元件的电光转换特性(包括效率、均一性、色坐 标等)随着电流而改变，使得包括发光二极管元件显示产品的显示不均一且发光效率较低，降低了显示产品的显示效果。
图1为本公开实施例提供的像素电路的结构示意图。如图1所示，本公开实施例提供的像素电路包括：驱动电路和发光元件，驱动电路和发光元件串联于第一电源端VDD和第三电源端VSS之间；驱动电路用于提供驱动电流，并控制第一电源端VDD和第三电源端VSS之间电流通路的导通时长；发光元件用于在所述电流通路中接收所述驱动电流，并发光；驱动电路包括：驱动控制子电路、发光控制子电路和时长控制子电路。
如图1所示，驱动控制子电路，分别与第一扫描信号端Gate1、第一数据信号端Data1、第一节点N1和第二节点N2电连接，设置为在第一扫描信号端Gate1、第一数据信号端Data1和第二节点N2的控制下，向第一节点N1提供驱动电流。发光控制子电路，分别与发光信号端EM、第一电源端VDD和第二节点N2电连接，设置为在发光信号端EM的控制下，向第二节点N2提供第一电源端VDD的信号。时长控制子电路，分别与第二扫描信号端Gate2、第二数据信号端Data2、第二电源端Vcom1、第一节点N1和第三节点N3电连接，设置为在第二扫描信号端Gate2和第二数据信号端Data2的控制下，向第三节点N3提供第一节点N1的信号。
如图1所示，发光元件，分别与第三节点N3和第三电源端VSS电连接。
在一种示例性实施例中，第一电源端VDD持续提供高电平信号，第二电源端Vcom1和第三电源端VSS持续提供低电平信号。示例性地，第二电源端Vcom1的信号的电压值可以为0V，第三电源端VSS的信号的电压值可以为负值，例如，可以为-2V。
在一种示例性实施例中，发光元件包括第一极和第二极。示例性地，发光元件的第一极与第三节点N3电连接，发光元件的第二极与第三电源端VSS电连接。
在一种示例性实施例中，发光元件可以是微型发光二极管或者迷你发光二极管。微型发光二极管的典型尺寸(例如长度)可以小于80μm，例如10μm至50μm，并且不包含生长衬底(例如蓝宝石)；迷你发光二极管的典型尺寸(例如长度)可以约为80μm至350μm，例如100μm至220μm。
本公开中的像素电路可以在发光元件的光电参数较为稳定的区间内通过时长控制子电路和发光控制子电路控制发光元件的发光时长。
在一种示例性实施例中，本公开中的像素电路可以设置在硅基衬底上。本公开中的像素电路设置在硅基衬底上可以提升像素电路的电学稳定性。由于设置在硅基衬底上的像素电路的电学稳定性较好，因此，设置在硅基衬底上的像素电路中的驱动电路不需要设置内部补偿电路，可以减少驱动电路所占用的面积，提升像素电路所在的显示产品的PPI，避免了出现“纱窗效应”，可以提升像素电路所在的显示产品的显示效果。
本公开实施例提供的像素电路包括：驱动电路和发光元件，所述驱动电路和所述发光元件串联于第一电源端和第三电源端之间；所述驱动电路用于提供驱动电流，并控制所述第一电源端和第三电源端之间电流通路的导通时长；所述发光元件用于在所述电流通路中接收所述驱动电流，并发光；所述驱动电路包括：驱动控制子电路、发光控制子电路和时长控制子电路；驱动控制子电路，分别与第一扫描信号端、第一数据信号端、第一节点和第二节点电连接，设置为在第一扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流；发光控制子电路，分别与发光信号端、第一电源端和第二节点电连接，设置为在发光信号端的控制下，向第二节点提供第一电源端的信号；时长控制子电路，分别与第二扫描信号端、第二数据信号端、第二电源端、第一节点和第三节点电连接，设置为在第二扫描信号端和第二数据信号端的控制下，向第三节点提供第一节点的信号；发光元件，分别与第三节点和第三电源端电连接。本公开通过设置发光控制子电路和时长控制子电路，可以控制发光元件的发光时间，提升了发光元件在低灰阶的均一性和发光效率，提升了显示产品的显示效果。
在一种示例性实施例中，当第一扫描信号端Gate1的信号为有效电平信号时，第二扫描信号端Gate2的信号为有效电平信号，发光信号端EM为无效电平信号；当发光信号端EM的信号为有效电平信号时，第一扫描信号端Gate1和第二扫描信号端Gate2的信号为无效电平信号。
在一种示例性实施例中，像素电路设置在显示基板中，显示基板包括：显示阶段和非显示阶段。
在一种示例性实施例中，显示阶段可以包括：多个显示帧，显示帧包括：至少一个显示子帧；显示子帧包括：发光数据写入阶段和发光阶段。本公开中显示帧包括：至少一个显示子帧可以实现一帧多扫，实现了发光元件的发光时长的灵活控制，提升了像素电路在低灰阶时的均一性，提高了对比度，提升了显示产品的显示效果。
在一种示例性实施例中，非显示阶段可以包括：开机阶段、关机阶段以及位于显示阶段之间的空白阶段。
在一种示例性实施例中，不同显示子帧的发光阶段的时长可以相同，或者可以不同。当不同显示子帧的发光阶段的时长不同时，较晚发生的显示子帧的发光阶段的时长小于较早发生的显示子帧的发光阶段的时长，较晚发生的显示子帧的发光阶段的时长小于较早发生的显示子帧的发光阶段时长可以对发光元件的发光时长的控制更加精确。
在一种示例性实施例中，在发光数据写入阶段，第一扫描信号端Gate1的信号和第二扫描信号端Gate2的信号为有效电平信号，发光信号端EM的信号为无效电平信号；在发光阶段，第一扫描信号端Gate1的信号和第二扫描信号端Gate2的信号为无效电平信号，发光信号端EM的信号为有效电平信号。
图2为一种示例性实施例提供的像素电路的结构示意图。如图2所示，在一种示例性实施例中，驱动控制子电路，还与第三扫描信号端Gate3电连接，设置为在第一扫描信号端Gate1、第三扫描信号端Gate3、第一数据信号端Data1和第二节点N2的控制下，向第一节点N1提供驱动电流。
在一种示例性实施例中，当第一扫描信号端Gate1的信号为有效电平信号时，第三扫描信号端Gate3的信号为有效电平信号；当发光信号端EM的信号为有效电平信号时，第三扫描信号端Gate3的信号为无效电平信号。
在一种示例性实施例中，在发光数据写入阶段，第三扫描信号端Gate3的信号为有效电平信号，在发光阶段，第三扫描信号端Gate3的信号为无效电平信号。
图3为另一示例性实施例提供的像素电路的结构示意图，图4为又一示例性实施例提供的像素电路的结构示意图，图5为再一示例性实施例提供的 像素电路的结构示意图。如图3至图5所示，在一种示例性实施例中，像素电路还可以包括：复位子电路和/或节点控制子电路。图3是以像素电路还包括复位子电路为例进行说明的，图4是以像素电路还包括节点控制子电路为例进行说明的，图5是以像素电路还包括复位子电路和节点控制子电路为例进行说明的。图3至图5均是以驱动控制子电路，分别与第一扫描信号端Gate1、第一数据信号端Data1、第一节点N1和第二节点N2电连接为例进行说明的。驱动控制子电路还可以与第三扫描信号端Gate3电连接。
如图3和图5所示，复位子电路，分别与复位信号端Reset、初始信号端INIT和第三节点N3电连接，设置为在复位信号端Reset的控制下，向第三节点N3提供初始信号端INIT的信号。
本公开通过设置复位子电路，可以保证发光元件的发光均一性，提升显示产品的显示效果。
如图4和图5所示，节点控制子电路，分别与第一扫描信号端Gate1、控制信号端S和第一节点N1电连接，设置为在第一扫描信号端Gate1的控制下，向第一节点N1提供控制信号端S的信号，或者将第一节点N1的信号读取至控制信号端S。
在一种示例性实施例中，控制信号端S的信号的电压值恒定，控制信号端S的信号的电压值可以为0V。
本公开通过设置节点控制子电路可以在显示阶段对第一节点进行复位，还可以在非显示阶段获取第一节点N1的信号，以对第一数据信号端Data1在显示阶段的信号进行外部补偿，提升显示产品的显示效果。
在一种示例性实施例中，当复位信号端Reset的信号为有效电平信号时，第一扫描信号端Gate1、第二扫描信号端Gate2和发光信号端EM为无效电平信号；当第一扫描信号端Gate1的信号为有效电平信号时，复位信号端Reset的信号为无效电平信号；当发光信号端EM的信号为有效电平信号时，复位信号端Reset的信号为无效电平信号。
在一种示例性实施例中，像素电路包括：复位子电路时，显示子帧还可以包括：复位阶段。复位阶段发生在发光数据写入阶段之前。其中，在复位阶段，复位信号端Reset的信号为有效电平信号，第一扫描信号端Gate1、第 二扫描信号端Gate2和发光信号端EM的信号为无效电平信号；在数据写入阶段和发光阶段，复位信号端Reset的信号为无效电平信号。
在一种示例性实施例中，驱动控制子电路还可以与第四电源端电连接。第三电源端和第四电源端可以为同一电源端，或者可以为不同电源端，本公开对此不作任何限定。
图6A为一种示例性实施例提供的驱动控制子电路的等效电路图。如图6A所示，在一种示例性实施例中，驱动控制子电路可以包括：第一晶体管T1、第二晶体管T2和第一电容C1。其中，第一晶体管T1的控制极与第四节点N4电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一扫描信号端Gate1电连接，第二晶体管T2的第一极与第一数据信号端Data1电连接，第二晶体管T2的第二极与第四节点N4电连接；第一电容C1的一个极板与第四节点N4电连接，第一电容C1的另一个极板与第四电源端Vcom2或者第一节点N1电连接。
图6B为另一示例性实施例提供的驱动控制子电路的等效电路图。如图6B所示，在一种示例性实施例中，驱动控制子电路可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1。其中，第一晶体管T1的控制极与第四节点N4电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一扫描信号端Gate1电连接，第二晶体管T2的第一极与第一数据信号端Data1电连接，第二晶体管T2的第二极与第四节点N4电连接；第三晶体管T3的控制极与第三扫描信号端Gate3电连接，第三晶体管T3的第一极与第一数据信号端Data1电连接，第三晶体管T3的第二极T3与第四节点N4电连接；第一电容C1的一个极板与第四节点N4电连接，第一电容C1的另一个极板与第四电源端Vcom2或者第一节点N1电连接。
在一种示例性实施例中，第二晶体管T2和第三晶体管T3的晶体管类型不同。
本公开中，第二晶体管T2和第三晶体管T3相当于传输门，可以提升第一数据信号端Data1的数据信号的写入范围，提升像素电路的可靠性。
图6A和图6B中示出了驱动控制子电路的两个示例性结构。本领域技术人员容易理解是，驱动控制子电路的实现方式不限于此。
图7为一种示例性实施例提供的发光控制子电路的等效电路图。如图7所示，在一种示例性实施例中，发光控制子电路可以包括：第四晶体管T4。其中，第四晶体管T4的控制极与发光信号端EM电连接，第四晶体管T4的第一极与第一电源端VDD电连接，第四晶体管T4的第二极与第二节点N2电连接。
图7是以驱动控制子电路，分别与第一扫描信号端Gate1、第一数据信号端Data1、第一节点N1和第二节点N2电连接为例进行说明的。驱动控制子电路还可以与第三扫描信号端Gate3和/或第四电源端Vcom2电连接。
图7中示出了发光控制子电路的一个示例性结构。本领域技术人员容易理解是，发光控制子电路的实现方式不限于此。
图8为一种示例性实施例提供的时长控制子电路的等效电路图。如图8所示，在一种示例性实施例中，时长控制子电路可以包括：第五晶体管T5、第六晶体管T6和第二电容C2。其中，第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一节点N1电连接，第五晶体管T5的第二极与第三节点N3电连接；第六晶体管T6的控制极与第二扫描信号端Gate2电连接，第六晶体管T6的第一极与第二数据信号端Data2电连接，第六晶体管T6的第二极与第五节点N5电连接；第二电容C2的一个极板与第五节点N5电连接，第二电容C2的另一个极板与第二电源端Vcom1电连接。
图8是以驱动控制子电路，分别与第一扫描信号端Gate1、第一数据信号端Data1、第一节点N1和第二节点N2电连接为例进行说明的。驱动控制子电路还可以与第三扫描信号端Gate3和/或第四电源端Vcom2电连接。
图8中示出了时长控制子电路的一个示例性结构。本领域技术人员容易理解是，时长控制子电路的实现方式不限于此。
图9为一种示例性实施例提供的复位子电路的等效电路图。如图9所示，在一种示例性实施例中，复位子电路可以包括：第七晶体管T7。其中，第七晶体管T7的控制极与复位信号端Reset电连接，第七晶体管T7的第一极与初始信号端INIT电连接，第七晶体管T7的第二极与第三节点N3电连接。
图9是以驱动控制子电路，分别与第一扫描信号端Gate1、第一数据信号端Data1、第一节点N1和第二节点N2电连接为例进行说明的。驱动控制子电路还可以与第三扫描信号端Gate3和/或第四电源端Vcom2电连接。
图9中示出了复位子电路的一个示例性结构。本领域技术人员容易理解是，复位子电路的实现方式不限于此。
图10为一种示例性实施例提供的节点控制子电路的等效电路图。如图10所示，在一种示例性实施例中，节点控制子电路可以包括：第八晶体管T8。其中，第八晶体管T8的控制极与第一扫描信号端Gate1电连接，第八晶体管T8的第一极与控制信号端S电连接，第八晶体管T8的第二极与第一节点N1电连接。
图10是以驱动控制子电路，分别与第一扫描信号端Gate1、第一数据信号端Data1、第一节点N1和第二节点N2电连接为例进行说明的。驱动控制子电路还可以与第三扫描信号端Gate3电连接。
图10中示出了节点控制子电路的一个示例性结构。本领域技术人员容易理解是，节点控制子电路的实现方式不限于此。
图11为一种示例性实施例提供的像素电路的等效电路图一。如图11所示，在一种示例性实施例中，驱动控制子电路可以包括：第一晶体管T1、第二晶体管T2和第一电容C1，发光控制子电路可以包括：第四晶体管T4，时长控制子电路可以包括：第五晶体管T5、第六晶体管T6和第二电容C2。
如图11所示，第一晶体管T1的控制极与第四节点N4电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一扫描信号端Gate1电连接，第二晶体管T2的第一极与第一数据信号端Data1电连接，第二晶体管T2的第二极与第四节点N4电连接；第四晶体管T4的控制极与发光信号端EM电连接，第四晶体管T4的第一极与第一电源端VDD电连接，第四晶体管T4的第二极与第二节点N2电连接；第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一节点N1电连接，第五晶体管T5的第二极与第三节点N3电连接；第六晶体管T6的控制极与第二扫描信号端Gate2电连接，第六晶体管T6的第一极与第二数据信号端Data2电连接，第六晶体 管T6的第二极与第五节点N5电连接；第一电容C1的一个极板与第四节点N4电连接，第一电容C1的另一个极板与第四电源端Vcom2或者第一节点N1电连接；第二电容C2的一个极板与第五节点N5电连接，第二电容C2的另一个极板与第二电源端Vcom1电连接。
在一种示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第六晶体管T6的晶体管类型可以相同，或者可以不同，本公开对此不作任何限定。图11是以第一晶体管T1、第二晶体管T2、第五晶体管T5和第六晶体管T6为N型晶体管，第四晶体管T4为P型晶体管为例进行说明的。
一种示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第六晶体管T6均为金属氧化物半导体晶体管。金属氧化物半导体晶体管可以减少漏电流，提升像素电路的性能，可以降低像素电路的功耗。
图12为一种示例性实施例提供的像素电路的等效电路图二。如图12所示，在一种示例性实施例中，驱动控制子电路可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1，发光控制子电路可以包括：第四晶体管T4，时长控制子电路可以包括：第五晶体管T5、第六晶体管T6和第二电容C2。
如图12所示，第一晶体管T1的控制极与第四节点N4电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一扫描信号端Gate1电连接，第二晶体管T2的第一极与第一数据信号端Data1电连接，第二晶体管T2的第二极与第四节点N4电连接；第三晶体管T3的控制极与第三扫描信号端Gate3电连接，第三晶体管T3的第一极与第一数据信号端Data1电连接，第三晶体管T3的第二极T3与第四节点N4电连接；第四晶体管T4的控制极与发光信号端EM电连接，第四晶体管T4的第一极与第一电源端VDD电连接，第四晶体管T4的第二极与第二节点N2电连接；第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一节点N1电连接，第五晶体管T5的第二极与第三节点N3电连接；第六晶体管T6的控制极与第二扫描信号端Gate2电连接，第六晶体管T6的第一极与第二数据信号端Data2电连接，第六晶体管T6的第二极与第五节点N5电连接；第一电容C1的一 个极板与第四节点N4电连接，第一电容C1的另一个极板与第四电源端Vcom2或者第一节点N1电连接；第二电容C2的一个极板与第五节点N5电连接，第二电容C2的另一个极板与第二电源端Vcom1电连接。
在一种示例性实施例中，第二晶体管T2和第三晶体管T3的晶体管类型相反。
在一种示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第六晶体管T6的晶体管类型可以相同，或者可以不同，本公开对此不作任何限定。图12是以第一晶体管T1、第二晶体管T2、第五晶体管T5和第六晶体管T6为N型晶体管，第三晶体管T3和第四晶体管T4为P型晶体管为例进行说明的。
一种示例性实施例中，第一晶体管T1至第六晶体管T6均为金属氧化物半导体晶体管。金属氧化物半导体晶体管可以减少漏电流，提升像素电路的性能，可以降低像素电路的功耗。
图13为一种示例性实施例提供的像素电路的等效电路图三，图14为一种示例性实施例提供的像素电路的等效电路图四，图15为一种示例性实施例提供的像素电路的等效电路图五，图16为一种示例性实施例提供的像素电路的等效电路图六，图17为一种示例性实施例提供的像素电路的等效电路图七，图18为一种示例性实施例提供的像素电路的等效电路图八。如图13至图18所示，一种示例性实施例中，像素电路还可以包括：复位子电路和/或节点控制子电路。图13和图14是以像素电路包括复位子电路为例进行说明的，图15和图16是以像素电路包括节点控制子电路为例进行说明的。图17和图18是以像素电路包括节点控制子电路和复位子电路为例进行说明的。
如图13、图15和图17所示，一种示例性实施例中，驱动控制子电路可以包括：第一晶体管T1、第二晶体管T2和第一电容C1，发光控制子电路包括：第四晶体管T4，时长控制子电路可以包括：第五晶体管T5、第六晶体管T6和第二电容C2，复位子电路可以包括：第七晶体管T7，节点控制子电路可以包括：第八晶体管T8。
如图13、图15和图17所示，第一晶体管T1的控制极与第四节点N4电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的 第二极与第一节点N1电连接；第二晶体管T2的控制极与第一扫描信号端Gate1电连接，第二晶体管T2的第一极与第一数据信号端Data1电连接，第二晶体管T2的第二极与第四节点N4电连接；第四晶体管T4的控制极与发光信号端EM电连接，第四晶体管T4的第一极与第一电源端VDD电连接，第四晶体管T4的第二极与第二节点N2电连接；第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一节点N1电连接，第五晶体管T5的第二极与第三节点N3电连接；第六晶体管T6的控制极与第二扫描信号端Gate2电连接，第六晶体管T6的第一极与第二数据信号端Data2电连接，第六晶体管T6的第二极与第五节点N5电连接；第七晶体管T7的控制极与复位信号端Reset电连接，第七晶体管T7的第一极与初始信号端INIT电连接，第七晶体管T7的第二极与第三节点N3电连接；第八晶体管T8的控制极与第一扫描信号端Gate1电连接，第八晶体管T8的第一极与控制信号端S电连接，第八晶体管T8的第二极与第一节点N1电连接；第一电容C1的一个极板与第四节点N4电连接，第一电容C1的另一个极板与第四电源端Vcom2或者第一节点N1电连接；第二电容C2的一个极板与第五节点N5电连接，第二电容C2的另一个极板与第二电源端Vcom1电连接。
在一种示例性实施例中，当像素电路包括节点控制子电路时，第一电容C1的另一个极板与第一节点N1电连接，当像素电路不包括节点控制子电路时，第一电容C1的另一个极板可以与第四电源端Vcom2或者第一节点N1电连接。
在一种示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第八晶体管T8的晶体管类型可以相同，或者可以不同，本公开对此不作任何限定。图13、图15和图17是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第八晶体管T8为N型晶体管，第四晶体管T4为P型晶体管为例进行说明的。
一种示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4至第八晶体管T8均为金属氧化物半导体晶体管。金属氧化物半导体晶体管可以减少漏电流，提升像素电路的性能，可以降低像素电路的功耗。
如图14、图16和图18所示，一种示例性实施例中，驱动控制子电路可 以包括：第一晶体管T1至第三晶体管T3和第一电容C1，发光控制子电路包括：第四晶体管T4，时长控制子电路可以包括：第五晶体管T5、第六晶体管T6和第二电容C2，复位子电路可以包括：第七晶体管T7，节点控制子电路可以包括：第八晶体管T8。
如图14、图16和图18所示，第一晶体管T1的控制极与第四节点N4电连接，第一晶体管T1的第一极与第二节点N2电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一扫描信号端Gate1电连接，第二晶体管T2的第一极与第一数据信号端Data1电连接，第二晶体管T2的第二极与第四节点N4电连接；第三晶体管T3的控制极与第三扫描信号端Gate3电连接，第三晶体管T3的第一极与第一数据信号端Data1电连接，第三晶体管T3的第二极T3与第四节点N4电连接；第四晶体管T4的控制极与发光信号端EM电连接，第四晶体管T4的第一极与第一电源端VDD电连接，第四晶体管T4的第二极与第二节点N2电连接；第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一节点N1电连接，第五晶体管T5的第二极与第三节点N3电连接；第六晶体管T6的控制极与第二扫描信号端Gate2电连接，第六晶体管T6的第一极与第二数据信号端Data2电连接，第六晶体管T6的第二极与第五节点N5电连接；第七晶体管T7的控制极与复位信号端Reset电连接，第七晶体管T7的第一极与初始信号端INIT电连接，第七晶体管T7的第二极与第三节点N3电连接；第八晶体管T8的控制极与第一扫描信号端Gate1电连接，第八晶体管T8的第一极与控制信号端S电连接，第八晶体管T8的第二极与第一节点N1电连接；第一电容C1的一个极板与第四节点N4电连接，第一电容C1的另一个极板与第四电源端Vcom2或者第一节点N1电连接；第二电容C2的一个极板与第五节点N5电连接，第二电容C2的另一个极板与第二电源端Vcom1电连接。
在一种示例性实施例中，当像素电路包括节点控制子电路时，第一电容C1的另一个极板与第一节点N1电连接，当像素电路不包括节点控制子电路时，第一电容C1的另一个极板可以与第四电源端Vcom2或者可以与第一节点N1电连接。
在一种示例性实施例中，在一种示例性实施例中，第二晶体管T2和第三晶体管T3的晶体管类型相反。
在一种示例性实施例中，第一晶体管T1至第八晶体管T8的晶体管类型可以相同，或者可以不同，本公开对此不作任何限定。图14、图16和图18是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第八晶体管T8为N型晶体管，第三晶体管T3和第四晶体管T4为P型晶体管为例进行说明的。
一种示例性实施例中，第一晶体管T1至第八晶体管T8均为金属氧化物半导体晶体管。金属氧化物半导体晶体管可以减少漏电流，提升像素电路的性能，可以降低像素电路的功耗。
一种示例性实施例中，第一晶体管T1可以称为驱动晶体管，第一晶体管T1根据其控制极与第一极之间的电位差来确定在第二节点N2与第一节点N1之间流经的驱动电流。
在一种示例性实施例中，本公开中的发光元件可以为硅基LED，即发光元件设置在硅基衬底上。
在一种示例性实施例中，本公开中的所有晶体管可以设置在硅基衬底上，且可以为金属氧化物半导体晶体管，金属氧化物半导体晶体管的有源层的宽长比在(亚)微米级，即尺寸较小。因此，本公开中的像素电路也可以称为硅基电路。
由于金属氧化物半导体晶体管的有源层的宽长比在(亚)微米级，像素电路所在的显示基板可以实现高PPI，通常在2000-3000PPI以上，避免了出现“纱窗效应”。由于金属氧化物半导体晶体管的电学性能比较稳定使得硅基电路的电学性能稳定性更好，在追求高PPI的同时，不需要过多的进行内部阈值补偿。
下面通过图11示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图19为图11提供的像素电路在显示阶段的工作时序图。图19是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第六晶体管T6为N型晶体管，第四晶体管T4为P型晶体管为例进行说明的。结合图11和图19，像素电路在一个显示子帧的工作过程可以包括：
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第二晶体管T2导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2写入第四节点N4，第二扫描信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端Data2输出数据电压，第二数据信号端Data2的信号通过导通的第六晶体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
下面通过图12示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图20为图12提供的像素电路在显示阶段的工作时序图。图20是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第六晶体管T6为N型晶体管，第三晶体管T3和第四晶体管T4为P型晶体管为例进行说明的。结合图12和图20，像素电路在一个显示子帧的工作过程可以包括：
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第二晶体管T2导通，第三扫描信号端Gate3的信号为低电平信号，第三晶体管T3导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2和导通的第三晶体管T3写入第四节点N4，第二扫描信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端Data2输出数据电压，第二数据信号端Data2的信号通过导通的第六晶 体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2截止，第三扫描信号端Gate3的信号为高电平信号，第三晶体管T3截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
下面通过图13示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图21为图13提供的像素电路在显示阶段的工作时序图。图21是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第七晶体管T7为N型晶体管，第四晶体管T4为P型晶体管为例进行说明的。结合图13和图21，像素电路在一个显示子帧的工作过程可以包括：
复位阶段P3，复位信号端Reset的信号为高电平信号，第七晶体管T7导通，初始信号端INIT的信号通过导通的第七晶体管T7写入第三节点N3，对发光元件的第一极进行复位，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2截止，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第二晶体管T2导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2写入第四节点N4，第二扫描信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端Data2输 出数据电压，第二数据信号端Data2的信号通过导通的第六晶体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
下面通过图14示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图22为图14提供的像素电路在显示阶段的工作时序图。图22是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第七晶体管T7为N型晶体管，第三晶体管T3和第四晶体管T4为P型晶体管为例进行说明的。结合图14和图22，像素电路在一个显示子帧的工作过程可以包括：
复位阶段P3，复位信号端Reset的信号为高电平信号，第七晶体管T7导通，初始信号端INIT的信号通过导通的第七晶体管T7写入第三阶段N3，对发光元件的第一极进行复位，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2截止，第三扫描信号端Gate3的信号为高电平信号，第三晶体管T3截止，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第二晶体管T2导通，第三扫描信号端Gate3的信号为低电平信号，第三晶体管 T3导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2和导通的第三晶体管T3写入第四节点N4，第二扫描信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端Data2输出数据电压，第二数据信号端Data2的信号通过导通的第六晶体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2截止，第三扫描信号端Gate3的信号为高电平信号，第三晶体管T3截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
下面通过图15示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图23为图15提供的像素电路在显示阶段的工作时序图。图23是以第一晶体管T1、第二晶体管T2、第五晶体管T5、第六晶体管T6和第八晶体管T8为N型晶体管，第四晶体管T4为P型晶体管为例进行说明的。结合图15和图23，像素电路在一个显示子帧的工作过程可以包括：
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第二晶体管T2和第八晶体管T8导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2写入第四节点N4，控制信号端S的信号通过导通的第八晶体管T8写入第一节点N1，第二扫描 信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端Data2输出数据电压，第二数据信号端Data2的信号通过导通的第六晶体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2和第八晶体管T8截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
下面通过图16示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图24为图16提供的像素电路在显示阶段的工作时序图。图24是以第一晶体管T1、第二晶体管T2、第五晶体管T5、第六晶体管T6和第八晶体管T8为N型晶体管，第三晶体管T3和第四晶体管T4为P型晶体管为例进行说明的。结合图16和图24，像素电路在一个显示子帧的工作过程可以包括：
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第二晶体管T2和第八晶体管T8导通，第三扫描信号端Gate3的信号为低电平信号，第三晶体管T3导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2和导通的第三晶体管T3写入第四节点N4，控制信号端S的信号通过导通的第八晶体管T8写入第一节点N1，第二扫描信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端Data2输出数据电压，第二数据信号端Data2的信号通过导通的第六晶体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电 平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2和第八晶体管T8截止，第三扫描信号端Gate3的信号为高电平信号，第三晶体管T3截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
下面通过图17示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图25为图17提供的像素电路在显示阶段的工作时序图。图25是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第八晶体管T8为N型晶体管，第四晶体管T4为P型晶体管为例进行说明的。结合图17和图25，像素电路在一个显示子帧的工作过程可以包括：
复位阶段P3，复位信号端Reset的信号为高电平信号，第七晶体管T7导通，初始信号端INIT的信号通过导通的第七晶体管T7写入第三节点N3，对发光元件的第一极进行复位，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2和第八晶体管T8截止，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第二晶体管T2和第八晶体管T8导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2写入第四节点N4，控制信号端S的信号通过导通的第八晶体管T8写入第一节点N1，第二扫描信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端 Data2输出数据电压，第二数据信号端Data2的信号通过导通的第六晶体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2和第八晶体管T8截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
下面通过图18示例的像素电路在显示阶段的工作过程说明本公开示例性实施例。图26为图18提供的像素电路在显示阶段的工作时序图。图26是以第一晶体管T1、第二晶体管T2、第五晶体管T5至第八晶体管T8为N型晶体管，第三晶体管T3和第四晶体管T4为P型晶体管为例进行说明的。结合图18和图26，像素电路在一个显示子帧的工作过程可以包括：
复位阶段P3，复位信号端Reset的信号为高电平信号，第七晶体管T7导通，初始信号端INIT的信号通过导通的第七晶体管T7写入第三阶段N3，对发光元件的第一极进行复位，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2和第八晶体管T8截止，第三扫描信号端Gate3的信号为高电平信号，第三晶体管T3截止，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，发光元件L不发光。
发光数据写入阶段P1，第一扫描信号端Gate1的信号为高电平信号，第 二晶体管T2和第八晶体管T8导通，第三扫描信号端Gate3的信号为低电平信号，第三晶体管T3导通，第一数据信号端Data1输出数据电压，第一数据信号端Data1的信号通过导通的第二晶体管T2和导通的第三晶体管T3写入第四节点N4，控制信号端S的信号通过导通的第八晶体管T8写入第一节点N1，第二扫描信号端Gate2的信号为高电平信号，第六晶体管T6导通，第二数据信号端Data2输出数据电压，第二数据信号端Data2的信号通过导通的第六晶体管T6写入第五节点N5，当第二数据信号端Data2的信号为高电平信号时，第五晶体管T5导通，当第二数据信号端Data2的信号为低电平信号时，第五晶体管T5截止，发光信号端EM的信号为高电平信号，第四晶体管T4截止，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，发光元件L不发光。
发光阶段P2，发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的高电平信号通过导通的第四晶体管T4写入第二节点N2，复位信号端Reset的信号为低电平信号，第七晶体管T7截止，第一扫描信号端Gate1的信号为低电平信号，第二晶体管T2和第八晶体管T8截止，第三扫描信号端Gate3的信号为高电平信号，第三晶体管T3截止，第四节点N4保持上一阶段的信号，第一晶体管T1导通，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5保持上一阶段的导通或者截止状态，当第五晶体管T5导通时，第一电源端VDD至第三电源端VSS之间的电流通路导通，发光元件L发光，当第五晶体管T5截止时，第一电源端VDD至第三电源端VSS之间的电流通路关断，发光元件L不发光。
本公开根据第二数据信号端Data2的信号控制第五晶体管T5在一显示帧内的至少一个显示子帧中导通或者截止，第一电源端VDD至第三电源端VSS之间的电流通路在相同驱动电流下，发光元件不同的发光时长，从而达到不同亮度和灰阶的效果。
在一种示例性实施例中，图19至图26是以一个显示帧包括：三个显示子帧，且显示子帧S1的发光阶段P2的时长、显示子帧S2的发光阶段P2的时长和显示子帧S3的发光阶段P2的时长的比例可以为4:2:1为例进行说明 的。
本公开中的驱动控制子电路和发光控制子电路设置为控制第一晶体管的控制极的电压幅值，可以控制发光元件L的发光亮度幅值；时间控制子电路控制像素电路的电流通路时长，控制发光元件L在一显示帧内的总亮度。
下面通过图15和图17示例的像素电路在非显示阶段的工作过程说明本公开示例性实施例。图27为图15和图17提供的像素电路在非显示阶段的工作时序图。
结合图15、图17和图27，像素电路在非显示阶段工作过程可以包括：
补偿数据写入阶段SP1，发光信号端EM的信号为高电平信号，第四晶体管T4截止，第一扫描信号端Gate1的信号为高电平信号，第一数据信号端Data1输出数据电压，第二晶体管T2和第八晶体管T8导通，第一数据信号端Data1的信号经过导通的第二晶体管T2写入至第四节点N4，第一晶体管T1导通，控制信号端S的信号通过导通的第八晶体管T8写入第一节点N1。第二扫描信号端Gate2的信号为高电平信号，第二数据信号端Data2输出低电平数据电压，第六晶体管T6导通，第二数据信号端Data2的信号经过导通的第六晶体管T6写入第五节点N5，第五晶体管T5截止。
补偿阶段SP2，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5截止。发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的信号通过导通的第四晶体管T4写入第二节点N2，第一扫描信号端Gate1的信号为高电平信号，第一数据信号端Data1输出数据电压，第二晶体管T2和第八晶体管T8持续导通，第一数据信号端Data1的信号经过导通的第二晶体管T2写入至第四节点N4，第一晶体管T1导通，第一电源端VDD的信号经过导通的第四晶体管T4、第二节点N2和导通的第一晶体管T1向第一节点N1进行充电，直至第一节点N1的信号的电压值为Vdata1-Vth1，Vdata1为第一数据信号端Data1的信号的电压值，Vth1为第一晶体管的阈值电压，此时，第一电容C1两端的电压差为Vth1，第一晶体管T1截止，第一节点N1的信号可以通过导通的第八晶体管T8读取至控制信号端S。
下面通过图16和图18示例的像素电路在非显示阶段的工作过程说明本公开示例性实施例。图28为图16和图18提供的像素电路在非显示阶段的工作时序图。
结合图16、图18和图28，像素电路在非显示阶段工作过程可以包括：
补偿数据写入阶段SP1，发光信号端EM的信号为高电平信号，第四晶体管T4截止，第一扫描信号端Gate1的信号为高电平信号，第一数据信号端Data1输出数据电压，第二晶体管T2和第八晶体管T8导通，第三扫描信号端Gate3的信号为低电平信号，第三晶体管T3导通，第一数据信号端Data1的信号经过导通的第二晶体管T2和第三晶体管T3写入至第四节点N4，第一晶体管T1导通，控制信号端S的信号通过导通的第八晶体管T8写入第一节点N1。第二扫描信号端Gate2的信号为高电平信号，第二数据信号端Data2输出低电平数据电压，第六晶体管T6导通，第二数据信号端Data2的信号经过导通的第六晶体管T6写入第五节点N5，第五晶体管T5截止。
补偿阶段SP2，第二扫描信号端Gate2的信号为低电平信号，第六晶体管T6截止，第五节点N5保持上一阶段的信号，第五晶体管T5截止。发光信号端EM的信号为低电平信号，第四晶体管T4导通，第一电源端VDD的信号通过导通的第四晶体管T4写入第二节点N2，第一扫描信号端Gate1的信号为高电平信号，第一数据信号端Data1输出数据电压，第二晶体管T2和第八晶体管T8持续导通，第三扫描信号端Gate3的信号为低电平信号，第三晶体管T3导通，第一数据信号端Data1的信号经过导通的第二晶体管T2和第三晶体管T3写入至第四节点N4，第一晶体管T1导通，第一电源端VDD的信号经过导通的第四晶体管T4、第二节点N2和导通的第一晶体管T1向第一节点N1进行充电，直至第一节点N1的信号的电压值为Vdata1-Vth1，Vdata1为第一数据信号端Data1的信号的电压值，Vth1为第一晶体管的阈值电压，此时，第一电容C1两端的电压差为Vth1，第一晶体管T1截止，第一节点N1的信号可以通过导通的第八晶体管T8读取至控制信号端S。
本公开通过将第一节点N1的信号读取至控制信号端S，根据控制信号端S的信号可以获得为第一晶体管的阈值电压Vth1，根据第一晶体管的阈值电压Vth1对第一数据信号端Data1在显示阶段的数据信号进行外部补偿。
本公开实施例还提供了一种像素电路的驱动方法，设置为驱动像素电路，像素电路位于显示基板中，显示基板包括：显示阶段，显示阶段包括：多个显示帧，显示帧包括：至少一个显示子帧；显示子帧包括：发光数据写入阶段和发光阶段，本公开实施例提供的像素电路的驱动方法可以包括以下步骤：
步骤100、在发光数据写入阶段，驱动控制子电路在第一扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流，时长控制子电路在第二扫描信号端和第二数据信号端的控制下，向第三节点提供第一节点的信号。
步骤200、在发光阶段，发光控制子电路在发光信号端的控制下，向第二节点提供第一电源端的信号。
像素电路为前述任一个实施例提供的像素电路，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，像素电路还可以包括：复位子电路，显示子帧还包括：复位阶段，在一种示例性实施例中提供的像素电路的驱动方法还可以包括以下步骤：
在复位阶段，复位子电路在复位信号端的控制下，向第三节点提供初始信号端的信号。
在一种示例性实施例中，像素电路还可以包括：节点控制子电路，显示基板还包括：非显示阶段，非显示阶段包括：补偿数据写入阶段和补偿阶段，在一种示例性实施例中提供的像素电路的驱动方法还可以包括以下步骤：
在发光数据写入阶段和补偿数据写入阶段，节点控制子电路在第一扫描信号端的控制下，向第一节点提供控制信号端的信号；
在补偿阶段，节点控制子电路在第一扫描信号端的控制下，将第一节点的信号读取至控制信号端。
本公开实施例还提供了一种显示基板，包括：显示区域和围设在显示区域至少一侧的非显示区域，显示区域设置有多个像素，像素内设置有像素电路。
像素电路为前述任一个实施例提供的像素电路，实现原理和实现效果类 似，在此不再赘述。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
在一种示例性实施例中，当像素电路包括：节点控制子电路时，显示基板还包括：与控制信号端连接的第一芯片和与第一数据信号端连接的第二芯片。其中，第一芯片设置为在显示阶段向控制信号端提供信号，在非显示阶段读取控制信号端的信号，还设置在根据控制信号端的信号，获得第一晶体管的阈值电压，根据第一晶体管的阈值电压，生成控制信号，并将控制信号发送至第二芯片；第二芯片根据控制信号，向第一数据信号端提供信号。
本公开可以根据第一芯片对第一数据信号端进行外部补偿，可以提升显示基板的寿命，提升显示基板的显示效果。
本公开实施例还提供了一种显示装置，包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

  1. 一种像素电路，包括：驱动电路和发光元件，所述驱动电路和所述发光元件串联于第一电源端和第三电源端之间；所述驱动电路用于提供驱动电流，并控制所述第一电源端和第三电源端之间电流通路的导通时长；所述发光元件用于在所述电流通路中接收所述驱动电流，并发光；所述驱动电路包括：驱动控制子电路、发光控制子电路和时长控制子电路；
    所述驱动控制子电路，分别与第一扫描信号端、第一数据信号端、第一节点和第二节点电连接，设置为在第一扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流；
    所述发光控制子电路，分别与发光信号端、第一电源端和第二节点电连接，设置为在发光信号端的控制下，向第二节点提供第一电源端的信号；
    所述时长控制子电路，分别与第二扫描信号端、第二数据信号端、第二电源端、第一节点和第三节点电连接，设置为在第二扫描信号端和第二数据信号端的控制下，向第三节点提供第一节点的信号；
    所述发光元件，分别与第三节点和第三电源端电连接。
  2. 根据权利要求1所述的像素电路，其中，当所述第一扫描信号端的信号为有效电平信号时，所述第二扫描信号端的信号为有效电平信号，所述发光信号端为无效电平信号；
    当所述发光信号端的信号为有效电平信号时，所述第一扫描信号端和所述第二扫描信号端的信号为无效电平信号。
  3. 根据权利要求2所述的像素电路，其中，所述驱动控制子电路，还与第三扫描信号端电连接，设置为在第一扫描信号端、第三扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流；
    当所述第一扫描信号端的信号为有效电平信号时，第三扫描信号端的信号为有效电平信号；
    当所述发光信号端的信号为有效电平信号时，第三扫描信号端的信号为无效电平信号。
  4. 根据权利要求2或3所述的像素电路，还包括：复位子电路和/或节 点控制子电路；
    所述复位子电路，分别与复位信号端、初始信号端和第三节点电连接，设置为在复位信号端的控制下，向第三节点提供初始信号端的信号；
    所述节点控制子电路，分别与第一扫描信号端、控制信号端和第一节点电连接，设置为在第一扫描信号端的控制下，向第一节点提供控制信号端的信号，或者将第一节点的信号读取至控制信号端，其中，控制信号端的信号的电压值恒定。
  5. 根据权利要求4所述的像素电路，其中，当复位信号端的信号为有效电平信号时，所述第一扫描信号端、所述第二扫描信号端和所述发光信号端为无效电平信号；
    当所述第一扫描信号端的信号为有效电平信号时，所述复位信号端的信号为无效电平信号；
    当所述发光信号端的信号为有效电平信号时，所述复位信号端的信号为无效电平信号。
  6. 根据权利要求1所述的像素电路，其中，所述驱动控制子电路包括：第一晶体管、第二晶体管和第一电容；
    第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
    第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接。
  7. 根据权利要求3所述的像素电路，其中，所述驱动控制子电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容；
    第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
    第三晶体管的控制极与第三扫描信号端电连接，第三晶体管的第一极与第一数据信号端电连接，第三晶体管的第二极与第四节点电连接；
    第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；
    所述第二晶体管和所述第三晶体管的晶体管类型不同。
  8. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括：第四晶体管；
    第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接。
  9. 根据权利要求1所述的像素电路，其中，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容；
    第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
    第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
    第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接。
  10. 根据权利要求4所述的像素电路，其中，所述复位子电路包括：第七晶体管；
    第七晶体管的控制极与复位信号端电连接，第七晶体管的第一极与初始信号端电连接，第七晶体管的第二极与第三节点电连接。
  11. 根据权利要求4所述的像素电路，其中，节点控制子电路包括：第八晶体管；
    第八晶体管的控制极与第一扫描信号端电连接，第八晶体管的第一极与控制信号端电连接，第八晶体管的第二极与第一节点电连接。
  12. 根据权利要求1所述的像素电路，其中，所述驱动控制子电路包括：第一晶体管、第二晶体管和第一电容，所述发光控制子电路包括：第四晶体 管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容；
    第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
    第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接；
    第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
    第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
    第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；
    第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接。
  13. 根据权利要求1所述的像素电路，其中，所述驱动控制子电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容，所述发光控制子电路包括：第四晶体管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容；
    第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
    第三晶体管的控制极与第三扫描信号端电连接，第三晶体管的第一极与第一数据信号端电连接，第三晶体管的第二极与第四节点电连接；
    第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接；
    第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
    第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
    第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；
    第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接；
    所述第二晶体管和所述第三晶体管的晶体管类型相反。
  14. 根据权利要求1所述的像素电路，还包括：复位子电路和/或节点控制子电路，所述驱动控制子电路包括：第一晶体管、第二晶体管和第一电容，所述发光控制子电路包括：第四晶体管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容，所述复位子电路包括：第七晶体管，所述节点控制子电路包括：第八晶体管；
    第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
    第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接；
    第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
    第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
    第七晶体管的控制极与复位信号端电连接，第七晶体管的第一极与初始信号端电连接，第七晶体管的第二极与第三节点电连接；
    第八晶体管的控制极与第一扫描信号端电连接，第八晶体管的第一极与控制信号端电连接，第八晶体管的第二极与第一节点电连接；
    第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；当所述像素电路包括节点控制子电路时，第一电容的另一个极板与第一节点电连接；
    第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接。
  15. 根据权利要求1所述的像素电路，还包括：复位子电路和/或节点控制子电路，所述驱动控制子电路包括：第一晶体管、第二晶体管、第三晶体管和第一电容，所述发光控制子电路包括：第四晶体管，所述时长控制子电路包括：第五晶体管、第六晶体管和第二电容，所述复位子电路包括：第七晶体管，所述节点控制子电路包括：第八晶体管；
    第一晶体管的控制极与第四节点电连接，第一晶体管的第一极与第二节点电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一扫描信号端电连接，第二晶体管的第一极与第一数据信号端电连接，第二晶体管的第二极与第四节点电连接；
    第三晶体管的控制极与第三扫描信号端电连接，第三晶体管的第一极与第一数据信号端电连接，第三晶体管的第二极与第四节点电连接；
    第四晶体管的控制极与发光信号端电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第二节点电连接；
    第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一节点电连接，第五晶体管的第二极与第三节点电连接；
    第六晶体管的控制极与第二扫描信号端电连接，第六晶体管的第一极与第二数据信号端电连接，第六晶体管的第二极与第五节点电连接；
    第七晶体管的控制极与复位信号端电连接，第七晶体管的第一极与初始信号端电连接，第七晶体管的第二极与第三节点电连接；
    第八晶体管的控制极与第一扫描信号端电连接，第八晶体管的第一极与控制信号端电连接，第八晶体管的第二极与第一节点电连接；
    第一电容的一个极板与第四节点电连接，第一电容的另一个极板与第四电源端或者第一节点电连接；当所述像素电路包括节点控制子电路时，第一 电容的另一个极板与第一节点电连接；
    第二电容的一个极板与第五节点电连接，第二电容的另一个极板与第二电源端电连接；
    所述第二晶体管和所述第三晶体管的晶体管类型相反。
  16. 根据权利要求1所述的像素电路，其中，所述发光元件包括：微型发光二极管或者迷你发光二极管。
  17. 一种显示基板，包括：显示区域和围设在所述显示区域至少一侧的非显示区域，所述显示区域设置有多个像素，所述像素内设置有如权利要求1至16任一项所述的像素电路。
  18. 根据权利要求17所述的显示基板，其中，所述像素电路包括：节点控制子电路，所述显示基板还包括：与控制信号端连接的第一芯片和与第一数据信号端连接的第二芯片；
    所述第一芯片设置为在显示阶段向控制信号端提供信号，在非显示阶段读取控制信号端的信号，还设置在根据控制信号端的信号，获得第一晶体管的阈值电压，根据第一晶体管的阈值电压，生成控制信号，并将控制信号发送至所述第二芯片；
    所述第二芯片根据所述控制信号，向第一数据信号端提供信号。
  19. 一种显示装置，包括：如权利要求17或18所述的显示基板。
  20. 一种像素电路的驱动方法，设置为驱动如权利要求1至16任一项所述的像素电路，所述像素电路位于显示基板中，显示基板包括：显示阶段，所述显示阶段包括：多个显示帧，所述显示帧包括：至少一个显示子帧；所述显示子帧包括：发光数据写入阶段和发光阶段，所述方法包括：
    在发光数据写入阶段，驱动控制子电路在第一扫描信号端、第一数据信号端和第二节点的控制下，向第一节点提供驱动电流，时长控制子电路在第二扫描信号端和第二数据信号端的控制下，向第三节点提供第一节点的信号；
    在发光阶段，发光控制子电路在发光信号端的控制下，向第二节点提供第一电源端的信号。
  21. 根据权利要求20所述的方法，其中，所述像素电路还包括：复位子 电路，所述显示子帧还包括：复位阶段，所述方法还包括：
    在复位阶段，复位子电路在复位信号端的控制下，向第三节点提供初始信号端的信号。
  22. 根据权利要求20或21所述的方法，其中，所述像素电路还包括：节点控制子电路，所述显示基板还包括：非显示阶段，所述非显示阶段包括：补偿数据写入阶段和补偿阶段，所述方法还包括：
    在发光数据写入阶段和补偿数据写入阶段，节点控制子电路在第一扫描信号端的控制下，向第一节点提供控制信号端的信号；
    在补偿阶段，节点控制子电路在第一扫描信号端的控制下，将第一节点的信号读取至控制信号端。
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