WO2021175017A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2021175017A1
WO2021175017A1 PCT/CN2021/071512 CN2021071512W WO2021175017A1 WO 2021175017 A1 WO2021175017 A1 WO 2021175017A1 CN 2021071512 W CN2021071512 W CN 2021071512W WO 2021175017 A1 WO2021175017 A1 WO 2021175017A1
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Prior art keywords
light
emitting
transistor
sub
circuit
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PCT/CN2021/071512
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English (en)
French (fr)
Inventor
陈亮
刘冬妮
肖丽
玄明花
郑皓亮
张振宇
陈昊
赵蛟
齐琪
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京东方科技集团股份有限公司
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Priority to US17/424,176 priority Critical patent/US11763743B2/en
Publication of WO2021175017A1 publication Critical patent/WO2021175017A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/088—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element
    • G09G2300/0895—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element having more than one selection line for a two-terminal active matrix LCD, e.g. Lechner and D2R circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a pixel circuit, a driving method thereof, and a display device.
  • Micro Light Emitting Diode (Micro LED) technology is to realize the thin-film, miniaturization and matrixing of LEDs by high-density integration of micro-sized LED arrays on a chip.
  • the distance between the pixels can reach micrometers.
  • Level, and each pixel can be addressed and emit light individually.
  • Micro LED display panels have gradually developed into display panels used in consumer terminals due to their low driving voltage, long life, and wide temperature resistance.
  • the pixel circuit is electrically connected to the Micro LED to drive the Micro LED to emit light.
  • the gray scale is usually adjusted by the current and the light-emitting time.
  • adjusting the gray scale by the current will make the low gray scale correspond to the low current density, and its efficiency will decrease, and as the current density increases Changes, the color coordinates of the Micro LED will change, that is, the color shift of the Micro LED will occur when the gray scale changes. Relying on reducing the light-emitting time to adjust the gray scale will easily cause screen flicker, which will affect the display effect of the display panel.
  • the embodiment of the present disclosure provides a pixel circuit, including: a current control sub-circuit, a combined light-emitting sub-circuit, a first light-emitting element to an N-th light-emitting element, N is a natural number greater than 1, wherein: the current control sub-circuit is It is configured to receive the display data signal and the light-emitting control signal, control whether to generate a driving current according to the light-emitting control signal, and control the current intensity of the generated driving current according to the display data signal; the combined light-emitting sub-circuit is configured to receive the driving current and the first The light-emitting data signal to the Nth light-emitting data signal, and one or more of the first light-emitting element to the Nth light-emitting element are driven to emit light according to the received driving current and the first light-emitting data signal to the Nth light-emitting data signal.
  • the combined light-emitting sub-circuit includes a first light-emitting sub-circuit and a second light-emitting sub-circuit, and the driving current is divided into a first driving current for driving a first light-emitting element and a first driving current for driving a second light-emitting element.
  • the second driving current of the two light-emitting elements wherein: the first light-emitting sub-circuit is respectively connected to the reset control signal terminal, the first light-emitting data signal terminal and the first light-emitting element, and is configured to receive the first driving current, and is configured to receive the first driving current.
  • the first light-emitting element Under the control of the control signal terminal and the first light-emitting data signal terminal, the first light-emitting element is driven to emit light or the first light-emitting element is controlled not to emit light;
  • the second light-emitting sub-circuit is connected to the first scan signal terminal and the second light-emitting data signal terminal It is connected to the second light-emitting element and is configured to receive a second driving current, and under the control of the first scan signal terminal and the second light-emitting data signal terminal, drive the second light-emitting element to emit light or control the second light-emitting element not to emit light.
  • the first light-emitting sub-circuit includes a first transistor, a second transistor, and a first capacitor
  • the second light-emitting sub-circuit includes a third transistor, a fourth transistor, and a second capacitor
  • the control electrode of the first transistor is connected to the second node, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the first light-emitting element
  • the second transistor The control electrode of the second transistor is connected to the reset control signal terminal, the first electrode of the second transistor is connected to the first light-emitting data signal terminal, and the second electrode of the second transistor is connected to the second node
  • one end of the first capacitor Connected to the second node, the other end of the first capacitor is connected to the common voltage terminal
  • the control electrode of the third transistor is connected to the third node, and the first electrode of the third transistor is connected to the first node
  • the second electrode of the third transistor is connected to the second light-emitting element
  • the current control sub-circuit is further configured to control the duration of the generated driving current according to the light-emitting control signal; the combined light-emitting sub-circuit is further configured to, according to the duration of the generated driving current, Control the light-emitting duration from the first light-emitting element to the Nth light-emitting element.
  • the combined light-emitting sub-circuit includes a third light-emitting sub-circuit and a fourth light-emitting sub-circuit, and the driving current is divided into a first driving current for driving the first light-emitting element and a first driving current for driving the first light-emitting element.
  • the second driving current of the two light-emitting elements wherein: the third light-emitting sub-circuit is respectively connected to the second scan signal terminal, the first light-emitting data signal terminal and the first light-emitting element, and is configured to receive the first driving current, Under the control of the second scan signal terminal and the first light-emitting data signal terminal, the first light-emitting element is driven to emit light, and the light-emitting duration of the first light-emitting element is controlled according to the duration of the first driving current, or the first light-emitting element is controlled not to emit light;
  • the fourth light-emitting sub-circuit is respectively connected to the third scan signal terminal, the second light-emitting data signal terminal and the second light-emitting element, and is configured to receive the second driving current, and is controlled at the third scan signal terminal and the second light-emitting data signal terminal
  • the second light-emitting element is driven to emit light, and according to the time length of the second driving current, the light-emitting
  • the third light-emitting sub-circuit includes a first transistor, a fifth transistor, and a first capacitor
  • the fourth light-emitting sub-circuit includes a third transistor, a sixth transistor, and a second capacitor, wherein: The control electrode of the first transistor is connected to the second node, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the first light-emitting element; the fifth transistor The control electrode of the fifth transistor is connected to the second scan signal terminal, the first electrode of the fifth transistor is connected to the first light-emitting data signal terminal, and the second electrode of the fifth transistor is connected to the second node; One end is connected to the second node, the other end of the first capacitor is connected to the common voltage end; the control electrode of the third transistor is connected to the third node, and the first electrode of the third transistor is connected to the first node Connected, the second electrode of the third transistor is connected to the second light-emitting element; the control electrode of
  • the current control sub-circuit includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a reset sub-circuit, and a light emission control sub-circuit.
  • the node, the fifth node, and the sixth node are connected, and are configured to provide a driving current to the sixth node under the control of the signals of the fourth node and the fifth node;
  • the writing sub-circuit is connected to the first scan signal terminal, respectively ,
  • the display data signal terminal and the fifth node are connected, and are configured to write the signal of the display data signal terminal into the fifth node under the control of the signal of the first scan signal terminal;
  • the compensation sub-circuit is connected to the first voltage terminal,
  • the first scan signal terminal, the fourth node, and the sixth node are connected, and are configured to compensate the fourth node under the control of the signal of the first scan signal terminal and the signal of the first voltage terminal;
  • the reset sub-circuit is respectively connected to the reset The control signal terminal,
  • the driving sub-circuit includes a seventh transistor
  • the compensation sub-circuit includes an eighth transistor and a third capacitor
  • the reset sub-circuit includes a ninth transistor
  • the writing sub-circuit includes a first transistor.
  • the light emission control sub-circuit includes an eleventh transistor and a twelfth transistor, wherein: the control electrode of the seventh transistor is connected to the fourth node, and the first electrode of the seventh transistor is connected to the fifth node , The second electrode of the seventh transistor is connected to the sixth node; the control electrode of the eighth transistor is connected to the first scanning signal terminal, the first electrode of the eighth transistor is connected to the fourth node, and the first electrode of the eighth transistor is connected to the fourth node.
  • the second electrode of the eight transistor is connected to the sixth node; one end of the third capacitor is connected to the fourth node, and the other end of the third capacitor is connected to the first voltage terminal;
  • the control electrode is connected to the reset control signal terminal, the first electrode of the ninth transistor is connected to the initial voltage terminal, the second electrode of the ninth transistor is connected to the fourth node; the control electrode of the tenth transistor is connected to the first
  • the scan signal terminal is connected, the first electrode of the tenth transistor is connected to the display data signal terminal, the second electrode of the tenth transistor is connected to the fifth node;
  • the control electrode of the eleventh transistor and the light emitting control signal terminal Connected, the first electrode of the eleventh transistor is connected to the first voltage terminal, the second electrode of the eleventh transistor is connected to the fifth node;
  • the control electrode of the twelfth transistor is connected to the light emitting control signal terminal ,
  • the first pole of the twelfth transistor is connected to the sixth node, and the second pole of the
  • An embodiment of the present disclosure also provides a display device, including: the pixel circuit described above.
  • the embodiment of the present disclosure also provides a driving method of a pixel circuit, which is used to drive the above-mentioned pixel circuit.
  • the pixel circuit has a plurality of scanning periods.
  • the driving method includes: a current control sub
  • the circuit receives the display data signal and the light-emitting control signal, controls whether to generate a driving current according to the light-emitting control signal, and controls the current intensity of the generated driving current according to the display data signal;
  • the combined light-emitting sub-circuit receives the driving current and the first light-emitting data signal to the Nth light-emitting
  • the data signal drives one or more of the first light-emitting element to the N-th light-emitting element to emit light according to the received driving current, the first light-emitting data signal to the Nth light-emitting data signal.
  • the driving method further includes: the current control sub-circuit controls the duration of the generated driving current according to the light emission control signal; the combined light-emitting sub-circuit controls the first duration according to the duration of the generated driving current.
  • the light-emitting time from the light-emitting element to the Nth light-emitting element.
  • FIG. 1 is one of the structural schematic diagrams of a pixel circuit provided by an embodiment of the disclosure
  • FIG. 2 is the second structural diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 3 is one of the equivalent circuit diagrams of the combined light-emitting sub-circuit provided by an embodiment of the disclosure
  • FIG. 4 is a schematic structural diagram of a current control sub-circuit provided by an embodiment of the disclosure.
  • FIG. 5 is an equivalent circuit diagram of a current control sub-circuit provided by an embodiment of the disclosure.
  • FIG. 6 is one of the equivalent circuit diagrams of the pixel circuit provided by the embodiments of the disclosure.
  • FIG. 7 is a working timing diagram of the pixel circuit shown in FIG. 6 in one scanning period
  • FIG. 8 is the third structural diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 11 is a working timing diagram of the pixel circuit shown in FIG. 10 in one scanning period
  • FIG. 12 is one of the flowcharts of the driving method of the pixel circuit provided by the embodiments of the disclosure.
  • FIG. 13 is the second flowchart of the driving method of the pixel circuit provided by the embodiment of the disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the thin film transistor used in the embodiment of the present disclosure may be an oxide semiconductor transistor. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged.
  • one of the electrodes is called the first pole, and the other is called the second pole.
  • the first pole can be a source or a drain
  • the second The electrode can be a drain or a source.
  • FIG. 1 is a schematic structural diagram of the pixel circuit of the embodiment of the present disclosure.
  • the pixel circuit provided by the embodiment of the present disclosure includes: a current control subcircuit, a combined light emitting subcircuit, and From the first light-emitting element EL1 to the N-th light-emitting element ELN, N is a natural number greater than one.
  • the current control sub-circuit is respectively connected to the first voltage terminal VDD, the display data signal terminal DataI, the light emission control signal terminal EM and the first node N1, and is configured to receive the display data signal and the light emission control signal terminal of the display data signal terminal DataI
  • the EM light-emitting control signal controls whether to generate a driving current according to the light-emitting control signal, and controls the current intensity of the generated driving current according to the display data signal.
  • the combined light-emitting sub-circuit is respectively connected to the first node N1, the first light-emitting data signal terminal DataS(1) to the Nth light-emitting data signal terminal DataS(N), the first light-emitting element EL1 to the Nth light-emitting element ELN, and is configured to receive The driving current of the current control sub-circuit and the first light-emitting data signal of the first light-emitting data signal terminal DataS(1) to the Nth light-emitting data signal of the Nth light-emitting data signal terminal DataS(N), according to the received driving current, the first light-emitting data signal
  • the light emitting data signal to the Nth light emitting data signal drive one or more of the first light emitting element EL1 to the Nth light emitting element ELN to emit light.
  • the first light-emitting data signal may be configured to control whether the first light-emitting element EL1 emits light
  • the second light-emitting data signal may be configured to control whether the second light-emitting element EL2 emits light
  • the Nth light-emitting data signal It may be configured to control whether the Nth light emitting element ELN emits light. For example, when the i-th light-emitting data signal is at a low level, the i-th light-emitting element ELi emits light, and i is a natural number between 1 and N.
  • the pixel circuit provided by the embodiment of the present disclosure drives one or more of the first light-emitting element EL1 to the N-th light-emitting element ELN by combining the light-emitting sub-circuit according to the received driving current, the first light-emitting data signal to the Nth light-emitting data signal Emitting, realizing the combination of light-emitting element chips of different areas to emit light, thereby improving the display effect of the display device under high and low gray levels.
  • the pixel circuit of the embodiment of the present disclosure can be implemented through a variety of solutions.
  • the technical solutions of the embodiments of the present disclosure will be described in detail below through a number of embodiments.
  • the first light-emitting element EL1 emits light.
  • the area may be smaller than the light-emitting area of the second light-emitting element EL2 to achieve a combined light-emitting effect of different areas.
  • the structure of the pixel circuit provided in this embodiment is also applicable when N is other values.
  • N 3 or more
  • the sub-circuit is connected to the first scanning signal terminal GateA, and M is a natural number between 1 and N-1.
  • FIG. 2 is a schematic diagram of a structure of a pixel circuit according to an embodiment of the disclosure.
  • the combined light-emitting sub-circuit includes a first light-emitting sub-circuit and a second light-emitting sub-circuit.
  • the driving current is divided into a first driving current configured to drive the first light-emitting element EL1 and a second light-emitting sub-circuit configured to drive the The second drive current of the element EL2.
  • the first light-emitting sub-circuit is respectively connected to the first node N1, the reset control signal terminal Reset, the first light-emitting data signal terminal DataS(1) and the first light-emitting element EL1, and is configured to receive the first driving current, and is configured to receive the first driving current.
  • the first light-emitting element EL1 Under the control of the reset signal of the signal terminal Reset and the first light-emitting data signal of the first light-emitting data signal terminal DataS(1), the first light-emitting element EL1 is driven to emit light or the first light-emitting element EL1 is controlled to not emit light.
  • the second light-emitting sub-circuit is respectively connected to the first node N1, the first scan signal terminal GateA, the second light-emitting data signal terminal DataS(2), and the second light-emitting element EL2, and is configured to receive the second driving current.
  • the second light-emitting element EL2 Under the control of the first scan signal of the signal terminal GateA and the second light-emitting data signal of the second light-emitting data signal terminal DataS(2), the second light-emitting element EL2 is driven to emit light or the second light-emitting element EL2 is controlled to not emit light.
  • the driving current corresponding to the light-emitting element branch that does not emit light is zero, for example, when the first light-emitting element EL1 emits light.
  • the current value of the second driving current is zero, and the current value of the first driving current is equal to the current value of the driving current.
  • the first light-emitting sub-circuit provided by an embodiment of the present disclosure includes a first transistor T1, a second transistor T2, and a first capacitor C1
  • the second light-emitting sub-circuit includes a third transistor. T3, the fourth transistor T4 and the second capacitor C2.
  • the control electrode of the first transistor T1 is connected to the second node N2, the first electrode of the first transistor T1 is connected to the first node N1, the second electrode of the first transistor T1 is connected to the anode of the first light-emitting element EL1,
  • the cathode of a light-emitting element EL1 is connected to the second voltage terminal VSS;
  • the control electrode of the second transistor T2 is connected to the reset control signal terminal Reset, and the first electrode of the second transistor T2 is connected to the first light-emitting data signal terminal DataS(1)
  • the second electrode of the second transistor T2 is connected to the second node N2; one end of the first capacitor C1 is connected to the second node N2, the other end of the first capacitor C1 is connected to the common voltage terminal VCOM;
  • the control electrode of the third transistor T3 is connected to The third node N3 is connected, the first electrode of the third transistor T3 is connected to the first node N1, the second electrode of the third transistor T3 is connected to the ano
  • FIG. 3 shows an exemplary structure of the first light-emitting sub-circuit and the second light-emitting sub-circuit. It is easily understood by those skilled in the art that the implementation of the first light-emitting sub-circuit and the second light-emitting sub-circuit are not limited to this, as long as they can achieve their respective functions.
  • the current control sub-circuit provided by the embodiment of the present disclosure includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a reset sub-circuit, and a light emission control sub-circuit.
  • the driving sub-circuit is respectively connected to the fourth node N4, the fifth node N5, and the sixth node N6, and is configured to provide a driving current to the sixth node N6 under the control of the signals of the fourth node N4 and the fifth node N5
  • the write sub-circuit is respectively connected to the first scan signal terminal GateA, the display data signal terminal DataI and the fifth node N5, and is configured to display the data signal terminal under the control of the first scan signal of the first scan signal terminal GateA
  • the display data signal of DataI is written into the fifth node N5;
  • the compensation sub-circuit is respectively connected to the first voltage terminal VDD, the first scan signal terminal GateA, the fourth node N4, and the sixth node N6, and is configured to be at the first scan signal terminal
  • the fourth node N4 is compensated under the control of the first scan signal of GateA and the first voltage signal of the first voltage terminal VDD;
  • the reset sub-circuit is respectively connected to the reset control signal terminal Reset, the initial voltage terminal Vin
  • the driving sub-circuit includes a seventh transistor T7
  • the compensation sub-circuit includes an eighth transistor T8 and a third capacitor C3
  • the reset sub-circuit includes a ninth transistor T9
  • the writing sub-circuit It includes a tenth transistor T10
  • the light emission control sub-circuit includes an eleventh transistor T11 and a twelfth transistor T12.
  • the control electrode of the seventh transistor T7 is connected to the fourth node N4, the first electrode of the seventh transistor T7 is connected to the fifth node N5, and the second electrode of the seventh transistor T7 is connected to the sixth node N6; the eighth transistor T8 The control electrode of the eighth transistor T8 is connected to the first scan signal terminal GateA, the first electrode of the eighth transistor T8 is connected to the fourth node N4, and the second electrode of the eighth transistor T8 is connected to the sixth node N6; one end of the third capacitor C3 is connected to the The four-node N4 is connected, the other end of the third capacitor C3 is connected to the first voltage terminal VDD; the control electrode of the ninth transistor T9 is connected to the reset control signal terminal Reset, and the first electrode of the ninth transistor T9 is connected to the initial voltage terminal Vinit, The second electrode of the ninth transistor T9 is connected to the fourth node N4; the control electrode of the tenth transistor T10 is connected to the first scanning signal terminal GateA, the first electrode of the tenth transistor T10 is
  • FIG. 5 shows an exemplary structure of the driving sub-circuit, the writing sub-circuit, the compensation sub-circuit, the reset sub-circuit, and the light emission control sub-circuit.
  • the combined light-emitting sub-circuit includes a first light-emitting sub-circuit and a second light-emitting sub-circuit.
  • the control sub-circuit includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a reset sub-circuit, and a light-emitting control sub-circuit.
  • the first light-emitting sub-circuit includes a first transistor T1, a second transistor T2, and a first capacitor C1.
  • the light-emitting sub-circuit includes a third transistor T3, a fourth transistor T4 and a second capacitor C2, the driving sub-circuit includes a seventh transistor T7, the compensation sub-circuit includes an eighth transistor T8 and a third capacitor C3, and the reset sub-circuit includes a ninth transistor T9.
  • the writing sub-circuit includes a tenth transistor T10, and the light-emitting control sub-circuit includes an eleventh transistor T11 and a twelfth transistor T12.
  • the control electrode of the first transistor T1 is connected to the second node N2, the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the anode terminal of the first light-emitting element EL1,
  • the cathode terminal of the first light-emitting element EL1 is connected to the second voltage terminal VSS;
  • the control electrode of the second transistor T2 is connected to the reset control signal terminal Reset, and the first electrode of the second transistor T2 is connected to the first light-emitting data signal terminal DataS(1) Connected, the second pole of the second transistor T2 is connected to the second node N2; one end of the first capacitor C1 is connected to the second node N2, the other end of the first capacitor C1 is connected to the common voltage terminal VCOM;
  • the control of the third transistor T3 The electrode is connected to the third node N3, the first electrode of the third transistor T3 is connected to the first node N1, the second electrode of the third transistor T3 is connected to
  • Fig. 6 shows an exemplary structure of a combined light-emitting sub-circuit and a current control sub-circuit. It is easily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their respective functions can be realized.
  • the light-emitting element EL (including the first light-emitting element EL1 to the N-th light-emitting element ELN) may be a micro light-emitting diode, or a sub-millimeter light-emitting diode (Mini LED), or an organic light-emitting diode (Organic Light Emitting Diode). OLED) and other types of light-emitting diodes.
  • the structure of the light-emitting element EL can be designed and determined according to the actual application environment, which is not limited here.
  • the light emitting element EL is a micro light emitting diode as an example.
  • the first transistor T1 to the fourth transistor T4 and the seventh transistor T7 to the twelfth transistor T12 can be N-type thin film transistors or P-type thin film transistors. All transistors use the same type of thin film transistors, which can be unified The technological process, reducing the technological process, helps to improve the yield of the product. In addition, considering the low leakage current of low-temperature polysilicon thin-film transistors, all transistors in the embodiments of the present disclosure may be low-temperature polysilicon thin-film transistors.
  • the thin-film transistors may be thin-film transistors with a bottom-gate structure or a top-gate structure, as long as they can be implemented. Just switch function.
  • the first capacitor C1 to the third capacitor C3 may be liquid crystal capacitors composed of pixel electrodes and common electrodes, or equivalent capacitors composed of liquid crystal capacitors composed of pixel electrodes and common electrodes and storage capacitors. This disclosure does not limit this.
  • FIG. 7 is a working timing diagram of the pixel circuit of this embodiment. While the current control sub-circuit completes threshold voltage compensation, the combined light-emitting sub-circuit adjusts the light-emitting data signal DataS of the first light-emitting element EL1 and the second light-emitting element EL2 through timing control.
  • (1) and DataS(2) are transferred to the first capacitor C1 and the second capacitor C2, and the combined light emission of the first light-emitting element EL1 and the second light-emitting element EL2 is completed in a time, wherein the first light-emitting data signal DataS(1 ) And the signal value of the second light-emitting data signal DataS(2) can be high or low, and the first transistors T1 and T1 and T1 are controlled by the first light-emitting data signal DataS(1) and the second light-emitting data signal DataS(2).
  • the third transistor T3 is turned on and off.
  • the pixel circuit provided by the embodiment of the present disclosure includes 10 transistor units (T1 to T4, T7 to T12), 3 capacitor units (C1 to C3) and three voltage terminals (VDD, VSS, VCOM) , Wherein the first voltage terminal VDD continuously provides a high-level signal, the second voltage terminal VSS continuously provides a low-level signal, and the common voltage terminal VCOM is grounded. Its working process includes:
  • the reset stage the reset control signal terminal Reset is pulled low, the ninth transistor T9 is turned on, and the gate of the seventh transistor T7 and one end of the third capacitor C3 (ie the fourth node N4) are reset to the initial voltage
  • the second transistor T2 is turned on, the first light-emitting data signal of the first light-emitting data signal terminal DataS(1) is transmitted to one end of the first capacitor C1 and the gate of the first transistor T1, and the second transistor T1 is controlled A switch of transistor T1;
  • the second stage t2 is the threshold voltage compensation and display data reading stage.
  • the voltage of the first scan signal terminal GateA is pulled down, the tenth transistor T10, the seventh transistor T7, and the eighth transistor T8 are turned on to display the data signal terminal
  • the display data signal of DataI is input, and the display data signal and the threshold voltage (VdataI+Vth) are stored on the third capacitor C3; at the same time, the fourth transistor T4 is turned on, and the second light-emitting data signal terminal DataS(2)
  • the light-emitting data signal is transmitted to the gate of the second capacitor C2 and the third transistor T3 to control the switching of the third transistor T3;
  • the light-emitting control signal terminal EM is set to low level, and the eleventh transistor T11 and the twelfth transistor T12 are in the conducting state, which is determined according to the switching states of the first transistor T1 and the third transistor T3
  • the working states of the first light-emitting elements EL1 and EL2 for example, when the first light-emitting data signal terminal DataS(1) is at a low level, the first transistor T1 is turned on, and the first light-emitting element EL1 is in the working state.
  • the first light-emitting data signal terminal DataS(1) is at low level
  • the second light-emitting data signal terminal DataS(2) is at high level.
  • the small area The Micro LED chip EL1 works, and the large-area Micro LED chip EL2 is disconnected; when a sub-pixel displays a low-gray-scale picture, the first light-emitting data signal terminal DataS(1) is low, and the second light-emitting data signal terminal DataS (2) It is low level.
  • the Micro LED chips EL1 and EL2 are both in working state.
  • the enhanced grayscale display effect is achieved by selecting a combination of light emitting elements of different areas to emit light.
  • this embodiment introduces two independent sets of scanning signals GOA: GateA and GateB( Among them, GateB includes GateB(1) and GateB(2)), which can not only choose the combination of chips of different areas, but also choose different light-emitting time periods of the chips in one frame of display.
  • the current control sub-circuit is further configured to control the duration of the generated driving current according to the light-emitting control signal; the combined light-emitting sub-circuit is also configured to control the first light-emitting element EL1 according to the duration of the generated driving current The light-emitting time to the Nth light-emitting element ELN.
  • the pixel circuit provided by the embodiment of the present disclosure drives one of the first light-emitting element EL1 to the N-th light-emitting element ELN by combining the light-emitting sub-circuit according to the duration of the generated driving current and the received first light-emitting data signal to the Nth light-emitting data signal.
  • One or more light-emitting elements and their light-emitting durations realize the combination of light-emitting element chips with different areas and different light-emitting durations, thereby further improving the display effect of the display device under high and low gray levels.
  • the first light-emitting element EL1 The light-emitting area may be smaller than the light-emitting area of the second light-emitting element EL2 to achieve a combined light-emitting effect of different areas.
  • the structure of the pixel circuit provided in this embodiment is also applicable when N is other values.
  • the light-emitting sub-circuit where the i-th light-emitting element is located is connected to the (i+1)-th scanning signal terminal GateB(i) and the i-th light-emitting data signal terminal DataS(i), and i is 1 to A natural number between N.
  • FIG. 8 is a schematic diagram of another structure of a pixel circuit according to an embodiment of the disclosure.
  • the combined light-emitting sub-circuit includes a third light-emitting sub-circuit and a fourth light-emitting sub-circuit, and the driving current is divided into a first driving current for driving the first light-emitting element EL1 and a second light-emitting element EL2.
  • the second drive current is divided into a first driving current for driving the first light-emitting element EL1 and a second light-emitting element EL2.
  • the third light-emitting sub-circuit is respectively connected to the first node N1, the second scan signal terminal GateB(1), the first light-emitting data signal terminal DataS(1) and the first light-emitting element EL1, and is configured to receive the first driving current .
  • the first light emitting element EL1 Under the control of the second scan signal of the second scan signal terminal GateB(1) and the first light emission data signal of the first light emission data signal terminal DataS(1), the first light emitting element EL1 is driven to emit light according to the first driving current Control the light-emitting duration of the first light-emitting element EL1, or control the first light-emitting element EL1 not to emit light.
  • the fourth light-emitting sub-circuit is respectively connected to the first node N1, the third scan signal terminal GateB(2), the second light-emitting data signal terminal DataS(2), and the second light-emitting element EL2, and is configured to receive the second driving current.
  • the second light-emitting element EL2 Under the control of the third scan signal of the third scan signal terminal GateB(2) and the second emission data signal of the second emission data signal terminal DataS(2), the second light-emitting element EL2 is driven to emit light, and according to the second driving current Duration, control the light-emitting duration of the second light-emitting element EL2, or control the second light-emitting element EL2 not to emit light.
  • the driving current corresponding to the light-emitting element branch that does not emit light is zero, for example, when the first light-emitting element EL1 emits light.
  • the current value of the second driving current is zero, and the current value of the first driving current is equal to the current value of the driving current.
  • the third light-emitting sub-circuit provided by the embodiments of the present disclosure includes a first transistor T1, a fifth transistor T5, and a first capacitor C1, and the second light-emitting sub-circuit includes a third transistor. T3, the sixth transistor T6 and the second capacitor C2.
  • the control electrode of the first transistor T1 is connected to the second node N2, the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the anode terminal of the first light-emitting element EL1,
  • the cathode terminal of the first light-emitting element EL1 is connected to the second voltage terminal VSS;
  • the control electrode of the fifth transistor T5 is connected to the second scan signal terminal GateB(1), and the first electrode of the fifth transistor T5 is connected to the first light-emitting data signal terminal DataS(1) is connected, the second electrode of the fifth transistor T5 is connected to the second node N2; one end of the first capacitor C1 is connected to the second node N2, and the other end of the first capacitor C1 is connected to the common voltage terminal VCOM;
  • third The control electrode of the transistor T3 is connected to the third node N3, the first electrode of the third transistor T3 is connected to the first node N1, the second electrode of the third transistor T3 is connected to
  • FIG. 9 shows an exemplary structure of the third light-emitting sub-circuit and the fourth light-emitting sub-circuit. It is easily understood by those skilled in the art that the implementation of the third light-emitting sub-circuit and the fourth light-emitting sub-circuit are not limited to this, as long as their respective functions can be realized.
  • the current control sub-circuit of this embodiment can adopt the same structure as the current control sub-circuit of the previous embodiment, and will not be repeated here.
  • FIG. 10 is another equivalent circuit diagram of the pixel circuit provided by the embodiment of the disclosure.
  • the combined light-emitting sub-circuit includes a first light-emitting sub-circuit and a second light-emitting sub-circuit
  • the current control sub-circuit includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a reset sub-circuit, and a light-emitting control sub-circuit.
  • the first light-emitting sub-circuit includes a first transistor T1, a fifth transistor T5 and a first capacitor C1
  • the second light-emitting sub-circuit includes a third transistor T3, a sixth transistor T6 and a second capacitor C2
  • the driving sub-circuit includes a seventh transistor T7
  • the compensation sub-circuit includes an eighth transistor T8 and a third capacitor C3
  • the reset sub-circuit includes a Nine transistors T9
  • the writing sub-circuit includes a tenth transistor T10
  • the light emission control sub-circuit includes an eleventh transistor T11 and a twelfth transistor T12.
  • the control electrode of the first transistor T1 is connected to the second node N2, the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the anode terminal of the first light-emitting element EL1,
  • the cathode terminal of the first light-emitting element EL1 is connected to the second voltage terminal VSS;
  • the control electrode of the fifth transistor T5 is connected to the second scan signal terminal GateB(1), and the first electrode of the fifth transistor T5 is connected to the first light-emitting data signal terminal DataS(1) is connected, the second electrode of the fifth transistor T5 is connected to the second node N2; one end of the first capacitor C1 is connected to the second node N2, and the other end of the first capacitor C1 is connected to the common voltage terminal VCOM;
  • third The control electrode of the transistor T3 is connected to the third node N3, the first electrode of the third transistor T3 is connected to the first node N1, the second electrode of the third transistor T3 is connected to
  • FIG. 10 shows an exemplary structure of a combined light-emitting sub-circuit and a current control sub-circuit. It is easily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their respective functions can be realized.
  • the light-emitting element EL (including the first light-emitting element EL1 to the N-th light-emitting element ELN) may be micro light-emitting diodes, or other types of light-emitting diodes such as sub-millimeter light-emitting diodes and organic light-emitting diodes.
  • the structure of the light-emitting element EL can be designed and determined according to the actual application environment, which is not limited here.
  • the light emitting element EL is a micro light emitting diode as an example.
  • the first transistor T1, the third transistor T3, and the fifth transistor T5 to the twelfth transistor T12 can all be N-type thin film transistors or P-type thin film transistors, which can unify the process flow, reduce the number of processes, and help To improve the yield of products.
  • all transistors in the embodiments of the present disclosure may be low-temperature polysilicon thin-film transistors.
  • the thin-film transistors may be thin-film transistors with a bottom-gate structure or a top-gate structure, as long as they can be implemented. Just switch function.
  • the first capacitor C1 to the third capacitor C3 can be liquid crystal capacitors composed of a pixel electrode and a common electrode, or can be equivalent capacitors composed of a liquid crystal capacitor composed of a pixel electrode and a common electrode and a storage capacitor. There is no limit to this publicly.
  • the working process of the first-level pixel circuit is taken as an example, and the technical solution of the embodiment of the present disclosure is explained through the working process of the pixel circuit.
  • the pixel circuit provided by the embodiment of the present disclosure includes 10 transistor units (T1, T3, T5 ⁇ T12), 3 capacitor units (C1 ⁇ C3) and 3 voltage terminals (VDD, VSS, VCOM) , Wherein the first voltage terminal VDD continuously provides a high-level signal, the second voltage terminal VSS continuously provides a low-level signal, and the common voltage terminal VCOM is grounded. Its working process includes:
  • the reset stage the reset control signal terminal Reset is pulled low, the ninth transistor T9 is turned on, and the gate of the seventh transistor T7 and one end of the third capacitor C3 (ie the fourth node N4) are reset to the initial voltage The initial voltage of the terminal Vinit; at the same time, the second scan signal terminal GateB(1) is at low level, the second transistor T2 is turned on, and the first light-emitting data signal of the first light-emitting data signal terminal DataS(1) is transferred to the first capacitor One end of C1 and the gate of the first transistor T1 control the switching of the first transistor T1;
  • the second stage t2 is the threshold voltage compensation and display data reading stage.
  • the voltage of the first scan signal terminal GateA is pulled down, the tenth transistor T10, the seventh transistor T7 and the eighth transistor T8 are turned on, and the display data signal terminal DataI
  • the display data signal is input, and the display data signal and the threshold voltage (VdataI+Vth) are stored on the third capacitor C3; at the same time, the third scan signal terminal GateB (2) is at low level, and the fourth transistor T4 is turned on,
  • the second light-emitting data signal of the second light-emitting data signal terminal DataS(2) is transmitted to the second capacitor C2 and the gate of the third transistor T3 to control the switching of the third transistor T3;
  • the light-emitting control signal terminal EM is given the low level time time1, and the light-emitting control signal terminal EM is high during the remaining (t3-time1) time.
  • the eleventh transistor T11 and the twelfth transistor T12 are in the on state, and the light-emitting state of the first light-emitting elements EL1 and EL2 is determined according to the switching state of the first transistor T1 and the third transistor T3, For example, when the first light-emitting data signal terminal DataS(1) is at a low level, the first transistor T1 is turned on, the first light-emitting element EL1 is in a light-emitting state, and the light-emitting duration is time1.
  • the fourth stage t4 the first light-emitting data input stage, the second scan signal terminal GateB(1) is at low level, the second transistor T2 is turned on, and the first light-emitting data signal of the first light-emitting data signal terminal DataS(1) To one end of the first capacitor C1 and the gate of the first transistor T1 to control the switching of the first transistor T1;
  • the third scan signal terminal GateB(2) is at low level, the fourth transistor T4 is turned on, and the second light-emitting data signal of the second light-emitting data signal terminal DataS(2) To the gate of the second capacitor C2 and the third transistor T3 to control the switching of the third transistor T3;
  • the light-emitting control signal terminal EM is given a low level time time2, and the light-emitting control signal terminal EM is at a high level during the remaining (t6-time2) time.
  • the eleventh transistor T11 and the twelfth transistor T12 are in the conducting state, and the light-emitting states of the first light-emitting elements EL1 and EL2 are determined according to the switching states of the first transistor T1 and the third transistor T3.
  • the third transistor T3 is turned on, the second light-emitting element EL2 is in a light-emitting state, and the light-emitting duration is time2.
  • the working process of the seventh phase t7 is the same as the fourth phase t4, the working process of the eighth phase t8 is the same as the fifth phase t5, and the working process of the ninth phase t9 is the same as the sixth phase t6.
  • the small area first light-emitting element EL1 can be used to emit light for time1 time; for high gray levels, the first light-emitting element EL1 and the second light-emitting element EL2 can emit light at the same time (time1 +time2+time3) time.
  • An embodiment of the present disclosure also provides a display device, including the pixel circuit described in any of the foregoing embodiments.
  • the display device of the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure also provides a method for driving a pixel circuit, which is used to drive the pixel circuit that controls whether to generate a driving current according to the light emission control signal as described in the previous embodiment.
  • the pixel circuit has a plurality of scanning periods. In the scan period, as shown in FIG. 12, the driving method includes step 100 to step 200.
  • step 100 includes: the current control sub-circuit receives the display data signal and the light emission control signal, controls whether to generate a driving current according to the light emission control signal, and controls the current intensity of the generated driving current according to the display data signal.
  • step 100 includes:
  • the reset sub-circuit discharges the third capacitor under the control of the reset signal
  • the writing sub-circuit and the compensating sub-circuit store the display data signal and the threshold voltage on the third capacitor under the control of the first scan signal;
  • the lighting control sub-circuit is turned on under the control of the lighting control signal, and the driving current generated by the driving sub-circuit is provided to the combined lighting sub-circuit via the lighting control sub-circuit.
  • Step 200 includes: the combined light-emitting sub-circuit receives the driving current and the first light-emitting data signal to the Nth light-emitting data signal, and drives one of the first light-emitting element to the Nth light-emitting element according to the first light-emitting data signal to the Nth light-emitting data signal Or multiple glows.
  • the combined light-emitting sub-circuit includes a first light-emitting sub-circuit and a second light-emitting sub-circuit, and the driving current is divided into a first driving current for driving the first light-emitting element and a second driving current for driving the second light-emitting element.
  • Driving current, step 200 includes:
  • the first light-emitting sub-circuit receives the first driving current and the first light-emitting data signal, and drives the first light-emitting element to emit light or controls the first light-emitting element to not emit light under the control of the reset signal and the first light-emitting data signal;
  • the second light-emitting sub-circuit receives the second driving current and the second light-emitting data signal, and drives the second light-emitting element to emit light or controls the second light-emitting element to not emit light under the control of the first scan signal and the second light-emitting data signal.
  • the embodiments of the present disclosure also provide a method for driving a pixel circuit, which is used to drive the pixel circuit that controls whether to generate a driving current and the duration of the generated driving current according to a light-emitting control signal as described in the previous embodiment, and the pixel circuit has Multiple scanning periods, within one scanning period, as shown in FIG. 13, the driving method includes step 300 to step 400.
  • step 300 includes: the current control sub-circuit receives the display data signal and the light emission control signal, controls whether to generate the driving current and the duration of the generated driving current according to the light emission control signal, and controls the current intensity of the generated driving current according to the display data signal.
  • step 300 includes:
  • the reset sub-circuit discharges the third capacitor under the control of the reset signal
  • the writing sub-circuit and the compensating sub-circuit store the display data signal and the threshold voltage on the third capacitor under the control of the first scan signal;
  • the lighting control sub-circuit is turned on under the control of the lighting control signal, and the driving current generated by the driving sub-circuit is provided to the combined lighting sub-circuit via the lighting control sub-circuit, and the lighting control sub-circuit controls the passage time of the driving current.
  • Step 400 includes: combining the light-emitting sub-circuit receives the driving current and the first light-emitting data signal to the Nth light-emitting data signal, and drives one of the first light-emitting element to the Nth light-emitting element according to the first light-emitting data signal to the Nth light-emitting data signal Or a plurality of light-emitting, and according to the duration of the generated driving current, the light-emitting duration of the first light-emitting element to the Nth light-emitting element is controlled.
  • the combined light-emitting sub-circuit includes a first light-emitting sub-circuit and a second light-emitting sub-circuit, and the driving current is divided into a first driving current for driving the first light-emitting element and a second driving current for driving the second light-emitting element.
  • Driving current, step 400 includes:
  • the third light-emitting sub-circuit receives the first driving current, drives the first light-emitting element to emit light under the control of the second scan signal terminal and the first light-emitting data signal terminal, and controls the light-emitting duration of the first light-emitting element according to the duration of the first driving current , Or control the first light-emitting element not to emit light;
  • the fourth light-emitting sub-circuit receives the second driving current, drives the second light-emitting element to emit light under the control of the third scan signal terminal and the second light-emitting data signal terminal, and controls the light-emitting duration of the second light-emitting element according to the duration of the second driving current , Or control the second light-emitting element not to emit light.
  • the first light-emitting element to the Nth light-emitting element are driven by combining the light-emitting sub-circuit according to the received driving current, the first light-emitting data signal to the Nth light-emitting data signal
  • One or more of the light-emitting devices can realize the combined light-emitting of light-emitting element chips of different areas, thereby improving the display effect of the display device under high and low gray levels.

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Abstract

一种像素电路及其驱动方法、显示装置，该像素电路包括电流控制子电路、组合发光子电路、第一发光元件至第N发光元件，N为大于1的自然数，其中：电流控制子电路被配置为接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度；组合发光子电路被配置为接收驱动电流以及第一发光数据信号至第N发光数据信号，根据第一发光数据信号至第N发光数据信号，驱动第一发光元件至第N发光元件中的一个或多个发光。

Description

像素电路及其驱动方法、显示装置
本申请要求于2020年3月4日提交中国专利局、申请号为2020101428661、发明名称为“一种像素电路及其驱动方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
微发光二极管(Micro Light Emitting Diode，Micro LED)技术是通过在一个芯片上高密度地集成微小尺寸的LED阵列，以实现LED的薄膜化、微小化和矩阵化，其像素间的距离能够达到微米级别，而且每一个像素都能定址、单独发光。Micro LED显示面板因其低驱动电压、长寿命、耐宽温等特点，逐渐向消费者终端机所用的显示面板发展。
通常通过像素电路与Micro LED电连接，以驱动Micro LED发光。在相关的像素电路中，通常通过电流和发光时间来共同调节灰阶，但是，通过电流来调节灰阶，会使得低灰阶对应低电流密度，其效率就会降低，并且随着电流密度的变化，Micro LED的色坐标会发生变化，即Micro LED在灰阶变化时会发生色偏；而依靠减小发光时间来调节灰阶，容易造成画面闪烁，进而影响显示面板的显示效果。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种像素电路，包括：电流控制子电路、组合发光子电路、第一发光元件至第N发光元件，N为大于1的自然数，其中：所述电流控制子电路，被配置为接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度；所述组合发光子电路，被配置为接收驱动电流以及第一发光数据信号至第N发光数据信号，根据接收的驱动电流、第一发光数据信号至第N发光数据信号，驱动第一发光元件至第N发光元件中的一个或多个发光。
在一些示例性实施例中，所述组合发光子电路包括第一发光子电路和第二发光子电路，所述驱动电流分为用于驱动第一发光元件的第一驱动电流和用于驱动第二发光元件的第二驱动电流，其中：所述第一发光子电路，分别与复位控制信号端、第一发光数据信号端和第一发光元件连接，被配置为接收第一驱动电流，在复位控制信号端和第一发光数据信号端的控制下，驱动第一发光元件发光或控制第一发光元件不发光；所述第二发光子电路，分别与第一扫描信号端、第二发光数据信号端和第二发光元件连接，被配置为接收第二驱动电流，在第一扫描信号端和第二发光数据信号端的控制下，驱动第二发光元件发光或控制第二发光元件不发光。
在一些示例性实施例中，所述第一发光子电路包括第一晶体管、第二晶体管和第一电容，所述第二发光子电路包括第三晶体管、第四晶体管和第二电容，其中：所述第一晶体管的控制极和第二节点连接，所述第一晶体管的第一极和第一节点连接，所述第一晶体管的第二极与第一发光元件连接；所述第二晶体管的控制极和复位控制信号端连接，所述第二晶体管的第一极和第一发光数据信号端连接，所述第二晶体管的第二极与第二节点连接；所述第一电容的一端与所述第二节点连接，所述第一电容的另一端与公共电压端连接；所述第三晶体管的控制极和第三节点连接，所述第三晶体管的第一极和第一节点连接，所述第三晶体管的第二极与第二发光元件连接；所述第四晶体管的控制极和第一扫描信号端连接，所述第四晶体管的第一极和第二发光数据信号端连接，所述第四晶体管的第二极与第三节点连接；所述第二电容的一端与所述第三节点连接，所述第二电容的另一端与公共电压端连接。
在一些示例性实施例中，所述电流控制子电路还被配置为，根据发光控 制信号控制产生的驱动电流的时长；所述组合发光子电路还被配置为，根据产生的驱动电流的时长，控制第一发光元件至第N发光元件的发光时长。
在一些示例性实施例中，所述组合发光子电路包括第三发光子电路和第四发光子电路，所述驱动电流分为用于驱动第一发光元件的第一驱动电流和用于驱动第二发光元件的第二驱动电流，其中：所述第三发光子电路，分别与第二扫描信号端、第一发光数据信号端和第一发光元件连接，被配置为接收第一驱动电流，在第二扫描信号端和第一发光数据信号端的控制下，驱动第一发光元件发光并根据第一驱动电流的时长，控制第一发光元件的发光时长，或控制第一发光元件不发光；所述第四发光子电路，分别与第三扫描信号端、第二发光数据信号端和第二发光元件连接，被配置为接收第二驱动电流，在第三扫描信号端和第二发光数据信号端的控制下，驱动第二发光元件发光并根据第二驱动电流的时长，控制第二发光元件的发光时长，或控制第二发光元件不发光。
在一些示例性实施例中，所述第三发光子电路包括第一晶体管、第五晶体管和第一电容，所述第四发光子电路包括第三晶体管、第六晶体管和第二电容，其中：所述第一晶体管的控制极和第二节点连接，所述第一晶体管的第一极和第一节点连接，所述第一晶体管的第二极与第一发光元件连接；所述第五晶体管的控制极和第二扫描信号端连接，所述第五晶体管的第一极和第一发光数据信号端连接，所述第五晶体管的第二极与第二节点连接；所述第一电容的一端与所述第二节点连接，所述第一电容的另一端与公共电压端连接；所述第三晶体管的控制极和第三节点连接，所述第三晶体管的第一极和第一节点连接，所述第三晶体管的第二极与第二发光元件连接；所述第六晶体管的控制极和第三扫描信号端连接，所述第六晶体管的第一极和第二发光数据信号端连接，所述第六晶体管的第二极与第三节点连接；所述第二电容的一端与所述第三节点连接，所述第二电容的另一端与公共电压端连接。
在一些示例性实施例中，所述电流控制子电路包括：驱动子电路、写入子电路、补偿子电路、复位子电路和发光控制子电路，其中：所述驱动子电路，分别与第四节点、第五节点和第六节点连接，被配置为在第四节点和第五节点的信号的控制下，向第六节点提供驱动电流；所述写入子电路，分别 与第一扫描信号端、显示数据信号端以及第五节点连接，被配置为在第一扫描信号端的信号的控制下，将显示数据信号端的信号写入第五节点；所述补偿子电路，分别与第一电压端、第一扫描信号端、第四节点以及第六节点连接，被配置为在第一扫描信号端的信号和第一电压端的信号的控制下，对第四节点进行补偿；所述复位子电路分别与复位控制信号端、初始电压端以及第四节点连接，被配置为在复位控制信号端的信号的控制下，将初始电压端的信号写入第四节点；所述发光控制子电路，分别与第一电压端、发光控制信号端、第一节点、第五节点和第六节点连接，被配置为在发光控制信号端的信号的控制下，向第五节点提供第一电压端的信号，并在第六节点和第一节点之间允许驱动电流通过。
在一些示例性实施例中，所述驱动子电路包括第七晶体管，所述补偿子电路包括第八晶体管和第三电容，所述复位子电路包括第九晶体管，所述写入子电路包括第十晶体管，所述发光控制子电路包括第十一晶体管和第十二晶体管，其中：所述第七晶体管的控制极和第四节点连接，所述第七晶体管的第一极和第五节点连接，所述第七晶体管的第二极与第六节点连接；所述第八晶体管的控制极和第一扫描信号端连接，所述第八晶体管的第一极和第四节点连接，所述第八晶体管的第二极与第六节点连接；所述第三电容的一端与所述第四节点连接，所述第三电容的另一端与所述第一电压端连接；所述第九晶体管的控制极和复位控制信号端连接，所述第九晶体管的第一极和初始电压端连接，所述第九晶体管的第二极与第四节点连接；所述第十晶体管的控制极和第一扫描信号端连接，所述第十晶体管的第一极和显示数据信号端连接，所述第十晶体管的第二极与第五节点连接；所述第十一晶体管的控制极和发光控制信号端连接，所述第十一晶体管的第一极和第一电压端连接，所述第十一晶体管的第二极与第五节点连接；所述第十二晶体管的控制极和发光控制信号端连接，所述第十二晶体管的第一极和第六节点连接，所述第十二晶体管的第二极与第一节点连接。
本公开实施例还提供了一种显示装置，包括：如上任一所述的像素电路。
本公开实施例还提供了一种像素电路的驱动方法，用于驱动如上所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，所述驱动 方法包括：电流控制子电路接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度；组合发光子电路接收驱动电流以及第一发光数据信号至第N发光数据信号，根据接收的驱动电流、第一发光数据信号至第N发光数据信号，驱动第一发光元件至第N发光元件中的一个或多个发光。
在一些示例性实施例中，所述驱动方法还包括：所述电流控制子电路根据发光控制信号控制产生的驱动电流的时长；所述组合发光子电路根据产生的驱动电流的时长，控制第一发光元件至第N发光元件的发光时长。
在阅读并理解了附图概述和本公开的实施方式后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的像素电路的结构示意图之一；
图2为本公开实施例提供的像素电路的结构示意图之二；
图3为本公开实施例提供的组合发光子电路的等效电路图之一；
图4为本公开实施例提供的电流控制子电路的结构示意图；
图5为本公开实施例提供的电流控制子电路的等效电路图；
图6为本公开实施例提供的像素电路的等效电路图之一；
图7为图6所示像素电路在一个扫描周期内的工作时序图；
图8为本公开实施例提供的像素电路的结构示意图之三；
图9为本公开实施例提供的组合发光子电路的等效电路图之二；
图10为本公开实施例提供的像素电路的等效电路图之二；
图11为图10所示像素电路在一个扫描周期内的工作时序图；
图12为本公开实施例提供的像素电路的驱动方法的流程图之一；
图13为本公开实施例提供的像素电路的驱动方法的流程图之二。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开实施例公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本领域技术人员可以理解，本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在一些示例性实施例中，本公开实施例中使用的薄膜晶体管可以是氧化物半导体晶体管。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。
本公开实施例提供一种像素电路，图1为本公开实施例的像素电路的结构示意图，如图1所示，本公开实施例提供的像素电路包括：电流控制子电路、组合发光子电路以及第一发光元件EL1至第N发光元件ELN，其中，N为大于1的自然数。
其中，电流控制子电路分别与第一电压端VDD、显示数据信号端DataI、发光控制信号端EM和第一节点N1连接，被配置为接收显示数据信号端DataI的显示数据信号和发光控制信号端EM的发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度。
组合发光子电路分别与第一节点N1、第一发光数据信号端DataS(1)至第 N发光数据信号端DataS(N)、第一发光元件EL1至第N发光元件ELN连接，被配置为接收电流控制子电路的驱动电流以及第一发光数据信号端DataS(1)的第一发光数据信号至第N发光数据信号端DataS(N)的第N发光数据信号，根据接收的驱动电流、第一发光数据信号至第N发光数据信号，驱动第一发光元件EL1至第N发光元件ELN中的一个或多个发光。
在本实施例中，第一发光数据信号可以被配置为控制第一发光元件EL1是否发光，第二发光数据信号可以被配置为控制第二发光元件EL2是否发光，……，第N发光数据信号可以被配置为控制第N发光元件ELN是否发光。例如，当第i发光数据信号为低电平时，第i发光元件ELi发光，i为1至N之间的自然数。
本公开实施例提供的像素电路，通过组合发光子电路根据接收的驱动电流、第一发光数据信号至第N发光数据信号，驱动第一发光元件EL1至第N发光元件ELN中的一个或多个发光，实现不同面积的发光元件芯片的组合发光，从而提高了显示装置在高低灰阶下的显示效果。
本公开实施例的像素电路，可以通过多种方案实现。下面通过多个实施例来详细说明本公开实施例的技术方案。
本公开实施例以N＝2为例进行说明，即该像素电路中包括两个发光元件，该两个发光元件的发光面积可以相同，也可以不同，示例性的，第一发光元件EL1的发光面积可以小于第二发光元件EL2的发光面积，以实现不同面积的组合发光效果。本实施例提供的像素电路的结构同样适用于N为其他值时的情况。当N为3或3个以上时，可以选择N个发光元件中的M个发光元件所在的发光子电路和复位控制信号端Reset连接，N个发光元件中的(N-M)个发光元件所在的发光子电路和第一扫描信号端GateA连接，M为1至N-1之间的自然数。
图2为本公开实施例的像素电路的一种结构示意图。如图2所示，该组合发光子电路包括第一发光子电路和第二发光子电路，驱动电流分为被配置为驱动第一发光元件EL1的第一驱动电流和被配置为驱动第二发光元件EL2的第二驱动电流。
其中，第一发光子电路分别与第一节点N1、复位控制信号端Reset、第 一发光数据信号端DataS(1)和第一发光元件EL1连接，被配置为接收第一驱动电流，在复位控制信号端Reset的复位信号和第一发光数据信号端DataS(1)的第一发光数据信号的控制下，驱动第一发光元件EL1发光或控制第一发光元件EL1不发光。
第二发光子电路分别与第一节点N1、第一扫描信号端GateA、第二发光数据信号端DataS(2)和第二发光元件EL2连接，被配置为接收第二驱动电流，在第一扫描信号端GateA的第一扫描信号和第二发光数据信号端DataS(2)的第二发光数据信号的控制下，驱动第二发光元件EL2发光或控制第二发光元件EL2不发光。
在一些示例性实施例中，当第一发光元件EL1和第二发光元件EL2中只有一个发光时，对应不发光的发光元件支路的驱动电流为零，例如，当第一发光元件EL1发光、第二发光元件EL2不发光时，第二驱动电流的电流值为零，第一驱动电流的电流值等于驱动电流的电流值。
在一些示例性实施例中，如图3所示，本公开实施例提供的第一发光子电路包括第一晶体管T1、第二晶体管T2和第一电容C1，第二发光子电路包括第三晶体管T3、第四晶体管T4和第二电容C2。
其中，第一晶体管T1的控制极和第二节点N2连接，第一晶体管T1的第一极和第一节点N1连接，第一晶体管T1的第二极与第一发光元件EL1的阳极连接，第一发光元件EL1的阴极与第二电压端VSS连接；第二晶体管T2的控制极和复位控制信号端Reset连接，第二晶体管T2的第一极和第一发光数据信号端DataS(1)连接，第二晶体管T2的第二极与第二节点N2连接；第一电容C1的一端与第二节点N2连接，第一电容C1的另一端与公共电压端VCOM连接；第三晶体管T3的控制极和第三节点N3连接，第三晶体管T3的第一极和第一节点N1连接，第三晶体管T3的第二极与第二发光元件EL2的阳极连接，第二发光元件EL2的阴极与第二电压端VSS连接；第四晶体管T4的控制极和第一扫描信号端GateA连接，第四晶体管T4的第一极和第二发光数据信号端DataS(2)连接，第四晶体管T4的第二极与第三节点N3连接；第二电容C2的一端与第三节点N3连接，第二电容C2的另一端与公共电压端VCOM连接。
图3示出了第一发光子电路和第二发光子电路的一种示例性结构。本领域技术人员容易理解是，第一发光子电路和第二发光子电路的实现方式不限于此，只要能够实现其各自的功能即可。
在一些示例性实施例中，如图4所示，本公开实施例提供的电流控制子电路包括：驱动子电路、写入子电路、补偿子电路、复位子电路和发光控制子电路。
其中，驱动子电路分别与第四节点N4、第五节点N5和第六节点N6连接，被配置为在第四节点N4和第五节点N5的信号的控制下，向第六节点N6提供驱动电流；写入子电路分别与第一扫描信号端GateA、显示数据信号端DataI以及第五节点N5连接，被配置为在第一扫描信号端GateA的第一扫描信号的控制下，将显示数据信号端DataI的显示数据信号写入第五节点N5；补偿子电路分别与第一电压端VDD、第一扫描信号端GateA、第四节点N4以及第六节点N6连接，被配置为在第一扫描信号端GateA的第一扫描信号和第一电压端VDD的第一电压信号的控制下，对第四节点N4进行补偿；复位子电路分别与复位控制信号端Reset、初始电压端Vinit以及第四节点N4连接，被配置为在复位控制信号端Reset的复位控制信号的控制下，将初始电压端Vinit的初始电压信号写入第四节点N4；发光控制子电路分别与第一电压端VDD、发光控制信号端EM、第一节点N1、第五节点N5和第六节点N6连接，被配置为在发光控制信号端EM的发光控制信号的控制下，向第五节点N5提供第一电压端VDD的第一电压信号，并在第六节点N6和第一节点N1之间允许驱动电流通过。
在一些示例性实施例中，如图5所示，驱动子电路包括第七晶体管T7，补偿子电路包括第八晶体管T8和第三电容C3，复位子电路包括第九晶体管T9，写入子电路包括第十晶体管T10，发光控制子电路包括第十一晶体管T11和第十二晶体管T12。
其中，第七晶体管T7的控制极和第四节点N4连接，第七晶体管T7的第一极和第五节点N5连接，第七晶体管T7的第二极与第六节点N6连接；第八晶体管T8的控制极和第一扫描信号端GateA连接，第八晶体管T8的第一极和第四节点N4连接，第八晶体管T8的第二极与第六节点N6连接；第 三电容C3的一端与第四节点N4连接，第三电容C3的另一端与第一电压端VDD连接；第九晶体管T9的控制极和复位控制信号端Reset连接，第九晶体管T9的第一极和初始电压端Vinit连接，第九晶体管T9的第二极与第四节点N4连接；第十晶体管T10的控制极和第一扫描信号端GateA连接，第十晶体管T10的第一极和显示数据信号端DataI连接，第十晶体管T10的第二极与第五节点N5连接；第十一晶体管T11的控制极和发光控制信号端EM连接，第十一晶体管T11的第一极和第一电压端VDD连接，第十一晶体管T11的第二极与第五节点N5连接；第十二晶体管T12的控制极和发光控制信号端EM连接，第十二晶体管T12的第一极和第六节点N6连接，第十二晶体管T12的第二极与第一节点N1连接。
图5示出了驱动子电路、写入子电路、补偿子电路、复位子电路和发光控制子电路的一种示例性结构。本领域技术人员容易理解是，驱动子电路、写入子电路、补偿子电路、复位子电路和发光控制子电路的实现方式不限于此，只要能够实现其各自的功能即可。
图6为本公开实施例提供的像素电路的等效电路图，如图6所示，本公开实施例提供的像素电路中，组合发光子电路包括第一发光子电路和第二发光子电路，电流控制子电路包括：驱动子电路、写入子电路、补偿子电路、复位子电路和发光控制子电路，第一发光子电路包括第一晶体管T1、第二晶体管T2和第一电容C1，第二发光子电路包括第三晶体管T3、第四晶体管T4和第二电容C2，驱动子电路包括第七晶体管T7，补偿子电路包括第八晶体管T8和第三电容C3，复位子电路包括第九晶体管T9，写入子电路包括第十晶体管T10，发光控制子电路包括第十一晶体管T11和第十二晶体管T12。
其中，第一晶体管T1的控制极和第二节点N2连接，第一晶体管T1的第一极和第一节点N1连接，第一晶体管T1的第二极与第一发光元件EL1的阳极端连接，第一发光元件EL1的阴极端与第二电压端VSS连接；第二晶体管T2的控制极和复位控制信号端Reset连接，第二晶体管T2的第一极和第一发光数据信号端DataS(1)连接，第二晶体管T2的第二极与第二节点N2连接；第一电容C1的一端与第二节点N2连接，第一电容C1的另一端与公共电压端VCOM连接；第三晶体管T3的控制极和第三节点N3连接， 第三晶体管T3的第一极和第一节点N1连接，第三晶体管T3的第二极与第二发光元件EL2的阳极端连接，第二发光元件EL2的阴极端与第二电压端VSS连接；第四晶体管T4的控制极和第一扫描信号端GateA连接，第四晶体管T4的第一极和第二发光数据信号端DataS(2)连接，第四晶体管T4的第二极与第三节点N3连接；第二电容C2的一端与第三节点N3连接，第二电容C2的另一端与公共电压端VCOM连接；第七晶体管T7的控制极和第四节点N4连接，第七晶体管T7的第一极和第五节点N5连接，第七晶体管T7的第二极与第六节点N6连接；第八晶体管T8的控制极和第一扫描信号端GateA连接，第八晶体管T8的第一极和第四节点N4连接，第八晶体管T8的第二极与第六节点N6连接；第三电容C3的一端与第四节点N4连接，第三电容C3的另一端与第一电压端VDD连接；第九晶体管T9的控制极和复位控制信号端Reset连接，第九晶体管T9的第一极和初始电压端Vinit连接，第九晶体管T9的第二极与第四节点N4连接；第十晶体管T10的控制极和第一扫描信号端GateA连接，第十晶体管T10的第一极和显示数据信号端DataI连接，第十晶体管T10的第二极与第五节点N5连接；第十一晶体管T11的控制极和发光控制信号端EM连接，第十一晶体管T11的第一极和第一电压端VDD连接，第十一晶体管T11的第二极与第五节点N5连接；第十二晶体管T12的控制极和发光控制信号端EM连接，第十二晶体管T12的第一极和第六节点N6连接，第十二晶体管T12的第二极与第一节点N1连接。
图6示出了组合发光子电路和电流控制子电路的示例性结构。本领域技术人员容易理解是，以上各子电路的实现方式不限于此，只要能够实现其各自的功能即可。
在本实施例中，发光元件EL(包括第一发光元件EL1至第N发光元件ELN)可以为微发光二极管，也可以为次毫米发光二极管(Mini LED)、有机发光二极管(Organic Light Emitting Diode，OLED)等其他类型的发光二极管。在实际应用中，发光元件EL的结构可以根据实际应用环境来设计确定，在此不作限定。以下均以发光元件EL为微发光二极管为例进行说明。
在本实施例中，第一晶体管T1～第四晶体管T4以及第七晶体管T7至第十二晶体管T12均可以为N型薄膜晶体管或P型薄膜晶体管，所有晶体管 使用相同类型的薄膜晶体管，可以统一工艺流程，减少工艺制程，有助于提高产品的良率。此外，考虑到低温多晶硅薄膜晶体管的漏电流较小，因此，本公开实施例所有晶体管可以为低温多晶硅薄膜晶体管，薄膜晶体管可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。
本公开实施例中，第一电容C1至第三电容C3可以是由像素电极与公共电极构成的液晶电容，也可以是由像素电极与公共电极构成的液晶电容以及存储电容构成的等效电容，本公开对此不作限定。
图7为本实施例的像素电路的工作时序图，在电流控制子电路完成阈值电压补偿的同时，组合发光子电路通过时序调控将第一发光元件EL1、第二发光元件EL2的发光数据信号DataS(1)和DataS(2)传递到第一电容C1和第二电容C2，在一时间内完成第一发光元件EL1和第二发光元件EL2的组合发光，其中，第一发光数据信号DataS(1)和第二发光数据信号DataS(2)的信号值可以为高电平或低电平，通过第一发光数据信号DataS(1)和第二发光数据信号DataS(2)控制第一晶体管T1和第三晶体管T3的通断。下面以第一级像素电路的工作过程为例，通过像素电路的工作过程来说明本公开实施例的技术方案。
下面以本公开实施例提供的像素电路中第一晶体管T1～第四晶体管T4以及第七晶体管T7至第十二晶体管T12均为P型薄膜晶体管为例，结合图6所示的像素电路和图7所示的工作时序图，对一个像素电路在一帧周期内的工作过程进行描述。如图6所示，本公开实施例提供的像素电路包括10个晶体管单元(T1～T4、T7～T12)、3个电容单元(C1～C3)和三个电压端(VDD、VSS、VCOM)，其中，第一电压端VDD持续提供高电平信号，第二电压端VSS持续提供低电平信号，公共电压端VCOM接地。其工作过程包括：
第一阶段t1，即复位阶段，复位控制信号端Reset拉低，第九晶体管T9导通，将第七晶体管T7的栅极及第三电容C3的一端(即第四节点N4)复位为初始电压端Vinit的初始电压；同时，第二晶体管T2导通，第一发光数据信号端DataS(1)的第一发光数据信号传递到第一电容C1的一端和第一晶 体管T1的栅极，控制第一晶体管T1的开关；
第二阶段t2，即阈值电压补偿及显示数据读取阶段，此时，第一扫描信号端GateA电压拉低，第十晶体管T10、第七晶体管T7和第八晶体管T8导通，显示数据信号端DataI的显示数据信号输入，并且将显示数据信号和阈值电压(VdataI+Vth)储存在第三电容C3上；同时，第四晶体管T4导通，第二发光数据信号端DataS(2)的第二发光数据信号传递到第二电容C2和第三晶体管T3的栅极，控制第三晶体管T3的开关；
第三阶段t3，即发光阶段，发光控制信号端EM给低电平，第十一晶体管T11和第十二晶体管T12处于导通状态，根据第一晶体管T1和第三晶体管T3的开关状态，决定第一发光元件EL1和EL2的工作状态，例如，当第一发光数据信号端DataS(1)为低电平时，第一晶体管T1导通，第一发光元件EL1处于工作状态。
根据显示需要，当某子像素显示低灰阶画面时，第一发光数据信号端DataS(1)为低电平，第二发光数据信号端DataS(2)为高电平，此时，小面积的Micro LED芯片EL1工作，大面积的Micro LED芯片EL2断开；当某子像素显示低灰阶画面时，第一发光数据信号端DataS(1)为低电平，第二发光数据信号端DataS(2)为低电平，此时，Micro LED芯片EL1和EL2均处于工作状态。
在上述实施例中，通过选择不同面积的发光元件的组合发光，来实现增强灰阶显示效果，本实施例在上述实施例的基础上，通过引入独立的两组扫描信号GOA：GateA和GateB(其中，GateB包括GateB(1)和GateB(2))，实现在一帧显示中既可以选择不同面积的芯片组合工作，又可以选择芯片不同的发光时间段。
在本实施例中，电流控制子电路还被配置为，根据发光控制信号控制产生的驱动电流的时长；组合发光子电路还被配置为，根据产生的驱动电流的时长，控制第一发光元件EL1至第N发光元件ELN的发光时长。
本公开实施例提供的像素电路，通过组合发光子电路根据产生的驱动电 流的时长以及接收的第一发光数据信号至第N发光数据信号，驱动第一发光元件EL1至第N发光元件ELN中的一个或多个发光及其发光时长，实现不同面积以及不同发光时长的发光元件芯片的组合发光，进一步提高了显示装置在高低灰阶下的显示效果。
本公开实施例仍以N＝2为例进行说明，即该像素电路中包括两个发光元件，该两个发光元件的发光面积可以相同，也可以不同，示例性的，第一发光元件EL1的发光面积可以小于第二发光元件EL2的发光面积，以实现不同面积的组合发光效果。本实施例提供的像素电路的结构同样适用于N为其他值时的情况。当N为3或3个以上时，第i发光元件所在的发光子电路和第(i+1)扫描信号端GateB(i)、第i发光数据信号端DataS(i)连接，i为1至N之间的自然数。
图8为本公开实施例的像素电路的又一种结构示意图。如图8所示，该组合发光子电路包括第三发光子电路和第四发光子电路，驱动电流分为用于驱动第一发光元件EL1的第一驱动电流和用于驱动第二发光元件EL2的第二驱动电流。
其中，第三发光子电路分别与第一节点N1、第二扫描信号端GateB(1)、第一发光数据信号端DataS(1)和第一发光元件EL1连接，被配置为接收第一驱动电流，在第二扫描信号端GateB(1)的第二扫描信号和第一发光数据信号端DataS(1)的第一发光数据信号的控制下，驱动第一发光元件EL1发光并根据第一驱动电流的时长，控制第一发光元件EL1的发光时长，或控制第一发光元件EL1不发光。
第四发光子电路分别与第一节点N1、第三扫描信号端GateB(2)、第二发光数据信号端DataS(2)和第二发光元件EL2连接，被配置为接收第二驱动电流，在第三扫描信号端GateB(2)的第三扫描信号和第二发光数据信号端DataS(2)的第二发光数据信号的控制下，驱动第二发光元件EL2发光，并根据第二驱动电流的时长，控制第二发光元件EL2的发光时长，或控制第二发光元件EL2不发光。
在一些示例性实施例中，当第一发光元件EL1和第二发光元件EL2中只有一个发光时，对应不发光的发光元件支路的驱动电流为零，例如，当第一 发光元件EL1发光、第二发光元件EL2不发光时，第二驱动电流的电流值为零，第一驱动电流的电流值等于驱动电流的电流值。
在一些示例性实施例中，如图9所示，本公开实施例提供的第三发光子电路包括第一晶体管T1、第五晶体管T5和第一电容C1，第二发光子电路包括第三晶体管T3、第六晶体管T6和第二电容C2。
其中，第一晶体管T1的控制极和第二节点N2连接，第一晶体管T1的第一极和第一节点N1连接，第一晶体管T1的第二极与第一发光元件EL1的阳极端连接，第一发光元件EL1的阴极端与第二电压端VSS连接；第五晶体管T5的控制极和第二扫描信号端GateB(1)连接，第五晶体管T5的第一极和第一发光数据信号端DataS(1)连接，第五晶体管T5的第二极与第二节点N2连接；第一电容C1的一端与第二节点N2连接，第一电容C1的另一端与公共电压端VCOM连接；第三晶体管T3的控制极和第三节点N3连接，第三晶体管T3的第一极和第一节点N1连接，第三晶体管T3的第二极与第二发光元件EL2的阳极端连接，第二发光元件EL2的阴极端与第二电压端VSS连接；第六晶体管T6的控制极和第三扫描信号端GateB(2)连接，第六晶体管T6的第一极和第二发光数据信号端DataS(2)连接，第六晶体管T6的第二极与第三节点N3连接；第二电容C2的一端与第三节点N3连接，第二电容C2的另一端与公共电压端VCOM连接。
图9示出了第三发光子电路和第四发光子电路的一种示例性结构。本领域技术人员容易理解是，第三发光子电路和第四发光子电路的实现方式不限于此，只要能够实现其各自的功能即可。
本实施例的电流控制子电路可以采用与前述实施例的电流控制子电路相同的结构，此处不再赘述。
图10为本公开实施例提供的像素电路的另一种等效电路图，如图10所示，本公开实施例提供的像素电路中，组合发光子电路包括第一发光子电路和第二发光子电路，电流控制子电路包括：驱动子电路、写入子电路、补偿子电路、复位子电路和发光控制子电路，第一发光子电路包括第一晶体管T1、第五晶体管T5和第一电容C1，第二发光子电路包括第三晶体管T3、第六晶体管T6和第二电容C2，驱动子电路包括第七晶体管T7，补偿子电路包括第 八晶体管T8和第三电容C3，复位子电路包括第九晶体管T9，写入子电路包括第十晶体管T10，发光控制子电路包括第十一晶体管T11和第十二晶体管T12。
其中，第一晶体管T1的控制极和第二节点N2连接，第一晶体管T1的第一极和第一节点N1连接，第一晶体管T1的第二极与第一发光元件EL1的阳极端连接，第一发光元件EL1的阴极端与第二电压端VSS连接；第五晶体管T5的控制极和第二扫描信号端GateB(1)连接，第五晶体管T5的第一极和第一发光数据信号端DataS(1)连接，第五晶体管T5的第二极与第二节点N2连接；第一电容C1的一端与第二节点N2连接，第一电容C1的另一端与公共电压端VCOM连接；第三晶体管T3的控制极和第三节点N3连接，第三晶体管T3的第一极和第一节点N1连接，第三晶体管T3的第二极与第二发光元件EL2的阳极端连接，第二发光元件EL2的阴极端与第二电压端VSS连接；第六晶体管T6的控制极和第三扫描信号端GateB(2)连接，第六晶体管T6的第一极和第二发光数据信号端DataS(2)连接，第六晶体管T6的第二极与第三节点N3连接；第二电容C2的一端与第三节点N3连接，第二电容C2的另一端与公共电压端VCOM连接；第七晶体管T7的控制极和第四节点N4连接，第七晶体管T7的第一极和第五节点N5连接，第七晶体管T7的第二极与第六节点N6连接；第八晶体管T8的控制极和第一扫描信号端GateA连接，第八晶体管T8的第一极和第四节点N4连接，第八晶体管T8的第二极与第六节点N6连接；第三电容C3的一端与第四节点N4连接，第三电容C3的另一端与第一电压端VDD连接；第九晶体管T9的控制极和复位控制信号端Reset连接，第九晶体管T9的第一极和初始电压端Vinit连接，第九晶体管T9的第二极与第四节点N4连接；第十晶体管T10的控制极和第一扫描信号端GateA连接，第十晶体管T10的第一极和显示数据信号端DataI连接，第十晶体管T10的第二极与第五节点N5连接；第十一晶体管T11的控制极和发光控制信号端EM连接，第十一晶体管T11的第一极和第一电压端VDD连接，第十一晶体管T11的第二极与第五节点N5连接；第十二晶体管T12的控制极和发光控制信号端EM连接，第十二晶体管T12的第一极和第六节点N6连接，第十二晶体管T12的第二极与第一节点N1连接。
图10示出了组合发光子电路和电流控制子电路的示例性结构。本领域技术人员容易理解是，以上各子电路的实现方式不限于此，只要能够实现其各自的功能即可。
在本实施例中，发光元件EL(包括第一发光元件EL1至第N发光元件ELN)可以为微发光二极管，也可以为次毫米发光二极管、有机发光二极管等其他类型的发光二极管。在实际应用中，发光元件EL的结构可以根据实际应用环境来设计确定，在此不作限定。以下均以发光元件EL为微发光二极管为例进行说明。
在本实施例中，第一晶体管T1、第三晶体管T3、第五晶体管T5～第十二晶体管T12均可以为N型薄膜晶体管或P型薄膜晶体管，可以统一工艺流程，减少工艺制程，有助于提高产品的良率。此外，考虑到低温多晶硅薄膜晶体管的漏电流较小，因此，本公开实施例所有晶体管可以为低温多晶硅薄膜晶体管，薄膜晶体管可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。
本实施例中，第一电容C1至第三电容C3可以是由像素电极与公共电极构成的液晶电容，也可以是由像素电极与公共电极构成的液晶电容以及存储电容构成的等效电容，本公开对此不作限定。
下面以第一级像素电路的工作过程为例，通过像素电路的工作过程来说明本公开实施例的技术方案。
下面以本公开实施例提供的像素电路中第一晶体管T1、第三晶体管T3、第五晶体管T5～第十二晶体管T12均为P型薄膜晶体管为例，结合图10所示的像素电路和图11所示的工作时序图，对一个像素电路在一帧周期内的工作过程进行描述。如图10所示，本公开实施例提供的像素电路包括10个晶体管单元(T1、T3、T5～T12)、3个电容单元(C1～C3)和3个电压端(VDD、VSS、VCOM)，其中，第一电压端VDD持续提供高电平信号，第二电压端VSS持续提供低电平信号，公共电压端VCOM接地。其工作过程包括：
第一阶段t1，即复位阶段，复位控制信号端Reset拉低，第九晶体管T9导通，将第七晶体管T7的栅极及第三电容C3的一端(即第四节点N4)复位为初始电压端Vinit的初始电压；同时，第二扫描信号端GateB(1)为低电 平，第二晶体管T2导通，第一发光数据信号端DataS(1)的第一发光数据信号传递到第一电容C1的一端和第一晶体管T1的栅极，控制第一晶体管T1的开关；
第二阶段t2，即阈值电压补偿及显示数据读取阶段，此时第一扫描信号端GateA电压拉低，第十晶体管T10、第七晶体管T7和第八晶体管T8导通，显示数据信号端DataI的显示数据信号输入，并且将显示数据信号和阈值电压(VdataI+Vth)储存在第三电容C3上；同时，第三扫描信号端GateB(2)为低电平，第四晶体管T4导通，第二发光数据信号端DataS(2)的第二发光数据信号传递到第二电容C2和第三晶体管T3的栅极，控制第三晶体管T3的开关；
第三阶段t3，即第一发光子阶段，发光控制信号端EM给低电平时间time1，其余(t3-time1)时间内，发光控制信号端EM为高电平，当发光控制信号端EM在时间time1内为低电平时，第十一晶体管T11和第十二晶体管T12处于导通状态，根据第一晶体管T1和第三晶体管T3的开关状态，决定第一发光元件EL1和EL2的发光状态，例如，当第一发光数据信号端DataS(1)为低电平时，第一晶体管T1导通，第一发光元件EL1处于发光状态，且发光时长为time1。
第四阶段t4，即第一发光数据输入阶段，第二扫描信号端GateB(1)为低电平，第二晶体管T2导通，第一发光数据信号端DataS(1)的第一发光数据信号传递到第一电容C1的一端和第一晶体管T1的栅极，控制第一晶体管T1的开关；
第五阶段t5，即第二发光数据输入阶段，第三扫描信号端GateB(2)为低电平，第四晶体管T4导通，第二发光数据信号端DataS(2)的第二发光数据信号传递到第二电容C2和第三晶体管T3的栅极，控制第三晶体管T3的开关；
第六阶段t6，即第二发光子阶段，发光控制信号端EM给低电平时间time2，其余(t6-time2)时间内，发光控制信号端EM为高电平，当发光控制信号端EM在时间time2内为低电平时，第十一晶体管T11和第十二晶体管T12处于导通状态，根据第一晶体管T1和第三晶体管T3的开关状态，决定第一发光元件EL1和EL2的发光状态，例如，当第二发光数据信号端 DataS(2)为低电平，第三晶体管T3导通，第二发光元件EL2处于发光状态，且发光时长为time2。
第七阶段t7的工作过程同第四阶段t4，第八阶段t8的工作过程同第五阶段t5，第九阶段t9的工作过程同第六阶段t6。
综合以上步骤，在显示子像素显示低灰阶时可在一帧时间内采用小面积第一发光元件EL1发光time1时间；高灰阶采用第一发光元件EL1和第二发光元件EL2同时发光(time1+time2+time3)时间。
本公开实施例还提供了一种显示装置，包括前述任一实施例所述的像素电路。本公开实施例的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种像素电路的驱动方法，用于驱动如前实施例所述的根据发光控制信号控制是否产生驱动电流的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，如图12所示，所述驱动方法包括步骤100至步骤200。
其中，步骤100包括：电流控制子电路接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度。
在本实施例中，步骤100包括：
复位子电路在复位信号的控制下，对第三电容进行放电；
写入子电路和补偿子电路在第一扫描信号的控制下，将显示数据信号和阈值电压储存在第三电容上；
发光控制子电路在发光控制信号的控制下开启，驱动子电路产生的驱动电流经由发光控制子电路提供给组合发光子电路。
步骤200包括：组合发光子电路接收驱动电流以及第一发光数据信号至第N发光数据信号，根据第一发光数据信号至第N发光数据信号，驱动第一 发光元件至第N发光元件中的一个或多个发光。
在本实施例中，组合发光子电路包括第一发光子电路和第二发光子电路，驱动电流分为用于驱动第一发光元件的第一驱动电流和用于驱动第二发光元件的第二驱动电流，步骤200包括：
第一发光子电路接收第一驱动电流与第一发光数据信号，在复位信号和第一发光数据信号的控制下，驱动第一发光元件发光或控制第一发光元件不发光；
第二发光子电路接收第二驱动电流与第二发光数据信号，在第一扫描信号和第二发光数据信号的控制下，驱动第二发光元件发光或控制第二发光元件不发光。
本公开实施例还提供了一种像素电路的驱动方法，用于驱动如前实施例所述的根据发光控制信号控制是否产生驱动电流以及产生的驱动电流的时长的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，如图13所示，所述驱动方法包括步骤300至步骤400。
其中，步骤300包括：电流控制子电路接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流以及产生的驱动电流的时长，根据显示数据信号控制产生的驱动电流的电流强度。
在本实施例中，步骤300包括：
复位子电路在复位信号的控制下，对第三电容进行放电；
写入子电路和补偿子电路在第一扫描信号的控制下，将显示数据信号和阈值电压储存在第三电容上；
发光控制子电路在发光控制信号的控制下开启，驱动子电路产生的驱动电流经由发光控制子电路提供给组合发光子电路，并由发光控制子电路控制驱动电流的通过时长。
步骤400包括：组合发光子电路接收驱动电流以及第一发光数据信号至第N发光数据信号，根据第一发光数据信号至第N发光数据信号，驱动第一发光元件至第N发光元件中的一个或多个发光，并根据产生的驱动电流的时 长，控制第一发光元件至第N发光元件的发光时长。
在本实施例中，组合发光子电路包括第一发光子电路和第二发光子电路，驱动电流分为用于驱动第一发光元件的第一驱动电流和用于驱动第二发光元件的第二驱动电流，步骤400包括：
第三发光子电路接收第一驱动电流，在第二扫描信号端和第一发光数据信号端的控制下，驱动第一发光元件发光并根据第一驱动电流的时长，控制第一发光元件的发光时长，或控制第一发光元件不发光；
第四发光子电路接收第二驱动电流，在第三扫描信号端和第二发光数据信号端的控制下，驱动第二发光元件发光并根据第二驱动电流的时长，控制第二发光元件的发光时长，或控制第二发光元件不发光。
本公开实施例提供的像素电路及其驱动方法、显示装置，通过组合发光子电路根据接收的驱动电流、第一发光数据信号至第N发光数据信号，驱动第一发光元件至第N发光元件中的一个或多个发光，实现不同面积的发光元件芯片的组合发光，从而提高了显示装置在高低灰阶下的显示效果。
有以下几点需要说明：
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种像素电路，包括：电流控制子电路、组合发光子电路、第一发光元件至第N发光元件，N为大于1的自然数，其中：
    所述电流控制子电路，被配置为接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度；
    所述组合发光子电路，被配置为接收驱动电流以及第一发光数据信号至第N发光数据信号，根据接收的驱动电流、第一发光数据信号至第N发光数据信号，驱动第一发光元件至第N发光元件中的一个或多个发光。
  2. 根据权利要求1所述的像素电路，其中，所述组合发光子电路包括第一发光子电路和第二发光子电路，所述驱动电流分为用于驱动第一发光元件的第一驱动电流和用于驱动第二发光元件的第二驱动电流，其中：
    所述第一发光子电路，分别与复位控制信号端、第一发光数据信号端和第一发光元件连接，被配置为接收第一驱动电流，在复位控制信号端和第一发光数据信号端的控制下，驱动第一发光元件发光或控制第一发光元件不发光；
    所述第二发光子电路，分别与第一扫描信号端、第二发光数据信号端和第二发光元件连接，被配置为接收第二驱动电流，在第一扫描信号端和第二发光数据信号端的控制下，驱动第二发光元件发光或控制第二发光元件不发光。
  3. 根据权利要求2所述的像素电路，其中，所述第一发光子电路包括第一晶体管、第二晶体管和第一电容，其中：
    所述第一晶体管的控制极和第二节点连接，所述第一晶体管的第一极和第一节点连接，所述第一晶体管的第二极与第一发光元件连接；
    所述第二晶体管的控制极和复位控制信号端连接，所述第二晶体管的第一极和第一发光数据信号端连接，所述第二晶体管的第二极与第二节点连接；
    所述第一电容的一端与所述第二节点连接，所述第一电容的另一端与公 共电压端连接。
  4. 根据权利要求2所述的像素电路，其中，所述第二发光子电路包括第三晶体管、第四晶体管和第二电容，其中：
    所述第三晶体管的控制极和第三节点连接，所述第三晶体管的第一极和第一节点连接，所述第三晶体管的第二极与第二发光元件连接；
    所述第四晶体管的控制极和第一扫描信号端连接，所述第四晶体管的第一极和第二发光数据信号端连接，所述第四晶体管的第二极与第三节点连接；
    所述第二电容的一端与所述第三节点连接，所述第二电容的另一端与公共电压端连接。
  5. 根据权利要求1所述的像素电路，其中，所述电流控制子电路还被配置为，根据发光控制信号控制产生的驱动电流的时长；所述组合发光子电路还被配置为，根据产生的驱动电流的时长，控制第一发光元件至第N发光元件的发光时长。
  6. 根据权利要求5所述的像素电路，其中，所述组合发光子电路包括第三发光子电路和第四发光子电路，所述驱动电流分为用于驱动第一发光元件的第一驱动电流和用于驱动第二发光元件的第二驱动电流，其中：
    所述第三发光子电路，分别与第二扫描信号端、第一发光数据信号端和第一发光元件连接，被配置为接收第一驱动电流，在第二扫描信号端和第一发光数据信号端的控制下，驱动第一发光元件发光并根据第一驱动电流的时长，控制第一发光元件的发光时长，或控制第一发光元件不发光；
    所述第四发光子电路，分别与第三扫描信号端、第二发光数据信号端和第二发光元件连接，被配置为接收第二驱动电流，在第三扫描信号端和第二发光数据信号端的控制下，驱动第二发光元件发光并根据第二驱动电流的时长，控制第二发光元件的发光时长，或控制第二发光元件不发光。
  7. 根据权利要求6所述的像素电路，其中，所述第三发光子电路包括第一晶体管、第五晶体管和第一电容，其中：
    所述第一晶体管的控制极和第二节点连接，所述第一晶体管的第一极和第一节点连接，所述第一晶体管的第二极与第一发光元件连接；
    所述第五晶体管的控制极和第二扫描信号端连接，所述第五晶体管的第一极和第一发光数据信号端连接，所述第五晶体管的第二极与第二节点连接；
    所述第一电容的一端与所述第二节点连接，所述第一电容的另一端与公共电压端连接。
  8. 根据权利要求6所述的像素电路，其中，所述第四发光子电路包括第三晶体管、第六晶体管和第二电容，其中：
    所述第三晶体管的控制极和第三节点连接，所述第三晶体管的第一极和第一节点连接，所述第三晶体管的第二极与第二发光元件连接；
    所述第六晶体管的控制极和第三扫描信号端连接，所述第六晶体管的第一极和第二发光数据信号端连接，所述第六晶体管的第二极与第三节点连接；
    所述第二电容的一端与所述第三节点连接，所述第二电容的另一端与公共电压端连接。
  9. 根据权利要求1至8任一所述的像素电路，其中，所述电流控制子电路包括：驱动子电路、写入子电路、补偿子电路、复位子电路和发光控制子电路，其中：
    所述驱动子电路，分别与第四节点、第五节点和第六节点连接，被配置为在第四节点和第五节点的信号的控制下，向第六节点提供驱动电流；
    所述写入子电路，分别与第一扫描信号端、显示数据信号端以及第五节点连接，被配置为在第一扫描信号端的信号的控制下，将显示数据信号端的信号写入第五节点；
    所述补偿子电路，分别与第一电压端、第一扫描信号端、第四节点以及第六节点连接，被配置为在第一扫描信号端的信号和第一电压端的信号的控制下，对第四节点进行补偿；
    所述复位子电路分别与复位控制信号端、初始电压端以及第四节点连接，被配置为在复位控制信号端的信号的控制下，将初始电压端的信号写入第四 节点；
    所述发光控制子电路，分别与第一电压端、发光控制信号端、第一节点、第五节点和第六节点连接，被配置为在发光控制信号端的信号的控制下，向第五节点提供第一电压端的信号，并在第六节点和第一节点之间允许驱动电流通过。
  10. 根据权利要求9所述的像素电路，其中，所述驱动子电路包括第七晶体管，所述补偿子电路包括第八晶体管和第三电容，所述复位子电路包括第九晶体管，所述写入子电路包括第十晶体管，所述发光控制子电路包括第十一晶体管和第十二晶体管，其中：
    所述第七晶体管的控制极和第四节点连接，所述第七晶体管的第一极和第五节点连接，所述第七晶体管的第二极与第六节点连接；
    所述第八晶体管的控制极和第一扫描信号端连接，所述第八晶体管的第一极和第四节点连接，所述第八晶体管的第二极与第六节点连接；
    所述第三电容的一端与所述第四节点连接，所述第三电容的另一端与所述第一电压端连接；
    所述第九晶体管的控制极和复位控制信号端连接，所述第九晶体管的第一极和初始电压端连接，所述第九晶体管的第二极与第四节点连接；
    所述第十晶体管的控制极和第一扫描信号端连接，所述第十晶体管的第一极和显示数据信号端连接，所述第十晶体管的第二极与第五节点连接；
    所述第十一晶体管的控制极和发光控制信号端连接，所述第十一晶体管的第一极和第一电压端连接，所述第十一晶体管的第二极与第五节点连接；
    所述第十二晶体管的控制极和发光控制信号端连接，所述第十二晶体管的第一极和第六节点连接，所述第十二晶体管的第二极与第一节点连接。
  11. 根据权利要求1所述的像素电路，其中，所述第一发光元件至第N发光元件为微发光二极管、次毫米发光二极管或有机发光二极管。
  12. 一种显示装置，包括如权利要求1至11任一所述的像素电路。
  13. 一种像素电路的驱动方法，被配置为驱动如权利要求1至11任一所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，所述驱动方法包括：
    电流控制子电路接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度；
    组合发光子电路接收驱动电流以及第一发光数据信号至第N发光数据信号，根据接收的驱动电流、第一发光数据信号至第N发光数据信号，驱动第一发光元件至第N发光元件中的一个或多个发光。
  14. 根据权利要求13所述的像素电路的驱动方法，当所述电流控制子电路采用如权利要求10所述的电流控制子电路的结构时，所述电流控制子电路接收显示数据信号和发光控制信号，根据发光控制信号控制是否产生驱动电流，根据显示数据信号控制产生的驱动电流的电流强度，包括：
    所述复位子电路在复位信号的控制下，对第三电容进行放电；
    所述写入子电路和补偿子电路在第一扫描信号的控制下，将显示数据信号和阈值电压储存在第三电容上；
    所述发光控制子电路在发光控制信号的控制下开启，驱动子电路产生的驱动电流经由发光控制子电路提供给组合发光子电路。
  15. 根据权利要求13所述的像素电路的驱动方法，所述驱动方法还包括：
    所述电流控制子电路根据发光控制信号控制产生的驱动电流的时长；
    所述组合发光子电路根据产生的驱动电流的时长，控制第一发光元件至第N发光元件的发光时长。
  16. 根据权利要求15所述的像素电路的驱动方法，当所述电流控制子电路采用如权利要求10所述的电流控制子电路的结构时，所述电流控制子电路根据发光控制信号控制是否产生驱动电流以及产生的驱动电流的时长，根据显示数据信号控制产生的驱动电流的电流强度，包括：
    所述复位子电路在复位信号的控制下，对第三电容进行放电；
    所述写入子电路和补偿子电路在第一扫描信号的控制下，将显示数据信号和阈值电压储存在第三电容上；
    所述发光控制子电路在发光控制信号的控制下开启，驱动子电路产生的驱动电流经由发光控制子电路提供给组合发光子电路，并由发光控制子电路控制驱动电流的通过时长。
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