WO2023004810A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2023004810A1
WO2023004810A1 PCT/CN2021/109884 CN2021109884W WO2023004810A1 WO 2023004810 A1 WO2023004810 A1 WO 2023004810A1 CN 2021109884 W CN2021109884 W CN 2021109884W WO 2023004810 A1 WO2023004810 A1 WO 2023004810A1
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Prior art keywords
transistor
signal
reset
node
circuit
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PCT/CN2021/109884
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English (en)
French (fr)
Inventor
王彬艳
黄耀
李孟
承天一
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/109884 priority Critical patent/WO2023004810A1/zh
Priority to CN202180002058.8A priority patent/CN114258320B/zh
Priority to EP21951400.7A priority patent/EP4300471A4/en
Priority to CN202210913633.6A priority patent/CN115691411A/zh
Priority to US18/273,788 priority patent/US20240078976A1/en
Priority to PCT/CN2022/109160 priority patent/WO2023006100A1/zh
Publication of WO2023004810A1 publication Critical patent/WO2023004810A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
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    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
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    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
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Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technology, especially a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • An embodiment of the present disclosure provides a pixel circuit, including: a driving subcircuit, a first reset subcircuit, a second reset subcircuit, and a light emitting element, wherein: the driving subcircuit is configured to respond to a control signal of the first node , generating a driving current between the second node and the third node; the first reset sub-circuit is configured to respond to the signal of the first light emission control signal line or the second reset control signal line, to the anode of the light emitting element Writing a first reset signal to the pole; the second reset subcircuit is configured to write a second reset signal to the first pole or the second pole of the driving subcircuit in response to the signal of the first reset control signal line; The second reset signal is greater than the first reset signal.
  • the absolute value of the second reset signal is greater than 1.5 times the threshold voltage of the driving sub-circuit.
  • the magnitude of the second reset signal is greater than zero.
  • the pixel circuit further includes: a write subcircuit, a compensation subcircuit, a first light emission control subcircuit, and a second light emission control subcircuit, wherein: the write subcircuit is configured to respond to The signal of the second scanning signal line writes the data signal to the second node; the compensation sub-circuit is configured to respond to the signal of the first scanning signal line and write the first reset signal or the first reset signal of the third node Two reset signals are written into the first node; it is also configured to compensate the first node in response to the signal of the first scanning signal line; the first light emission control sub-circuit is configured to respond to the first scanning signal line A signal of a light emission control signal line, providing the second node with a signal of the first power line; the second light emission control subcircuit is configured to respond to the signal of the second light emission control signal line, A reset signal is written into the third node; and is further configured to allow a driving current to pass between the third node and the fourth node in response to the signal
  • the second reset signal comes from at least one of the following signal lines: the first power supply line, the first light emission control signal line, the second light emission control signal line or the first light emission control signal line. Three power cords.
  • the pulse width of the signal of the first reset control signal line is approximately the same as the pulse width of the signal of the second scan signal line.
  • the signal pulse of the first light emission control signal line differs from the signal pulse of the second light emission control signal line by one or two time units, and one time unit is one row of sub-pixel scanning. time.
  • the first reset subcircuit includes a first transistor, wherein: the control electrode of the first transistor is connected to the first light emission control signal line or the second reset control signal line, and the The first pole of the first transistor is connected to the first reset signal line, and the second pole of the first transistor is connected to the fourth node.
  • the compensation sub-circuit includes a second transistor and a first capacitor, wherein: the control electrode of the second transistor is connected to the first scanning signal line, and the first pole is connected to the third node, the second pole of the second transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the Connect the first power cord.
  • the driving sub-circuit includes a third transistor, wherein: the control electrode of the third transistor is connected to the first node, and the first electrode of the third transistor is connected to the second node , the second pole of the third transistor is connected to the third node.
  • the writing sub-circuit includes a fourth transistor, wherein: the control electrode of the fourth transistor is connected to the second scanning signal line, and the first electrode of the fourth transistor is connected to the data connected to the signal line, and the second pole of the fourth transistor is connected to the second node.
  • the first light emission control sub-circuit includes a fifth transistor, wherein: the control electrode of the fifth transistor is connected to the first light emission control signal line, and the first light emission control signal line of the fifth transistor The pole is connected to the first power line, and the second pole of the fifth transistor is connected to the second node.
  • the second light emission control subcircuit includes a sixth transistor, wherein: the control electrode of the sixth transistor is connected to the second light emission control signal line, and the first The pole is connected to the third node, and the second pole of the sixth transistor is connected to the fourth node.
  • the second reset subcircuit includes a seventh transistor, wherein: the control electrode of the seventh transistor is connected to the reset control signal line, and the first electrode of the seventh transistor is connected to the first The two reset signal lines are connected, and the second pole of the seventh transistor is connected to the second node or the third node.
  • the first reset subcircuit includes a first transistor
  • the compensation subcircuit includes a second transistor and a first capacitor
  • the drive subcircuit includes a third transistor
  • the write subcircuit Including a fourth transistor
  • the first light emission control subcircuit includes a fifth transistor
  • the second light emission control subcircuit includes a sixth transistor
  • the second reset subcircuit includes a seventh transistor, wherein: the first transistor The control pole of the first transistor is connected to the first light emission control signal line or the second reset control signal line, the first pole of the first transistor is connected to the first reset signal line, and the second pole of the first transistor is connected to the The fourth node is connected;
  • the control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first power line; the control electrode of the third transistor is connected
  • At least one of the first transistor, the second transistor, and the seventh transistor is a first type transistor, and the third transistor to the sixth transistor are all second transistors. type transistors, the transistor types of the first type transistor and the second type transistor are different.
  • the first type transistor is an N-type thin film transistor; the second type transistor is a P-type thin film transistor.
  • At least one of the first transistor, the second transistor, and the seventh transistor is an indium gallium zinc oxide thin film transistor, and the third transistor to the sixth transistor are all It is a low temperature polysilicon thin film transistor.
  • An embodiment of the present disclosure also provides a display device, including: the pixel circuit described in any one of the above items.
  • An embodiment of the present disclosure also provides a driving method for a pixel circuit, which is used to drive the above-mentioned pixel circuit, the pixel circuit has multiple scanning periods, and within one scanning period, the driving method includes: in the reset phase , the first reset subcircuit writes the first reset signal to the anode terminal of the light-emitting element in response to the signal of the first light emission control signal line or the second reset control signal line; in the reset phase, the second reset subcircuit responds to the first A signal of a reset control signal line, write a second reset signal to the first pole or the second pole of the driving sub-circuit; the second reset signal is greater than the first reset signal; in the light-emitting phase, the driving sub-circuit responds to The control signal of the first node generates a driving current between the second node and the third node.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1;
  • FIG. 3 is a simulation timing diagram of the first node, the second node, and the third node in the driving method shown in FIG. 2 of the pixel driving circuit in FIG. 1;
  • FIG. 4 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit of the present disclosure
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 8 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 7;
  • FIG. 9 is a simulation timing diagram of the first node, the second node, and the third node in the driving method shown in FIG. 8 of the pixel driving circuit in FIG. 7;
  • FIG. 10 is a structural diagram of an exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 13 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 12;
  • FIG. 14 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 15 is a distribution diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure
  • 16 is a distribution diagram of a pixel driving circuit in another exemplary embodiment of a display panel of the present disclosure.
  • 17 is a distribution diagram of a pixel driving circuit in another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 18 is a partial structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 19 is a structural layout of the first conductive layer in FIG. 18;
  • FIG. 20 is a structural layout of the second conductive layer in FIG. 18;
  • FIG. 21 is a structural layout of the second active layer in FIG. 18;
  • FIG. 22 is a structural layout of the third conductive layer in FIG. 18;
  • FIG. 23 is a structural layout of the fourth conductive layer in FIG. 18;
  • FIG. 24 is a structural layout of the first conductive layer, the second conductive layer, and the second active layer in FIG. 18;
  • FIG. 25 is a structural layout of the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG. 18;
  • Figure 26 is a partial sectional view along the dotted line A in Figure 18;
  • FIG. 27 is one of the structural schematic diagrams of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 28 is the second structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 29 is a schematic structural diagram of a first reset subcircuit provided by an embodiment of the present disclosure.
  • FIG. 30 is a schematic structural diagram of a compensation sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 31 is a schematic structural diagram of a driving sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 32 is a schematic structural diagram of a writing sub-circuit provided by an embodiment of the present disclosure.
  • Fig. 33 is a schematic structural diagram of a first light emission control sub-circuit provided by an embodiment of the present disclosure.
  • Fig. 34 is a schematic structural diagram of a second lighting control sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 35 is one of the structural schematic diagrams of the second reset subcircuit provided by the embodiment of the present disclosure.
  • FIG. 36 is the second structural schematic diagram of the second reset sub-circuit provided by an embodiment of the present disclosure.
  • Fig. 37a is one of the equivalent circuit diagrams of the pixel circuit provided by the embodiment of the present disclosure.
  • Fig. 37b is the second equivalent circuit diagram of the pixel circuit provided by the embodiment of the present disclosure.
  • Fig. 38a is the third equivalent circuit diagram of the pixel circuit provided by the embodiment of the present disclosure.
  • FIG. 38b is the fourth equivalent circuit diagram of the pixel circuit provided by the embodiment of the present disclosure.
  • Fig. 39 is a working timing diagram of the pixel circuit shown in Fig. 37a or Fig. 37b in one scanning period;
  • FIG. 40 is a working timing diagram of the pixel circuit shown in FIG. 38a or 38b in one scanning period
  • FIG. 41 is a schematic diagram of the working state of transistors in the reset phase of the pixel circuit shown in FIG. 37a;
  • FIG. 42 is a schematic diagram of the working state of transistors in the reset phase of the pixel circuit shown in FIG. 37a;
  • FIG. 43 is a schematic diagram of the working state of the transistor in the data writing phase of the pixel circuit shown in FIG. 37a;
  • FIG. 44 is a schematic diagram of the working state of the transistor in the light-emitting phase of the pixel circuit shown in FIG. 37a;
  • FIG. 45 is a schematic flowchart of a driving method for a pixel circuit provided by an embodiment of the present disclosure.
  • Fig. 46 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 47 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 48 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 49 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 50 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 51 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 50 of the present disclosure.
  • FIG. 52 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 53 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 54 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 55 is a schematic diagram of the electrical connection between two adjacent rows of pixel circuits and the same row of reset voltage lines;
  • Fig. 56 is a schematic diagram of the electrical connection between two adjacent columns of pixel circuits and the reset voltage line of the same column;
  • Fig. 57 is a schematic diagram of a reset voltage line shared by pixel circuits in adjacent rows and adjacent columns;
  • Fig. 58 is a schematic diagram of the connection relationship and position relationship between reset voltage lines arranged in a grid and a plurality of pixel circuits;
  • Fig. 59 is a structural diagram of a display device according to at least one embodiment of the present disclosure.
  • Fig. 60 is a structural diagram of a display device according to at least another embodiment of the present disclosure.
  • Fig. 61 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 62 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 63 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 64 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 65 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 66 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 67 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • FIG. 68 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 69 is a working timing diagram of at least one embodiment of the pixel circuit shown in Fig. 68;
  • FIG. 70 is a working timing diagram of at least another embodiment of the pixel circuit shown in FIG. 68;
  • Fig. 71 is a working timing diagram of at least another embodiment of the pixel circuit shown in Fig. 68;
  • Fig. 72 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Fig. 73 is a working timing diagram of at least one embodiment of the pixel circuit shown in Fig. 72;
  • FIG. 74 is a working timing diagram of at least another embodiment of the pixel circuit shown in FIG. 72;
  • Fig. 75 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure.
  • Fig. 76 is a working timing diagram of at least one embodiment of the pixel circuit shown in Fig. 75;
  • Fig. 77 is a structural diagram of a display device according to at least another embodiment of the present disclosure.
  • Fig. 78 is a structural diagram of a display device according to at least another embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the gate of the driving transistor T3 is connected to the first node N1, the first pole is connected to the second node N2, and the second pole is connected to the third node N3; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to The second node N2, the gate is connected to the gate drive signal terminal G2; the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the second node N2, and the gate is connected to the enable signal terminal EM; The first pole of the transistor T2 is connected to the first node N1, the second pole is connected to the third node N3, and the gate is connected to the gate drive signal terminal G1; the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole is connected to the third node N3.
  • the first pole of the seven transistor T7, the gate is connected to the enable signal terminal EM, the second pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first pole of the first transistor T1 The pole is connected to the first node N1, the second pole is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power supply terminal VDD and the first node N1.
  • the pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the power supply terminal VSS.
  • the first transistor T1 and the second transistor T2 may be N-type transistors, for example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors, and the N-type metal oxide transistors have a small leakage current, Therefore, the light-emitting phase can be avoided, and the node N leaks electricity through the first transistor T1 and the second transistor T2.
  • the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, for example, the drive transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be P-type low-temperature polysilicon transistors.
  • Low-temperature polysilicon transistors have high carrier mobility, which is conducive to achieving high resolution, high response speed, high pixel density, and high aperture ratio. display panel.
  • the first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.
  • FIG. 2 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1 .
  • G1 indicates the timing of the gate driving signal terminal G1
  • G2 indicates the timing of the gate driving signal terminal G2
  • Re1 indicates the timing of the first reset signal terminal Re1
  • Re2 indicates the timing of the second reset signal terminal Re2
  • EM indicates enable
  • Da represents the timing of the data signal terminal Da
  • N1 represents the timing of the first node N1.
  • the driving method of the pixel driving circuit may include a first reset phase t1, a threshold compensation phase t2, a second reset phase t3, and a light emitting phase t4.
  • the first reset phase t1 the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the first node N1.
  • the threshold compensation stage t2 the gate drive signal terminal G1 outputs a high-level signal, the gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da outputs a drive signal Write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • the second reset signal terminal Re2 outputs a low-level signal
  • the seventh transistor T7 is turned on
  • the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6.
  • Light-emitting stage t4 the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the gate voltage of the driving transistor is initialized to the initial voltage.
  • the source voltage of the transistor changes accordingly.
  • the gate voltage of the drive transistor changes in different amounts, and thus the source voltage of the drive transistor also changes in different amounts, which in turn causes the Vgs (gate-to-source voltage difference) of the drive transistor to be different after the reset phase is completed.
  • FIG. 3 it is a simulation timing diagram of the first node, the second node, and the third node in the driving method shown in FIG. 2 of the pixel driving circuit in FIG.
  • the timing diagram of the second node N2, N3 represents the timing diagram of the third node N3, wherein Figure 3 specifically shows the timing diagram of each node of the pixel drive circuit shown in Figure 1 under four data signals, the reset phase t1 in Figure 3
  • the first node N1 under the four data signals needs to be reset, and this exemplary embodiment is described by using the timing of each node under the two data signals.
  • the timing of each node is shown as curve Vda1
  • Vda2 the timing of each node is shown as curve Vda2 .
  • the voltage of the first node N1 under the two data signals is pulled down to the initial voltage, because the pull-down variation of the first node N1 under the first data signal is smaller than that of the first node under the second data signal.
  • the pull-down variation of N1 so that the pull-down variation of the second node under the first data signal is smaller than the pull-down variation of the second node N2 under the second data signal, that is, in the reset phase, the voltage of the second node N2 under the first data signal is less than The voltage of the second node N2 under the second data signal, so that under different data signals, the Vgs (gate-source voltage difference) of the driving transistor is different.
  • the pixel driving circuit may include: a driving circuit 1, a first reset circuit 2, and a second reset circuit 3, the driving circuit 1 is connected to the first node N1 and the second node N2, and is used for The voltage difference output drive current of the second node N2; the first reset circuit 2 is connected to the first node N1, the first initial signal terminal Vinit1, and the first reset signal terminal Re1 for responding to the first reset signal terminal
  • the signal of Re1 transmits the signal of the first initial signal terminal Vinit1 to the first node N1;
  • the second reset circuit 3 is connected to the second node N2 and the first power supply terminal VGH, and is used to respond to a control signal to transmit the signal to the first node N1.
  • the signal of the first power supply terminal VGH is transmitted to the second node N2.
  • the pixel driving circuit can use the first reset circuit 2 to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 during the reset phase, and at the same time, use the second reset circuit 3 to transmit the signal of the first initial signal terminal Vinit1 to the first node N1
  • the signal of the first power supply terminal VGH is transmitted to the second node N2, so that under different data signals, the pixel driving circuit can reset the gate-source voltage difference of the driving transistor to the same value, thereby improving the display panel Afterimage and flickering issues.
  • the drive circuit 1 may also be connected to the third node N3, and the drive circuit 1 may include: a drive transistor T3, the gate of which is connected to the first node N1, the first pole is connected to the second node N2, and the second pole is connected to the third node N3.
  • the driving transistor T3 may be a P-type transistor, for example, the driving transistor T3 may be a P-type low-temperature polysilicon transistor, and the driving transistor T3 may input a driving current to the third node according to the voltage difference between the first node N1 and the second node N2.
  • the driving transistor T3 may also be an N-type transistor, and when the driving transistor T3 is an N-type transistor, the driving transistor may move toward The second node inputs a driving current.
  • the driving circuit 1 may further include a plurality of driving transistors, and the plurality of driving transistors may be connected in parallel between the second node and the third node.
  • the first reset circuit 2 may include: a first transistor T1, the gate of the first transistor T1 is connected to the first reset signal terminal Re1, and the first pole is connected to the The first initial signal terminal Vinit1, and the second pole is connected to the first node N1.
  • the turn-on level of the second reset circuit 3 may have the same polarity as the turn-on level of the first reset circuit 2, and the second reset circuit 3 may also be connected to the first reset signal terminal Re1, so
  • the second reset circuit 3 can be configured to transmit the signal of the first power supply terminal VGH to the second node N2 in response to the signal of the first reset signal terminal Re1.
  • the second reset circuit 3 may include: an eighth transistor T8, the gate of the eighth transistor T8 is connected to the first reset signal terminal Re1, and the first pole is connected to the first power supply terminal VGH.
  • the second pole is connected to the second node N2.
  • the pixel driving circuit needs to turn on the driving transistor T3 in the threshold compensation stage, therefore, the voltage difference Vinit1-Vgh between the first initial signal terminal Vinit1 and the first power supply terminal VGH needs to be smaller than the threshold voltage of the driving transistor T3, where , Vinit1 is the voltage of the first initial signal terminal, and Vgh is the voltage of the first power supply terminal VGH.
  • the second reset circuit 3 may also transmit signals of other signal terminals to the second node in response to a control signal, so as to reset the second node.
  • both the first transistor T1 and the eighth transistor T8 can be oxide transistors, for example, the semiconductor material of the first transistor T1 and the eighth transistor T8 can be indium gallium zinc oxide, correspondingly, the first transistor T1 and the eighth transistor T8 may be N-type transistors.
  • the oxide transistor has a small turn-off leakage current, so that the leakage current of the first node N1 through the first transistor T1 and the leakage current of the second node N2 through the eighth transistor T8 can be reduced.
  • the conduction level of the second reset circuit 3 and the conduction level of the first reset circuit 2 may be opposite in polarity.
  • FIG. 5 it is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the second reset circuit 3 can also be connected to the second reset signal terminal Re2, and the second reset circuit 3 can be used to respond to the signal of the second reset signal terminal Re2 to change the signal of the first power supply terminal VGH to transmitted to the second node N2; wherein, the signal polarity of the second reset signal terminal Re2 and the signal polarity of the first reset signal terminal Re1 may be opposite.
  • the first reset circuit 2 may include: an N-type first transistor T1, the gate of the first transistor T1 is connected to the first reset signal terminal Re1, the first pole is connected to the first initial signal terminal Vinit1, and the second pole is connected to the first node N1.
  • the second reset circuit 3 may include: a P-type eighth transistor T8, the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2, the first pole is connected to the first power supply terminal VGH, and the second pole The second node N2 is connected.
  • the pixel drive circuit may further include: a control circuit 5, a coupling circuit 6, the control circuit 5 is connected to the second power supply terminal VDD, the second node N2, the third node N3, the fourth node N4, and the enable signal terminal EM for Transmitting the signal of the second power supply terminal VDD to the second node N2 in response to the signal of the enabling signal terminal EM, and for connecting to the third node N3 in response to the signal of the enabling signal terminal EM and the fourth node N4; the coupling circuit 6 is connected between the second power supply terminal VDD and the first node N1.
  • the pixel driving circuit may further include: a data writing circuit 7, a threshold compensation circuit 8, and the data writing circuit 7 is connected to the second node N2, the data signal terminal Vdata , the first gate drive signal terminal G1, used to transmit the signal of the data signal terminal Vdata to the second node N2 in response to the signal of the first gate drive signal terminal G1; the threshold compensation circuit 8 can be connected to the The first node N1 and the third node N3 are used to connect the first node N1 and the third node N3 in response to a control signal.
  • the data writing circuit 7 and the threshold compensation circuit 8 are used to conduct in the threshold compensation phase to write the compensation voltage Vdata+Vth to the first node N1, wherein Vdata is the voltage of the data signal terminal, and Vth is the threshold voltage of the driving transistor.
  • Vdata is the voltage of the data signal terminal
  • Vth is the threshold voltage of the driving transistor.
  • a data writing circuit may be connected to the third node N3, the data signal terminal Vdata, the second A gate drive signal terminal G1, the data writing circuit is used to transmit the signal of the data signal terminal Vdata to the third node N3 in response to the signal of the first gate drive signal terminal G1, and at the same time, the threshold compensation The circuit 8 is connected to the first node N1 and the second node N2, and the threshold compensation circuit 8 can be used to connect the first node N1 and the second node N2 in response to a control signal.
  • the pixel driving circuit can also write the compensation voltage Vdata+Vth
  • the fourth node N4 can be used to connect a light-emitting unit OLED, the light-emitting unit OLED can be a light-emitting diode, and the other electrode of the light-emitting unit OLED can be connected to the fourth power supply terminal VSS , the voltage of the fourth power supply terminal VSS is lower than the voltage of the second power supply terminal VDD.
  • the pixel driving circuit may further include: a third reset circuit 4, the third reset circuit 4 is connected to the fourth node N4 and the second initial signal terminal Vinit2, and is used to switch the second initial signal terminal Vinit2 to the second initial signal terminal Vinit2 in response to a control signal The signal of is transmitted to the fourth node N4. Wherein, writing the initial signal to the fourth node N4 can eliminate the carriers that are not recombined on the light-emitting interface inside the light-emitting diode, and alleviate the aging of the light-emitting diode.
  • the control circuit 5 may include: a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is connected to the enable signal terminal EM, and the first stage connected to the second power supply terminal VDD, the second pole is connected to the second node N2; the gate of the sixth transistor T6 is connected to the enabling signal terminal EM, the first pole is connected to the third node N3, and the second pole The fourth node N4 is connected.
  • the coupling circuit 6 may include: a third capacitor C3, and the third capacitor C3 is connected between the second power supply terminal VDD and the first node N1.
  • the polarity of the conduction level of the threshold compensation circuit 8 and the conduction level of the data writing circuit 7 can be reversed; the threshold compensation circuit 8 can also be connected to The second gate driving signal terminal G2, the threshold compensation circuit 8 is used to connect the first node N1 and the third node N3 in response to the signal of the second gate driving signal terminal G2; wherein, the The polarity of the signal at the first gate driving signal terminal G1 and the signal at the second gate driving signal terminal G2 may be opposite.
  • the data writing circuit 7 may include: a fourth transistor T4, the gate of the fourth transistor T4 is connected to the first gate drive signal terminal G1, the first pole is connected to the data signal terminal Vdata, and the second pole is connected to the The second node N2;
  • the threshold compensation circuit 8 may include: a second transistor T2, the gate of the second transistor T2 is connected to the second gate drive signal terminal G2, and the first pole is connected to the first node N1, The second pole is connected to the third node N3; wherein, the fourth transistor T4 can be a P-type transistor, for example, the fourth transistor T4 can be a P-type low-temperature polysilicon transistor, and the low-temperature polysilicon transistor has a higher Carrier mobility, so that the response speed of the fourth transistor T4 can be improved; the second transistor T2 can be an N-type transistor, for example, the second transistor T2 can be an oxide transistor, and the semiconductor material of the second transistor T2 can be Indium Gallium Zinc Oxide. Setting the second transistor T2 as an oxide transistor
  • the fourth transistor T4 and the second transistor T2 can also be both N-type transistors or P-type transistors, and correspondingly, the fourth transistor T4 and the second transistor T2 can also share the same Gate drive signal terminal.
  • the third reset circuit 4 can also be connected to the third reset signal terminal Re3, and the third reset circuit 4 can be used to respond to the third reset signal terminal Re3
  • the signal transmits the signal of the second initial signal terminal Vinit2 to the fourth node N4.
  • the third reset circuit 4 may include: a seventh transistor T7, the gate of the seventh transistor T7 is connected to the third reset signal terminal Re3, the first pole is connected to the second initial signal terminal Vinit2, and the second pole is connected to the second initial signal terminal Vinit2. Describe the fourth node N4.
  • the seventh transistor T7 may be a P-type transistor, for example, the seventh transistor T7 may be a P-type low-temperature polysilicon transistor, and the low-temperature polysilicon transistor has a higher carrier mobility, so that the seventh transistor T7 has a higher Fast response time.
  • the first pole of the eighth transistor T8 and the first pole of the fifth transistor T5 are respectively connected to different power supply terminals.
  • FIG. 7 which is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure, the first pole of the eighth transistor T8 and the first pole of the fifth transistor T5 can be connected to the same power supply terminal, that is, the The second power supply terminal VDD may share the first power supply terminal VGH.
  • FIG. 8 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG.
  • the timing of the first reset signal terminal, Re3 indicates the timing of the third reset signal terminal
  • EM indicates the timing of the enable signal terminal.
  • the pixel driving circuit driving method may include four stages: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light emitting stage t4. Among them, in the reset phase t1: the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal output high-level signals, and the second gate drive signal terminal G2 and the third reset signal terminal Re3 output low-level signals.
  • the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, and the first power supply terminal VDD inputs power to the second node N2 signal, the second initial signal terminal Vinit2 inputs the second initial signal to the fourth node, wherein the voltages of the first initial signal and the second initial signal may be the same or different.
  • the threshold compensation stage t2 the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal output high-level signals, and the first reset signal terminal Re1 and the first gate drive signal terminal G1 output low-level signals.
  • the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Vdata writes the compensation voltage Vdata+Vth to the first node N1, wherein Vdata is the voltage of the data signal terminal, and Vth is the threshold voltage of the driving transistor.
  • the buffer stage t3 the enable signal terminal EM, the third reset signal terminal Re3, and the first gate drive signal terminal G1 output high-level signals, and the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals level signal, all transistors are turned off.
  • the third reset signal terminal Re3 and the first gate drive signal terminal G1 output high-level signals, and the enable signal terminal EM, the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals
  • the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the third capacitor C3.
  • the driving method may not include a buffer stage; the first transistor T1 and the seventh transistor T7 may also be turned on in different stages.
  • the duration of the active level (low level) of the first gate drive signal terminal G1 may be shorter than the duration of the active level (high level) of the second gate drive signal terminal G2, in the threshold compensation phase t2, the first gate driving signal terminal G1 can scan a row of pixel driving circuits, and the second gate driving signal terminal G2 can scan multiple rows of pixel driving circuits row by row, for example, two rows of pixel driving circuits.
  • FIG. 9 it is a simulation timing diagram of the first node, the second node, and the third node in the driving method shown in FIG. 8 of the pixel driving circuit in FIG.
  • the timing diagram of the second node N2, N3 represents the timing diagram of the third node N3, wherein, FIG. 9 specifically shows the timing diagram of each node of the pixel driving circuit shown in FIG. 7 under four kinds of data signals, and the reset stage t1 in FIG. 9
  • the first node N1 under the four data signals needs to be reset, and this exemplary embodiment is described by using the timing of each node under the two data signals.
  • FIG. 9 specifically shows the timing diagram of each node of the pixel driving circuit shown in FIG. 7 under four kinds of data signals, and the reset stage t1 in FIG. 9
  • the first node N1 under the four data signals needs to be reset, and this exemplary embodiment is described by using the timing of each node under the two data signals.
  • FIG. 9 specifically shows the timing diagram of each node of the pixel driving circuit
  • This exemplary embodiment also provides a method for driving a pixel driving circuit, for driving the above-mentioned pixel driving circuit, wherein the method includes:
  • the first reset circuit 2 is used to transmit the signal of the first initial signal terminal Vinit1 to the first node N1
  • the second reset circuit 3 is used to transmit the signal of the first power supply terminal VGH to the Describe the second node N2.
  • the pixel driving method has been described in detail above, and will not be repeated here.
  • This exemplary embodiment also provides a display panel, which may include the above-mentioned pixel driving circuit.
  • the display panel can be applied to display devices such as mobile phones, tablet computers, and televisions.
  • this exemplary embodiment provides a pixel driving circuit, as shown in FIG. 10 , which is a structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure, wherein the pixel driving circuit may include: a driving transistor T3 , data writing circuit 7, threshold compensation circuit 8, first capacitor C1, second capacitor C2, the gate of the driving transistor T3 is connected to the first node N1, the first pole is connected to the second node N2, and the second pole is connected to the third node N3; the data writing circuit 7 is connected to the second node N2 and the data signal terminal Vdata, and is used to transmit the signal of the data signal terminal Vdata to the second node N2 in response to the signal of the first gate drive signal terminal G1
  • the threshold compensation circuit 8 is connected to the first node N1, the third node N3, and the second gate drive signal terminal G2, and is used to respond to the signal of the second gate drive signal terminal G2 to communicate with the first node N1 and the third node N3; the first capacitor C1 is connected between the first node
  • the first gate driving signal terminal G1 can output a low-level signal
  • the second gate driving signal terminal G2 can output a high-level signal, thereby realizing writing to the first node N1 Input the compensation voltage Vdata+Vth
  • Vdata is the voltage of the data signal terminal
  • Vth is the threshold voltage of the driving transistor T3.
  • the signal of the first gate drive signal terminal G1 changes from low level to high level, and under the coupling effect of the first capacitor C1, the first node N1 is pulled high by the first gate drive signal terminal G1 ;
  • the signal of the second gate drive signal terminal G2 changes from high level to low level, under the coupling effect of the second capacitor C2, the first node N1 is pulled down by the second gate drive signal terminal G2, due to the first capacitor
  • the capacitance of C1 is greater than the capacitance of the second capacitor C2, therefore, the first node N1 is generally pulled high.
  • the source drive circuit corresponding to the pixel drive circuit only needs to provide a small voltage signal to the data signal terminal to realize the limit gray scale (minimum gray scale or maximum gray scale) display of the pixel drive circuit.
  • the display panel of the pixel driving circuit can have less power consumption.
  • the driving transistor T3 may be a P-type transistor.
  • the driving transistor may be a P-type low-temperature polysilicon transistor.
  • the driving transistor T3 is a P-type transistor, the voltage of the first node N1 is higher than that of the driving transistor T3. The smaller the output current is, that is, the pixel driving circuit can reduce the data signal voltage output by the source driving circuit at 0 gray scale.
  • the driving transistor T3 may also be an N-type transistor, and when the driving transistor T3 is an N-type transistor, the higher the voltage of the first node N1 is, the larger the output current of the driving transistor T3 is, namely
  • the pixel driving circuit can reduce the data signal voltage output by the source driving circuit at the maximum gray scale.
  • the capacitance value of the first capacitor C1 is C1
  • the capacitance value of the second capacitor C2 is C2
  • C1/C2 may be greater than or equal to 1.5 and less than or equal to 4, for example, C1/C2 may be 1.5, 2, 2.3, 2.5, 3, 3.5, 4.
  • the greater the value of C1/C2 the more obvious the effect of the first node N1 being pulled up.
  • Vdata-L0 represents the voltage of the data signal required by each color sub-pixel at gray scale 0
  • ⁇ V represents the difference between the maximum output voltage of the source driver circuit and the voltage of the maximum data signal required at gray scale 0
  • the maximum output voltage of the source drive circuit is 6.89V.
  • C1/C2 is 1.35, 1.73, 2.05, and 2.3.
  • the multiple sets of data corresponding to the same design structure except C1/C2 are different, other structures are the same), and C1/C2 is the data corresponding to 2.2. It is the data under another design structure. According to the table, it can be seen that under the same design structure, the larger C1/C2 is, the more obvious the effect of the first node N1 being pulled up, so the required data signal under 0 gray scale The voltage is smaller.
  • the data writing circuit 7 may include: a P-type fourth transistor T4, for example, the fourth transistor T4 may be a P-type low-temperature polysilicon transistor, and the fourth The gate of the transistor T4 is connected to the first gate drive signal terminal G1, the first pole is connected to the second node N2, and the second pole is connected to the data signal terminal Vdata;
  • the threshold compensation circuit 8 may include: N-type The second transistor T2, for example, the second transistor T2 can be an N-type oxide transistor, the semiconductor material of the oxide transistor can be indium gallium zinc oxide, and the gate of the second transistor T2 is connected to the second gate driver The first pole of the signal terminal G2 is connected to the first node N1, and the second pole is connected to the third node N3.
  • FIG. 11 it is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the pixel driving circuit may also include: a control circuit 5 , a coupling circuit 6 , and a control circuit 5 It can be connected to the second power supply terminal VDD, the second node N2, the third node N3, the fourth node N4, and the enable signal terminal EM, and the control circuit 5 can be used to respond to the signal of the enable signal terminal EM to turn the second
  • the signal of the power supply terminal VDD is transmitted to the second node N2, and is used to connect the third node N3 and the fourth node N4 in response to the signal of the enable signal terminal EM;
  • the coupling circuit 6 can be connected to the between the first node N1 and the second power supply terminal VDD.
  • control circuit 5 may also be configured to transmit the signal of the second power supply terminal VDD to the third node N3 in response to the signal of the enable signal terminal EM, and It is used for connecting the second node N2 and the fourth node N4 in response to the signal of the enable signal terminal EM.
  • the pixel driving circuit may further include: a first reset circuit 2, and the first reset circuit 2 may be connected to the first node N1, the first initial signal terminal Vinit1, the first A reset signal terminal Re1, the first reset circuit 2 can be used to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 in response to the signal of the first reset signal terminal Re1.
  • the fourth node N4 can be used to connect a light emitting unit OLED
  • the pixel drive circuit can further include: a third reset circuit 4 connected to the The fourth node N4, the second initial signal terminal Vinit2, and the third reset signal terminal Re3, the third reset circuit 4 can be used to respond to the signal of the third reset signal terminal Re3 to change the signal of the second initial signal terminal Vinit2 transmitted to the fourth node N4.
  • the other end of the light emitting unit OLED can be connected to the third power supply terminal VSS, and the light emitting unit OLED can be a light emitting diode.
  • Writing the initial signal to the fourth node N4 can eliminate the carriers that are not recombined on the light-emitting interface inside the light-emitting diode, and alleviate the aging of the light-emitting diode.
  • the coupling circuit 6 may include: a third capacitor C3, and the third capacitor C3 is connected between the first node N1 and the second power supply terminal VDD; wherein The capacitance value of the third capacitor C3 may be greater than the capacitance value of the first capacitor C1, and the capacitance value of the third capacitor C3 may be greater than the capacitance value of the second capacitor C2. Setting the third capacitor C3 to a larger capacitance value can increase the charge storage capacity of the third capacitor C3, thereby increasing the maximum duration of the light-emitting phase.
  • the control circuit 5 may include: a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first pole is connected to the second power supply terminal VDD, and the second pole is connected to the second power supply terminal VDD.
  • the second node N2; the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first pole is connected to the third node N3, and the second pole is connected to the fourth node N4.
  • the first reset circuit 2 may include: a first transistor T1, the gate of the first transistor T1 is connected to the first reset signal terminal Re1, the first pole is connected to the first initial signal terminal Vinit1, and the second pole is connected to the first reset signal terminal Vinit1.
  • the first node N1; the third reset circuit 4 may include: a seventh transistor T7, the gate of the seventh transistor T7 is connected to the third reset signal terminal Re3, and the first pole is connected to the second initial signal terminal Vinit2 , the second pole is connected to the fourth node N4.
  • the first transistor T1 and the second transistor T2 can be N-type transistors, and the semiconductor material of the N-type transistors can be indium gallium zinc oxide, and the oxide transistors have a small turn-off leakage current, which can reduce the first The node N1 passes the leakage current of the first transistor T1 and the second transistor T2.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature Polycrystalline silicon transistors, low-temperature polycrystalline silicon transistors have high carrier mobility, which is conducive to the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.
  • the pixel driving circuit may further include: a second reset circuit 3, which may be connected to the second node N2 and the first power supply terminal VGH, and the second reset circuit 3 may be used to respond to a control signal to reset the The signal of the first power supply terminal VGH is transmitted to the second node N2.
  • the conduction level of the first reset circuit and the conduction level of the third reset circuit may have opposite polarities, and the polarities of the signal at the first reset signal terminal Re1 and the third reset signal terminal Re3 may be reversed.
  • the conduction level of the second reset circuit 3 and the conduction level of the first reset circuit 2 may be opposite in polarity; the second reset circuit 3 may also be connected to the third reset signal terminal Re3, The second reset circuit 3 can be configured to transmit the signal of the first power supply terminal VGH to the second node N2 in response to the signal of the third reset signal terminal Re3.
  • the gate voltage of the driving transistor is initialized to the initial voltage.
  • the source voltage of the drive transistor also changes accordingly.
  • the gate voltage of the drive transistor changes in different amounts, and thus the source voltage of the drive transistor also changes in different amounts, which in turn causes the Vgs (gate-to-source voltage difference) of the drive transistor to be different after the reset phase is completed.
  • the Vgs of the driving transistor will affect its threshold voltage, the afterimage problem will occur on the display panel.
  • the pixel driving circuit can use the first reset circuit 2 to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 during the reset phase, and at the same time, use the second reset circuit 3 to transmit the signal of the first initial signal terminal Vinit1 to the first node N1
  • the signal of the first power supply terminal VGH is transmitted to the second node N2, so that under different data signals, the pixel driving circuit can reset the gate-source voltage difference of the driving transistor to the same value, thereby improving the display panel Afterimage problem.
  • the second reset circuit 3 may include: an eighth transistor T8, the gate of the eighth transistor T8 is connected to the third reset signal terminal Re3, and the first pole is connected to the first power supply terminal VGH , the second pole is connected to the second node N2; wherein, the eighth transistor T8 may be a P-type transistor.
  • the conduction level of the second reset circuit may have the same polarity as the conduction level of the first reset circuit, and the second reset circuit may be connected to the first reset signal terminal.
  • the second reset circuit can be used to transmit the signal of the first power supply terminal VGH to the second node in response to the signal of the first reset signal terminal.
  • the eighth transistor may be an N-type transistor, and the semiconductor material of the N-type transistor may be InGaZnO.
  • the first power supply terminal VGH may also share the second power supply terminal VDD, for example, the second reset circuit may be connected to the second power supply terminal VDD.
  • FIG. 13 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 12 .
  • G1 represents the timing of the first gate driving signal terminal
  • G2 represents the timing of the second gate driving signal terminal
  • Re1 represents the timing of the first reset signal terminal
  • Re3 represents the timing of the third reset signal terminal
  • EM represents the timing of the enable signal terminal.
  • the pixel driving circuit driving method may include four stages: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light emitting stage t4.
  • the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal output high-level signals, and the second gate drive signal terminal G2 and the third reset signal terminal Re3 output low-level signals.
  • Level signal, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, and the first power supply terminal VDD inputs power to the second node N2 signal, the second initial signal terminal Vinit2 inputs the second initial signal to the fourth node, wherein the voltages of the first initial signal and the second initial signal may be the same or different.
  • the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal output a high-level signal
  • the first reset signal terminal Re1 outputs a low-level signal
  • the second transistor T2 and the fourth transistor T4 are turned on
  • the data signal terminal Vdata writes the compensation voltage Vdata+Vth to the first node N1, where Vdata is the data
  • Vth is the threshold voltage of the driving transistor.
  • the enable signal terminal EM, the third reset signal terminal Re3, and the first gate drive signal terminal G1 output high-level signals, and the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals. level signal, all transistors are turned off.
  • the light-emitting phase t4 the third reset signal terminal Re3 and the first gate drive signal terminal G1 output high-level signals, and the enable signal terminal EM, the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the duration of the active level (low level) of the first gate drive signal terminal G1 may be shorter than the active level (high level) of the second gate drive signal terminal G2
  • the first gate drive signal terminal G1 can scan a row of pixel drive circuits
  • the second gate drive signal terminal G2 can scan multiple rows of pixel drive circuits row by row, for example, the second gate drive signal Terminal G2 can scan two rows of pixel driving circuits row by row.
  • the driving method may not include a buffer stage; the first transistor T1 and the seventh transistor T7 may also be turned on in different stages.
  • the duration of the active level (low level) of the first gate driving signal terminal G1 may also be equal to the duration of the active level (high level) of the second gate driving signal terminal G2.
  • the pixel driving circuit may further include a fourth capacitor C4, and the first electrode of the fourth capacitor C4 may be connected to the second node N2.
  • the second power supply terminal VDD can charge the fourth capacitor C4, and at the beginning of the reset phase, the fourth capacitor C4 can maintain the high level of the second node N2, so that this setting can speed up the reset The speed at which the first power supply terminal VGH writes a high-level signal to the second node N2 in the stage.
  • the second electrode of the fourth capacitor C4 can be connected to the fifth node N5, and when the equipotential conductive part of the fifth node N5 has a pull-down action before the threshold compensation stage or the initial stage, the fifth node N5 will have an effect on the second node N2.
  • the pull-down effect leads to differences in the voltage of the second node N2 at different positions of the display panel.
  • the equipotential conducting portion of the fifth node N5 may be a first gate line for providing the first gate driving signal terminal G1, and the first gate line may partially overlap with the equipotential conducting portion of the second node N2, so that the second A partial structure of a gate line can be used to form the second electrode of the fourth capacitor C4, and the first gate line changes from a high level to a low level at the initial stage of the threshold compensation phase, so that the first gate line will pull down the second electrode The voltage of the two node N2.
  • This exemplary embodiment can minimize the overlapping area of the equipotential conducting part of the second node N2 and the first gate line, so as to reduce the pull-down effect of the first gate line on the second node N2.
  • the capacitance value C4 of the fourth capacitor C4 may be smaller than the capacitance value of the second capacitor C2, and the fourth capacitor C4 may be 0.5fF-4fF, for example, 0.5fF, 2fF, 4fF.
  • the capacitance value C4 of the fourth capacitor C4 can also be less than half of the capacitance value of the first capacitor C1, for example, the capacitance value C4 of the fourth capacitor C4 can be 1/3, 1/4, 1/5 of the capacitance value of the first capacitor C1 wait.
  • the pixel driving circuit needs to turn on the driving transistor T3 in the threshold compensation stage. Therefore, the voltage difference Vinit1-Vgh between the first initial signal terminal Vinit1 and the first power supply terminal VGH It needs to be lower than the threshold voltage Vth of the driving transistor T3, wherein Vinit1 is the voltage of the first initial signal terminal, and Vgh is the voltage of the first power supply terminal VGH.
  • Vinit1 may be -2 to -6V, for example, -2V, -3V, -4V, -5V, -6V and so on.
  • Vinit1-Vgh can be less than a*Vth, a can be 2-7, for example, a can be 2, 4, 6, 7; Vth can be -2-5V, such as -2V, -3V, -5V and so on. Vgh may be greater than 1.5 times Vth, for example, Vgh may be 1.6 times, 1.8 times, 2 times, etc. of Vth.
  • FIG. 15 it is a distribution diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure.
  • Two adjacent columns of pixel circuits can be connected to the first power supply line VGH extending in the same column direction, and the first power supply line VGH is used to provide the first power supply terminal to the pixel driving circuit, and the first power supply line VGH can be located in the adjacent Between two columns of pixel drive circuits.
  • two pixel circuits in adjacent columns can be mirrored to facilitate wiring.
  • FIG. 16 it is a distribution diagram of a pixel driving circuit in another exemplary embodiment of a display panel of the present disclosure.
  • Two adjacent rows of pixel circuits can be connected to the first power supply line VGH extending in the same row, and the first power supply line VGH is used to provide the first power supply terminal to the pixel driving circuit, and the first power supply line VGH can be located in the adjacent Between the two rows of pixel drive circuits.
  • two pixel circuits in adjacent columns can be mirrored to facilitate wiring.
  • FIG. 17 it is a distribution diagram of a pixel driving circuit in another exemplary embodiment of a display panel of the present disclosure.
  • the display panel may include a plurality of pixel driving circuits P distributed in an array, a plurality of first power lines VGH11, VGH12, VGH21, VGH22, and the first power lines VGH11, VGH12, VGH21, VGH22 may be used to provide the first power terminal.
  • the first power supply lines VGH11 and VGH12 extend along the column direction
  • the first power supply lines VGH21 and VGH22 extend along the row direction. Pixel circuits in two adjacent rows can be connected to the first power supply lines extending in the same row direction.
  • the first power supply line VGH may be located between the above-mentioned two adjacent rows of pixel driving circuits, and the first power supply line extending along the column direction may be connected to intersect with multiple first power supply lines extending along the row direction, so that the multiple power supply lines A grid structure can be formed.
  • the first power line extending along the column direction may be located in the area where the red pixel driving circuit is located.
  • two pixel circuits in adjacent columns can be mirrored to facilitate wiring.
  • This exemplary embodiment also provides a driving method for a pixel driving circuit, for driving the above-mentioned pixel driving circuit, including:
  • a high-level signal is input to the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal G1, and a high-level signal is input to the second gate drive signal terminal G2 and the third reset signal terminal.
  • Terminal Re3 inputs a low-level signal;
  • the threshold compensation stage input a high-level signal to the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal Re3, and input a high-level signal to the first reset signal terminal Re1 and the first gate drive
  • the signal terminal G1 inputs a low-level signal
  • This exemplary embodiment also provides a display panel, wherein the display panel may include the above-mentioned pixel driving circuit.
  • the display panel can be applied to display devices such as mobile phones, tablet computers, and televisions.
  • the pixel drive circuit in the display panel can be shown in Figure 10, wherein the display panel can include a base substrate, a first conductive layer, a second conductive layer, a second active layer, and a third conductive layer stacked in sequence. .
  • the fourth conductive layer wherein an insulating layer may also be provided between the above-mentioned hierarchical structures.
  • Figure 18 is a partial structural layout of an exemplary embodiment of a display panel of the present disclosure
  • Figure 19 is a structural layout of the first conductive layer in Figure 18
  • Figure 20 is a structural layout of the second conductive layer in Figure 18
  • Figure 21 is the structural layout of the second active layer in Figure 18
  • Figure 22 is the structural layout of the third conductive layer in Figure 18
  • Figure 23 is the structural layout of the fourth conductive layer in Figure 18
  • Figure 24 is The structural layout of the first conductive layer, the second conductive layer, and the second active layer in Figure 18, and Figure 25 is the structure of the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 18 territory.
  • the first conductive layer may include a first conductive portion 11 and the first gate line G1, and the first conductive portion 11 may be used to form the gate of the driving transistor T3,
  • the orthographic projection of the first gate line G1 on the base substrate may extend along the first direction X, and the first gate line G1 may be connected to the gate of the fourth transistor T4, for example, a partial structure of the first gate line G1 Can be used to form the gate of the fourth transistor.
  • the second conductive layer may include the second grid line 2G2, and the orthographic projection of the second grid line 2G2 on the base substrate may be along the first direction X extends, the second gate line 2G2 can be connected to the gate of the second transistor, for example, a part of the structure of the second gate line 2G2 can be used to form the bottom gate of the second transistor.
  • the second active layer may include a first active portion 71, a second active portion 72, and a third active portion 73, and the second active portion 72 is connected to Between the first active portion 71 and the third active portion 73, the first active portion 71 can be used to form the channel region of the second transistor T2, and the second gate line 2G2
  • the orthographic projection on the base substrate may cover the orthographic projection of the first active portion 71 on the base substrate.
  • the material of the second active layer may be InGaZnO.
  • the third conductive layer may include the third gate line 3G2, and the orthographic projection of the third gate line 3G2 on the base substrate may be along the first direction X extends, the orthographic projection of the third gate line 3G2 on the base substrate can cover the orthographic projection of the first active portion 71 on the base substrate, and part of the structure of the third gate line 3G2 can be used to form the top gate of the second transistor.
  • the display panel can use the third conductive part as a mask to conduct conductorization treatment on the second active layer, that is, the area of the second active layer covered by the third conductive layer forms the channel region of the transistor, and the second active layer The regions not covered by the third conductive layer form conductor structures.
  • the fourth conductive layer may include a connecting portion 41, and the connecting portion 41 may be connected to the first conductive portion 11 through a via hole H1, and connected to the third active active portion 11 through a via hole H2. Section 73.
  • first conductive layer, first insulating layer 92, second conductive layer, second insulating layer 93, second active layer, third insulating layer 94, third conductive layer, dielectric layer 95, fourth conductive layer Layers are set one after the other.
  • the first insulating layer 92, the second insulating layer 93, and the third insulating layer 94 may include a silicon oxide layer.
  • the dielectric layer 95 may include a silicon nitride layer.
  • the material of the fourth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminate, etc., or may be a titanium/aluminum/titanium laminate .
  • the material of the first conductive layer, the second conductive layer, and the third conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminated layers.
  • the first gate line G1 may include a first extension portion G11, and the orthographic projection of the first extension portion G11 on the base substrate may be aligned with the third active portion 73
  • the orthographic projections on the base substrate coincide, the first extension part G11 can be used to form the first electrode of the first capacitor C1, and the third active part 73 can be used to form the first The second electrode of capacitor C1.
  • the second gate line 2G2 may include a second extension portion 2G22, and the orthographic projection of the second extension portion 2G22 on the base substrate may be the same as that of the second active portion 72 on the base substrate.
  • the orthographic projections coincide, and the orthographic projection of the third grid line 3G2 on the base substrate is located on one side of the orthographic projection of the second active portion 72 on the base substrate, that is, the third grid line
  • the orthographic projection of 3G2 on the base substrate does not overlap with the orthographic projection of the second active portion 72 on the base substrate.
  • the orthographic projection on the base substrate may be located on one side of the orthographic projection of the second active portion 72 on the base substrate in the second direction Y, and the second direction Y may intersect the first direction X, for example , the second direction Y may be perpendicular to the first direction X.
  • the second extension part 2G22 can be used to form a part of the first electrode of the second capacitor C2, and the second active part 72 can be used to form a part of the second electrode of the second capacitor C2; the third gate
  • the line 3G2 may include a third extension 3G23, the connecting portion 41 may include a fourth extension 414, and the orthographic projection of the third extension 3G23 on the base substrate may be in the same position as the fourth extension 414.
  • the orthographic projections on the base substrate coincide, the third extension 3G23 can be used to form part of the first electrode of the second capacitor C2, and the fourth extension 414 can be used to form the second capacitor C2. Part of the second electrode of C2.
  • the size of the orthographic projection of the third active portion 73 on the base substrate in the first direction X may be larger than the size of the orthographic projection of the second active portion 72 on the base substrate in the first direction X.
  • the size in the first direction X this setting can increase the capacitance value of the first capacitor C1, wherein, this exemplary embodiment can adjust the orthographic projection of the third active portion 73 on the base substrate in the first
  • this exemplary embodiment can also adjust the capacitance value of the first capacitor C1 by adjusting the thicknesses of the first insulating layer 92 and the second insulating layer 93 at the third active portion 73, for example, this exemplary embodiment can reduce The thickness of the first insulating layer 92 and/or the second insulating layer 93 located at the third active portion 73 is reduced to increase the capacitance of the first capacitor C1.
  • the capacitance value of the second capacitor can also be adjusted by adjusting the size of the orthographic projection of the fourth extension 414 on the base substrate in the first direction X.
  • the orthographic projection of the fourth extension 414 on the base substrate The smaller the size projected on the first direction X, the smaller the capacitance value of the second capacitor, and the size of the orthographic projection of the fourth extension 414 on the base substrate in the first direction can be 2um-4um, for example, 4um , 3.7um, 3.5um, 2.95um, 2.2um, 2um.
  • this exemplary embodiment can also adjust the capacitance value of the second capacitor by adjusting the size of the orthographic projection of the second extension part 2G22 on the base substrate in the second direction Y.
  • the second extension part 2G22 is on the base substrate The smaller the size of the orthographic projection on is in the second direction Y, the smaller the capacitance value of the second capacitor.
  • the orthographic projection of the third grid line 3G2 on the base substrate covers the orthographic projection of the second grid line 2G2 on the base substrate, although , the orthographic projection of the second grid line 2G2 in this area on the base substrate overlaps with the orthographic projection of the fourth extension part 414 on the base substrate, but due to the shielding effect of the third grid line 3G2, the second grid line 2G2 in this area
  • the change in the area of the orthographic projection of the second gate line 2G2 on the base substrate will not affect the capacitance value of the second capacitor.
  • the orthographic projection of the third active portion 73 on the base substrate covers the orthographic projection of the connection portion 41 on the base substrate, although the connection portion in this area
  • the orthographic projection of 41 on the base substrate overlaps with the orthographic projection of the first extension portion G11 on the base substrate, but due to the shielding effect of the third active portion 73, the connecting portion 41 in this area is The projected area change will not affect the capacitance value of the first capacitor.
  • FIGS. 27-45 they are explanatory drawings of another set of exemplary embodiments of the pixel driving circuit of the present disclosure.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • connection includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • FIG. 27 and FIG. 28 are schematic structural diagrams of two pixel circuits according to exemplary embodiments of the present disclosure.
  • the pixel circuits provided by the embodiments of the present disclosure include: a driving subcircuit, a first reset subcircuit, The second reset subcircuit and the light emitting element.
  • the driving sub-circuit is respectively connected to the first node N1, the second node N2 and the third node N3, and is configured to generate a driving circuit between the second node N2 and the third node N3 in response to the control signal of the first node N1. current;
  • the first reset subcircuit is respectively connected to the first reset signal line INIT1 and the anode terminal of the light emitting element, and is also connected to the first light emission control signal line EM1 or the second reset control signal line Reset2, and is configured to respond to the first light emission control signal
  • the signal of the line EM1 or the second reset control signal line Reset2 writes the first reset signal provided by the first reset signal line INIT1 to the anode end of the light-emitting element;
  • the second reset subcircuit is respectively connected to the first reset control signal line Reset1 and the second reset signal line INIT2, and is also connected to the second node N2 or the third node N3, and is configured to respond to the signal of the first reset control signal line Reset1 , write the second reset signal provided by the second reset signal line INIT2 into the first pole or the second pole of the driving sub-circuit; the second reset signal is greater than the first reset signal.
  • the absolute value of the second reset signal is greater than 1.5 times the threshold voltage of the driving sub-circuit.
  • the magnitude of the second reset signal is greater than zero.
  • the second reset signal is generally a reset voltage of 4 to 10V
  • the first reset signal is generally a reset voltage of -2V to -6V
  • the threshold voltage of the driving sub-circuit is generally -5V to -2V.
  • the threshold voltage of the driving sub-circuit may be -3V.
  • the pixel circuit further includes a writing subcircuit, a compensation subcircuit, a first light emission control subcircuit and a second light emission control subcircuit.
  • the writing sub-circuit is respectively connected with the second scanning signal line G2, the data signal line Data and the second node N2, and is configured to write the data signal line to the second node N2 in response to the signal of the second scanning signal line G2.
  • the data signal of Data is respectively connected with the second scanning signal line G2, the data signal line Data and the second node N2, and is configured to write the data signal line to the second node N2 in response to the signal of the second scanning signal line G2.
  • the data signal of Data is respectively connected with the second scanning signal line G2, the data signal line Data and the second node N2, and is configured to write the data signal line to the second node N2 in response to the signal of the second scanning signal line G2.
  • the compensation sub-circuit is respectively connected to the first power supply line VDD, the first scanning signal line G1, the first node N1 and the third node N3, and is configured to respond to the signal of the first scanning signal line G1 to connect the first node of the third node N3 to A reset signal or a second reset signal is written into the first node N1; and is also configured to compensate the first node N1 in response to the signal of the first scanning signal line G1.
  • the first light emission control subcircuit is respectively connected to the first light emission control signal line EM1, the first power supply line VDD and the second node N2, and is configured to provide the second node N2 with the second light emission control signal in response to the signal of the first light emission control signal line EM1.
  • the second light emission control subcircuit is respectively connected to the second light emission control signal line EM2, the third node N3 and the fourth node N4, and is configured to control the first A reset signal is written into the third node N3; and is also configured to allow a driving current to pass between the third node N3 and the fourth node N4 in response to a signal of the second light emission control signal line EM2.
  • the driving subcircuit when the second reset subcircuit writes the second reset signal to the second node N2, the driving subcircuit is further configured to, in response to the control signal of the first node N1, set the second node N2 to The second reset signal is written into the third node N3.
  • one end of the light emitting element is connected to the fourth node N4 , and the other end of the light emitting element is connected to the second power line VSS.
  • the first reset subcircuit includes a first transistor T1.
  • control pole of the first transistor T1 is connected to the first light emission control signal line EM1 or the second reset control signal line Reset2 (not shown in the figure), and the first pole of the first transistor T1 is connected to the first reset signal line INIT1 , the second pole of the first transistor T1 is connected to the fourth node N4.
  • FIG. 29 An exemplary structure of the first reset subcircuit is shown in FIG. 29 .
  • the implementation of the first reset subcircuit is not limited thereto, as long as its function can be realized.
  • the compensation subcircuit includes a second transistor T2 and a first capacitor C1 .
  • control electrode of the second transistor T2 is connected to the first scanning signal line G1
  • first electrode of the second transistor T2 is connected to the third node N3
  • second electrode of the second transistor T2 is connected to the first node N1.
  • One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first power line VDD.
  • FIG. 30 An exemplary structure of the compensation subcircuit is shown in FIG. 30 .
  • the implementation of the compensation sub-circuit is not limited thereto, as long as its function can be realized.
  • the driving subcircuit includes a third transistor T3.
  • control electrode of the third transistor T3 is connected to the first node N1
  • first electrode of the third transistor T3 is connected to the second node N2
  • second electrode of the third transistor T3 is connected to the third node N3.
  • FIG. 31 An exemplary structure of the driver subcircuit is shown in FIG. 31 .
  • the implementation of the driving sub-circuit is not limited to this, as long as its function can be realized.
  • the writing sub-circuit includes a fourth transistor T4.
  • control electrode of the fourth transistor T4 is connected to the second scanning signal line G2
  • first electrode of the fourth transistor T4 is connected to the data signal line Data
  • second electrode of the fourth transistor T4 is connected to the second node N2.
  • FIG. 32 An exemplary structure of the write subcircuit is shown in FIG. 32 .
  • the implementation of the writing sub-circuit is not limited thereto, as long as its function can be realized.
  • the first light emission control subcircuit includes a fifth transistor T5.
  • control electrode of the fifth transistor T5 is connected to the first light emission control signal line EM1 , the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2 .
  • FIG. 33 An exemplary structure of the first lighting control subcircuit is shown in FIG. 33 .
  • the implementation of the first light emission control sub-circuit is not limited thereto, as long as its function can be realized.
  • the second light emission control subcircuit includes a sixth transistor T6.
  • control electrode of the sixth transistor T6 is connected to the second light emission control signal line EM2 , the first electrode of the sixth transistor T6 is connected to the third node N3 , and the second electrode of the sixth transistor T6 is connected to the fourth node N4 .
  • FIG. 34 An exemplary structure of the second lighting control subcircuit is shown in FIG. 34 .
  • the implementation of the second light emission control sub-circuit is not limited thereto, as long as its function can be realized.
  • the second reset subcircuit includes a seventh transistor T7.
  • control electrode of the seventh transistor T7 is connected to the reset control signal line Reset, the first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the second node N2.
  • the second reset subcircuit includes a seventh transistor T7.
  • control electrode of the seventh transistor T7 is connected to the reset control signal line Reset
  • first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2
  • second electrode of the seventh transistor T7 is connected to the third node N3.
  • FIG. 35 and FIG. 36 Two exemplary structures of the second reset subcircuit are shown in FIG. 35 and FIG. 36 . Those skilled in the art can easily understand that the implementation of the second reset subcircuit is not limited thereto, as long as its function can be realized.
  • the first reset subcircuit includes a first transistor T1
  • the compensation subcircuit includes a second transistor T2 and a first capacitor C1
  • the driving subcircuit includes a third transistor T3.
  • the write subcircuit includes a fourth transistor T4
  • the first light emission control subcircuit includes a fifth transistor T5
  • the second light emission control subcircuit includes a sixth transistor T6
  • the second reset subcircuit includes a seventh transistor T7.
  • control electrode of the first transistor T1 is connected to the first light emission control signal line EM1
  • first electrode of the first transistor T1 is connected to the first reset signal line INIT1
  • second electrode of the first transistor T1 is connected to the fourth node N4.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line G1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1.
  • One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first power line VDD.
  • the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the second scanning signal line G2, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the control electrode of the fifth transistor T5 is connected to the first light emission control signal line EM1 , the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2 .
  • the control electrode of the sixth transistor T6 is connected to the second light emission control signal line EM2 , the first electrode of the sixth transistor T6 is connected to the third node N3 , and the second electrode of the sixth transistor T6 is connected to the fourth node N4 .
  • the control electrode of the seventh transistor T7 is connected to the first reset control signal line Reset1, the first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the second node N2 or the third node N2. Node N3 is connected.
  • Figure 37a and Figure 37b show two examples of the first reset subcircuit, compensation subcircuit, drive subcircuit, write subcircuit, first light emission control subcircuit, second light emission control subcircuit, and second reset subcircuit sexual structure.
  • Those skilled in the art can easily understand that the implementation manners of the above sub-circuits are not limited thereto, as long as their respective functions can be realized. Since the number of transistors in the pixel circuit of the present disclosure is small, the occupied space of the pixel circuit is small, thereby improving the pixel resolution of the display device.
  • the second reset signal line INIT2 may be the same voltage line as at least one of the following: the first power supply line VDD, the first light emission control signal line EM1 , the second light emission control signal line EM2 or the third power supply line. line, the third power supply line provides a third power supply voltage, and the third power supply voltage is greater than the first reset voltage provided by the first reset signal line INIT1.
  • the pulse width of the signal of the reset control signal line Reset is substantially the same as the pulse width of the signal of the second scanning signal line G2.
  • the signal pulse of the first light emission control signal line EM1 is different from the signal pulse of the second light emission control signal line EM2 by one or two time units h, and one time unit h is the scanning time of a row of sub-pixels.
  • the first reset subcircuit includes a first transistor T1
  • the compensation subcircuit includes a second transistor T2 and a first capacitor C1
  • the driving subcircuit includes a third transistor T3.
  • the write subcircuit includes a fourth transistor T4
  • the first light emission control subcircuit includes a fifth transistor T5
  • the second light emission control subcircuit includes a sixth transistor T6
  • the second reset subcircuit includes a seventh transistor T7.
  • control electrode of the first transistor T1 is connected to the second reset control signal line Reset2, the first electrode of the first transistor T1 is connected to the first reset signal line INIT1, and the second electrode of the first transistor T1 is connected to the fourth node N4. .
  • the control electrode of the second transistor T2 is connected to the first scanning signal line G1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1.
  • One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first power line VDD.
  • the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the second scanning signal line G2, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the control electrode of the fifth transistor T5 is connected to the first light emission control signal line EM1 , the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2 .
  • the control electrode of the sixth transistor T6 is connected to the second light emission control signal line EM2 , the first electrode of the sixth transistor T6 is connected to the third node N3 , and the second electrode of the sixth transistor T6 is connected to the fourth node N4 .
  • the control electrode of the seventh transistor T7 is connected to the first reset control signal line Reset1, the first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the second node N2 or the third node N2. Node N3 is connected.
  • Figure 38a and Figure 38b show the first reset subcircuit, compensation subcircuit, drive subcircuit, write subcircuit, first light emission control subcircuit, second light emission control subcircuit, and the other two reset subcircuits Exemplary structure.
  • Figure 38a and Figure 38b show the first reset subcircuit, compensation subcircuit, drive subcircuit, write subcircuit, first light emission control subcircuit, second light emission control subcircuit, and the other two reset subcircuits Exemplary structure.
  • the light-emitting element EL can be an organic light-emitting diode (Organic Light Emitting Diode, OLED), and can also be a sub-millimeter light-emitting diode (Mini Light Emitting Diodes), a micro light-emitting diode (Micro Light Emitting Diodes), a quantum Other types of light-emitting diodes such as Quantum-dot Light Emitting Diodes (QLED).
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • the structure of the light emitting element EL needs to be designed and determined according to the actual application environment, which is not limited here.
  • the light-emitting element EL is an organic light-emitting diode as an example.
  • At least one of the first transistor T1, the second transistor T2, and the seventh transistor T7 is a first-type transistor, and the first-type transistor includes an N-type transistor or a P-type transistor, and the third transistor T3 to The sixth transistor T6 is a second-type transistor, the second-type transistor includes a P-type transistor or an N-type transistor, and the transistor type of the second-type transistor is different from that of the first-type transistor, that is, when the first-type transistor is an N-type transistor , the second-type transistor is a P-type transistor, and when the first-type transistor is a P-type transistor, the second-type transistor is an N-type transistor.
  • the first transistor T1 and the second transistor T2 are both N-type thin film transistors
  • the third transistor T3 to the seventh transistor T7 are all P-type thin film transistors.
  • the first transistor T1 , the second transistor T2 and the seventh transistor T7 are all N-type thin film transistors, and the third transistor T3 to the sixth transistor T6 are all P-type thin film transistors.
  • the second transistor T2 is an N-type thin film transistor
  • the first transistor T1 and the third transistor T3 to the seventh transistor T7 are all P-type thin film transistors.
  • the N-type thin film transistor can be a low temperature polysilicon (Low Temperature Poly Silicon, LTPS) thin film transistor (Thin Film Transistor, TFT), and the P-type thin film transistor can be an Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide) , IGZO) thin film transistor; or, the N-type thin film transistor may be an IGZO thin film transistor, and the P-type thin film transistor may be an LTPS thin film transistor.
  • LTPS Low Temperature Poly Silicon
  • TFT Thin Film Transistor
  • IGZO Indium Gallium Zinc Oxide
  • IGZO Indium Gallium Zinc Oxide
  • the N-type thin film transistor may be an IGZO thin film transistor
  • the P-type thin film transistor may be an LTPS thin film transistor.
  • the first transistor T1 and the second transistor T2 are all IGZO thin film transistors
  • the third transistor T3 to the seventh transistor T7 are all LTPS thin film transistors.
  • the indium gallium zinc oxide thin film transistor generates less leakage current than the low temperature polysilicon thin film transistor, therefore, the first transistor T1 and the second transistor T2 are set as indium gallium zinc oxide thin film transistors, which can Significantly reduce the leakage of the control electrode of the drive transistor during the light-emitting phase, thereby improving the problem of low-frequency, low-brightness flickering of the display panel.
  • the first transistor T1 , the second transistor T2 and the seventh transistor T7 are all IGZO thin film transistors, and the third transistor T3 to the sixth transistor T6 are all LTPS thin film transistors.
  • the second transistor T2 is an IGZO thin film transistor
  • the first transistor T1 and the third transistor T3 to the seventh transistor T7 are all LTPS thin film transistors.
  • the first capacitor C1 may be a liquid crystal capacitor formed by a pixel electrode and a common electrode, or may be an equivalent capacitor formed by a liquid crystal capacitor formed by a pixel electrode and a common electrode and a storage capacitor. This is not limited.
  • FIG. 39 is a working timing diagram of the pixel circuit shown in FIG. 37a or FIG. 37b in one scanning period.
  • the first transistor T1 and the second transistor T2 are N-type transistors
  • the third transistor T3 to the seventh transistor T7 are all P-type transistors as an example, combined with the pixel circuit shown in FIG. 11a and the working timing diagram shown in FIG. 39 describe the working process of a pixel circuit in one frame period.
  • the pixel circuit provided by the embodiment of the present disclosure includes 7 transistor units (T1 ⁇ T7), 1 capacitor unit (C1) and 3 voltage lines (VDD, VSS, INIT1, because the second reset signal line INIT2 can be the same voltage line as any one of the first power supply line VDD, the first light emission control signal line EM1 and the second light emission control signal line EM2, so the second reset signal line INIT2 is not included in the above three voltage lines ), wherein the first power line VDD continuously provides a high-level signal, the second power line VSS continuously provides a low-level signal, and the first reset signal line INIT1 provides a first reset voltage (initial voltage signal).
  • its working process includes:
  • the first reset control signal line Reset1 and the first light emission control signal line EM1 are at high level, and the second light emission control signal line EM2 is low level.
  • the first light emission control signal line EM1 is at a high level, which turns on the first transistor T1 and resets the fourth node N4 (ie, the anode terminal of the light emitting element EL) to the first reset voltage of the first reset signal line INIT1 .
  • the second light emission control signal line EM2 is low level, so that the sixth transistor T6 is turned on; the first scanning signal line G1 is high level, so that the second transistor T2 is turned on, and the first node N1 (that is, the third transistor T3 The gate and one terminal of the first capacitor C1) and the third node N3 are reset to the first reset voltage of the first reset signal line INIT1.
  • the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are kept off, as shown in FIG. 41 .
  • the first scanning signal line G1, the second scanning signal line G2, the first light emission control signal line EM1 and the second light emission control signal line EM2 are at high level, and the first reset control signal line Reset is low level.
  • the second light emission control signal line EM2 is at a high level, so that the sixth transistor T6 is turned off.
  • the first reset control signal line Reset1 is at a low level, so that the seventh transistor T7 is turned on (this sequence is described by taking the seventh transistor T7 as a P-type thin film transistor as an example, when the seventh transistor T7 is an N-type thin film transistor,
  • the first reset control signal line Reset1 provides a high-level signal in the second stage t2, and provides a low-level signal in other stages), and resets the second node N2 to a second reset voltage, wherein the second reset voltage can be the first The voltage signal provided by the power line VDD, the first light emission control signal line EM1, the second light emission control signal line EM2 or the third power line, the second reset voltage is greater than the first reset voltage, because the first node N1 is the first reset signal line
  • the first reset voltage of INIT1 the third transistor T3 is turned on, the first scanning signal line G1 is at a high level, the second transistor T2 is turned on, and the voltage of the second node N2 is transmitted through the third transistor T3 and the second
  • the first scanning signal line G1, the first reset control signal line Reset1, the first light emission control signal line EM1 and the second light emission control signal line EM2 are at high level, and the second scanning signal line Line G2 is low.
  • the second scanning signal line G2 is at low level, so that the fourth transistor T4 is turned on, and the data voltage signal Vdata output by the data signal line Data is provided by the turned-on fourth transistor T4, third transistor T3 and second transistor T2. to the first node N1, and store the sum of the data voltage signal Vdata output from the data signal line Data and the threshold voltage Vth of the third transistor T3 in the first capacitor C1.
  • the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 are kept off, as shown in FIG. 43 .
  • the second scanning signal line G2 and the first reset control signal line Reset1 are at high level, and the first scanning signal line G1, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 is low level.
  • the first light emission control signal line EM1 is at a low level, so that the fifth transistor T5 is turned on, the first transistor T1 is turned off, and the second light emission control signal line EM2 is at a low level, so that the sixth transistor T6 is turned on, and the first power line
  • the power supply voltage output by VDD provides a driving voltage to the fourth node N4 (ie, the anode terminal of the light emitting element EL) through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6 to drive the light emitting element EL to emit light.
  • the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 are kept off, as shown in FIG. 44 .
  • FIG. 40 is a working timing diagram of the pixel circuit shown in FIG. 38a or FIG. 38b in one scan period.
  • the second transistor T2 in the pixel circuit provided by the embodiment of the present disclosure as an N-type transistor
  • the first transistor T1, and the third transistor T3 to the seventh transistor T7 as P-type transistors as an example, combined with the pixel circuit shown in FIG. 38a and the working timing diagram shown in FIG. 40 describe the working process of a pixel circuit in one frame period.
  • the pixel circuit provided by the embodiment of the present disclosure includes 7 transistor units (T1 ⁇ T7), 1 capacitor unit (C1) and 3 voltage lines (VDD, VSS, INIT1, because the second reset signal line INIT2 can be the same voltage line as any one of the first power supply line VDD, the first light emission control signal line EM1 and the second light emission control signal line EM2, so the second reset signal line INIT2 is not included in the above three voltage lines ), wherein the first power line VDD continuously provides a high-level signal, the second power line VSS continuously provides a low-level signal, and the first reset signal line INIT1 provides a first reset voltage (initial voltage signal).
  • its working process includes:
  • the first stage A1 that is, the reset stage, the first scanning signal line G1, the second scanning signal line G2, the first reset control signal line Reset1 and the first light emission control signal line EM1 are at high level, and the second reset control signal line Reset2 And the second light emission control signal line EM2 is at low level.
  • the first transistor T1, the sixth transistor T6, and the second transistor T2 are turned on, and the fourth node N4 (ie, the anode terminal of the light-emitting element EL), the third node N3, and the first node N1 (ie, the gate of the third transistor T3) are turned on. and one terminal of the first capacitor C1) is reset to the first reset voltage of the first reset signal line INIT1.
  • the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are kept off.
  • the first scanning signal line G1, the second scanning signal line G2, the second reset control signal line Reset2, the first light emission control signal line EM1 and the second light emission control signal line EM2 are at high voltage. level, the first reset control signal line Reset1 is at low level. The second light emission control signal line EM2 is at a high level, so that the sixth transistor T6 is turned off.
  • the first reset control signal line Reset1 is at a low level, so that the seventh transistor T7 is turned on (this sequence is described by taking the seventh transistor T7 as a P-type thin film transistor as an example, when the seventh transistor T7 is an N-type thin film transistor,
  • the first reset control signal line Reset1 provides a high-level signal in the second stage A2, and provides a low-level signal in other stages), and resets the second node N2 to the second reset voltage, wherein the second reset voltage can be the first The voltage signal provided by the power line VDD, the first light emission control signal line EM1, the second light emission control signal line EM2 or the third power line, the second reset voltage is greater than the first reset voltage, because the first node N1 is the first reset signal line
  • the first reset voltage of INIT1 the third transistor T3 is turned on, the first scanning signal line G1 is at a high level, the second transistor T2 is turned on, and the voltage of the second node N2 is transmitted through the third transistor T3 and the second transistor T
  • the first scanning signal line G1, the second reset control signal line Reset2, the first reset control signal line Reset1, the first light emission control signal line EM1 and the second light emission control signal line EM2 are: High level, the second scanning signal line G2 is low level. At this time, the second scanning signal line G2 is at low level, so that the fourth transistor T4 is turned on, and the data voltage signal Vdata output by the data signal line Data is provided by the turned-on fourth transistor T4, third transistor T3 and second transistor T2. to the first node N1, and store the sum of the data voltage signal Vdata output from the data signal line Data and the threshold voltage Vth of the third transistor T3 in the first capacitor C1. At this stage, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are kept off.
  • the fourth stage A4 that is, the light-emitting stage, the second scanning signal line G2, the second reset control signal line Reset2 and the first reset control signal line Reset1 are at high level, the first scanning signal line G1, the first light-emitting control signal line EM1 and the second light emission control signal line EM2 is at low level.
  • the first light emission control signal line EM1 is at low level, so that the fifth transistor T5 is turned on, and the second reset control signal line Reset2 is at high level.
  • the first transistor T1 is turned off, the second light emission control signal line EM2 is at a low level, and the sixth transistor T6 is turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and The sixth transistor T6 provides a driving voltage to the fourth node N4 (ie, the anode terminal of the light emitting element EL) to drive the light emitting element EL to emit light.
  • the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 are kept off.
  • the driving current flowing through the third transistor T3 (ie, the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata+Vth, the driving current of the third transistor T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the first electrode of the third transistor T3.
  • the threshold voltage of the three transistors T3, Vdata is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the first power line VDD.
  • the current I flowing through the light-emitting element EL has nothing to do with the threshold voltage Vth of the third transistor T3, which eliminates the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensures the uniformity of brightness.
  • the pixel circuit in the embodiment of the present disclosure through the drive transistor reset stage, The third transistor T3 (driving transistor) increases a large bias voltage to improve hysteresis, so that the brightness of the screen can be maintained when switching between high and low frequencies, and the risk of flicker (Flicker) can be reduced.
  • the second light emission control signal line EM2 in the upper row of sub-pixels is electrically connected to the first light emission control signal line EM1 in the next row of sub-pixels, and in the upper row of sub-pixels
  • the second scanning signal line G2 is electrically connected to the first reset control signal line Reset1 in the next row of sub-pixels.
  • An embodiment of the present disclosure also provides a method for driving a pixel circuit, which is used to drive the aforementioned pixel circuit.
  • the pixel circuit has multiple scan periods. In one scan period, as shown in FIG. 45 , the The driving method includes step 100 to step 400 .
  • step 100 includes: in the reset phase, the first reset subcircuit writes the first reset signal to the anode terminal (that is, the fourth node) of the light-emitting element in response to the signal of the first light-emitting control signal line or the second reset control signal line. Signal.
  • step 100 further includes: the second light emission control subcircuit writes the first reset signal of the fourth node into the third node in response to the signal of the second light emission control signal line; the compensation subcircuit Writing the first reset signal of the third node into the first node in response to the signal of the first scan signal line.
  • Step 200 includes: in the reset phase, the second reset subcircuit responds to the signal of the first reset control signal line, writing inputting a second reset signal; the second reset signal is greater than the first reset signal.
  • step 100 further includes: the compensation subcircuit writes the second reset signal of the third node into the first node in response to the signal of the first scanning signal line.
  • the second reset signal may be a signal derived from at least one of the following voltage lines: a first power line, a first light emission control signal line, a second light emission control signal line or a third power line.
  • Step 300 includes: in the light-emitting phase, the driving sub-circuit generates a driving current between the second node and the third node in response to the control signal of the first node
  • the method before step 300, further includes: in the data writing phase, the writing subcircuit writes a data signal to the second node in response to the signal of the second scanning signal line; compensating The sub-circuit compensates the first node in response to the signal of the first scanning signal line.
  • step 300 further includes: in the light-emitting phase, the first light-emitting control subcircuit provides the signal of the first power line to the second node in response to the signal of the first light-emitting control signal line. Signal; the second light emission control sub-circuit allows a driving current to pass between the third node and the fourth node in response to the signal of the second light emission control signal line.
  • the second reset signal is written into the first pole or the second pole of the driving subcircuit in response to the signal of the first reset control signal line through the second reset subcircuit Adding a large bias voltage to the driving sub-circuit improves hysteresis, so that the brightness of the screen can be maintained when switching between high and low frequencies, reducing the risk of flickering, and improving the display effect of the display device under high and low gray scales.
  • the pixel circuit occupies less space, thereby improving the pixel resolution of the display device.
  • FIGS. 46-60 are explanatory drawings of another set of exemplary embodiments of the pixel driving circuit of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11 , a first control circuit 12 , a compensation control circuit 13 and a first initialization circuit 14 ;
  • the first control circuit 12 is electrically connected to the first scanning line S1, the control terminal of the driving circuit 11, and the connection node N0, and is used to control the first scanning signal provided by the first scanning line S1, controlling the communication between the control terminal of the driving circuit 11 and the connection node N0;
  • the compensation control circuit 13 is respectively electrically connected to the second scanning line S2, the connection node N0 and the first end of the driving circuit 11, and is used for controlling the second scanning signal provided on the second scanning line S2 Next, controlling the connection between the connection node N0 and the first end of the driving circuit 11;
  • the first initialization circuit 14 is electrically connected to the initialization control line R1, the first initialization voltage line and the connection node N0 respectively, and is used to control the initialization control signal provided by the initialization control line R1 to connect the first Write the first initialization voltage Vi1 provided by an initialization voltage line into the connection node N0;
  • the driving circuit 11 is used to control the communication between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the potential of the control terminal.
  • the first node N1 is a node connected to the control terminal of the driving circuit 11 .
  • the first control circuit 12 is directly electrically connected to the first node N1
  • neither the first initialization circuit 14 nor the compensation control circuit 13 is directly electrically connected to the first node N1
  • the display cycle includes an initialization phase and a data writing phase;
  • the driving method includes:
  • the first control circuit 12 controls the communication between the control terminal of the driving circuit 11 and the connection node N0, and the first initialization circuit 14 controls the first initialization
  • the voltage Vi1 is written into the connection node N0, so that the first initialization voltage Vi1 is written into the control terminal of the driving circuit 11, so that the driving circuit 11 can control its first terminal and the driving circuit 11 at the beginning of the data writing phase. communication between the second ends of the circuit;
  • the first control circuit 12 controls the communication between the control terminal of the driving circuit 11 and the connection node N0, and the compensation control circuit 13 controls all the terminals under the control of the second scanning signal.
  • the connecting node N0 communicates with the first terminal of the driving circuit 11 , so that the control terminal of the driving circuit 11 communicates with the first terminal of the driving circuit 11 .
  • the first control circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first scanning line, the first electrode of the first transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the first transistor is electrically connected to the connecting the nodes electrically;
  • the first control transistor is an oxide thin film transistor.
  • the first transistor included in the control circuit is an oxide thin film transistor.
  • Oxide transistors have good hysteresis characteristics, low leakage current, and low mobility. Therefore, at least one embodiment of the present disclosure configures the first transistor as an oxide thin film transistor to achieve low leakage and ensure the stability of the potential of the control terminal of the driving circuit.
  • the compensation control circuit includes a second transistor
  • the control electrode of the second transistor is electrically connected to the second scanning line, the first electrode of the second transistor is electrically connected to the connection node, and the second electrode of the second transistor is electrically connected to the driving circuit. The first end is electrically connected.
  • the second transistor may be a low temperature polysilicon thin film transistor, but not limited thereto. During specific implementation, the second transistor may also be other types of transistors.
  • the first initialization circuit includes a third transistor
  • the control electrode of the third transistor is electrically connected to the initialization control line, the first electrode of the third transistor is electrically connected to the first initialization voltage line, and the second electrode of the third transistor is electrically connected to the connection node. connect.
  • the third transistor is a low temperature polysilicon thin film transistor.
  • the third transistor may also be other types of transistors.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a reset circuit 20;
  • the reset circuit 20 is electrically connected to the third scanning line S3, the reset voltage line DR and the second end of the driving circuit 11 respectively, for controlling the third scanning signal provided by the third scanning line S3, Write the reset voltage provided by the reset voltage line DR into the second terminal of the driving circuit 11 .
  • a reset circuit 20 is added. Under the control of the third scanning signal, the reset circuit 20 is non-luminous before the data voltage is written into the second terminal of the driving circuit 11. time period, the reset voltage is written into the second end of the drive circuit 11 to provide a bias voltage to the drive transistor in the drive circuit 11 (the gate potential of the drive transistor is also initialized to Vi1 at this time), so that the drive transistor remains in the reset state , to improve the hysteresis of the driving transistor, which is beneficial to the FFR (first frame response time) of the display screen.
  • FFR first frame response time
  • the hysteresis of the driving transistor will cause the characteristic response of the driving transistor to be sluggish, but in at least one embodiment of the present disclosure, before the data voltage is written, the gate-source voltage of the driving transistor is quickly reset, which is beneficial to the recovery speed of the driving transistor. , so the hysteresis phenomenon of the drive transistor will be improved, and the hysteresis recovery speed will be increased.
  • At least one embodiment of the pixel circuit shown in FIG. 47 of the present disclosure is in operation, during the non-light-emitting time period (the non-light-emitting time period may refer to the time period included in the display cycle except the light-emitting period) , before the data voltage is written into the second terminal of the driving circuit 11, the time for resetting the second terminal of the driving circuit 11 can be increased by increasing the duty cycle of the third scanning signal, so that the second terminal of the driving circuit 11 The reset effect of the potential of the terminal is better.
  • the reset voltage is a DC voltage signal to provide a fixed bias voltage for the driving transistor and improve hysteresis.
  • the reset voltage may be a high voltage, but not limited thereto.
  • a separate third scan signal generation module can be used to provide the third scan signal to the third scan line, which is beneficial to reset the potential of the second terminal of the driving circuit.
  • the reset voltage line and the first voltage line may be the same voltage line, which can reduce the number of signal lines used.
  • the voltage value of the reset voltage is greater than the voltage value of the first initialization voltage; the first voltage line is used to provide a first voltage signal (the first voltage line may be a high voltage line).
  • the voltage value of the first voltage signal may be greater than 0V and less than or equal to 5V, for example, the voltage value of the first voltage signal may be 4.6V, but not limited thereto.
  • the first initialization voltage may be a DC voltage, and the voltage value of the first initialization voltage may be greater than or equal to -7V and less than or equal to 0V; for example, the voltage value of the first initialization voltage may be -6V, - 5V, -4V, -3V or -2V, but not limited thereto.
  • the threshold voltage Vth of the driving transistor in the driving circuit may be greater than or equal to -5V and less than or equal to -2V, preferably, Vth may be greater than or equal to -4V and less than or equal to -2.5V ;
  • Vth can be -4V, -3.5V, -3V or -2.5V, but not limited thereto.
  • the absolute value of the voltage value of the reset voltage may be greater than 1.5 times the absolute value of the threshold voltage, so as to ensure that the bias effect can be quickly achieved in a relatively short period of time.
  • the absolute value of the voltage value of the reset voltage may be greater than 2 times, 2.5 times or 3 times the absolute value of the threshold voltage, but not limited thereto.
  • the reset circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the third scanning line, the first electrode of the fourth transistor is electrically connected to the reset voltage line, and the second electrode of the fourth transistor is electrically connected to the driving circuit.
  • the second terminal is electrically connected.
  • the fourth transistor may be a low temperature polysilicon thin film transistor, but not limited thereto.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a light emitting element 30 , a light emitting control circuit 31 and a second initialization circuit 32 ;
  • the light emission control circuit 31 is electrically connected to the light emission control line E1, the first voltage line V1, the second end of the driving circuit 11, and the first end of the driving circuit 11 to the first pole of the light emitting element 30. for controlling the communication between the first voltage line V1 and the second end of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control line E1, and controlling the second terminal of the driving circuit 11 One end communicates with the first pole of the light emitting element 30;
  • the second initialization circuit 32 is electrically connected to the fourth scanning line S4, the second initialization voltage line and the first electrode of the light-emitting element 30, and is used for the fourth scanning signal provided on the fourth scanning line S4. Under control, write the second initialization voltage Vi2 provided by the second initialization voltage line into the first pole of the light emitting element 30;
  • the second pole of the light emitting element 30 is electrically connected to the second voltage line V2.
  • the first voltage line V1 may be a high voltage line
  • the second voltage line V2 may be a low voltage line, but not limited thereto;
  • the light-emitting element 30 can be an OLED (organic light-emitting diode), the first pole of the light-emitting element 30 can be the anode of the OLED, and the second pole of the light-emitting element 30 can be the cathode of the OLED, but not limited thereto .
  • OLED organic light-emitting diode
  • the fourth scanning signal can be provided to the fourth scanning line through a separate fourth scanning signal generation module, which is beneficial to switching frequency switching under low-frequency flickering degrees of freedom (the switching frequency is the switching frequency of the transistors included in the second initialization circuit 32).
  • the switching frequency is the switching frequency of the transistors included in the second initialization circuit 32.
  • the third scan signal and the fourth scan signal may be the same scan signal, and the third scan signal generating module and the fourth scan signal generating module may be the same mods, but not limited to.
  • the first scan signal and the light-emitting control signal may be the same signal, but considering that when PWM (pulse width modulation) controls the light-emitting function EM may provide a high-voltage signal during the lighting process, then the first scanning signal is provided for the first scanning line through a separate first scanning signal generation module, and the lighting control line is provided for the lighting control line through the lighting control signal generation module. control signal.
  • PWM pulse width modulation
  • a voltage value of the reset voltage when the reset voltage line is the first voltage line, a voltage value of the reset voltage may be greater than a voltage value of the second initialization voltage.
  • the voltage value of the second initialization voltage may be greater than or equal to -7V and less than or equal to 0V.
  • the voltage value of the second initialization voltage may be -6V, -5V, -4V, -3V or -2V.
  • the light emission control circuit includes a fifth transistor and a sixth transistor;
  • the control electrode of the fifth transistor is electrically connected to the light emission control line, the first electrode of the fifth transistor is electrically connected to the first voltage line, and the second electrode of the fifth transistor is electrically connected to the driving circuit.
  • the second terminal is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the The first pole of the light emitting element is electrically connected;
  • the second initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the fourth scan line, the first electrode of the seventh transistor is electrically connected to the second initialization voltage line, and the second electrode of the seventh transistor is electrically connected to the The first poles of the light emitting elements are electrically connected.
  • the seventh transistor may be an oxide thin film transistor.
  • the seventh transistor can be set as an oxide thin film transistor, which can reduce leakage and ensure the stability of the potential of the first electrode of the light emitting element.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a data writing circuit 41 and an energy storage circuit 42;
  • the data writing circuit 41 is respectively electrically connected to the second scanning line S2, the data line D1 and the second end of the driving circuit 11, and is used for controlling the second scanning signal provided by the second scanning line S2. , writing the data voltage on the data line D1 into the second terminal of the driving circuit 11;
  • the energy storage circuit 42 is electrically connected to the control terminal of the driving circuit 11 for storing electric energy.
  • the display cycle also includes a light-emitting phase set after the data writing phase;
  • the second initialization circuit 32 writes the second initialization voltage Vi2 provided by the second initialization voltage line into the light-emitting element 30 under the control of the fourth scanning signal provided by the fourth scanning line S4. first pole;
  • the data writing circuit 41 writes the data voltage Vdata on the data line D1 into the second terminal of the driving circuit 11 under the control of the second scanning signal;
  • the driving circuit 11 controls the communication between its first end and the second end of the driving circuit 11, so as to charge the energy storage circuit 42 through the data voltage Vdata, and change the control of the driving circuit 11. terminal until the potential of the control terminal of the drive circuit 11 becomes Vdata+Vth, where Vth is the threshold voltage of the drive transistor comprising 11 in the drive circuit;
  • the light-emitting control circuit 31 controls the connection between the first voltage line V1 and the second end of the driving circuit 11 under the control of the light-emitting control signal, and controls the connection between the first end of the driving circuit 11 and the second end of the driving circuit 11.
  • the first poles of the light emitting element 30 are connected to each other, and the driving circuit 11 drives the light emitting element 30 to emit light.
  • the data writing circuit includes an eighth transistor, and the energy storage circuit includes a storage capacitor;
  • the control electrode of the eighth transistor is electrically connected to the second scanning line, the first electrode of the eighth transistor is electrically connected to the data line, and the second electrode of the eighth transistor is electrically connected to the driving circuit. the second terminal is electrically connected;
  • the first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the storage capacitor is electrically connected to the first voltage line.
  • the driving circuit may include a driving transistor
  • the driving transistor is a single-gate transistor, the gate of the driving transistor is electrically connected to the control terminal of the driving circuit, the first pole of the driving transistor is electrically connected to the first terminal of the driving circuit, and the driving transistor is electrically connected to the first terminal of the driving circuit.
  • the second pole of the transistor is electrically connected to the second terminal of the drive circuit; or,
  • the drive transistor is a double-gate transistor, the first gate of the drive transistor is electrically connected to the control terminal of the drive circuit, the second gate of the drive transistor is electrically connected to the first voltage line, and the drive transistor The first pole of the drive transistor is electrically connected to the first end of the drive circuit, and the second pole of the drive transistor is electrically connected to the second end of the drive circuit; the first gate is a top gate, and the second gate Very bottom grill.
  • the driving transistor may be a single-gate transistor or a double-gate transistor.
  • the driving transistor is a double-gate transistor
  • the first gate of the driving transistor is electrically connected to the control terminal of the driving circuit
  • the second gate of the driving transistor is electrically connected to the first voltage line
  • the first The gate is a top gate
  • the second gate is a bottom gate, so that the substrate of the driving transistor is biased to improve the hysteresis of the driving transistor.
  • the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 electrically connected to the connection node N0;
  • the compensation control circuit 13 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second scanning line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, the source of the second transistor T2 is electrically connected to the The drain of the drive transistor T0 is electrically connected;
  • the first initialization circuit 14 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the initialization control line R1.
  • the node N0 is electrically connected; the first initialization voltage line is used to provide a first initialization voltage Vi1;
  • the reset circuit 20 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the third scanning line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the third scanning line S3.
  • the source electrode of the driving transistor T0 is electrically connected;
  • the light emission control circuit includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the driving transistor T0.
  • the source is electrically connected; the high voltage line is used to provide a high voltage signal VDD;
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1
  • the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0
  • the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0.
  • the anode of the organic light emitting diode O1 is electrically connected;
  • the second initialization circuit 32 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the second initialization voltage line.
  • the anode of the organic light emitting diode O1 is electrically connected; the second initial voltage line is used to provide a second initial voltage Vi2;
  • the data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;
  • the gate of the eighth transistor T8 is electrically connected to the second scanning line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the The source of the drive transistor T0 is electrically connected;
  • the first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C is electrically connected to the high voltage line;
  • the cathode of O1 is electrically connected to a low voltage line for providing a low voltage VSS.
  • the one labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0;
  • the one labeled N2 is the second node, and the one labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.
  • the first voltage line is a high voltage line
  • the second voltage line is a low voltage line
  • T1 may be an oxide thin film transistor
  • T0, T2, T3, T4, T5, T6, T7, and T8 may all be low-temperature polysilicon thin film transistors
  • T1 may be an n-type transistor.
  • Transistors, T0, T2, T3, T4, T5, T6, T7 and T8 are p-type transistors, and T0 is a single-gate transistor, but not limited thereto.
  • N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce the leakage of N1 and stabilize the potential of the gate of T0. sex.
  • T1 is an oxide thin film transistor, which can reduce leakage and ensure the stability of the potential of N1 .
  • T2 and T3 can be single-gate transistors to save space.
  • the initialization control signal provided by the initialization control line R1 and the second scan signal provided by the second scan line may both be generated by the second scan signal module provided.
  • each transistor included in the pixel circuit may be disposed on a substrate, and the orthographic projection of the conductive pattern on the substrate is consistent with the fourth scanning line S4 on the substrate.
  • the overlapping area between the orthographic projections is as small as possible, and the overlapping area between the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the initialization control line R1 on the substrate is as small as possible, so as to reduce parasitic capacitance .
  • the capacitance between the conductive pattern and the fourth scan line S4 is less than 0.3Cz
  • the capacitance between the conductive pattern for electrically connecting the source of T0 and the source of T5 and the initialization control line R1 is less than 0.3Cz Cz; wherein, Cz is the capacitance value of the storage capacitor C.
  • the conductive pattern includes a source of T0, a source of T5, and a connecting conductive pattern for electrically connecting the source of T0 and the source of T5.
  • the display cycle includes an initialization phase t1, a data writing phase t2, and a lighting phase t3 which are set successively;
  • E1 provides a high voltage signal
  • S1 provides a high voltage signal
  • T1 opens
  • R1 provides a low voltage signal
  • S2 provides a high voltage signal
  • T2 opens
  • T3 closes
  • Vi1 is written into N1, so that in the data writing phase
  • T0 is turned on
  • S3 and S4 provide low-voltage signals
  • T7 is turned on
  • T4 is turned on to write the reset voltage provided by DR into N2, and write Vi2 into the anode of O1, so that O1 does not emit light, and clears O1 Anode residual charge
  • E1 provides a high voltage signal
  • S1 provides a high voltage signal
  • T1 is turned on
  • R1 provides a high voltage signal
  • S2 provides a high voltage signal
  • T2 is turned on
  • T3 is turned off
  • T8 is turned on
  • S3 and S4 provide a high voltage signal
  • T7 and T4 are turned off, and the data voltage Vdata on the data line D1 is written into N2;
  • T0 is turned on to charge C through Vdata through the turned on T8, T0, T2 and T1 to increase the potential of N1 until T0 is turned off.
  • the potential of N1 is Vdata+ Vth, Vth is the threshold voltage of T0;
  • E1 provides a low voltage signal
  • R1 provides a high voltage signal
  • S1 provides a low voltage signal
  • S2, S3 and S4 provide a high voltage signal
  • T1, T2, T3, T4, T7 and T8 are turned off
  • T5 and T6 Turn on
  • T0 is turned on to drive O1 to emit light.
  • T4 is added to provide a high voltage for N2, and the potential of N2 is initialized during the non-light-emitting period, which is beneficial to improve the stability of T0; and T7 is provided to provide Initializing the potential of the anode of O1 is beneficial to the degree of freedom of switching frequency switching under low-frequency flickering.
  • the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 electrically connected to the connection node N0;
  • the compensation control circuit 13 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second scanning line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, the source of the second transistor T2 is electrically connected to the The drain of the drive transistor T0 is electrically connected;
  • the first initialization circuit 14 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the initialization control line R1.
  • the node N0 is electrically connected; the first initialization voltage line is used to provide a first initialization voltage Vi1;
  • the reset circuit 20 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the third scanning line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the third scanning line S3.
  • the source electrode of the driving transistor T0 is electrically connected;
  • the light emission control circuit includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the driving transistor T0.
  • the source is electrically connected; the high voltage line is used to provide a high voltage signal VDD;
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1
  • the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0
  • the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0.
  • the anode of the organic light emitting diode O1 is electrically connected;
  • the second initialization circuit 32 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the second initialization voltage line.
  • the anode of the organic light emitting diode O1 is electrically connected; the second initial voltage line is used to provide a second initial voltage Vi2;
  • the data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;
  • the gate of the eighth transistor T8 is electrically connected to the second scanning line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the The source of the drive transistor T0 is electrically connected;
  • the first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C is electrically connected to the high voltage line;
  • the cathode of O1 is electrically connected to a low voltage line for providing a low voltage VSS.
  • the first node labeled N1 is electrically connected to the gate of T0;
  • the one labeled N2 is the second node, and the one labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.
  • the first voltage line is a high voltage line
  • the second voltage line is a low voltage line
  • T1 and T7 may be oxide thin film transistors, T0, T2, T3, T4, T5, T6 and T8 may all be low temperature polysilicon thin film transistors, T1 and T7 are N-type transistors, T0, T2, T3, T4, T5, T6 and T8 are p-type transistors, and T0 is a single-gate transistor, but not limited thereto.
  • T7 is an oxide thin film transistor.
  • N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce the leakage of N1 and stabilize the potential of the gate of T0. sex.
  • T1 and T7 are oxide thin film transistors to reduce leakage, ensure the stability of the potential of N1, and ensure the stability of the potential of the anode of O1.
  • the fourth scanning signal can be provided to the fourth scanning line through a separate fourth scanning signal generation module, which facilitates the freedom of switching frequency switching under low-frequency flickering.
  • the switching frequency is the switching frequency of the transistors included in the second initialization circuit 32.
  • the fourth scanning line may be the light-emitting control line, so that in the low-frequency refresh stage, only the light-emitting control signal provided by the light-emitting control line needs to be periodically controlled, that is, the light-emitting elements can be periodically reset/brightness adjusted , so as to achieve brightness balance.
  • the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 electrically connected to the connection node N0;
  • the compensation control circuit 13 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second scanning line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, the source of the second transistor T2 is electrically connected to the The drain of the drive transistor T0 is electrically connected;
  • the first initialization circuit 14 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the initialization control line R1.
  • the node N0 is electrically connected; the first initialization voltage line is used to provide a first initialization voltage Vi1;
  • the reset circuit 20 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the third scanning line S3, the drain of the fourth transistor T4 is electrically connected to the high voltage line, and the source of the fourth transistor T4 is electrically connected to the driving transistor
  • the source of T0 is electrically connected; the high voltage line is used to provide a high voltage signal VDD;
  • the light emission control circuit includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the driving transistor T0.
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1
  • the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0
  • the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0.
  • the anode of the organic light emitting diode O1 is electrically connected;
  • the second initialization circuit 32 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the second initialization voltage line.
  • the anode of the organic light emitting diode O1 is electrically connected; the second initial voltage line is used to provide a second initial voltage Vi2;
  • the data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;
  • the gate of the eighth transistor T8 is electrically connected to the second scanning line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the The source of the drive transistor T0 is electrically connected;
  • the first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and the second end of the storage capacitor C is electrically connected to the high voltage line;
  • the cathode of O1 is electrically connected to a low voltage line for providing a low voltage VSS.
  • the first node labeled N1 is electrically connected to the gate of T0;
  • the one labeled N2 is the second node, and the one labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.
  • the first voltage line is a high voltage line
  • the second voltage line is a low voltage line
  • T1 may be an oxide thin film transistor
  • T0, T2, T3, T4, T5, T6, T7, and T8 may all be low-temperature polysilicon thin film transistors
  • T1 may be an n-type transistor.
  • Transistors, T0, T2, T3, T4, T5, T6, T7 and T8 are p-type transistors, and T0 is a single-gate transistor, but not limited thereto.
  • N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce the leakage of N1 and stabilize the potential of the gate of T0. sex;
  • T1 is an oxide thin film transistor, so as to reduce the leakage of N1 and stabilize the potential stability of the gate of T0.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 53 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 50 of the present disclosure is that the reset voltage line DR is the high voltage line, which can reduce the used The number of signal lines.
  • the voltage value of VDD may be 4.6V, the voltage value of VDD is greater than the voltage value of Vi1, and the voltage value of VDD is greater than the voltage value of Vi2.
  • T7 can also be replaced by an oxide thin film transistor, and T0 can also be replaced by a double-gate transistor, but not limited thereto.
  • the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, the drain of the first transistor T1 is electrically connected to the first gate of the driving transistor T0, and the first transistor T1 The source is electrically connected to the connection node N0;
  • the compensation control circuit 13 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second scanning line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, the source of the second transistor T2 is electrically connected to the The drain of the drive transistor T0 is electrically connected;
  • the first initialization circuit 14 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the initialization control line R1.
  • the node N0 is electrically connected; the first initialization voltage line is used to provide a first initialization voltage Vi1;
  • the reset circuit 20 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the third scanning line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the third scanning line S3.
  • the source electrode of the driving transistor T0 is electrically connected;
  • the light emission control circuit includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the driving transistor T0.
  • the source is electrically connected; the high voltage line is used to provide a high voltage signal VDD;
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1
  • the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0
  • the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0.
  • the anode of the organic light emitting diode O1 is electrically connected;
  • the second initialization circuit 32 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the second initialization voltage line.
  • the anode of the organic light emitting diode O1 is electrically connected; the second initial voltage line is used to provide a second initial voltage Vi2;
  • the data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;
  • the gate of the eighth transistor T8 is electrically connected to the second scanning line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the The source of the drive transistor T0 is electrically connected;
  • the first end of the storage capacitor C is electrically connected to the first gate of the driving transistor T0, and the second end of the storage capacitor C is electrically connected to the high voltage line;
  • the second gate of the driving transistor T0 is electrically connected to the high voltage line
  • the cathode of O1 is electrically connected to a low voltage line for providing a low voltage VSS.
  • the first node labeled N1 is electrically connected to the gate of T0;
  • the one labeled N2 is the second node, and the one labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.
  • the first voltage line is a high voltage line
  • the second voltage line is a low voltage line
  • T1 may be an oxide thin film transistor
  • T0, T2, T3, T4, T5, T6, T7, and T8 may all be low-temperature polysilicon thin film transistors
  • T1 may be an n-type transistor.
  • Transistors, T0, T2, T3, T4, T5, T6, T7 and T8 are p-type transistors, and T0 is a double-gate transistor, but not limited thereto.
  • N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce the leakage of N1 and stabilize the potential of the gate of T0. sex.
  • T1 is an oxide thin film transistor, which can reduce leakage and ensure the stability of the potential of N1 .
  • T0 is a double-gate transistor
  • the first gate of T0 is a top gate
  • the second gate of T0 is a bottom gate
  • the second gate of T0 is connected to the high voltage
  • the wires are electrically connected to bias the substrate of T0, which is beneficial to improve the hysteresis of T0.
  • T0 is a double-gate transistor.
  • T7 may be replaced by an oxide thin film transistor, and DR may be a first voltage line, but not limited thereto.
  • the on-time of T4 can be increased by increasing the duty cycle of the third scanning signal, so that the effect of resetting the potential of N2 is better.
  • two adjacent rows of pixel circuits may be electrically connected to the same row of reset voltage lines.
  • the one labeled DRn is the reset voltage line of the nth row (n is a positive integer); and the two pixel circuits located in adjacent columns are mirrored to facilitate wiring.
  • two adjacent columns of pixel circuits can be electrically connected to the reset voltage line of the same column.
  • the one labeled DRm is the reset voltage line of the mth column (m is a positive integer); and the two pixel circuits located in adjacent columns are mirrored to facilitate wiring.
  • pixel circuits in two adjacent rows can be electrically connected to the reset voltage line in the same row
  • pixel circuits in two adjacent columns can be electrically connected to the reset voltage line in the same column
  • two pixel circuits in adjacent columns are mirrored.
  • Multiple reset voltage lines are arranged in grid form to facilitate wiring.
  • the one labeled DR11 is the reset voltage line for the first row
  • the one labeled DR12 is the reset voltage line for the second row
  • the one labeled DR21 is the reset voltage line for the first column
  • the one labeled DR22 is the reset voltage line for the second row.
  • the voltage line, labeled DR23 is the reset voltage line of the third column.
  • the one labeled DR11 is the reset voltage line of the first row
  • the one labeled DR12 is the reset voltage line of the second row
  • the one labeled DR13 is the reset voltage line of the third row
  • the one labeled DR14 is the reset voltage line of the fourth row.
  • the voltage lines marked DR21 are the reset voltage lines of the first column
  • the lines marked DR22 are the reset voltage lines of the second column.
  • the pixel circuits in the first row are electrically connected to the reset voltage line DR11 in the first row
  • the pixel circuits in the second row are electrically connected to the reset voltage line DR12 in the second row
  • the pixel circuits in the third row Both are electrically connected to the reset voltage line DR13 in the third row
  • the pixel circuit located in the fourth row is electrically connected to the reset voltage line DR14 in the fourth row;
  • reset voltage lines are provided, so that a plurality of reset voltage lines are arranged in a grid; moreover, a column of reset voltage lines can be provided every few columns of pixel circuits to save wiring space.
  • a vertically extending reset voltage line may be provided on one side of the red pixel circuit column.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display cycle includes an initialization phase and a data writing phase; the driving method includes:
  • the first control circuit controls the connection between the control terminal of the driving circuit and the connection node, and the first initialization circuit writes the first initialization voltage into the connection node under the control of the initialization control signal. node, so that the first initialization voltage is written into the control terminal of the driving circuit, so that the driving circuit can control the communication between its first terminal and the second terminal of the driving circuit when the data writing phase begins;
  • the first control circuit controls the connection between the control terminal of the driving circuit and the connection node
  • the compensation control circuit controls the connection between the connection node and the connection node under the control of the second scan signal.
  • the first terminals of the driving circuit are connected to each other, so that the control terminal of the driving circuit is connected to the first terminal of the driving circuit.
  • the first control circuit controls the connection between the control terminal of the driving circuit and the connection node, and the first initialization circuit writes the first initialization voltage into the connection node under the control of the initialization control signal
  • the compensation control circuit controls the connection between the connection node and the first end of the drive circuit under the control of the second scan signal
  • the first control circuit is directly electrically connected to the control end of the drive circuit
  • the first initialization circuit and The compensation control circuit is not directly electrically connected to the control terminal of the drive circuit, so as to reduce the leakage path of the first node (the node electrically connected to the control terminal of the drive circuit), so as to ensure the stability of the voltage of the first node during low-frequency operation It is beneficial to improve display quality, improve display uniformity, and reduce Flicker (flicker).
  • the reset circuit In the initialization phase, the reset circuit writes a reset voltage into the second terminal of the driving circuit under the control of the third scanning signal.
  • the pixel circuit may further include a light emitting element and a second initialization circuit; the driving method further includes:
  • the second initialization circuit writes the second initialization voltage into the first pole of the light emitting element, so as to control the light emitting element not to emit light.
  • the pixel circuit also includes a light emission control circuit, a data writing circuit and an energy storage circuit, and the display period includes a light emitting stage set after the data writing stage, and the driving method further includes:
  • the data writing circuit writes the data voltage Vdata on the data line into the second terminal of the driving circuit under the control of the second scanning signal;
  • the driving circuit controls the connection between its first terminal and the second terminal of the driving circuit, so as to charge the energy storage circuit with the data voltage Vdata, and change the potential of the control terminal of the driving circuit until The potential of the control terminal of the drive circuit becomes Vdata+Vth, where Vth is the threshold voltage of the drive transistor included in the drive circuit;
  • the light-emitting control circuit controls the connection between the first voltage line and the second end of the driving circuit under the control of the light-emitting control signal, and controls the connection between the first end of the driving circuit and the second end of the light-emitting element.
  • One pole is connected, and the driving circuit drives the light-emitting element to emit light.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the pixel circuit includes a reset circuit and a second initialization circuit, the reset circuit is electrically connected to the third scan line, and the second initialization circuit is electrically connected to the fourth scan line; the display device also Including a third scanning signal generating module and a fourth scanning signal generating module;
  • the third scan signal generation module is electrically connected to the third scan line, and is used to provide a third scan signal for the third scan line;
  • the fourth scan signal generation module is electrically connected to the fourth scan line, and is used to provide a fourth scan signal for the fourth scan line.
  • the third scan signal and the fourth scan signal may be the same scan signal, and the third scan signal generating module and the fourth scan signal generating module may be the same mod.
  • the display device includes a display panel, and the display panel includes a pixel module P0, and the pixel module P0 includes multiple rows and columns of the above-mentioned pixel circuits; the pixel The module P0 is set in the effective display area of the display panel;
  • the display panel also includes a lighting control signal generating module 70, a first scanning signal generating module 71, a first second scanning signal generating module 721, a second second scanning signal generating module 722, a third scanning signal generating module Signal generating module 73 and the fourth scanning signal generating module 74;
  • the luminescence control signal generation module 70 is used to provide a luminescence control signal
  • the first scan signal generation module 71 is used to provide a first scan signal
  • the signal generation module 722 is used to provide a second scan signal
  • the third scan signal generation module 73 is used to provide a third scan signal
  • the fourth scan signal generation module 74 is used to provide a fourth scan signal
  • the light emission control signal generating module 70, the first scanning signal generating module 71 and the first second scanning signal generating module 721 are arranged on the left side of the display panel,
  • the second second scan signal generation module 722 , the third scan signal generation module 73 and the fourth scan signal generation module 74 are arranged on the right side of the display panel.
  • the display device includes a display panel, and the display panel includes a pixel module P0, and the pixel module P0 includes multiple rows and columns of the above-mentioned pixel circuits; the pixel The module P0 is set in the effective display area of the display panel;
  • the display panel also includes a lighting control signal generating module 70, a first first scanning signal generating module 711, a second first scanning signal generating module 712, a first second scanning signal generating module 721, The second second scanning signal generating module 722 and the fourth scanning signal generating module 74;
  • the luminescence control signal generation module 70 is used to provide a luminescence control signal
  • the first scan signal generation module 711 and the second first scan signal generation module 712 are used to provide the first scan signal
  • the first second scan signal generation module 712 is used to provide the first scan signal.
  • the scan signal generation module 721 and the second second scan signal generation module 722 are used to provide the second scan signal;
  • the third scanning signal and the fourth scanning signal are the same scanning signal
  • the fourth scan signal generating module 74 is used to provide a third scan signal and a fourth scan signal
  • the lighting control signal generating module 70, the first first scanning signal generating module 711 and the first second scanning signal generating module 721 are arranged on the left side of the display panel,
  • the second first scan signal generating module 712 , the second second scan signal generating module 722 and the fourth scan signal generating module 74 are arranged on the right side of the display panel.
  • the one labeled Vi1 is the first initialization voltage
  • the one labeled Vi2 is the second initialization voltage
  • the one labeled VDD is the high voltage signal
  • the one labeled D1 is the data line
  • the one labeled DR is Reset voltage line.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIGS. 61-78 are explanatory drawings of another set of exemplary embodiments of the pixel driving circuit of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • the pixel circuit described in the embodiment of the present disclosure includes a driving circuit, a first initialization circuit and a reset circuit;
  • the first initialization circuit is electrically connected to the initialization control line, the first terminal of the driving circuit, and the first initial voltage terminal, and is used to control the initialization control signal provided by the initialization control line.
  • a first initial voltage provided by an initial voltage terminal is written into the first terminal of the drive circuit;
  • the reset circuit is electrically connected to the second scanning line and the reset voltage terminal, and the reset circuit is also electrically connected to the second terminal of the driving circuit or the first terminal of the driving circuit, for Under the control of the second scanning signal provided by the scanning line, control writing the reset voltage provided by the reset voltage terminal into the second terminal of the driving circuit or the first terminal of the driving circuit;
  • the driving circuit is used to control the communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of the control terminal.
  • At least one embodiment of the pixel circuit described in the present disclosure includes a first initialization circuit and a reset circuit. terminal, so as to cooperate with the compensation control circuit included in the pixel circuit to write the first initial voltage into the control terminal of the drive circuit;
  • the reset voltage is written into the second terminal of the driving circuit or the first terminal of the driving circuit to provide a bias voltage to the driving transistor in the driving circuit (the gate potential of the driving transistor is also initialized to Vi1 at this time),
  • the drive transistor is kept in a reset state to improve the hysteresis of the drive transistor, which is beneficial to the FFR (first frame response time) of the display screen.
  • the hysteresis of the driving transistor will cause the characteristic response of the driving transistor to be sluggish, but in at least one embodiment of the present disclosure, before the data voltage is written, the gate-source voltage of the driving transistor is quickly reset, which is beneficial to the recovery speed of the driving transistor. , so the hysteresis phenomenon of the drive transistor will be improved, and the hysteresis recovery speed will be increased.
  • a separate second scan signal generating module can be used to provide the second scan signal to the second scan line, which is beneficial to reset the potential of the second terminal of the driving circuit.
  • the reset voltage is a constant voltage to provide a fixed bias voltage for the driving transistor and improve hysteresis.
  • the first initial voltage is a low potential constant voltage, and the voltage value of the first initial voltage is greater than or equal to -6V and less than or equal to -2V; for example, the voltage value of the first initialization voltage may be -6V, -5V, -4V, -3V or -2V, but not limited to.
  • the reset voltage can be a high potential constant voltage, so as to ensure that the driving transistor in the driving circuit can be quickly turned on when the data writing phase begins; the voltage value of the reset voltage is greater than or equal to 4V but less than or equal to 10V; or,
  • the reset voltage may be a low potential constant voltage, and the voltage value of the reset voltage is greater than or equal to -6V and less than or equal to -2V.
  • the voltage value of the reset voltage may be, for example, 4V, 5V, 6V, 7V, 8V, 9V or 10V, but not limited thereto;
  • the voltage value of the reset voltage can be, for example, -6V, -5V, -4V, -3V or -2V, but not limited thereto.
  • the voltage value of the reset voltage is approximately the same as the voltage value of the first initial voltage, so that the reset voltage can be reset by the reset circuit at the same time.
  • Writing to the second terminal of the driving circuit when the first initial voltage is written into the first terminal of the driving circuit through the first initialization circuit, the driving transistor in the driving circuit will not fail.
  • the voltage value of the reset voltage is approximately the same as the voltage value of the first initial voltage, it means that the absolute value of the difference between the voltage value of the reset voltage and the voltage value of the first initial voltage is less than Predetermined voltage difference.
  • the predetermined voltage difference may be 0.1V or 0.05V, but not limited thereto.
  • the threshold voltage Vth of the driving transistor in the driving circuit may be greater than or equal to -5V and less than or equal to -2V, preferably, Vth may be greater than or equal to -4V and less than or equal to -2.5V ;
  • Vth can be -4V, -3.5V, -3V or -2.5V, but not limited thereto.
  • the driving circuit includes a driving transistor, and the absolute value of the voltage value of the reset voltage is greater than 1.5 times the absolute value of the threshold voltage, so as to ensure that the bias effect can be quickly achieved in a short time.
  • the threshold voltage is the threshold voltage of the driving transistor.
  • the absolute value of the voltage value of the reset voltage may be greater than 2 times, 2.5 times or 3 times the absolute value of the threshold voltage, but not limited thereto.
  • the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11, a first initialization circuit 13 and a reset circuit 20;
  • the first initialization circuit 13 is electrically connected to the initialization control line R1, the first terminal of the driving circuit 11, and the first initial voltage terminal, respectively, and is used for controlling the initialization control signal provided by the initialization control line R1, Writing the first initial voltage Vi1 provided by the first initial voltage terminal into the first terminal of the driving circuit 11;
  • the reset circuit 20 is electrically connected to the second scanning line S2 and the reset voltage terminal DR respectively, and the reset circuit 20 is also electrically connected to the second end of the driving circuit 11, for providing voltage on the second scanning line S2. Under the control of the second scanning signal of the control, the reset voltage provided by the reset voltage terminal DR is controlled to be written into the second terminal of the driving circuit 11;
  • the driving circuit 11 is used to control the communication between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 12 under the control of the potential of the control terminal.
  • the one labeled N1 is the first node, and the first node N1 is electrically connected to the control terminal of the driving circuit 11 .
  • the display cycle may include an initialization phase and a reset phase
  • the first initialization circuit 13 writes the first initial voltage Vi1 into the first terminal of the driving circuit 11 under the control of the initialization control signal;
  • the reset circuit 20 writes a reset voltage into the second terminal of the driving circuit 11 under the control of the second scanning signal.
  • the pixel circuit described in at least one embodiment of the present disclosure may include a driving circuit 11, a first initialization circuit 13 and a reset circuit 20;
  • the first initialization circuit 13 is electrically connected to the initialization control line R1, the first terminal of the driving circuit 11, and the first initial voltage terminal, respectively, and is used for controlling the initialization control signal provided by the initialization control line R1, Writing the first initial voltage Vi1 provided by the first initial voltage terminal into the first terminal of the driving circuit 11;
  • the reset circuit 20 is electrically connected to the second scanning line S2 and the reset voltage terminal DR respectively, and the reset circuit 20 is also electrically connected to the first end of the driving circuit 11, for providing the voltage on the second scanning line S2. Under the control of the second scan signal, the reset voltage provided by the reset voltage terminal DR is controlled to be written into the first terminal of the driving circuit 11 .
  • the display cycle may include an initialization phase and a reset phase
  • the first initialization circuit 13 writes the first initial voltage Vi1 into the first terminal of the driving circuit 11 under the control of the initialization control signal;
  • the reset circuit 20 writes a reset voltage into the first terminal of the driving circuit 11 under the control of the second scan signal.
  • the first initialization circuit includes a second transistor
  • the control electrode of the second transistor is electrically connected to the initialization control line, the first electrode of the second transistor is electrically connected to the first initial voltage terminal, and the second electrode of the second transistor is electrically connected to the drive The first ends of the circuit are electrically connected.
  • the second transistor may be a low temperature polysilicon thin film transistor, but not limited thereto.
  • the reset circuit includes a third transistor
  • the control electrode of the third transistor is electrically connected to the second scanning line, the first electrode of the third transistor is electrically connected to the reset voltage terminal, and the second electrode of the third transistor is electrically connected to the driving circuit The second end of the drive circuit or the first end of the drive circuit is electrically connected.
  • the pixel circuit may include a compensation control circuit
  • the compensation control circuit is respectively electrically connected to the first scanning line, the control terminal of the driving circuit and the first terminal of the driving circuit, and is used to control the first scanning signal provided by the first scanning line,
  • the control terminal for controlling the driving circuit communicates with the first terminal of the driving circuit.
  • the display cycle may include an initialization phase; in the initialization phase, the first initialization circuit writes the first initial voltage into the first drive circuit under the control of the initialization control signal. Under the control of the first scanning signal, the compensation control circuit controls the communication between the control terminal of the driving circuit and the first terminal of the driving circuit, so as to write the first initial voltage into the control terminal of the driving circuit, so as to This enables the driving circuit to control the communication between the first terminal of the driving circuit and the second terminal of the driving transistor under the control of the potential of the control terminal at the beginning of the data writing phase.
  • the control terminal of the driving circuit is only directly electrically connected to the compensation control circuit, and the first initialization circuit is directly electrically connected to the first terminal of the driving circuit, so as to pass the compensation
  • the control circuit and the first initialization circuit initialize the potential of the control terminal of the driving circuit, reduce the leakage path to the control terminal of the driving circuit, and ensure the voltage of the first node under the condition that the design complexity of the pixel circuit does not increase significantly. Stability is beneficial to improve display quality, improve display uniformity, and reduce Flicker (flicker).
  • the compensation control circuit includes a first transistor
  • the control electrode of the first transistor is electrically connected to the first scanning line, the first electrode of the first transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the first transistor is electrically connected to the the first end of the driving circuit is electrically connected;
  • the first transistor is an oxide thin film transistor.
  • the compensation control circuit may include a first transistor, and the first transistor is an oxide thin film transistor.
  • Oxide transistors have good hysteresis characteristics, low leakage current, and low mobility. Therefore, at least one embodiment of the present disclosure configures the first transistor as an oxide thin film transistor to achieve low leakage and ensure the stability of the potential of the control terminal of the driving circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit 12;
  • the compensation control circuit 12 is electrically connected to the first scanning line S1, the control terminal of the driving circuit 11, and the first terminal of the driving circuit 11, and is used for the first scanning provided on the first scanning line S1. Under the control of the signal, the control terminal of the driving circuit 11 is controlled to communicate with the first terminal of the driving circuit 11 .
  • the display cycle may include an initialization phase.
  • the compensation control circuit 12 controls the control terminal of the driving circuit 11 under the control of the first scanning signal. It communicates with the first end of the driving circuit 11 .
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit 12;
  • the compensation control circuit 12 is electrically connected to the first scanning line S1, the control terminal of the driving circuit 11, and the first terminal of the driving circuit 11, and is used for the first scanning provided on the first scanning line S1. Under the control of the signal, the control terminal of the driving circuit 11 is controlled to communicate with the first terminal of the driving circuit 11 .
  • the display cycle may include an initialization phase.
  • the compensation control circuit 12 controls the control terminal of the driving circuit 11 under the control of the first scanning signal. It communicates with the first end of the driving circuit 11 .
  • the pixel circuit may further include a light-emitting element, an energy storage circuit, a second initialization circuit, a data writing circuit, and a light-emitting control circuit;
  • the energy storage circuit is electrically connected to the control terminal of the drive circuit for storing electric energy
  • the second initialization circuit is electrically connected to the third scanning line, the second initial voltage terminal, and the first electrode of the light-emitting element, and is used to control the third scanning signal provided by the third scanning line.
  • the second initial voltage provided by the second initial voltage terminal is written into the first electrode of the light emitting element;
  • the data writing circuit is electrically connected to the fourth scanning line, the data line and the second end of the driving circuit, and is used to write the data to The data voltage provided by the line is written into the second end of the driving circuit;
  • the lighting control circuit is electrically connected to the lighting control line, the first voltage terminal, the second terminal of the driving circuit, the first terminal of the driving circuit and the first pole of the light emitting element, for Under the control of the light emission control signal provided by the light emission control line, control the communication between the first voltage end and the second end of the driving circuit, and control the connection between the first end of the driving circuit and the first pole of the light emitting element. connection between
  • the second pole of the light emitting element is electrically connected to the second voltage terminal.
  • the pixel circuit may further include a light-emitting element, an energy storage circuit, a second initialization circuit, a data writing circuit, and a light-emitting control circuit, and the second initialization circuit initializes the first pole of the light-emitting element , the data writing circuit writes the data voltage into the second end of the drive circuit, and the light emission control circuit controls the communication between the first voltage end and the second end of the drive circuit under the control of the light emission control signal, and controls the The first end of the driving circuit is connected to the first pole of the light emitting element.
  • the light-emitting element may be an organic light-emitting diode
  • the first pole of the light-emitting element may be the anode of the organic light-emitting diode
  • the second pole of the light-emitting element may be the cathode of the organic light-emitting diode
  • the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal;
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a light emitting element 40, an energy storage circuit 41, a second initialization circuit 42. Data writing circuit 43 and lighting control circuit 44;
  • the energy storage circuit 41 is electrically connected to the control terminal of the drive circuit 11 for storing electric energy
  • the second initialization circuit 42 is electrically connected to the third scanning line S3, the second initial voltage terminal and the first electrode of the light-emitting element 40, and is used for the third scanning signal provided on the third scanning line S3. Under control, write the second initial voltage Vi2 provided by the second initial voltage terminal into the first pole of the light emitting element 40;
  • the data writing circuit 43 is electrically connected to the fourth scanning line S4, the data line D1 and the second end of the driving circuit 11 respectively, for controlling the fourth scanning signal provided by the fourth scanning line S4 , writing the data voltage provided by the data line D1 into the second terminal of the driving circuit 11;
  • the light emission control circuit 44 is electrically connected to the first voltage terminal V1 of the light emission control line E1, the second end of the driving circuit 11, the first end of the driving circuit 11 and the first pole of the light emitting element 40, Under the control of the light emission control signal provided by the light emission control line E1, control the connection between the first voltage terminal V1 and the second end of the driving circuit 11, and control the first end of the driving circuit 11 communicate with the first pole of the light emitting element 40;
  • the second pole of the light emitting element 40 is electrically connected to the second voltage terminal V2.
  • the display cycle also includes a data writing phase and a light emitting phase set after the initialization phase;
  • the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the second terminal of the driving circuit 11 under the control of the fourth scanning signal; Under the control of the scanning signal, the control terminal of the driving circuit 11 is connected to the first terminal of the driving circuit 11;
  • the driving circuit 11 Under the control of its control terminal, conducts the connection between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11, so as to pass
  • the data voltage Vdata charges the energy storage circuit 41, thereby changing the potential of the control terminal of the driving circuit 11 until the potential of the control terminal of the driving circuit 11 becomes Vdata+Vth, and Vth is the driving transistor included in the driving circuit 11. threshold voltage;
  • the light-emitting control circuit 44 controls the connection between the first voltage terminal V1 and the second end of the driving circuit 11 under the control of the light-emitting control signal, and controls the connection between the first end of the driving circuit 11 and the light-emitting element 40.
  • the first poles of the two poles are connected, and the driving circuit 11 drives the light emitting element 40 to emit light.
  • the reset phase may be set between the initialization phase and the data writing phase, but not limited thereto.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a light emitting element 40, an energy storage circuit 41, a second initialization circuit 42. Data writing circuit 43 and lighting control circuit 44;
  • the energy storage circuit 41 is electrically connected to the control terminal of the drive circuit 11 for storing electric energy
  • the second initialization circuit 42 is electrically connected to the third scanning line S3, the second initial voltage terminal and the first electrode of the light-emitting element 40, and is used for the third scanning signal provided on the third scanning line S3. Under control, write the second initial voltage Vi2 provided by the second initial voltage terminal into the first pole of the light emitting element 40;
  • the data writing circuit 43 is electrically connected to the fourth scanning line S4, the data line D1 and the second end of the driving circuit 11 respectively, for controlling the fourth scanning signal provided by the fourth scanning line S4 , writing the data voltage provided by the data line D1 into the second terminal of the driving circuit 11;
  • the light emission control circuit 44 is electrically connected to the light emission control line E1, the first voltage terminal V1, the second end of the driving circuit 11, the first end of the driving circuit 11, and the first pole of the light emitting element 40, respectively. , for controlling the communication between the first voltage terminal V1 and the second terminal of the driving circuit 11 under the control of the lighting control signal provided by the lighting control line E1, and controlling the first voltage of the driving circuit 11.
  • the end communicates with the first pole of the light emitting element 40;
  • the second pole of the light emitting element 40 is electrically connected to the second voltage terminal V2.
  • the display cycle also includes a data writing phase and a light emitting phase set after the initialization phase;
  • the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the second terminal of the driving circuit 11 under the control of the fourth scanning signal; Under the control of the scanning signal, the control terminal of the driving circuit 11 is connected to the first terminal of the driving circuit 11;
  • the driving circuit 11 Under the control of its control terminal, conducts the connection between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11, so as to pass
  • the data voltage Vdata charges the energy storage circuit 41, thereby changing the potential of the control terminal of the driving circuit 11 until the potential of the control terminal of the driving circuit 11 becomes Vdata+Vth, and Vth is the driving transistor included in the driving circuit 11. threshold voltage;
  • the light-emitting control circuit 44 controls the connection between the first voltage terminal V1 and the second end of the driving circuit 11 under the control of the light-emitting control signal, and controls the connection between the first end of the driving circuit 11 and the light-emitting element 40.
  • the first poles of the two poles are connected, and the driving circuit 11 drives the light emitting element 40 to emit light.
  • the pixel circuit described in at least one embodiment of the present disclosure may include a drive circuit 11, a compensation control circuit 12, a first initialization circuit 13, a light emitting element 40, an energy storage circuit 41, a second initialization circuit 42, a data Write circuit 43 and light emission control circuit 44;
  • the compensation control circuit 12 is electrically connected to the first scanning line S1, the control terminal of the driving circuit 11, and the first terminal of the driving circuit 11, and is used for the first scanning provided on the first scanning line S1. Under the control of the signal, control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11;
  • the first initialization circuit 13 is electrically connected to the initialization control line R1, the first terminal of the driving circuit 11, and the first initial voltage terminal, respectively, and is used for controlling the initialization control signal provided by the initialization control line R1, Writing the first initial voltage Vi1 provided by the first initial voltage terminal into the first terminal of the driving circuit 11;
  • the drive circuit 11 is used to control the communication between the first terminal of the drive circuit 11 and the second terminal of the drive circuit 12 under the control of the potential of the control terminal;
  • the energy storage circuit 41 is electrically connected to the control terminal of the drive circuit 11 for storing electric energy
  • the second initialization circuit 42 is electrically connected to the third scanning line S3, the second initial voltage terminal and the first electrode of the light-emitting element 40, and is used for the third scanning signal provided on the third scanning line S3. Under control, write the second initial voltage Vi2 provided by the second initial voltage terminal into the first pole of the light emitting element 40;
  • the data writing circuit 43 is electrically connected to the fourth scanning line S4, the data line D1 and the second end of the driving circuit 11 respectively, for controlling the fourth scanning signal provided by the fourth scanning line S4 , writing the data voltage provided by the data line D1 into the second terminal of the driving circuit 11;
  • the light emission control circuit 44 is electrically connected to the light emission control line E1, the first voltage terminal V1, the second end of the driving circuit 11, the first end of the driving circuit 11, and the first pole of the light emitting element 40, respectively. , for controlling the communication between the first voltage terminal V1 and the second terminal of the driving circuit 11 under the control of the lighting control signal provided by the lighting control line E1, and controlling the first voltage of the driving circuit 11.
  • the end communicates with the first pole of the light emitting element 40;
  • the second pole of the light emitting element 40 is electrically connected to the second voltage terminal V2.
  • the display cycle includes an initialization phase, a data writing phase, and a light-emitting phase that are set successively;
  • the first initialization circuit 13 writes the first initial voltage Vi1 into the first terminal of the driving circuit 11 under the control of the initialization control signal, and the compensation control circuit 12 controls the driving circuit 11 under the control of the first scanning signal.
  • the control end of the drive circuit 11 is communicated with the first end of the drive circuit 11, so as to write the first initial voltage Vi1 into the control end of the drive circuit 11, so that when the data writing phase begins, the drive circuit 11 Under the control of the potential of the control terminal, the communication between the first terminal of the driving circuit 11 and the second terminal of the driving transistor 11 can be controlled;
  • the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the second terminal of the driving circuit 11 under the control of the fourth scanning signal; Under the control of the scanning signal, the control terminal of the driving circuit 11 is connected to the first terminal of the driving circuit 11;
  • the driving circuit 11 Under the control of its control terminal, conducts the connection between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11, so as to pass
  • the data voltage Vdata charges the energy storage circuit 41, thereby changing the potential of the control terminal of the driving circuit 11 until the potential of the control terminal of the driving circuit 11 becomes Vdata+Vth, and Vth is the driving transistor included in the driving circuit 11. threshold voltage;
  • the light-emitting control circuit 44 controls the connection between the first voltage terminal V1 and the second end of the driving circuit 11 under the control of the light-emitting control signal, and controls the connection between the first end of the driving circuit 11 and the light-emitting element 40.
  • the first poles of the two poles are connected, and the driving circuit 11 drives the light emitting element 40 to emit light.
  • a separate third scanning signal generation module can be used to provide the third scanning signal to the third scanning line S3, which is beneficial to low-frequency flickering.
  • the degree of freedom of switching the switching frequency is the switching frequency of the transistors included in the second initialization circuit, but not limited thereto.
  • the third scanning signal and the fourth scanning signal may also be the same scanning signal.
  • the second scan signal and the third scan signal may be the same scan signal, and the second scan signal generation module and the third scan signal generation module may be the same mods, but not limited to.
  • the second scan signal may also be a different scan signal from the third scan signal.
  • At least one embodiment of the pixel circuit shown in FIG. 65 , FIG. 66 , and FIG. 67 of the present disclosure is in operation.
  • the circuit 42 writes the second initial voltage Vi2 provided by the second initial voltage terminal into the first electrode of the light emitting element 40, so as to control the The light emitting element 40 does not emit light, and the charge remaining on the first electrode of the light emitting element 40 is removed.
  • the time interval between the initialization phase and the data writing phase is greater than a predetermined time interval, so as to improve the hysteresis of the driving transistor by initializing the gate potential of the driving transistor in advance, Reduce the high and low frequency Flicker (flicker) of the pixel circuit.
  • the predetermined time interval may be selected according to actual conditions.
  • the initialization control signal provided by the initialization control line R1 and the fourth scanning signal can be generated by the same fourth scanning signal generating module
  • the fourth scanning signal may be an Nth-level fourth scanning signal generated by the fourth scanning signal generation module
  • the initialization control signal may be an N-Mth-level fourth scanning signal generated by the fourth scanning signal generation module.
  • the scanning signal is used to initialize the potential of the gate of the driving transistor in advance; N is a positive integer, and M can be a positive integer greater than 6, for example, M can be 14, but not limited thereto.
  • the data writing circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the fourth scanning line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second electrode of the driving circuit. Terminal connection;
  • the light emission control circuit includes a fifth transistor and a sixth transistor
  • the control electrode of the fifth transistor is electrically connected to the light-emitting control line, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the driving circuit.
  • the second terminal is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the The first pole of the light emitting element is electrically connected;
  • the second initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the third scanning line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the The first pole of the light emitting element is electrically connected;
  • the drive circuit includes a drive transistor; the control pole of the drive transistor is electrically connected to the control terminal of the drive circuit, the first pole of the drive transistor is electrically connected to the first end of the drive circuit, and the drive circuit The second pole of the drive circuit is electrically connected to the second end;
  • the energy storage circuit includes a storage capacitor; the first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the storage capacitor is connected to the first voltage terminal.
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit 12 includes a first transistor T1; the driving circuit 11 Including drive transistor T0;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 electrically connected to the drain of the driving transistor T1;
  • the first initialization circuit 13 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initial voltage terminal, and the source of the second transistor T2 is electrically connected to the The drain of the driving transistor T0 is electrically connected; the first initial voltage terminal is used to provide a first initial voltage Vi1;
  • the reset circuit 20 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the second scan line S2, the drain of the third transistor T3 is electrically connected to the reset voltage terminal DR, and the source of the third transistor T3 is electrically connected to the reset voltage terminal DR.
  • the source electrode of the driving transistor T0 is electrically connected;
  • the data writing circuit 43 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the fourth scanning line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the driving transistor The source electrical connection of T0;
  • the light emission control circuit includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal, and the source of the fifth transistor T5 is electrically connected to the driving transistor T0.
  • the source is electrically connected; the high voltage terminal is used to provide a high voltage signal VDD;
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0.
  • the anode of the organic light emitting diode O1 is electrically connected; the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide a low voltage signal VSS;
  • the second initialization circuit 42 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the third scanning line S3, the drain of the seventh transistor T7 is electrically connected to the second initial voltage terminal, and the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal.
  • the anode of the organic light emitting diode O1 is electrically connected; the second initial voltage terminal is used to provide a second initial voltage Vi2;
  • the energy storage circuit 41 includes a storage capacitor C; a first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is connected to the high voltage end.
  • T1 is an oxide thin film transistor
  • T2, T3, T4, T5, T6 and T7 are low temperature polysilicon thin film transistors
  • T1 is an n-type transistor
  • T2, T3, T4 , T5, T6 and T7 are p-type transistors.
  • N1 is the first node electrically connected to the gate of T0
  • N2 is the second node electrically connected to the source of T0
  • N3 is the drain of T0 electrically connected to the third node.
  • the initialization control signal and the fourth scan signal can be provided by the same fourth scan signal generating module.
  • the reset phase and the initialization phase are different phases to avoid the gate-source short circuit of T0; when the reset voltage provided by DR is a low voltage, the reset phase and the initialization phase can be the same stage.
  • the display cycle may include an initialization phase t1 and a reset phase t2 set successively. , data writing phase t3 and light emitting phase t4;
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • S4 provides a high voltage signal
  • S1 provides a high voltage signal
  • both S2 and S3 provide a high voltage signal
  • T1 and T2 are turned on to write Vi1 into N1, Initializing the potential of the gate of T0, so that T0 can be turned on when the data writing phase t3 starts;
  • E1 provides a high voltage signal
  • R1 provides a high voltage signal
  • S4 provides a high voltage signal
  • S1 provides a low voltage signal
  • both S2 and S3 provide a low voltage signal
  • T3 and T7 are turned on to pass through the high voltage provided by DR
  • E1 provides a high voltage signal
  • R1 provides a high voltage signal
  • S4 provides a low voltage signal
  • S1 provides a high voltage signal
  • both S2 and S3 provide a high voltage signal
  • T1 is turned on
  • T4 is turned on;
  • T0 is turned on, and the data voltage Vdata provided by D1 charges C to increase the potential of N1 until T0 is turned off, and the potential of N1 is Vdata+Vth, where Vth is the threshold voltage of T0 ;
  • E1 provides a low-voltage signal
  • R1 provides a high-voltage signal
  • S4 provides a high-voltage signal
  • S1 provides a low-voltage signal
  • S2 and S3 both provide high-voltage signals
  • T5 T0 and T6 are turned on, and T0 drives O1 to emit light.
  • the display cycle may include the initialization phase t1, data writing Phase t3 and Lighting Phase t4;
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • S4 provides a high voltage signal
  • S1 provides a high voltage signal
  • both S2 and S3 provide a low voltage signal
  • T1 and T2 are turned on to write Vi1 into N1, So that at the beginning of the data writing phase t3, T0 can be turned on; T3 and T7 are turned on, the reset voltage provided by DR is written into N2, and Vi2 is written into the anode of O1 to reset the gate-source voltage of T0, which is conducive to the recovery of T0
  • the speed is increased, so the hysteresis phenomenon of T0 will be improved, and the hysteresis recovery speed will be improved; Vi2 will be written into the anode of O1, so that O1 does not emit light, and the residual charge of the anode of O1 will be removed;
  • E1 provides a high voltage signal
  • R1 provides a high voltage signal
  • S4 provides a low voltage signal
  • S1 provides a high voltage signal
  • both S2 and S3 provide a high voltage signal
  • T1 is turned on
  • T4 is turned on;
  • T0 is turned on, and the data voltage Vdata provided by D1 charges C to increase the potential of N1 until T0 is turned off, and the potential of N1 is Vdata+Vth, where Vth is the threshold voltage of T0 ;
  • E1 provides a low-voltage signal
  • R1 provides a high-voltage signal
  • S4 provides a high-voltage signal
  • S1 provides a low-voltage signal
  • S2 and S3 both provide high-voltage signals
  • T5 T0 and T6 are turned on, and T0 drives O1 to emit light.
  • the display cycle may include successively set initialization phase t1, reset phase t2, data writing phase t3, and light-emitting phase t4; in the initialization phase t1, E1 provides a high voltage signal, and S1 provides a high voltage signal, R1 provides a low voltage signal, both S2 and S3 provide a high voltage signal, S4 provides a high voltage signal, T1 and T2 are turned on, to write Vi1 into N1, so that T0 can be turned on at the beginning of the data writing phase t3;
  • E1 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • both S2 and S3 provide a low voltage signal
  • S4 provides a high voltage signal
  • T3 and T7 open to pass the high voltage provided by DR
  • E1 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • both S2 and S3 provide a high voltage signal
  • S4 provides a low voltage signal
  • T1 and T4 are turned on to write Vdata N2 is connected between N1 and N3, so as to charge C through the data voltage Vdata on D1, and increase the potential of N1 until T0 is turned off.
  • the potential of the gate of T0 is Vdata+Vth;
  • E1 provides a low-voltage signal
  • S1 provides a low-voltage signal
  • R1 provides a high-voltage signal
  • both S2 and S3 provide a high-voltage signal
  • S4 provides a high-voltage signal
  • T5 T6 and T0 are turned on, and T0 drives O1 to emit light.
  • the reset voltage provided by DR may be VDD, or, DR may be the same signal terminal as E1; or, the reset voltage provided by D4 may be the third initialization voltage; but This is not the limit.
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit 12 includes a first transistor T1; the driving circuit 11 Including drive transistor T0;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 electrically connected to the drain of the driving transistor T1;
  • the first initialization circuit 13 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initial voltage terminal, and the source of the second transistor T2 is electrically connected to the The drain of the driving transistor T0 is electrically connected; the first initial voltage terminal is used to provide a first initial voltage Vi1;
  • the data writing circuit 43 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the fourth scanning line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the driving transistor The source electrical connection of T0;
  • the light emission control circuit includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal, and the source of the fifth transistor T5 is electrically connected to the driving transistor T0.
  • the source is electrically connected; the high voltage terminal is used to provide a high voltage signal VDD;
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0.
  • the anode of the organic light emitting diode O1 is electrically connected; the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide a low voltage signal VSS;
  • the second initialization circuit 42 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the third scanning line S3, the drain of the seventh transistor T7 is electrically connected to the second initial voltage terminal, and the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal.
  • the anode of the organic light emitting diode O1 is electrically connected; the second initial voltage terminal is used to provide a second initial voltage Vi2;
  • the energy storage circuit 41 includes a storage capacitor C; a first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is connected to the high voltage end.
  • T1 is an oxide thin film transistor
  • T2, T4, T5, T6 and T7 are low temperature polysilicon thin film transistors
  • T1 is an n-type transistor
  • T2, T4, T5, T6 and T7 are p-type transistors.
  • N1 is the first node electrically connected to the gate of T0
  • N2 is the second node electrically connected to the source of T0
  • N3 is the drain of T0 electrically connected to the third node.
  • the third scan signal and the fourth scan signal are the same scan signal, but not limited thereto.
  • the display cycle may include an initialization phase t1, a data writing phase t3, and a lighting phase t4 that are set successively;
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • both S3 and S4 provide a high voltage signal
  • S1 provides a high voltage signal
  • T1 and T2 are turned on to write Vi1 into N1, so that in the data writing phase At the beginning of t3, T0 can be opened;
  • E1 provides a high voltage signal
  • R1 provides a high voltage signal
  • both S3 and S4 provide a low voltage signal
  • S1 provides a high voltage signal
  • T7 is turned on to write Vi2 to the anode of O1
  • T1 and T4 are turned on , so as to write the data voltage Vdata on D1 into N2, and connect between N1 and N3;
  • T0 is turned on, and C is charged by Vdata to increase the potential of the gate of T0 until the potential of the gate of T0 becomes Vdata+Vth, Vth is the threshold voltage of T0, and T0 is turned off ;
  • E1 provides a low-voltage signal
  • R1 provides a high-voltage signal
  • both S3 and S4 provide a high-voltage signal
  • S1 provides a low-voltage signal
  • T5 T6 and T0 are turned on
  • T0 drives O1 to emit light.
  • the display period may include an initialization phase t1, a data writing phase t3 and a light emitting phase t4 which are set successively;
  • E1 provides a high voltage signal
  • R1 provides a low voltage signal
  • both S3 and S4 provide a high voltage signal
  • S1 provides a high voltage signal
  • T1 and T2 are turned on to write Vi1 into N1, so that in the data writing phase At the beginning of t3, T0 can be opened;
  • E1 provides a high voltage signal
  • R1 provides a high voltage signal
  • both S3 and S4 provide a low voltage signal
  • S1 provides a high voltage signal
  • T7 is turned on to write Vi2 to the anode of O1
  • T1 and T4 are turned on , so as to write the data voltage Vdata on D1 into N2, and connect between N1 and N3;
  • T0 is turned on, and C is charged by Vdata to increase the potential of the gate of T0 until the potential of the gate of T0 becomes Vdata+Vth, Vth is the threshold voltage of T0, and T0 is turned off ;
  • E1 provides a low-voltage signal
  • R1 provides a high-voltage signal
  • both S3 and S4 provide a high-voltage signal
  • S1 provides a low-voltage signal
  • T5 T6 and T0 are turned on
  • T0 drives O1 to emit light.
  • the time interval between the initialization phase t1 and the data writing phase t3 is relatively large, so that the potential of N1 can be reset in advance, which is beneficial to improve the hysteresis phenomenon of T0 .
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit 12 includes a first transistor T1; the driving circuit 11 Including drive transistor T0;
  • the gate of the first transistor T1 is electrically connected to the first scanning line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 electrically connected to the drain of the driving transistor T1;
  • the first initialization circuit 13 includes a second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initial voltage terminal, and the source of the second transistor T2 is electrically connected to the
  • the first electrode of the driving transistor T0 is electrically connected; the first initial voltage terminal is used to provide a first initial voltage Vi1;
  • the reset circuit 20 includes a third transistor T3;
  • the gate of the third transistor T3 is electrically connected to the second scan line S2, the drain of the third transistor T3 is electrically connected to the reset voltage terminal DR, and the source of the third transistor T3 is electrically connected to the reset voltage terminal DR.
  • the second pole of the driving transistor T0 is electrically connected;
  • the data writing circuit 43 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the fourth scanning line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the driving transistor
  • the second pole of T0 is electrically connected;
  • the light emission control circuit 44 includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal, and the source of the fifth transistor T5 is electrically connected to the driving transistor T0.
  • the second pole is electrically connected; the high voltage terminal is used to provide a high voltage signal VDD;
  • the gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the drain of the sixth transistor T6 is electrically connected to the first electrode of the driving transistor T0, and the source of the sixth transistor T6 It is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal, and the low voltage terminal is used to provide a low voltage signal VSS;
  • the second initialization circuit 42 includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the third scanning line S3, the drain of the seventh transistor T7 is electrically connected to the second initial voltage terminal, and the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal.
  • the anode of the organic light emitting diode O1 is electrically connected; the second initial voltage terminal is used to provide a second initial voltage Vi2;
  • the energy storage circuit 41 includes a storage capacitor C; a first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is connected to the high voltage end.
  • T1 is an oxide thin film transistor
  • T2, T3, T4, T5, T6 and T7 are low temperature polysilicon thin film transistors
  • T1 is an n-type transistor
  • T2, T3, T4 , T5, T6 and T7 are p-type transistors.
  • N1 is a first node electrically connected to the gate of T0
  • N2 is a second node electrically connected to the second electrode of T0
  • N3 is a second node electrically connected to the gate of T0.
  • the first pole of T0 can be a drain, and the first pole of T0 can be a source; or, the first pole of T0 can be a source, and the first pole of T0 can be a source.
  • the diode can be a drain.
  • the initialization control signal provided by R1 may be the N-14th level fourth scanning signal
  • the fourth scanning signal provided by S4 may be the Nth level fourth scanning signal. signal, but not limited to.
  • the display cycle may include an initialization phase t1, a reset phase t2, a data writing phase t3, and a light emitting phase t4;
  • E1 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a low voltage signal
  • both S2 and S3 provide a high voltage signal
  • S4 provides a high voltage signal
  • T1 and T2 are turned on to write Vi1 into N1, so that T0 can be turned on when the data writing phase t3 starts;
  • E1 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • both S2 and S3 provide a low voltage signal
  • S4 provides a high voltage signal
  • T3 and T7 open to pass the high voltage provided by DR
  • E1 provides a high voltage signal
  • S1 provides a high voltage signal
  • R1 provides a high voltage signal
  • both S2 and S3 provide a high voltage signal
  • S4 provides a low voltage signal
  • T1 and T4 are turned on to write Vdata N2 is connected between N1 and N3, so as to charge C through the data voltage Vdata on D1, and increase the potential of N1 until T0 is turned off.
  • the potential of the gate of T0 is Vdata+Vth;
  • E1 provides a low-voltage signal
  • S1 provides a low-voltage signal
  • R1 provides a high-voltage signal
  • both S2 and S3 provide a high-voltage signal
  • S4 provides a high-voltage signal
  • T5 T6 and T0 are turned on, and T0 drives O1 to emit light.
  • the driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display cycle includes an initialization phase and a reset phase; the driving method includes:
  • the first initialization circuit writes the first initial voltage into the first terminal of the drive circuit under the control of the initialization control signal
  • the reset circuit In the reset phase, the reset circuit writes a reset voltage into the second terminal of the driving circuit or the first terminal of the driving circuit under the control of the second scan signal.
  • the reset circuit under the control of the second scanning signal, writes the reset voltage into The second end of the driving circuit or the first end of the driving circuit to provide bias voltage to the driving transistor in the driving circuit (the gate potential of the driving transistor is also initialized as Vi1 at this time), so that the driving transistor remains in a reset state to improve
  • the hysteresis of the driving transistor is beneficial to the FFR (first frame response time) of the display.
  • the reset circuit when in the reset phase, writes the reset voltage into the second terminal of the drive circuit under the control of the second scan signal
  • the reset voltage is a high potential constant voltage
  • the first initial voltage is a low potential constant voltage
  • the initialization phase and the reset phase are different time periods; or,
  • the reset voltage and the first initial voltage are low-potential constant voltages, and the initialization phase and the reset phase are the same time period or different time periods.
  • the reset phase is a different time period from the initialization phase, So that in the initialization phase, the first initialization voltage is written into the first terminal of the driving circuit, and in the reset phase, the reset voltage is written into the first terminal of the driving circuit.
  • the pixel circuit may also include a compensation control circuit
  • the driving method may also include:
  • the compensation control circuit controls the communication between the control terminal of the driving circuit and the first terminal of the driving circuit, so as to write the first initial voltage into the driving circuit. control side of the circuit.
  • the compensation control circuit controls the communication between the control terminal of the driving circuit and the first terminal of the driving circuit, and the control terminal of the driving circuit It is only directly electrically connected to the compensation control circuit, and the first initialization circuit writes the first initial voltage into the first terminal of the driving circuit under the control of the initialization control signal, and the first initialization circuit is directly electrically connected to the first terminal of the driving circuit. connection, to initialize the potential of the control terminal of the drive circuit through the compensation control circuit and the first initialization circuit, reduce the leakage path to the control terminal of the drive circuit, and under the condition that the complexity of the pixel circuit design does not increase significantly, the second can be guaranteed.
  • the stability of the voltage of one node is beneficial to improve display quality, improve display uniformity, and reduce flicker (flicker).
  • the pixel circuit also includes a data writing circuit and an energy storage circuit;
  • the display cycle also includes a data writing phase set after the initialization phase;
  • the driving method further includes:
  • the data writing circuit writes the data voltage Vdata provided by the data line into the second terminal of the driving circuit under the control of the fourth scanning signal; Next, the control end of the driving circuit is communicated with the first end of the driving circuit;
  • the drive circuit Under the control of its control terminal, conducts the connection between the first terminal of the drive circuit and the second terminal of the drive circuit to pass the data voltage Vdata Charging the energy storage circuit, thereby changing the potential of the control terminal of the driving circuit until the potential of the control terminal of the driving circuit becomes Vdata+Vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit.
  • the data writing phase may be set after the reset phase.
  • the time interval between the initialization phase and the data writing phase is greater than a predetermined time interval, so as to improve the hysteresis of the driving transistor and reduce the high voltage of the pixel circuit by initializing the gate potential of the driving transistor in advance.
  • Low frequency Flicker flashing
  • the pixel circuit further includes a light emission control circuit
  • the display cycle further includes a light emission stage set after the data writing stage
  • the driving method includes:
  • the light-emitting control circuit controls the communication between the first voltage end and the second end of the driving circuit under the control of the light-emitting control signal, and controls the connection between the first end of the driving circuit and the first pole of the light-emitting element.
  • the drive circuit drives the light-emitting element to emit light.
  • the display device described in at least one embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • the pixel circuit includes a reset circuit and a second initialization circuit; the display device further includes a second scan signal generation module and a third scan signal generation module;
  • the reset circuit is electrically connected to the second scanning line, and the second initialization circuit is electrically connected to the third scanning line;
  • the second scan signal generating module is electrically connected to the second scan line for providing a second scan signal to the second scan line;
  • the third scan signal generating module is electrically connected to the third scan line for providing a third scan signal to the third scan line.
  • the second scan signal and the third scan signal are the same control signal
  • the second scan signal generation module is the same module as the third scan signal generation module.
  • the display device includes a display panel, and the display panel includes a pixel module P0, and the pixel module P0 includes multiple rows and columns of the above-mentioned pixel circuits; the pixel The module P0 is set in the effective display area of the display panel;
  • the display panel also includes a lighting control signal generating module 70, a first scanning signal generating module 71, a first fourth scanning signal generating module 721, a second fourth scanning signal generating module 722, a second scanning signal generating module Signal generating module 73 and the third scanning signal generating module 74;
  • the luminescence control signal generation module 70 is used to provide a luminescence control signal
  • the first scan signal generation module 71 is used to provide a first scan signal
  • the signal generation module 722 is used to provide a fourth scan signal
  • the second scan signal generation module 73 is used to provide a second scan signal
  • the third scan signal generation module 74 is used to provide a third scan signal
  • the light emission control signal generating module 70, the first scanning signal generating module 71 and the first fourth scanning signal generating module 721 are arranged on the left side of the display panel,
  • the second fourth scan signal generation module 722 , the second scan signal generation module 73 and the third scan signal generation module 74 are arranged on the right side of the display panel.
  • the display device includes a display panel, and the display panel includes a pixel module P0, and the pixel module P0 includes multiple rows and multiple columns of the above-mentioned pixel circuits; the pixel The module P0 is set in the effective display area of the display panel;
  • the display panel also includes a lighting control signal generating module 70, a first first scanning signal generating module 711, a second first scanning signal generating module 712, a first fourth scanning signal generating module 721, The second fourth scanning signal generating module 722 and the third scanning signal generating module 74;
  • the luminescence control signal generation module 70 is used to provide a luminescence control signal
  • the first scan signal generation module 71 is used to provide a first scan signal
  • the signal generation module 722 is used to provide a fourth scan signal
  • the third scan signal generation module 74 is used to provide a second scan signal and a third scan signal;
  • the light emission control signal generating module 70, the first first scanning signal generating module 711 and the first fourth scanning signal generating module 721 are arranged on the left side of the display panel,
  • the second fourth scan signal generation module 722 , the second first scan signal generation module 712 and the third scan signal generation module 74 are arranged on the right side of the display panel.
  • the one labeled Vi1 is the first initialization voltage
  • the one labeled Vi2 is the second initialization voltage
  • the one labeled VDD is the high voltage signal
  • the one labeled D1 is the data line
  • the one labeled DR is Reset voltage terminal.
  • the width-to-length ratio W/L of the eighth transistor T8 may be approximately equal to the width-to-length ratio W/L of the seventh transistor T7;
  • the width-to-length ratio W/L of the eight transistor T8 can be greater than the width-to-length ratio W/L of the seventh transistor T7, that is, the width-to-length ratio W/L of T8 can be slightly larger, so that the N2 node can be quickly reset.
  • the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of the seventh transistor T7 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.
  • the design of the above-mentioned transistors is also applicable to the seventh transistor T7 in the embodiments such as Fig. 38a, and the first thin body transistor T1; and the fourth transistor T1 in the embodiments such as Fig. 50 The transistor T4 and the seventh transistor T7.
  • the width-to-length ratio W/L of the eighth transistor T8 may be approximately equal to the width-to-length ratio W/L of the first transistor T1;
  • the width-to-length ratio W/L of the eight transistors T8 may be smaller than the width-to-length ratio W/L of the first transistor T1, so that the resetting capabilities of the N1 node and the N2 node can be balanced.
  • the width-to-length ratio W/L of the eighth transistor T8 can be greater than the width-to-length ratio W/L of the first transistor T1, so that the N2 node can be improved reset capability.
  • the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of the first transistor T1 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.
  • the design of the above transistors is also applicable to the fourth transistor T4 and the third transistor T3 in the embodiment of FIG. 50 and the like.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the names and labels of the functional modules/electrical devices do not limit the specific functions of the functional modules/electrical devices.
  • the driving circuit 1 in Fig. 3-26, the driving sub-circuit in Fig. 27-45, the driving circuit 11 in Fig. 46-60, and the driving circuit 11 in Fig. 61-48 all have the same function;
  • the second reset circuit 3 among Fig. 3-26, the second reset subcircuit among Fig. 27-45, the reset circuit 20 among Fig. 46-60, the reset circuit 20 among Fig. 61-48 all have the same function;
  • the second initialization circuit 32 in FIGS. 46-60, and the second initialization circuit 42 in FIGS. 60-78 are all Have the same function; for another example, the threshold compensation circuit 8 in Fig. 3-26, the second transistor T2 in Fig. 27-45, the compensation control circuit 13 and the compensation control circuit 12 in Fig. 46-60 all have the same function.
  • the data writing circuit 7 among Fig. 3-26, the writing subcircuit among Fig. 27-45, the data writing circuit 41 among Fig. 46-60, the data writing circuit 43 among Fig. 60-78 All have the same function; as another example, the control circuit 5 in Fig. 3-26, the first light emission control subcircuit and the second light emission control subcircuit in Fig.
  • the lighting control circuits 44 in FIGS. 61-78 all have the same function; for another example, the coupling circuit 6 in FIGS. 3-26 , the first capacitor C1 in FIGS. 27-45 , and the energy storage circuit 42 in FIGS. 46-60 , the energy storage circuits 41 in FIGS. 61-78 all have the same function; for another example, the drive transistor T3 in FIGS. 3-26, the drive transistor T3 in FIGS. 27-45, the drive transistor T0 in FIGS. 46-60, The drive transistors T0 in FIGS. 61-78 all have the same function.
  • the above-mentioned functional modules/electrical devices with the same function can be replaced with each other to form a new embodiment, wherein the replacement of the functional modules/electrical devices can include the replacement of the functional modules/electrical devices themselves, the replacement of the signal terminals connected to the functional modules/electrical devices Replacement of voltage state.

Abstract

提供了一种像素电路及其驱动方法、显示装置，像素电路包括：驱动子电路、第一复位子电路、第二复位子电路和发光元件，驱动子电路被配置为响应于第一节点(N1)的控制信号，在驱动子电路的第一极和第二极之间产生驱动电流；第一复位子电路被配置为响应于第一发光控制信号线(EM1)或者第二复位控制信号线(Reset2)的信号，向发光元件的阳极端写入第一复位信号；第二复位子电路被配置为响应于第一复位控制信号线(Reset1)的信号，向驱动子电路的第一极或第二极写入第二复位信号；第二复位信号大于第一复位信号。

Description

像素电路及其驱动方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种像素电路及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种像素电路，包括：驱动子电路、第一复位子电路、第二复位子电路和发光元件，其中：所述驱动子电路被配置为响应于第一节点的控制信号，在第二节点和第三节点之间产生驱动电流；所述第一复位子电路被配置为响应于第一发光控制信号线或者第二复位控制信号线的信号，向所述发光元件的阳极端写入第一复位信号；所述第二复位子电路被配置为响应于第一复位控制信号线的信号，向所述驱动子电路的第一极或第二极写入第二复位信号；所述第二复位信号大于所述第一复位信号。
在一些示例性实施方式中，所述第二复位信号的绝对值大于所述驱动子电路的阈值电压的1.5倍。
在一些示例性实施方式中，所述第二复位信号的幅值大于0。
在一些示例性实施方式中，该像素电路还包括：写入子电路、补偿子电 路、第一发光控制子电路和第二发光控制子电路，其中：所述写入子电路被配置为响应于第二扫描信号线的信号，向所述第二节点写入数据信号；所述补偿子电路被配置为响应于第一扫描信号线的信号，将所述第三节点的第一复位信号或第二复位信号写入第一节点；还被配置为响应于所述第一扫描信号线的信号，对所述第一节点进行补偿；所述第一发光控制子电路被配置为响应于所述第一发光控制信号线的信号，向所述第二节点提供第一电源线的信号；所述第二发光控制子电路被配置为响应于第二发光控制信号线的信号，将第四节点的第一复位信号写入第三节点；还被配置为响应于所述第二发光控制信号线的信号，在所述第三节点和第四节点之间允许驱动电流通过。
在一些示例性实施方式中，所述第二复位信号来源于以下至少之一的信号线：所述第一电源线、所述第一发光控制信号线、所述第二发光控制信号线或者第三电源线。
在一些示例性实施方式中，所述第一复位控制信号线的信号的脉冲宽度与所述第二扫描信号线的信号的脉冲宽度大致相同。
在一些示例性实施方式中，所述第一发光控制信号线的信号脉冲与所述第二发光控制信号线的信号脉冲相差一个或两个时间单元，一个所述时间单元为一行子像素扫描的时间。
在一些示例性实施方式中，所述第一复位子电路包括第一晶体管，其中：所述第一晶体管的控制极与所述第一发光控制信号线或者第二复位控制信号线连接，所述第一晶体管的第一极与第一复位信号线连接，所述第一晶体管的第二极与所述第四节点连接。
在一些示例性实施方式中，所述补偿子电路包括第二晶体管和第一电容，其中：所述第二晶体管的控制极与所述第一扫描信号线连接，所述第二晶体管的第一极与第三节点连接，所述第二晶体管的第二极与所述第一节点连接；所述第一电容的一端与所述第一节点连接，所述第一电容的另一端与所述第一电源线连接。
在一些示例性实施方式中，所述驱动子电路包括第三晶体管，其中：所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与第二节点连接，所述第三晶体管的第二极与所述第三节点连接。
在一些示例性实施方式中，所述写入子电路包括第四晶体管，其中：所述第四晶体管的控制极与所述第二扫描信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第二节点连接。
在一些示例性实施方式中，所述第一发光控制子电路包括第五晶体管，其中：所述第五晶体管的控制极与所述第一发光控制信号线连接，所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与所述第二节点连接。
在一些示例性实施方式中，所述第二发光控制子电路包括第六晶体管，其中：所述第六晶体管的控制极与所述第二发光控制信号线连接，所述第六晶体管的第一极与第三节点连接，所述第六晶体管的第二极与所述第四节点连接。
在一些示例性实施方式中，所述第二复位子电路包括第七晶体管，其中：所述第七晶体管的控制极与所述复位控制信号线连接，所述第七晶体管的第一极与第二复位信号线连接，所述第七晶体管的第二极与所述第二节点或所述第三节点连接。
在一些示例性实施方式中，所述第一复位子电路包括第一晶体管，所述补偿子电路包括第二晶体管和第一电容，所述驱动子电路包括第三晶体管，所述写入子电路包括第四晶体管，所述第一发光控制子电路包括第五晶体管，所述第二发光控制子电路包括第六晶体管，所述第二复位子电路包括第七晶体管，其中：所述第一晶体管的控制极与所述第一发光控制信号线或者第二复位控制信号线连接，所述第一晶体管的第一极与第一复位信号线连接，所述第一晶体管的第二极与所述第四节点连接；所述第二晶体管的控制极与所述第一扫描信号线连接，所述第二晶体管的第一极与第三节点连接，所述第二晶体管的第二极与所述第一节点连接；所述第一电容的一端与所述第一节点连接，所述第一电容的另一端与所述第一电源线连接；所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与第二节点连接，所述第三晶体管的第二极与所述第三节点连接；所述第四晶体管的控制极与所述第二扫描信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第二节点连接；所述第五晶体管的控制极与所述 第一发光控制信号线连接，所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与所述第二节点连接；所述第六晶体管的控制极与所述第二发光控制信号线连接，所述第六晶体管的第一极与第三节点连接，所述第六晶体管的第二极与所述第四节点连接；所述第七晶体管的控制极与所述复位控制信号线连接，所述第七晶体管的第一极与第二复位信号线连接，所述第七晶体管的第二极与所述第二节点或所述第三节点连接。
在一些示例性实施方式中，所述第一晶体管、所述第二晶体管和所述第七晶体管中的至少一个为第一类型晶体管，所述第三晶体管至所述第六晶体管均为第二类型晶体管，所述第一类型晶体管与所述第二类型晶体管的晶体管类型不同。
在一些示例性实施方式中，所述第一类型晶体管为N型薄膜晶体管；所述第二类型晶体管为P型薄膜晶体管。
在一些示例性实施方式中，所述第一晶体管、所述第二晶体管和所述第七晶体管中的至少一个为铟镓锌氧化物薄膜晶体管，所述第三晶体管至所述第六晶体管均为低温多晶硅薄膜晶体管。
本公开实施例还提供了一种显示装置，包括：如上任一项所述的像素电路。
本公开实施例还提供了一种像素电路的驱动方法，用于驱动如上所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，所述驱动方法包括：在复位阶段，第一复位子电路响应于第一发光控制信号线或者第二复位控制信号线的信号，向发光元件的阳极端写入第一复位信号；在重置阶段，第二复位子电路响应于第一复位控制信号线的信号，向驱动子电路的第一极或第二极写入第二复位信号；所述第二复位信号大于所述第一复位信号；在发光阶段，驱动子电路响应于第一节点的控制信号，在第二节点和第三节点之间产生驱动电流。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为相关技术中像素驱动电路的电路结构示意图；
图2为图1像素驱动电路一种驱动方法中各节点的时序图；
图3为图1中像素驱动电路在图2所示驱动方法中第一节点、第二节点、第三节点的仿真时序图；
图4为本公开像素驱动电路一种示例性实施例的结构示意图；
图5为本公开像素驱动电路另一种示例性实施例的结构示意图；
图6为本公开像素驱动电路另一种示例性实施例中的结构示意图；
图7为本公开像素驱动电路另一种示例性实施例中的结构示意图；
图8为图7中像素驱动电路一种驱动方法中各节点的时序图；
图9为图7中像素驱动电路在图8所示驱动方法中第一节点、第二节点、第三节点的仿真时序图；
图10为本公开像素驱动电路一种示例性实施例的结构图；
图11为本公开像素驱动电路另一种示例性实施例的结构示意图；
图12为本公开像素驱动电路另一种示例性实施例的结构示意图；
图13为图12中像素驱动电路一种驱动方法中各节点的时序图；
图14为本公开像素驱动电路另一种示例性实施例的结构示意图；
图15为本公开显示面板一种示例性实施例中像素驱动电路的分布图；
图16为本公开显示面板另一种示例性实施例中像素驱动电路的分布图；
图17为本公开显示面板另一种示例性实施例中像素驱动电路的分布图；
图18为本公开显示面板一种示例性实施例的部分结构版图；
图19为图18中第一导电层的结构版图；
图20为图18中第二导电层的结构版图；
图21为图18中第二有源层的结构版图；
图22为图18中第三导电层的结构版图；
图23为图18中第四导电层的结构版图；
图24为图18中第一导电层、第二导电层、第二有源层的结构版图；
图25为图18中第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图26为图18中沿虚线A的部分剖视图；
图27为本公开实施例提供的像素电路的结构示意图之一；
图28为本公开实施例提供的像素电路的结构示意图之二；
图29为本公开实施例提供的第一复位子电路的结构示意图；
图30为本公开实施例提供的补偿子电路的结构示意图；
图31为本公开实施例提供的驱动子电路的结构示意图；
图32为本公开实施例提供的写入子电路的结构示意图；
图33为本公开实施例提供的第一发光控制子电路的结构示意图；
图34为本公开实施例提供的第二发光控制子电路的结构示意图；
图35为本公开实施例提供的第二复位子电路的结构示意图之一；
图36为本公开实施例提供的第二复位子电路的结构示意图之二；
图37a为本公开实施例提供的像素电路的等效电路图之一；
图37b为本公开实施例提供的像素电路的等效电路图之二；
图38a为本公开实施例提供的像素电路的等效电路图之三；
图38b为本公开实施例提供的像素电路的等效电路图之四；
图39为图37a或图37b所示像素电路在一个扫描周期内的工作时序图；
图40为图38a或38b所示像素电路在一个扫描周期内的工作时序图；
图41为图37a所示的像素电路在复位阶段的晶体管工作状态示意图；
图42为图37a所示的像素电路在重置阶段的晶体管工作状态示意图；
图43为图37a所示的像素电路在数据写入阶段的晶体管工作状态示意图；
图44为图37a所示的像素电路在发光阶段的晶体管工作状态示意图；
图45为本公开实施例提供的像素电路的驱动方法的流程示意图；
图46是本公开至少一实施例所述的像素电路的结构图；
图47是本公开至少另一实施例所述的像素电路的结构图；
图48是本公开至少又一实施例所述的像素电路的结构图；
图49是本公开至少又一实施例所述的像素电路的结构图；
图50是本公开至少一实施例所述的像素电路的电路图；
图51是本公开如图50所示的像素电路的至少一实施例的工作时序图；
图52是本公开至少另一实施例所述的像素电路的电路图；
图53是本公开至少又一实施例所述的像素电路的电路图；
图54是本公开至少又一实施例所述的像素电路的电路图；
图55是相邻两行像素电路与同一行复位电压线电连接的示意图；
图56是相邻两列像素电路与同一列复位电压线电连接的示意图；
图57是相邻行相邻列像素电路共用复位电压线的示意图；
图58是网格状设置的复位电压线与多个像素电路的连接关系及位置关系示意图；
图59是本公开至少一实施例所述的显示装置的结构图；
图60是本公开至少另一实施例所述的显示装置的结构图；
图61是本公开至少又一实施例所述的像素电路的结构图；
图62是本公开至少又一实施例所述的像素电路的结构图；
图63是本公开至少又一实施例所述的像素电路的结构图；
图64是本公开至少又一实施例所述的像素电路的结构图；
图65是本公开至少又一实施例所述的像素电路的结构图；
图66是本公开至少又一实施例所述的像素电路的结构图；
图67是本公开至少又一实施例所述的像素电路的结构图；
图68是本公开至少又一实施例所述的像素电路的电路图；
图69是图68所示的像素电路的至少一实施例的工作时序图；
图70是图68所示的像素电路的至少另一实施例的工作时序图；
图71是图68所示的像素电路的至少又一实施例的工作时序图；
图72是本公开至少一实施例所述的像素电路的结构图；
图73是图72所示的像素电路的至少一实施例的工作时序图；
图74是图72所示的像素电路的至少另一实施例的工作时序图；
图75是本公开至少又一实施例所述的像素电路的结构图；
图76是图75所示的像素电路的至少一实施例的工作时序图；
图77是本公开至少又一实施例所述的显示装置的结构图；
图78是本公开至少又一实施例所述的显示装置的结构图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，驱动晶体管T3的栅极连接第一节点N1，第一极连接第二节点N2，第二极连接第三节点N3；第四晶体管T4的第一极连接数据信号端Da、第二极连接 第二节点N2，栅极连接栅极驱动信号端G2；第五晶体管T5的第一极连接第一电源端VDD，第二极连接第二节点N2，栅极连接使能信号端EM；第二晶体管T2的第一极连接第一节点N1，第二极连接第三节点N3，栅极连接栅极驱动信号端G1；第六晶体管T6的第一极连接第三节点N3，第二极连接第七晶体管T7的第一极，栅极连接使能信号端EM，第七晶体管T7的第二极连接第二初始信号端Vinit2，栅极连接第二复位信号端Re2；第一晶体管T1的第一极连接第一节点N1，第二极连接第一初始信号端Vinit1，栅极连接第一复位信号端Re1，电容C连接于第一电源端VDD和第一节点N1之间。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和电源端VSS之间。其中，第一晶体管T1和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型金属氧化物晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，低温多晶体硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端和第二初始信号端可以根据实际情况输出相同或不同电压信号。
如图2所示，为图1像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示栅极驱动信号端G1的时序，G2表示栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序，N1表示第一节点N1的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、阈值补偿阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出高电平信号，第一晶体管T1导通，第一初始信号端Vinit1向第一节点N1输入初始信号。在阈值补偿阶段t2：栅极驱动信号端G1输出高电平信号，栅极驱动信号端G2输出低电平信号，第四晶体管T4、第二晶 体管T2导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压，在第二复位阶段t3，第二复位信号端Re2输出低电平信号，第七晶体管T7导通，第二初始信号端Vinit2向第六晶体管T6的第二极输入初始信号。发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
相关技术中，像素驱动电路中驱动晶体管的栅极和源极之间存在寄生电容，像素驱动电路在复位阶段，驱动晶体管的栅极电压被初始化到初始电压，在上述寄生电容耦合作用下，驱动晶体管的源极电压也相应发生变化。在复位阶段对不同灰阶复位时，驱动晶体管栅极电压的变化量不同，从而驱动晶体管源极电压的变化量也不同，进而导致复位阶段完成后驱动晶体管Vgs(栅极源极电压差)不同。如图3所示，为图1中像素驱动电路在图2所示驱动方法中第一节点、第二节点、第三节点的仿真时序图，N1表示第一节点N1的时序图，N2表示第二节点N2的时序图，N3表示第三节点N3的时序图，其中，图3具体示出了图1所示像素驱动电路在四种数据信号下各个节点的时序图，图3中复位阶段t1需要对该四种数据信号下的第一节点N1进行复位，本示例性实施例以两种数据信号下各个节点的时序进行说明。如图3所示，在第一数据信号下，各个节点的时序如曲线Vda1所示，在第二数据信号下，各个节点的时序如曲线Vda2所示。由于第一数据信号和第二数据信号的电压不同，在复位阶段t1前，第一节点N1的电压不同，第三节点N3的电压也不相同，第二节点的电压均为第一电源端VDD的电压；在复位阶段t1，第一节点N1在两种数据信号下的电压均被下拉到初始电压，由于第一数据信号下第一节点N1的下拉变化量小于第二数据信号下第一节点N1 的下拉变化量，从而第一数据信号下第二节点的下拉变化量小于第二数据信号下第二节点N2的下拉变化量，即复位阶段，第一数据信号下第二节点N2的电压小于第二数据信号下第二节点N2的电压，从而在不同数据信号下，驱动晶体管Vgs(栅极源极电压差)不同。同时由于驱动晶体管的Vgs会影响其阈值电压，从而显示面板会发生残像和闪烁问题。例如，当显示面板从黑白画面转变为同一灰阶画面时，由于黑白画面对应像素点中驱动晶体管的阈值电压不同，从而导致转变为同一灰阶画面后，上一帧黑白画面所在区域会分别显示不同的灰度，即出现残像问题。
基于此，本示例性实施例提供一种像素驱动电路，如图4所示，为本公开像素驱动电路一种示例性实施例的结构示意图。其中，所述像素驱动电路可以包括：驱动电路1、第一复位电路2、第二复位电路3，驱动电路1连接第一节点N1、第二节点N2，用于根据所述第一节点N1和所述第二节点N2的压差输出驱动电流；第一复位电路2连接所述第一节点N1、第一初始信号端Vinit1、第一复位信号端Re1，用于响应所述第一复位信号端Re1的信号将所述第一初始信号端Vinit1的信号传输到所述第一节点N1；第二复位电路3连接所述第二节点N2、第一电源端VGH，用于响应一控制信号将所述第一电源端VGH的信号传输到所述第二节点N2。
本示例性实施例中，像素驱动电路可以在复位阶段，利用第一复位电路2将所述第一初始信号端Vinit1的信号传输到所述第一节点N1，同时，利用第二复位电路3将所述第一电源端VGH的信号传输到所述第二节点N2，从而使得在不同数据信号下，该像素驱动电路均可以将驱动晶体管的栅源电压差复位到同一值，从而改善了显示面板的残像和闪烁的问题。
本示例性实施例中，如图4所示，所述驱动电路1还可以连接第三节点N3，所述驱动电路1可以包括：驱动晶体管T3，驱动晶体管T3的栅极连接所述第一节点N1，第一极连接所述第二节点N2，第二极连接所述第三节点N3。其中，驱动晶体管T3可以为P型晶体管，例如，驱动晶体管T3可以为P型低温多晶硅晶体管，驱动晶体管T3可以根据第一节点N1和第二节点N2的电压差向第三节点输入驱动电流。应该理解的是，在其他示例性实施例中，驱动晶体管T3也可以为N型晶体管，当驱动晶体管T3为N型晶体管 时，驱动晶体管可以根据第一节点N1和第二节点N2的电压差向第二节点输入驱动电流。此外，驱动电路1还可以包括多个驱动晶体管，多个驱动晶体管可以并联于第二节点和第三节点之间。
本示例性实施例中，如图4所示，所述第一复位电路2可以包括：第一晶体管T1，第一晶体管T1的栅极连接所述第一复位信号端Re1，第一极连接所述第一初始信号端Vinit1，第二极连接所述第一节点N1。所述第二复位电路3的导通电平可以与所述第一复位电路2的导通电平极性相同，所述第二复位电路3还可以连接所述第一复位信号端Re1，所述第二复位电路3可以用于响应所述第一复位信号端Re1的信号将所述第一电源端VGH的信号传输到所述第二节点N2。如图4所示，所述第二复位电路3可以包括：第八晶体管T8，第八晶体管T8的栅极连接所述第一复位信号端Re1，第一极连接所述第一电源端VGH，第二极连接所述第二节点N2。
需要说明的是，该像素驱动电路需要在阈值补偿阶段导通驱动晶体管T3，因此，第一初始信号端Vinit1与第一电源端VGH的电压差Vinit1-Vgh需要小于驱动晶体管T3的阈值电压，其中，Vinit1为第一初始信号端的电压，Vgh为第一电源端VGH的电压。此外，在其他示例性实施例中，所述第二复位电路3还可以响应于一控制信号将其他信号端的信号传输到第二节点，以对第二节点进行复位。
本示例性实施例中，第一晶体管T1、第八晶体管T8均可以为氧化物晶体管，例如，第一晶体管T1、第八晶体管T8的半导体材料可以为氧化铟镓锌，相应的，第一晶体管T1、第八晶体管T8可以为N型晶体管。氧化物晶体管具有较小的关断漏电流，从而可以降低第一节点N1通过第一晶体管T1的漏电流，以及第二节点N2通过第八晶体管T8的漏电流。
应该理解的是，在其他示例性实施例中，所述第二复位电路3的导通电平与所述第一复位电路2的导通电平极性还可以相反。例如，如图5所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。所述第二复位电路3还可以连接所述第二复位信号端Re2，所述第二复位电路3可以用于响应所述第二复位信号端Re2的信号将所述第一电源端VGH的信号传输到所 述第二节点N2；其中，所述第二复位信号端Re2的信号与所述第一复位信号端Re1的信号极性可以相反。所述第一复位电路2可以包括：N型的第一晶体管T1，第一晶体管T1的栅极连接所述第一复位信号端Re1，第一极连接所述第一初始信号端Vinit1，第二极连接所述第一节点N1。所述第二复位电路3可以包括：P型的第八晶体管T8，第八晶体管T8的栅极连接所述第二复位信号端Re2，第一极连接所述第一电源端VGH，第二极连接所述第二节点N2。
本示例性实施例中，如图6所示，为本公开像素驱动电路另一种示例性实施例中的结构示意图。所述像素驱动电路还可以包括：控制电路5、耦合电路6，控制电路5连接第二电源端VDD、第二节点N2、第三节点N3、第四节点N4、使能信号端EM，用于响应所述使能信号端EM的信号将所述第二电源端VDD的信号传输到所述第二节点N2，以及用于响应所述使能信号端EM的信号以连通所述第三节点N3和所述第四节点N4；耦合电路6连接于所述第二电源端VDD和所述第一节点N1之间。
本示例性实施例中，如图6所示，所述像素驱动电路还可以包括：数据写入电路7、阈值补偿电路8，数据写入电路7连接所述第二节点N2、数据信号端Vdata、第一栅极驱动信号端G1，用于响应所述第一栅极驱动信号端G1的信号将所述数据信号端Vdata的信号传输到所述第二节点N2；阈值补偿电路8可以连接所述第一节点N1、第三节点N3，用于响应一控制信号以连接所述第一节点N1和所述第三节点N3。数据写入电路7、阈值补偿电路8用于在阈值补偿阶段导通，以向第一节点N1写入补偿电压Vdata+Vth，其中，Vdata为数据信号端的电压，Vth为驱动晶体管的阈值电压。应该理解的是，在其他示例性实施例中，向第一节点N1写入补偿电压还有其他方式，例如，可以将数据写入电路连接于所述第三节点N3、数据信号端Vdata、第一栅极驱动信号端G1，数据写入电路用于响应所述第一栅极驱动信号端G1的信号将所述数据信号端Vdata的信号传输到所述第三节点N3，同时可以将阈值补偿电路8连接于所述第一节点N1、第二节点N2，阈值补偿电路8可以用于响应一控制信号以连接所述第一节点N1和所述第二节点N2。当数据写入电路7、阈值补偿电路8导通时，该像素驱动电路同样可以向第一节点 N1写入补偿电压Vdata+Vth。
本示例性实施例中，如图6所示，所述第四节点N4可以用于连接一发光单元OLED，发光单元OLED可以为发光二极管，该发光单元OLED另一电极可以连接第四电源端VSS，第四电源端VSS的电压小于第二电源端VDD的电压。所述像素驱动电路还可以包括：第三复位电路4，第三复位电路4连接所述第四节点N4、第二初始信号端Vinit2，用于响应一控制信号将所述第二初始信号端Vinit2的信号传输到所述第四节点N4。其中，向第四节点N4写入初始信号可以消除发光二极管内部发光界面上没有复合的载流子，缓解发光二极管的老化。
本示例性实施例中，如图6所示，所述控制电路5可以包括：第五晶体管T5、第六晶体管T6，第五晶体管T5的栅极连接所述使能信号端EM，第一级连接所述第二电源端VDD，第二极连接所述第二节点N2；第六晶体管T6的栅极连接所述使能信号端EM，第一极连接所述第三节点N3，第二极连接所述第四节点N4。所述耦合电路6可以包括：第三电容C3，第三电容C3连接于所述第二电源端VDD和所述第一节点N1之间。
本示例性实施例中，如图6所示，所述阈值补偿电路8的导通电平和所述数据写入电路7的导通电平极性可以相反；所述阈值补偿电路8还可以连接第二栅极驱动信号端G2，所述阈值补偿电路8用于响应所述第二栅极驱动信号端G2的信号以连接所述第一节点N1和所述第三节点N3；其中，所述第一栅极驱动信号端G1的信号和所述第二栅极驱动信号端G2的信号极性可以相反。所述数据写入电路7可以包括：第四晶体管T4，第四晶体管T4的栅极连接所述第一栅极驱动信号端G1，第一极连接所述数据信号端Vdata，第二极连接所述第二节点N2；所述阈值补偿电路8可以包括：第二晶体管T2，第二晶体管T2的栅极连接所述第二栅极驱动信号端G2，第一极连接所述第一节点N1，第二极连接所述第三节点N3；其中，所述第四晶体管T4可以为P型晶体管，例如，第四晶体管T4可以为P型低温多晶体硅晶体管，低温多晶体硅晶体管具有较高的载流子迁移率，从而可以提高第四晶体管T4的响应速度；所述第二晶体管T2可以为N型晶体管，例如，第二晶体管T2可以为氧化物晶体管，第二晶体管T2的半导体材料可以为氧化铟镓锌。将 第二晶体管T2设置为氧化物晶体管可以降低该像素驱动电路在发光节点第一节点N1通过第二晶体管的漏电流。
应该理解的是，在其他示例性实施例中，第四晶体管T4和第二晶体管T2也可以同为N型晶体管或P型晶体管，相应的，第四晶体管T4和第二晶体管T2也可以共用同一栅极驱动信号端。
本示例性实施例中，如图6所示，所述第三复位电路4还可以连接第三复位信号端Re3，所述第三复位电路4可以用于响应所述第三复位信号端Re3的信号将所述第二初始信号端Vinit2的信号传输到所述第四节点N4。所述第三复位电路4可以包括：第七晶体管T7，第七晶体管T7的栅极连接所述第三复位信号端Re3，第一极连接所述第二初始信号端Vinit2，第二极连接所述第四节点N4。其中，第七晶体管T7可以为P型晶体管，例如，第七晶体管T7可以为P型低温多晶体硅晶体管，低温多晶体硅晶体管具有较高的载流子迁移率，从而第七晶体管T7具有较快的响应速度。
本示例性实施例中，如图6所示，第八晶体管T8的第一极和第五晶体管T5的第一极分别连接不同的电源端，应该理解的是，在其他示例性实施例中，如图7所示，为本公开像素驱动电路另一种示例性实施例中的结构示意图，第八晶体管T8的第一极和第五晶体管T5的第一极可以连接同一电源端，即所述第二电源端VDD可以共用所述第一电源端VGH。
如图8所示，为图7中像素驱动电路一种驱动方法中各节点的时序图，其中，G1表示第一栅极驱动信号端的时序，G2表示第二栅极驱动信号端的时序，Re1表示第一复位信号端的时序，Re3表示第三复位信号端的时序，EM表示使能信号端的时序。该像素驱动电路驱动方法可以包括四个阶段：复位阶段t1、阈值补偿阶段t2、缓冲阶段t3、发光阶段t4。其中，在复位阶段t1：使能信号端EM、第一复位信号端Re1、第一栅极驱动信号端输出高电平信号，第二栅极驱动信号端G2、第三复位信号端Re3输出低电平信号，第一晶体管T1、第七晶体管T7、第八晶体管T8导通，第一初始信号端Vinit1向第一节点N1输入第一初始信号，第一电源端VDD向第二节点N2输入电源信号，第二初始信号端Vinit2向第四节点输入第二初始信号，其中，第一 初始信号和第二初始信号的电压可以相同或不同。在阈值补偿阶段t2：使能信号端EM、第二栅极驱动信号端G2、第三复位信号端输出高电平信号，第一复位信号端Re1、第一栅极驱动信号端G1输出低电平信号，第二晶体管T2、第四晶体管T4导通，数据信号端Vdata向第一节点N1写入补偿电压Vdata+Vth，其中，Vdata为数据信号端的电压，Vth为驱动晶体管的阈值电压。在缓冲阶段t3：使能信号端EM、第三复位信号端Re3、第一栅极驱动信号端G1输出高电平信号，第二栅极驱动信号端G2、第一复位信号端Re1输出低电平信号，所有晶体管均关断。在发光阶段t4：第三复位信号端Re3、第一栅极驱动信号端G1输出高电平信号，使能信号端EM、第二栅极驱动信号端G2、第一复位信号端Re1输出低电平信号，第五晶体管T5、第六晶体管T6导通，驱动晶体管T3在第三电容C3存储的电压Vdata+Vth作用下发光。应该理解的是，在其他示例性实施例中，该驱动方法还可以不包括缓冲阶段；第一晶体管T1和第七晶体管T7还可以在不同阶段导通。在阈值补偿阶段t2，第一栅极驱动信号端G1的有效电平(低电平)时长可以小于第二栅极驱动信号端G2的有效电平(高电平)时长，在该阈值补偿阶段t2，第一栅极驱动信号端G1可以扫描一行像素驱动电路，第二栅极驱动信号端G2可以逐行扫描多行像素驱动电路，例如两行像素驱动电路。
如图9所示，为图7中像素驱动电路在图8所示驱动方法中第一节点、第二节点、第三节点的仿真时序图，N1表示第一节点N1的时序图，N2表示第二节点N2的时序图，N3表示第三节点N3的时序图，其中，图9具体示出了图7所示像素驱动电路在四种数据信号下各个节点的时序图，图9中复位阶段t1需要对该四种数据信号下的第一节点N1进行复位，本示例性实施例以两种数据信号下各个节点的时序进行说明。如图9所示，在第一数据信号下，各个节点的时序如曲线Vda1所示，在第二数据信号下，各个节点的时序如曲线Vda2所示。如图9所示，由于第一数据信号和第二数据信号的电压不同，在复位阶段t1前，第一节点N1的电压不同，第三节点N3的电压也不相同，第二节点的电压均为第一电源端VDD的电压；在复位阶段t1，第一节点N1在两种数据信号下的电压均下拉到第一初始信号的电压，同时第二节点N2的电压也被初始化到第一电源端VDD的电压，从而在复位阶 段结束时，第一数据信号下驱动晶体管的栅源电压差等于第二数据信号下驱动晶体管的栅源电压差，从而该像素驱动电路能够改善由于不同数据信号下驱动晶体管栅源电压差不同而造成的残像问题。
本示例性实施例还提供一种像素驱动电路驱动方法，用于驱动上述的像素驱动电路，其中，所述方法包括：
在复位阶段，利用所述第一复位电路2将第一初始信号端Vinit1的信号传输到第一节点N1，同时利用所述第二复位电路3将所述第一电源端VGH的信号传输到所述第二节点N2。该像素驱动方法在上述内容中已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种显示面板，该显示面板可以包括上述的像素驱动电路。其中，该显示面板可以应用于手机、平板电脑、电视等显示装置。
如图1所示，相关技术中，第一节点N1与栅极驱动信号端G1之间具有寄生电容，如图2所示，在阈值补偿阶段t2结束时，栅极驱动信号端G1的信号从高电平变为低电，在该寄生电容耦合作用下，第一节点N1的电压被栅极驱动信号端G1拉低，从而使得数据信号端的最大电压无法实现0灰阶(黑画面)的显示，或者说如果需要正常显示0灰阶需要数据信号端提供更大的电压信号。
基于此，本示例性实施例提供一种像素驱动电路，如图10所示，为本公开像素驱动电路一种示例性实施例的结构图，其中，所述像素驱动电路可以包括：驱动晶体管T3、数据写入电路7、阈值补偿电路8、第一电容C1、第二电容C2，驱动晶体管T3的栅极连接第一节点N1，第一极连接第二节点N2，第二极连接第三节点N3；数据写入电路7连接所述第二节点N2、数据信号端Vdata，用于响应第一栅极驱动信号端G1的信号将所述数据信号端Vdata的信号传输到所述第二节点N2；阈值补偿电路8连接所述第一节点N1、第三节点N3、第二栅极驱动信号端G2，用于响应所述第二栅极驱动信号端G2的信号以连通所述第一节点N1和所述第三节点N3；第一电容C1连接于所述第一节点N1和所述第一栅极驱动信号端G1之间；第二电容C2 连接于所述第一节点N1和所述第二栅极驱动信号端G2之间；其中，所述数据写入电路7的导通电平为低电平，所述阈值补偿电路8的导通电平为高电平，且所述第一电容C1的电容值大于所述第二电容C2的电容值。
本示例性实施例中，在阈值补偿阶段，第一栅极驱动信号端G1可以输出低电平信号，第二栅极驱动信号端G2可以输出高电平信号，从而实现向第一节点N1写入补偿电压Vdata+Vth，Vdata为数据信号端的电压，Vth为驱动晶体管T3的阈值电压。阈值补偿阶段结束后，第一栅极驱动信号端G1的信号从低电平变为高电平，在第一电容C1耦合作用下，第一节点N1被第一栅极驱动信号端G1拉高；第二栅极驱动信号端G2的信号从高电平变为低电平，在第二电容C2耦合作用下，第一节点N1被第二栅极驱动信号端G2拉低，由于第一电容C1的电容值大于第二电容C2的电容值，因此，第一节点N1总体被拉高。从而与该像素驱动电路对应设置的源极驱动电路仅需要向数据信号端提供较小的电压信号即可实现该像素驱动电路的极限灰阶(最小灰阶或最大灰阶)显示，即应用该像素驱动电路的显示面板可以具有较小的功耗。
本示例性实施例中，驱动晶体管T3可以为P型晶体管，例如，驱动晶体管可以为P型低温多晶硅晶体管，当驱动晶体管T3为P型晶体管时，第一节点N1的电压越大驱动晶体管T3的输出电流越小，即该像素驱动电路能够降低0灰阶下源极驱动电路输出的数据信号电压。应该理解的是，在其他示例性实施例中，驱动晶体管T3也可以为N型晶体管，当驱动晶体管T3为N型晶体管时，第一节点N1电压越大驱动晶体管T3的输出电流越大，即该像素驱动电路能够降低最大灰阶下源极驱动电路输出的数据信号电压。
本示例性实施例中，所述第一电容C1的电容值为C1，所述第二电容C2的电容值为C2，C1/C2可以大于等于1.5且小于等于4，例如，C1/C2可以为1.5、2、2.3、2.5、3、3.5、4。其中，C1/C2的值越大第一节点N1被上拉的效果越明显。
Figure PCTCN2021109884-appb-000001
Figure PCTCN2021109884-appb-000002
如上表所示，Vdata-L0表示0灰阶下各种颜色子像素所需数据信号的电压，ΔV表示源极驱动电路的最大输出电压和0灰阶下所需最大数据信号的电压之差，其中，源极驱动电路的最大输出电压为6.89V。其中，C1/C2为1.35、1.73、2.05、2.3所对应的多组数据为同一设计结构(除C1/C2不同以外，其他结构相同)下的多组数据，C1/C2为2.2所对应的数据为另一设计结构下的数据，根据该表可以看出，在同一设计结构下，C1/C2越大，第一节点N1被上拉的效果越明显，从而0灰阶下所需数据信号的电压越小。
本示例性实施例中，如图10所示，所述数据写入电路7可以包括：P型的第四晶体管T4，例如，第四晶体管T4可以为P型的低温多晶体硅晶体管，第四晶体管T4的栅极连接所述第一栅极驱动信号端G1，第一极连接所述第二节点N2，第二极连接所述数据信号端Vdata；所述阈值补偿电路8可以包括：N型的第二晶体管T2，例如，第二晶体管T2可以为N型的氧化物晶体管，该氧化物晶体管的半导体材料可以为氧化铟镓锌，第二晶体管T2的栅极连接所述第二栅极驱动信号端G2，第一极连接所述第一节点N1，第二极连接所述第三节点N3。
本示例性实施例中，如图11所示，为本公开像素驱动电路另一种示例性实施例的结构示意图，所述像素驱动电路还可以包括：控制电路5、耦合电路6，控制电路5可以连接第二电源端VDD、第二节点N2、第三节点N3、第四节点N4、使能信号端EM，控制电路5可以用于响应所述使能信号端EM的信号将所述第二电源端VDD的信号传输到所述第二节点N2，以及用于响应所述使能信号端EM的信号以连通所述第三节点N3和所述第四节点N4；耦合电路6可以连接于所述第一节点N1和所述第二电源端VDD之间。应该理解的是，在其他示例性实施例中，控制电路5还可以用于响应所述使 能信号端EM的信号将所述第二电源端VDD的信号传输到所述第三节点N3，以及用于响应所述使能信号端EM的信号以连通所述第二节点N2和所述第四节点N4。
本示例性实施例中，如图11所示，所述像素驱动电路还可以包括：第一复位电路2，第一复位电路2可以连接所述第一节点N1、第一初始信号端Vinit1、第一复位信号端Re1，第一复位电路2可以用于响应所述第一复位信号端Re1的信号将所述第一初始信号端Vinit1的信号传输到所述第一节点N1。
本示例性实施例中，如图11所示，所述第四节点N4可以用于连接一发光单元OLED，所述像素驱动电路还可以包括：第三复位电路4，第三复位电路4连接所述第四节点N4、第二初始信号端Vinit2、第三复位信号端Re3，第三复位电路4可以用于响应所述第三复位信号端Re3的信号将所述第二初始信号端Vinit2的信号传输到所述第四节点N4。发光单元OLED的另一端可以连接第三电源端VSS，发光单元OLED可以为发光二极管。向第四节点N4写入初始信号可以消除发光二极管内部发光界面上没有复合的载流子，缓解发光二极管的老化。
本示例性实施例中，如图11所示，所述耦合电路6可以包括：第三电容C3，第三电容C3连接于所述第一节点N1和所述第二电源端VDD之间；其中，所述第三电容C3的电容值可以大于所述第一电容C1的电容值，且所述第三电容C3的电容值可以大于所述第二电容C2的电容值。将第三电容C3设置为较大的电容值可以增加第三电容C3的存储电荷能力，从而可以增加发光阶段的最大持续时长。所述控制电路5可以包括：第五晶体管T5、第六晶体管T6，第五晶体管T5的栅极连接所述使能信号端EM，第一极连接所述第二电源端VDD，第二极连接所述第二节点N2；第六晶体管T6的栅极连接所述使能信号端EM，第一极连接所述第三节点N3，第二极连接所述第四节点N4。所述第一复位电路2可以包括：第一晶体管T1，第一晶体管T1的栅极连接所述第一复位信号端Re1，第一极连接所述第一初始信号端Vinit1，第二极连接所述第一节点N1；所述第三复位电路4可以包括：第七晶体管T7，第七晶体管T7的栅极连接所述第三复位信号端Re3，第一极连接所述 第二初始信号端Vinit2，第二极连接所述第四节点N4。其中，第一晶体管T1、第二晶体管T2可以为N型晶体管，该N型晶体管的半导体材料可以为氧化铟镓锌，氧化物晶体管具有较小的关断漏电流，从而可以降低发光阶段第一节点N1通过第一晶体管T1、第二晶体管T2的漏电流。第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以P型晶体管，例如，第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，低温多晶体硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。
如图12所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。所述像素驱动电路还可以包括：第二复位电路3，第二复位电路3可以连接所述第二节点N2、第一电源端VGH，第二复位电路3可以用于响应一控制信号将所述第一电源端VGH的信号传输到所述第二节点N2。本示例性实施例中，第一复位电路的导通电平和第三复位电路的导通电平可以极性相反，第一复位信号端Re1的信号和第三复位信号端Re3的极性可以相反，所述第二复位电路3的导通电平与所述第一复位电路2的导通电平可以极性相反；所述第二复位电路3还可以连接所述第三复位信号端Re3，所述第二复位电路3可以用于响应所述第三复位信号端Re3的信号将所述第一电源端VGH的信号传输到所述第二节点N2。
本示例性实施例中，像素驱动电路中驱动晶体管的栅极和源极之间存在寄生电容，像素驱动电路在复位阶段，驱动晶体管的栅极电压被初始化到初始电压，在上述寄生电容耦合作用下，驱动晶体管的源极电压也相应发生变化。在复位阶段对不同灰阶复位时，驱动晶体管栅极电压的变化量不同，从而驱动晶体管源极电压的变化量也不同，进而导致复位阶段完成后驱动晶体管Vgs(栅极源极电压差)不同。同时由于驱动晶体管的Vgs会影响其阈值电压，从而显示面板会发生残像问题。例如，当显示面板从黑白画面转变为同一灰阶画面时，由于黑白画面对应像素点中驱动晶体管的阈值电压不同，从而导致转变为同一灰阶画面后，上一帧黑白画面所在区域会分别显示不同的灰度，即出现残像问题。本示例性实施例中，像素驱动电路可以在复位阶段，利用第一复位电路2将所述第一初始信号端Vinit1的信号传输到所述第 一节点N1，同时，利用第二复位电路3将所述第一电源端VGH的信号传输到所述第二节点N2，从而使得在不同数据信号下，该像素驱动电路均可以将驱动晶体管的栅源电压差复位到同一值，从而改善了显示面板残像的问题。
本示例性实施例中，所述第二复位电路3可以包括：第八晶体管T8，第八晶体管T8的栅极连接所述第三复位信号端Re3，第一极连接所述第一电源端VGH，第二极连接所述第二节点N2；其中，第八晶体管T8可以为P型晶体管。应该理解的是，在其他示例性实施例中，第二复位电路的导通电平可以和第一复位电路的导通电平极性相同，第二复位电路可以连接第一复位信号端，第二复位电路可以用于响应第一复位信号端的信号将第一电源端VGH的信号传输到第二节点。相应的，第八晶体管可以为N型晶体管，该N型晶体管的半导体材料可以为氧化铟镓锌。所述第一电源端VGH还可以共用所述第二电源端VDD，例如，第二复位电路可以连接第二电源端VDD。
如图13所示，为图12中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端的时序，G2表示第二栅极驱动信号端的时序，Re1表示第一复位信号端的时序，Re3表示第三复位信号端的时序，EM表示使能信号端的时序。该像素驱动电路驱动方法可以包括四个阶段：复位阶段t1、阈值补偿阶段t2、缓冲阶段t3、发光阶段t4。其中，在复位阶段t1：使能信号端EM、第一复位信号端Re1、第一栅极驱动信号端输出高电平信号，第二栅极驱动信号端G2、第三复位信号端Re3输出低电平信号，第一晶体管T1、第七晶体管T7、第八晶体管T8导通，第一初始信号端Vinit1向第一节点N1输入第一初始信号，第一电源端VDD向第二节点N2输入电源信号，第二初始信号端Vinit2向第四节点输入第二初始信号，其中，第一初始信号和第二初始信号的电压可以相同或不同。在阈值补偿阶段t2：使能信号端EM、第二栅极驱动信号端G2、第三复位信号端输出高电平信号，第一复位信号端Re1输出低电平信号，阈值补偿阶段t2的至少部分时段第一栅极驱动信号端G1输出低电平信号，第二晶体管T2、第四晶体管T4导通，数据信号端Vdata向第一节点N1写入补偿电压Vdata+Vth，其中，Vdata为数据信号端的电压，Vth为驱动晶体管的阈值电压。在缓冲阶段t3：使能信号端EM、第三复位信号端Re3、第一栅极驱动信号端G1输出高电平信号， 第二栅极驱动信号端G2、第一复位信号端Re1输出低电平信号，所有晶体管均关断。在发光阶段t4：第三复位信号端Re3、第一栅极驱动信号端G1输出高电平信号，使能信号端EM、第二栅极驱动信号端G2、第一复位信号端Re1输出低电平信号，第五晶体管T5、第六晶体管T6导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。本示例性实施例中，在阈值补偿阶段t2，第一栅极驱动信号端G1的有效电平(低电平)时长可以小于第二栅极驱动信号端G2的有效电平(高电平)时长，在该阈值补偿阶段t2，第一栅极驱动信号端G1可以扫描一行像素驱动电路，第二栅极驱动信号端G2可以逐行扫描多行像素驱动电路，例如，第二栅极驱动信号端G2可以逐行扫描两行像素驱动电路。应该理解的是，在其他示例性实施例中，该驱动方法还可以不包括缓冲阶段；第一晶体管T1和第七晶体管T7还可以在不同阶段导通。第一栅极驱动信号端G1的有效电平(低电平)时长还可以等于第二栅极驱动信号端G2的有效电平(高电平)时长。
如图14所示，为本公开像素驱动电路另一种示例性实施例的结构示意图，该像素驱动电路还可以包括第四电容C4，第四电容C4第一电极可以连接于第二节点N2上，该像素驱动电路在发光阶段，第二电源端VDD可以向第四电容C4充电，在复位阶段起始时刻，第四电容C4可以维持第二节点N2的高电平，从而该设置可以加快复位阶段第一电源端VGH向第二节点N2写入高电平信号的速度。第四电容C4的第二电极可以连接第五节点N5，当第五节点N5的等电位导电部在阈值补偿阶段前或起始阶段有下拉动作时，第五节点N5会对第二节点N2有下拉作用，从而导致显示面板不同位置上的第二节点N2电压存在差异。例如，第五节点N5的等电位导电部可以为用于提供第一栅极驱动信号端G1的第一栅线，第一栅线可以与第二节点N2的等电位导电部部分重合，从而第一栅线的部分结构可以用于形成第四电容C4的第二电极，第一栅线在阈值补偿阶段的起始阶段从高电平变为低电平，从而第一栅线会拉低第二节点N2的电压。本示例性实施例可以尽量减小第二节点N2的等电位导电部和第一栅线的交叠面积，以降低第一栅线对第二节点N2的下拉作用。其中，第四电容C4的电容值C4可以小于第二电容C2的电容值，第四电容C4可以为0.5fF-4fF，例如，0.5fF、2fF、4fF。第四电容C4的 电容值C4还可以小于第一电容C1电容值的一半，例如，第四电容C4的电容值C4可以为第一电容C1电容值的1/3、1/4、1/5等。
本示例性实施例中，如图12、14所示，该像素驱动电路需要在阈值补偿阶段导通驱动晶体管T3，因此，第一初始信号端Vinit1与第一电源端VGH的电压差Vinit1-Vgh需要小于驱动晶体管T3的阈值电压Vth，其中，Vinit1为第一初始信号端的电压，Vgh为第一电源端VGH的电压。其中，Vinit1可以为-2～-6V，例如，-2V、-3V、-4V、-5V、-6V等。Vinit1-Vgh可以小于a*Vth，a可以为2～7，例如，a可以为2、4、6、7；Vth可以为-2～-5V，例如-2V、-3V、-5V等。Vgh可以大于1.5倍的Vth，例如，Vgh可以为Vth的1.6倍、1.8倍、2倍等。
如图15所示，为本公开显示面板一种示例性实施例中像素驱动电路的分布图。相邻两列像素电路可以与同一列向延伸的第一电源线VGH连接，该第一电源线VGH用于向像素驱动电路提供第一电源端，且该第一电源线VGH可以位于上述相邻两列像素驱动电路之间。如图15所示，在同一像素行中，相邻列的两个像素电路可以镜像设置，以方便布线。
如图16所示，为本公开显示面板另一种示例性实施例中像素驱动电路的分布图。相邻两行像素电路可以与同一行向延伸的第一电源线VGH连接，该第一电源线VGH用于向像素驱动电路提供第一电源端，且该第一电源线VGH可以位于上述相邻两行像素驱动电路之间。如图16所示，在同一像素行中，相邻列的两个像素电路可以镜像设置，以方便布线。
如图17所示，为本公开显示面板另一种示例性实施例中像素驱动电路的分布图。该显示面板可以包括多个阵列分布的像素驱动电路P，多条第一电源线VGH11、VGH12、VGH21、VGH22，第一电源线VGH11、VGH12、VGH21、VGH22均可以用于提供第一电源端。如图17所示，第一电源线VGH11、VGH12沿列方向延伸，第一电源线VGH21、VGH22沿行方向延伸，相邻两行像素电路可以与同一行向延伸的第一电源线连接，该第一电源线VGH可以位于上述相邻两行像素驱动电路之间，沿列方向延伸的第一电源线可以连接与其相交的多条沿行方向延伸的第一电源线相交，从而多条电源线 可以形成网格结构。其中，沿列方向延伸的第一电源线可以位于红色像素驱动电路所在的区域内。此外，在同一像素行中，相邻列的两个像素电路可以镜像设置，以方便布线。
本示例性实施例还提供一种像素驱动电路驱动方法，用于驱动上述的像素驱动电路，其中，包括：
在复位阶段，向所述使能信号端EM、第一复位信号端Re1、第一栅极驱动信号端G1输入高电平信号，向所述第二栅极驱动信号端G2、第三复位信号端Re3输入低电平信号；
在阈值补偿阶段：向所述使能信号端EM、第二栅极驱动信号端G2、第三复位信号端Re3输入高电平信号，向所述第一复位信号端Re1、第一栅极驱动信号端G1输入低电平信号；
在发光阶段：向所述第三复位信号端Re3、第一栅极驱动信号端G1输入高电平信号，向所述使能信号端EM、第二栅极驱动信号端G2、第一复位信号端Re1输入低电平信号。
该驱动方法在上述内容中已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种显示面板，其中，所述显示面板可以包括上述的像素驱动电路。该显示面板可以应用于手机、平板电脑、电视等显示装置。该显示面板中的像素驱动电路可以如图10所示，其中，该显示面板可以包括依次层叠设置的衬底基板、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层，其中，上述层级结构之间还可以设置有绝缘层。如图18-25所示，图18为本公开显示面板一种示例性实施例的部分结构版图，图19为图18中第一导电层的结构版图，图20为图18中第二导电层的结构版图，图21为图18中第二有源层的结构版图，图22为图18中第三导电层的结构版图，图23为图18中第四导电层的结构版图，图24为图18中第一导电层、第二导电层、第二有源层的结构版图，图25为图18中第一导电层、第二导电层、第二有源层、第三导电层的结构版图。
如图18、19、24所示，第一导电层可以包括第一导电部11和所述第一栅线G1，所述第一导电部11可以用于形成所述驱动晶体管T3的栅极，所 述第一栅线G1在所述衬底基板上的正投影可以沿第一方向X延伸，第一栅线G1可以连接第四晶体管T4的栅极，例如，第一栅线G1的部分结构可以用于形成第四晶体管的栅极。
如图18、20、24所示，所述第二导电层可以包括所述第二栅线2G2，所述第二栅线2G2在所述衬底基板上的正投影可以沿所述第一方向X延伸，第二栅线2G2可以连接第二晶体管的栅极，例如，第二栅线2G2的部分结构可以用于形成第二晶体管的底栅。
如图18、21、24所示，所述第二有源层可以包括第一有源部71、第二有源部72、第三有源部73，所述第二有源部72连接于所述第一有源部71和所述第三有源部73之间，所述第一有源部71可以用于形成所述第二晶体管T2的沟道区，所述第二栅线2G2在所述衬底基板上的正投影可以覆盖所述第一有源部71在所述衬底基板上的正投影。第二有源层的材料可以为氧化铟镓锌。
如图18、22、25所示，所述第三导电层可以包括所述第三栅线3G2，所述第三栅线3G2在所述衬底基板上的正投影可以沿所述第一方向X延伸，所述第三栅线3G2在所述衬底基板的正投影可以覆盖所述第一有源部71在所述衬底基板上的正投影，第三栅线3G2的部分结构可以用于形成第二晶体管的顶栅。该显示面板可以以第三导电部为掩膜版对第二有源层进行导体化处理，即第二有源层被第三导电层覆盖的区域形成晶体管的沟道区，第二有源层未被第三导电层覆盖的区域形成导体结构。
如图18、23所示，所述第四导电层可以包括连接部41，所述连接部41可以通过过孔H1连接所述第一导电部11，通过过孔H2连接所述第三有源部73。
如图26所示，为图18中沿虚线A的部分剖视图，该显示面板还可以包括第一绝缘层92、第二绝缘层93、第三绝缘层94、介电层95，其中，衬底基板91、第一导电层、第一绝缘层92、第二导电层、第二绝缘层93、第二有源层、第三绝缘层94、第三导电层、介电层95、第四导电层依次层叠设置。第一绝缘层92、第二绝缘层93、第三绝缘层94可以包括氧化硅层。介电层 95可以包括氮化硅层。第四导电层的材料可以包括金属材料，例如可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。第一导电层、第二导电层、第三导电层的材料可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等。
如图18-26所示，所述第一栅线G1可以包括第一延伸部G11，所述第一延伸部G11在所述衬底基板上的正投影可以与所述第三有源部73在所述衬底基板上的正投影重合，所述第一延伸部G11可以用于形成所述第一电容C1的第一电极，所述第三有源部73可以用于形成所述第一电容C1的第二电极。所述第二栅线2G2可以包括第二延伸部2G22，所述第二延伸部2G22在所述衬底基板上的正投影可以与所述第二有源部72在所述衬底基板上的正投影重合，且所述第三栅线3G2在所述衬底基板上的正投影位于所述第二有源部72在所述衬底基板上的正投影的一侧，即第三栅线3G2在所述衬底基板上的正投影与第二有源部72在所述衬底基板上的正投影不交叠，例如，如图18所示，所述第三栅线3G2在所述衬底基板上的正投影可以位于所述第二有源部72在所述衬底基板上的正投影在第二方向Y上的一侧，第二方向Y可以与第一方向X相交，例如，第二方向Y可以与第一方向X垂直。所述第二延伸部2G22可以用于形成第二电容C2的部分第一电极，所述第二有源部72可以用于形成所述第二电容C2的部分第二电极；所述第三栅线3G2可以包括第三延伸部3G23，所述连接部41可以包括第四延伸部414，所述第三延伸部3G23在所述衬底基板上的正投影可以与所述第四延伸部414在所述衬底基板上的正投影重合，所述第三延伸部3G23可以用于形成所述第二电容C2的部分第一电极，所述第四延伸部414可以用于形成所述第二电容C2的部分第二电极。所述第三有源部73在所述衬底基板上的正投影在所述第一方向X上的尺寸可以大于所述第二有源部72在所述衬底基板上的正投影在所述第一方向X上的尺寸，该设置可以增加第一电容C1的电容值，其中，本示例性实施例可以通过调节第三有源部73在衬底基板上的正投影在所述第一方向X上的尺寸调节第一电容的电容值，第三有源部73在衬底基板上的正投影在所述第一方向X上的尺寸可以为5um-20um，例如，5um、9.7um、12um、15.55um、50um。此外，本示例性实施例还可以通过调节第 一绝缘层92、第二绝缘层93位于第三有源部73处的厚度调节第一电容C1的电容值，例如，本示例性实施例可以减薄位于第三有源部73处的第一绝缘层92和/或第二绝缘层93的厚度以增加第一电容C1的电容值。本示例性实施例还可以通过调节第四延伸部414在衬底基板上的正投影在第一方向X上的尺寸调节第二电容的电容值，第四延伸部414在衬底基板上的正投影在第一方向X上的尺寸越小，第二电容的电容值越小，第四延伸部414在衬底基板上的正投影在第一方向上的尺寸可以为2um-4um，例如，4um、3.7um、3.5um、2.95um、2.2um、2um。此外，本示例性实施例还可以通过调节第第二延伸部2G22在衬底基板上的正投影在第二方向Y上的尺寸调节第二电容的电容值，第二延伸部2G22在衬底基板上的正投影在第二方向Y上的尺寸越小，第二电容的电容值越小。
需要说明的是，如图18、26所示，在第四延伸部414所处的区域内，第三栅线3G2在衬底基板正投影覆盖第二栅线2G2在衬底基板正投影，虽然，该区域内的第二栅线2G2在衬底基板上的正投影与第四延伸部414在衬底基板上的正投影交叠，但是由于第三栅线3G2的屏蔽作用，该区域内第二栅线2G2在衬底基板上正投影的面积变化并不会影响第二电容的电容值。同理，在第一延伸部G11所处的区域内，第三有源部73在衬底基板上的正投影覆盖连接部41在衬底基板上的正投影，虽然，该区域内的连接部41在衬底基板上的正投影与第一延伸部G11在衬底基板上的正投影交叠，但是由于第三有源部73的屏蔽作用，该区域内连接部41在衬底基板上正投影的面积变化并不会影响第一电容的电容值。
如图27-45所示，为本公开像素驱动电路另一组示例性实施例的说明附图。
在本公开实施例中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
本领域技术人员可以理解，本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
图27和图28为本公开示例性实施例的两种像素电路的结构示意图，如图27和图28所示，本公开实施例提供的像素电路包括：驱动子电路、第一复位子电路、第二复位子电路和发光元件。
其中，驱动子电路分别与第一节点N1、第二节点N2和第三节点N3连接，被配置为响应于第一节点N1的控制信号，在第二节点N2和第三节点N3之间产生驱动电流；
第一复位子电路分别与第一复位信号线INIT1和发光元件的阳极端连接，还与第一发光控制信号线EM1或者第二复位控制信号线Reset2连接，被配置为响应于第一发光控制信号线EM1或者第二复位控制信号线Reset2的信号，向发光元件的阳极端写入第一复位信号线INIT1提供的第一复位信号；
第二复位子电路分别与第一复位控制信号线Reset1和第二复位信号线INIT2连接，还与第二节点N2或第三节点N3连接，被配置为响应于第一复位控制信号线Reset1的信号，向驱动子电路的第一极或第二极写入第二复位信号线INIT2提供的第二复位信号；第二复位信号大于第一复位信号。
在一些示例性实施方式中，第二复位信号的绝对值大于驱动子电路的阈值电压的1.5倍。
在一些示例性实施方式中，第二复位信号的幅值大于0。
示例性的，第二复位信号一般为4～10V的复位电压，第一复位信号一般为-2V～-6V的复位电压，驱动子电路的阈值电压一般为-5V～-2V，可选地，驱动子电路的阈值电压可以为-3V。
在一些示例性实施方式中，如图27和图28所示，所述像素电路还包括写入子电路、补偿子电路、第一发光控制子电路和第二发光控制子电路。
其中，写入子电路分别与第二扫描信号线G2、数据信号线Data和第二节点N2连接，被配置为响应于第二扫描信号线G2的信号，向第二节点N2写入数据信号线Data的数据信号。
补偿子电路分别与第一电源线VDD、第一扫描信号线G1、第一节点N1和第三节点N3连接，被配置为响应于第一扫描信号线G1的信号，将第三节点N3的第一复位信号或第二复位信号写入第一节点N1；还被配置为响应于第一扫描信号线G1的信号，对第一节点N1进行补偿。
第一发光控制子电路分别与第一发光控制信号线EM1、第一电源线VDD和第二节点N2连接，被配置为响应于第一发光控制信号线EM1的信号，向第二节点N2提供第一电源线VDD的信号。
第二发光控制子电路分别与第二发光控制信号线EM2、第三节点N3和第四节点N4连接，被配置为响应于第二发光控制信号线EM2的信号，将第四节点N4的第一复位信号写入第三节点N3；还被配置为响应于第二发光控制信号线EM2的信号，在第三节点N3和第四节点N4之间允许驱动电流通过。
在一些示例性实施方式中，当第二复位子电路向第二节点N2写入第二复位信号时，驱动子电路还被配置为响应于第一节点N1的控制信号，将第二节点N2的第二复位信号写入第三节点N3。
在一些示例性实施方式中，如图27和图28所示，发光元件的一端与第四节点N4连接，发光元件的另一端与第二电源线VSS连接。
在一些示例性实施方式中，如图29所示，第一复位子电路包括第一晶体管T1。
其中，第一晶体管T1的控制极与第一发光控制信号线EM1或第二复位控制信号线Reset2(图中未示出)连接，第一晶体管T1的第一极与第一复位信号线INIT1连接，第一晶体管T1的第二极与第四节点N4连接。
图29中示出了第一复位子电路的一种示例性结构。本领域技术人员容易理解的是，第一复位子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施方式中，如图30所示，补偿子电路包括第二晶体管T2和第一电容C1。
其中，第二晶体管T2的控制极与所述第一扫描信号线G1连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第一节点N1连接。
第一电容C1的一端与第一节点N1连接，第一电容C1的另一端与第一电源线VDD连接。
图30中示出了补偿子电路的一种示例性结构。本领域技术人员容易理解的是，补偿子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施方式中，如图31所示，驱动子电路包括第三晶体管T3。
其中，第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。
图31中示出了驱动子电路的一种示例性结构。本领域技术人员容易理解的是，驱动子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施方式中，如图32所示，写入子电路包括第四晶体管T4。
其中，第四晶体管T4的控制极与第二扫描信号线G2连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。
图32中示出了写入子电路的一种示例性结构。本领域技术人员容易理解的是，写入子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施方式中，如图33所示，第一发光控制子电路包括第五晶体管T5。
其中，第五晶体管T5的控制极与第一发光控制信号线EM1连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。
图33中示出了第一发光控制子电路的一种示例性结构。本领域技术人员容易理解的是，第一发光控制子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施方式中，如图34所示，第二发光控制子电路包括第六晶体管T6。
其中，第六晶体管T6的控制极与第二发光控制信号线EM2连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。
图34中示出了第二发光控制子电路的一种示例性结构。本领域技术人员容易理解的是，第二发光控制子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施方式中，如图35所示，第二复位子电路包括第七晶体管T7。
其中，第七晶体管T7的控制极与复位控制信号线Reset连接，第七晶体管T7的第一极与第二复位信号线INIT2连接，第七晶体管T7的第二极与第二节点N2连接。
在一些示例性实施方式中，如图36所示，第二复位子电路包括第七晶体管T7。
其中，第七晶体管T7的控制极与复位控制信号线Reset连接，第七晶体管T7的第一极与第二复位信号线INIT2连接，第七晶体管T7的第二极与第三节点N3连接。
图35和图36中示出了第二复位子电路的两种示例性结构。本领域技术 人员容易理解的是，第二复位子电路的实现方式不限于此，只要能够实现其功能即可。
在一些示例性实施方式中，如图37a或图37b所示，第一复位子电路包括第一晶体管T1，补偿子电路包括第二晶体管T2和第一电容C1，驱动子电路包括第三晶体管T3，写入子电路包括第四晶体管T4，第一发光控制子电路包括第五晶体管T5，第二发光控制子电路包括第六晶体管T6，第二复位子电路包括第七晶体管T7。
其中，第一晶体管T1的控制极与第一发光控制信号线EM1连接，第一晶体管T1的第一极与第一复位信号线INIT1连接，第一晶体管T1的第二极与第四节点N4连接。
第二晶体管T2的控制极与第一扫描信号线G1连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第一节点N1连接。
第一电容C1的一端与第一节点N1连接，第一电容C1的另一端与第一电源线VDD连接。
第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。
第四晶体管T4的控制极与第二扫描信号线G2连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。
第五晶体管T5的控制极与第一发光控制信号线EM1连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。
第六晶体管T6的控制极与第二发光控制信号线EM2连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。
第七晶体管T7的控制极与第一复位控制信号线Reset1连接，第七晶体管T7的第一极与第二复位信号线INIT2连接，第七晶体管T7的第二极与第 二节点N2或第三节点N3连接。
图37a和图37b示出了第一复位子电路、补偿子电路、驱动子电路、写入子电路、第一发光控制子电路、第二发光控制子电路、第二复位子电路的两种示例性结构。本领域技术人员容易理解的是，以上各子电路的实现方式不限于此，只要能够实现其各自的功能即可。由于本公开像素电路中晶体管数量较少，因此，像素电路的占用空间较少，由此提高了显示装置的像素分辨率。
在一些示例性实施方式中，第二复位信号线INIT2可以与以下至少之一为同一电压线：第一电源线VDD、第一发光控制信号线EM1、第二发光控制信号线EM2或者第三电源线，第三电源线提供第三电源电压，第三电源电压大于第一复位信号线INIT1提供的第一复位电压。
在一些示例性实施方式中，复位控制信号线Reset的信号的脉冲宽度与第二扫描信号线G2的信号的脉冲宽度大致相同。
在一些示例性实施方式中，第一发光控制信号线EM1的信号脉冲与第二发光控制信号线EM2的信号脉冲相差一个或两个时间单元h，一个时间单元h为一行子像素扫描的时间。
在一些示例性实施方式中，如图38a或图38b所示，第一复位子电路包括第一晶体管T1，补偿子电路包括第二晶体管T2和第一电容C1，驱动子电路包括第三晶体管T3，写入子电路包括第四晶体管T4，第一发光控制子电路包括第五晶体管T5，第二发光控制子电路包括第六晶体管T6，第二复位子电路包括第七晶体管T7。
其中，第一晶体管T1的控制极与第二复位控制信号线Reset2连接，第一晶体管T1的第一极与第一复位信号线INIT1连接，第一晶体管T1的第二极与第四节点N4连接。
第二晶体管T2的控制极与第一扫描信号线G1连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第一节点N1连接。
第一电容C1的一端与第一节点N1连接，第一电容C1的另一端与第一电源线VDD连接。
第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。
第四晶体管T4的控制极与第二扫描信号线G2连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。
第五晶体管T5的控制极与第一发光控制信号线EM1连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。
第六晶体管T6的控制极与第二发光控制信号线EM2连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。
第七晶体管T7的控制极与第一复位控制信号线Reset1连接，第七晶体管T7的第一极与第二复位信号线INIT2连接，第七晶体管T7的第二极与第二节点N2或第三节点N3连接。
图38a和图38b示出了第一复位子电路、补偿子电路、驱动子电路、写入子电路、第一发光控制子电路、第二发光控制子电路、第二复位子电路的另两种示例性结构。本领域技术人员容易理解的是，以上各子电路的实现方式不限于此，只要能够实现其各自的功能即可。
在一些示例性实施方式中，发光元件EL可以为有机发光二极管(Organic Light Emitting Diode，OLED)，也可以为次毫米发光二极管(Mini Light Emitting Diodes)、微发光二极管(Micro Light Emitting Diodes)、量子点发光二极管(Quantum-dot Light Emitting Diodes，QLED)等其他类型的发光二极管。在实际应用中，发光元件EL的结构需要根据实际应用环境来设计确定，在此不作限定。以下均以发光元件EL为有机发光二极管为例进行说明。
在一些示例性实施方式中，第一晶体管T1、第二晶体管T2和第七晶体管T7中的至少一个为第一类型晶体管，第一类型晶体管包括N型晶体管或P型晶体管，第三晶体管T3至第六晶体管T6均为第二类型晶体管，第二类型晶体管包括P型晶体管或N型晶体管，且第二类型晶体管与第一类型晶体 管的晶体管类型不同，即当第一类型晶体管为N型晶体管时，第二类型晶体管为P型晶体管，当第一类型晶体管为P型晶体管时，第二类型晶体管为N型晶体管。
在一些示例性实施方式中，如图37a和图37b所示，第一晶体管T1和第二晶体管T2均为N型薄膜晶体管，第三晶体管T3至第七晶体管T7均为P型薄膜晶体管。
在一些示例性实施方式中，第一晶体管T1、第二晶体管T2和第七晶体管T7均为N型薄膜晶体管，第三晶体管T3至第六晶体管T6均为P型薄膜晶体管。
在一些示例性实施方式中，如图38a和图38b所示，第二晶体管T2为N型薄膜晶体管，第一晶体管T1以及第三晶体管T3至第七晶体管T7均为P型薄膜晶体管。
在一些示例性实施方式中，N型薄膜晶体管可以是低温多晶硅(Low Temperature Poly Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)，P型薄膜晶体管可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)薄膜晶体管；或者，N型薄膜晶体管可以是IGZO薄膜晶体管，P型薄膜晶体管可以为LTPS薄膜晶体管。
在一些示例性实施方式中，第一晶体管T1和第二晶体管T2均为IGZO薄膜晶体管，第三晶体管T3至第七晶体管T7均为LTPS薄膜晶体管。
本实施例中，铟镓锌氧化物薄膜晶体管与低温多晶硅薄膜晶体管相比，产生的漏电流更少，因此，将第一晶体管T1和第二晶体管T2设置为铟镓锌氧化物薄膜晶体管，可以显著减少发光阶段驱动晶体管控制极的漏电，从而改善显示面板的低频、低亮度闪烁的问题。
在一些示例性实施方式中，第一晶体管T1、第二晶体管T2和第七晶体管T7均为IGZO薄膜晶体管，第三晶体管T3至第六晶体管T6均为LTPS薄膜晶体管。
在一些示例性实施方式中，第二晶体管T2为IGZO薄膜晶体管，第一晶体管T1以及第三晶体管T3至第七晶体管T7均为LTPS薄膜晶体管。在一 些示例性实施方式中，第一电容C1可以是由像素电极与公共电极构成的液晶电容，也可以是由像素电极与公共电极构成的液晶电容以及存储电容构成的等效电容，本公开对此不作限定。
图39为图37a或图37b所示像素电路在一个扫描周期内的工作时序图。下面以本公开实施例提供的像素电路中第一晶体管T1和第二晶体管T2为N型晶体管、第三晶体管T3至第七晶体管T7均为P型晶体管为例，结合图11a所示的像素电路和图39所示的工作时序图，对一个像素电路在一帧周期内的工作过程进行描述。如图37a所示，本公开实施例提供的像素电路包括7个晶体管单元(T1～T7)、1个电容单元(C1)和3个电压线(VDD、VSS、INIT1，由于第二复位信号线INIT2可以与第一电源线VDD、第一发光控制信号线EM1和第二发光控制信号线EM2中的任一个为同一电压线，所以，第二复位信号线INIT2未计算在上述3个电压线内)，其中，第一电源线VDD持续提供高电平信号，第二电源线VSS持续提供低电平信号，第一复位信号线INIT1提供第一复位电压(初始电压信号)。如图39所示，其工作过程包括：
第一阶段t1，即复位阶段，第一扫描信号线G1、第二扫描信号线G2、第一复位控制信号线Reset1和第一发光控制信号线EM1为高电平，第二发光控制信号线EM2为低电平。第一发光控制信号线EM1为高电平，使第一晶体管T1导通，将第四节点N4(即发光元件EL的阳极端)复位为第一复位信号线INIT1的第一复位电压。第二发光控制信号线EM2为低电平，使第六晶体管T6导通；第一扫描信号线G1为高电平，使第二晶体管T2导通，将第一节点N1(即第三晶体管T3的栅极及第一电容C1的一端)以及第三节点N3复位为第一复位信号线INIT1的第一复位电压。本阶段，第四晶体管T4、第五晶体管T5和第七晶体管T7保持关闭，如图41所示。
第二阶段t2，即重置阶段，第一扫描信号线G1、第二扫描信号线G2、第一发光控制信号线EM1和第二发光控制信号线EM2为高电平，第一复位控制信号线Reset为低电平。第二发光控制信号线EM2为高电平，使第六晶体管T6关闭。第一复位控制信号线Reset1为低电平，使第七晶体管T7导通(本时序是以第七晶体管T7为P型薄膜晶体管为例进行说明，当第七晶体 管T7为N型薄膜晶体管时，第一复位控制信号线Reset1在第二阶段t2提供高电平信号，在其他阶段提供低电平信号)，将第二节点N2复位为第二复位电压，其中，第二复位电压可以为第一电源线VDD、第一发光控制信号线EM1、第二发光控制信号线EM2或者第三电源线提供的电压信号，第二复位电压大于第一复位电压，由于第一节点N1为第一复位信号线INIT1的第一复位电压，第三晶体管T3导通，第一扫描信号线G1为高电平，第二晶体管T2导通，第二节点N2的电压通过第三晶体管T3和第二晶体管T2，传递至第一节点N1。本阶段，第四晶体管T4、第五晶体管T5和第六晶体管T6保持关闭，如图42所示。
第三阶段t3，即数据写入阶段，第一扫描信号线G1、第一复位控制信号线Reset1、第一发光控制信号线EM1和第二发光控制信号线EM2为高电平，第二扫描信号线G2为低电平。此时第二扫描信号线G2为低电平，使第四晶体管T4导通，数据信号线Data输出的数据电压信号Vdata通过导通的第四晶体管T4、第三晶体管T3和第二晶体管T2提供至第一节点N1，并将数据信号线Data输出的数据电压信号Vdata与第三晶体管T3的阈值电压Vth之和储存在第一电容C1上。本阶段，第五晶体管T5、第六晶体管T6和第七晶体管T7保持关闭，如图43所示。
第四阶段t4，即发光阶段，第二扫描信号线G2和第一复位控制信号线Reset1为高电平，第一扫描信号线G1、第一发光控制信号线EM1和第二发光控制信号线EM2为低电平。第一发光控制信号线EM1为低电平，使第五晶体管T5导通、第一晶体管T1关闭，第二发光控制信号线EM2为低电平，使第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向第四节点N4(即发光元件EL的阳极端)提供驱动电压，驱动发光元件EL发光。本阶段，第一晶体管T1、第二晶体管T2、第四晶体管T4和第七晶体管T7保持关闭，如图44所示。
图40为图38a或图38b所示像素电路在一个扫描周期内的工作时序图。下面以本公开实施例提供的像素电路中第二晶体管T2为N型晶体管、第一晶体管T1以及第三晶体管T3至第七晶体管T7均为P型晶体管为例，结合图38a所示的像素电路和图40所示的工作时序图，对一个像素电路在一帧周 期内的工作过程进行描述。如图38a所示，本公开实施例提供的像素电路包括7个晶体管单元(T1～T7)、1个电容单元(C1)和3个电压线(VDD、VSS、INIT1，由于第二复位信号线INIT2可以与第一电源线VDD、第一发光控制信号线EM1和第二发光控制信号线EM2中的任一个为同一电压线，所以，第二复位信号线INIT2未计算在上述3个电压线内)，其中，第一电源线VDD持续提供高电平信号，第二电源线VSS持续提供低电平信号，第一复位信号线INIT1提供第一复位电压(初始电压信号)。如图40所示，其工作过程包括：
第一阶段A1，即复位阶段，第一扫描信号线G1、第二扫描信号线G2、第一复位控制信号线Reset1和第一发光控制信号线EM1为高电平，第二复位控制信号线Reset2和第二发光控制信号线EM2为低电平。第一晶体管T1、第六晶体管T6和第二晶体管T2导通，将第四节点N4(即发光元件EL的阳极端)、第三节点N3以及第一节点N1(即第三晶体管T3的栅极及第一电容C1的一端)复位为第一复位信号线INIT1的第一复位电压。本阶段，第四晶体管T4、第五晶体管T5和第七晶体管T7保持关闭。
第二阶段A2，即重置阶段，第一扫描信号线G1、第二扫描信号线G2、第二复位控制信号线Reset2、第一发光控制信号线EM1和第二发光控制信号线EM2为高电平，第一复位控制信号线Reset1为低电平。第二发光控制信号线EM2为高电平，使第六晶体管T6关闭。第一复位控制信号线Reset1为低电平，使第七晶体管T7导通(本时序是以第七晶体管T7为P型薄膜晶体管为例进行说明，当第七晶体管T7为N型薄膜晶体管时，第一复位控制信号线Reset1在第二阶段A2提供高电平信号，在其他阶段提供低电平信号)，将第二节点N2复位为第二复位电压，其中，第二复位电压可以为第一电源线VDD、第一发光控制信号线EM1、第二发光控制信号线EM2或者第三电源线提供的电压信号，第二复位电压大于第一复位电压，由于第一节点N1为第一复位信号线INIT1的第一复位电压，第三晶体管T3导通，第一扫描信号线G1为高电平，第二晶体管T2导通，第二节点N2的电压通过第三晶体管T3和第二晶体管T2，传递至第一节点N1。本阶段，第四晶体管T4、第五晶体管T5和第六晶体管T6保持关闭。
第三阶段A3，即数据写入阶段，第一扫描信号线G1、第二复位控制信号线Reset2、第一复位控制信号线Reset1、第一发光控制信号线EM1和第二发光控制信号线EM2为高电平，第二扫描信号线G2为低电平。此时第二扫描信号线G2为低电平，使第四晶体管T4导通，数据信号线Data输出的数据电压信号Vdata通过导通的第四晶体管T4、第三晶体管T3和第二晶体管T2提供至第一节点N1，并将数据信号线Data输出的数据电压信号Vdata与第三晶体管T3的阈值电压Vth之和储存在第一电容C1上。本阶段，第五晶体管T5、第六晶体管T6和第七晶体管T7保持关闭。
第四阶段A4，即发光阶段，第二扫描信号线G2、第二复位控制信号线Reset2和第一复位控制信号线Reset1为高电平，第一扫描信号线G1、第一发光控制信号线EM1和第二发光控制信号线EM2为低电平。第一发光控制信号线EM1为低电平，使第五晶体管T5导通，第二复位控制信号线Reset2为高电平。使第一晶体管T1关闭，第二发光控制信号线EM2为低电平，使第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向第四节点N4(即发光元件EL的阳极端)提供驱动电压，驱动发光元件EL发光。本阶段，第一晶体管T1、第二晶体管T2、第四晶体管T4和第七晶体管T7保持关闭。
在像素电路驱动过程中，流过第三晶体管T3(即驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata+Vth，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdata+Vth-Vdd)-Vth]2＝K*[(Vdata-Vdd)]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线Data输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述公式可以看出，流经发光元件EL的电流I与第三晶体管T3的阈值电压Vth无关，消除了第三晶体管T3的阈值电压Vth对电流I的影响，保证了亮度的均一性。
由于LTPO((LTPS低温多晶硅晶体管+Oxide氧化物晶体管)像素电路的响应时间较长，导致在低频切换时，画面出现亮度闪烁。本公开实施例的像素电路，通过在驱动晶体管重置阶段，对第三晶体管T3(驱动晶体管)增加大的偏压改善迟滞，使得在高低频切换时能够保持画面亮度，降低闪屏(Flicker)风险。
在一列子像素中，对于至少相邻的两个子像素，上一行子像素中的第二发光控制信号线EM2与下一行子像素中的第一发光控制信号线EM1电连接，上一行子像素中的第二扫描信号线G2与下一行子像素中的第一复位控制信号线Reset1电连接。
本公开实施例还提供了一种像素电路的驱动方法，用于驱动如前所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，如图45所示，所述驱动方法包括步骤100至步骤400。
其中，步骤100包括：在复位阶段，第一复位子电路响应于第一发光控制信号线或者第二复位控制信号线的信号，向发光元件的阳极端(即第四节点)写入第一复位信号。
在一些示例性实施方式中，步骤100还包括：第二发光控制子电路响应于第二发光控制信号线的信号，将所述第四节点的第一复位信号写入第三节点；补偿子电路响应于第一扫描信号线的信号，将所述第三节点的第一复位信号写入第一节点。
步骤200包括：在重置阶段，第二复位子电路响应于第一复位控制信号线的信号，向驱动子电路的第一极(即第二节点)或第二极(即第三节点)写入第二复位信号；所述第二复位信号大于所述第一复位信号。
在一些示例性实施方式中，步骤100还包括：补偿子电路响应于第一扫描信号线的信号，将第三节点的第二复位信号写入第一节点。
在一些示例性实施方式中，第二复位信号可以为来源于以下至少之一的电压线的信号：第一电源线、第一发光控制信号线、第二发光控制信号线或者第三电源线。
步骤300包括：在发光阶段，驱动子电路响应于第一节点的控制信号， 向第二节点和第三节点之间产生驱动电流
在一些示例性实施方式中，在步骤300之前，该方法还包括：在数据写入阶段，写入子电路响应于所述第二扫描信号线的信号，向第二节点写入数据信号；补偿子电路响应于第一扫描信号线的信号，对第一节点进行补偿。
在一些示例性实施方式中，步骤300还包括：在发光阶段，第一发光控制子电路响应于所述第一发光控制信号线的信号，向所述第二节点提供所述第一电源线的信号；第二发光控制子电路响应于所述第二发光控制信号线的信号，在所述第三节点和第四节点之间允许驱动电流通过。
本公开实施例的像素电路及其驱动方法、显示装置，通过第二复位子电路响应于第一复位控制信号线的信号，向驱动子电路的第一极或第二极写入第二复位信号，对驱动子电路增加大的偏压改善迟滞，使得在高低频切换时能够保持画面亮度，降低闪屏风险，提高了显示装置在高低灰阶下的显示效果。此外，由于本公开像素电路中晶体管数量较少，因此，像素电路的占用空间较少，由此提高了显示装置的像素分辨率。
有以下几点需要说明：
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
如图46-60所示，为本公开像素驱动电路另一组示例性实施例的说明附图。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图46所示，本公开实施例所述的像素电路包括驱动电路11、第一控制电路12、补偿控制电路13和第一初始化电路14；
所述第一控制电路12分别与第一扫描线S1、所述驱动电路11的控制端和连接节点N0电连接，用于在所述第一扫描线S1提供的第一扫描信号的控制下，控制所述驱动电路11的控制端与所述连接节点N0之间连通；
所述补偿控制电路13分别与第二扫描线S2、所述连接节点N0和所述驱动电路11的第一端电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，控制所述连接节点N0与所述驱动电路11的第一端之间连通；
所述第一初始化电路14分别与初始化控制线R1、第一初始化电压线和所述连接节点N0电连接，用于在所述初始化控制线R1提供的初始化控制信号的控制下，将所述第一初始化电压线提供的第一初始化电压Vi1写入所述连接节点N0；
所述驱动电路11用于在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通。
在图46所示的至少一实施例中，第一节点N1为与驱动电路11的控制端连接的节点。
在本公开实施例所述的像素电路中，第一控制电路12与直接与第一节点N1电连接，第一初始化电路14和所述补偿控制电路13都不直接与第一节点N1电连接，以减少第一节点N1的漏电路径，以能够在低频工作时保证第一节点的电压的稳定性，利于提升显示质量，提升显示均一性，减轻Flicker(闪烁)。
本公开如图46所示的像素电路的实施例在工作时，显示周期包括初始化阶段和数据写入阶段；所述驱动方法包括：
在初始化阶段，第一控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与连接节点N0之间连通，第一初始化电路14在初始化控制信号的控制下，将第一初始化电压Vi1写入连接节点N0，从而将第一初始化电压Vi1写入所述驱动电路11的控制端，以使得在所述数据写入阶段开始时驱动电路11能够控制其第一端与所述驱动电路的第二端之间连通；
在数据写入阶段，第一控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与连接节点N0之间连通，补偿控制电路13在第二扫描信号的控制下，控制所述连接节点N0与所述驱动电路11的第一端之间连通，以使得所述驱动电路11的控制端与所述驱动电路11的第一端之间连通。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述驱动电路的控制端电连接，所述第一晶体管的第二极与所述连接节点电连接；
所述第一控制晶体管为氧化物薄膜晶体管。
在本公开至少一实施例中，所述控制电路包括的第一晶体管为氧化物薄膜晶体管。
氧化物晶体管具有磁滞特性好，漏电流低，同时Mobility(迁移率)较低。因此本公开至少一实施例将第一晶体管设置为氧化物薄膜晶体管，实现低漏电，保证驱动电路的控制端的电位的稳定性。
可选的，所述补偿控制电路包括第二晶体管；
所述第二晶体管的控制极与所述第二扫描线电连接，所述第二晶体管的第一极与所述连接节点电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
在本公开至少一实施例中，所述第二晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。在具体实施时，所述第二晶体管也可以为其他类型的晶体管。
可选的，所述第一初始化电路包括第三晶体管；
所述第三晶体管的控制极与所述初始化控制线电连接，所述第三晶体管的第一极与第一初始化电压线电连接，所述第三晶体管的第二极与所述连接节点电连接。
在本公开至少一实施例中，所述第三晶体管为低温多晶硅薄膜晶体管。在具体实施时，所述第三晶体管也可以为其他类型的晶体管。
如图47所示，在图46所示的像素电路的基础上，本公开至少一实施例所述的像素电路还可以包括复位电路20；
所述复位电路20分别与第三扫描线S3、复位电压线DR和所述驱动电路11的第二端电连接，用于在所述第三扫描线S3提供的第三扫描信号的控制下，将所述复位电压线DR提供的复位电压写入所述驱动电路11的第二端。
本公开如图47所示的像素电路的至少一实施例增设了复位电路20，复位电路20在第三扫描信号的控制下，在数据电压写入驱动电路11的第二端之前，在非发光时间段，将复位电压写入驱动电路11的第二端，以对驱动电路11中的驱动晶体管提供偏压(此时驱动晶体管的栅极电位也被初始化为Vi1)，使得驱动晶体管保持复位状态，以改善驱动晶体管的磁滞，利于显示屏FFR(第一帧响应时间)。
在具体实施时，驱动晶体管的磁滞会导致驱动晶体管的特性反应较迟钝，而本公开至少一实施例在数据电压写入之前，快速复位驱动晶体管的栅源电压，利于驱动晶体管的恢复速度加快，因此会改善驱动晶体管的磁滞现象，提升磁滞恢复速度。
本公开如图47所示的像素电路的至少一实施例在工作时，在非发光时间段(所述非发光时间段指的可以是所述显示周期包括的除了发光阶段之外的时间段)，在数据电压写入驱动电路11的第二端之前，可以通过增加第三扫描信号的占空比，提升对驱动电路11的第二端进行复位的时间，以使得对驱动电路11的第二端的电位的复位效果更好。
本公开如图47所示的像素电路的至少一实施例在工作时，在所述初始化阶段，所述复位电路在第三扫描信号的控制下，将复位电压写入所述驱动电路的第二端。
在本公开至少一实施例中，所述复位电压为直流电压信号，以为驱动晶体管提供固定偏压，改善磁滞现象。
可选的，所述复位电压可以为高电压，但不以此为限。
在本公开至少一实施例中，可以通过一个单独的第三扫描信号生成模组来提供第三扫描信号至第三扫描线，利于对驱动电路的第二端的电位进行复 位。
在本公开至少一实施例中，所述复位电压线与第一电压线可以为同一电压线，这样可以减少采用的信号线的个数。所述复位电压的电压值大于所述第一初始化电压的电压值；所述第一电压线用于提供第一电压信号(所述第一电压线可以为高电压线)。所述第一电压信号的电压值可以大于0V而小于或等于5V，例如，所述第一电压信号的电压值可以为4.6V，但不以此为限。所述第一初始化电压可以为直流电压，所述第一初始化电压的电压值可以在大于或等于-7V而小于或等于0V；例如，所述第一初始化电压的电压值可以为-6V、-5V、-4V、-3V或-2V，但不以此为限。
在本公开至少一实施例中，驱动电路中的驱动晶体管的阈值电压Vth可以大于或等于-5V而小于或等于-2V，优选情况下，Vth可以大于或等于-4V而小于或等于-2.5V；例如，Vth可以为-4V、-3.5V、-3V或-2.5V，但不以此为限。
所述复位电压的电压值的绝对值可以大于阈值电压的绝对值的1.5倍，以保证在较短时间内能够快速达到偏置效果。例如，所述复位电压的电压值的绝对值可以大于阈值电压的绝对值的2倍、2.5倍或3倍，但不以此为限。
可选的，所述复位电路包括第四晶体管；
所述第四晶体管的控制极与所述第三扫描线电连接，所述第四晶体管的第一极与所述复位电压线电连接，所述第四晶体管的第二极与所述驱动电路的第二端电连接。
在本公开至少一实施例中，所述第四晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
如图48所示，本公开至少一实施例所述的像素电路还可以包括发光元件30、发光控制电路31和第二初始化电路32；
所述发光控制电路31分别与发光控制线E1、第一电压线V1、所述驱动电路11的第二端、所述驱动电路11的第一端与所述发光元件30的第一极电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压线V1与所述驱动电路11的第二端之间连通，并控制所述驱动电路 11的第一端与所述发光元件30的第一极连通；
所述第二初始化电路32分别与第四扫描线S4、第二初始化电压线和所述发光元件30的第一极电连接，用于在所述第四扫描线S4提供的第四扫描信号的控制下，将第二初始化电压线提供的第二初始化电压Vi2写入所述发光元件30的第一极；
所述发光元件30的第二极与第二电压线V2电连接。
在本公开至少一实施例中，所述第一电压线V1可以为高电压线，所述第二电压线V2可以为低电压线，但不以此为限；
所述发光元件30可以为OLED(有机发光二极管)，所述发光元件30的第一极可以为OLED的阳极，所述发光元件30的第二极可以为OLED的阴极，但不以此为限。
在本公开如图48所示的像素电路的至少一实施例中，可以通过一个单独的第四扫描信号生成模组来提供第四扫描信号至第四扫描线，利于低频闪烁下的开关频率切换的自由度(所述开关频率为所述第二初始化电路32包括的晶体管的开关频率)。当所述像素电路应用于的显示面板工作于低频下时，当发光控制电路31控制所述第一电压线V1与所述驱动电路11的第二端之间断开，并控制所述驱动电路11的第一端与所述发光元件30的第一极断开时，能够通过提升所述第四扫描信号的频率，以减轻Flicker(闪烁)。
在本公开至少一实施例中，所述第三扫描信号与所述第四扫描信号可以为同一扫描信号，所述第三扫描信号生成模组与所述第四扫描信号生成模组可以为同一模组，但不以此为限。
本公开如图48所示的像素电路的至少一实施例在工作时，所述第一扫描信号与所述发光控制信号可以为相同的信号，但是考虑到当PWM(脉冲宽度调制)控制发光功能时，在发光过程中，EM可能提供高电压信号，则通过单独的第一扫描信号生成模组为第一扫描线提供第一扫描信号，并通过发光控制信号生成模组为发光控制线提供发光控制信号。
在本公开至少一实施例中，当所述复位电压线为第一电压线时，所述复位电压的电压值可以大于所述第二初始化电压的电压值。
所述第二初始化电压的电压值可以大于或等于-7V而小于或等于0V。例如，所述第二初始化电压的电压值可以为-6V、-5V、-4V、-3V或-2V。
可选的，所述发光控制电路包括第五晶体管和第六晶体管；
所述第五晶体管的控制极与所述发光控制线电连接，所述第五晶体管的第一极与所述第一电压线电连接，所述第五晶体管的第二极与所述驱动电路的第二端电连接；
所述第六晶体管的控制极与所述发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述第二初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述第四扫描线电连接，所述第七晶体管的第一极与所述第二初始化电压线电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第七晶体管可以为氧化物薄膜晶体管。
在本公开至少一实施例中，可以将第七晶体管设置为氧化物薄膜晶体管，这样可以减少漏电，以能够保证发光元件的第一极的电位的稳定性。
如图49所示，在图48所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括数据写入电路41和储能电路42；
所述数据写入电路41分别与第二扫描线S2、数据线D1和所述驱动电路11的第二端电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，将所述数据线D1上的数据电压写入所述驱动电路11的第二端；
所述储能电路42与所述驱动电路11的控制端电连接，用于储存电能。
本公开如图49所示的像素电路的至少一实施例在工作时，显示周期还包括设置于数据写入阶段之后的发光阶段；
在初始化阶段，所述第二初始化电路32在所述第四扫描线S4提供的第四扫描信号的控制下，将第二初始化电压线提供的第二初始化电压Vi2写入所述发光元件30的第一极；
在数据写入阶段，数据写入电路41在第二扫描信号的控制下，将数据线D1上的数据电压Vdata写入驱动电路11的第二端；
在数据写入阶段开始时，驱动电路11控制其第一端与所述驱动电路11的第二端之间连通，以通过数据电压Vdata为储能电路42充电，改变所述驱动电路11的控制端的电位，直至所述驱动电路11的控制端的电位变为Vdata+Vth，Vth为所述驱动电路包括11的驱动晶体管的阈值电压；
在发光阶段，发光控制电路31在发光控制信号的控制下，控制所述第一电压线V1与所述驱动电路11的第二端之间连通，并控制所述驱动电路11的第一端与发光元件30的第一极之间连通，驱动电路11驱动发光元件30发光。
可选的，所述数据写入电路包括第八晶体管，所述储能电路包括存储电容；
所述第八晶体管的控制极与所述第二扫描线电连接，所述第八晶体管的第一极与所述数据线电连接，所述第八晶体管的第二极与所述驱动电路的第二端电连接；
所述存储电容的第一端与所述驱动电路的控制端电连接，所述存储电容的第二端与所述第一电压线电连接。
在本公开至少一实施例中，所述驱动电路可以包括驱动晶体管；
所述驱动晶体管为单栅晶体管，所述驱动晶体管的栅极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；或者，
所述驱动晶体管为双栅晶体管，所述驱动晶体管的第一栅极与所述驱动电路的控制端电连接，所述驱动晶体管的第二栅极与第一电压线电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；所述第一栅极为顶栅，所述第二栅极为底栅。
可选的，所述驱动晶体管可以为单栅晶体管或双栅晶体管。当所述驱动 晶体管为双栅晶体管时，所述驱动晶体管的第一栅极与所述驱动电路的控制端电连接，所述驱动晶体管的第二栅极与第一电压线电连接，第一栅极为顶栅，第二栅极为底栅，以使得驱动晶体管的衬底加偏压，改善驱动晶体管的磁滞现象。
如图50所示，在图49所示的像素电路的至少一实施例的基础上，所述第一控制电路12包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与所述第一扫描线S1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的栅极电连接，所述第一晶体管T1的源极与所述连接节点N0电连接；
所述补偿控制电路13包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第二扫描线S2电连接，所述第二晶体管T2的漏极与所述连接节点N0电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；
所述第一初始化电路14包括第三晶体管T3；
所述第三晶体管T3的栅极与所述初始化控制线R1电连接，所述第三晶体管T3的漏极与第一初始化电压线电连接，所述第三晶体管T3的源极与所述连接节点N0电连接；所述第一初始化电压线用于提供第一初始化电压Vi1；
所述复位电路20包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第三扫描线S3电连接，所述第四晶体管T4的漏极与所述复位电压线DR电连接，所述第四晶体管T4的源极与所述驱动晶体管T0的源极电连接；
所述发光控制电路包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制线E1电连接，所述第五晶体管T5的漏极与高电压线电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的源极电连接；所述高电压线用于提供高电压信号VDD；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体 管T6的漏极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的源极与有机发光二极管O1的阳极电连接；
所述第二初始化电路32包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第四扫描线S4电连接，所述第七晶体管T7的漏极与所述第二初始化电压线电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
所述数据写入电路41包括第八晶体管T8，所述储能电路42包括存储电容C；
所述第八晶体管T8的栅极与所述第二扫描线S2电连接，所述第八晶体管T8的漏极与所述数据线D1电连接，所述第八晶体管T8的源极与所述驱动晶体管T0的源极电连接；
所述存储电容C的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C的第二端与所述高电压线电连接；
O1的阴极与低电压线电连接，所述低电压线用于提供低电压VSS。
在图50中，标号为N1的为第一节点，第一节点N1与T0的栅极电连接；
标号为N2的为第二节点，标号为N3的为第三节点；N2与T0的源极电连接，N3与T0的漏极电连接。
在图50所示的至少一实施例中，第一电压线为高电压线，第二电压线为低电压线。
在图50所示的像素电路的至少一实施例中，T1可以为氧化物薄膜晶体管，T0、T2、T3、T4、T5、T6、T7和T8可以都为低温多晶硅薄膜晶体管，T1为n型晶体管，T0、T2、T3、T4、T5、T6、T7和T8为p型晶体管，T0为单栅晶体管，但不以此为限。
在图50所示的像素电路的至少一实施例中，N1仅直接与T1电连接，N1并不直接与T2和T3电连接，以减少N1的漏电，能够稳定T0的栅极的 电位的稳定性。
在图50所示的像素电路的至少一实施例中，T1为氧化物薄膜晶体管，可以减少漏电，保证N1的电位的稳定性。
可选的，T2和T3可以为单栅晶体管，节省空间。
在如图50所示的像素电路的至少一实施例中，所述初始化控制线R1提供的初始化控制信号，以及，所述第二扫描线提供的第二扫描信号可以都由第二扫描信号生成模组提供。
可选的，在像素电路的至少一实施例中，所述像素电路包括的各晶体管可以设置于基底上，导电图形在所述基底上的正投影与第四扫描线S4在所述基底上的正投影之间的交叠面积尽量少，所述导电图形在所述基底上的正投影与初始化控制线R1在所述基底上的正投影之间的交叠面积尽量少，以减小寄生电容。在优选情况下，所述导电图形与第四扫描线S4之间的电容小于0.3Cz，用于电连接T0的源极和T5的源极的导电图形与初始化控制线R1之间的电容小于0.3Cz；其中，Cz是所述存储电容C的电容值。
所述导电图形包括T0的源极、T5的源极，以及，用于电连接T0的源极与T5的源极的连接导电图形。
如图51所示，本公开如图50所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段t1、数据写入阶段t2和发光阶段t3；
在初始化阶段t1，E1提供高电压信号，S1提供高电压信号，T1打开，R1提供低电压信号，S2提供高电压信号，T2打开，T3关闭，Vi1写入N1，以使得在数据写入阶段t2开始时，T0打开；S3和S4提供低电压信号，T7打开，T4打开，以将DR提供的复位电压写入N2，将Vi2写入O1的阳极，以使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t2，E1提供高电压信号，S1提供高电压信号，T1打开，R1提供高电压信号，S2提供高电压信号，T2打开，T3关断，T8打开，S3和S4提供高电压信号，T7和T4关断，数据线D1上的数据电压Vdata写入N2；
在数据写入阶段t2开始时，T0打开，以通过Vdata，经过打开的T8、T0、T2和T1为C充电，以提升N1的电位，直至T0关断，此时，N1的电位为Vdata+Vth，Vth为T0的阈值电压；
在发光阶段t3，E1提供低电压信号，R1提供高电压信号，S1提供低电压信号，S2、S3和S4提供高电压信号，T1、T2、T3、T4、T7和T8关断，T5和T6打开，T0打开，以驱动O1发光。
在图50所示的像素电路的至少一实施例中，增设了T4，为N2提供高电压，在非发光时间段对N2的电位进行初始化，有利于提高T0稳定性；并提供了T7，以对O1的阳极的电位进行初始化，利于低频闪烁下的开关频率切换的自由度。
如图52所示，在图49所示的像素电路的至少一实施例的基础上，所述第一控制电路12包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与所述第一扫描线S1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的栅极电连接，所述第一晶体管T1的源极与所述连接节点N0电连接；
所述补偿控制电路13包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第二扫描线S2电连接，所述第二晶体管T2的漏极与所述连接节点N0电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；
所述第一初始化电路14包括第三晶体管T3；
所述第三晶体管T3的栅极与所述初始化控制线R1电连接，所述第三晶体管T3的漏极与第一初始化电压线电连接，所述第三晶体管T3的源极与所述连接节点N0电连接；所述第一初始化电压线用于提供第一初始化电压Vi1；
所述复位电路20包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第三扫描线S3电连接，所述第四晶体管T4的漏极与所述复位电压线DR电连接，所述第四晶体管T4的源极与所 述驱动晶体管T0的源极电连接；
所述发光控制电路包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制线E1电连接，所述第五晶体管T5的漏极与高电压线电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的源极电连接；所述高电压线用于提供高电压信号VDD；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的源极与有机发光二极管O1的阳极电连接；
所述第二初始化电路32包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第四扫描线S4电连接，所述第七晶体管T7的漏极与所述第二初始化电压线电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
所述数据写入电路41包括第八晶体管T8，所述储能电路42包括存储电容C；
所述第八晶体管T8的栅极与所述第二扫描线S2电连接，所述第八晶体管T8的漏极与所述数据线D1电连接，所述第八晶体管T8的源极与所述驱动晶体管T0的源极电连接；
所述存储电容C的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C的第二端与所述高电压线电连接；
O1的阴极与低电压线电连接，所述低电压线用于提供低电压VSS。
在图52中，标号为N1的为第一节点，第一节点N1与T0的栅极电连接；
标号为N2的为第二节点，标号为N3的为第三节点；N2与T0的源极电连接，N3与T0的漏极电连接。
在图52所示的至少一实施例中，第一电压线为高电压线，第二电压线为低电压线。
在图52所示的像素电路的至少一实施例中，T1和T7可以为氧化物薄膜晶体管，T0、T2、T3、T4、T5、T6和T8可以都为低温多晶硅薄膜晶体管，T1和T7为n型晶体管，T0、T2、T3、T4、T5、T6和T8为p型晶体管，T0为单栅晶体管，但不以此为限。
本公开图52所示的像素电路的至少一实施例与本公开图50所示的像素电路的至少一实施例的区别在于：T7为氧化物薄膜晶体管。
在图52所示的像素电路的至少一实施例中，N1仅直接与T1电连接，N1并不直接与T2和T3电连接，以减少N1的漏电，能够稳定T0的栅极的电位的稳定性。
在图52所示的像素电路的至少一实施例中，T1和T7为氧化物薄膜晶体管，以减少漏电，保证N1的电位的稳定性，并保证O1的阳极的电位的稳定性。
在图52所示的像素电路的至少一实施例中，可以通过一个单独的第四扫描信号生成模组来提供第四扫描信号至第四扫描线，利于低频闪烁下的开关频率切换的自由度(所述开关频率为所述第二初始化电路32包括的晶体管的开关频率)。当所述像素电路应用于的显示面板工作于低频下时，当发光控制电路31控制所述第一电压线V1与所述驱动电路11的第二端之间断开，并控制所述驱动电路11的第一端与所述发光元件30的第一极断开时，能够通过提升所述第四扫描信号的频率，以减轻Flicker(闪烁)；或者，
所述第四扫描线可以为所述发光控制线，以能够在低频刷新阶段，只需对发光控制线提供的发光控制信号进行周期性控制，即能周期性的对发光元件进行复位/亮度调节，从而实现亮度均衡。
如图53所示，在图49所示的像素电路的至少一实施例的基础上，所述第一控制电路12包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与所述第一扫描线S1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的栅极电连接，所述第一晶体管T1的源极与所述连接节点N0电连接；
所述补偿控制电路13包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第二扫描线S2电连接，所述第二晶体管T2的漏极与所述连接节点N0电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；
所述第一初始化电路14包括第三晶体管T3；
所述第三晶体管T3的栅极与所述初始化控制线R1电连接，所述第三晶体管T3的漏极与第一初始化电压线电连接，所述第三晶体管T3的源极与所述连接节点N0电连接；所述第一初始化电压线用于提供第一初始化电压Vi1；
所述复位电路20包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第三扫描线S3电连接，所述第四晶体管T4的漏极与高电压线电连接，所述第四晶体管T4的源极与所述驱动晶体管T0的源极电连接；所述高电压线用于提供高电压信号VDD；
所述发光控制电路包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制线E1电连接，所述第五晶体管T5的漏极与高电压线电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的源极电连接；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的源极与有机发光二极管O1的阳极电连接；
所述第二初始化电路32包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第四扫描线S4电连接，所述第七晶体管T7的漏极与所述第二初始化电压线电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
所述数据写入电路41包括第八晶体管T8，所述储能电路42包括存储电容C；
所述第八晶体管T8的栅极与所述第二扫描线S2电连接，所述第八晶体 管T8的漏极与所述数据线D1电连接，所述第八晶体管T8的源极与所述驱动晶体管T0的源极电连接；
所述存储电容C的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C的第二端与所述高电压线电连接；
O1的阴极与低电压线电连接，所述低电压线用于提供低电压VSS。
在图53中，标号为N1的为第一节点，第一节点N1与T0的栅极电连接；
标号为N2的为第二节点，标号为N3的为第三节点；N2与T0的源极电连接，N3与T0的漏极电连接。
在图53所示的至少一实施例中，第一电压线为高电压线，第二电压线为低电压线。
在图53所示的像素电路的至少一实施例中，T1可以为氧化物薄膜晶体管，T0、T2、T3、T4、T5、T6、T7和T8可以都为低温多晶硅薄膜晶体管，T1为n型晶体管，T0、T2、T3、T4、T5、T6、T7和T8为p型晶体管，T0为单栅晶体管，但不以此为限。
在图53所示的像素电路的至少一实施例中，N1仅直接与T1电连接，N1并不直接与T2和T3电连接，以减少N1的漏电，能够稳定T0的栅极的电位的稳定性；
T1为氧化物薄膜晶体管，以减少N1的漏电，稳定T0的栅极的电位的稳定性。
本公开图53所示的像素电路的至少一实施例与本公开图50所示的像素电路的至少一实施例的区别在于：所述复位电压线DR为所述高电压线，可以减少采用的信号线的个数。
在本公开图53所示的像素电路的至少一实施例中，VDD的电压值可以为4.6V，VDD的电压值大于Vi1的电压值，VDD的电压值大于Vi2的电压值。
在本公开图53所示的像素电路的至少一实施例中，T7也可以被替换为 氧化物薄膜晶体管，T0也可以被替换为双栅晶体管，但不以此为限。
如图54所示，在图49所示的像素电路的至少一实施例的基础上，所述第一控制电路12包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；所述发光元件为有机发光二极管O1；
所述第一晶体管T1的栅极与所述第一扫描线S1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的第一栅极电连接，所述第一晶体管T1的源极与所述连接节点N0电连接；
所述补偿控制电路13包括第二晶体管T2；
所述第二晶体管T2的栅极与所述第二扫描线S2电连接，所述第二晶体管T2的漏极与所述连接节点N0电连接，所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；
所述第一初始化电路14包括第三晶体管T3；
所述第三晶体管T3的栅极与所述初始化控制线R1电连接，所述第三晶体管T3的漏极与第一初始化电压线电连接，所述第三晶体管T3的源极与所述连接节点N0电连接；所述第一初始化电压线用于提供第一初始化电压Vi1；
所述复位电路20包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第三扫描线S3电连接，所述第四晶体管T4的漏极与所述复位电压线DR电连接，所述第四晶体管T4的源极与所述驱动晶体管T0的源极电连接；
所述发光控制电路包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制线E1电连接，所述第五晶体管T5的漏极与高电压线电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的源极电连接；所述高电压线用于提供高电压信号VDD；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的源极与有机发光二极管O1的阳极电连接；
所述第二初始化电路32包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第四扫描线S4电连接，所述第七晶体管T7的漏极与所述第二初始化电压线电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阳极电连接；所述第二初始电压线用于提供第二初始电压Vi2；
所述数据写入电路41包括第八晶体管T8，所述储能电路42包括存储电容C；
所述第八晶体管T8的栅极与所述第二扫描线S2电连接，所述第八晶体管T8的漏极与所述数据线D1电连接，所述第八晶体管T8的源极与所述驱动晶体管T0的源极电连接；
所述存储电容C的第一端与所述驱动晶体管T0的第一栅极电连接，所述存储电容C的第二端与所述高电压线电连接；
所述驱动晶体管T0的第二栅极与所述高电压线电连接；
O1的阴极与低电压线电连接，所述低电压线用于提供低电压VSS。
在图54中，标号为N1的为第一节点，第一节点N1与T0的栅极电连接；
标号为N2的为第二节点，标号为N3的为第三节点；N2与T0的源极电连接，N3与T0的漏极电连接。
在图54所示的至少一实施例中，第一电压线为高电压线，第二电压线为低电压线。
在图54所示的像素电路的至少一实施例中，T1可以为氧化物薄膜晶体管，T0、T2、T3、T4、T5、T6、T7和T8可以都为低温多晶硅薄膜晶体管，T1为n型晶体管，T0、T2、T3、T4、T5、T6、T7和T8为p型晶体管，T0为双栅晶体管，但不以此为限。
在图54所示的像素电路的至少一实施例中，N1仅直接与T1电连接，N1并不直接与T2和T3电连接，以减少N1的漏电，能够稳定T0的栅极的电位的稳定性。
在图54所示的像素电路的至少一实施例中，T1为氧化物薄膜晶体管， 可以减少漏电，保证N1的电位的稳定性。
在图54所示的像素电路的至少一实施例中，T0为双栅晶体管，T0的第一栅极为顶栅，T0的第二栅极为底栅，T0的第二栅极与所述高电压线电连接，以对T0的衬底加偏压，利于改善T0的磁滞现象。
本公开如图54所示的像素电路的至少一实施例与本公开如图50所示的像素电路的至少一实施例的区别在于：T0为双栅晶体管。
在本公开图54所示的像素电路的至少一实施例中，T7可以被替换为氧化物薄膜晶体管，DR可以为第一电压线，但不以此为限。
在本公开图50、图52、图53、图54所示的像素电路的至少一实施例中，在非发光时间段(所述非发光时间段指的可以是所述显示周期包括的除了发光阶段之外的时间段)，在数据电压Vdata写入N2之前，可以通过增加第三扫描信号的占空比，提升T4的导通时间，以使得对N2的电位的复位效果更好。
如图55所示，相邻两行像素电路可以与同一行复位电压线电连接。在图55中，标号为DRn的为第n行复位电压线(n为正整数)；并位于相邻列的两个像素电路镜像设置，以方便布线。
如图56所示，相邻两列像素电路可以与同一列复位电压线电连接。在图56中，标号为DRm的为第m列复位电压线(m为正整数)；并位于相邻列的两个像素电路镜像设置，以方便布线。
如图57所示，相邻两行像素电路可以与同一行复位电压线电连接，相邻两列像素电路可以与同一列复位电压线电连接，并位于相邻列的两个像素电路镜像设置，多条复位电压线网格状设置，以方便布线。
在图57中，标号为DR11的为第一行复位电压线，标号为DR12的为第二行复位电压线，标号为DR21的为第一列复位电压线，标号为DR22的为第二列复位电压线，标号为DR23的为第三列复位电压线。
在图58中，标号为DR11的为第一行复位电压线，标号为DR12的为第二行复位电压线，标号为DR13的为第三行复位电压线，标号为DR14的为 第四行复位电压线，标号为DR21的为第一列复位电压线，标号为DR22的为第二列复位电压线。
如图58所示，位于第一行的像素电路都与第一行复位电压线DR11电连接，位于第二行的像素电路与第二行复位电压线DR12电连接，位于第三行的像素电路都与第三行复位电压线DR13电连接，位于第四行的像素电路与第四行复位电压线DR14电连接；
并设置有竖向延伸的复位电压线，使得多条复位电压线网格状设置；并且，可以每隔几列像素电路设置一列复位电压线，以节省布线空间。
在具体实施时，可以在红色像素电路列一侧设置竖向延伸的复位电压线。
本公开实施例所述的驱动方法，应用于上述的像素电路，显示周期包括初始化阶段和数据写入阶段；所述驱动方法包括：
在初始化阶段，第一控制电路在第一扫描信号的控制下，控制驱动电路的控制端与连接节点之间连通，第一初始化电路在初始化控制信号的控制下，将第一初始化电压写入连接节点，从而将第一初始化电压写入所述驱动电路的控制端，以使得在所述数据写入阶段开始时驱动电路能够控制其第一端与所述驱动电路的第二端之间连通；
在数据写入阶段，第一控制电路在第一扫描信号的控制下，控制驱动电路的控制端与连接节点之间连通，补偿控制电路在第二扫描信号的控制下，控制所述连接节点与所述驱动电路的第一端之间连通，以使得所述驱动电路的控制端与所述驱动电路的第一端之间连通。
在本公开实施例所述的驱动方法中，第一控制电路控制驱动电路的控制端与连接节点之间连通，第一初始化电路在初始化控制信号的控制下，将第一初始化电压写入连接节点，补偿控制电路在第二扫描信号的控制下，控制所述连接节点与所述驱动电路的第一端之间连通，第一控制电路直接与驱动电路的控制端电连接，第一初始化电路和补偿控制电路并不直接与驱动电路的控制端电连接，以减少第一节点(与驱动电路的控制端电连接的节点)的漏电路径，以能够在低频工作时保证第一节点的电压的稳定性，利于提升显示质量，提升显示均一性，减轻Flicker(闪烁)。
在具体实施时，所述像素电路还可以包括复位电路；所述驱动方法还包括：
在所述初始化阶段，所述复位电路在第三扫描信号的控制下，将复位电压写入所述驱动电路的第二端。
可选的，所述像素电路还可以包括发光元件和第二初始化电路；所述驱动方法还包括：
所述第二初始化电路在第四扫描信号的控制下，将第二初始化电压写入所述发光元件的第一极，以控制所述发光元件不发光。
在具体实施时，所述像素电路还包括发光控制电路、数据写入电路和储能电路，显示周期包括设置于数据写入阶段之后的发光阶段，所述驱动方法还包括：
在数据写入阶段，数据写入电路在第二扫描信号的控制下，将数据线上的数据电压Vdata写入驱动电路的第二端；
在数据写入阶段开始时，驱动电路控制其第一端与所述驱动电路的第二端之间连通，以通过数据电压Vdata为储能电路充电，改变所述驱动电路的控制端的电位，直至所述驱动电路的控制端的电位变为Vdata+Vth，Vth为所述驱动电路包括的驱动晶体管的阈值电压；
在发光阶段，发光控制电路在发光控制信号的控制下，控制所述第一电压线与所述驱动电路的第二端之间连通，并控制所述驱动电路的第一端与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
本公开实施例所述的显示装置包括上述的像素电路。
可选的，所述像素电路包括复位电路和第二初始化电路，所述复位电路与第三扫描线电连接，所述第二初始化电路与所述第四扫描线电连接；所述显示装置还包括第三扫描信号生成模组和第四扫描信号生成模组；
所述第三扫描信号生成模组与所述第三扫描线电连接，用于为所述第三扫描线提供第三扫描信号；
所述第四扫描信号生成模组与所述第四扫描线电连接，用于为所述第四 扫描线提供第四扫描信号。
在本公开至少一实施例中，所述第三扫描信号与所述第四扫描信号可以为同一扫描信号，所述第三扫描信号生成模组与所述第四扫描信号生成模组可以为同一模组。
如图59所示，本公开至少一实施例所述的显示装置包括显示面板，所述显示面板包括像素模组P0，所述像素模组P0包括多行多列上述的像素电路；所述像素模组P0设置于显示面板的有效显示区域内；
所述显示面板还包括发光控制信号生成模组70、第一扫描信号生成模组71、第一个第二扫描信号生成模组721、第二个第二扫描信号生成模组722、第三扫描信号生成模组73和第四扫描信号生成模组74；
所述发光控制信号生成模组70用于提供发光控制信号，第一扫描信号生成模组71用于提供第一扫描信号，第一个第二扫描信号生成模组721和第二个第二扫描信号生成模组722用于提供第二扫描信号，所述第三扫描信号生成模组73用于提供第三扫描信号，所述第四扫描信号生成模组74用于提供第四扫描信号；
发光控制信号生成模组70、第一扫描信号生成模组71和第一个第二扫描信号生成模组721设置于所述显示面板左侧边，
第二个第二扫描信号生成模组722、第三扫描信号生成模组73和第四扫描信号生成模组74设置于所述显示面板右侧边。
如图60所示，本公开至少一实施例所述的显示装置包括显示面板，所述显示面板包括像素模组P0，所述像素模组P0包括多行多列上述的像素电路；所述像素模组P0设置于显示面板的有效显示区域内；
所述显示面板还包括发光控制信号生成模组70、第一个第一扫描信号生成模组711、第二个第一扫描信号生成模组712、第一个第二扫描信号生成模组721、第二个第二扫描信号生成模组722和第四扫描信号生成模组74；
所述发光控制信号生成模组70用于提供发光控制信号，第一个扫描信号生成模组711和第二个第一扫描信号生成模组712用于提供第一扫描信号， 第一个第二扫描信号生成模组721和第二个第二扫描信号生成模组722用于提供第二扫描信号；
第三扫描信号和第四扫描信号为同一扫描信号；
所述第四扫描信号生成模组74用于提供第三扫描信号和第四扫描信号；
发光控制信号生成模组70、第一个第一扫描信号生成模组711和第一个第二扫描信号生成模组721设置于所述显示面板左侧边，
第二个第一扫描信号生成模组712、第二个第二扫描信号生成模组722和第四扫描信号生成模组74设置于所述显示面板右侧边。
在图55和图56中，标号为Vi1的为第一初始化电压，标号为Vi2的为第二初始化电压，标号为VDD的为高电压信号，标号为D1的为数据线，标号为DR的为复位电压线。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
如图61-78所示，为本公开像素驱动电路另一组示例性实施例的说明附图。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素电路包括驱动电路、第一初始化电路和复位电路；
所述第一初始化电路分别与初始化控制线、所述驱动电路的第一端和第一初始电压端电连接，用于在所述初始化控制线提供的初始化控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的第一端；
所述复位电路分别与第二扫描线和复位电压端电连接，所述复位电路还与所述驱动电路的第二端或所述驱动电路的第一端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制将所述复位电压端提供的复位电压写入所述驱动电路的第二端或所述驱动电路的第一端；
所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通。
本公开所述的像素电路的至少一实施例包括第一初始化电路和复位电路，第一初始化电路在数据电压写入驱动电路的第二端之前，将第一初始电压写入驱动电路的第一端，以便配合像素电路包括的补偿控制电路将第一初始电压写入驱动电路的控制端；复位电路在第二扫描信号的控制下，在数据电压写入驱动电路的第二端之前，在非发光时间段，将复位电压写入驱动电路的第二端或驱动电路的第一端，以对驱动电路中的驱动晶体管提供偏压(此时驱动晶体管的栅极电位也被初始化为Vi1)，使得驱动晶体管保持复位状态，以改善驱动晶体管的磁滞，利于显示屏FFR(第一帧响应时间)。
在具体实施时，驱动晶体管的磁滞会导致驱动晶体管的特性反应较迟钝，而本公开至少一实施例在数据电压写入之前，快速复位驱动晶体管的栅源电压，利于驱动晶体管的恢复速度加快，因此会改善驱动晶体管的磁滞现象，提升磁滞恢复速度。
在本公开至少一实施例中，可以通过一个单独的第二扫描信号生成模组来提供第二扫描信号至第二扫描线，利于对驱动电路的第二端的电位进行复位。
在本公开至少一实施例中，所述复位电压为恒定电压，以为驱动晶体管提供固定偏压，改善磁滞现象。
可选的，所述第一初始电压为低电位恒定电压，所述第一初始电压的电压值大于或等于-6V而小于或等于-2V；例如，所述第一初始化电压的电压值可以为-6V、-5V、-4V、-3V或-2V，但不以此为限。
在具体实施时，所述复位电压可以为高电位恒定电压，以保证在数据写入阶段开始时，驱动电路中的驱动晶体管能够快速导通；所述复位电压的电 压值大于或等于4V而小于或等于10V；或者，
所述复位电压可以为低电位恒定电压，所述复位电压的电压值大于或等于-6V而小于或等于-2V。
可选的，当所述复位电压为高电位恒定电压时，所述复位电压的电压值例如可以为4V、5V、6V、7V、8V、9V或10V，但不以此为限；
当所述复位电压为低电位恒定电压时，所述复位电压的电压值例如可以为-6V、-5V、-4V、-3V或-2V，但不以此为限。
在本公开至少一实施例中，当所述复位电压为低电位恒定电压时，所述复位电压的电压值与所述第一初始电压的电压值大致相同，以在同时通过复位电路将复位电压写入驱动电路的第二端，通过第一初始化电路将第一初始电压写入驱动电路的第一端时，驱动电路中的驱动晶体管不会发生故障。
所述复位电压的电压值与所述第一初始电压的电压值大致相同指的可以时：所述复位电压的电压值与所述第一初始电压的电压值之间的差值的绝对值小于预定电压差值。例如，所述预定电压差值可以为0.1V或0.05V，但不以此为限。
在本公开至少一实施例中，驱动电路中的驱动晶体管的阈值电压Vth可以大于或等于-5V而小于或等于-2V，优选情况下，Vth可以大于或等于-4V而小于或等于-2.5V；例如，Vth可以为-4V、-3.5V、-3V或-2.5V，但不以此为限。
可选的，所述驱动电路包括驱动晶体管，所述复位电压的电压值的绝对值大于阈值电压的绝对值的1.5倍，以保证在较短时间内能够快速达到偏置效果。所述阈值电压为所述驱动晶体管的阈值电压。例如，所述复位电压的电压值的绝对值可以大于阈值电压的绝对值的2倍、2.5倍或3倍，但不以此为限。
如图61所示，本公开实施例所述的像素电路包括驱动电路11、第一初始化电路13和复位电路20；
所述第一初始化电路13分别与初始化控制线R1、所述驱动电路11的第 一端和第一初始电压端电连接，用于在所述初始化控制线R1提供的初始化控制信号的控制下，将所述第一初始电压端提供的第一初始电压Vi1写入所述驱动电路11的第一端；
所述复位电路20分别与第二扫描线S2和复位电压端DR电连接，所述复位电路20还与所述驱动电路11的第二端电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，控制将所述复位电压端DR提供的复位电压写入所述驱动电路11的第二端；
所述驱动电路11用于在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路12的第二端之间连通。
在图61中，标号为N1的为第一节点，所述第一节点N1与所述驱动电路11的控制端电连接。
本公开如图61所示的像素电路的至少一实施例在工作时，所述显示周期可以包括初始化阶段和复位阶段；
在所述初始化阶段，第一初始化电路13在初始化控制信号的控制下，将第一初始电压Vi1写入驱动电路11的第一端；
在所述复位阶段，复位电路20在第二扫描信号的控制下，将复位电压写入驱动电路11的第二端。
如图62所示，本公开至少一实施例所述的像素电路可以包括驱动电路11、第一初始化电路13和复位电路20；
所述第一初始化电路13分别与初始化控制线R1、所述驱动电路11的第一端和第一初始电压端电连接，用于在所述初始化控制线R1提供的初始化控制信号的控制下，将所述第一初始电压端提供的第一初始电压Vi1写入所述驱动电路11的第一端；
所述复位电路20分别与第二扫描线S2和复位电压端DR电连接，所述复位电路20还与所述驱动电路11的第一端电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，控制将所述复位电压端DR提供的复位电压写入所述驱动电路11的第一端。
本公开如图62所示的像素电路的至少一实施例在工作时，所述显示周期可以包括初始化阶段和复位阶段；
在所述初始化阶段，第一初始化电路13在初始化控制信号的控制下，将第一初始电压Vi1写入驱动电路11的第一端；
在所述复位阶段，复位电路20在第二扫描信号的控制下，将复位电压写入驱动电路11的第一端。
可选的，所述第一初始化电路包括第二晶体管；
所述第二晶体管的控制极与所述初始化控制线电连接，所述第二晶体管的第一极与所述第一初始电压端电连接，所述第二晶体管的第二极与所述驱动电路的第一端电连接。
在本公开至少一实施例中，所述第二晶体管可以为低温多晶硅薄膜晶体管，但不以此为限。
可选的，所述复位电路包括第三晶体管；
所述第三晶体管的控制极与所述第二扫描线电连接，所述第三晶体管的第一极与所述复位电压端电连接，所述第三晶体管的第二极与所述驱动电路的第二端或所述驱动电路的第一端电连接。
在本公开至少一实施例中，所述像素电路可以包括补偿控制电路；
所述补偿控制电路分别与第一扫描线、所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通。
本公开至少一实施例所述的像素电路在工作时，显示周期可以包括初始化阶段；在初始化阶段，第一初始化电路在初始化控制信号的控制下，将第一初始电压写入驱动电路的第一端，补偿控制电路在第一扫描信号的控制下，控制驱动电路的控制端与所述驱动电路的第一端之间连通，以将第一初始电压写入所述驱动电路的控制端，以使得在数据写入阶段开始时，所述驱动电路能够在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动晶体管的第二端之间连通。
在本公开至少一实施例所述的像素电路中，所述驱动电路的控制端仅直接与补偿控制电路电连接，第一初始化电路直接与所述驱动电路的第一端电连接，以通过补偿控制电路和第一初始化电路为驱动电路的控制端的电位进行初始化，减少对所述驱动电路的控制端的漏电路径，在像素电路设计复杂性没有明显增加的条件下，可以保证第一节点的电压的稳定性，利于提升显示质量，提升显示均一性，减轻Flicker(闪烁)。
可选的，所述补偿控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第一扫描线电连接，所述第一晶体管的第一极与所述驱动电路的控制端电连接，所述第一晶体管的第二极与所述驱动电路的第一端电连接；
所述第一晶体管为氧化物薄膜晶体管。
在本公开实施例中，所述补偿控制电路可以包括第一晶体管，第一晶体管为氧化物薄膜晶体管。氧化物晶体管具有磁滞特性好，漏电流低，同时Mobility(迁移率)较低。因此本公开至少一实施例将第一晶体管设置为氧化物薄膜晶体管，实现低漏电，保证驱动电路的控制端的电位的稳定性。
如图63所示，在图61所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括补偿控制电路12；
所述补偿控制电路12分别与第一扫描线S1、所述驱动电路11的控制端和所述驱动电路11的第一端电连接，用于在所述第一扫描线S1提供的第一扫描信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第一端之间连通。
本公开如图63所述的像素电路的至少一实施例在工作时，显示周期可以包括初始化阶段，在初始化阶段，补偿控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与驱动电路11的第一端之间连通。
如图64所示，在图62所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括补偿控制电路12；
所述补偿控制电路12分别与第一扫描线S1、所述驱动电路11的控制端 和所述驱动电路11的第一端电连接，用于在所述第一扫描线S1提供的第一扫描信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第一端之间连通。
本公开如图64所述的像素电路的至少一实施例在工作时，显示周期可以包括初始化阶段，在初始化阶段，补偿控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与驱动电路11的第一端之间连通。
在本公开至少一实施例中，所述的像素电路还可以包括发光元件、储能电路、第二初始化电路、数据写入电路和发光控制电路；
所述储能电路与所述驱动电路的控制端电连接，用于储存电能；
所述第二初始化电路分别与第三扫描线、第二初始电压端和所述发光元件的第一极电连接，用于在所述第三扫描线提供的第三扫描信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极；
所述数据写入电路分别与第四扫描线、数据线和所述驱动电路的第二端电连接，用于在所述第四扫描线提供的第四扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第二端；
所述发光控制电路分别与发光控制线、第一电压端、所述驱动电路的第二端、所述驱动电路的第一端和所述发光元件的第一极电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通，控制所述驱动电路的第一端与所述发光元件的第一极之间连通；
所述发光元件的第二极与第二电压端电连接。
在本公开至少一实施例中，所述像素电路还可以包括发光元件、储能电路、第二初始化电路、数据写入电路和发光控制电路，第二初始化电路为发光元件的第一极进行初始化，数据写入电路将数据电压写入驱动电路的第二端，发光控制电路在发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第二端之间连通，控制所述驱动电路的第一端与所述发光元件的第一极之间连通。
可选的，所述发光元件可以为有机发光二极管，所述发光元件的第一极可以为有机发光二极管的阳极，所述发光元件的第二极可以为有机发光二极管的阴极；
所述第一电压端可以为高电压端，所述第二电压端可以为低电压端；
但不以此为限。
如图65所示，在图63所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括发光元件40、储能电路41、第二初始化电路42、数据写入电路43和发光控制电路44；
所述储能电路41与所述驱动电路11的控制端电连接，用于储存电能；
所述第二初始化电路42分别与第三扫描线S3、第二初始电压端和所述发光元件40的第一极电连接，用于在所述第三扫描线S3提供的第三扫描信号的控制下，将所述第二初始电压端提供的第二初始电压Vi2写入所述发光元件40的第一极；
所述数据写入电路43分别与第四扫描线S4、数据线D1和所述驱动电路11的第二端电连接，用于在所述第四扫描线S4提供的第四扫描信号的控制下，将所述数据线D1提供的数据电压写入所述驱动电路11的第二端；
所述发光控制电路44分别与发光控制线E1第一电压端V1、所述驱动电路11的第二端、所述驱动电路11的第一端和所述发光元件40的第一极电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路11的第二端之间连通，控制所述驱动电路11的第一端与所述发光元件40的第一极之间连通；
所述发光元件40的第二极与第二电压端V2电连接。
本公开如图65所示的像素电路的至少一实施例在工作时，显示周期还包括设置于所述初始化阶段之后的数据写入阶段和发光阶段；
在所述数据写入阶段，数据写入电路43在第四扫描信号的控制下，将数据线D1提供的数据电压Vdata写入所述驱动电路11的第二端；补偿控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与所述驱动电路 11的第一端之间连通；
在所述数据写入阶段开始时，所述驱动电路11在其控制端的控制下，导通所述驱动电路11的第一端与所述驱动电路11的第二端之间的连接，以通过数据电压Vdata向储能电路41充电，从而改变所述驱动电路11的控制端的电位，直至所述驱动电路11的控制端的电位变为Vdata+Vth，Vth为所述驱动电路11包括的驱动晶体管的阈值电压；
在发光阶段，发光控制电路44在发光控制信号的控制下，控制第一电压端V1与所述驱动电路11的第二端之间连通，控制所述驱动电路11的第一端与发光元件40的第一极之间连通，驱动电路11驱动发光元件40发光。
在具体实施时，所述复位阶段可以设置于所述初始化阶段和所述数据写入阶段之间，但不以此为限。
如图66所示，在图64所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括发光元件40、储能电路41、第二初始化电路42、数据写入电路43和发光控制电路44；
所述储能电路41与所述驱动电路11的控制端电连接，用于储存电能；
所述第二初始化电路42分别与第三扫描线S3、第二初始电压端和所述发光元件40的第一极电连接，用于在所述第三扫描线S3提供的第三扫描信号的控制下，将所述第二初始电压端提供的第二初始电压Vi2写入所述发光元件40的第一极；
所述数据写入电路43分别与第四扫描线S4、数据线D1和所述驱动电路11的第二端电连接，用于在所述第四扫描线S4提供的第四扫描信号的控制下，将所述数据线D1提供的数据电压写入所述驱动电路11的第二端；
所述发光控制电路44分别与发光控制线E1、第一电压端V1、所述驱动电路11的第二端、所述驱动电路11的第一端和所述发光元件40的第一极电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路11的第二端之间连通，控制所述驱动电路11的第一端与所述发光元件40的第一极之间连通；
所述发光元件40的第二极与第二电压端V2电连接。
本公开如图66所示的像素电路的至少一实施例在工作时，显示周期还包括设置于所述初始化阶段之后的数据写入阶段和发光阶段；
在所述数据写入阶段，数据写入电路43在第四扫描信号的控制下，将数据线D1提供的数据电压Vdata写入所述驱动电路11的第二端；补偿控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与所述驱动电路11的第一端之间连通；
在所述数据写入阶段开始时，所述驱动电路11在其控制端的控制下，导通所述驱动电路11的第一端与所述驱动电路11的第二端之间的连接，以通过数据电压Vdata向储能电路41充电，从而改变所述驱动电路11的控制端的电位，直至所述驱动电路11的控制端的电位变为Vdata+Vth，Vth为所述驱动电路11包括的驱动晶体管的阈值电压；
在发光阶段，发光控制电路44在发光控制信号的控制下，控制第一电压端V1与所述驱动电路11的第二端之间连通，控制所述驱动电路11的第一端与发光元件40的第一极之间连通，驱动电路11驱动发光元件40发光。
如图67所示，本公开至少一实施例所述的像素电路可以包括驱动电路11、补偿控制电路12、第一初始化电路13、发光元件40、储能电路41、第二初始化电路42、数据写入电路43和发光控制电路44；
所述补偿控制电路12分别与第一扫描线S1、所述驱动电路11的控制端和所述驱动电路11的第一端电连接，用于在所述第一扫描线S1提供的第一扫描信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第一端之间连通；
所述第一初始化电路13分别与初始化控制线R1、所述驱动电路11的第一端和第一初始电压端电连接，用于在所述初始化控制线R1提供的初始化控制信号的控制下，将所述第一初始电压端提供的第一初始电压Vi1写入所述驱动电路11的第一端；
所述驱动电路11用于在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路12的第二端之间连通；
所述储能电路41与所述驱动电路11的控制端电连接，用于储存电能；
所述第二初始化电路42分别与第三扫描线S3、第二初始电压端和所述发光元件40的第一极电连接，用于在所述第三扫描线S3提供的第三扫描信号的控制下，将所述第二初始电压端提供的第二初始电压Vi2写入所述发光元件40的第一极；
所述数据写入电路43分别与第四扫描线S4、数据线D1和所述驱动电路11的第二端电连接，用于在所述第四扫描线S4提供的第四扫描信号的控制下，将所述数据线D1提供的数据电压写入所述驱动电路11的第二端；
所述发光控制电路44分别与发光控制线E1、第一电压端V1、所述驱动电路11的第二端、所述驱动电路11的第一端和所述发光元件40的第一极电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路11的第二端之间连通，控制所述驱动电路11的第一端与所述发光元件40的第一极之间连通；
所述发光元件40的第二极与第二电压端V2电连接。
本公开如图67所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段、数据写入阶段和发光阶段；
在初始化阶段，第一初始化电路13在初始化控制信号的控制下，将第一初始电压Vi1写入驱动电路11的第一端，补偿控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与所述驱动电路11的第一端之间连通，以将第一初始电压Vi1写入所述驱动电路11的控制端，以使得在数据写入阶段开始时，所述驱动电路11能够在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动晶体管11的第二端之间连通；
在所述数据写入阶段，数据写入电路43在第四扫描信号的控制下，将数据线D1提供的数据电压Vdata写入所述驱动电路11的第二端；补偿控制电路12在第一扫描信号的控制下，控制驱动电路11的控制端与所述驱动电路11的第一端之间连通；
在所述数据写入阶段开始时，所述驱动电路11在其控制端的控制下，导通所述驱动电路11的第一端与所述驱动电路11的第二端之间的连接，以通 过数据电压Vdata向储能电路41充电，从而改变所述驱动电路11的控制端的电位，直至所述驱动电路11的控制端的电位变为Vdata+Vth，Vth为所述驱动电路11包括的驱动晶体管的阈值电压；
在发光阶段，发光控制电路44在发光控制信号的控制下，控制第一电压端V1与所述驱动电路11的第二端之间连通，控制所述驱动电路11的第一端与发光元件40的第一极之间连通，驱动电路11驱动发光元件40发光。
在图65、图66、图67所示的像素电路的至少一实施例中，可以通过一个单独的第三扫描信号生成模组来提供第三扫描信号至第三扫描线S3，利于低频闪烁下的开关频率切换的自由度(所述开关频率为所述第二初始化电路包括的晶体管的开关频率)，但不以此为限。在具体实施时，所述第三扫描信号也可以与所述第四扫描信号为同一扫描信号。
当所述像素电路应用于的显示面板工作于低频下时，当发光控制电路44控制所述第一电压端V1与所述驱动电路11的第二端之间断开，并控制所述驱动电路11的第一端与所述发光元件40的第一极断开时，能够通过提升所述第三扫描信号的频率，以减轻Flicker(闪烁)。
在本公开至少一实施例中，所述第二扫描信号与所述第三扫描信号可以为同一扫描信号，所述第二扫描信号生成模组与所述第三扫描信号生成模组可以为同一模组，但不以此为限。在具体实施时，所述第二扫描信号也可以与第三扫描信号为不同的扫描信号。
本公开如图65、图66、图67所示的像素电路的至少一实施例在工作时，在非发光时间段，在数据电压写入驱动电路11的第二端之前，所述第二初始化电路42在所述第三扫描线S3提供的第三扫描信号的控制下，将所述第二初始电压端提供的第二初始电压Vi2写入所述发光元件40的第一极，以控制所述发光元件40不发光，并清除所述发光元件40的第一极残留的电荷。
在本公开至少一实施例中，所述初始化阶段与所述数据写入阶段之间的时间间隔大于预定时间间隔，以通过对驱动晶体管的栅极电位提前初始化，改善驱动晶体管的磁滞现象，降低像素电路的高低频Flicker(闪烁)。
在具体实施时，所述预定时间间隔可以根据实际情况选定。
在本公开如图65、图66、图67所示的像素电路的至少一实施例中，初始化控制线R1提供的初始化控制信号和第四扫描信号可以由同一第四扫描信号生成模组生成，所述第四扫描信号可以为所述第四扫描信号生成模组生成的第N级第四扫描信号，所述初始化控制信号可以为所述第四扫描信号生成模组生成的第N-M级第四扫描信号，以提前对驱动晶体管的栅极的电位进行初始化；N为正整数，M可以为大于6的正整数，例如，M可以为14，但不以此为限。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的控制极与所述第四扫描线电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与驱动电路的第二端电连接；
所述发光控制电路包括第五晶体管和第六晶体管；
所述第五晶体管的控制极与所述发光控制线电连接，所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述驱动电路的第二端电连接；
所述第六晶体管的控制极与所述发光控制线电连接，所述第六晶体管的第一极与所述驱动电路的第一端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接；
所述第二初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述第三扫描线电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接；
所述驱动电路包括驱动晶体管；所述驱动晶体管的控制极与所述驱动电路的控制端电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动电路的第二极与所述驱动电路的第二端电连接；
所述储能电路包括存储电容；所述存储电容的第一端与所述驱动电路的控制端电连接，所述存储电容的第二端与所述第一电压端连接。
如图68所示，在图65所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述补偿控制电路12包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；
所述第一晶体管T1的栅极与所述第一扫描线S1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的栅极电连接，所述第一晶体管T1的源极与所述驱动晶体管T1的漏极电连接；
所述第一初始化电路13包括第二晶体管T2；
所述第二晶体管T2的栅极与所述初始化控制线R1电连接，所述第二晶体管T2的漏极与所述第一初始电压端电连接所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；所述第一初始电压端用于提供第一初始电压Vi1；
所述复位电路20包括第三晶体管T3；
所述第三晶体管T3的栅极与所述第二扫描线S2电连接，所述第三晶体管T3的漏极与所述复位电压端DR电连接，所述第三晶体管T3的源极与所述驱动晶体管T0的源极电连接；
所述数据写入电路43包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第四扫描线S4电连接，所述第四晶体管T4的漏极与所述数据线D1电连接，所述第四晶体管T4的源极与驱动晶体管T0的源极电连接；
所述发光控制电路包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制线E1电连接，所述第五晶体管T5的漏极与高电压端电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的源极电连接；所述高电压端用于提供高电压信号VDD；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的源极与有机发光二极管O1的阳极电连接；O1的阴极与低电压端电连接，所述低电压端用于提供低电压信号VSS；
所述第二初始化电路42包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第三扫描线S3电连接，所述第七晶体管T7的漏极与所述第二初始电压端电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阳极电连接；所述第二初始电压端用于提供第二初始电压Vi2；
所述储能电路41包括存储电容C；所述存储电容C的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C的第二端与所述高电压端连接。
在图68所示的像素电路的至少一实施例中，T1为氧化物薄膜晶体管，T2、T3、T4、T5、T6和T7为低温多晶硅薄膜晶体管，T1为n型晶体管，T2、T3、T4、T5、T6和T7为p型晶体管。
在图68所示的像素电路的至少一实施例中，N1为与T0的栅极电连接的第一节点，N2为与T0的源极电连接的第二节点，N3为与T0的漏极电连接的第三节点。
在图68所示的像素电路的至少一实施例中，所述初始化控制信号和所述第四扫描信号可以由同一第四扫描信号生成模组提供。
在具体实施时，当DR提供的复位电压为高电压时，复位阶段和初始化阶段为不同的阶段，以避免T0的栅源短路；当DR提供的复位电压为低电压时，复位阶段和初始化阶段可以为同一阶段。
如图69所示，本公开如图68所示的像素电路的至少一实施例在工作时，当DR提供的复位电压为高电压时，显示周期可以包括先后设置的初始化阶段t1、复位阶段t2、数据写入阶段t3和发光阶段t4；
在初始化阶段t1，E1提供高电压信号，R1提供低电压信号，S4提供高电压信号，S1提供高电压信号，S2和S3都提供高电压信号，T1和T2打开，以将Vi1写入N1，对T0的栅极的电位进行初始化，使得在数据写入阶段t3开始时，T0能够打开；
在复位阶段t2，E1提供高电压信号，R1提供高电压信号，S4提供高电压信号，S1提供低电压信号，S2和S3都提供低电压信号，T3和T7打开， 以通过DR提供的高电压为N2的电位进行初始化，以对T0的栅源电压进行复位，利于T0的恢复速度加快，因此会改善T0的磁滞现象，提升磁滞恢复速度；将Vi2写入O1的阳极，以使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t3，E1提供高电压信号，R1提供高电压信号，S4提供低电压信号，S1提供高电压信号，S2和S3都提供高电压信号，T1打开，T4打开；
在数据写入阶段t3开始时，T0打开，通过D1提供的数据电压Vdata为C充电，以提升N1的电位，直至T0关断，N1的电位为Vdata+Vth，其中，Vth为T0的阈值电压；
在发光阶段，E1提供低电压信号，R1提供高电压信号，S4提供高电压信号，S1提供低电压信号，S2和S3都提供高电压信号，T5、T0和T6打开，T0驱动O1发光。
如图70所示，本公开如图68所示的像素电路的至少一实施例在工作时，当DR提供的复位电压为低电压时，显示周期可以包括先后设置的初始化阶段t1、数据写入阶段t3和发光阶段t4；
在初始化阶段t1，E1提供高电压信号，R1提供低电压信号，S4提供高电压信号，S1提供高电压信号，S2和S3都提供低电压信号，T1和T2打开，以将Vi1写入N1，以使得在数据写入阶段t3开始时，T0能够打开；T3和T7打开，DR提供的复位电压写入N2，Vi2写入O1的阳极，以对T0的栅源电压进行复位，利于T0的恢复速度加快，因此会改善T0的磁滞现象，提升磁滞恢复速度；将Vi2写入O1的阳极，以使得O1不发光，并清除O1的阳极残留的电荷；
在数据写入阶段t3，E1提供高电压信号，R1提供高电压信号，S4提供低电压信号，S1提供高电压信号，S2和S3都提供高电压信号，T1打开，T4打开；
在数据写入阶段t3开始时，T0打开，通过D1提供的数据电压Vdata为C充电，以提升N1的电位，直至T0关断，N1的电位为Vdata+Vth，其中， Vth为T0的阈值电压；
在发光阶段，E1提供低电压信号，R1提供高电压信号，S4提供高电压信号，S1提供低电压信号，S2和S3都提供高电压信号，T5、T0和T6打开，T0驱动O1发光。
如图71所示，本公开如图68所示的像素电路的至少一实施例在工作时，当R1提供的初始化控制信号为第N-14级第四扫描信号，S4提供的第四扫描信号为第N级第四扫描信号时，显示周期可以包括先后设置的初始化阶段t1、复位阶段t2、数据写入阶段t3和发光阶段t4；在初始化阶段t1，E1提供高电压信号，S1提供高电压信号，R1提供低电压信号，S2和S3都提供高电压信号，S4提供高电压信号，T1和T2打开，以将Vi1写入N1，以使得在数据写入阶段t3开始时，T0能够打开；
在复位阶段t2，E1提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2和S3都提供低电压信号，S4提供高电压信号，T3和T7打开，以通过DR提供的高电压为N2的电位进行初始化，以对T0的栅源电压进行复位，利于T0的恢复速度加快，因此会改善T0的磁滞现象，提升磁滞恢复速度；将Vi2写入O1的阳极，以使得O1不发光，并清除O1的阳极残留的电荷；T1打开，T2关断，T5和T6关断；
在数据写入阶段t3，E1提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2和S3都提供高电压信号，S4提供低电压信号，T1和T4打开，以将Vdata写入N2，并N1和N3之间连通，以通过D1上的数据电压Vdata为C充电，提升N1的电位，直至T0关断，此时T0的栅极的电位为Vdata+Vth；
在发光阶段t4，E1提供低电压信号，S1提供低电压信号，R1提供高电压信号，S2和S3都提供高电压信号，S4提供高电压信号，T5、T6和T0打开，T0驱动O1发光。
在图68所示的像素电路的至少一实施例中，DR提供的复位电压可以为VDD，或者，DR可以与E1为同一信号端；或者，D4提供的复位电压可以为第三初始化电压；但不以此为限。
如图72所示，在图67所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述补偿控制电路12包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；
所述第一晶体管T1的栅极与所述第一扫描线S1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的栅极电连接，所述第一晶体管T1的源极与所述驱动晶体管T1的漏极电连接；
所述第一初始化电路13包括第二晶体管T2；
所述第二晶体管T2的栅极与所述初始化控制线R1电连接，所述第二晶体管T2的漏极与所述第一初始电压端电连接所述第二晶体管T2的源极与所述驱动晶体管T0的漏极电连接；所述第一初始电压端用于提供第一初始电压Vi1；
所述数据写入电路43包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第四扫描线S4电连接，所述第四晶体管T4的漏极与所述数据线D1电连接，所述第四晶体管T4的源极与驱动晶体管T0的源极电连接；
所述发光控制电路包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制线E1电连接，所述第五晶体管T5的漏极与高电压端电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的源极电连接；所述高电压端用于提供高电压信号VDD；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的源极与有机发光二极管O1的阳极电连接；O1的阴极与低电压端电连接，所述低电压端用于提供低电压信号VSS；
所述第二初始化电路42包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第三扫描线S3电连接，所述第七晶体管T7的漏极与所述第二初始电压端电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阳极电连接；所述第二初始电压端用于提供第二初 始电压Vi2；
所述储能电路41包括存储电容C；所述存储电容C的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C的第二端与所述高电压端连接。
在图72所示的像素电路的至少一实施例中，T1为氧化物薄膜晶体管，T2、T4、T5、T6和T7为低温多晶硅薄膜晶体管，T1为n型晶体管，T2、T4、T5、T6和T7为p型晶体管。
在图72所示的像素电路的至少一实施例中，N1为与T0的栅极电连接的第一节点，N2为与T0的源极电连接的第二节点，N3为与T0的漏极电连接的第三节点。
在图72所示的像素电路的至少一实施例中，第三扫描信号与第四扫描信号为同一扫描信号，但不以此为限。
如图73所示，本公开如图72所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段t1、数据写入阶段t3和发光阶段t4；
在初始化阶段t1，E1提供高电压信号，R1提供低电压信号，S3和S4都提供高电压信号，S1提供高电压信号，T1和T2打开，以将Vi1写入N1，使得在数据写入阶段t3开始时，T0能够打开；
在数据写入阶段t3，E1提供高电压信号，R1提供高电压信号，S3和S4都提供低电压信号，S1提供高电压信号，T7打开，以将Vi2写入O1的阳极，T1和T4打开，以将D1上的数据电压Vdata写入N2，并N1与N3之间连通；
在数据写入阶段t3开始时，T0打开，通过Vdata为C充电，以提升T0的栅极的电位，直至T0的栅极的电位变为Vdata+Vth，Vth为T0的阈值电压，T0关断；
在发光阶段t4，E1提供低电压信号，R1提供高电压信号，S3和S4都提供高电压信号，S1提供低电压信号，T5、T6和T0打开，T0驱动O1发光。
如图74所示，本公开如图72所示的像素电路的至少一实施例在工作时，当R1提供的初始化控制信号为第N-14级第四扫描信号，S4提供的第四扫描信号为第N级第四扫描信号时，显示周期可以包括先后设置的初始化阶段 t1、数据写入阶段t3和发光阶段t4；
在初始化阶段t1，E1提供高电压信号，R1提供低电压信号，S3和S4都提供高电压信号，S1提供高电压信号，T1和T2打开，以将Vi1写入N1，使得在数据写入阶段t3开始时，T0能够打开；
在数据写入阶段t3，E1提供高电压信号，R1提供高电压信号，S3和S4都提供低电压信号，S1提供高电压信号，T7打开，以将Vi2写入O1的阳极，T1和T4打开，以将D1上的数据电压Vdata写入N2，并N1与N3之间连通；
在数据写入阶段t3开始时，T0打开，通过Vdata为C充电，以提升T0的栅极的电位，直至T0的栅极的电位变为Vdata+Vth，Vth为T0的阈值电压，T0关断；
在发光阶段t4，E1提供低电压信号，R1提供高电压信号，S3和S4都提供高电压信号，S1提供低电压信号，T5、T6和T0打开，T0驱动O1发光。
如图74所示，所述初始化阶段t1与所述数据写入阶段t3之间的时间间隔较大，以能够提前对N1的电位进行复位，利于改善T0的磁滞现象。
如图75所示，在图66所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述补偿控制电路12包括第一晶体管T1；所述驱动电路11包括驱动晶体管T0；
所述第一晶体管T1的栅极与所述第一扫描线S1电连接，所述第一晶体管T1的漏极与所述驱动晶体管T0的栅极电连接，所述第一晶体管T1的源极与所述驱动晶体管T1的漏极电连接；
所述第一初始化电路13包括第二晶体管T2；
所述第二晶体管T2的栅极与所述初始化控制线R1电连接，所述第二晶体管T2的漏极与所述第一初始电压端电连接所述第二晶体管T2的源极与所述驱动晶体管T0的第一极电连接；所述第一初始电压端用于提供第一初始电压Vi1；
所述复位电路20包括第三晶体管T3；
所述第三晶体管T3的栅极与所述第二扫描线S2电连接，所述第三晶体 管T3的漏极与所述复位电压端DR电连接，所述第三晶体管T3的源极与所述驱动晶体管T0的第二极电连接；
所述数据写入电路43包括第四晶体管T4；
所述第四晶体管T4的栅极与所述第四扫描线S4电连接，所述第四晶体管T4的漏极与所述数据线D1电连接，所述第四晶体管T4的源极与驱动晶体管T0的第二极电连接；
所述发光控制电路44包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制线E1电连接，所述第五晶体管T5的漏极与高电压端电连接，所述第五晶体管T5的源极与所述驱动晶体管T0的第二极电连接；所述高电压端用于提供高电压信号VDD；
所述第六晶体管T6的栅极与所述发光控制线E1电连接，所述第六晶体管T6的漏极与所述驱动晶体管T0的第一极电连接，所述第六晶体管T6的源极与有机发光二极管O1的阳极电连接；O1的阴极与低电压端电连接，所述低电压端用于提供低电压信号VSS；
所述第二初始化电路42包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第三扫描线S3电连接，所述第七晶体管T7的漏极与所述第二初始电压端电连接，所述第七晶体管T7的源极与所述有机发光二极管O1的阳极电连接；所述第二初始电压端用于提供第二初始电压Vi2；
所述储能电路41包括存储电容C；所述存储电容C的第一端与所述驱动晶体管T0的栅极电连接，所述存储电容C的第二端与所述高电压端连接。
在图75所示的像素电路的至少一实施例中，T1为氧化物薄膜晶体管，T2、T3、T4、T5、T6和T7为低温多晶硅薄膜晶体管，T1为n型晶体管，T2、T3、T4、T5、T6和T7为p型晶体管。
在图75所示的像素电路的至少一实施例中，N1为与T0的栅极电连接的第一节点，N2为与T0的第二极电连接的第二节点，N3为与T0的第一极电连接的第三节点。
在图75所示的像素电路的至少一实施例中，T0的第一极可以为漏极，T0的第一极可以为源极；或者，T0的第一极可以为源极，T0的第二极可以为漏极。
本公开如图75所示的像素电路的至少一实施例中，R1提供的初始化控制信号可以为第N-14级第四扫描信号，S4提供的第四扫描信号可以为第N级第四扫描信号，但不以此为限。
如图76所示，本公开如图75所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段t1、复位阶段t2、数据写入阶段t3和发光阶段t4；
在初始化阶段t1，E1提供高电压信号，S1提供高电压信号，R1提供低电压信号，S2和S3都提供高电压信号，S4提供高电压信号，T1和T2打开，以将Vi1写入N1，以使得在数据写入阶段t3开始时，T0能够打开；
在复位阶段t2，E1提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2和S3都提供低电压信号，S4提供高电压信号，T3和T7打开，以通过DR提供的高电压为N2的电位进行初始化，以对T0的栅源电压进行复位，利于T0的恢复速度加快，因此会改善T0的磁滞现象，提升磁滞恢复速度；将Vi2写入O1的阳极，以使得O1不发光，并清除O1的阳极残留的电荷；T1打开，T2关断，T5和T6关断；
在数据写入阶段t3，E1提供高电压信号，S1提供高电压信号，R1提供高电压信号，S2和S3都提供高电压信号，S4提供低电压信号，T1和T4打开，以将Vdata写入N2，并N1和N3之间连通，以通过D1上的数据电压Vdata为C充电，提升N1的电位，直至T0关断，此时T0的栅极的电位为Vdata+Vth；
在发光阶段t4，E1提供低电压信号，S1提供低电压信号，R1提供高电压信号，S2和S3都提供高电压信号，S4提供高电压信号，T5、T6和T0打开，T0驱动O1发光。
本公开至少一实施例所述的驱动方法，应用于上述的像素电路，显示周期包括初始化阶段和复位阶段；所述驱动方法包括：
在所述初始化阶段，第一初始化电路在初始化控制信号的控制下，将第一初始电压写入驱动电路的第一端；
在所述复位阶段，复位电路在第二扫描信号的控制下，将复位电压写入所述驱动电路的第二端或所述驱动电路的第一端。
在本公开所述的驱动方法的至少一实施例中，复位电路在第二扫描信号的控制下，在数据电压写入驱动电路的第二端之前，在非发光时间段，将复位电压写入驱动电路的第二端或驱动电路的第一端，以对驱动电路中的驱动晶体管提供偏压(此时驱动晶体管的栅极电位也被初始化为Vi1)，使得驱动晶体管保持复位状态，以改善驱动晶体管的磁滞，利于显示屏FFR(第一帧响应时间)。
在本公开至少一实施例中，当在复位阶段，所述复位电路在第二扫描信号的控制下，将复位电压写入驱动电路的第二端时，
所述复位电压为高电位恒定电压，所述第一初始电压为低电位恒定电压，所述初始化阶段和所述复位阶段为不同的时间段；或者，
所述复位电压为和所述第一初始电压为低电位恒定电压，所述初始化阶段和所述复位阶段为相同的时间段或不同的时间段。
可选的，当在复位阶段，所述复位电路在第二扫描信号的控制下，将复位电压写入驱动电路的第一端时，所述复位阶段与所述初始化阶段为不同的时间段，以便在初始化阶段，将第一初始化电压写入驱动电路的第一端，在复位阶段，将复位电压写入驱动电路的第一端。
在具体实施时，所述像素电路还可以包括补偿控制电路，所述驱动方法还可以包括：
在所述初始化阶段，所述补偿控制电路在第一扫描信号的控制下，控制驱动电路的控制端与所述驱动电路的第一端之间连通，以将第一初始电压写入所述驱动电路的控制端。
在本公开实施例所述的驱动方法中，补偿控制电路在第一扫描信号的控制下，控制驱动电路的控制端与所述驱动电路的第一端之间连通，所述驱动 电路的控制端仅直接与补偿控制电路电连接，第一初始化电路在初始化控制信号的控制下，将第一初始电压写入驱动电路的第一端，第一初始化电路直接与所述驱动电路的第一端电连接，以通过补偿控制电路和第一初始化电路为驱动电路的控制端的电位进行初始化，减少对所述驱动电路的控制端的漏电路径，在像素电路设计复杂性没有明显增加的条件下，可以保证第一节点的电压的稳定性，利于提升显示质量，提升显示均一性，减轻Flicker(闪烁)。
在具体实施时，所述像素电路还包括数据写入电路和储能电路；显示周期还包括设置于所述初始化阶段之后的数据写入阶段；所述驱动方法还包括：
在所述数据写入阶段，数据写入电路在第四扫描信号的控制下，将数据线提供的数据电压Vdata写入所述驱动电路的第二端；补偿控制电路在第一扫描信号的控制下，控制驱动电路的控制端与所述驱动电路的第一端之间连通；
在所述数据写入阶段开始时，所述驱动电路在其控制端的控制下，导通所述驱动电路的第一端与所述驱动电路的第二端之间的连接，以通过数据电压Vdata向储能电路充电，从而改变所述驱动电路的控制端的电位，直至所述驱动电路的控制端的电位变为Vdata+Vth，Vth为所述驱动电路包括的驱动晶体管的阈值电压。
在具体实施时，所述数据写入阶段可以设置于所述复位阶段之后。
可选的，所述初始化阶段与所述数据写入阶段之间的时间间隔大于预定时间间隔，以通过对驱动晶体管的栅极电位提前初始化，改善驱动晶体管的磁滞现象，降低像素电路的高低频Flicker(闪烁)。
在本公开至少一实施例中，所述像素电路还包括发光控制电路，所述显示周期还包括设置于所述数据写入阶段之后的发光阶段；所述驱动方法包括：
在发光阶段，发光控制电路在发光控制信号的控制下，控制第一电压端与所述驱动电路的第二端之间连通，控制所述驱动电路的第一端与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
本公开至少一实施例所述的显示装置包括上述的像素电路。
可选的，所述像素电路包括复位电路和第二初始化电路；所述显示装置还包括第二扫描信号生成模组和第三扫描信号生成模组；
所述复位电路与第二扫描线电连接，所述第二初始化电路与第三扫描线电连接；
所述第二扫描信号生成模组与所述第二扫描线电连接，用于提供第二扫描信号至所述第二扫描线；
所述第三扫描信号生成模组与所述第三扫描线电连接，用于提供第三扫描信号至所述第三扫描线。
可选的，所述第二扫描信号和所述第三扫描信号为同一控制信号；
所述第二扫描信号生成模组与所述第三扫描信号生成模组为同一模组。
如图77所示，本公开至少一实施例所述的显示装置包括显示面板，所述显示面板包括像素模组P0，所述像素模组P0包括多行多列上述的像素电路；所述像素模组P0设置于显示面板的有效显示区域内；
所述显示面板还包括发光控制信号生成模组70、第一扫描信号生成模组71、第一个第四扫描信号生成模组721、第二个第四扫描信号生成模组722、第二扫描信号生成模组73和第三扫描信号生成模组74；
所述发光控制信号生成模组70用于提供发光控制信号，第一扫描信号生成模组71用于提供第一扫描信号，第一个第四扫描信号生成模组721和第二个第四扫描信号生成模组722用于提供第四扫描信号，所述第二扫描信号生成模组73用于提供第二扫描信号，所述第三扫描信号生成模组74用于提供第三扫描信号；
发光控制信号生成模组70、第一扫描信号生成模组71和第一个第四扫描信号生成模组721设置于所述显示面板左侧边，
第二个第四扫描信号生成模组722、第二扫描信号生成模组73和第三扫描信号生成模组74设置于所述显示面板右侧边。
如图78所示，本公开至少一实施例所述的显示装置包括显示面板，所述显示面板包括像素模组P0，所述像素模组P0包括多行多列上述的像素电路； 所述像素模组P0设置于显示面板的有效显示区域内；
所述显示面板还包括发光控制信号生成模组70、第一个第一扫描信号生成模组711、第二个第一扫描信号生成模组712、第一个第四扫描信号生成模组721、第二个第四扫描信号生成模组722和第三扫描信号生成模组74；
所述发光控制信号生成模组70用于提供发光控制信号，第一扫描信号生成模组71用于提供第一扫描信号，第一个第四扫描信号生成模组721和第二个第四扫描信号生成模组722用于提供第四扫描信号，所述第三扫描信号生成模组74用于提供第二扫描信号和第三扫描信号；
发光控制信号生成模组70、第一个第一扫描信号生成模组711和第一个第四扫描信号生成模组721设置于所述显示面板左侧边，
第二个第四扫描信号生成模组722、第二个第一扫描信号生成模组712和第三扫描信号生成模组74设置于所述显示面板右侧边。
在图77和图78中，标号为Vi1的为第一初始化电压，标号为Vi2的为第二初始化电压，标号为VDD的为高电压信号，标号为D1的为数据线，标号为DR的为复位电压端。
本公开实施例中，参考图6，图7，图12，图14等，第八晶体管T8的宽长比W/L可以大致等于第七晶体管T7的宽长比W/L；又例如，第八晶体管T8的宽长比W/L可以大于第七晶体管T7的宽长比W/L，也即是T8的宽长比W/L可以稍大，如此可以使得N2节点得到快速复位。
本公开实施例中，参考图6，图7，图12，图14等，第八晶体管T8的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等；第七晶体管T7的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。
需要说明的是，参考图38a、图50等，上述晶体管的设计，同样适用图38a等实施例中的第七晶体管T7，以及第一薄体管T1；以及图50等实施例中的第四晶体管T4以及第七晶体管T7。
本公开实施例中，参考图6，图7，图12，图14等，第八晶体管T8的宽长比W/L可以大致等于第一晶体管T1的宽长比W/L；又例如，第八晶体管T8的宽长比W/L可以小于第一晶体管T1的宽长比W/L，如此可以平衡N1节点和N2节点复位能力。
本公开实施例中，参考图6，图7，图12，图14等，第八晶体管T8的宽长比W/L可以大于第一晶体管T1的宽长比W/L，如此可以提升N2节点复位能力。
本公开实施例中，参考图6，图7，图12，图14等，第八晶体管T8的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等；第一晶体管T1的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。
需要说明的是，参考图50等，上述晶体管的设计，同样适用图50等实施例中的第四晶体管T4以及第三晶体管T3。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，图1-图78所示的所有实施例中，功能模块/电学器件的名称和标号并不限定该功能模块/电学器件的具体功能。例如，图3-26中的驱动电路1、图27-45中的驱动子电路、图46-60中的驱动电路11、图61-48中的驱动电路11均具有相同的功能；再例如，图3-26中的第二复位电路3、图27-45中的第二复位子电路、图46-60中的复位电路20、图61-48中的复位电路20均具有相同的功能；再例如，图3-26中的第三复位电路4、图27-45中的第一复位子电路、图46-60中的第二初始化电路32、图60-78中的第二初始化电路42均具有相同的功能；再例如，图3-26中的阈值补偿电路8、图27-45中的第二晶体管T2、图46-60中的补偿控制电路13、补偿控制电路12均具有相同的功能；再例如，图3-26中的数据写入电路7、图27-45中的写入子电路、图46-60中的数据写入电路41、图60-78中的数据写入电路43均具有相同的功能；再例如，图3-26中的控制电路5、图27-45中的第一发 光控制子电路和第二发光控制子电路、图46-60中的发光控制电路31、图61-78中的发光控制电路44均具有相同的功能；再例如，图3-26中的耦合电路6、图27-45中的第一电容C1、图46-60中的储能电路42、图61-78中的储能电路41均具有相同的功能；再例如，图3-26中的驱动晶体管T3、图27-45中的驱动晶体管T3、图46-60中的驱动晶体管T0、图61-78中的驱动晶体管T0均具有相同的功能。上述具有相同功能的功能模块/电学器件可以相互替换以组成新的实施例，其中，功能模块/电学器件的替换可以包括功能模块/电学器件自身结构的替换、功能模块/电学器件连接的信号端的电压状态的替换。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (20)

  1. 一种像素电路，其特征在于，包括：驱动子电路、第一复位子电路、第二复位子电路和发光元件，其中：
    所述驱动子电路被配置为响应于第一节点的控制信号，在所述驱动子电路的第一极和第二极之间产生驱动电流；
    所述第一复位子电路被配置为响应于第一发光控制信号线或者第二复位控制信号线的信号，向所述发光元件的阳极端写入第一复位信号；
    所述第二复位子电路被配置为响应于第一复位控制信号线的信号，向所述驱动子电路的第一极或第二极写入第二复位信号；
    所述第二复位信号大于所述第一复位信号。
  2. 根据权利要求1所述的像素电路，其特征在于，所述第二复位信号的绝对值大于所述驱动子电路的阈值电压的1.5倍。
  3. 根据权利要求1所述的像素电路，其特征在于，所述第二复位信号的幅值大于0。
  4. 根据权利要求1所述的一种像素电路，其特征在于，还包括：写入子电路、补偿子电路、第一发光控制子电路和第二发光控制子电路，其中：
    所述写入子电路被配置为响应于第二扫描信号线的信号，向第二节点写入数据信号；
    所述补偿子电路被配置为响应于第一扫描信号线的信号，将第三节点的第一复位信号或第二复位信号写入第一节点；还被配置为响应于所述第一扫描信号线的信号，对所述第一节点进行补偿；
    所述第一发光控制子电路被配置为响应于所述第一发光控制信号线的信号，向所述第二节点提供第一电源线的信号；
    所述第二发光控制子电路被配置为响应于第二发光控制信号线的信号，将第四节点的第一复位信号写入第三节点；还被配置为响应于所述第二发光控制信号线的信号，在所述第三节点和第四节点之间允许驱动电流通过。
  5. 根据权利要求4所述的像素电路，其特征在于，所述第二复位信号来源于以下至少之一的信号线：所述第一电源线、所述第一发光控制信号线、所述第二发光控制信号线或者第三电源线。
  6. 根据权利要求4所述的像素电路，其特征在于，所述第一复位控制信号线的信号的脉冲宽度与所述第二扫描信号线的信号的脉冲宽度大致相同。
  7. 根据权利要求4所述的像素电路，其特征在于，所述第一发光控制信号线的信号脉冲与所述第二发光控制信号线的信号脉冲相差一个或两个时间单元，一个所述时间单元为一行子像素扫描的时间。
  8. 根据权利要求4所述的像素电路，其特征在于，所述第一复位子电路包括第一晶体管，其中：
    所述第一晶体管的控制极与所述第一发光控制信号线或者第二复位控制信号线连接，所述第一晶体管的第一极与第一复位信号线连接，所述第一晶体管的第二极与所述第四节点连接。
  9. 根据权利要求4所述的像素电路，其特征在于，所述补偿子电路包括第二晶体管和第一电容，其中：
    所述第二晶体管的控制极与所述第一扫描信号线连接，所述第二晶体管的第一极与第三节点连接，所述第二晶体管的第二极与所述第一节点连接；
    所述第一电容的一端与所述第一节点连接，所述第一电容的另一端与所述第一电源线连接。
  10. 根据权利要求4所述的像素电路，其特征在于，所述驱动子电路包括第三晶体管，其中：
    所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与第二节点连接，所述第三晶体管的第二极与所述第三节点连接。
  11. 根据权利要求4所述的像素电路，其特征在于，所述写入子电路包括第四晶体管，其中：
    所述第四晶体管的控制极与所述第二扫描信号线连接，所述第四晶体管 的第一极与数据信号线连接，所述第四晶体管的第二极与所述第二节点连接。
  12. 根据权利要求4所述的像素电路，其特征在于，所述第一发光控制子电路包括第五晶体管，其中：
    所述第五晶体管的控制极与所述第一发光控制信号线连接，所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与所述第二节点连接。
  13. 根据权利要求4所述的像素电路，其特征在于，所述第二发光控制子电路包括第六晶体管，其中：
    所述第六晶体管的控制极与所述第二发光控制信号线连接，所述第六晶体管的第一极与第三节点连接，所述第六晶体管的第二极与所述第四节点连接。
  14. 根据权利要求4所述的像素电路，其特征在于，所述第二复位子电路包括第七晶体管，其中：
    所述第七晶体管的控制极与所述第一复位控制信号线连接，所述第七晶体管的第一极与第二复位信号线连接，所述第七晶体管的第二极与所述第二节点或所述第三节点连接。
  15. 根据权利要求4所述的像素电路，其特征在于，所述第一复位子电路包括第一晶体管，所述补偿子电路包括第二晶体管和第一电容，所述驱动子电路包括第三晶体管，所述写入子电路包括第四晶体管，所述第一发光控制子电路包括第五晶体管，所述第二发光控制子电路包括第六晶体管，所述第二复位子电路包括第七晶体管，其中：
    所述第一晶体管的控制极与所述第一发光控制信号线或者第二复位控制信号线连接，所述第一晶体管的第一极与第一复位信号线连接，所述第一晶体管的第二极与所述第四节点连接；
    所述第二晶体管的控制极与所述第一扫描信号线连接，所述第二晶体管的第一极与第三节点连接，所述第二晶体管的第二极与所述第一节点连接；
    所述第一电容的一端与所述第一节点连接，所述第一电容的另一端与所述第一电源线连接；
    所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与第二节点连接，所述第三晶体管的第二极与所述第三节点连接；
    所述第四晶体管的控制极与所述第二扫描信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第二节点连接；
    所述第五晶体管的控制极与所述第一发光控制信号线连接，所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与所述第二节点连接；
    所述第六晶体管的控制极与所述第二发光控制信号线连接，所述第六晶体管的第一极与第三节点连接，所述第六晶体管的第二极与所述第四节点连接；
    所述第七晶体管的控制极与所述第一复位控制信号线连接，所述第七晶体管的第一极与第二复位信号线连接，所述第七晶体管的第二极与所述第二节点或所述第三节点连接。
  16. 根据权利要求15所述的像素电路，其特征在于，所述第一晶体管、所述第二晶体管和所述第七晶体管中的至少一个为第一类型晶体管，所述第三晶体管至所述第六晶体管均为第二类型晶体管，所述第一类型晶体管与所述第二类型晶体管的晶体管类型不同。
  17. 根据权利要求16所述的像素电路，其中，所述第一类型晶体管为N型薄膜晶体管；所述第二类型晶体管为P型薄膜晶体管。
  18. 根据权利要求15所述的像素电路，其特征在于，所述第一晶体管、所述第二晶体管和所述第七晶体管中的至少一个为铟镓锌氧化物薄膜晶体管，所述第三晶体管至所述第六晶体管均为低温多晶硅薄膜晶体管。
  19. 一种显示装置，其特征在于，包括如权利要求1至18任一所述的像素电路。
  20. 一种像素电路的驱动方法，其特征在于，用于驱动如权利要求1至18任一所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，所述驱动方法包括：
    在复位阶段，第一复位子电路响应于第一发光控制信号线或者第二复位控制信号线的信号，向发光元件的阳极端写入第一复位信号；
    在重置阶段，第二复位子电路响应于第一复位控制信号线的信号，向驱动子电路的第一极或第二极写入第二复位信号；所述第二复位信号大于所述第一复位信号；
    在发光阶段，驱动子电路响应于第一节点的控制信号，在所述驱动子电路的第一极和第二极之间产生驱动电流。
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CN115023756B (zh) * 2021-07-30 2023-10-20 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
CN116935789A (zh) * 2022-03-30 2023-10-24 华为技术有限公司 像素电路及显示屏
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130026338A (ko) * 2011-09-05 2013-03-13 엘지디스플레이 주식회사 유기 발광 다이오드 표시 장치의 화소 회로
KR20150064543A (ko) * 2013-12-03 2015-06-11 삼성디스플레이 주식회사 유기전계발광 표시장치와 그 구동방법
CN107274830A (zh) * 2017-07-12 2017-10-20 上海天马有机发光显示技术有限公司 一种像素电路、其驱动方法及有机电致发光显示面板
CN109285500A (zh) * 2018-12-05 2019-01-29 武汉天马微电子有限公司 像素驱动电路和有机发光显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102093664B1 (ko) * 2012-11-20 2020-04-16 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN109599062A (zh) * 2017-09-30 2019-04-09 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN107610651B (zh) * 2017-10-31 2019-11-08 武汉天马微电子有限公司 像素电路、像素电路的驱动方法和显示面板
CN110047432B (zh) * 2019-05-30 2020-07-28 京东方科技集团股份有限公司 一种像素电路、其驱动方法、显示面板及显示装置
KR102627150B1 (ko) * 2019-10-14 2024-01-22 삼성디스플레이 주식회사 유기 발광 표시 장치의 화소, 및 유기 발광 표시 장치
KR20210050050A (ko) * 2019-10-25 2021-05-07 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
KR20210077087A (ko) * 2019-12-16 2021-06-25 삼성디스플레이 주식회사 발광 구동부 및 이를 포함하는 표시장치
KR20210095278A (ko) * 2020-01-22 2021-08-02 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN111462694B (zh) * 2020-04-20 2022-06-10 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
CN111508426B (zh) * 2020-05-29 2022-04-15 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN114999396A (zh) * 2020-08-28 2022-09-02 武汉天马微电子有限公司 显示面板及其驱动方法及显示装置
CN113160740A (zh) * 2021-04-28 2021-07-23 厦门天马微电子有限公司 显示面板和显示装置
CN113178170A (zh) * 2021-06-29 2021-07-27 深圳小米通讯技术有限公司 像素驱动电路、方法、装置及显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130026338A (ko) * 2011-09-05 2013-03-13 엘지디스플레이 주식회사 유기 발광 다이오드 표시 장치의 화소 회로
KR20150064543A (ko) * 2013-12-03 2015-06-11 삼성디스플레이 주식회사 유기전계발광 표시장치와 그 구동방법
CN107274830A (zh) * 2017-07-12 2017-10-20 上海天马有机发光显示技术有限公司 一种像素电路、其驱动方法及有机电致发光显示面板
CN109285500A (zh) * 2018-12-05 2019-01-29 武汉天马微电子有限公司 像素驱动电路和有机发光显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4300471A4 *

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