WO2022252077A1 - 发光器件、像素电路、发光基板及显示装置 - Google Patents

发光器件、像素电路、发光基板及显示装置 Download PDF

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Publication number
WO2022252077A1
WO2022252077A1 PCT/CN2021/097478 CN2021097478W WO2022252077A1 WO 2022252077 A1 WO2022252077 A1 WO 2022252077A1 CN 2021097478 W CN2021097478 W CN 2021097478W WO 2022252077 A1 WO2022252077 A1 WO 2022252077A1
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Prior art keywords
node
coupled
signal terminal
transistor
voltage
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PCT/CN2021/097478
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English (en)
French (fr)
Inventor
刘伟星
彭宽军
李小龙
滕万鹏
秦斌
陈婉芝
张方振
张春芳
徐智强
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/789,351 priority Critical patent/US20240186454A1/en
Priority to PCT/CN2021/097478 priority patent/WO2022252077A1/zh
Priority to CN202180001363.5A priority patent/CN115699322A/zh
Publication of WO2022252077A1 publication Critical patent/WO2022252077A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a light emitting device, a pixel circuit, a light emitting substrate and a display device.
  • Miniature light-emitting diodes (English: Light Emitting Diode; abbreviation: LED), such as Micro-LED and mini-LED, reduce the size of the LED structure by miniaturizing, arraying, and thinning.
  • organic light-emitting diodes (English: Organic Light-Emitting Diode; abbreviation: OLED)
  • micro-light-emitting diodes have the advantages of high brightness, high luminous efficiency, and low power consumption
  • micro-light-emitting diodes use inorganic light-emitting materials, and their material stability Better and more reliable, it is a new generation of display technology.
  • a light emitting device in one aspect, includes a first semiconductor layer, a light-emitting functional layer and a second semiconductor layer which are stacked.
  • the first semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern.
  • the light-emitting functional layer is disposed on one of two opposite sides along the thickness direction of the first semiconductor layer, and includes a first light-emitting pattern and a second light-emitting pattern arranged at intervals.
  • the second semiconductor layer is disposed on a side of the light-emitting functional layer away from the first semiconductor layer, and includes a third semiconductor pattern and a fourth semiconductor pattern arranged at intervals.
  • Orthographic projections of the first semiconductor pattern, the first light-emitting pattern and the third semiconductor pattern on the reference plane are at least partially overlapped to form a first light-emitting portion.
  • Orthographic projections of the second semiconductor pattern, the second light-emitting pattern and the fourth semiconductor pattern on the reference plane are at least partially overlapped to form a second light-emitting portion.
  • the first semiconductor pattern and the second semiconductor pattern are electrically connected; the reference plane is a plane parallel to the first semiconductor layer.
  • the light emitting device further includes an electrode layer.
  • the electrode layer is disposed on a side of the second semiconductor layer away from the first semiconductor layer, and includes a first electrode and a second electrode arranged at intervals.
  • the first electrode is electrically connected to the third semiconductor pattern
  • the second electrode is electrically connected to the fourth semiconductor pattern.
  • the light emitting device further includes a passivation layer.
  • the passivation layer is disposed between the second semiconductor layer and the electrode layer; a first via hole and a second via hole are disposed in the passivation layer, and the first electrode passes through the first via hole
  • the hole is electrically connected to the third semiconductor pattern, and the second electrode is electrically connected to the fourth semiconductor pattern through the second via hole.
  • the light emitting device further includes at least one insulating layer and a binding electrode layer.
  • the at least one insulating layer is disposed on a side of the electrode layer away from the first semiconductor layer, and the at least one insulating layer is provided with a third via hole and a fourth via hole.
  • the binding electrode layer is disposed on the side of the at least one insulating layer away from the electrode layer, and includes a first binding electrode and a second binding electrode. The first binding electrode is electrically connected to the first electrode through the third via hole, and the second binding electrode is electrically connected to the second electrode through the fourth via hole.
  • the at least one insulating layer is further provided with at least one fifth via hole;
  • the binding electrode layer further includes a third binding electrode; the third binding electrode passes through the at least one The fifth via hole is electrically connected with the first semiconductor pattern and the second semiconductor pattern.
  • the first semiconductor pattern and the second semiconductor pattern are spaced apart.
  • the light emitting device includes at least one insulating layer and a bonding electrode layer, two fifth via holes are arranged in the at least one insulating layer, and the bonding electrode layer includes a third bonding electrode layer. electrode.
  • the third binding electrode is electrically connected to the first semiconductor pattern through one of the two fifth via holes, and the third binding electrode is connected to the second semiconductor pattern through the other of the two fifth via holes.
  • the semiconductor patterns are electrically connected.
  • the first semiconductor pattern and the second semiconductor pattern are integrated.
  • the light emitting device includes at least one insulating layer; and the at least one insulating layer includes at least one of a reflective layer, a heat dissipation layer and an encapsulation layer.
  • the light emitting device further includes a substrate.
  • the first semiconductor layer is disposed on one of two opposite sides of the substrate along the thickness direction, the first semiconductor pattern and the second semiconductor pattern are disposed on the same substrate, and the light-emitting functional layer It is disposed on the side of the first semiconductor layer away from the sinking bottom.
  • the third semiconductor pattern and the fourth semiconductor pattern are configured to transmit different voltage signals.
  • a pixel circuit configured to drive the light emitting device described in any one of the above embodiments, and includes a first control circuit and a second control circuit.
  • the first control circuit is coupled to the first scan signal terminal, the first data signal terminal, the first voltage signal terminal, and the first light-emitting part of the light-emitting device, and is configured to Under the control of the first scanning signal and the first data signal from the first data signal terminal, the line between the first voltage signal terminal and the first light emitting part is turned on, and the first light emitting part is controlled.
  • the brightness of the part switches between the first gray scale and the second gray scale.
  • the second control circuit is coupled to the first scan signal terminal, the first voltage signal terminal, and the second light emitting part of the light emitting device, and is configured to Under the control of the scanning signal, the line between the first voltage signal terminal and the second light emitting part is turned on, and the magnitude of the driving current flowing through the second light emitting part is controlled.
  • the first control circuit includes a first data writing subcircuit, a switch control subcircuit, and a first storage subcircuit.
  • the first data writing sub-circuit is coupled to the first scan signal terminal, the first data signal terminal, and the first node, and is configured to receive the first scan signal from the first scan signal terminal Under control, the first data signal from the first data signal terminal is transmitted to the first node.
  • the switch control subcircuit is coupled to the first node, the first voltage signal terminal, and the first light emitting part, and is configured to switch the first The circuit between a voltage signal terminal and the first light emitting part is conducted.
  • the first storage sub-circuit is coupled to the first voltage signal terminal and the first node, and is configured to store and maintain the voltage of the first node.
  • the first data writing sub-circuit includes a first transistor, the control electrode of the first transistor is coupled to the first scan signal terminal, and the first electrode of the first transistor is connected to the The first data signal terminal is coupled, and the second pole of the first transistor is coupled to the first node.
  • the switch control sub-circuit includes a second transistor, the control pole of the second transistor is coupled to the first node, the first pole of the second transistor is coupled to the first voltage signal terminal, and the The second pole of the second transistor is coupled to the first light emitting part.
  • the first storage sub-circuit includes a first storage capacitor, a first end of the first storage capacitor is coupled to the first node, a second end of the first storage capacitor is connected to the first voltage signal end coupling.
  • the second control circuit includes: a second data writing subcircuit, a second storage subcircuit, a first driving subcircuit, a compensation subcircuit, a voltage control subcircuit, a light emission control subcircuit, and an initialization sub-circuit.
  • the second data writing sub-circuit is coupled to the first scan signal terminal, the second data signal terminal, and the second node, and is configured to be controlled by a first scan signal from the first scan signal terminal , transmitting the second data signal from the second data signal terminal to the second node.
  • the second storage sub-circuit is coupled to the second node and the third node, and is configured to store the voltage of the second node and adjust the voltage of the third node.
  • the first driving sub-circuit is coupled to the third node, the first voltage signal terminal, and the fourth node, and is configured to, under the control of the voltage of the third node, output from the first voltage
  • the first voltage signal at the signal end is transmitted to the fourth node.
  • the compensation subcircuit is coupled to the first scan signal terminal, the fourth node, and the third node, and is configured to, under the control of the first scan signal from the first scan signal terminal,
  • the threshold voltage of the first driving sub-circuit is compensated to the third node.
  • the voltage control subcircuit is coupled to the second scan signal terminal, the second voltage signal terminal, and the second node, and is configured to, under the control of the second scan signal from the second scan signal terminal, The second voltage signal of the second voltage signal terminal is transmitted to the second node.
  • the light emission control subcircuit is coupled to the enable signal terminal, the fourth node, and the second light emitting part, and is configured to turn the first light emitting part under the control of the enable signal from the enable signal terminal The voltages of the four nodes are transmitted to the second light emitting part.
  • the initialization subcircuit is coupled to the reset signal terminal, the second voltage signal terminal, and the second node, and is configured to, under the control of the reset signal from the reset signal terminal, convert the voltage from the second voltage signal terminal to The second voltage signal is transmitted to the second node.
  • the second data writing sub-circuit includes a third transistor, the control electrode of the third transistor is coupled to the first scan signal terminal, and the first electrode of the third transistor is connected to the The second data signal terminal is coupled, and the second pole of the third transistor is coupled to the second node.
  • the second storage sub-circuit includes a second storage capacitor, the first end of the second storage capacitor is electrically connected to the second node, and the second end of the second storage capacitor is electrically connected to the third node .
  • the first driving sub-circuit includes a fourth transistor, the control electrode of the fourth transistor is coupled to the third node, and the first electrode of the fourth transistor is coupled to the first voltage signal terminal, so The second pole of the fourth transistor is coupled to the fourth node.
  • the compensation sub-circuit includes a fifth transistor, the control electrode of the fifth transistor is coupled to the first scanning signal terminal, the first electrode of the fifth transistor is coupled to the fourth node, and the first electrode of the fifth transistor is coupled to the fourth node.
  • the second poles of the five transistors are coupled to the third node.
  • the voltage control sub-circuit includes a sixth transistor, the control electrode of the sixth transistor is coupled to the second scan signal terminal, the first electrode of the sixth transistor is coupled to the second voltage signal terminal, The second pole of the sixth transistor is coupled to the second node.
  • the light emission control sub-circuit includes a seventh transistor, the control electrode of the seventh transistor is coupled to the enabling signal terminal, the first electrode of the seventh transistor is coupled to the fourth node, and the first electrode of the seventh transistor is coupled to the fourth node.
  • the second electrodes of the seven transistors are coupled to the second light emitting part.
  • the reset subcircuit includes an eighth transistor, the control electrode of the eighth transistor is coupled to the reset signal end, the first electrode of the eighth transistor is coupled to the initialization signal end, and the eighth transistor The second pole of is coupled to the second node.
  • the second control circuit includes: a feedback subcircuit, an input subcircuit, a second drive subcircuit, a third storage subcircuit and a modulation subcircuit.
  • the feedback subcircuit is coupled to the first scanning signal terminal, the feedback signal terminal, and the feedback node, and is configured to, under the control of the first scanning signal from the first scanning signal terminal, switch the feedback node to The voltage is transmitted to the feedback signal end; the feedback node is coupled with the second light emitting part.
  • the input subcircuit is coupled to the first scan signal terminal, the input signal terminal, and the fifth node, and is configured to, under the control of the first scan signal from the first scan signal terminal,
  • the input signal at the signal terminal is transmitted to the fifth node; the input signal is generated according to the voltage of the feedback node and the third data signal for controlling the gray scale of the second light emitting part.
  • the second driving sub-circuit is coupled to the fifth node, the sixth node, and the feedback node, and is configured to, under the control of the voltage of the fifth node, according to the voltage signal of the sixth node , to regulate the voltage of the feedback node.
  • the third storage sub-circuit is coupled to the first voltage signal terminal and the fifth node, and is configured to store and maintain the voltage of the fifth node.
  • the modulation subcircuit is coupled to the third scan signal terminal, the first voltage signal terminal, and the sixth node, and is configured to, under the control of the third scan signal from the third scan signal terminal, The first voltage signal from the first voltage signal terminal is transmitted to the sixth node, and modulates the conduction time of the line between the first voltage signal terminal and the second light emitting part.
  • the feedback sub-circuit includes a ninth transistor, the control electrode of the ninth transistor is coupled to the first scan signal terminal, and the first electrode of the ninth transistor is coupled to the feedback node. connected, and the second pole of the ninth transistor is coupled to the feedback signal terminal.
  • the input sub-circuit includes a tenth transistor, the control electrode of the tenth transistor is coupled to the first scanning signal end, the first electrode of the tenth transistor is coupled to the input signal end, and the first The second pole of the ten-transistor is coupled to the fifth node.
  • the second driving sub-circuit includes an eleventh transistor, the control electrode of the eleventh transistor is coupled to the fifth node, and the first electrode of the eleventh transistor is coupled to the sixth node, The second pole of the eleventh transistor is coupled to the feedback node.
  • the third storage sub-circuit includes a third capacitor, a first terminal of the third capacitor is coupled to the first voltage signal terminal, and a second terminal of the third capacitor is coupled to the fifth node.
  • the modulation sub-circuit includes a twelfth transistor, the control electrode of the twelfth transistor is coupled to the third scanning signal terminal, and the first electrode of the twelfth transistor is coupled to the first voltage signal terminal. connected, the second pole of the twelfth transistor is coupled to the sixth node.
  • a light emitting substrate in yet another aspect, includes a driving backplane and the light-emitting device described in any one of the above embodiments.
  • the driving backplane includes a plurality of pixel circuits described in any one of the above-mentioned embodiments.
  • the first control circuit of each pixel circuit is coupled to the first light emitting part of one light emitting device, and the second control circuit of each pixel circuit is coupled to the second light emitting part of one light emitting device.
  • the second control circuit of the pixel circuit includes a feedback subcircuit, an input subcircuit, a second drive subcircuit, a third storage subcircuit, and a modulation subcircuit.
  • the light-emitting substrate further includes: a circuit board coupled to the driving backplane, and the circuit board includes a third control circuit.
  • the third control circuit includes a comparison subcircuit and a signal conversion subcircuit.
  • the comparison subcircuit is coupled to the third data signal terminal, the feedback signal terminal, and the seventh node, and is configured to compare the voltage of the feedback node transmitted by the feedback signal terminal with the third voltage from the third data signal terminal. data signal, and output a regulated voltage to the seventh node according to the comparison result.
  • the signal conversion sub-circuit is coupled to the seventh node, a ground voltage terminal, and an input signal terminal, and is configured to transmit to the input signal terminal according to the adjusted voltage of the seventh node and the voltage of the ground voltage terminal Transmits the input signal.
  • the third data signal terminal is configured to transmit a third data signal for controlling the gray scale of the second light emitting part.
  • the comparison subcircuit includes a first amplifier, the first amplifier includes a first positive input terminal, a first negative input terminal and a first output terminal, and the first positive input terminal is connected to The feedback signal terminal is coupled, the first negative input terminal is coupled to the third data signal terminal, and the first output terminal is coupled to the seventh node.
  • the signal conversion sub-circuit includes a second amplifier and a fourth capacitor.
  • the second amplifier has a second positive input terminal, a second negative input terminal and a second output terminal, the second positive input terminal is coupled to the ground voltage terminal, and the second negative input terminal Coupled with the seventh node, the second output terminal is coupled with the signal input terminal.
  • One terminal of the fourth capacitor is coupled to the second negative input terminal, and a second terminal of the fourth capacitor is coupled to the second output terminal.
  • the comparison subcircuit further includes a first resistor, one end of the first resistor is electrically connected to the first positive input end, and two ends of the first resistor are electrically connected to the first negative input end. Electrically connected to the input.
  • the signal conversion sub-circuit also includes a second resistor and a third resistor. One end of the second resistor is electrically connected to the seventh node, and two ends of the second resistor are electrically connected to the second negative input end. One end of the third resistor is electrically connected to the ground voltage end, and two ends of the third resistor are electrically connected to the second positive input end.
  • a display device in yet another aspect, includes the light-emitting substrate described in any one of the above embodiments.
  • FIG. 1 is a schematic diagram of a display device according to some embodiments.
  • Fig. 2 is a sectional view along A-A in Fig. 1;
  • Fig. 3 is a relationship diagram between luminous efficiency and current density of a light emitting device
  • Fig. 4A is a partial enlarged view of B in Fig. 1;
  • Fig. 4B is another partial enlarged view of B in Fig. 1;
  • Figure 5A is a sectional view along C-C in Figure 4A;
  • Figure 5B is a sectional view along D-D in Figure 4B;
  • FIG. 6 is a structural block diagram of a pixel circuit according to some embodiments.
  • FIG. 7 is a structural block diagram of a first control circuit according to some embodiments.
  • FIG. 8 is a block diagram of a first control circuit according to some embodiments.
  • FIG. 9 is a structural block diagram of a second control circuit according to some embodiments.
  • FIG. 10 is a block diagram of a second control circuit according to some embodiments.
  • FIG. 11 is a structural diagram of a pixel circuit according to some embodiments.
  • FIG. 12 is a control timing diagram of a pixel circuit according to some embodiments.
  • FIG. 13 is a structural block diagram of a second control circuit and a third control circuit according to some embodiments.
  • Fig. 14 is another structural diagram of a pixel circuit according to some embodiments.
  • FIG. 15 is another control timing diagram of a pixel circuit according to some embodiments.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the term “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B, and C includes the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and A , a combination of B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the transistors used in the pixel circuit provided by the embodiments of the present disclosure may be thin film transistors (English: Thin Film Transistor; TFT for short), field effect transistors (English: metal oxide semiconductor; MOS for short), or other switching devices with the same characteristics.
  • the embodiments of the present disclosure all take the thin film transistor as an example for illustration.
  • the thin film transistor can be a P-type transistor or an N-type transistor.
  • the P-type transistor is turned on under the action of a low potential and turned off under the action of a high potential; the N-type transistor is turned on under the action of a high potential and turned off under the action of a low potential.
  • a P-type transistor is taken as an example for illustration.
  • the control electrode of each thin film transistor used in the pixel circuit is the gate of the thin film transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor may be symmetrical in structure, there may be no difference in structure between the source and drain, that is to say, the first electrode of the thin film transistor in the embodiment of the present disclosure There may be no difference in structure from the second pole. Exemplarily, the first pole of the thin film transistor is the source, and the second pole is the drain.
  • the first node, the second node, etc. in the pixel circuit do not represent actual components, but represent the confluence points of relevant electrical connections in the circuit diagram, that is, these nodes are equivalent to the confluence points of relevant electrical connections in the circuit diagram formed node.
  • Some embodiments of the present disclosure provide a display device 1000.
  • wearable devices augmented reality (English: Augmented Reality; abbreviation: AR) equipment, virtual reality (English: Virtual Reality; abbreviation: VR) equipment and any other products or components with display functions.
  • augmented reality English: Augmented Reality; abbreviation: AR
  • virtual reality English: Virtual Reality; abbreviation: VR
  • the display device 1000 includes a light emitting substrate 1100, and the light emitting substrate 1100 can be used as a backlight source or directly used for displaying images.
  • FIG. 2 is a cross-sectional view of a light emitting device taken along A-A in FIG. 1 ;
  • the driving backplane 200 includes a plurality of pixel circuits 300 for driving the light emitting device 100 to emit light, wherein each pixel circuit 300 drives one light emitting device 100 .
  • multiple light-emitting devices 100 can emit light of the same color (approximately the same wavelength), and a color conversion layer (such as a color filter structure layer) can be provided on the light-emitting side of the light-emitting substrate 1100 to emit light.
  • the light emitted by the device 100 is mixed by the color conversion layer to form the desired displayed color.
  • the plurality of light-emitting devices 100 can emit light of different colors, so that the light-emitting substrate 1100 can display images with colors.
  • the plurality of light emitting devices 100 may include a first light emitting device emitting red light, a second light emitting device emitting green light, and a third light emitting device emitting blue light.
  • the display device 1000 may be a display device including miniature light-emitting devices (such as: mini-LED or Micro LED).
  • micro light emitting devices miniature light emitting diodes
  • the specific performance is: when the current density (driving current) input to the micro light emitting device reaches a certain value, the luminous efficiency of the micro light emitting device reaches the highest; when the current density does not reach this value, the luminous efficiency of the micro light emitting device has been in the climbing stage , that is, with the increase of the supplied driving current, the luminous brightness of the micro light-emitting device gradually increases, and at the same time, the luminous efficiency gradually increases.
  • each light-emitting device includes a light-emitting part, that is, each light-emitting device includes a light-emitting area, and the pixel circuit controls the gray scale (brightness) displayed by the light-emitting part by controlling the magnitude of the driving current flowing through the light-emitting part. ).
  • the light-emitting device displays low grayscale, the driving current flowing through the light-emitting device is small, the current density is small, and the luminous efficiency is low.
  • the light emitting device 100 includes a first semiconductor layer 120, a light emitting functional layer 130 and a second semiconductor layer 140 stacked.
  • the first semiconductor layer 120 includes first semiconductor patterns 121 and second semiconductor patterns 122 .
  • the luminescent functional layer 130 is disposed on one side of the opposite sides along the thickness direction M1 (vertical direction in FIG. 5A ) of the first semiconductor layer 120 (in FIG. the upper side of the semiconductor layer 120).
  • the light-emitting functional layer 130 includes a first light-emitting pattern 131 and a second light-emitting pattern 132 arranged at intervals, that is, there is an interval between the first light-emitting pattern 131 and the second light-emitting pattern 132, so that the first light-emitting pattern 131 and the second light-emitting pattern 132 It is possible to form two independent light-emitting areas.
  • the second semiconductor layer 140 is disposed on the side of the light-emitting functional layer 130 away from the first semiconductor layer 120, and includes a third semiconductor pattern 141 and a fourth semiconductor pattern 142 arranged at intervals, that is, between the third semiconductor pattern 141 and the fourth semiconductor pattern 142. These are electrically insulated so that the third semiconductor pattern 141 and the fourth semiconductor pattern 142 can transmit different voltage signals.
  • the first semiconductor layer 120 can be an N-type semiconductor layer (N-GaN)
  • the second semiconductor layer 140 can be a P-type semiconductor layer (P-GaN)
  • a PN junction is formed between the second semiconductor pattern 122 and the fourth semiconductor layer 142 .
  • the light-emitting functional layer 130 can be a multiple quantum well (English: Multiple Quantum Well; abbreviation: MQW), in the case of forming a PN junction with a potential barrier between the first semiconductor layer and the second semiconductor layer, the minority carriers and the majority When carriers recombine, excess energy is released in the form of light, thereby directly converting electrical energy into light energy.
  • MQW Multiple Quantum Well
  • Orthographic projections of the first semiconductor pattern 121 , the first light-emitting pattern 131 and the third semiconductor pattern 141 on the reference plane at least partially overlap to form the first light-emitting portion D1 .
  • the orthographic projections of the second semiconductor pattern 122 , the second light emitting pattern 132 and the fourth semiconductor pattern 142 on the reference plane are at least partially overlapped to form the second light emitting portion D2 .
  • the reference plane is a plane parallel to the first semiconductor layer 120 .
  • the first light-emitting part D1 works (lights), it needs to input a voltage signal on the first semiconductor pattern 121 and the third semiconductor pattern 141 respectively, and the voltage signal input on the first semiconductor pattern 121 is different from that input on the third semiconductor pattern 141.
  • the voltage signal has a voltage difference.
  • the second light emitting part D2 it is necessary to input a voltage signal on the second semiconductor pattern 122 and the fourth semiconductor pattern 142 respectively, and the voltage signal input on the second semiconductor pattern 122 and the voltage signal input on the fourth semiconductor pattern 142 have a voltage difference.
  • a negative voltage can be input to each of the first semiconductor pattern 121 and the second semiconductor pattern 122, A positive voltage is input to each of the third semiconductor pattern 141 and the fourth semiconductor pattern 142 .
  • the same or different voltage signals can be input to the third semiconductor pattern 141 and the fourth semiconductor pattern 142, that is, the third semiconductor pattern 141 and the first semiconductor pattern
  • the voltage difference between the patterns 121 can be the same as or different from the voltage difference between the fourth semiconductor pattern 142 and the second semiconductor pattern 122, and the first light emitting part D1 and the second light emitting part D2 can work independently to display different gray scales. .
  • the light-emitting device 100 displays a low gray scale
  • one of the first light-emitting part D1 and the second light-emitting part D2 can be controlled to work, and the other can not work, that is, through one light-emitting part (the first light-emitting part D1 or the second light-emitting part D1
  • the second light emitting portion D2) displays low gray scales, so that the light emitting area of the light emitting device 100 when displaying low gray scales can be reduced.
  • the light emitting device 100 provided by the embodiments of the present disclosure has a smaller light emitting area. In order to enable the light emitting device 100 to display the same low gray scale, it is necessary to increase the current of the working light emitting part size, thereby increasing the current density of the light-emitting part and improving the luminous efficiency.
  • the first light emitting part D1 can be controlled to emit light, and the second light emitting part D2 can not emit light.
  • the overall light emitting area of the light emitting device 100 can be reduced, and by increasing the first light emitting The current in the portion D1 makes the light emitting device 100 display a corresponding gray scale, thereby increasing the current density of the first light emitting portion D1 and increasing the luminous efficiency of the first light emitting portion D1.
  • the first light emitting part D1 and the second light emitting part D2 work simultaneously, wherein the first light emitting part D1 and the second light emitting part D2 can display the same gray scale or different gray scales.
  • the first light-emitting part D1 can display grayscales of 0-127, while the second light-emitting part D2 can only display grayscales of 0 and grayscale 127. order.
  • the first light-emitting part D1 works independently, and the second light-emitting part D2 does not work, that is, the second light-emitting part D2 displays a gray scale of 0.
  • the current is used to adjust the gray scale displayed by the first light emitting part D1 , and further adjust the gray scale displayed by the light emitting device 100 .
  • the first light emitting part D1 and the second light emitting part D2 work simultaneously, and the second light emitting part D2 displays 127 gray scales. In this way, by adjusting the gray scale displayed by the first light emitting part D1 , to adjust the gray scale displayed by the light emitting device 100 .
  • the first semiconductor pattern 121 and the second semiconductor pattern 122 are electrically connected, and the third semiconductor pattern 141 and the fourth semiconductor pattern 142 are configured to transmit different voltage signals.
  • the first light-emitting part D1 and the second light-emitting part D2 can work independently, and the light-emitting device 100 can display low grayscale when one light-emitting part works, and display high gray-scale when the two light-emitting parts work together.
  • the light emitting device 100 further includes a substrate 110 .
  • the first semiconductor layer 120 is disposed on one of the opposite sides of the substrate 110 along the thickness direction M1, the first semiconductor pattern 121 and the second semiconductor pattern 122 are disposed on the same substrate 110, and the light-emitting functional layer 130 is located on the first The side of the semiconductor layer 120 away from the substrate 110 , that is, the substrate 110 is disposed on the side of the first semiconductor layer 120 away from the light-emitting functional layer 130 .
  • the first light emitting part D1 and the second light emitting part D2 belong to the same light emitting device 100, and both the first light emitting part D1 and the second light emitting part D2 are arranged on the same substrate 110, and one light emitting device 100 has two light emitting devices that can work independently. of the luminous department.
  • the substrate 110 can be a sapphire (aluminum oxide, chemical formula: Al 2 O 3 ) substrate, a silicon carbide (chemical formula: SiC) substrate, a silicon (chemical formula: Si) substrate, a gallium phosphide (chemical formula: GaP) substrate , or gallium arsenide (chemical formula: GaAs) substrate.
  • a sapphire aluminum oxide, chemical formula: Al 2 O 3
  • SiC silicon carbide
  • Si silicon
  • GaP gallium phosphide
  • GaAs gallium arsenide
  • the first semiconductor layer 120, the light-emitting functional layer 130, and the second semiconductor layer 140 are sequentially formed on the substrate 110 through the epitaxial process, and then the second semiconductor layer 140 is fabricated.
  • Other film layers form the light emitting device 100 .
  • the substrate 110 can be peeled off (for example, when the light-emitting substrate 1100 is formed by Micro LED, the substrate 110 can be peeled off), or the substrate 110 can be kept.
  • the bottom 110 for example, when the light-emitting substrate 1100 is formed by Mini-LED, the substrate 110 can be kept).
  • the light emitting device 100 further includes an electrode layer 150 .
  • the electrode layer 150 is disposed on the side of the second semiconductor layer 140 away from the first semiconductor layer 120 , and includes a first electrode 151 and a second electrode 152 arranged at intervals, that is, the first electrode 151 and the second electrode 152 are electrically insulated.
  • the first electrode 151 is electrically connected to the third semiconductor pattern 141 and configured to transmit a voltage signal to the third semiconductor pattern 141 .
  • the second electrode 152 is electrically connected to the fourth semiconductor pattern 142 and configured to transmit a voltage signal to the fourth semiconductor pattern 142 .
  • the electrode layer 150 may be a transparent conductive layer, for example, the electrode layer 150 may be an indium tin oxide (English: Indium tin oxide; ITO for short) layer.
  • the light emitting device 110 further includes a passivation layer 160 .
  • the passivation layer 160 is disposed between the second semiconductor layer 140 and the electrode layer 150, and the passivation layer 160 is provided with a first via hole 161 and a second via hole 162, and the first electrode 151 passes through the first via hole 161 and the third via hole 161.
  • the semiconductor pattern 141 is electrically connected, and the second electrode 152 is electrically connected to the fourth semiconductor pattern 142 through the second via hole 162 .
  • the structure of the first via hole 161 and the second via hole 162 may be the same.
  • the passivation layer 160 can isolate the electrode layer 150 from the first semiconductor layer 120 , and the electrode layer 150 from the light-emitting functional layer 130 , so that the electrode layer 150 remains electrically insulated from the first semiconductor layer 120 and the light-emitting functional layer 130 .
  • the voltage signal from the first electrode 151 can be transmitted to the third semiconductor pattern 141, the voltage signal from the second electrode 152 can be transmitted to the fourth semiconductor pattern 142, and both the first light emitting part D1 and the second light emitting part D2 can be Stable and work independently.
  • the light emitting device 100 further includes at least one insulating layer 170 and a binding electrode layer 180 .
  • At least one insulating layer 170 is disposed on a side of the electrode layer 150 away from the first semiconductor layer 120
  • the bonding electrode layer 180 is disposed on a side of the at least one insulating layer 170 away from the electrode layer 150 .
  • a third via hole 1701 and a fourth via hole 1702 are disposed in at least one insulating layer 170 .
  • the binding electrode layer 180 includes a first binding electrode 181 and a second binding electrode 182 .
  • the first binding electrode 181 is electrically connected to the first electrode 151 through the third via hole 1701
  • the second binding electrode 182 is electrically connected to the second electrode 152 through the fourth via hole 1702 .
  • the surface of the electrode layer 150 away from the first semiconductor layer 120 is uneven, which is not conducive to the bonding and electrical connection between the light emitting device 100 and the pixel circuit in the driving backplane 200 .
  • the surface of at least one insulating layer 170 away from the first semiconductor layer 120 is substantially flat, so that the surface of the binding electrodes (including the first binding electrode 181 and the second binding electrode 182 ) away from the first semiconductor layer 120 is flat, which is conducive to light emission
  • the device 100 is bonded to the driving backplane 200 to improve the stability and reliability of the electrical connection between the light emitting device 100 and the driving backplane 200 .
  • at least one insulating layer 170 can protect the electrode layer 150, weaken or prevent the electrode layer 150 from being corroded.
  • At least one insulating layer 170 may include at least one of a reflective layer 171 , a heat dissipation layer 172 and an encapsulation layer 173 .
  • at least one insulating layer 170 includes a reflective layer 171 , a heat dissipation layer 172 and an encapsulation layer 173 .
  • the reflective layer 171 can form a substantially tapered reflector on the side away from the substrate 110 of the first light-emitting portion D1 and the second light-emitting portion D2, and further reflect the light emitted by the first light-emitting portion D1 and the second light-emitting portion D2.
  • the light toward the emission layer 170 is reflected to the light emitting surface of the light emitting device 100 (the side of the first light emitting part D1 and the second light emitting part D2 away from the binding electrode layer 180 ), thereby improving the light extraction efficiency of the light emitting device 100 .
  • the heat dissipation layer 172 can absorb and conduct the heat emitted by the first light emitting part D1 and the second light emitting part D2 to the outside of the light emitting device 100, which is beneficial to reduce the operating temperature of the first light emitting part D1 and the second light emitting part D2 and improve the performance of the light emitting device. 100 luminous efficiency.
  • the encapsulation layer 173 can protect the reflective layer 171 and the heat dissipation layer 172 , and at the same time can form a substantially flat surface, which facilitates the setting of the bonding electrode layer 180 .
  • At least one fifth via hole 1703 is further disposed in at least one insulating layer 170 .
  • the binding electrode layer 180 further includes a third binding electrode 183 , and the third binding electrode 183 is electrically connected to the first semiconductor pattern 121 and the second semiconductor pattern 122 through at least one fifth via hole 1703 .
  • the grayscale displayed by the light emitting part (the first light emitting part D1 or the second light emitting part D2) is related to the driving current flowing through the light emitting part, and the driving current flowing through the light emitting part is related to the driving current input to the light emitting part.
  • the voltage difference across the two semiconductor patterns is positively correlated.
  • the first semiconductor pattern 121 and the second semiconductor pattern 122 are electrically connected, and the two light-emitting parts can be controlled to work independently by controlling the voltage input to the third semiconductor pattern 141 and the fourth semiconductor pattern 142. In this way, the pixel of the light-emitting device 100 can be simplified.
  • the circuit 300 reduces the manufacturing difficulty of the driving backplane 200 and reduces the manufacturing cost of the driving backplane 200 .
  • FIG. 4A and FIG. 5A are structural diagrams of the light emitting device 100 when the first semiconductor pattern 121 and the second semiconductor pattern 122 are arranged at intervals.
  • the first semiconductor pattern 121 and the second semiconductor pattern 122 are electrically connected, and the first semiconductor pattern 121 and the second semiconductor pattern 122 may be spaced apart, and the third binding electrode 183 passes through one of the two fifth via holes 1703
  • the hole 1703 is electrically connected to the first semiconductor pattern 121 , and is electrically connected to the second semiconductor pattern 122 through another fifth via hole 1703 among the two fifth via holes 1703 .
  • it is beneficial to reduce the area of the first semiconductor pattern 121 and the second semiconductor pattern 122 and it is beneficial to improve the light extraction efficiency of the light emitting device 100 .
  • FIG. 4B and FIG. 5B are structural diagrams of the light emitting device 100 when the first semiconductor pattern 121 and the second semiconductor pattern 122 are integrally arranged.
  • the first semiconductor pattern 121 and the second semiconductor pattern 122 are electrically connected, and the first semiconductor pattern 121 and the second semiconductor pattern 122 can also be integrally arranged, that is, there is no space between the first semiconductor pattern 121 and the second semiconductor pattern 122, and the third
  • the binding electrode 183 may be electrically connected to the first semiconductor pattern 121 and the second semiconductor pattern 122 through one or more fifth via holes 1703 . In this way, the pattern of the first semiconductor layer 120 is simpler, and one fifth via hole 1703 can be reduced, which is beneficial to simplify the manufacturing process of the light emitting device 100 and reduce the manufacturing cost of the light emitting device 100 .
  • the display device 1000 may further include a polarizer, a driving chip and the like.
  • the pixel circuit 300 included in the driving backplane 200 includes a first control circuit 310 and a second control circuit 320 .
  • the first control circuit 310 is configured to drive one of the first light-emitting part D1 and the second light-emitting part D2 in the light-emitting device 100 described in any of the above-mentioned embodiments
  • the second control circuit 320 is configured to drive any of the above-mentioned light-emitting parts.
  • the first control circuit 310 is coupled to the first scan signal terminal GATE1, the first data signal terminal DATA1, the first voltage signal terminal VDD, and the first light-emitting portion D1 of the light-emitting device 100.
  • the line between the first voltage signal terminal VDD and the first light emitting part D1 is turned on, and The brightness of the first light-emitting part D1 is controlled to switch between the first gray scale and the second gray scale.
  • the first control circuit 310 provided by the embodiment of the present disclosure can conduct or interrupt the line between the first voltage signal terminal VDD and the first light emitting part D1, and the connection between the first voltage signal terminal VDD and the first light emitting part D1
  • the first light emitting part D1 works and displays the first gray scale; since the current flowing through the first light emitting part D1 cannot be adjusted, the light emitting part D1 works and the light emitting device 100 displays different gray scales.
  • the gray levels displayed by the first light-emitting portion D1 are the same.
  • the first light emitting portion D1 does not emit light, that is, the first light emitting portion D1 displays the second gray scale (0 gray scale).
  • the second control circuit 320 is coupled to the first scan signal terminal GATE1, the first voltage signal terminal VDD, and the second light-emitting part D2 of the light-emitting device 100, and is configured to Under the control of , the line between the first voltage signal terminal VDD and the second light emitting part D2 is turned on, and the magnitude of the driving current flowing through the second light emitting part D2 is controlled.
  • the second control circuit 320 provided by the embodiment of the present disclosure can conduct the line between the first voltage signal terminal VDD and the second light emitting part D2 to make the second light emitting part D2 emit light, and can control the current flowing through the second light emitting part D2.
  • the magnitude of the driving current of the light emitting portion D2 controls the second light emitting portion D2 to display different gray scales.
  • the pixel circuit 300 provided by the embodiment of the present disclosure can control the first light-emitting part D1 and the second light-emitting part D2 to work independently, and can control the first light-emitting part D1 to work or not work (not emit light), and control the second light-emitting part D1 to work independently.
  • Part D2 shows the gray scale.
  • the pixel circuit 300 can control the light emitting device 100 to display low gray scales, the first light emitting part D1 does not work, and the second light emitting part D2 works; that is, only the second light emitting part D2 displays low gray scales. In this way, the light-emitting area of the light-emitting device 100 can be reduced when displaying low gray scales.
  • the light-emitting device 100 when displaying the same low gray scale, the light-emitting device 100 provided by the embodiments of the present disclosure has a smaller light-emitting area.
  • the device 100 In order for the device 100 to display the same low grayscale, it is necessary to increase the current magnitude of the second light emitting part D2, thereby increasing the current density of the second light emitting part D2 and improving the luminous efficiency of the second light emitting part D2.
  • the first light emitting part D1 works (lights up)
  • the fixed gray scale is usually a high gray scale.
  • the first light emitting part D1 itself Luminous efficiency can be at a high level.
  • the first control circuit 310 interrupts the line between the first voltage signal terminal VDD and the first light emitting part D1, and the first light emitting part D1 does not emit light; meanwhile, the first light emitting part D1 does not emit light;
  • the second control circuit 320 conducts the line between the first voltage signal terminal VDD and the second light emitting part D2, and controls the second light emitting part D2 to display different low grays by controlling the magnitude of the driving current flowing through the second light emitting part D2. levels, so that the light emitting device 100 can display different gray levels.
  • the first control circuit 310 conducts the line between the first voltage signal terminal VDD and the first light-emitting part D1, and the first light-emitting part D1 emits light.
  • the driving current flowing through the first light emitting part D1 is the same, that is, the displayed gray scale is fixed when the first light emitting part D1 is working (light emitting).
  • the first control circuit 310 only needs to control whether the line between the first voltage signal terminal VDD and the first light emitting part D1 is turned on or not, which is conducive to simplifying the structure of the first control circuit 310 and further simplifying the structure of the pixel circuit 300.
  • the second control circuit 320 conducts the line between the first voltage signal terminal VDD and the second light emitting part D2, and by controlling the magnitude of the driving current flowing through the second light emitting part D2, controls the second light emitting part D2 to display different gray scales, and then control the light emitting device 100 to display different gray scales.
  • the pixel circuit 300 provided by the embodiments of the present disclosure is configured to drive the light-emitting device 100 described in any of the above-mentioned embodiments. While improving the luminous efficiency of the light-emitting device 100 , it can reduce the low display performance of the pixel circuit 300 when driving the light-emitting device 100 . The energy consumption of the gray scale is reduced, and the energy consumption of the pixel circuit 300 is reduced.
  • both the first light-emitting part D1 and the second light-emitting part D2 include an anode voltage terminal and a cathode voltage terminal
  • the first control circuit 310 is used to electrically connect with the anode voltage terminal of the first light-emitting part D1
  • the second control circuit 320 is used for electrical connection with the anode voltage terminal of the second light emitting part D2.
  • the cathode voltage terminals of the first light-emitting part D1 and the second light-emitting part D2 can also be electrically connected with a cathode voltage signal terminal VSS, and the cathode voltage signal terminal VSS can be the cathode voltage terminal of the first light-emitting part D1 and the second light-emitting part.
  • the cathode voltage terminal of D2 provides a negative voltage, or the cathode voltage signal terminal VSS can also be directly grounded.
  • the first control circuit 310 may be electrically connected to the first binding electrode 181
  • the second control circuit 320 may be electrically connected to the second binding electrode 182
  • the cathode voltage signal terminal VSS can be electrically connected to the third binding electrode 183 .
  • the first control sub-circuit 310 and the second control sub-circuit 320 share the same voltage signal terminal (such as the first voltage signal terminal VDD, the cathode voltage signal terminal VSS, and the first scanning signal terminal GATE1, etc.), which can simplify driving the backplane 200
  • the circuit layout reduces the difficulty of manufacturing the driving backplane 200 and reduces the manufacturing cost of the light-emitting substrate 1100; at the same time, it can simplify the complexity of the pixel circuit 300 and reduce the difficulty of controlling the pixel circuit 300.
  • the first control circuit 310 includes a first data writing subcircuit 311 , a switch control subcircuit 312 , and a first storage subcircuit 313 .
  • the first data writing sub-circuit 311 is coupled to the first scanning signal terminal GATE1, the first data signal terminal DATA1, and the first node N1, and is configured to be controlled by the first scanning signal Gate1 from the first scanning signal terminal GATE1. Next, the first data signal Data1 from the first data signal terminal DATA1 is transmitted to the first node N1.
  • the switch control sub-circuit 312 is coupled to the first node N1, the first voltage signal terminal VDD, and the first light-emitting part D1, and is configured to connect the first voltage signal terminal VDD to the first light-emitting part D1 under the control of the voltage of the first node N1. A line between the light emitting parts D1 is turned on.
  • the first storage sub-circuit 313 is coupled to the first voltage signal terminal VDD and the first node N1, and is configured to store and maintain the voltage of the first node N1.
  • one frame period of the first light emitting part D1 includes a reset phase t1 , a scanning phase t2 , and a light emitting phase t2 .
  • the first scan signal Gate1 of the first scan signal terminal GATE1 is a low-level signal, and the first transistor T1 is turned off.
  • the first data signal Data1 is transmitted to the first node N1.
  • the first data signal Data1 may be a signal for controlling the switch control sub-circuit 312 to be turned on, or a signal for controlling the switch control sub-circuit 312 to be closed.
  • the switch control sub-circuit 312 is controlled by the first data signal Data1 of the first node N1 to conduct or disconnect the line between the first voltage signal terminal VDD and the first light-emitting part D1.
  • the first storage sub-circuit 313 maintains the voltage of the first node N1 to keep the light emitting state of the first light emitting portion D1 stable within one frame period.
  • the first data signal Data1 when the light emitting device 100 needs to display a low gray scale, the first data signal Data1 may be a signal for interrupting the line between the first voltage signal terminal VDD and the first light emitting part D1.
  • the first data signal Data1 when the light emitting device 100 needs to display a high gray scale, the first data signal Data1 may be a signal for turning on the line between the first voltage signal terminal VDD and the first light emitting part D1.
  • the first data writing sub-circuit 311 includes a first transistor T1, the control electrode of the first transistor T1 is coupled to the first scanning signal terminal GATE1, and the first electrode of the first transistor T1 is connected to the first scanning signal terminal GATE1.
  • the first data signal terminal DATA1 is coupled, and the second pole of the first transistor T1 is coupled to the first node N1.
  • the switch control sub-circuit 312 includes a second transistor T2, the control electrode of the second transistor T2 is coupled to the first node N1, the first electrode of the second transistor T2 is coupled to the first voltage signal VDD terminal, and the second transistor T2 The diode is coupled with the first light emitting part D1.
  • the first storage sub-circuit 313 includes a first storage capacitor C1, a first terminal of the first storage capacitor C1 is coupled to the first node N1, and a second terminal of the first storage capacitor C1 is coupled to the first voltage signal terminal VDD.
  • the first control circuit 310 only includes two transistors and one capacitor, and has a simple structure, which is conducive to reducing the space occupied by the first control circuit 310 and increasing the density of the pixel circuit 300 driving the backplane 200.
  • the second control circuit 320 not only needs to control the conduction of the line between the first voltage signal terminal VDD and the second light emitting part D2, but also needs to control the driving current flowing through the second light emitting part D2. Therefore, more precise control input is required.
  • the second control circuit 320 may adopt a circuit of internal compensation technology or a circuit of external compensation technology.
  • the second control circuit 320 may be a circuit using internal compensation techniques.
  • the second control circuit 320 includes: a second data writing subcircuit 321, a second storage subcircuit 322, a first driving subcircuit 323, a compensation subcircuit 324, a voltage control subcircuit 325, a light emission control subcircuit circuit 326, and an initialization sub-circuit 327.
  • the second data writing sub-circuit 321 is coupled to the first scanning signal terminal GATE1, the second data signal terminal DATA2, and the second node N2, and is configured to be controlled by the first scanning signal Gate1 from the first scanning signal terminal GATE1 , to transmit the second data signal Data2 from the second data signal terminal DATA2 to the second node N2.
  • the second storage sub-circuit 322 is coupled to the second node N2 and the third node N3, and is configured to store the voltage of the second node N2 and adjust the voltage of the third node N3.
  • the first driving sub-circuit 323 is coupled to the third node N3, the first voltage signal terminal VDD, and the fourth node N4, and is configured to drive the first voltage signal from the first voltage signal terminal VDD under the voltage control of the third node N3.
  • a voltage signal Vdd is transmitted to the fourth node N4.
  • the compensation sub-circuit 324 is coupled to the first scan signal terminal GATE1, the fourth node N4, and the third node N3, and is configured to drive the first drive under the control of the first scan signal Gate1 from the first scan signal terminal GATE1.
  • the threshold voltage Vth of the sub-circuit 323 is compensated to the third node N3.
  • the voltage control sub-circuit 325 is coupled to the second scan signal terminal GATE2, the second voltage signal terminal VINIT, and the second node N2, and is configured to, under the control of the second scan signal Gate2 from the second scan signal terminal GATE2, The second voltage signal Vinit from the second voltage signal terminal VINIT is transmitted to the second node N2.
  • the light emission control subcircuit 326 is coupled to the enable signal terminal EM, the fourth node N4, and the second light emitting part D2, and is configured to turn the fourth node N4 under the control of the enable signal Em from the enable signal terminal EM.
  • the voltage is transmitted to the second light emitting part D2.
  • the initialization sub-circuit 327 is coupled to the reset signal terminal RESET, the second voltage signal terminal V2, and the second node N2, and is configured to convert the voltage from the second voltage signal terminal V2 under the control of the reset signal from the reset signal terminal RESET.
  • the second voltage signal Vinit is transmitted to the second node N2.
  • a frame period of the first light emitting part and the second light emitting part D2 both includes a reset period t1 , a scanning period t2 , and a light emitting period t3 .
  • the initialization sub-circuit 327 initializes the voltage of the second node N2.
  • the second data writing sub-circuit 321 transmits the second data signal Data2 to the second node
  • the second storage sub-circuit 322 stores the voltage of the second node N2
  • the compensation sub-circuit 324 transfers the first driving sub-circuit 323
  • the threshold voltage V th of is compensated to the third node N3.
  • the voltage of the second node N2 is V Data2
  • the voltage of the third node N3 is V DD +V th .
  • the voltage control sub-circuit 325 transmits the second voltage signal Vinit to the second node N2, and the voltage of the second node N2 jumps to V GL (namely Vinit).
  • the first driving sub-circuit 323 is in a saturated state.
  • the driving current I D2 of the second light emitting part D2 has nothing to do with the threshold voltage V th of the second storage sub-circuit 322 , and the second light emitting part D2 emits light stably during the light emitting phase of one frame period.
  • the first control circuit 310 compensates the threshold voltage V th of the first driving sub-circuit 323 to the gate (third node N3) of the first driving sub-circuit 323 through the compensation sub-circuit 324 to eliminate the threshold voltage V th of the fourth transistor T4 effect on the first control circuit.
  • the plurality of pixel circuits 300 included in the drive backplane 200 are arranged in multiple rows and columns, and each row of pixel circuits 300 is provided with at least one scanning signal line, and at least one scanning signal line can be multiple lines of the row.
  • Each pixel circuit 300 provides a scanning signal, and multiple rows of pixel circuits 300 are controlled in a progressive scanning manner.
  • the reset signal terminal VINIT of any row of pixel circuits 300 can be connected to the scanning signal line of the previous row of pixel circuits 300, and the second scanning signal terminal GATE2 can be electrically connected to the scanning signal line of the next row of pixel circuits 300.
  • the layout of the scanning signal lines can be simplified, which is beneficial to reduce the manufacturing difficulty of the driving backplane 200 , thereby reducing the manufacturing cost of the light emitting substrate 1100 .
  • the second data writing sub-circuit 321 includes a third transistor T3, the control electrode of the third transistor T3 is coupled to the first scanning signal terminal GATE1, and the first electrode of the third transistor T3 is connected to The second data signal terminal DATA2 is coupled, and the second pole of the third transistor T3 is coupled to the second node N2.
  • the second storage sub-circuit 322 includes a second storage capacitor C2, a first terminal of the second storage capacitor C2 is electrically connected to the second node N2, and a second terminal of the second storage capacitor C2 is electrically connected to the third node N3.
  • the first driving sub-circuit 323 includes a fourth transistor T4, the control electrode of the fourth transistor T4 is coupled to the third node N3, the first electrode of the fourth transistor T4 is coupled to the first voltage signal terminal VDD, and the control electrode of the fourth transistor T4 is coupled to the first voltage signal terminal VDD.
  • the second pole is coupled to the fourth node N4.
  • the compensation sub-circuit 324 includes a fifth transistor T5, the control electrode of the fifth transistor T5 is coupled to the first scanning signal terminal GATE1, the first electrode of the fifth transistor T5 is coupled to the fourth node N4, and the second electrode of the fifth transistor T5 pole is coupled to the third node N3.
  • the voltage control sub-circuit 325 includes a sixth transistor T6, the control electrode of the sixth transistor T6 is coupled to the second scanning signal terminal GATE2, the first electrode of the sixth transistor T6 is coupled to the second voltage signal terminal V2, and the sixth transistor T6 The second pole of is coupled to the second node N2.
  • the light emission control sub-circuit 326 includes a seventh transistor T7, the control pole of the seventh transistor T7 is coupled to the enable signal terminal EM, the first pole of the seventh transistor T7 is coupled to the fourth node N4, and the second pole of the seventh transistor T7 The pole is coupled with the second light emitting part D2.
  • the reset sub-circuit 327 includes an eighth transistor T8, the control pole of the eighth transistor T8 is coupled to the reset signal terminal RESET, the first pole of the eighth transistor T8 is coupled to the initialization signal terminal VINIT, and the second pole of the eighth transistor T8 is coupled to the reset signal terminal VINIT.
  • the second node N2 is coupled.
  • the reset signal terminal RESET provides a low-level signal
  • the first scan signal terminal GATE1, the second scan signal terminal GATE2, and the enable signal terminal EM provide a high-level signal signal
  • the eighth transistor T8 is turned on, and the other transistors are turned off, to initialize the voltage of the second storage capacitor C2.
  • the first scanning signal terminal GATE1 provides a low-level signal
  • the reset signal terminal RESET the second scanning signal terminal GATE2, and the enable signal terminal EM provide a high-level signal
  • the first transistor T1 and the third transistor T3 , and the fifth transistor T5 are turned on, and the remaining transistors are turned off
  • the first node N1 writes the first data signal Data1
  • the second node N2 writes the second data signal Data2
  • the threshold voltage V th of the fourth transistor T4 is compensated to the third node N3.
  • the second scan signal terminal GATE2 and the enable signal terminal EM provide low-level signals
  • the reset signal terminal RESET and the first scan signal terminal GATE1 provide high-level signals.
  • the sixth transistor T6, the fourth transistor T4, and the seventh transistor T7 are turned on, and other transistors are turned off.
  • the voltage of the second node N2 jumps to V GL
  • the voltage of the third node N3 jumps to Then, the fourth transistor T4 drives the second light emitting part D2 to work under the control of the voltage of the third node N3.
  • the first control circuit 310 if the first data signal Data1 is a low-level signal, the second transistor T2 is turned on, the first light-emitting part D1 displays the first gray scale, and the light-emitting device 100 displays a high gray scale; if the first data signal Data1 is a high level signal, the second transistor T2 is turned off, the first light emitting part D1 displays the second gray scale (0 gray scale), and the light emitting device 100 displays a low gray scale.
  • the second control circuit 320 may be a circuit using external compensation techniques. In this way, referring to FIG. 13 , the second control circuit 320 includes a feedback subcircuit 328 , an input subcircuit 329 , a second drive subcircuit 3210 , a third storage subcircuit 3211 and a modulation subcircuit 3212 .
  • the feedback sub-circuit 328 is coupled to the first scanning signal terminal GATE1, the feedback signal terminal M1, and the feedback node N0, and is configured to convert the feedback node N0 under the control of the first scanning signal Gate1 from the first scanning signal terminal GATE1. The voltage is transmitted to the feedback signal terminal M1.
  • the feedback node N0 is coupled to the second light emitting part D2, that is, the voltage input to the second light emitting part D2 is controlled by the voltage of the feedback node N0. Therefore, by adjusting the voltage of the feedback node N0 , the driving current of the second light emitting portion D2 can be controlled, thereby controlling the gray scale displayed by the second light emitting portion D2 .
  • the input sub-circuit 329 is coupled to the first scanning signal terminal GATE1, the input signal terminal M2, and the fifth node N5, and is configured to receive the input signal from the input signal under the control of the first scanning signal Gate1 from the first scanning signal terminal GATE1.
  • the input signal of the terminal M1 is transmitted to the fifth node N5.
  • the input signal is generated according to the voltage of the feedback node N0 and the third data signal Data3 for controlling the gray scale of the second light emitting part D2.
  • the third data signal Data3 is used to control the gray scale displayed by the second light emitting part D2, that is, it is necessary to adjust the voltage of the feedback node N0 to be the same as the third data signal Data3, so that the second light emitting part D2 can Display the corresponding gray scale.
  • an input signal can be input to the fifth node through the input sub-circuit 329 according to the voltage of the feedback node N0 and the third data signal Data3.
  • the second driving sub-circuit 3210 is coupled to the fifth node N5, the sixth node N6, and the feedback node N0, and is configured to adjust the feedback node according to the voltage signal of the sixth node N6 under the control of the voltage of the fifth node N5 The voltage of N0.
  • the impedance of the second driving sub-circuit 3210 can be adjusted, and then the voltage shared (consumed) by the second driving sub-circuit 3210 can be adjusted, and then the feedback node N0 can be adjusted. potential until the voltage of the feedback node N0 is consistent with the voltage of the third data signal Data3.
  • the third storage sub-circuit 3211 is coupled to the first voltage signal terminal VDD and the fifth node N5, and is configured to store and maintain the voltage of the fifth node N5.
  • the third storage sub-circuit 3211 is used to maintain the voltage of the fifth node N5 during the light-emitting phase of one frame, so as to keep the voltage of the feedback node N0 stable, so that the second light-emitting part D2 can emit light stably.
  • the modulation subcircuit 3212 is coupled to the third scanning signal terminal G3, the first voltage signal terminal VDD, and the sixth node N6, and is configured to, under the control of the third scanning signal Gate from the third scanning signal terminal G3, convert the The first voltage signal Vdd of the first voltage signal terminal VDD is transmitted to the sixth node N6, and modulates the conduction time of the line between the first voltage signal terminal VDD and the second light emitting part D2.
  • the second light-emitting part D2 displays low grayscale
  • the current required by the second light-emitting part D2 is relatively small, and the voltage required by the feedback node N0 is relatively small.
  • the voltage shared by the second driving sub-circuit 3210 will be relatively large, and the power consumption of the second control circuit 320 itself will be relatively large.
  • the modulation sub-circuit 3212 conducts the line between the first voltage signal terminal VDD and the sixth node N6, and controls the light-emitting time of the second light-emitting part D2 by controlling the time length of the line conduction, that is, the modulation sub-circuit 3212 By reducing the light-emitting duration of the second light-emitting part D2, the current required by the second light-emitting part D2 can be increased, and the voltage required by the second node N2 can be increased to reduce the power consumption of the second control circuit 320 itself, and reduce the cost of the light-emitting substrate 1100. power consumption.
  • the third scan signal Gate3 of the third scan signal terminal GATE3 can be an alternate high-level and low-level signal In this way, the light-emitting duration of the second light-emitting portion D2 can be reduced to increase the current when the second light-emitting portion D2 emits light, and increase the current density of the second light-emitting portion D2 and the luminous efficiency of the second light-emitting portion D2.
  • the third scanning signal Gate3 of the third scanning signal terminal GATE3 can be at a continuous high level, which can be achieved by increasing the second light-emitting part
  • the light-emitting time of D2 is long to reduce the current when the second light-emitting portion D2 emits light, avoiding excessive current passing through the second light-emitting portion D2, and reducing the load of the second control circuit 320 .
  • the second control circuit 320 when the second control circuit 320 is a circuit using external compensation technology, that is, the second control circuit 320 of the pixel circuit 300 includes a feedback sub-circuit 328, an input sub-circuit 329, a second driving sub-circuit 3210, the third storage subcircuit 3211, and the modulation subcircuit 3212.
  • the light-emitting substrate 1100 further includes at least a circuit board (not shown in the figure), and the circuit board is electrically connected to the driving backplane 200 .
  • the circuit board includes a third control circuit 400 .
  • the third control circuit 400 is configured to output an input signal for adjusting the voltage of the fifth node to the fifth node N5 according to the voltage of the feedback node N0 received by the feedback signal terminal M0 and the third data signal Data3.
  • the third control circuit 400 includes a comparison subcircuit 410 and a signal conversion subcircuit 420 .
  • the comparison subcircuit 410 is coupled to the third data signal terminal DATA3, the feedback signal terminal M1, and the seventh node N7, and is configured to compare the voltage of the feedback node N0 transmitted from the feedback signal terminal M1 with the voltage from the third data signal terminal DATA3 The third data signal Data3, and output the adjustment voltage to the seventh node N7 according to the comparison result.
  • the third data signal terminal DATA3 is configured to transmit the third data signal Data3 for controlling the gray scale of the second light emitting part D2.
  • the signal conversion sub-circuit 420 is coupled to the seventh node N7, the ground voltage terminal GND, and the input signal terminal M2, and is configured to transmit to the input signal terminal M2 according to the adjusted voltage of the seventh node N7 and the voltage of the ground voltage terminal GND.
  • the second control circuit using the external compensation technology provided by the embodiments of the present disclosure transmits the voltage of the feedback node N0 to the feedback node M1 under the control of the feedback sub-circuit 328 during the scanning phase.
  • the comparison sub-circuit 410 receives and compares the voltage V N0 of the feedback node N0 received by the feedback signal terminal M1 with the voltage V Data3 of the third data signal Data3 received from the third data signal terminal DATA3, and then sends the voltage V Data3 to the third data signal terminal DATA3 according to the comparison result.
  • the seven node N7 outputs a regulated voltage.
  • the signal conversion sub-circuit 420 outputs an output signal V M2 to the input signal terminal M2 according to the regulated voltage received from the seventh node N7.
  • the output signal V M2 is output to the fifth node N5.
  • the voltage shared by the second driving sub-circuit 3210 is controlled by the voltage of the fifth node N5, thereby adjusting the voltage of the feedback node N0.
  • the sum of the voltage shared by the second driving sub-circuit 3210 and the voltage of the feedback node N0 is equal to the voltage provided by the first voltage signal terminal VDD.
  • the third control circuit 400 can directly adjust the anode voltage of the second light emitting part D2 (the feedback node N0 is directly electrically connected to the anode voltage terminal of the second light emitting part D2), so that the anode voltage of the second light emitting part D2 is consistent with the third data
  • the voltage of the third data signal Data3 at the signal terminal DATA3 is consistent, so there is no need to compensate the threshold voltage of the second driving sub-circuit 3210, so that the second driving sub-circuit 3210 can work in the linear region.
  • the feedback sub-circuit 328 includes a ninth transistor T9, the control electrode of the ninth transistor T9 is coupled to the first scanning signal terminal GATE1, and the first electrode of the ninth transistor T9 is connected to the feedback The node N0 is coupled, and the second pole of the ninth transistor T9 is coupled to the feedback signal terminal M1.
  • the input sub-circuit 329 includes a tenth transistor T10, the control pole of the tenth transistor T10 is coupled to the first scan signal terminal GATE1, the first pole of the tenth transistor T10 is coupled to the input signal terminal M2, and the second pole of the tenth transistor T10 pole is coupled to the fifth node N5.
  • the second driving sub-circuit 3210 includes an eleventh transistor T11, the control electrode of the eleventh transistor T11 is coupled to the fifth node N5, the first electrode of the eleventh transistor T11 is coupled to the sixth node N6, and the eleventh transistor T11 The second pole of T11 is coupled to the feedback node N0.
  • the third storage sub-circuit 3211 includes a third capacitor C3, a first terminal of the third capacitor C3 is coupled to the first voltage signal terminal VDD, and a second terminal of the third capacitor C3 is coupled to the fifth node N5.
  • the modulation sub-circuit 3212 includes a twelfth transistor T12, the control pole of the twelfth transistor T12 is coupled to the third scanning signal terminal G3, the first pole of the twelfth transistor T12 is coupled to the first voltage signal terminal VDD, and the tenth transistor T12 is coupled to the first voltage signal terminal VDD.
  • the second pole of the second transistor T12 is coupled to the sixth node N6.
  • the comparison subcircuit 410 includes a first amplifier OP1, and the first amplifier OP1 includes a first positive input terminal I1, a first negative input terminal I2 and a first output terminal O1,
  • the first positive input terminal I1 is coupled to the feedback signal terminal M1
  • the first negative input terminal I2 is coupled to the third data signal terminal DATA2
  • the first output terminal O1 is coupled to the seventh node N7.
  • the signal converting sub-circuit 420 includes a second amplifier OP2 and a fourth capacitor C4.
  • the second amplifier OP2 has a second positive input terminal I3, a second negative input terminal I4 and a second output terminal O2, the second positive input terminal I3 is coupled to the ground voltage terminal GND, and the second negative input terminal I4 is connected to the ground voltage terminal GND.
  • the seventh node N7 is coupled, and the second output terminal O2 is coupled to the signal input terminal M2.
  • One terminal of the fourth capacitor C4 is coupled to the second negative input terminal I4, and the second terminal of the fourth capacitor C4 is coupled to the second output terminal O2.
  • one frame period includes a scanning phase t2 and a light emitting phase t3 .
  • the first data signal terminal DATA1 starts to output the first data signal Data1, the first scanning signal terminal Gate1 is a low-level signal, the first transistor T1 is turned on, and the first data signal Data1 from the first data signal terminal DATA1 is transmitted to the first node N1.
  • the first data signal Data1 may be a low-level signal (for displaying high grayscale) or a high-level signal (for displaying low grayscale).
  • the second data signal terminal DATA2 starts to output the second data signal Data2.
  • the ninth transistor T9 and the tenth transistor T10 are turned on, the voltage of the feedback node N0 is transmitted to the positive input terminal I1 of the first amplifier OP1, and the third data signal Data3 from the third data signal terminal DATA3 is transmitted to the first amplifier OP1
  • the first amplifier OP1 transmits a regulated voltage to the seventh node N7 according to the voltage of the feedback node N0 and the third data signal Data3.
  • the fourth capacitor C4 is charged or discharged according to the regulated voltage received from the seventh node N7, and changes the voltage of the second output terminal O2 of the second amplifier OP, that is, changes the voltage of the fifth node N5, thereby controlling the eleventh transistor T11 control the impedance of the eleventh transistor T11, adjust the voltage division of the eleventh transistor T11, and realize the purpose of adjusting the voltage of the feedback node N0; until the voltage of the feedback node N0 is adjusted to be equal to that of the third data signal Data3 same voltage.
  • the voltage of the feedback node N0 (the anode voltage of the second light emitting part D2) V N0 is lower than the voltage V Data3 of the third data signal Data3 of the third data signal terminal DATA3, the first output terminal O1 of the first amplifier OP1 output a low-level (negative voltage signal) regulation voltage; the potential of one end of the fourth capacitor C4 drops, the fourth capacitor C4 starts to discharge, the second output terminal O2 outputs a low-level voltage signal, and the voltage of the fifth node N5 decreases, the impedance of the eleventh transistor T11 decreases, the voltage shared by the eleventh transistor T11 decreases, and the voltage of the feedback node N0 increases until the voltage V N0 of the feedback node N0 is equal to the voltage V Data3 of the third data signal Data3 .
  • the first light emitting unit D1 operates (emits light) or does not operate (emits light) according to the first data signal Data1. Exemplarily, when the first data signal Data1 is a low level signal, the first light emitting part D1 works; when the first data signal Data1 is a high level signal, the first light emitting part D1 does not work.
  • the third scanning signal terminal GATE3 provides intermittent or continuous low-level signals.
  • the second light-emitting part D2 emits light when the third scanning signal terminal GATE3 provides a low-level signal, and does not emit light when the third scanning signal terminal GATE3 provides a high-level signal.
  • the feedback signal terminals M1 of the plurality of pixel circuits 300 in the same column are coupled to the first positive input terminal I1 of the first amplifier OP1 of the same third control circuit 400; the plurality of pixel circuits in the same column
  • the input signal terminal M2 of 300 is coupled to the second output terminal O2 of the same third control circuit 400 ; that is, multiple pixel circuits 300 in the same column are coupled to the same third control circuit 400 .
  • the comparison subcircuit 410 further includes a first resistor R1, one end of the first resistor R1 is electrically connected to the first positive input terminal I1, and two ends of the first resistor R1 are electrically connected to the first negative input terminal I1.
  • the input terminal I2 is electrically connected.
  • the third data signal terminal DATA3 will have a blank (Blank) period. In this period, the first negative access terminal I2 of the first amplifier OP1 is in a floating state.
  • a resistor R1 can weaken or even eliminate the above noise.
  • the resistance value of the first resistor R1 is generally set relatively large, such as 1K ⁇ , 2K ⁇ and so on.
  • the first resistor R1 may not be provided.
  • the signal converting sub-420 circuit further includes a second resistor R2 and a third resistor R3.
  • One end of the second resistor R2 is electrically connected to the seventh node N7, and two ends of the second resistor R2 are electrically connected to the second negative input terminal I4.
  • One terminal of the third resistor R3 is electrically connected to the ground voltage terminal GND, and two terminals of the third resistor R3 are electrically connected to the second positive input terminal I3.
  • the line between the feedback signal terminal M1 and the first positive input terminal I1 itself has a resistance RL1, and this line may form a capacitance CL1 with other lines in the light-emitting substrate 1100; for the same reason , the line between the input signal terminal M2 and the second output terminal OUT2 itself has a resistance RL2, and this line may form a capacitance CL2 with other lines in the light-emitting substrate 1100 . That is, in the figure, RL1, CL1, RL2, and CL2 are the capacitance and resistance generated by the line itself. In some other schematic drawings, structures such as RL1, CL1, RL2, and CL2 may not be shown.
  • the product of RL1 and CL1 is equal to the product of RL2 and CL2, so that the charging and discharging rate of the fourth capacitor C4 is the same as the rate at which the first amplifier OP1 obtains the voltage of the feedback node N0, so that the charging and discharging of the fourth capacitor C4 is stable.

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Abstract

一种发光器件，包括层叠设置的第一半导体层、发光功能层和第二半导体层。第一半导体层包括第一半导体图案和第二半导体图案；发光功能层设置于第一半导体层的沿厚度方向相对两侧中的一侧，包括间隔设置的第一发光图案和第二发光图案；第二半导体层设置于发光功能层远离第一半导体层的一侧，包括间隔设置的第三半导体图案和第四半导体图案。第一半导体图案、第一发光图案和第三半导体图案在参考面上的正投影至少部分重叠，形成第一发光部；第二半导体图案、第二发光图案和第四半导体图案在参考面上的正投影至少部分重叠，形成第二发光部。其中，第一半导体图案和第二半导体图案电连接；参考面为平行于第一半导体层的平面。

Description

发光器件、像素电路、发光基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光器件、像素电路、发光基板及显示装置。
背景技术
微型发光二极管(英文：Light Emitting Diode；简称：LED)比如Micro-LED和mini-LED，通过将LED结构微小化、阵列化、及薄膜化，使其尺寸进行缩小。相较于有机发光二极管(英文：Organic Light-Emitting Diode；简称：OLED)，微型发光二极管具有亮度高、发光效率高、功耗低等优势，而且微型发光二极管采用无机发光材料，其材料稳定性更好，可靠性更高，是新一代显示技术。
公开内容
一方面，提供一种发光器件。所述发光器件包括层叠设置的第一半导体层、发光功能层和第二半导体层。所述第一半导体层包括第一半导体图案和第二半导体图案。所述发光功能层设置于所述第一半导体层的沿厚度方向相对两侧中的一侧，包括间隔设置的第一发光图案和第二发光图案。所述第二半导体层设置于所述发光功能层远离所述第一半导体层的一侧，包括间隔设置的第三半导体图案和第四半导体图案。所述第一半导体图案、所述第一发光图案和所述第三半导体图案在参考面上的正投影至少部分重叠，形成第一发光部。所述第二半导体图案、所述第二发光图案和所述第四半导体图案在参考面上的正投影至少部分重叠，形成第二发光部。其中，所述第一半导体图案和第二半导体图案电连接；所述参考面为平行于所述第一半导体层的平面。
在一些实施例中，所述发光器件还包括电极层。所述电极层设置于所述第二半导体层远离所述第一半导体层的一侧，包括间隔设置的第一电极和第二电极。所述第一电极与所述第三半导体图案电连接，所述第二电极与所述第四半导体图案电连接。
在一些实施例中，所述发光器件还包括钝化层。所述钝化层设置于所述第二半导体层与所述电极层之间；所述钝化层中设置有第一过孔和第二过孔，所述第一电极通过所述第一过孔与所述第三半导体图案电连接，所述第二电极通过所述第二过孔与所述第四半导体图案电连接。
在一些实施例中，所述发光器件还包括至少一层绝缘层和绑定电极层。 所述至少一层绝缘层设置于所述电极层远离所述第一半导体层的一侧，所述至少一层绝缘层中设置有第三过孔和第四过孔。所述绑定电极层设置于所述至少一层绝缘层远离所述电极层的一侧，包括第一绑定电极和第二绑定电极。所述第一绑定电极通过所述第三过孔与所述第一电极电连接，所述第二绑定电极通过所述第四过孔与所述第二电极电连接。
在一些实施例中，所述至少一层绝缘层中还设置有至少一个第五过孔；所述绑定电极层还包括第三绑定电极；所述第三绑定电极通过所述至少一个第五过孔与所述第一半导体图案及所述第二半导体图案电连接。
在一些实施例中，所述第一半导体图案和所述第二半导体图案间隔设置。
在一些实施例中，所述发光器件包括至少一层绝缘层和绑定电极层，所述至少一层绝缘层中设置有两个第五过孔，所述绑定电极层包括第三绑定电极。所述第三绑定电极通过两个第五过孔中的一个与所述第一半导体图案电连接，所述第三绑定电极通过两个第五过孔中的另一个与所述第二半导体图案电连接。
在一些实施例中，所述第一半导体图案和所述第二半导体图案一体设置。
在一些实施例中，所述发光器件包括至少一层绝缘层；所述至少一层绝缘层包括反射层、散热层和封装层中的至少一层。
在一些实施例中，所述发光器件还包括衬底。所述第一半导体层设置于所述衬底的沿厚度方向相对两侧中的一侧，所述第一半导体图案和所述第二半导体图案设置于同一衬底上，且所述发光功能层设置于所述第一半导体层远离所述沉底的一侧。
在一些实施例中，所述第三半导体图案和所述第四半导体图案被配置为传输不同的电压信号。
另一方面，提供一种像素电路。所述像素电路被配置为驱动上述任一实施例中所述的发光器件，包括第一控制电路和第二控制电路。所述第一控制电路与第一扫描信号端、第一数据信号端、第一电压信号端、及所述发光器件的第一发光部耦接，被配置为在来自所述第一扫描信号端的第一扫描信号和来自所述第一数据信号端的第一数据信号的控制下，将所述第一电压信号端与所述第一发光部之间的线路导通，并控制所述第一发光部的亮度在第一灰阶和第二灰阶之间切换。所述第二控制电路与所述第一扫描信号端、所述第一电压信号端、及所述发光器件的第二发光部耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将所述第一电压信号端与所述第二发光部之间的线路导通，并控制流经所述第二发光部的驱动电流的大小。
在一些实施例中，所述第一控制电路包括第一数据写入子电路、开关控制子电路、及第一存储子电路。所述第一数据写入子电路与所述第一扫描信号端、所述第一数据信号端、及第一节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将来自所述第一数据信号端的第一数据信号传输至所述第一节点。所述开关控制子电路与所述第一节点、所述第一电压信号端、及所述第一发光部耦接，被配置为在所述第一节点的电压的控制下，将所述第一电压信号端与所述第一发光部之间的线路导通。所述第一存储子电路与所述第一电压信号端及所述第一节点耦接，被配置为存储并维持所述第一节点的电压。
在一些实施例中，所述第一数据写入子电路包括第一晶体管，所述第一晶体管的控制极与所述第一扫描信号端耦接，所述第一晶体管的第一极与所述第一数据信号端耦接，所述第一晶体管的第二极与所述第一节点耦接。所述开关控制子电路包括第二晶体管，所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第一电压信号端耦接，所述第二晶体管的第二极与所述第一发光部耦接。所述第一存储子电路包括第一存储电容器，所述第一存储电容器的第一端与所述第一节点耦接，所述第一存储电容器的第二端与所述第一电压信号端耦接。
在一些实施例中，所述第二控制电路包括：第二数据写入子电路、第二存储子电路、第一驱动子电路、补偿子电路、电压控制子电路、发光控制子电路、及初始化子电路。所述第二数据写入子电路与所述第一扫描信号端、第二数据信号端、及第二节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将来自所述第二数据信号端的第二数据信号传输至所述第二节点。所述第二存储子电路与所述第二节点及第三节点耦接，被配置为存储所述第二节点的电压，并调节所述第三节点的电压。所述第一驱动子电路与所述第三节点、所述第一电压信号端、及第四节点耦接，被配置为在所述第三节点的电压控制下，将来自所述第一电压信号端的第一电压信号传输至所述第四节点。所述补偿子电路与所述第一扫描信号端、所述第四节点、及所述第三节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将所述第一驱动子电路的阈值电压补偿至所述第三节点。所述电压控制子电路与第二扫描信号端、第二电压信号端、及所述第二节点耦接，被配置为在来自所述第二扫描信号端的第二扫描信号的控制下，将来自所述第二电压信号端的第二电压信号传输至所述第二节点。所述发光控制子电路与使能信号端、所述第四节点、及所述第二发光部耦接，被配置为在来 自所述使能信号端的使能信号的控制下，将所述第四节点的电压传输至所述第二发光部。所述初始化子电路与复位信号端、第二电压信号端、及所述第二节点耦接，被配置为在来自所述复位信号端的复位信号的控制下，将来自所述第二电压信号端的第二电压信号传输至所述第二节点。
在一些实施例中，所述第二数据写入子电路包括第三晶体管，所述第三晶体管的控制极与所述第一扫描信号端耦接，所述第三晶体管的第一极与所述第二数据信号端耦接，所述第三晶体管的第二极与所述第二节点耦接。所述第二存储子电路包括第二存储电容器，所述第二存储电容器的第一端与所述第二节点电连接，所述第二存储电容器的第二端与所述第三节点电连接。所述第一驱动子电路包括第四晶体管，所述第四晶体管的控制极与所述第三节点耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第四节点耦接。所述补偿子电路包括第五晶体管，所述第五晶体管的控制极与所述第一扫描信号端耦接，所述第五晶体管的第一极与所述第四节点耦接，所述第五晶体管的第二极与所述第三节点耦接。所述电压控制子电路包括第六晶体管，所述第六晶体管的控制极与所述第二扫描信号端耦接，所述第六晶体管的第一极与所述第二电压信号端耦接，所述第六晶体管的第二极与所述第二节点耦接。所述发光控制子电路包括第七晶体管，所述第七晶体管的控制极与所述使能信号端耦接，所述第七晶体管的第一极与所述第四节点耦接，所述第七晶体管的第二极与所述第二发光部耦接。所述复位子电路包括第八晶体管，所述第八晶体管的控制极与所述复位信号端耦接，所述第八晶体管的第一极与所述初始化信号端耦接，所述第八晶体管的第二极与所述第二节点耦接。
在一些实施例中，所述第二控制电路包括：反馈子电路、输入子电路、第二驱动子电路、第三存储子电路及调制子电路。所述反馈子电路与所述第一扫描信号端、反馈信号端、及反馈节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将所述反馈节点的电压传输至所述反馈信号端；所述反馈节点与所述第二发光部耦接。所述输入子电路与所述第一扫描信号端、输入信号端、及第五节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将来自所述输入信号端的输入信号传输至所述第五节点；所述输入信号根据所述反馈节点的电压和用于控制所述第二发光部的灰阶的第三数据信号生成。所述第二驱动子电路与所述第五节点、第六节点、及所述反馈节点耦接，被配置为在所述第五节点的电压的控制下，根据所述第六节点的电压信号，调节所述反馈节点的电压。所述第三存储子 电路与所述第一电压信号端及所述第五节点耦接，被配置存储并维持所述第五节点的电压。所述调制子电路与第三扫描信号端、所述第一电压信号端、及所述第六节点耦接，被配置为在来自所述第三扫描信号端的第三扫描信号的控制下，将来自所述第一电压信号端的第一电压信号传输至所述第六节点，并对所述第一电压信号端与所述第二发光部之间的线路的导通时间进行调制。
在一些实施例中，所述反馈子电路包括第九晶体管，所述第九晶体管的控制极与所述第一扫描信号端耦接，所述第九晶体管的第一极与所述反馈节点耦接，所述第九晶体管的第二极与所述反馈信号端耦接。所述输入子电路包括第十晶体管，所述第十晶体管的控制极与所述第一扫描信号端耦接，所述第十晶体管的第一极与所述输入信号端耦接，所述第十晶体管的第二极与所述第五节点耦接。所述第二驱动子电路包括第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第六节点耦接，所述第十一晶体管的第二极与所述反馈节点耦接。所述第三存储子电路包括第三电容器，所述第三电容器的第一端与所述第一电压信号端耦接，所述第三电容器的第二端与所述第五节点耦接。所述调制子电路包括第十二晶体管，所述第十二晶体管的控制极与所述第三扫描信号端耦接，所述第十二晶体管的第一极与所述第一电压信号端耦接，所述第十二晶体管的第二极与所述第六节点耦接。
又一方面，提供一种发光基板。所述发光基板包括驱动背板和上述任一实施例中所述的发光器件。所述驱动背板包括多个上述任一实施例所述的像素电路。每个像素电路的第一控制电路与一个发光器件的第一发光部耦接，每个像素电路的第二控制电路与一个发光器件的第二发光部耦接。
在一些实施例中，所述像素电路的第二控制电路包括反馈子电路、输入子电路、第二驱动子电路、第三存储子电路、及调制子电路。所述发光基板还包括：与所述驱动背板耦接的电路板，所述电路板包括第三控制电路。所述第三控制电路包括比较子电路和信号转换子电路。所述比较子电路与第三数据信号端、反馈信号端、及第七节点耦接，被配置为，比较所述反馈信号端传输的反馈节点的电压与来自所述第三数据信号端的第三数据信号，并根据比较结果向所述第七节点输出调节电压。所述信号转换子电路与所述第七节点、接地电压端、及输入信号端耦接，被配置为根据所述第七节点的调节电压及所述接地电压端的电压，向所述输入信号端传输输入信号。其中，所述第三数据信号端被配置为传输用于控制所述第二发光部的灰阶的第三数据 信号。
在一些实施例中，所述比较子电路包括第一放大器，所述第一放大器包括第一正向输入端、第一负向输入端和第一输出端，所述第一正向输入端与所述反馈信号端耦接，所述第一负向输入端与所述第三数据信号端耦接，所述第一输出端与所述第七节点耦接。
所述信号转换子电路包括第二放大器和第四电容器。所述第二放大器具有第二正向输入端、第二负向输入端和第二输出端，所述第二正向输入端与所述接地电压端耦接，所述第二负向输入端与所述第七节点耦接，所述第二输出端与所述信号输入端耦接。所述第四电容器的一端与所述第二负向输入端耦接，所述第四电容器的第二端与所述第二输出端耦接。
在一些实施例中，所述比较子电路还包括第一电阻，所述第一电阻的一端与所述第一正向输入端电连接，所述第一电阻的二端与所述第一负向输入端电连接。所述信号转换子电路还包括第二电阻和第三电阻。所述第二电阻的一端与所述第七节点电连接，所述第二电阻的二端与所述第二负向输入端电连接。所述第三电阻的一端与所述接地电压端电连接，所述第三电阻的二端与所述第二正向输入端电连接。
又一方面，提供一种显示装置。所述显示装置包括上述任一实施例中所述的发光基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的示意图；
图2为图1中沿A-A的剖视图；
图3为发光器件的发光效率与电流密度的关系图；
图4A为图1中B的一种局部放大图；
图4B为图1中B的另一种局部放大图；
图5A为沿图4A中C-C的剖视图；
图5B为沿图4B中D-D的剖视图；
图6为根据一些实施例的像素电路的结构框图；
图7为根据一些实施例的第一控制电路的结构框图；
图8为根据一些实施例的第一控制电路的结构图；
图9为根据一些实施例的第二控制电路的结构框图；
图10为根据一些实施例的第二控制电路的结构图；
图11为根据一些实施例的像素电路的一种结构图；
图12为根据一些实施例的像素电路的一种控制时序图；
图13为根据一些实施例的第二控制电路及第三控制电路的结构框图；
图14为根据一些实施例的像素电路的另一种结构图；
图15为根据一些实施例的像素电路的另一种控制时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”或“示例(example)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协 作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的像素电路中所采用的晶体管可以为薄膜晶体管(英文：Thin Film Transistor；简称TFT)、场效应晶体管(英文：metal oxide semiconductor；简称MOS)或其他特性相同的开关器件，其中，本公开的实施例中均以薄膜晶体管为例进行说明。薄膜晶体管可以为P型晶体管或者N型晶体管，P型晶体管在低电位作用下导通，在高电位作用下截止；N型晶体管在高电位作用下导通，在低电位作用下截止。本公开的实施例中均以P型晶体管为例进行说明。
像素电路所采用的各薄膜晶体管的控制极为薄膜晶体管的栅极，第一极为薄膜晶体管的源极和漏极中一者，第二极为薄膜晶体管的源极和漏极中另一者。由于薄膜晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的薄膜晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，薄膜晶体管的第一极为源极，第二极为漏极。
像素电路中的第一节点、第二节点等并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
本公开的一些实施例提供了一种显示装置1000，参阅图1，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(英文：personal digital assistant；简称：PDA)、导航仪、可穿戴设备、增强现实(英文：Augmented Reality；简称：AR)设备、虚拟现实(英文：Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
在一些实施例中，显示装置1000包括发光基板1100，发光基板1100可以用作背光源或者直接用作显示图像。
参阅图2，图2为图1中沿A-A截取一个发光器件的剖面视图；发光基板1100包括多个发光器件100及驱动背板200。驱动背板200内包括多个用于驱动发光器件100发光的像素电路300，其中，每个像素电路300驱动一个发光器件100。
在发光基板1100用作背光源时，多个发光器件100可以发射相同颜色(波长大致相同)的光线，并且可以在发光基板1100的出光侧设置色转换层(比如：彩膜结构层)，发光器件100发射的光线经色转换层混色后形成所需显示的颜色。
在发光基板1100用作显示图像时，多个发光器件100可以发射不同颜色的光线，以使发光基板1100能够显示具有色彩的图像。示例性的，多个发光器件100可以包括发射红色光线的第一发光器件、发射绿色光线的第二发光器件、以及发射蓝色光线的第三发光器件。
在一些实施例中，显示装置1000可以为包括微型发光器件(比如：mini-LED或Micro LED)的显示装置。
参阅图3，微型发光器件(微型发光二极管)具有在高电流密度下发光效率高，在低电流密度下发光效率低的特性。具体表现为：在输入微型发光器件的电流密度(驱动电流)达到一定值时，微型发光器件的发光效率达到最高；在电流密度没有达到该值时，微型发光器件的发光效率一直处于爬坡阶段，即随着所提供的驱动电流的增大，微型发光器件的发光亮度逐渐增大，同时发光效率逐渐增大。
相关技术中，每个发光器件包括一个发光部，即每个发光器件包括一个发光区，像素电路通过控制流经该发光部的驱动电流的大小，来控制该发光部所显示的灰阶(亮度)。在发光器件显示低灰阶时，流经发光器件的驱动电流较小，电流密度较小，发光效率较低。
本公开的一些实施例提供了一种发光器件100，参阅4A和图5A，发光器件100包括层叠设置的第一半导体层120、发光功能层130及第二半导体层 140。
第一半导体层120包括第一半导体图案121和第二半导体图案122。
发光功能层130设置于第一半导体层120的沿厚度方向M1(图5A中的竖直方向)相对两侧中的一侧(图5A中仅示例性的展示了发光功能层130设置于第一半导体层120的上侧)。发光功能层130包括间隔设置的第一发光图案131和第二发光图案132，即第一发光图案131和第二发光图案132之间具有间隔，以使第一发光图案131和第二发光图案132能够形成两个独立的发光区。
第二半导体层140设置于发光功能层130远离第一半导体层120的一侧，包括间隔设置的第三半导体图案141和第四半导体图案142，即第三半导体图案141与第四半导体图案142之间电绝缘，以使第三半导体图案141和第四半导体图案142能够传输不同的电压信号。
示例性的，第一半导体层120可以为N型半导体层(N-GaN)，第二半导体层140可以为P型半导体层(P-GaN)，第一半导体图案121与第三半导体层141之间形成一个PN结，第二半导体图案122与第四半导体层142之间形成一个PN结。发光功能层130可以为多量子阱(英文：Multiple Quantum Well；简称：MQW)，在第一半导体层和第二半导体层之间形成具有势垒的PN结的情况下，少数载流子与多数载流子复合时会把多余的能量以光的形式释放出来，从而把电能直接转换为光能。
第一半导体图案121、第一发光图案131和第三半导体图案141在参考面上的正投影至少部分重叠，形成第一发光部D1。第二半导体图案122、第二发光图案132和第四半导体图案142在参考面上的正投影至少部分重叠，形成第二发光部D2。其中，参考面为平行于第一半导体层120的平面。
第一发光部D1工作(发光)时，需要在第一半导体图案121和第三半导体图案141上各输入一个电压信号，且输入第一半导体图案121上的电压信号与输入第三半导体图案141上的电压信号具有电压差。第二发光部D2工作时，需要在第二半导体图案122和第四半导体图案142上各输入一个电压信号，且输入第二半导体图案122上的电压信号与输入第四半导体图案142上的电压信号具有电压差。示例性的，在第一半导体层120为N型半导体层，第二半导体层140为P型半导体层的情况下，可以在第一半导体图案121和第二半导体图案122上各输入一个负电压，在第三半导体图案141和第四半导体图案142上各输入一个正电压。
由于第三半导体图案141与第四半导体图案142之间电绝缘，因此，可 以对第三半导体图案141和第四半导体图案142输入相同或者不同的电压信号，即第三半导体图案141与第一半导体图案121之间的电压差，可以与第四半导体图案142与第二半导体图案122之间的电压差相同或者不同，第一发光部D1和第二发光部D2可以各自独立工作，显示不同灰阶。基于此，可以在发光器件100显示低灰阶时，控制第一发光部D1和第二发光部D2中的一个工作，另一个不工作，即，通过一个发光部(第一发光部D1或第二发光部D2)显示低灰阶，这样，可以减小发光器件100显示低灰阶时的发光面积。与相关技术相比，在显示相同低灰阶时，本公开的实施例提供的发光器件100的发光面积更小，为了使发光器件100能够显示相同低灰阶，需要提升工作的发光部的电流大小，进而提升该发光部的电流密度，提升发光效率。
示例性的，在发光器件100显示低灰阶时，可以控制第一发光部D1发光，第二发光部D2不发光，这样，可以减小发光器件100整体的发光面积，并通过增加第一发光部D1的电流使发光器件100显示相应的灰阶，进而提升第一发光部D1的电流密度，提升第一发光部D1的发光效率。
在发光器件100需要显示高灰阶时，第一发光部D1和第二发光部D2同时工作，其中，第一发光部D1和第二发光部D2可以显示相同灰阶，或者显示不同灰阶。
示例性的，以发光器件100能够显示0～255灰阶为例，第一发光部D1能够显示0～127灰阶，而第二发光部D2只能显示0灰阶和127灰阶两个灰阶。发光器件100需要显示0～127灰阶时，第一发光部D1独立工作，第二发光部D2不工作，即第二发光部D2显示0灰阶，通过调节流经第一发光部D1的驱动电流，来调节第一发光部D1显示的灰阶，进而调节发光器件100显示的灰阶。发光器件100需要显示128～255灰阶时，第一发光部D1和第二发光部D2同时工作，且第二发光部D2显示127灰阶，这样，通过调节第一发光部D1显示的灰阶，来调节发光器件100显示的灰阶。
在一些实施例中，第一半导体图案121和第二半导体图案122电连接，且第三半导体图案141和第四半导体图案142被配置为传输不同的电压信号。这样，使第一发光部D1和第二发光部D2能够各自独立工作，使发光器件100能够在一个发光部工作的情况下显示低灰阶，在两个发光部一起工作时显示高灰阶。
在一些实施例中，参阅图5A，发光器件100还包括衬底110。第一半导体层120设置于衬底110的沿厚度方向M1的相对两侧中的一侧，第一半导体图案121和第二半导体图案122设置于同一衬底110上，发光功能层130位 于第一半导体层120远离衬底110的一侧，即衬底110设置于第一半导体层120远离发光功能层130的一侧。第一发光部D1和第二发光部D2属于同一个发光器件100，且第一发光部D1和第二发光部D2均设置于同一个衬底110上，一个发光器件100具有两个可以独立工作的发光部。
衬底110可以为蓝宝石(氧化铝，化学式为：Al 2O 3)衬底、碳化硅(化学式：SiC)衬底、硅(化学式：Si)衬底、磷化镓(化学式：GaP)衬底、或砷化镓(化学式：GaAs)衬底中的一种。
在发光器件100的制作过程中，通过磊晶工艺，在衬底110上依次形成第一半导体层120、发光功能层130、及第二半导体层140等，然后再在第二半导体层140上制作其他膜层形成发光器件100。但是，在将发光器件100转移至驱动背板200上形成发光基板1100过程中，可以将衬底110剥离(比如由Micro LED形成发光基板1100时，可以将衬底110剥离)，或者继续保留衬底110(比如由Mini-LED形成发光基板1100时，可以保留衬底110)。
在一些实施例中，参阅图5A，发光器件100还包括电极层150。电极层150设置于第二半导体层140远离第一半导体层120的一侧，包括间隔设置的第一电极151和第二电极152，即第一电极151和第二电极152电绝缘。第一电极151与第三半导体图案141电连接，被配置为向第三半导体图案141传输电压信号。第二电极152与第四半导体图案142电连接，被配置为向第四半导体图案142传输电压信号。示例性的，电极层150可以为透明导电层，比如电极层150可以是氧化铟锡(英文：Indium tin oxide；简称：ITO)层。
在一些实施例中，参阅图5A，发光器件110还包括钝化层160。钝化层160设置于第二半导体层140与电极层150之间，钝化层160中设置有第一过孔161和第二过孔162，第一电极151通过第一过孔161与第三半导体图案141电连接，第二电极152通过第二过孔162与第四半导体图案142电连接。其中，第一过孔161与第二过孔162在结构上可以是一样的。钝化层160能够将电极层150与第一半导体层120，及电极层150与发光功能层130隔离开，以使电极层150与第一半导体层120和发光功能层130均保持电绝缘。使来自第一电极151的电压信号能够传输至第三半导体图案141上，来自第二电极152的电压信号能够传输至第四半导体图案142上，第一发光部D1和第二发光部D2均能稳定、独立工作。
在一些实施例中，参阅图5A，发光器件100还包括至少一层绝缘层170和绑定电极层180。至少一层绝缘层170设置于电极层150远离第一半导体层120的一侧，绑定电极层180设置于至少一层绝缘层170远离电极层150的一 侧。
至少一层绝缘层170中设置有第三过孔1701和第四过孔1702。绑定电极层180包括第一绑定电极181和第二绑定电极182。第一绑定电极181通过第三过孔1701与第一电极电151连接，第二绑定电极182通过第四过孔1702与第二电极152电连接。
本公开的实施例中，电极层150远离第一半导体层120的表面凹凸不平，不利于发光器件100与驱动背板200内的像素电路进行绑定电连接。至少一层绝缘层170远离第一半导体层120的表面大致平坦，使绑定电极(包括第一绑定电极181和第二绑定电极182)远离第一半导体层120的表面平坦，有利于发光器件100与驱动背板200进行绑定连接，提升发光器件100与驱动背板200之间电连接的稳定性和可靠性。而且，至少一层绝缘层170可以保护电极层150，减弱或避免电极层150遭到侵蚀。
在一些实施例中，参阅图5A，至少一层绝缘层170可以包括反射层171、散热层172和封装层173中的至少一层。示例性的，至少一层绝缘层170包括反射层171、散热层172和封装层173。
其中，反射层171能够在第一发光部D1和第二发光部D2远离衬底110的一侧形成大致为锥形的反射罩，进而将第一发光部D1和第二发光部D2发射的射向发射层170一侧的光线反射至由发光器件100的出光面(第一发光部D1和第二发光部D2远离绑定电极层180的一侧)射出，从而提升发光器件100的出光效率。
当发光器件100长时间工作时，第一发光部D1和第二发光部D2的温度会逐渐升高，随着温度的升高，第一发光部D1和第二发光部D2的发光效率会发生下降。散热层172能够将第一发光部D1和第二发光部D2散发的热量吸收并传导至发光器件100的外部，有利于降低第一发光部D1和第二发光部D2的工作温度，提升发光器件100的发光效率。
封装层173能够起到保护反射层171和散热层172的作用，同时能够形成大致平坦的表面，有利于绑定电极层180的设置。
在一些实施例中，参阅图4A和图5A，至少一层绝缘层170中还设置有至少一个第五过孔1703。绑定电极层180还包括第三绑定电极183，第三绑定电极183通过至少一个第五过孔1703与第一半导体图案121及第二半导体图案122电连接。
在一些实施例中，发光部(第一发光部D1或第二发光部D2)显示的灰阶与流经该发光部的驱动电流相关，流经该发光部的驱动电流与输入在该发 光部的两个半导体图案上的电压差正相关。第一半导体图案121和第二半导体图案122电连接，可以通过控制输入第三半导体图案141和第四半导体图案142的电压，控制两个发光部各自独立工作，这样，能够简化发光器件100的像素电路300，降低驱动背板200的制作难度，降低驱动背板200的制作成本。
在一些实施例中，参阅图4A和图5A，其中，图4A和图5A为第一半导体图案121和第二半导体图案122间隔设置时发光器件100的结构图。第一半导体图案121和第二半导体图案122电连接，可以是第一半导体图案121与第二半导体图案122间隔设置，第三绑定电极183通过两个第五过孔1703中的一个第五过孔1703与第一半导体图案121电连接，通过两个第五过孔1703中的另一个第五过孔1703与第二半导体图案122电连接。这样，有利于减小第一半导体图案121和第二半导体图案122的面积，有利于提升发光器件100的出光效率。
在一些实施例中，参阅图4B和图5B，其中，图4B和图5B为第一半导体图案121和第二半导体图案122一体设置时发光器件100的结构图。第一半导体图案121和第二半导体图案122电连接，还可以是第一半导体图案121和第二半导体图案122一体设置，即第一半导体图案121和第二半导体图案122之间没有间隔，第三绑定电极183可以通过一个或者多个第五过孔1703与第一半导体图案121及第二半导体图案122电连接。这样，第一半导体层120的图案更加简单，且能够减少一个第五过孔1703，有利于简化发光器件100的制作工艺，降低发光器件100的制作成本。
需要说明的是，在本公开的实施例中，仅介绍了显示装置1000中与本公开的实施例的方案相关的部分结构，对于未示出的已知结构，本领域技术人员能够获知，故不再赘述。示例性的，显示装置1000还可以包括偏光片，驱动芯片等。
在一些实施例中，驱动背板200所包含的像素电路300，包括第一控制电路310和第二控制电路320。第一控制电路310被配置为驱动上述任一实施例中所述的发光器件100中的第一发光部D1和第二发光部D2中的一者，第二控制电路320被配置为驱动上述任一实施例中所述的发光器件100中的第一发光部D1和第二发光部D2中的另一者。以下，以第一控制电路310驱动第一发光部D1，第二控制电路320驱动第二发光部D2为例进行说明。
参阅图6，第一控制电路310与第一扫描信号端GATE1、第一数据信号端DATA1、第一电压信号端VDD、及发光器件100的第一发光部D1耦接， 被配置为在来自第一扫描信号端GATE1的第一扫描信号Gate1和来自第一数据信号端DATA1的第一数据信号Data1的控制下，将第一电压信号端VDD与第一发光部D1之间的线路导通，并控制第一发光部D1的亮度在第一灰阶和第二灰阶之间切换。
本公开的实施例提供的第一控制电路310，能够将第一电压信号端VDD与第一发光部D1之间的线路导通或者中断，第一电压信号端VDD与第一发光部D1之间的线路导通时，第一发光部D1工作，并且显示第一灰阶；由于不能调节流经第一发光部D1的电流，因此，在第一发光部D1工作，且发光器件100显示不同灰阶时，第一发光部D1显示的灰阶相同。第一电压信号端VDD与第一发光部D1之间的线路中断时，第一发光部D1不发光，即第一发光部D1显示第二灰阶(0灰阶)。
第二控制电路320与第一扫描信号端GATE1、第一电压信号端VDD、及发光器件100的第二发光部D2耦接，被配置为在来自第一扫描信号端GATE1的第一扫描信号Gate1的控制下，将第一电压信号端VDD与第二发光部D2之间的线路导通，并控制流经第二发光部D2的驱动电流的大小。
本公开的实施例提供的第二控制电路320，能够将第一电压信号端VDD与第二发光部D2之间的线路导通，使第二发光部D2发光，并且可以通过控制流经第二发光部D2的驱动电流的大小，控制第二发光部D2显示不同的灰阶。
本公开的实施例提供的像素电路300，能够控制第一发光部D1和第二发光部D2各自独立工作，而且可以控制第一发光部D1工作或者不工作(不发光)，并控制第二发光部D2显示的灰阶。基于此，像素电路300可以控制发光器件100在显示低灰阶时，第一发光部D1不工作，第二发光部D2工作；即仅通过第二发光部D2显示低灰阶。这样，可以减小发光器件100显示低灰阶时的发光面积，与相关技术相比，在显示相同低灰阶时，本公开的实施例提供的发光器件100的发光面积更小，为了使发光器件100能够显示相同低灰阶，需要提升第二发光部D2的电流大小，进而提升第二发光部D2的电流密度，提升第二发光部D2的发光效率。同时，第一发光部D1工作(发光)时，显示固定灰阶，为了配合第二发光部D2显示全灰阶，上述固定灰阶通常为高灰阶，此时，第一发光部D1本身的发光效率可以处于较高的水平。
示例性的，在发光器件100需要显示低灰阶时，第一控制电路310将第一电压信号端VDD与第一发光部D1之间的线路中断，第一发光部D1不发光；同时，第二控制电路320将第一电压信号端VDD与第二发光部D2之间 的线路导通，并且通过控制流经第二发光部D2的驱动电流的大小，控制第二发光部D2显示不同低灰阶，进而使发光器件100显示不同灰阶。
示例性的，在发光器件100需要显示高灰阶时，第一控制电路310将第一电压信号端VDD与第一发光部D1之间的线路导通，第一发光部D1发光，且在发光器件100显示不同的高灰阶时，流经第一发光部D1的驱动电流相同，即第一发光部D1工作时(发光时)显示的灰阶是固定的。这样，第一控制电路310仅需要控制第一电压信号端VDD与第一发光部D1之间的线路导通与否，有利于简化第一控制电路310的结构，进而简化像素电路300的结构，有利于提升驱动背板200中的像素电路300的密度。同时，第二控制电路320将第一电压信号端VDD与第二发光部D2之间的线路导通，并且通过控制流经第二发光部D2的驱动电流的大小，控制第二发光部D2显示不同灰阶，进而控制发光器件100显示不同灰阶。
本公开的实施例提供的像素电路300，被配置为驱动上述任一实施例所述的发光器件100，在提升发光器件100的发光效率的同时，可以降低像素电路300在驱动发光器件100显示低灰阶时的能耗，降低像素电路300的能耗。
需要理解的是，第一发光部D1和第二发光部D2均包括阳极电压端和阴极电压端，第一控制电路310用于与第一发光部D1的阳极电压端电连接，第二控制电路320用于与第二发光部D2的阳极电压端电连接。此外，第一发光部D1和第二发光部D2的阴极电压端还可以同一个阴极电压信号端VSS电连接，阴极电压信号端VSS可以为第一发光部D1的阴极电压端和第二发光部D2的阴极电压端提供负电压，或者阴极电压信号端VSS也可以直接接地。
示例性的，在发光器件100包括绑定电极层18的情况下，第一控制电路310可以与第一绑定电极181电连接，第二控制电路320可以与第二绑定电极182电连接，阴极电压信号端VSS可以与第三绑定电极183电连接。
第一控制子电路310和第二控制子电路320共用相同的电压信号端(比如第一电压信号端VDD、阴极电压信号端VSS、及第一扫描信号端GATE1等)，能够简化驱动背板200的线路布置，降低驱动背板200的制作难度，降低发光基板1100的制作成本；同时，能够简化像素电路300的复杂程度，降低像素电路300的控制难度。
在一些实施例中，参阅图7，第一控制电路310包括第一数据写入子电路311、开关控制子电路312、及第一存储子电路313。
第一数据写入子电路311与第一扫描信号端GATE1、第一数据信号端DATA1、及第一节点N1耦接，被配置为在来自第一扫描信号端GATE1的第 一扫描信号Gate1的控制下，将来自第一数据信号端DATA1的第一数据信号Data1传输至第一节点N1。
开关控制子电路312与第一节点N1、第一电压信号端VDD、及第一发光部D1耦接，被配置为在第一节点N1的电压的控制下，将第一电压信号端VDD与第一发光部D1之间的线路导通。
第一存储子电路313与第一电压信号端VDD及第一节点N1耦接，被配置为存储并维持第一节点N1的电压。
参阅图8和图12，第一发光部D1的一个帧周期内，包括复位阶段t1、扫描阶段t2、和发光阶段t2。
在复位阶段t1，第一扫描信号端GATE1的第一扫描信号Gate1为低电平信号，第一晶体管T1关闭。
在扫描阶段t2，在第一扫描信号Gate1的控制下，将第一数据信号Data1传输至第一节点N1。其中，第一数据信号Data1既可以是控制开关控制子电路312打开的信号，也可以是控制开关控制子电路312关闭的信号。
在发光阶段，开关控制子电路312在第一节点N1的第一数据信号Data1的控制下，将第一电压信号端VDD与第一发光部D1之间的线路导通或者中断。同时，第一存储子电路313维持第一节点N1的电压使第一发光部D1在一帧周期内的发光状态保持稳定。
在一些实施例中，在发光器件100需要显示低灰阶时，第一数据信号Data1可以是将第一电压信号端VDD与第一发光部D1之间的线路中断的信号。在发光器件100需要显示高灰阶时，第一数据信号Data1可以是将第一电压信号端VDD与第一发光部D1之间的线路导通的信号。
在一些实施例中，参阅图8，第一数据写入子电路311包括第一晶体管T1，第一晶体管T1的控制极与第一扫描信号端GATE1耦接，第一晶体管T1的第一极与第一数据信号端DATA1耦接，第一晶体管T1的第二极与第一节点N1耦接。
开关控制子电路312包括第二晶体管T2，第二晶体管T2的控制极与第一节点N1耦接，第二晶体管T2的第一极与第一电压信号VDD端耦接，第二晶体管T2的第二极与第一发光部D1耦接。
第一存储子电路313包括第一存储电容器C1，第一存储电容器C1的第一端与第一节点N1耦接，第一存储电容器C1的第二端与第一电压信号端VDD耦接。
第一控制电路310仅包括两个晶体管和一个电容器，结构简单，有利于 降低第一控制电路310的占用的空间，提升驱动背板200的像素电路300的密度。
第二控制电路320不仅需要控制第一电压信号端VDD与第二发光部D2之间的线路的导通，还需要控制流经第二发光部D2的驱动电流，因此，需要更加精准的控制输入第二发光部D2的电流大小。由于电路本身的结构(比如晶体管、电容)会产生一定的电能损耗，比如驱动晶体管的阈值电压，因此需要对第二像素电路320中可能出现的电路本身的损耗进行补偿。第二控制电路320可以采用内部补偿技术的电路或者采用外部补偿技术的电路。
在一些实施例中，第二控制电路320可以是采用内部补偿技术的电路。这样，参阅图9，第二控制电路320包括：第二数据写入子电路321、第二存储子电路322、第一驱动子电路323、补偿子电路324、电压控制子电路325、发光控制子电路326、及初始化子电路327。
第二数据写入子电路321第一扫描信号端GATE1、第二数据信号端DATA2、及第二节点N2耦接，被配置为在来自第一扫描信号端GATE1的第一扫描信号Gate1的控制下，将来自第二数据信号端DATA2的第二数据信号Data2传输至第二节点N2。
第二存储子电路322与第二节点N2及第三节点N3耦接，被配置为存储第二节点N2的电压，并调节第三节点N3的电压。
第一驱动子电路323与第三节点N3、第一电压信号端VDD、及第四节点N4耦接，被配置为在第三节点N3的电压控制下，将来自第一电压信号端VDD的第一电压信号Vdd传输至第四节点N4。
补偿子电路324与第一扫描信号端GATE1、第四节点N4、及第三节点N3耦接，被配置为在来自第一扫描信号端GATE1的第一扫描信号Gate1的控制下，将第一驱动子电路323的阈值电压Vth补偿至第三节点N3。
电压控制子电路325与第二扫描信号端GATE2、第二电压信号端VINIT、及第二节点N2耦接，被配置为在来自第二扫描信号端GATE2的第二扫描信号Gate2的控制下，将来自第二电压信号端VINIT的第二电压信号Vinit传输至第二节点N2。
发光控制子电路326与使能信号端EM、第四节点N4、及第二发光部D2耦接，被配置为在来自使能信号端EM的使能信号Em的控制下，将第四节点N4的电压传输至第二发光部D2。
初始化子电路327与复位信号端RESET、第二电压信号端V2、及第二节点N2耦接，被配置为在来自复位信号端RESET的复位信号的控制下，将 来自第二电压信号端V2的第二电压信号Vinit传输至第二节点N2。
参阅图9和图12，第一发光部和第二发光部D2的一个帧周期均包括复位阶段t1、扫描阶段t2、和发光阶段t3。
在复位阶段t1，初始化子电路327将第二节点N2的电压初始化。
在扫描阶段t2，第二数据写入子电路321将第二数据信号Data2传输至第二节点，第二存储子电路322存储第二节点N2的电压，补偿子电路324将第一驱动子电路323的阈值电压V th补偿至第三节点N3。第二节点N2的电压为V Data2，第三节点N3的电压为V DD+V th。
在发光阶段t3，电压控制子电路325将第二电压信号Vinit传输至第二节点N2，第二节点N2电压跃变至V GL(即Vinit)，此时，在第二存储子电路322的作用下，第三节点N3的电压跃变为：V N3＝[V DD+V th-(V Data2-V GL)]。第一驱动子电路323处于饱和状态。V DD-V N3＝V DD-[V DD+V th-(V Data2-V GL)]＝V data-V GL-V th为第二发光部D2提供驱动电流；第二发光部D2的驱动电流为ID2。I D2＝K(V N3-VDD-V th) 2＝K(V Data2-V GL) 2；其中，V DD为第一电压信号端VDD提供的电压；V N3-VDD为第三节点N3的电压与第一电压信号端VDD之间的电压差，K为工艺设计有关的常数。由此可以看到第二发光部D2的驱动电流I D2与第二存储子电路322的阈值电压V th无关，第二发光部D2的在一个帧周期的发光阶段，发光稳定。
第一控制电路310通过补偿子电路324将第一驱动子电路323的阈值电压V th补偿至第一驱动子电路323的栅极(第三节点N3)进而消除第四晶体管T4的阈值电压V th对第一控制电路的影响。
需要理解的是，驱动背板200所包括的多个像素电路300排列成多行和多列，每行像素电路300均设置有至少一条扫描信号线，至少一条扫描信号线可以为该行的多个像素电路300提供扫描信号，多行像素电路300采用逐行扫描的方式进行控制。在一些实施例中，任一行像素电路300的复位信号端VINIT可以与上一行像素电路300扫描信号线连接，第二扫描信号端GATE2可以与下一行像素电路300的扫描信号线电连 接，这样，可以简化扫描信号线的布置，有利于降低驱动背板200的制作难度，进而降低发光基板1100的制作成本。
在一些实施例中，参阅图10，第二数据写入子电路321包括第三晶体管T3，第三晶体管T3的控制极与第一扫描信号端GATE1耦接，第三晶体管T3的第一极与第二数据信号端DATA2耦接，第三晶体管T3的第二极与第二节点N2耦接。
第二存储子电路322包括第二存储电容器C2，第二存储电容器C2的第一端与第二节点N2电连接，第二存储电容器C2的第二端与第三节点电N3连接。
第一驱动子电路323包括第四晶体管T4，第四晶体管T4的控制极与第三节点N3耦接，第四晶体管T4的第一极与第一电压信号端VDD耦接，第四晶体管T4的第二极与第四节点N4耦接。
补偿子电路324包括第五晶体管T5，第五晶体管T5的控制极与第一扫描信号端GATE1耦接，第五晶体管T5的第一极与第四节点N4耦接，第五晶体管T5的第二极与第三节点N3耦接。
电压控制子电路325包括第六晶体管T6，第六晶体管T6的控制极与第二扫描信号端GATE2耦接，第六晶体管T6的第一极与第二电压信号端V2耦接，第六晶体管T6的第二极与第二节点N2耦接。
发光控制子电路326包括第七晶体管T7，第七晶体管T7的控制极与使能信号端EM耦接，第七晶体管T7的第一极与第四节点N4耦接，第七晶体管T7的第二极与第二发光部D2耦接。
复位子电路327包括第八晶体管T8，第八晶体管T8的控制极与复位信号端RESET耦接，第八晶体管T8的第一极与初始化信号端VINIT耦接，第八晶体管T8的第二极与第二节点N2耦接。
示例性的，参阅图11和图12，在初始化阶段t1，复位信号端RESET提供低电平信号，第一扫描信号端GATE1、第二扫描信号端GATE2、及使能信号端EM提供高电平信号，第八晶体管T8打开，其余晶体管关闭，将第二存储电容器C2的电压初始化。
在扫描阶段t2，第一扫描信号端GATE1提供低电平信号，复位信号端RESET、第二扫描信号端GATE2、及使能信号端EM提供高电平信号，第一晶体管T1、第三晶体管T3、及第五晶体管T5打开，其余晶体管关闭，第一节点N1写入第一数据信号Data1，第二节点N2写入第二数据信号Data2，第四晶体管T4的阈值电压V th补偿至第三节点N3。
在发光阶段，第二扫描信号端GATE2及使能信号端EM提供低电平信号，复位信号端RESET及第一扫描信号端GATE1提供高电平信号。在第二控制电路320中，第六晶体管T6、第四晶体管T4、第七晶体管T7打开，其余晶体管关闭。第二节点N2电压跃迁至V GL，第三节点N3的电压随之跃迁至
Figure PCTCN2021097478-appb-000001
然后，第四晶体管T4在第三节点N3的电压的控制下，驱动第二发光部D2工作。在第一控制电路310中，若第一数据信号Data1为低电平信号,第二晶体管T2打开，第一发光部D1显示第一灰阶，发光器件100显示高灰阶；若第一数据信号Data1为高电平信号,第二晶体管T2截止，第一发光部D1显示第二灰阶(0灰阶)，发光器件100显示低灰阶。
在一些实施例中，第二控制电路320可以是采用外部补偿技术的电路。这样，参阅图13，第二控制电路320包括反馈子电路328、输入子电路329、第二驱动子电路3210、第三存储子电路3211及调制子电路3212。
反馈子电路328与第一扫描信号端GATE1、反馈信号端M1、及反馈节点N0耦接，被配置为在来自第一扫描信号端GATE1的第一扫描信号Gate1的控制下，将反馈节点N0的电压传输至反馈信号端M1。
其中，反馈节点N0与第二发光部D2耦接，即通过反馈节点N0的电压控制输入第二发光部D2的电压。因此，通过调节反馈节点N0的电压，即可控制第二发光部D2的驱动电流，进而控制第二发光部D2显示的灰阶。
输入子电路329与第一扫描信号端GATE1、输入信号端M2、及第五节点N5耦接，被配置为在来自第一扫描信号端GATE1的第一扫描信号Gate1的控制下，将来自输入信号端M1的输入信号传输至第五节点N5。
其中，输入信号根据反馈节点N0的电压和用于控制第二发光部D2的灰阶的第三数据信号Data3生成。第三数据信号Data3用于控制第二发光部D2显示的灰阶，即需要将反馈节点N0的电压调节至与第三数据信号Data3相同，以使第二发光部D2能够根据第三数据信号Data3显示相应的灰阶。基于此，可以根据反馈节点N0和第三数据信号Data3的电压，通过输入子电路329向第五节点输入一个输入信号。
第二驱动子电路3210与第五节点N5、第六节点N6、及反馈节点N0耦接，被配置为在第五节点N5的电压的控制下，根据第六节点N6的电压信号，调节反馈节点N0的电压。
其中，在输入子电路329输入第五节点N5的输入信号的控制下，可以调节第二驱动子电路3210的阻抗，进而调节第二驱动子电路3210分担(消耗) 的电压，然后调节反馈节点N0的电位，直至反馈节点N0的电压与第三数据信号Data3的电压一致。
第三存储子电路3211与第一电压信号端VDD及第五节点N5耦接，被配置存储并维持第五节点N5的电压。
第三存储子电路3211用于在一帧内的发光阶段，维持第五节点N5的电压，进而使的反馈节点N0的电压保持稳定，第二发光部D2能够稳定发光。
调制子电路3212与第三扫描信号端G3、第一电压信号端VDD、及第六节点N6耦接，被配置为在来自第三扫描信号端G3的第三扫描信号Gate的控制下，将来自第一电压信号端VDD的第一电压信号Vdd传输至第六节点N6，并对第一电压信号端VDD与第二发光部D2之间的线路的导通时间进行调制。
在第二发光部D2显示低灰阶时，如果第二发光部D2在一帧内的发光阶段持续发光，第二发光部D2所需的电流较小，反馈节点N0所需的电压较小，这样，会导致第二驱动子电路3210分担的电压较大，第二控制电路320本身的电能损耗较多。调制子电路3212将第一电压信号端VDD与第六节点N6之间的线路导通，并通过控制该线路导通的时间长度，控制第二发光部D2的发光时长，即，调制子电路3212能够通过降低第二发光部D2的发光时长，提升第二发光部D2所需的电流，进而提升第二节点N2所需的电压，减小第二控制电路320本身的电能损耗，降低发光基板1100的功耗。
示例性的，参阅图15，当第二发光部D2需要显示较低灰阶时，在发光阶段t2，第三扫描信号端GATE3的第三扫描信号Gate3可以是交替的高电平和低电平信号，这样可以降低第二发光部D2的发光时长，以提升第二发光部D2发光时的电流，提升第二发光部D2的电流密度，及第二发光部D2的发光效率。
示例性的，在第二发光部D2需要显示较高灰阶时，在发光阶段t2，第三扫描信号端GATE3的第三扫描信号Gate3可以是持续高电平，这样可以通过增加第二发光部D2的发光时长，来减小第二发光部D2发光时的电流，避免通过第二发光部D2的电流过大，降低第二控制电路320的负荷。
在一些实施例中，在第二控制电路320是采用外部补偿技术的电路的情况下，即在像素电路300的第二控制电路320包括反馈子电路328、输入子电路329、第二驱动子电路3210、第三存储子电路3211、及调制子电路3212时。参阅图13，发光基板1100至少还包括电路板(图中未示出)，电路板与驱动背板200电连接。电路板包括第三控制电路400。
第三控制电路400被配置为根据反馈信号端M0接收到的反馈节点N0的 电压和第三数据信号Data3，向第五节点N5输出一个用于调节第五节点电压的输入信号。
在一些实施例中，参阅图13，第三控制电路400包括比较子电路410和信号转换子电路420。
比较子电路410与第三数据信号端DATA3、反馈信号端M1、及第七节点N7耦接，被配置为，比较来自反馈信号端M1传输的反馈节点N0的电压与来自第三数据信号端DATA3的第三数据信号Data3，并根据比较结果向第七节点N7输出调节电压。其中，第三数据信号端DATA3被配置为传输用于控制第二发光部D2的灰阶的第三数据信号Data3。
信号转换子电路420与第七节点N7、接地电压端GND、及输入信号端M2耦接，被配置为根据第七节点N7的调节电压及接地电压端GND的电压，向输入信号端M2传输用于调节第五节点N5的电压的输入信号。
本公开的实施例提供的采用外部补偿技术的第二控制电路，在扫描阶段，在反馈子电路328的控制下，将反馈节点N0的电压传输至反馈节点M1。比较子电路410接收并且比较由反馈信号端M1接收到的反馈节点N0的电压V N0与接收到的来自第三数据信号端DATA3的第三数据信号Data3的电压V Data3，然后根据比较结果向第七节点N7输出一个调节电压。信号转换子电路420根据从第七节点N7接收到的调节电压向输入信号端M2输出一个输出信号V M2。然后在输入子电路329控制下，将输出信号V M2输出至第五节点N5。通过第五节点N5的电压控制第二驱动子电路3210分担的电压，进而调节反馈节点N0的电压。其中，第二驱动子电路3210分担的电压与反馈节点N0的电压之和等于第一电压信号端VDD提供的电压。
由于第三控制电路400能够直接调节第二发光部D2的阳极电压(反馈节点N0直接与第二发光部D2的阳极电压端电连接)，以使第二发光部D2的阳极电压与第三数据信号端DATA3的第三数据信号Data3的电压一致，因此无需对第二驱动子电路3210的阈值电压进行补偿，使第二驱动子电路3210可以工作在线性区。
在一些实施例中，参阅图13和图14，反馈子电路328包括第九晶体管T9，第九晶体管T9的控制极与第一扫描信号端GATE1耦接，第九晶体管T9的第一极与反馈节点N0耦接，第九晶体管T9的第二极与反馈信号端M1耦接。
输入子电路329包括第十晶体管T10，第十晶体管T10的控制极与第一扫描信号端GATE1耦接，第十晶体管T10的第一极与输入信号端M2耦接， 第十晶体管T10的第二极与第五节点N5耦接。
第二驱动子电路3210包括第十一晶体管T11，第十一晶体管T11的控制极与第五节点N5耦接，第十一晶体管T11的第一极与第六节点N6耦接，第十一晶体管T11的第二极与反馈节点N0耦接。
第三存储子电路3211包括第三电容器C3，第三电容器C3的第一端与第一电压信号端VDD耦接，第三电容器C3的第二端与第五节点N5耦接。
调制子电路3212包括第十二晶体管T12，第十二晶体管T12的控制极与第三扫描信号端G3耦接，第十二晶体管T12的第一极与第一电压信号端VDD耦接，第十二晶体管T12的第二极与第六节点N6耦接。
在一些实施例中，参阅图13和图14，比较子电路410包括第一放大器OP1，第一放大器OP1包括第一正向输入端I1、第一负向输入端I2和第一输出端O1，第一正向输入端I1与反馈信号端M1耦接，第一负向输入端I2与第三数据信号端DATA2耦接，第一输出端O1与第七节点N7耦接。
信号转换子电路420包括第二放大器OP2和第四电容器C4。第二放大器OP2具有第二正向输入端I3、第二负向输入端I4和第二输出端O2，第二正向输入端I3与接地电压端GND耦接，第二负向输入端I4与第七节点N7耦接，第二输出端O2与信号输入端M2耦接。第四电容器C4的一端与第二负向输入端I4耦接，第四电容器C4的第二端与第二输出端O2耦接。
示例性的，参阅图14和图15，一个帧周期包括扫描阶段t2和发光阶段t3。
在扫描阶段t2：
第一数据信号端DATA1开始输出第一数据信号Data1，第一扫描信号端Gate1为低电平信号，第一晶体管T1打开，来自第一数据信号端DATA1的第一数据信号Data1传输至第一节点N1。其中，第一数据信号Data1可以是低电平信号(用于显示高灰阶)或者高电平信号(用于显示低灰阶)。
第二数据信号端DATA2开始输出第二数据信号Data2。第九晶体管T9、和第十晶体管T10打开，反馈节点N0的电压传输至第一放大器OP1的第正向输入端I1，来自第三数据信号端DATA3的第三数据信号Data3传输至第一放大器OP1的第一负向输入端I2。第一放大器OP1根据反馈节点N0的电压和第三数据信号Data3，向第七节点N7传输一个调节电压。第四电容器C4根据从第七节点N7接收到的调节电压充电或者放电，改变第二放大器OP的第二输出端O2的电压，即，改变第五节点N5的电压，进而控制第十一晶体管T11的栅极电极，控制第十一晶体管T11的阻抗，调节第十一晶体管T11 的分压，实现调节反馈节点N0的电压的目的；直至将反馈节点N0的电压调至与第三数据信号Data3的电压相同。
示例性的，反馈节点N0的电压(第二发光部D2的阳极电压)V N0小于第三数据信号端DATA3的第三数据信号Data3的电压V Data3时，第一放大器OP1的第一输出端O1输出一低电平(负值的电压信号)的调节电压；第四电容器C4一端电位下降，第四电容器C4开始放电，第二输出端O2输出一个低电平电压信号，第五节点N5的电压降低，第十一晶体管T11的阻抗变小，第十一晶体管T11分担的电压降低，反馈节点N0的电压升高，直至反馈节点N0的电压V N0与第三数据信号Data3的电压V Data3相等。
在发光阶段t3：
第一发光部D1根据第一数据信号Data1，工作(发光)或者不工作(不发光)。示例性的，在第一数据信号Data1为低电平信号时，第一发光部D1工作；在第一数据信号Data1为高电平信号时，第一发光部D1不工作。
第三扫描信号端GATE3提供间断的或者持续的低电平信号。第二发光部D2在第三扫描信号端GATE3提供低电平信号时发光，在第三扫描信号端GATE3提供高电平信号时不发光。
在一些实施例中，同一列的多个像素电路300的反馈信号端M1与同一个第三控制电路400的第一放大器OP1的第一正向输入端I1耦接；同一列的多个像素电路300的输入信号端M2与同一个第三控制电路400的第二输出端O2耦接；即，同一列的多个像素电路300与同一个第三控制电路400耦接。
在一些实施例中，参阅图14，比较子电路410还包括第一电阻R1，第一电阻R1的一端与第一正向输入端I1电连接，第一电阻R1的二端与第一负向输入端I2电连接。发光基板1100工作时，相邻两个帧周期之间，第三数据信号端DATA3会有空白(Blank)阶段，该阶段第一放大器OP1的第一负向接入端I2处于浮接状态，第一电阻R1能够减弱甚至消除上述噪声。示例性的，第一电阻R1的电阻值一般设置的比较大，比如可以是1KΩ、2KΩ等。
需要理解的是，在其他一些实施例中，也可以不设置第一电阻R1。
信号转换子420电路还包括第二电阻R2和第三电阻R3。第二电阻R2的一端与第七节点N7电连接，第二电阻R2的二端与第二负向输入端I4电连接。第三电阻R3的一端与接地电压端GND电连接，第三电阻R3的二端与第二正向输入端I3电连接。
在一些实施例中，参阅图14，反馈信号端M1与第一正向输入端I1之间的线路本身具有电阻RL1，且该线路可能会与发光基板1100中的其他线路形 成电容CL1；同理，输入信号端M2与第而输出端OUT2之间的线路本身具有电阻RL2，且该线路可能会与发光基板1100中的其他线路形成电容CL2。即在图中，RL1、CL1、RL2、CL2为线路本身产生的电容和电阻。在其他一些示意性附图中，也可以不展示RL1、CL1、RL2、CL2等结构。示例性的，RL1和CL1的乘积等于RL2和CL2的乘积，以使第四电容C4的充放电速率和第一放大器OP1获取反馈节点N0的电压的速率相同，使第四电容C4充放电稳定。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种发光器件，包括：
    第一半导体层，包括第一半导体图案和第二半导体图案；
    发光功能层，设置于所述第一半导体层的沿厚度方向相对两侧中的一侧，包括间隔设置的第一发光图案和第二发光图案；
    第二半导体层，设置于所述发光功能层远离所述第一半导体层的一侧，包括间隔设置的第三半导体图案和第四半导体图案；
    其中，所述第一半导体图案、所述第一发光图案和所述第三半导体图案在参考面上的正投影至少部分重叠，形成第一发光部；所述第二半导体图案、所述第二发光图案和所述第四半导体图案在参考面上的正投影至少部分重叠，形成第二发光部；所述参考面为平行于所述第一半导体层的平面；
    所述第一半导体图案和第二半导体图案电连接。
  2. 根据权利要求1所述的发光器件，还包括：
    电极层，设置于所述第二半导体层远离所述第一半导体层的一侧，包括间隔设置的第一电极和第二电极；
    所述第一电极与所述第三半导体图案电连接，所述第二电极与所述第四半导体图案电连接。
  3. 根据权利要求2所述的发光器件，还包括：
    钝化层，设置于所述第二半导体层与所述电极层之间；所述钝化层中设置有第一过孔和第二过孔，所述第一电极通过所述第一过孔与所述第三半导体图案电连接，所述第二电极通过所述第二过孔与所述第四半导体图案电连接。
  4. 根据权利要求2或3所述的发光器件，还包括：
    至少一层绝缘层，设置于所述电极层远离所述第一半导体层的一侧，所述至少一层绝缘层中设置有第三过孔和第四过孔；
    绑定电极层，设置于所述至少一层绝缘层远离所述电极层的一侧，包括第一绑定电极和第二绑定电极；所述第一绑定电极通过所述第三过孔与所述第一电极电连接，所述第二绑定电极通过所述第四过孔与所述第二电极电连接。
  5. 根据权利要求4所述的发光器件，其中，所述至少一层绝缘层中还设置有至少一个第五过孔；
    所述绑定电极层还包括第三绑定电极，所述第三绑定电极通过所述至少一个第五过孔与所述第一半导体图案及所述第二半导体图案电连接。
  6. 根据权利要求1～5中任一项所述的发光器件，其中，所述第一半导体图案和所述第二半导体图案间隔设置。
  7. 根据权利要求6所述的发光器件，其中，所述发光器件包括至少一层绝缘层和绑定电极层，所述至少一层绝缘层中设置有两个第五过孔，所述绑定电极层包括第三绑定电极；
    所述第三绑定电极通过两个第五过孔中的一个与所述第一半导体图案电连接，所述第三绑定电极通过两个第五过孔中的另一个与所述第二半导体图案电连接。
  8. 根据权利要求1～5中任一项所述的发光器件，其中，所述第一半导体图案和所述第二半导体图案一体设置。
  9. 根据权利要求4～8中所述的发光器件，其中，所述发光器件包括至少一层绝缘层；
    所述至少一层绝缘层包括反射层、散热层和封装层中的至少一层。
  10. 根据权利要求1～9中任一项所述的发光器件，还包括：
    衬底，所述第一半导体层设置于所述衬底的沿厚度方向相对两侧中的一侧，所述第一半导体图案和所述第二半导体图案设置于同一衬底上，且所述发光功能层设置于所述第一半导体层远离所述衬底的一侧。
  11. 根据权利要求1～10中任一项所述的发光器件，其中，所述第三半导体图案和所述第四半导体图案被配置为传输不同的电压信号。
  12. 一种像素电路，被配置为驱动如权利要求1～11中任一项所述的发光器件，包括：
    第一控制电路，与第一扫描信号端、第一数据信号端、第一电压信号端、及所述发光器件的第一发光部耦接，被配置为在来自所述第一扫描信号端的第一扫描信号和来自所述第一数据信号端的第一数据信号的控制下，将所述第一电压信号端与所述第一发光部之间的线路导通，并控制所述第一发光部的亮度在第一灰阶和第二灰阶之间切换；
    第二控制电路，与所述第一扫描信号端、所述第一电压信号端、及所述发光器件的第二发光部耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将所述第一电压信号端与所述第二发光部之间的线路导通，并控制流经所述第二发光部的驱动电流的大小。
  13. 根据权利要求12所述的像素电路，所述第一控制电路包括：
    第一数据写入子电路，与所述第一扫描信号端、所述第一数据信号端、及第一节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控 制下，将来自所述第一数据信号端的第一数据信号传输至所述第一节点；
    开关控制子电路，与所述第一节点、所述第一电压信号端、及所述第一发光部耦接，被配置为在所述第一节点的电压的控制下，将所述第一电压信号端与所述第一发光部之间的线路导通；
    第一存储子电路，与所述第一电压信号端及所述第一节点耦接，被配置为存储并维持所述第一节点的电压。
  14. 根据权利要求13所述的像素电路，其中，
    所述第一数据写入子电路包括：
    第一晶体管，所述第一晶体管的控制极与所述第一扫描信号端耦接，所述第一晶体管的第一极与所述第一数据信号端耦接，所述第一晶体管的第二极与所述第一节点耦接；
    所述开关控制子电路包括：
    第二晶体管，所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第一电压信号端耦接，所述第二晶体管的第二极与所述第一发光部耦接；
    所述第一存储子电路包括：
    第一存储电容器，所述第一存储电容器的第一端与所述第一节点耦接，所述第一存储电容器的第二端与所述第一电压信号端耦接。
  15. 根据权利要求12～14中任一项所述的像素电路，其中，所述第二控制电路包括：
    第二数据写入子电路，与所述第一扫描信号端、第二数据信号端、及第二节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将来自所述第二数据信号端的第二数据信号传输至所述第二节点；
    第二存储子电路，与所述第二节点及第三节点耦接，被配置为存储所述第二节点的电压，并调节所述第三节点的电压；
    第一驱动子电路，与所述第三节点、所述第一电压信号端、及第四节点耦接，被配置为在所述第三节点的电压控制下，将来自所述第一电压信号端的第一电压信号传输至所述第四节点；
    补偿子电路，与所述第一扫描信号端、所述第四节点、及所述第三节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将所述第一驱动子电路的阈值电压补偿至所述第三节点；
    电压控制子电路，与第二扫描信号端、第二电压信号端、及所述第二节点耦接，被配置为在来自所述第二扫描信号端的第二扫描信号的控制下，将 来自所述第二电压信号端的第二电压信号传输至所述第二节点；
    发光控制子电路，与使能信号端、所述第四节点、及所述第二发光部耦接，被配置为在来自所述使能信号端的使能信号的控制下，将所述第四节点的电压传输至所述第二发光部。
    初始化子电路，与复位信号端、第二电压信号端、及所述第二节点耦接，被配置为在来自所述复位信号端的复位信号的控制下，将来自所述第二电压信号端的第二电压信号传输至所述第二节点。
  16. 根据权利要求15所述的像素电路，其中，
    所述第二数据写入子电路包括：
    第三晶体管，所述第三晶体管的控制极与所述第一扫描信号端耦接，所述第三晶体管的第一极与所述第二数据信号端耦接，所述第三晶体管的第二极与所述第二节点耦接；
    所述第二存储子电路包括：
    第二存储电容器，所述第二存储电容器的第一端与所述第二节点电连接，所述第二存储电容器的第二端与所述第三节点电连接；
    所述第一驱动子电路包括：
    第四晶体管，所述第四晶体管的控制极与所述第三节点耦接，所述第四晶体管的第一极与所述第一电压信号端耦接，所述第四晶体管的第二极与所述第四节点耦接；
    所述补偿子电路包括：
    第五晶体管，所述第五晶体管的控制极与所述第一扫描信号端耦接，所述第五晶体管的第一极与所述第四节点耦接，所述第五晶体管的第二极与所述第三节点耦接；
    所述电压控制子电路包括：
    第六晶体管，所述第六晶体管的控制极与所述第二扫描信号端耦接，所述第六晶体管的第一极与所述第二电压信号端耦接，所述第六晶体管的第二极与所述第二节点耦接；
    所述发光控制子电路包括：
    第七晶体管，所述第七晶体管的控制极与所述使能信号端耦接，所述第七晶体管的第一极与所述第四节点耦接，所述第七晶体管的第二极与所述第二发光部耦接；
    所述复位子电路包括：
    第八晶体管，所述第八晶体管的控制极与所述复位信号端耦接，所述第 八晶体管的第一极与所述初始化信号端耦接，所述第八晶体管的第二极与所述第二节点耦接。
  17. 根据权利要求12～14中任一项所述的像素电路，其中，所述第二控制电路包括：
    反馈子电路，与所述第一扫描信号端、反馈信号端、及反馈节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将所述反馈节点的电压传输至所述反馈信号端；所述反馈节点与所述第二发光部耦接；
    输入子电路，与所述第一扫描信号端、输入信号端、及第五节点耦接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将来自所述输入信号端的输入信号传输至所述第五节点；所述输入信号根据所述反馈节点的电压和用于控制所述第二发光部的灰阶的第三数据信号生成；
    第二驱动子电路，与所述第五节点、第六节点、及所述反馈节点耦接，被配置为在所述第五节点的电压的控制下，根据所述第六节点的电压信号，调节所述反馈节点的电压；
    第三存储子电路，与所述第一电压信号端及所述第五节点耦接，被配置存储并维持所述第五节点的电压；
    调制子电路，与第三扫描信号端、所述第一电压信号端、及所述第六节点耦接，被配置为在来自所述第三扫描信号端的第三扫描信号的控制下，将来自所述第一电压信号端的第一电压信号传输至所述第六节点，并对所述第一电压信号端与所述第二发光部之间的线路的导通时间进行调制。
  18. 根据权利要求17所述的像素电路，其中，
    所述反馈子电路包括：
    第九晶体管，所述第九晶体管的控制极与所述第一扫描信号端耦接，所述第九晶体管的第一极与所述反馈节点耦接，所述第九晶体管的第二极与所述反馈信号端耦接；
    所述输入子电路包括：
    第十晶体管，所述第十晶体管的控制极与所述第一扫描信号端耦接，所述第十晶体管的第一极与所述输入信号端耦接，所述第十晶体管的第二极与所述第五节点耦接；
    所述第二驱动子电路包括：
    第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第六节点耦接，所述第十一晶体管的第二极与所述反馈节点耦接；
    所述第三存储子电路包括：
    第三电容器，所述第三电容器的第一端与所述第一电压信号端耦接，所述第三电容器的第二端与所述第五节点耦接；
    所述调制子电路包括：
    第十二晶体管，所述第十二晶体管的控制极与所述第三扫描信号端耦接，所述第十二晶体管的第一极与所述第一电压信号端耦接，所述第十二晶体管的第二极与所述第六节点耦接。
  19. 一种发光基板，包括：
    驱动背板，包括多个如权利要求12～18中任一项所述的像素电路；
    多个如权利要求1～11中任一项所述的发光器件；
    其中，每个像素电路的第一控制电路与一个发光器件的第一发光部耦接，每个像素电路的第二控制电路与一个发光器件的第二发光部耦接。
  20. 根据权利要求19所述的发光基板，其中，所述像素电路的第二控制电路包括反馈子电路、输入子电路、第二驱动子电路、第三存储子电路、及调制子电路；
    所述发光基板还包括：与所述驱动背板耦接的电路板，所述电路板包括第三控制电路；所述第三控制电路包括：
    比较子电路，与第三数据信号端、反馈信号端、及第七节点耦接，被配置为，比较所述反馈信号端传输的反馈节点的电压与来自所述第三数据信号端的第三数据信号，并根据比较结果向所述第七节点输出调节电压；所述第三数据信号端被配置为传输用于控制所述第二发光部的灰阶的第三数据信号；
    信号转换子电路，与所述第七节点、接地电压端、及输入信号端耦接，被配置为根据所述第七节点的调节电压及所述接地电压端的电压，向所述输入信号端传输输入信号。
  21. 根据权利要求20所述的发光基板，其中，
    所述比较子电路包括：
    第一放大器，所述第一放大器包括第一正向输入端、第一负向输入端和第一输出端；所述第一正向输入端与所述反馈信号端耦接，所述第一负向输入端与所述第三数据信号端耦接，所述第一输出端与所述第七节点耦接；
    所述信号转换子电路包括：
    第二放大器，所述第二放大器具有第二正向输入端、第二负向输入端和第二输出端；所述第二正向输入端与所述接地电压端耦接，所述第二负向输 入端与所述第七节点耦接，所述第二输出端与所述信号输入端耦接；
    第四电容器，所述第四电容器的一端与所述第二负向输入端耦接，所述第四电容器的第二端与所述第二输出端耦接。
  22. 根据权利要求21所述的发光基板，其中，
    所述比较子电路还包括：
    第一电阻，所述第一电阻的一端与所述第一正向输入端电连接，所述第一电阻的二端与所述第一负向输入端电连接；
    所述信号转换子电路还包括：
    第二电阻，所述第二电阻的一端与所述第七节点电连接，所述第二电阻的二端与所述第二负向输入端电连接；
    第三电阻，所述第三电阻的一端与所述接地电压端电连接，所述第三电阻的二端与所述第二正向输入端电连接。
  23. 一种显示装置，包括如权利要求19～22中任一项所述的发光基板。
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