WO2020140287A1 - 像素电路及其驱动方法、显示面板和显示设备 - Google Patents

像素电路及其驱动方法、显示面板和显示设备 Download PDF

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Publication number
WO2020140287A1
WO2020140287A1 PCT/CN2019/070485 CN2019070485W WO2020140287A1 WO 2020140287 A1 WO2020140287 A1 WO 2020140287A1 CN 2019070485 W CN2019070485 W CN 2019070485W WO 2020140287 A1 WO2020140287 A1 WO 2020140287A1
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Prior art keywords
light
transistor
circuit
electrically connected
control
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PCT/CN2019/070485
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English (en)
French (fr)
Inventor
玄明花
岳晗
丛宁
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/629,097 priority Critical patent/US11620935B2/en
Priority to PCT/CN2019/070485 priority patent/WO2020140287A1/zh
Priority to CN201980000048.3A priority patent/CN110972503B/zh
Publication of WO2020140287A1 publication Critical patent/WO2020140287A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • Micro LED (light-emitting diode) display technology is to thin, miniaturize and array the LED structure design, so that the micro LED can be placed on the circuit substrate to achieve the display function.
  • Micro LED light-emitting devices have the characteristics of low driving voltage, ultra-high brightness, long life, low power consumption, high temperature resistance, etc., so Micro LED display technology is considered to be one of the next generation display panel technology.
  • Micro LED display technology has a wide range of applications. When Micro LED display technology is applied to smart phones and wearable devices, it can achieve extended battery life, reduce power consumption and increase display brightness. It can also solve the problem of strong ambient light causing displays The problem of whitening and poor recognition of the above image.
  • Some embodiments of the present disclosure provide a pixel circuit, including: a light emitting driving circuit, a storage circuit, and a data writing circuit, and a first end of the storage circuit is electrically connected to the data writing circuit and the light emitting driving circuit, respectively ,
  • the second end of the storage circuit is configured to receive a control signal
  • the storage circuit is configured to receive and store the first data voltage transmitted by the data writing circuit, and according to the control signal and the first
  • a data voltage generates a first control voltage that varies with time, so that the first control voltage is applied to the light-emitting drive circuit to control the turn-on time of the light-emitting drive circuit
  • the light-emitting drive circuit is configured to The light-emitting element is driven to emit light under the control of the first control voltage.
  • the second terminal of the storage circuit is electrically connected to a control voltage terminal, and the control voltage terminal is configured to output the control signal that changes with time.
  • control signal is a triangular wave signal, a sawtooth wave signal, or a sine wave signal.
  • the storage circuit includes a capacitor.
  • the second terminal of the storage circuit is electrically connected to a control voltage terminal, the control voltage terminal is configured to output the control signal, and the control signal is Wave signal.
  • the storage circuit includes a capacitor and a signal conversion sub-circuit
  • the first end of the storage circuit includes a first pole of the capacitor
  • the first The two ends include the second end of the signal conversion sub-circuit
  • the second pole of the capacitor is connected to the first end of the signal conversion sub-circuit
  • the signal conversion sub-circuit is configured to convert the control signal to With a time-varying intermediate control signal
  • the capacitor is configured to generate the first control voltage according to the intermediate control signal and the first data voltage.
  • the light emission driving circuit includes a driving transistor, a first electrode of the driving transistor is electrically connected to a first power supply terminal, and a second electrode of the driving transistor is The first end of the light-emitting element is electrically connected, and the gate of the drive transistor is electrically connected to the data writing circuit and the storage circuit, respectively.
  • the data writing circuit includes a data writing transistor, a first electrode of the data writing transistor is electrically connected to a data line, and the data writing transistor The second electrode is electrically connected to the storage circuit, and the gate of the data writing transistor is electrically connected to the scan signal line to receive the scan signal.
  • the pixel circuit provided by some embodiments of the present disclosure further includes a light emission control circuit configured to control the light emission driving circuit to drive the light emitting element to emit light under the control of a light emission control signal.
  • the light emission control circuit includes a first light emission control transistor and a second light emission control transistor, the first electrode of the first light emission control transistor and the first power supply
  • the terminal is electrically connected, the second electrode of the first light-emission control transistor is electrically connected to the first electrode of the drive transistor, the gate of the first light-emission control transistor is electrically connected to the light-emission control line to receive the light-emission control Signal;
  • the first electrode of the second light-emission control transistor is electrically connected to the second electrode of the drive transistor, the second electrode of the second light-emission control transistor is electrically connected to the first end of the light-emitting element, the The gate of the second light emission control transistor is electrically connected to the light emission control line to receive the light emission control signal.
  • the pixel circuit further includes: a light emission control circuit, the light emission drive circuit includes a drive transistor, the data writing circuit includes a data writing transistor, and the light emission control circuit includes a first light emission control A transistor and a second light-emission control transistor, the storage circuit includes a capacitor, the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the first electrode of the capacitor Connection, the gate of the data writing transistor is electrically connected to a scanning signal line to receive the scanning signal; the second electrode of the capacitor is configured to receive a control signal, the control signal is a triangular wave signal, a sawtooth wave signal Or a sine wave signal; the first pole of the driving transistor is electrically connected to the first power supply terminal, the second pole of the driving transistor is electrically connected to the first end of the light-emitting element, and the gate of the driving transistor is The second electrode of the data writing transistor is electrically connected to the first electrode of the capacitor;
  • the light emitting element is a light emitting diode
  • the size of the light emitting diode is less than 100 microns.
  • Some embodiments of the present disclosure provide a driving method applied to the pixel circuit according to any one of the above, wherein one frame time includes a first data writing stage and a first light emitting stage, including: writing in the first data Enter the stage, write the first data voltage to the storage circuit; in the first light-emitting stage, write the control signal to the storage circuit, the storage circuit according to the control signal and the first data
  • the voltage generates the first control voltage that changes with time, and drives the light-emitting element to emit light under the control of the first control voltage.
  • the one frame time further includes a second data writing stage and a second light-emitting stage.
  • the driving method further includes: in the second data writing stage, the The storage circuit writes a second data voltage; in the second light-emitting phase, writes the control signal to the storage circuit, the storage circuit generates a time-varying change according to the control signal and the second data voltage
  • the second control voltage drives the light emitting element to emit light under the control of the second control voltage.
  • the first data voltage and the second data voltage are different.
  • the light emitting time of the light emitting element in the first light emitting stage is different from the light emitting time of the light emitting element in the second light emitting stage.
  • the light emitting driving circuit includes a driving transistor, a first electrode of the driving transistor is electrically connected to a first power supply terminal, and a second electrode of the driving transistor is The first end of the light-emitting element is electrically connected, and the gate of the driving transistor is electrically connected to the data writing circuit and the storage circuit,
  • the control signal includes a maximum value and a minimum value
  • the driving transistor is a P-type transistor, and the maximum value and the minimum value satisfy the following relationship:
  • V data1 represents the first data voltage
  • V e1 represents the maximum value
  • V e2 represents the minimum value
  • V dd represents the first power supply voltage output by the first power supply terminal
  • V th represents the drive The threshold voltage of the transistor.
  • the light emitting driving circuit includes a driving transistor, a first electrode of the driving transistor is electrically connected to a first power supply terminal, and a second electrode of the driving transistor is The first end of the light-emitting element is electrically connected, and the gate of the driving transistor is electrically connected to the data writing circuit and the storage circuit,
  • the control signal includes a maximum value and a minimum value
  • the driving transistor is an N-type transistor, and the maximum value and the minimum value satisfy the following relationship:
  • V data1 represents the first data voltage
  • V e1 represents the maximum value
  • V e2 represents the minimum value
  • V dd represents the first power supply voltage output by the first power supply terminal
  • V th represents the drive The threshold voltage of the transistor.
  • Some embodiments of the present disclosure also provide a display device including the pixel circuit according to any one of the above.
  • FIG. 1 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • 3A is a schematic diagram of a control signal provided by some embodiments of the present disclosure.
  • 3B is a schematic diagram of a control signal provided by other embodiments of the present disclosure.
  • FIG. 4A is a schematic structural diagram of a pixel circuit provided by other embodiments of the present disclosure.
  • 4B is a schematic structural diagram of a signal conversion sub-circuit provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic flowchart of a pixel circuit driving method according to some embodiments of the present disclosure
  • FIG. 6 is an exemplary timing diagram of the driving method of the pixel circuit shown in FIG. 2;
  • FIG. 7 is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • FIG. 8 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • Micro LED ( ⁇ -LED) technology is a technology that sees LED miniaturization and matrixing. In simple terms, it means that the LED is thinned, miniaturized, and arrayed, and each LED pixel unit can be individually addressed and driven to emit light. .
  • Micro LED technology has the characteristics of high efficiency, high brightness, high reliability and fast response time of inorganic LEDs, and has the characteristics of self-illumination without backlight, small size, thin and light, etc., and can easily achieve the effect of energy saving. Mounted on the circuit board by other methods. However, due to problems such as the driving circuit provided on the glass substrate and the color coordinate shift at different currents, it is difficult for Micro LED display panels to be commercialized.
  • At least some embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display panel, and a display device.
  • the pixel circuit can control the gray scale by controlling the light-emitting time of the Micro LED as a light-emitting element at a fixed voltage, that is, using a fixed voltage Cooperate with the control voltage that changes with time (for example, the first control voltage, the second control voltage) to achieve a display driving scheme that displays more gray levels, and solves the problem of color coordinate shift of the Micro LED light emitting element under different currents.
  • the circuit can realize the control of the lighting time of the Micro LED without adding additional devices, and has a simple structure and low cost.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure.
  • one of the first pole and the second pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure It is interchangeable with the second pole as needed.
  • the first pole of the transistor described in the embodiments of the present disclosure may be a source, and the second pole may be a drain; or, the first pole of the transistor may be a drain and the second pole may be a source.
  • transistors can be divided into N-type transistors (N-type MOS transistors) and P-type transistors (P-type MOS transistors).
  • N-type MOS transistors N-type MOS transistors
  • P-type MOS transistors P-type MOS transistors
  • FIG. 1 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • the pixel circuit 100 includes a light-emitting drive circuit 11, a storage circuit 12 and a data writing circuit 13.
  • the storage circuit 12 includes a first end and a second end, the first end of the storage circuit 12 is electrically connected to the data writing circuit 13 and the light-emitting drive circuit 11, respectively, and the second end of the storage circuit 12 is configured to receive the control signal V cs ,
  • the storage circuit 12 is configured to receive and store the first data voltage V data1 transmitted by the data writing circuit 13 and generate a first control voltage V cv that varies with time according to the control signal V cs and the first data voltage V data1 , so that The first control voltage V cv is applied to the light emitting drive circuit 11 to control the on time of the light emitting drive circuit 11; the light emitting drive circuit 11 is configured to drive the light emitting element 10 to emit light under the control of the first control voltage V cv .
  • the data writing circuit 13 is configured to write the first data voltage V data1 into the storage circuit 12 under the control of the scan signal V scan .
  • the light-emitting element 10 when the light-emitting drive circuit 11 is turned on, the light-emitting element 10 can be driven to emit light, that is, the light-emitting drive circuit 11 is turned on for the same time as the light-emitting element 10 without considering an error.
  • the display brightness (gray scale) of the light emitting element 10 can be controlled, so that the light emitting element 10 displays more gray levels. For example, in each frame time, if the light emitting time of the light emitting element 10 is longer, the display brightness of the light emitting element 10 is higher, that is, the gray level corresponding to the light emitting element 10 is larger.
  • the light emitting element 10 is a light emitting diode, for example, an inorganic light emitting diode.
  • the size of the light emitting diode is less than 100 microns, for example, 1 to 10 microns.
  • the light emitting diode can emit red light, blue light, green light, or the like.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • the second terminal of the storage circuit 12 is electrically connected to the control voltage terminal Ctrl, and the control voltage terminal Ctrl is configured to output a control signal V cs that changes with time.
  • the first control voltage V cv is applied to the light-emitting drive circuit 11 via the first end of the storage circuit 12.
  • control signal V cs may be a triangle wave signal, a sawtooth wave signal, a sine wave signal, or a step wave signal.
  • the control signal V cs can change with time during the light-emission phase in a frame time, so that the first control voltage V cv can change with time, so that the on-time of the light-emitting drive circuit changes, the present disclosure
  • the specific type of the control signal V cs is not limited.
  • control signal V cs may still change with time, or it may not change with time, that is, in addition to light emission In stages other than the stage, the control signal V cs does not change.
  • the pixel circuit 100 may be integrated on a base substrate, and the base substrate may be a glass substrate, that is, the pixel circuit 100 is formed on the glass substrate.
  • the base substrate may also be a suitable substrate such as a ceramic substrate, a quartz substrate, or the like.
  • the light emission drive circuit 11 includes a drive transistor M1.
  • the first electrode of the driving transistor M1 is electrically connected to the first power supply terminal ELVDD
  • the second electrode of the driving transistor M1 is electrically connected to the first terminal of the light emitting element 10
  • the gate of the driving transistor M1 is respectively connected to the data writing circuit 13 and the storage circuit 12 Electrical connection.
  • the second end of the light emitting element 10 is electrically connected to the second power supply terminal ELVSS.
  • the first control voltage V cv may be applied to the gate of the driving transistor M1 to control the driving transistor M1 to be turned on or off.
  • the drive current is substantially equal each time the light-emitting drive circuit 11 is turned on, thereby adopting the pixel circuit
  • the unit time brightness of the light-emitting element of the sub-pixel is substantially equal, so that the gray level of the sub-pixel is only related to the length of time the light-emitting drive circuit 11 is turned on.
  • one of the first power supply terminal ELVDD and the second power supply terminal ELVSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power terminal ELVDD is a voltage source to output a constant positive voltage
  • the second power terminal ELVSS may be a voltage source to output a constant negative voltage, or may be grounded.
  • the voltage difference between the first power supply terminal ELVDD and the second power supply terminal ELVSS is smaller, for example, the first power supply terminal
  • the voltage output by ELVDD may be about 3V
  • the voltage output by the second power supply terminal ELVSS may be about 0V
  • the voltage difference between the first power supply terminal ELVDD and the second power supply terminal ELVSS is about 3V.
  • FIG. 3A is a schematic diagram of a control signal provided by some embodiments of the present disclosure
  • FIG. 3B is a schematic diagram of a control signal provided by other embodiments of the present disclosure.
  • the control signal V cs includes a maximum value and a minimum value.
  • a coordinate system is established by using the control signal V cs and time t as two coordinate axes, the control signal V cs as the ordinate, and the time t as the abscissa.
  • the driving transistor M1 is an N-type transistor
  • the maximum and minimum values of the control signal V cs satisfy the following relationship:
  • V data1 represents the first data voltage
  • V e1 represents the maximum value
  • V e2 represents the minimum value
  • V dd represents the first power supply voltage output by the first power supply terminal ELVDD
  • V th represents the threshold voltage of the driving transistor M1.
  • V cs is the maximum value of the control signal V e1" indicates the maximum value of the control signal V cs in the arc phase F2 "
  • the minimum value of the control signal V cs V e2" represents the minimum value signal V cs is controlled within the emission phase F2.
  • the control signal V cs gradually increases with time, that is, at the beginning of the lighting phase F2 (that is, time t1), the control signal V cs has a minimum value V e2 , and at the end of the lighting phase F2 (that is, time t2), the control signal V cs has the maximum value V e1 .
  • a coordinate system is established by using the control signal V cs and the time t as two coordinate axes, the control signal V cs is the ordinate, and the time t is the abscissa.
  • the maximum and minimum values of the control signal V cs satisfy the following relationship:
  • V data1 represents the first data voltage
  • V e1 represents the maximum value
  • V e2 represents the minimum value
  • V dd represents the first power supply voltage output by the first power supply terminal ELVDD
  • V th represents the threshold voltage of the driving transistor M1.
  • the control signal V cs gradually decreases with time, that is, at the starting point of the light-emitting phase F2' (that is, the time point t1'), the control signal V cs has the maximum value V e1 , and at the end of the light-emitting phase F2' ( That is, at time t2'), the control signal V cs has a minimum value V e2 .
  • control signal V cs is a sine wave signal.
  • the control signal V cs and the time may also have a nonlinear relationship, that is, the control signal V cs increases nonlinearly with time.
  • the control signal V cs is a sine wave signal, in the lighting phase F2, the sine wave signal also has a maximum value and a minimum value, and the maximum value and the minimum value still satisfy the above relationship (1) or relationship (2).
  • the control signal V cs in the light-emitting phase F2, at a time point t1 (ie, the starting point of the light-emitting phase F2), the control signal V cs has a minimum value V e2 , at At the time point t2 (ie the end of the light-emitting phase F2), the control signal V cs has the maximum value V e1 , and at the time point t3 (ie the critical time point), the control signal V cs has the critical value V cr , at this time, the critical value V cr satisfies the following relationship:
  • V data1 -V e2 +V cr V dd +V th .
  • the driving transistor M1 is in the off state in the time period ⁇ t1 from the time point t1 to the time point t3; in the time period ⁇ t2 from the time point t3 to the time point t2, the driving transistor T2 Then, the light-emitting element 10 can be driven to emit light.
  • the turn-on time of the light-emitting drive circuit 11 is the time period ⁇ t2 between the time point t3 and the time point t2.
  • the size of the time period ⁇ t2 can be adjusted by adjusting parameters such as the slope, minimum value, and maximum value of the triangular wave signal, thereby adjusting the length of the turn-on time of the light-emitting drive circuit 11.
  • the control signal V cs has a maximum value V e1 , at the time point t2' (ie the end of the lighting phase F2'), the control signal V cs has a minimum value V e2 , and at the time point t3' (ie the critical time point), the control signal V cs has a critical value V' cr , at this time, the critical value V'cr satisfies the following relationship:
  • V data1 -V e1 +V' cr V dd +V th .
  • the driving transistor M1 is in the off state in the time period ⁇ t1′ from the time point t1′ to the time point t3′; the time period from the time point t3′ to the time point t2′ In ⁇ t2′, the driving transistor M1 is turned on, so that the light emitting element 10 can be driven to emit light.
  • the turn-on time of the light-emitting drive circuit 11 is a time period ⁇ t2′ from the time point t3′ to the time point t2′.
  • the size of the time period ⁇ t2′ can be adjusted by adjusting parameters such as the slope, minimum value, and maximum value of the triangular wave signal, thereby adjusting the length of the turn-on time of the light-emitting drive circuit 11.
  • the memory circuit 12 includes a capacitor C1.
  • the first end of the storage circuit 12 includes the first pole of the capacitor C1
  • the second end of the storage circuit 12 includes the second pole of the capacitor C1, that is, the first pole of the capacitor C1 and the data writing circuit 13 and
  • the light-emitting drive circuit 11 is electrically connected
  • the second electrode of the capacitor C1 is electrically connected to the control voltage terminal Ctrl.
  • the storage circuit 12 shown in FIG. 2 is only schematic, and the present disclosure does not limit the specific structure of the storage circuit 12.
  • the storage circuit 12 may further include elements such as resistors. In this case, the two poles of the capacitor C1 may not be the two ends of the storage circuit 12.
  • FIG. 4A is a schematic structural diagram of a pixel circuit provided by some other embodiments of the disclosure
  • FIG. 4B is a schematic structural diagram of a signal conversion sub-circuit provided by some embodiments of the disclosure.
  • the second terminal of the storage circuit 12 is electrically connected to the control voltage terminal Ctrl.
  • the control voltage terminal Ctrl is configured to output the control signal V cs .
  • the control signal V cs may be a square wave signal, that is, during the light-emitting phase, the control The signal V cs does not change with time, that is, the value of the control signal V cs is the same throughout the lighting phase.
  • the memory circuit 12 may include a capacitor C1' and a signal conversion sub-circuit 121.
  • the first end of the storage circuit 12 includes the first pole of the capacitor C1′, and the second end of the storage circuit 12 includes the second end of the signal conversion sub-circuit 121, that is, the first pole of the capacitor C1′ and the data writing circuit 13 and
  • the light-emitting drive circuit 11 is electrically connected, the second end of the signal conversion sub-circuit 121 is electrically connected to the control voltage terminal Ctrl, and the second pole of the capacitor C1 ′ is connected to the first end of the signal conversion sub-circuit 121.
  • the signal conversion sub-circuit 121 is configured to convert the control signal V cs into an intermediate control signal that changes with time.
  • the intermediate control signal may be a triangular wave signal, a sawtooth wave signal, a sine wave signal, or a step wave signal.
  • the capacitor C1' is configured to generate a first control voltage Vcv that varies with time according to the intermediate control signal and the first data voltage Vdata1 .
  • control signal V cs is a square wave signal
  • intermediate control signal is a triangular wave signal
  • signal conversion sub-circuit 121 may include an integration circuit, as shown in FIG. 4B, an exemplary integration circuit includes a capacitor C2 and a first resistor R1, a second resistor R2 and an operational amplifier OP, the integrating circuit can convert the square wave signal into a triangular wave signal or a sawtooth wave signal, etc.
  • the first terminal of the first resistor R1 is configured to receive the control signal V cs
  • the second terminal of the first resistor R1 is connected to the inverting input terminal of the operational amplifier OP—the first terminal of the capacitor C2 is connected to The inverting input terminal of the operational amplifier OP—the second terminal of the capacitor C2 is connected to the output terminal of the operational amplifier OP; the first terminal of the second resistor R2 is connected to the non-inverting input terminal + of the operational amplifier OP, and the second terminal of the second resistor R2 Both ends are grounded.
  • the output of the operational amplifier OP is configured to output the intermediate control signal V mc .
  • the parameters such as the frequency, maximum value, and minimum value of the intermediate control signal V mc can be adjusted.
  • the intermediate control signal V mc also varies with the control signal V cs , that is, the control signal V cs (for example, period, amplitude, etc.) is different, and the generated intermediate control signal V mc is also different.
  • the signal conversion sub-circuit 121 may be formed on the base substrate. However, the embodiments of the present disclosure are not limited to this. In some embodiments, the signal conversion sub-circuit 121 may also be formed on the driving chip to reduce the area occupied by the pixel circuit 100 on the base substrate and improve the resolution. For example, the driving chip is bound to the base substrate through the flexible circuit board. At this time, the capacitor C1′ in the storage circuit 12 can still be formed on the base substrate.
  • the data writing circuit 13 includes a data writing transistor M2.
  • the first electrode of the data writing transistor M2 is electrically connected to the data line D to receive the first data voltage V data1
  • the second electrode of the data writing transistor M2 is electrically connected to the storage circuit 12
  • the gate of the data writing transistor M2 is
  • the scan signal line G is electrically connected to receive the scan signal V scan .
  • the second electrode of the data writing transistor M2 is electrically connected to the first electrode of the capacitor C1; the data line D is configured to provide the first data voltage V data1 to the data writing transistor M2; the scanning signal line G is configured to provide the scan signal Vscan to the data writing transistor M2.
  • the scan signal line G may provide a scan signal to the gate of the data writing transistor M2 to turn on the data writing transistor M2.
  • the data writing transistor M2 can transfer the first data voltage V data1 to the first electrode of the capacitor C1, and the capacitor C1 can store the first data voltage V data1 .
  • the pixel circuit 100 further includes a light emission control circuit 14.
  • the light emission control circuit 14 is configured to control the light emission driving circuit 11 to drive the light emitting element 10 to emit light under the control of the light emission control signal.
  • the light emission control circuit 14 may include a first light emission control transistor M3 and a second light emission control transistor M4. As shown in FIGS. 2 and 4A, the first electrode of the first light emission control transistor M3 is electrically connected to the first power supply terminal ELVDD, and the second electrode of the first light emission control transistor M3 is electrically connected to the first electrode of the driving transistor M1.
  • the gate of a light-emission control transistor M3 is electrically connected to the light-emission control line EM to receive the light-emission control signal V EM ;
  • the first electrode of the second light-emission control transistor M4 is electrically connected to the second electrode of the driving transistor M1, and the second light-emission control transistor
  • the second pole of M4 is electrically connected to the first end of the light emitting element 10, and the gate of the second light emission control transistor M4 is electrically connected to the light emission control line EM to receive the light emission control signal V EM .
  • the second light-emitting control transistor M4 may disconnect the driving transistor M1 and the light-emitting element 10 to ensure that the light-emitting element 10 does not emit light.
  • the light-emission control line EM may provide the first light-emission control transistor M3 and the second light-emission control transistor M4 with the light-emission control signal V EM to turn on the first light-emission control transistor M3 and the second light-emission control transistor M4, thereby forming From the conduction loop of the first power supply terminal ELVDD to the second power supply terminal ELVSS, the light-emitting current can be transmitted to the light-emitting element 10 via the conductive driving transistor M1 to drive it to emit light.
  • the first control voltage V cv can control the turn-on time of the driving transistor M2 to control the light-emitting time of the light-emitting element 10.
  • the length of the light-emitting time can determine the display brightness of the light-emitting element 10, that is, the gray-scale level corresponding to the light-emitting element 10.
  • the gates of the first emission control transistor M3 and the gates of the second emission control transistor M4 are connected to the same emission control line EM to receive the same emission Control signal V EM .
  • the gates of the first light-emission control transistor M3 and the second light-emission control transistor M4 may also be electrically connected to different light-emission control lines, and the light emission applied by the different light-emission control lines The control signal is synchronized.
  • the embodiments of the present disclosure do not limit the control manners of the first emission control transistor M3 and the second emission control transistor M4.
  • the light-emitting drive circuit 11, the storage circuit 12, the data writing circuit 13, and the light-emitting control circuit 14 are not limited to the structures described in the above embodiments, and their specific structures can be set according to actual application requirements. The example does not specifically limit this.
  • the pixel circuit 100 may further include a reset circuit, a compensation circuit, etc.
  • the compensation circuit may be implemented by voltage compensation, current compensation, or hybrid compensation.
  • the compensation circuit may compensate for the threshold voltage of the driving transistor M1 and the voltage drop (IR drop) at the power supply terminal, etc. To improve the display quality and display effect.
  • the reset circuit can reset the gate of the driving transistor M1 to prevent signals between different frames from interfering with each other.
  • Some embodiments of the present disclosure also provide a driving method for a pixel circuit, and the driving method may be applied to the pixel circuit described in any one of the above.
  • FIG. 5 is a schematic flowchart of a driving method of a pixel circuit provided by some embodiments of the present disclosure.
  • one frame time includes the first data writing stage and the first light emitting stage.
  • the driving method of the pixel circuit includes the following steps:
  • a control signal is written to the storage circuit.
  • the storage circuit generates a first control voltage that varies with time according to the control signal and the first data voltage, and drives the light-emitting element to emit light under the control of the first control voltage.
  • the driving method of the pixel circuit controls the gray scale by controlling the light-emitting time of the Micro LED under a fixed voltage, that is, using a fixed voltage in conjunction with a control voltage that changes with time (for example, the first control voltage) to realize a display drive that displays more gray scales
  • a control voltage that changes with time (for example, the first control voltage) to realize a display drive that displays more gray scales
  • control signal may be a signal that changes with time
  • the storage circuit may include a capacitor, that is, the storage circuit is the storage circuit in the example shown in FIG. 2, in this example, in step S102, according to the control signal and the first data Generating the first control voltage that varies with time includes: adding the control signal and the first data voltage to obtain the first control voltage.
  • the control signal may be a signal that does not change with time.
  • the control signal is a square wave signal.
  • the storage circuit includes a capacitor and a signal conversion sub-circuit, that is, the storage circuit is the storage circuit in the example shown in FIG. 4A.
  • generating a first control voltage that varies with time according to the control signal and the first data voltage includes: converting the control signal into an intermediate control signal through a signal conversion sub-circuit, where the intermediate control signal is time-dependent The changed signal; the intermediate control signal and the first data voltage are added to obtain the first control voltage.
  • the light-emitting drive circuit includes a drive transistor.
  • driving the light-emitting element to emit light under the control of the first control voltage includes: the first control voltage controls the drive transistor to turn on so that a light-emitting current flows into the light-emitting element via the drive transistor to drive The light emitting element emits light.
  • the first control voltage can control the turn-on time of the driving transistor to control the light-emitting time of the light-emitting element, and finally control the light-emitting brightness (ie, gray scale) of the light-emitting element.
  • one frame time further includes a second data writing stage and a second light emitting stage
  • the driving method further includes:
  • S104 In the second light-emitting stage, a control signal is written to the storage circuit, and the storage circuit generates a second control voltage that changes with time according to the control signal and the second data voltage, and drives the light-emitting element to emit light under the control of the second control voltage.
  • the light-emitting element is driven to emit light multiple times within a frame time, and the gray-scale of the light-emitting element during the multiple light-emitting processes is finally controlled to control the gray scale of the display panel, thereby enabling more display within a frame time Gray scale.
  • control signal is a signal that varies with time, and in the first lighting stage, the control signal includes a first maximum value and a first minimum value.
  • the driving transistor is a P-type transistor
  • the first maximum value and the first minimum value satisfy the following relationship:
  • V data1 represents the first data voltage
  • V e11 represents the first maximum value
  • V e12 represents the first minimum value
  • V dd represents the first power supply voltage output from the first power supply terminal
  • V th represents the threshold voltage of the driving transistor.
  • control signal also has a first critical value, and the first critical value V cr1 satisfies the following relationship:
  • V data1 -V e11 +V cr1 V dd +V th .
  • the first maximum value and the first minimum value satisfy the following relationship:
  • V data1 represents the first data voltage
  • V e11 represents the first maximum value
  • V e12 represents the first minimum value
  • V dd represents the first power supply voltage output from the first power supply terminal
  • V th represents the threshold voltage of the driving transistor.
  • control signal also has a first critical value, and the first critical value V cr1 satisfies the following relationship:
  • V data1 -V e12 +V cr1 V dd +V th .
  • control signal is a signal that varies with time, and in the second light-emitting phase, the control signal includes a second maximum value and a second minimum value.
  • the second maximum value and the second minimum value satisfy the following relationship:
  • V data2 represents the second data voltage
  • V e21 represents the second maximum value
  • V e22 represents the second minimum value
  • V dd represents the first power supply voltage output from the first power supply terminal
  • V th represents the threshold voltage of the driving transistor.
  • control signal also has a second critical value, and the second critical value V cr2 satisfies the following relationship:
  • V data2 -V e21 +V cr2 V dd +V th .
  • the second maximum value and the second minimum value satisfy the following relationship:
  • V data2 represents the second data voltage
  • V e21 represents the second maximum value
  • V e22 represents the second minimum value
  • V dd represents the first power supply voltage output from the first power supply terminal
  • V th represents the threshold voltage of the driving transistor.
  • control signal also has a second critical value, and the second critical value V cr2 satisfies the following relationship:
  • V data2 -V e22 +V cr2 V dd +V th .
  • the lighting time of the light emitting element is the first lighting time; in the second lighting stage, the lighting time of the light emitting element is the second lighting time.
  • the light emitting time of the light emitting element in the first light emitting stage is different from the light emitting time of the light emitting element in the second light emitting stage, that is, the first light emitting time and the second light emitting time are different.
  • the first data voltage and the second data voltage may be different.
  • the control signals in the first light-emitting stage and the second light-emitting stage may be the same.
  • the first control voltage generated in the first light-emitting stage and the second control voltage generated in the second light-emitting stage are different.
  • the first light-emitting time and the second light-emitting time may be different.
  • the first data voltage and the second data voltage may be the same.
  • the control signals in the first light-emitting stage and the second light-emitting stage may be different.
  • the first control voltage generated in the first light-emitting stage and the second control voltage generated in the second light-emitting stage are different.
  • the first light-emitting time and the second light-emitting time may be different.
  • the first data voltage and the second data voltage may be different, and the control signals in the first light-emitting stage and the second light-emitting stage may also be different. At this time, the first light-emitting stage is generated The first control voltage and the second control voltage generated in the second light emitting stage are different, and thus, the first light emitting time and the second light emitting time may be different.
  • the first data voltage and the second data voltage may be the same.
  • the control signals in the first light-emitting stage and the second light-emitting stage may also be the same.
  • the first control voltage generated in the first light-emitting stage and the second control voltage generated in the second light-emitting stage are the same.
  • the first lighting time and the second lighting time may be the same.
  • first data voltage, the second data voltage, the control signal in the first light-emission stage and the control signal in the second light-emission stage may be designed according to actual applications, which is not limited by the embodiments of the present disclosure.
  • the operation process of the second light-emission stage is similar to the first light-emission stage.
  • the timing diagram of the pixel circuit can be set according to actual needs, which is not specifically limited in the embodiments of the present disclosure.
  • FIG. 6 is an exemplary timing diagram of the driving method of the pixel circuit shown in FIG. 2.
  • the operation flow of a driving method of a pixel circuit provided by an embodiment of the present disclosure will be described in detail below with reference to FIGS. 2 and 6.
  • the light emission control signal provided by the light emission control line EM is a high-level signal, so that the first light emission control transistor M3 and the second light emission control transistor M4 are off Is turned on so that no current flows to the light emitting element 10, and the light emitting element 10 does not emit light.
  • Scan signals are sequentially provided to the pixel circuits in multiple rows through a plurality of scan signal lines G1 to Gn, and the scan signal provided by the scan signal lines is in an effective portion (ie, a portion where a switching circuit (eg, a transistor) connected thereto is turned on), for example It is a low-level signal, so that the data writing transistor M2 is turned on, and multiple first data voltages can be sequentially stored in the storage circuits of the respective pixel circuits. It should be noted that the plurality of first data voltages may be different or at least partially the same.
  • the control signal V cs does not change with time.
  • the light-emission control signal provided by the light-emission control line EM is a low-level signal, so that the first light-emission control transistor M3 and the second light-emission control transistor M4 are turned on,
  • the scanning signals provided by the plurality of scanning signal lines G1 to Gn to the rows of pixel circuits in sequence are at an invalid portion, such as a high level signal, so that the data writing transistor M2 is turned off, which also makes the first end of the capacitor C1 substantially Dangling.
  • the control signal V cs is a triangular wave signal as shown in FIG. 6. If in the first data writing stage TP1, the first data voltage satisfies the following relationship:
  • V data1 represents a first data voltage
  • V dd represents a first power supply voltage output by the first power supply terminal ELVDD
  • V th represents a threshold voltage of the driving transistor M1.
  • the driving transistor M1 is turned on throughout the first light-emitting phase TP2, so that the light-emitting time of the light-emitting element 10 is as shown in FIG. 6 as the P1 waveform, that is, the light-emitting time of the light-emitting element 10 is 100 times the time of the first light-emitting phase TP2 %, that is, the light-emitting element 10 emits light throughout the first light-emitting period TP2.
  • the first data voltage satisfies the following relationship: V data1 >V dd +V th , then in the initial period of the first light-emitting stage TP2, the driving transistor M1 is in the off state, No current flows to the light emitting element 10, and the light emitting element 10 does not emit light. Since the control signal V cs floats with time, and because the first end of the capacitor C1 is substantially suspended, according to the law of conservation of charge of the capacitor, the voltage value of the first end of the capacitor C1 also follows the control signal V cs , when the control signal V After the value of cs exceeds the critical value, the driving transistor M1 is turned on, so that the light emitting element 10 starts to emit light.
  • the light emitting time of the light emitting element 10 exhibits a P2 waveform, a P3 waveform, or a P4 waveform as shown in FIG. 6, that is, the light emitting time of the light emitting element 10 may be 75%, 50%, or 25 of the time of the first light emitting stage TP2, respectively. %.
  • the length of the light emitting time of the light emitting element 10 depends on the relationship between the voltage value of the first end of the capacitor C1 and the threshold voltage V th of the driving transistor M1.
  • the light emitting time of the light emitting element 10 is not limited to 75% of the time of the first light emitting stage TP2 %, 50%, 25% may also be 70%, 20%, or 15% of the time of the first light-emitting stage TP2.
  • this stage repeatedly performs the operation of the first data writing stage TP1, that is, in the second data writing stage TP3, the light emission control line EM provides
  • the light emission control signal is a high-level signal, so that the first light emission control transistor M3 and the second light emission control transistor M4 are turned off, so that no current flows to the light emitting element 10, and the light emitting element 10 does not emit light.
  • a plurality of rows of pixel circuits are sequentially provided with scan signals through a plurality of scan signal lines G1 to Gn, and the scan signals provided by the scan signal lines are in an active part, which are low-level signals, so that the data writing transistor M2 is turned on, and a plurality of second data
  • the voltage can be sequentially stored in the storage circuits of the respective pixel circuits.
  • the plurality of second data voltages may be different or at least partially the same.
  • the first data voltage and the second data voltage may be different, but the present disclosure is not limited thereto, and the first data voltage and the second data voltage may also be the same.
  • control signal V cs does not change with time.
  • this stage repeatedly performs the operation of the first lighting stage TP2, that is, in the second lighting stage TP4, the lighting control signal provided by the lighting control line EM is low Level signal, so that the first light-emission control transistor M3 and the second light-emission control transistor M4 are turned on, and at the same time, the scan signals provided by the plurality of scan signal lines G1 to Gn to the multi-row pixel circuits in sequence are at an invalid portion, which is a high-level signal, thereby The data writing transistor M2 is turned off, which also makes the first end of the capacitor C1 substantially suspended.
  • the control signal V cs is a triangular wave signal as shown in FIG. 6. If in the second data writing stage TP3, the second data voltage satisfies the following relationship:
  • V data2 represents the second data voltage
  • V dd represents the first power voltage output by the first power terminal ELVDD
  • V th represents the threshold voltage of the driving transistor M1 and is a negative value.
  • the driving transistor M1 is turned on throughout the second light-emitting stage TP4, so that the light-emitting element 10 emits light for 100% of the time of the second light-emitting stage TP4, that is, during the entire second light-emitting stage TP4, the light-emitting element 10 are glowing.
  • the driving transistor M1 In the second data writing stage TP3, if the second data voltage satisfies the following relationship: V data2 >V dd +V th , then in the initial period of the second light-emitting stage TP4, the driving transistor M1 is in the off state No current flows to the light-emitting element 10, and the light-emitting element 10 does not emit light. Since the control signal V cs floats with time, according to the law of conservation of charge of the capacitor, the voltage value at the first end of the capacitor C1 also follows the control signal V cs . When the value of the control signal V cs exceeds the critical value, the driving transistor M1 turns on. Thus, the light-emitting element 10 starts to emit light.
  • the light emitting time of the light emitting element 10 exhibits a P1 waveform, a P2 waveform, a P3 waveform, or a P4 waveform as shown in FIG. 6, that is, the light emitting time of the light emitting element 10 may be 25%, 75% of the time of the second light emitting stage TP4, respectively %, 50% or 25%.
  • the light-emitting time of one light-emitting element is the superposition of the light-emitting time in the first light-emitting stage TP2 and the light-emitting time in the second light-emitting stage TP4.
  • the light-emitting time of the light-emitting element can be expressed as:
  • t EL 100%*t TP2 +25%*t TP4
  • t EL represents the light-emitting time of the light-emitting element in one frame time
  • t TP2 represents the time of the first light-emitting phase TP2 in one frame time
  • t TP4 represents the time of the second light-emitting phase TP4 in one frame time.
  • the light-emitting time of the light-emitting element is like the P2 waveform in FIG. 6 in a frame time
  • the light-emitting time of the light-emitting element can be expressed as:
  • t EL 70%*t TP2 +50%*t TP4
  • t EL represents the light-emitting time of the light-emitting element in one frame time
  • t TP2 represents the time of the first light-emitting phase TP2 in one frame time
  • t TP4 represents the time of the second light-emitting phase TP4 in one frame time.
  • the display image on the display panel can realize more gray levels by superimposing two different lighting times.
  • one frame time may also be divided into one data writing stage and one Light-emitting phase, three data writing phases and three light-emitting phases, four data writing phases and four light-emitting phases, etc.
  • FIG. 7 is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • the display panel 70 includes a plurality of pixel units 110, and the plurality of pixel units 110 may be arranged in an array.
  • Each pixel unit 110 may include a light emitting element 120 and the pixel circuit 100 described in any of the above embodiments.
  • the light-emitting element 120 is the light-emitting element 10 in the above embodiment of the pixel circuit 100, and the repetition is not repeated.
  • the pixel circuit in the display panel can control the gray scale by controlling the lighting time of the Micro LED under a fixed voltage, that is, using a fixed voltage and a control voltage that changes with time to realize a display driving scheme that displays more gray scales, which solves the problem of Micro LED
  • the pixel circuit in the display panel can control the light emission time of the Micro LED without additional devices, the structure is simple, and the cost is low.
  • control signals applied to the pixel circuits of all the pixel units on the display panel 70 are the same; in other embodiments, they are applied to all the pixel circuits 100 in the pixel units in the same row
  • the control signals are the same, but the control signals applied to the pixel units located in different rows are different.
  • multiple control signals in different frames are the same; or, multiple control signals in different frames may be at least partially different.
  • the display panel 70 further includes a base substrate.
  • the base substrate may be a glass substrate.
  • the pixel circuit 100 and the light emitting element 120 are both formed on the base substrate, or at least partially prepared on other intermediate substrates and then transferred by transfer or other methods. And mounted on the base substrate.
  • the display panel 70 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 70 may be not only a flat panel, but also a curved panel or even a spherical panel.
  • the display panel 70 may also have a touch function, that is, the display panel 70 may be a touch display panel.
  • FIG. 8 is a schematic block diagram of a display device provided by some embodiments of the present disclosure. As shown in FIG. 8, the display device 80 may include any one of the display panels 70 described above, and the display panel 70 is used to display images.
  • the display device 80 may further include a gate driver 82.
  • the gate driver 320 is configured to be electrically connected to the data writing circuit through the scanning signal line for supplying the scanning signal to the data writing circuit.
  • the display device 80 may further include a data driver 84.
  • the data driver 84 is configured to be electrically connected to the data writing circuit through the data line for supplying the data voltage to the display panel 70, for example, the first data voltage and the second data voltage.
  • the display device 80 may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种像素电路及其驱动方法、显示面板和显示设备。像素电路(100)包括发光驱动电路(11)、存储电路(12)和数据写入电路(13)，存储电路(12)的第一端分别与数据写入电路(13)和发光驱动电路(11)电连接，存储电路(12)的第二端被配置为接收控制信号(V cs)，存储电路(12)被配置为接收并存储由数据写入电路(13)传输的第一数据电压(V data1)，且根据控制信号(V cs)和第一数据电压(V data1)产生随时间变化的第一控制电压(V cv)，使得第一控制电压(V cv)被施加至发光驱动电路(11)，以控制发光驱动电路(11)的开启时间；发光驱动电路(11)被配置为在第一控制电压(V cv)的控制下驱动发光元件(10)发光。

Description

像素电路及其驱动方法、显示面板和显示设备 技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示面板和显示设备。
背景技术
Micro LED(light-emitting diode，发光二极管)显示技术是将LED结构设计进行薄膜化、微小化和阵列化，从而可以将微型LED设置在电路基板上，以实现显示功能。Micro LED发光器件具有低驱动电压、超高亮度、长寿命、低功耗、耐高温等特点，从而Micro LED显示技术被认为是次世代显示面板技术之一。Micro LED显示技术的应用范围较广，当Micro LED显示技术应用在智能手机、可穿戴设备时，可以实现延长电池续航能力、降低功耗以及提高显示亮度等，还可以解决环境光较强致使显示器上的影像泛白、辨识度变差的问题。
发明内容
本公开的一些实施例提供一种像素电路，包括：发光驱动电路、存储电路和数据写入电路，所述存储电路的第一端分别与所述数据写入电路和所述发光驱动电路电连接，所述存储电路的第二端被配置为接收控制信号，所述存储电路被配置为接收并存储由所述数据写入电路传输的第一数据电压，且根据所述控制信号和所述第一数据电压产生随时间变化的第一控制电压，使得所述第一控制电压被施加至所述发光驱动电路，以控制所述发光驱动电路的开启时间；所述发光驱动电路被配置为在所述第一控制电压的控制下驱动发光元件发光。
例如，在本公开的一些实施例提供的像素电路中，所述存储电路的第二端与控制电压端电连接，所述控制电压端被配置为输出随时间变化的所述控制信号。
例如，在本公开的一些实施例提供的像素电路中，所述控制信号为三角波信号、锯齿波信号或正弦波信号。
例如，在本公开的一些实施例提供的像素电路中，所述存储电路包括电容。
例如，在本公开的一些实施例提供的像素电路中，所述存储电路的第二端与控制电压端电连接，所述控制电压端被配置为输出所述控制信号，所述控制信号为方波信号。
例如，在本公开的一些实施例提供的像素电路中，所述存储电路包括电容和信号转换子电路，所述存储电路的第一端包括所述电容的第一极，所述存储电路的第二端包括所述信号转换子电路的第二端，所述电容的第二极与所述信号转换子电路的第一端连接，所述信号转换子电路被配置为将所述控制信号转换为随时间变化的中间控制信号，所述电容被配置为根据所述中间控制信号和所述第一数据电压产生所述第一控制电压。
例如，在本公开的一些实施例提供的像素电路中，所述发光驱动电路包括驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述数据写入电路和所述存储电路电连接。
例如，在本公开的一些实施例提供的像素电路中，所述数据写入电路包括数据写入晶体管，所述数据写入晶体管的第一极与数据线电连接，所述数据写入晶体管的第二极与所述存储电路电连接，所述数据写入晶体管的栅极与扫描信号线电连接，以接收所述扫描信号。
例如，本公开的一些实施例提供的像素电路还包括：发光控制电路，所述发光控制电路被配置为在发光控制信号的控制下控制所述发光驱动电路驱动所述发光元件发光。
例如，在本公开的一些实施例提供的像素电路中，所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管，所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极与发光控制线电连接，以接收所述发光控制信号；所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一端电连接，所述第二发光控制晶体管的栅极与所述发光控制线电连接，以接收所述发光控制信号。
例如，本公开的一些实施例提供的像素电路还包括：发光控制电路，所述发光驱动电路包括驱动晶体管，所述数据写入电路包括数据写入晶体管，所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管，所述存储电路包括电容，所述数据写入晶体管的第一极与数据线电连接，所述数据写入晶体管的第二极与所述电容的第一极电连接，所述数据写入晶体管的栅极与扫描信号线电连接，以接收所述扫描信号；所述电容的第二极被配置为接收控制信号， 所述控制信号为三角波信号、锯齿波信号或正弦波信号；所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述数据写入晶体管的第二极和所述电容的第一极电连接；所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极与发光控制线电连接，以接收所述发光控制信号；所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一端电连接，所述第二发光控制晶体管的栅极与所述发光控制线电连接，以接收所述发光控制信号；所述发光元件的第二端与第二电源端电连接。
例如，在本公开的一些实施例提供的像素电路中，所述发光元件为发光二极管，所述发光二极管的尺寸小于100微米。
本公开的一些实施例提供一种应用于根据上述任一项所述的像素电路的驱动方法，其中，一帧时间包括第一数据写入阶段和第一发光阶段，包括：在第一数据写入阶段，向所述存储电路写入所述第一数据电压；在第一发光阶段，向所述存储电路写入所述控制信号，所述存储电路根据所述控制信号和所述第一数据电压产生随时间变化的所述第一控制电压，在所述第一控制电压的控制下，驱动所述发光元件发光。
例如，在本公开的一些实施例提供的驱动方法中，所述一帧时间还包括第二数据写入阶段和第二发光阶段，所述驱动方法还包括：在第二数据写入阶段，向所述存储电路写入第二数据电压；在第二发光阶段，向所述存储电路写入所述控制信号，所述存储电路根据所述控制信号和所述第二数据电压产生随时间变化的第二控制电压，在所述第二控制电压的控制下，驱动所述发光元件发光。
例如，在本公开的一些实施例提供的驱动方法中，所述第一数据电压和所述第二数据电压不相同。
例如，在本公开的一些实施例提供的驱动方法中，所述发光元件在所述第一发光阶段的发光时间与所述发光元件在所述第二发光阶段的发光时间不相同。
例如，在本公开的一些实施例提供的驱动方法中，所述发光驱动电路包括驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述 数据写入电路和所述存储电路电连接，
所述控制信号包括最大值和最小值，
所述驱动晶体管为P型晶体管，所述最大值和所述最小值满足以下关系式：
V data1-V e1+V e2<V dd+V th
其中，V data1表示所述第一数据电压，V e1表示所述最大值，V e2表示所述最小值，V dd表示所述第一电源端输出的第一电源电压，V th表示所述驱动晶体管的阈值电压。
例如，在本公开的一些实施例提供的驱动方法中，所述发光驱动电路包括驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述数据写入电路和所述存储电路电连接，
所述控制信号包括最大值和最小值，
所述驱动晶体管为N型晶体管，所述最大值和所述最小值满足以下关系式：
V data1-V e2+V e1>V dd+V th
其中，V data1表示所述第一数据电压，V e1表示所述最大值，V e2表示所述最小值，V dd表示所述第一电源端输出的第一电源电压，V th表示所述驱动晶体管的阈值电压。
本公开的一些实施例还提供一种显示设备，包括根据上述任一项所述的像素电路。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种像素电路的示意框图；
图2为本公开一些实施例提供的一种像素电路的结构示意图；
图3A为本公开一些实施例提供的一种控制信号的示意图；
图3B为本公开另一些实施例提供的一种控制信号的示意图；
图4A为本公开另一些实施例提供的一种像素电路的结构示意图；
图4B为本公开一些实施例提供的一种信号转换子电路的结构示意图；
图5为本公开一些实施例提供的一种像素电路的驱动方法的示意性流程图；
图6是图2所示的像素电路的驱动方法的示例性时序图；
图7为本公开一些实施例提供的一种显示面板的示意性框图；
图8为本公开一些实施例提供的一种显示设备的示意性框图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
Micro LED(μ-LED)技术是一种见LED微缩化和矩阵化技术，简单来说，就是将LED进行薄膜化、微小化、阵列化，能够实现每个LED像素单元单独定址，单独驱动发光。Micro LED技术具有无机LED的高效率、高亮度、高可靠度及反应时间快等特点，又具有自发光无需背光源、体积小、轻薄等特点，还能轻易实现节能的效果，可通过转印等方法安装在电路基板上。然而，由于设置在玻璃基板上的驱动电路、不同电流时的色坐标偏移等问题，Micro LED显示面板难以实现产品化。
本公开至少一些实施例提供一种像素电路及其驱动方法、显示面板和显示设备，该像素电路可以在固定电压下通过控制作为发光元件的Micro LED的发光时间来控制灰阶，即利用固定电压配合随时间变化的控制电压(例如，第一控制电压、第二控制电压)实现显示更多灰阶的显示驱动方案，解决了Micro LED发光元件在不同电流下色坐标偏移的问题，该像素电路无需增加额外的器件即可实现控制Micro LED的发光时间，结构简单，成本低。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。
按照晶体管的特性，晶体管可以分为N型晶体管(N型MOS晶体管)和P型晶体管(P型MOS晶体管)，为了清楚起见，本公开的实施例以晶体管为P型晶体管为例详细阐述了本公开的技术方案，然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管实现本公开中的实施例中的一个或多个晶体管的功能。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开一些实施例提供的一种像素电路的示意框图。
例如，如图1所示，像素电路100包括发光驱动电路11、存储电路12和数据写入电路13。存储电路12包括第一端和第二端，存储电路12的第一端分别与数据写入电路13和发光驱动电路11电连接，存储电路12的第二端被配置为接收控制信号V cs，存储电路12被配置为接收并存储由数据写入电路13传输的第一数据电压V data1，且根据控制信号V cs和第一数据电压V data1产生随时间变化的第一控制电压V cv，使得第一控制电压V cv被施加至发光驱动电路11，以控制发光驱动电路11的开启时间；发光驱动电路11被配置为在第一控制电压V cv的控制下驱动发光元件10发光。
例如，数据写入电路13被配置为在扫描信号V scan的控制下将第一数据电压V data1写入存储电路12。
例如，在发光驱动电路11开启时，可以驱动发光元件10发光，也就是说，在不考虑误差的情况下，发光驱动电路11的开启时间与发光元件10的发光时间相同。通过控制在一帧时间内发光元件10的发光时间的长短即可控制发光元件10的显示亮度的大小(灰阶)，使发光元件10显示更多灰阶。例如，在每一帧时间内，若发光元件10的发光时间越长，则该发光元件10的显示亮度越高，即发光元件10对应的灰阶等级越大。
例如，发光元件10为发光二极管，例如，无机发光二极管。发光二极管的尺寸小于100微米，例如，1至10微米。例如，发光二极管可以发出红光、蓝光或绿光等。
图2为本公开一些实施例提供的一种像素电路的结构示意图。
例如，如图2所示，存储电路12的第二端与控制电压端Ctrl电连接，控制电压端Ctrl被配置为输出随时间变化的控制信号V cs。第一控制电压V cv经由存储电路12的第一端被施加至发光驱动电路11。
例如，控制信号V cs可以为三角波信号、锯齿波信号、正弦波信号或阶梯波信号等。只要在一帧时间中的发光阶段中，该控制信号V cs能够随时间变化，以使第一控制电压V cv能随时间变化，从而使得发光驱动电路的导通时间变化即可，本公开对控制信号V cs的具体类型不作限制。在一帧时间中的除了发光阶段之外的阶段(例如，在数据写入阶段等)中，该控制信号V cs可以仍然随时间变化，或者，其也可以不随时间而变化，即在除了发光阶段之外的阶段中，控制信号V cs不变。
例如，存储电路12被配置为将控制信号V cs和第一数据电压V data1相加以得到第一控制电压V cv，也就是说，第一控制电压V cv可以表示为：V cv＝V cs+V data1。
例如，像素电路100可以集成在衬底基板上，衬底基板可以为玻璃基板，即像素电路100形成在玻璃基板上。然而，本公开不限于此，衬底基板也可以为陶瓷基板、石英基板等合适的基板。
例如，如图2所示，发光驱动电路11包括驱动晶体管M1。驱动晶体管M1的第一极与第一电源端ELVDD电连接，驱动晶体管M1的第二极与发光元件10的第一端电连接，驱动晶体管M1的栅极分别与数据写入电路13和存储电路12电连接。发光元件10的第二端与第二电源端ELVSS电连接。
例如，第一控制电压V cv可以被施加至驱动晶体管M1的栅极，以控制驱 动晶体管M1开启或断开。
例如，在本公开的实施例中，“发光驱动电路11开启”可以表示驱动晶体管M1导通且处于线性放大状态，在此阶段，通过驱动晶体管M1的电流大小与驱动晶体管M1的源漏电压成正比，而与栅极电压无关。在本公开的一些实施例中，可以通过固定第一电源端ELVDD和第二电源端ELVSS之间的电压差，使得发光驱动电路11每次开启时，驱动电流基本相等，由此采用该像素电路的子像素的发光元件的单位时间亮度基本相等，使得子像素的灰阶只与发光驱动电路11开启的时间长短相关。
例如，第一电源端ELVDD和第二电源端ELVSS之一为高压端，另一个为低压端。例如，如图2所示的实施例中，第一电源端ELVDD为电压源以输出恒定的正电压；而第二电源端ELVSS可以为电压源以输出恒定的负电压，或可以接地等。相较于有机发光二极管面板的像素电路而言，本公开一些实施例提供的像素电路100中，第一电源端ELVDD和第二电源端ELVSS之间的电压差较小，例如，第一电源端ELVDD输出的电压可以为3V左右，第二电源端ELVSS输出的电压可以为0V左右，第一电源端ELVDD和第二电源端ELVSS之间的电压差约为3V。
图3A为本公开一些实施例提供的一种控制信号的示意图，图3B为本公开另一些实施例提供的一种控制信号的示意图。
例如，以控制信号V cs为三角波信号为例，控制信号V cs包括最大值和最小值。如图3A所示，以控制信号V cs和时间t为两个坐标轴建立坐标系，控制信号V cs为纵坐标，时间t为横坐标，在一些示例中，当驱动晶体管M1为N型晶体管时，控制信号V cs的最大值和最小值满足以下关系式：
V data1-V e2+V e1>V dd+V th  (1)
其中，V data1表示第一数据电压，V e1表示最大值，V e2表示最小值，V dd表示第一电源端ELVDD输出的第一电源电压，V th表示驱动晶体管M1的阈值电压。“控制信号V cs的最大值V e1”表示在发光阶段F2内控制信号V cs的最大值“，控制信号V cs的最小值V e2”表示在发光阶段F2内控制信号V cs的最小值。此时，控制信号V cs随时间逐渐增大，也就是说，在发光阶段F2的起点(即时间点t1)，控制信号V cs具有最小值V e2，在发光阶段F2的终点(即时间点t2)，控制信号V cs具有最大值V e1。
或者，如图3B所示，以控制信号V cs和时间t为两个坐标轴建立坐标系， 控制信号V cs为纵坐标，时间t为横坐标，在另一些示例中，当驱动晶体管M1为P型晶体管时，控制信号V cs的最大值和最小值满足以下关系式：
V data1-V e1+V e2<V dd+V th  (2)
其中，V data1表示第一数据电压，V e1表示最大值，V e2表示最小值，V dd表示第一电源端ELVDD输出的第一电源电压，V th表示驱动晶体管M1的阈值电压。此时，控制信号V cs随时间逐渐减小，也就是说，在发光阶段F2'的起点(即时间点t1')，控制信号V cs具有最大值V e1，在发光阶段F2'的终点(即时间点t2')，控制信号V cs具有最小值V e2。
需要说明的是，在图3A和图3B所示的示例中，以控制信号V cs为三角波信号为例，此时，控制信号V cs与时间呈线性关系，即控制信号V cs随时间线性增长。但本公开的实施例不限于此，控制信号V cs为正弦波信号，此时控制信号V cs与时间也可以呈非线性关系，即控制信号V cs随时间非线性增长。当控制信号V cs为正弦波信号时，在发光阶段F2内，正弦波信号也具有最大值和最小值，该最大值和最小值仍然满足上面的关系式(1)或关系式(2)。
例如，如图3A所示，以驱动晶体管M1为N型晶体管为例，在发光阶段F2中，在时间点t1(即发光阶段F2的起点)处，控制信号V cs具有最小值V e2，在时间点t2(即发光阶段F2的终点)处，控制信号V cs具有最大值V e1，在时间点t3(即临界时间点)处，控制信号V cs具有临界值V cr，此时，临界值V cr满足以下关系式：
V data1-V e2+V cr＝V dd+V th。
从而，在发光阶段F2中，从时间点t1至时间点t3之间的时间段Δt1中，驱动晶体管M1处于截止状态；从时间点t3至时间点t2之间的时间段Δt2中，驱动晶体管T2则开启，从而发光元件10可以被驱动发光。发光驱动电路11的开启时间为时间点t3至时间点t2之间的时间段Δt2。通过调节该三角波信号的斜率、最小值和最大值等参数即可调节时间段Δt2的大小，从而调节发光驱动电路11的开启时间的长短。
例如，如图3B所示，以驱动晶体管M1为P型晶体管为例，在发光阶段F2'中，在时间点t1'(即发光阶段F2'的起点)处，控制信号V cs具有最大值V e1，在时间点t2'(即发光阶段F2'的终点)处，控制信号V cs具有最小值V e2，在时间点t3'(即临界时间点)处，控制信号V cs具有临界值V' cr，此时，临界值V' cr满足以下关系式：
V data1-V e1+V' cr＝V dd+V th。
从而，在发光阶段F2'中，从时间点t1'至时间点t3'之间的时间段Δt1'中，驱动晶体管M1处于截止状态；从时间点t3'至时间点t2'之间的时间段Δt2'中，驱动晶体管M1则开启，从而发光元件10可以被驱动发光。发光驱动电路11的开启时间为时间点t3'至时间点t2'之间的时间段Δt2'。通过调节该三角波信号的斜率、最小值和最大值等参数即可调节时间段Δt2'的大小，从而调节发光驱动电路11的开启时间的长短。
例如，如图2所示，存储电路12包括电容C1。在一些示例中，存储电路12的第一端包括电容C1的第一极，存储电路12的第二端包括电容C1的第二极，即电容C1的第一极分别与数据写入电路13和发光驱动电路11电连接，电容C1的第二极与控制电压端Ctrl电连接。需要说明的是，图2所示的存储电路12仅是示意性的，本公开对存储电路12的具体结构不作限制。例如，存储电路12还可以包括电阻等元件，此时，电容C1的两极可以不是存储电路12的两端。
图4A为本公开另一些实施例提供的一种像素电路的结构示意图，图4B为本公开一些实施例提供的一种信号转换子电路的结构示意图。
例如，存储电路12的第二端与控制电压端Ctrl电连接，控制电压端Ctrl被配置为输出控制信号V cs，控制信号V cs可以为方波信号，也就是说，在发光阶段内，控制信号V cs不随时间变化，即控制信号V cs的值在整个发光阶段内均相同。
例如，如图4A所示，存储电路12可以包括电容C1'和信号转换子电路121。存储电路12的第一端包括电容C1'的第一极，存储电路12的第二端包括信号转换子电路121的第二端，即电容C1'的第一极分别与数据写入电路13和发光驱动电路11电连接，信号转换子电路121的第二端与控制电压端Ctrl电连接，电容C1'的第二极与信号转换子电路121的第一端连接。
例如，信号转换子电路121被配置为将控制信号V cs转换为随时间变化的中间控制信号，中间控制信号可以为三角波信号、锯齿波信号、正弦波信号或阶梯波信号等。电容C1'被配置为根据中间控制信号和第一数据电压V data1产生随时间变化的第一控制电压V cv。
例如，控制信号V cs为方波信号，中间控制信号为三角波信号，信号转换子电路121可以包括积分电路，如图4B所示，一种示例性的积分电路包括一 个电容C2、一个第一电阻R1、一个第二电阻R2和运算放大器OP，积分电路可以将方波信号转换为三角波信号或锯齿波信号等。在一些示例中，第一电阻R1的第一端被配置为接收控制信号V cs，第一电阻R1的第二端连接至运算放大器OP的反相输入端—；电容C2的第一端连接至运算放大器OP的反相输入端—，电容C2的第二端连接至运算放大器OP的输出端；第二电阻R2的第一端连接至运算放大器OP的同相输入端+，第二电阻R2的第二端接地。运算放大器OP的输出端被配置为输出中间控制信号V mc。通过调节积分电路中的电容C2、第一电阻R1和第二电阻R2的参数可以实现调节中间控制信号V mc的频率、最大值、最小值等参数。另外，中间控制信号V mc还随控制信号V cs而变化，即控制信号V cs(例如，周期、幅值等)不同，则产生的中间控制信号V mc也不相同。
需要说明的是，信号转换子电路121可以形成在该衬底基板上。但本公开的实施例不限于此，在一些实施例中，信号转换子电路121也可以形成在驱动芯片上，以减少像素电路100在衬底基板上占用的面积，提高分辨率。例如，驱动芯片通过柔性电路板绑定在衬底基板上，此时，存储电路12中的电容C1'仍可以形成在衬底基板上。
例如，如图2和图4A所示，数据写入电路13包括数据写入晶体管M2。数据写入晶体管M2的第一极与数据线D电连接，以接收第一数据电压V data1，数据写入晶体管M2的第二极与存储电路12电连接，数据写入晶体管M2的栅极与扫描信号线G电连接，以接收扫描信号V scan。
例如，如图2所示，数据写入晶体管M2的第二极与电容C1的第一极电连接；数据线D被配置为向数据写入晶体管M2提供第一数据电压V data1；扫描信号线G被配置为向数据写入晶体管M2提供扫描信号V scan。例如，在数据写入阶段，扫描信号线G可以向数据写入晶体管M2的栅极提供扫描信号，以使数据写入晶体管M2导通。由此，数据写入晶体管M2可以将第一数据电压V data1传输至电容C1的第一极，电容C1可以存储该第一数据电压V data1。
例如，如图2和图4A所示，像素电路100还包括发光控制电路14。发光控制电路14被配置为在发光控制信号的控制下控制发光驱动电路11驱动发光元件10发光。
例如，发光控制电路14可以包括第一发光控制晶体管M3和第二发光控制晶体管M4。如图2和图4A所示，第一发光控制晶体管M3的第一极与第一 电源端ELVDD电连接，第一发光控制晶体管M3的第二极与驱动晶体管M1的第一极电连接，第一发光控制晶体管M3的栅极与发光控制线EM电连接，以接收发光控制信号V EM；第二发光控制晶体管M4的第一极与驱动晶体管M1的第二极电连接，第二发光控制晶体管M4的第二极与发光元件10的第一端电连接，第二发光控制晶体管M4的栅极与发光控制线EM电连接，以接收发光控制信号V EM。
例如，在数据写入阶段，第二发光控制晶体管M4可以将驱动晶体管M1和发光元件10断开，以保证发光元件10不发光。在发光阶段，发光控制线EM可以向第一发光控制晶体管M3和第二发光控制晶体管M4提供发光控制信号V EM，以使第一发光控制晶体管M3和第二发光控制晶体管M4导通，从而形成从第一电源端ELVDD至第二电源端ELVSS的导通回路，发光电流可以经由导通的驱动晶体管M1被传输至发光元件10以驱动其发光。第一控制电压V cv可以控制驱动晶体管M2的开启时间，从而控制发光元件10的发光时间，发光时间的长短可以决定发光元件10的显示亮度，即发光元件10对应的灰阶等级。
需要说明的是，在图2和图4A所示的示例中，第一发光控制晶体管M3的栅极和第二发光控制晶体管M4的栅极连接到相同的发光控制线EM，以接收相同的发光控制信号V EM。但不限于此，在其他实施例中，第一发光控制晶体管M3的栅极和第二发光控制晶体管M4的栅极也可以电连接至不同的发光控制线，而不同的发光控制线施加的发光控制信号同步。本公开的实施例对第一发光控制晶体管M3和第二发光控制晶体管M4的控制方式不作限制。
值得注意的是，发光驱动电路11、存储电路12、数据写入电路13和发光控制电路14不限于上述实施例中描述的结构，其具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。像素电路100还可以包括复位电路、补偿电路等，例如，补偿电路可以通过电压补偿、电流补偿或混合补偿来实现，补偿电路可以补偿驱动晶体管M1的阈值电压和电源端的电压降(IR drop)等，以提升显示质量、改善显示效果。复位电路可以对驱动晶体管M1的栅极进行复位，以防止不同帧之间的信号相互干扰。
本公开一些实施例还提供一种像素电路的驱动方法，该驱动方法可以应用于上述任一项所述的像素电路。
图5为本公开一些实施例提供的一种像素电路的驱动方法的示意性流程 图。
例如，一帧时间包括第一数据写入阶段和第一发光阶段。如图5所示，像素电路的驱动方法包括以下步骤：
S101：在第一数据写入阶段，向存储电路写入第一数据电压；
S102：在第一发光阶段，向存储电路写入控制信号，存储电路根据控制信号和第一数据电压产生随时间变化的第一控制电压，在第一控制电压的控制下，驱动发光元件发光。
该像素电路的驱动方法在固定电压下通过控制Micro LED的发光时间来控制灰阶，即利用固定电压配合随时间变化的控制电压(例如，第一控制电压)实现显示更多灰阶的显示驱动方案，从而解决了Micro LED发光器件对不同电流下色坐标偏移的问题。
例如，控制信号可以为随时间变化的信号，存储电路可以包括电容，即存储电路为图2所示的示例中的存储电路，在该示例中，在步骤S102中，根据控制信号和第一数据电压产生随时间变化的第一控制电压包括：将控制信号和第一数据电压相加以得到第一控制电压。
例如，控制信号可以为不随时间变化的信号，例如，控制信号为方波信号，此时，存储电路包括电容和信号转换子电路，即存储电路为图4A所示的示例中的存储电路，在该示例中，在步骤S102中，根据控制信号和第一数据电压产生随时间变化的第一控制电压包括：通过信号转换子电路将控制信号转换为中间控制信号，其中，中间控制信号为随时间变化的信号；将中间控制信号和第一数据电压相加以得到第一控制电压。
例如，发光驱动电路包括驱动晶体管，在步骤S102中，在第一控制电压的控制下，驱动发光元件发光包括：第一控制电压控制驱动晶体管开启，以使发光电流经由驱动晶体管流入发光元件以驱动发光元件发光。例如，第一控制电压可以控制驱动晶体管的开启时间，以控制发光元件的发光时间，最终控制发光元件的发光亮度(即灰阶)。
例如，在一些实施例中，一帧时间还包括第二数据写入阶段和第二发光阶段，驱动方法还包括：
S103：在第二数据写入阶段，向存储电路写入第二数据电压；
S104：在第二发光阶段，向存储电路写入控制信号，存储电路根据控制信号和第二数据电压产生随时间变化的第二控制电压，在第二控制电压的控制 下，驱动发光元件发光。
在该驱动方法中，在一帧时间内，驱动发光元件多次发光，通过叠加多次发光过程中发光元件的发光时间最终控制显示面板的灰阶，从而可以在一帧时间内实现显示更多的灰阶。
例如，在一些实施例中，控制信号为随时间变化的信号，且在第一发光阶段内，控制信号包括第一最大值和第一最小值。
在一些示例中，当驱动晶体管为P型晶体管，第一最大值和第一最小值满足以下关系式：
V data1-V e11+V e12<V dd+V th
其中，V data1表示第一数据电压，V e11表示第一最大值，V e12表示第一最小值，V dd表示第一电源端输出的第一电源电压，V th表示驱动晶体管的阈值电压。
例如，控制信号还具有第一临界值，第一临界值V cr1满足以下关系式：
V data1-V e11+V cr1＝V dd+V th。
在另一些示例中，当驱动晶体管为N型晶体管，第一最大值和第一最小值满足以下关系式：
V data1-V e12+V e11>V dd+V th
其中，V data1表示第一数据电压，V e11表示第一最大值，V e12表示第一最小值，V dd表示第一电源端输出的第一电源电压，V th表示驱动晶体管的阈值电压。
例如，控制信号还具有第一临界值，第一临界值V cr1满足以下关系式：
V data1-V e12+V cr1＝V dd+V th。
例如，在一些实施例中，控制信号为随时间变化的信号，且在第二发光阶段内，控制信号包括第二最大值和第二最小值。
在一些示例中，当驱动晶体管为P型晶体管，第二最大值和第二最小值满足以下关系式：
V data2-V e21+V e22<V dd+V th
其中，V data2表示第二数据电压，V e21表示第二最大值，V e22表示第二最小值，V dd表示第一电源端输出的第一电源电压，V th表示驱动晶体管的阈值电压。
例如，控制信号还具有第二临界值，第二临界值V cr2满足以下关系式：
V data2-V e21+V cr2＝V dd+V th。
在另一些示例中，当驱动晶体管为N型晶体管，第二最大值和第二最小值满足以下关系式：
V data2-V e22+V e21>V dd+V th
其中，V data2表示第二数据电压，V e21表示第二最大值，V e22表示第二最小值，V dd表示第一电源端输出的第一电源电压，V th表示驱动晶体管的阈值电压。
例如，控制信号还具有第二临界值，第二临界值V cr2满足以下关系式：
V data2-V e22+V cr2＝V dd+V th。
在另一些示例中，当驱动晶体管为需要说明的是，关于第一最大值和第二最大值的相关说明可以参考像素电路的实施例中关于最大值的相关描述，关于第一最小值和第二最小值的相关说明可以参考像素电路的实施例中关于最小值的相关描述，关于第一临界值和第二临界值的相关说明可以参考像素电路的实施例中关于临界值的相关描述，重复之处在此不再赘述。
例如，在第一发光阶段，发光元件的发光时间为第一发光时间；在第二发光阶段，发光元件的发光时间为第二发光时间。发光元件在第一发光阶段的发光时间与发光元件在第二发光阶段的发光时间不相同，即第一发光时间和第二发光时间不相同。
例如，在一些实施例中，第一数据电压和第二数据电压可以不相同。在第一发光阶段和第二发光阶段中的控制信号可以相同，此时，在第一发光阶段生成的第一控制电压和在第二发光阶生成的第二控制电压不相同，由此，第一发光时间和第二发光时间可以不相同。
又例如，在另一些实施例中，第一数据电压和第二数据电压可以相同。在第一发光阶段和第二发光阶段中的控制信号可以不相同，此时，在第一发光阶段生成的第一控制电压和在第二发光阶生成的第二控制电压不相同，由此，第一发光时间和第二发光时间可以不相同。
或者，在还一些实施例中，第一数据电压和第二数据电压可以不相同，在第一发光阶段和第二发光阶段中的控制信号也可以不相同，此时，在第一发光阶段生成的第一控制电压和在第二发光阶生成的第二控制电压不相同，由此，第一发光时间和第二发光时间可以不相同。
再例如，在又一些实施例中，第一数据电压和第二数据电压可以相同。在第一发光阶段和第二发光阶段中的控制信号也可以相同，此时，在第一发光阶段生成的第一控制电压和在第二发光阶生成的第二控制电压相同，由此，第一发光时间和第二发光时间可以相同。
需要说明的是，第一数据电压、第二数据电压、在第一发光阶段的控制信 号和在第二发光阶段的控制信号可以根据实际应用设计，本公开的实施例对此不作限制。第二发光阶段的操作过程与第一发光阶段类似，关于第二发光阶段的操作过程的相关说明可以参考上面关于第一发光阶段的描述，重复之处不再赘述。
例如，像素电路的时序图可以根据实际需求进行设定，本公开的实施例对此不作具体限定。
在一些示例中，图6是图2所示的像素电路的驱动方法的示例性时序图。下面结合图2和图6详细说明本公开实施例提供的一种像素电路的驱动方法的操作流程。
例如，如图2和图6所示，在第一数据写入阶段TP1，发光控制线EM提供的发光控制信号为高电平信号，从而第一发光控制晶体管M3和第二发光控制晶体管M4断开，从而无电流流至发光元件10，发光元件10不发光。通过多条扫描信号线G1～Gn依次向多行像素电路提供扫描信号，扫描信号线提供的扫描信号处于有效部分(即使得与之相连接的开关电路(例如晶体管)导通的部分)，例如为低电平信号，从而数据写入晶体管M2导通，多个第一数据电压可以依次被存入各个像素电路的存储电路中。需要说明的是，多个第一数据电压可以各不相同，也可以至少部分相同。
例如，在第一数据写入阶段TP1，控制信号V cs不随时间变化。
例如，如图2和图6所示，在第一发光阶段TP2，发光控制线EM提供的发光控制信号为低电平信号，从而第一发光控制晶体管M3和第二发光控制晶体管M4导通，同时多条扫描信号线G1～Gn依次向多行像素电路提供的扫描信号处于无效部分，例如为高电平信号，从而数据写入晶体管M2截止，这也使得电容C1的第一端实质上被悬空。此时，控制信号V cs为如图6所示的三角波信号，若在第一数据写入阶段TP1中，第一数据电压满足如下关系式：
V data1≤V dd+V th
其中，V data1表示第一数据电压，V dd表示第一电源端ELVDD输出的第一电源电压，V th表示驱动晶体管M1的阈值电压。此时，在整个第一发光阶段TP2，驱动晶体管M1均开启，从而发光元件10的发光时间如图6所示的P1波形，即发光元件10的发光时间为第一发光阶段TP2的时间的100％，也就是说，在整个第一发光阶段TP2，发光元件10均发光。
而当在第一数据写入阶段TP1中，第一数据电压满足如下关系式：V data1 ＞V dd+V th，则在第一发光阶段TP2的初始时间段内，驱动晶体管M1处于截止状态，没有电流流至发光元件10，发光元件10不发光。由于控制信号V cs随时间浮动，并且由于电容C1的第一端实质上被悬空，根据电容的电荷守恒定律，电容C1的第一端的电压值也跟着控制信号V cs浮动，当控制信号V cs的值超过临界值后，驱动晶体管M1开启，从而发光元件10开始发光。最终，发光元件10的发光时间呈现出如图6所示的P2波形、P3波形或P4波形，即发光元件10的发光时间分别可以为第一发光阶段TP2的时间的75％、50％或者25％。
例如，发光元件10的发光时间的长短取决于电容C1的第一端的电压值与驱动晶体管M1的阈值电压V th的关系，发光元件10的发光时间不限于第一发光阶段TP2的时间的75％、50％、25％，也可以是第一发光阶段TP2的时间的70％、20％或15％。
例如，如图2和图6所示，在第二数据写入阶段TP3，此阶段重复执行第一数据写入阶段TP1的操作，即在第二数据写入阶段TP3，发光控制线EM提供的发光控制信号为高电平信号，从而第一发光控制晶体管M3和第二发光控制晶体管M4断开，从而无电流流至发光元件10，发光元件10不发光。通过多条扫描信号线G1～Gn依次向多行像素电路提供扫描信号，扫描信号线提供的扫描信号处于有效部分，为低电平信号，从而数据写入晶体管M2导通，多个第二数据电压可以依次被存入各个像素电路的存储电路中。需要说明的是，多个第二数据电压可以各不相同，也可以至少部分相同。第一数据电压和第二数据电压可以不相同，但本公开不限于此，第一数据电压和第二数据电压也可以相同。
例如，在第二数据写入阶段TP3，控制信号V cs也不随时间变化。
例如，如图2和图6所示，在第二发光阶段TP4，此阶段重复执行第一发光阶段TP2的操作，即在第二发光阶段TP4，发光控制线EM提供的发光控制信号为低电平信号，从而第一发光控制晶体管M3和第二发光控制晶体管M4导通，同时多条扫描信号线G1～Gn依次向多行像素电路提供的扫描信号处于无效部分，为高电平信号，从而数据写入晶体管M2截止，这也使得电容C1的第一端实质上被悬空。此时，控制信号V cs为如图6所示的三角波信号，若在第二数据写入阶段TP3中，第二数据电压满足如下关系式：
V data2≤V dd+V th
其中，V data2表示第二数据电压，V dd表示第一电源端ELVDD输出的第一电源电压，V th表示驱动晶体管M1的阈值电压，且为负值。此时，在整个第二发光阶段TP4，驱动晶体管M1均开启，从而发光元件10的发光时间为第二发光阶段TP4的时间的100％，也就是说，在整个第二发光阶段TP4，发光元件10均发光。
而当在第二数据写入阶段TP3中，若第二数据电压满足如下关系式：V data2＞V dd+V th，则在第二发光阶段TP4的初始时间段内，驱动晶体管M1处于截止状态，没有电流流至发光元件10，发光元件10不发光。由于控制信号V cs随时间浮动，根据电容的电荷守恒定律，电容C1的第一端的电压值也跟着控制信号V cs浮动，当控制信号V cs的值超过临界值后，驱动晶体管M1开启，从而发光元件10开始发光。最终，发光元件10的发光时间呈现出如图6所示的P1波形、P2波形、P3波形或P4波形，即发光元件10的发光时间分别可以为第二发光阶段TP4的时间的25％、75％、50％或者25％。
例如，一帧时间中，一个发光元件的发光时间为在第一发光阶段TP2中的发光时间和第二发光阶段TP4中的发光时间的叠加。当在一帧时间中，该发光元件的发光时间的如图6中的P1波形，则该发光元件的发光时间可以表示为：
t EL＝100％*t TP2+25％*t TP4
其中，t EL表示发光元件在一帧时间中的发光时间，t TP2表示一帧时间中的第一发光阶段TP2的时间，t TP4表示一帧时间中的第二发光阶段TP4的时间。
当在一帧时间中，该发光元件的发光时间的如图6中的P2波形，则该发光元件的发光时间可以表示为：
t EL＝70％*t TP2+50％*t TP4
其中，t EL表示发光元件在一帧时间中的发光时间，t TP2表示一帧时间中的第一发光阶段TP2的时间，t TP4表示一帧时间中的第二发光阶段TP4的时间。
综上，显示面板上的显示画面可以通过两次不同发光时间的叠加来实现更多灰阶。
需要说明的是，本公开的实施例不限于将一帧时间划分为两个数据写入阶段和两个发光阶段，在一些示例中，一帧时间还可以被划分为一个数据写入阶段和一个发光阶段、三个数据写入阶段和三个发光阶段、四个数据写入阶段和四个发光阶段等。
本公开一些实施例还提供一种显示面板。图7为本公开一些实施例提供的 一种显示面板的示意性框图。如图7所示，显示面板70包括多个像素单元110，多个像素单元110可以阵列排布。每个像素单元110可以包括发光元件120和上述任一实施例所述的像素电路100。发光元件120即为上述像素电路100的实施例中的发光元件10，重复之处不再赘述。
该显示面板中的像素电路可以在固定电压下通过控制Micro LED的发光时间来控制灰阶，即利用固定电压配合随时间变化的控制电压实现显示更多灰阶的显示驱动方案，解决了Micro LED发光器件对不同电流下色坐标偏移的问题，该显示面板中的像素电路无需额外增加器件即可实现控制Micro LED的发光时间，结构简单，成本低。
例如，在一些实施例中，施加到显示面板70上的所有像素单元的像素电路上的控制信号均相同；在另一些实施例中，施加到位于同一行的像素单元中的所有像素电路100上的控制信号相同，而施加到位于不同行的像素单元中的控制信号则不相同。
例如，在不同帧中的多个控制信号均相同；或者，在不同帧中的多个控制信号可以至少部分不相同。
例如，显示面板70还包括衬底基板，衬底基板可以为玻璃基板，像素电路100和发光元件120均形成在衬底基板上，或者至少部分在其他中间基板上制备后通过转印等方法转移并安装到衬底基板上。
例如，显示面板70可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板70不仅可以为平面面板，也可以为曲面面板，甚至球面面板。
例如，显示面板70还可以具备触控功能，即显示面板70可以为触控显示面板。
本公开实施例还提供一种显示设备。图8为本公开一些实施例提供的一种显示设备的示意性框图。如图8所示，显示设备80可以包括上述任一所述的显示面板70，显示面板70用于显示图像。
例如，显示设备80还可以包括栅极驱动器82。栅极驱动器320被配置为通过扫描信号线与数据写入电路电连接，以用于为数据写入电路提供扫描信号。
例如，显示设备80还可以包括数据驱动器84。数据驱动器84被配置为通过数据线与数据写入电路电连接，以用于向显示面板70提供数据电压，例如， 第一数据电压和第二数据电压。
例如，显示设备80可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，对于显示设备80的其它组成部分(例如控制装置、图像数据编码/解码装置、时钟电路等)均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种像素电路，包括：发光驱动电路、存储电路和数据写入电路，
    其中，所述存储电路的第一端分别与所述数据写入电路和所述发光驱动电路电连接，所述存储电路的第二端被配置为接收控制信号，所述存储电路被配置为接收并存储由所述数据写入电路传输的第一数据电压，且根据所述控制信号和所述第一数据电压产生随时间变化的第一控制电压，使得所述第一控制电压被施加至所述发光驱动电路，以控制所述发光驱动电路的开启时间；
    所述发光驱动电路被配置为在所述第一控制电压的控制下驱动发光元件发光。
  2. 根据权利要求1所述的像素电路，其中，所述存储电路的第二端与控制电压端电连接，所述控制电压端被配置为输出随时间变化的所述控制信号。
  3. 根据权利要求2所述的像素电路，其中，所述控制信号为三角波信号、锯齿波信号或正弦波信号。
  4. 根据权利要求2或3任一项所述的像素电路，其中，所述存储电路包括电容。
  5. 根据权利要求1所述的像素电路，其中，所述存储电路的第二端与控制电压端电连接，所述控制电压端被配置为输出所述控制信号，所述控制信号为方波信号。
  6. 根据权利要求5所述的像素电路，其中，所述存储电路包括电容和信号转换子电路，
    所述存储电路的第一端包括所述电容的第一极，所述存储电路的第二端包括所述信号转换子电路的第二端，所述电容的第二极与所述信号转换子电路的第一端连接，
    所述信号转换子电路被配置为将所述控制信号转换为随时间变化的中间控制信号，
    所述电容被配置为根据所述中间控制信号和所述第一数据电压产生所述第一控制电压。
  7. 根据权利要求2-4任一项所述的像素电路，其中，所述发光驱动电路包括驱动晶体管，
    所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极 与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述数据写入电路和所述存储电路电连接。
  8. 根据权利要求1-7任一项所述的像素电路，其中，所述数据写入电路包括数据写入晶体管，
    所述数据写入晶体管的第一极与数据线电连接，所述数据写入晶体管的第二极与所述存储电路电连接，所述数据写入晶体管的栅极与扫描信号线电连接，以接收所述扫描信号。
  9. 根据权利要求7所述的像素电路，还包括：发光控制电路，
    其中，所述发光控制电路被配置为在发光控制信号的控制下控制所述发光驱动电路驱动所述发光元件发光。
  10. 根据权利要求9所述的像素电路，其中，所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管，
    所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极与发光控制线电连接，以接收所述发光控制信号；
    所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一端电连接，所述第二发光控制晶体管的栅极与所述发光控制线电连接，以接收所述发光控制信号。
  11. 根据权利要求1所述的像素电路，还包括：发光控制电路，
    其中，所述发光驱动电路包括驱动晶体管，所述数据写入电路包括数据写入晶体管，所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管，所述存储电路包括电容，
    所述数据写入晶体管的第一极与数据线电连接，所述数据写入晶体管的第二极与所述电容的第一极电连接，所述数据写入晶体管的栅极与扫描信号线电连接，以接收所述扫描信号；
    所述电容的第二极被配置为接收控制信号，所述控制信号为三角波信号、锯齿波信号或正弦波信号；
    所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述数据写入晶体管的第二极和所述电容的第一极电连接；
    所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发 光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极与发光控制线电连接，以接收所述发光控制信号；
    所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一端电连接，所述第二发光控制晶体管的栅极与所述发光控制线电连接，以接收所述发光控制信号；
    所述发光元件的第二端与第二电源端电连接。
  12. 根据权利要求1-11任一项所述的像素电路，其中，所述发光元件为发光二极管，所述发光二极管的尺寸小于100微米。
  13. 一种应用于根据权利要求1-12任一项所述的像素电路的驱动方法，其中，一帧时间包括第一数据写入阶段和第一发光阶段，包括：
    在第一数据写入阶段，向所述存储电路写入所述第一数据电压；
    在第一发光阶段，向所述存储电路写入所述控制信号，所述存储电路根据所述控制信号和所述第一数据电压产生随时间变化的所述第一控制电压，在所述第一控制电压的控制下，驱动所述发光元件发光。
  14. 根据权利要求13所述的驱动方法，其中，所述一帧时间还包括第二数据写入阶段和第二发光阶段，
    所述驱动方法还包括：
    在第二数据写入阶段，向所述存储电路写入第二数据电压；
    在第二发光阶段，向所述存储电路写入所述控制信号，所述存储电路根据所述控制信号和所述第二数据电压产生随时间变化的第二控制电压，在所述第二控制电压的控制下，驱动所述发光元件发光。
  15. 根据权利要求14所述的驱动方法，其中，所述第一数据电压和所述第二数据电压不相同。
  16. 根据权利要求15所述的驱动方法，其中，所述发光元件在所述第一发光阶段的发光时间与所述发光元件在所述第二发光阶段的发光时间不相同。
  17. 根据权利要求13-16任一项所述的驱动方法，其中，所述发光驱动电路包括驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述数据写入电路和所述存储电路电连接，
    所述控制信号包括最大值和最小值，
    所述驱动晶体管为P型晶体管，所述最大值和所述最小值满足以下关系 式：
    V data1-V e1+V e2<V dd+V th
    其中，V data1表示所述第一数据电压，V e1表示所述最大值，V e2表示所述最小值，V dd表示所述第一电源端输出的第一电源电压，V th表示所述驱动晶体管的阈值电压。
  18. 根据权利要求13-16任一项所述的驱动方法，其中，所述发光驱动电路包括驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述发光元件的第一端电连接，所述驱动晶体管的栅极分别与所述数据写入电路和所述存储电路电连接，
    所述控制信号包括最大值和最小值，
    所述驱动晶体管为N型晶体管，所述最大值和所述最小值满足以下关系式：
    V data1-V e2+V e1>V dd+V th
    其中，V data1表示所述第一数据电压，V e1表示所述最大值，V e2表示所述最小值，V dd表示所述第一电源端输出的第一电源电压，V th表示所述驱动晶体管的阈值电压。
  19. 一种显示设备，包括根据权利要求1-12任一项所述的像素电路。
PCT/CN2019/070485 2019-01-04 2019-01-04 像素电路及其驱动方法、显示面板和显示设备 WO2020140287A1 (zh)

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CN114093300B (zh) * 2020-07-30 2023-04-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN113674694B (zh) * 2021-08-23 2023-09-01 京东方科技集团股份有限公司 显示基板及显示装置
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227262A1 (en) * 2002-06-11 2003-12-11 Samsung Sdi Co., Ltd. Light emitting display, light emitting display panel, and driving method thereof
CN1979618A (zh) * 2005-12-06 2007-06-13 三星电子株式会社 显示装置及其驱动方法
CN103578426A (zh) * 2012-08-02 2014-02-12 三星显示有限公司 有机发光二极管显示器
CN107993609A (zh) * 2018-03-16 2018-05-04 成都晶砂科技有限公司 模拟和数字混合驱动显示单元显示的方法、系统及驱动电路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809710B2 (en) * 2000-01-21 2004-10-26 Emagin Corporation Gray scale pixel driver for electronic display and method of operation therefor
JP2006309104A (ja) * 2004-07-30 2006-11-09 Sanyo Electric Co Ltd アクティブマトリクス駆動型表示装置
JP4890470B2 (ja) * 2005-12-06 2012-03-07 パイオニア株式会社 アクティブマトリクス型表示装置及び駆動方法
KR101289642B1 (ko) * 2009-05-11 2013-07-30 엘지디스플레이 주식회사 액정표시장치
WO2014021159A1 (ja) * 2012-07-31 2014-02-06 シャープ株式会社 画素回路、それを備える表示装置、およびその表示装置の駆動方法
KR101411757B1 (ko) * 2012-11-09 2014-06-25 엘지디스플레이 주식회사 유기발광 표시장치
TWI623927B (zh) * 2017-07-20 2018-05-11 友達光電股份有限公司 顯示面板及其畫素的驅動方法
TWI643175B (zh) * 2018-03-06 2018-12-01 友達光電股份有限公司 微發光二極體顯示面板和驅動方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227262A1 (en) * 2002-06-11 2003-12-11 Samsung Sdi Co., Ltd. Light emitting display, light emitting display panel, and driving method thereof
CN1979618A (zh) * 2005-12-06 2007-06-13 三星电子株式会社 显示装置及其驱动方法
CN103578426A (zh) * 2012-08-02 2014-02-12 三星显示有限公司 有机发光二极管显示器
CN107993609A (zh) * 2018-03-16 2018-05-04 成都晶砂科技有限公司 模拟和数字混合驱动显示单元显示的方法、系统及驱动电路

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