WO2021203476A1 - 一种同步发光的像素补偿电路及显示面板 - Google Patents

一种同步发光的像素补偿电路及显示面板 Download PDF

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Publication number
WO2021203476A1
WO2021203476A1 PCT/CN2020/085885 CN2020085885W WO2021203476A1 WO 2021203476 A1 WO2021203476 A1 WO 2021203476A1 CN 2020085885 W CN2020085885 W CN 2020085885W WO 2021203476 A1 WO2021203476 A1 WO 2021203476A1
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Prior art keywords
transistor
pixel compensation
electrode
voltage
node
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PCT/CN2020/085885
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English (en)
French (fr)
Inventor
陈金祥
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/766,749 priority Critical patent/US20220415273A1/en
Publication of WO2021203476A1 publication Critical patent/WO2021203476A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • This application relates to the field of display technology, and in particular to a pixel compensation circuit and a display panel that emit light simultaneously.
  • A-Si (A-Si) TFT with mature technology has good large-area production uniformity and is widely used in TFT-Liquid Crystal Display (Liquid Crystal Display). Display, LCD for short); 2) Low Temperature Poly-Silicon (LTPS) TFT has high mobility and good stability, and is suitable for small and medium-sized panels; 3) Oxide TFT has high mobility and large The area production uniformity is good, the preparation temperature is low, the transparency is good, and the flexibility is high, so it can be applied to large-size high-definition displays.
  • LTPS Low Temperature Poly-Silicon
  • amorphous silicon TFTs have low mobility and are difficult to meet higher resolution requirements; low-temperature polysilicon TFTs have poor uniformity in large-area production due to the existence of grain boundaries; oxide TFTs have large threshold voltage (Vth) shifts, resulting in panel moiré (Mura) The defect is serious.
  • the embodiments of the present application provide a pixel compensation circuit and a display panel for synchronous light emission, which can resolve the threshold voltage difference of driving TFTs, realize compensation for positive and negative threshold voltage drifts, reduce the number of progressive scan signals, and realize synchronous light emission.
  • the embodiment of the present application provides a pixel compensation circuit for synchronous light emission.
  • the circuit includes a plurality of pixel compensation units, and the pixel compensation unit includes: a reset signal response module for transmitting an initialization voltage in response to a reset signal; A sensing signal response module for transmitting the initialization voltage and a reference voltage in response to a sensing signal; a scanning transistor for transmitting a data voltage in response to a scanning signal; a driving transistor, the driving transistor Using a dual-gate metal oxide field effect transistor, the bottom gate electrode of the driving transistor is electrically connected to a first node to receive the reference voltage, and the top gate electrode is electrically connected to a second node to receive the initialization voltage or the For data voltage, its first electrode is electrically connected to a driving voltage terminal, and its second electrode is electrically connected to a third node to receive the initialization voltage; the driving transistor is used to pass the bottom according to the initialization voltage and the reference voltage.
  • the gate electrode regulates and modulates the threshold voltage of the driving transistor, and is used to generate a driving current according to the data voltage; and a light emitting device is used to emit light according to the driving current; wherein, in the circuit, the scan signal It is a signal for progressive scanning, which is used to turn on the scanning transistors of the corresponding pixel compensation unit row by row in one frame time; the reset signal and the sensing signal are global signals, which are used to control all the pixels in one frame time.
  • the pixel compensation unit performs corresponding control.
  • An embodiment of the present application also provides a pixel compensation circuit for synchronous light emission, the circuit includes a plurality of pixel compensation units, and the pixel compensation unit includes: a reset signal response module for transmitting an initialization voltage in response to a reset signal A sensing signal response module, used to respond to a sensing signal to respectively transmit the initialization voltage and a reference voltage; a scan transistor, used to respond to a scan signal to transmit a data voltage; a drive transistor, the drive The transistor adopts a double-gate structure, and the driving transistor is used for adjusting and modulating the threshold voltage of the driving transistor through a bottom gate electrode according to the initialization voltage and the reference voltage, and for generating a driving current according to the data voltage; and A light emitting device for emitting light according to the driving current.
  • An embodiment of the present application also provides a display panel.
  • the display panel includes an array substrate; the array substrate includes the synchronously emitting pixel compensation circuit described in the present application.
  • the pixel compensation circuit of the present application adopts a double-gate structure transistor as the driving transistor, and regulates and modulates the threshold voltage of the driving transistor through the bottom gate electrode, so as to realize compensation for the positive and negative drift of the threshold voltage of the driving transistor, and solve the threshold voltage difference of the driving transistor.
  • Improve the uniformity of panel brightness by introducing synchronous lighting technology, using global signals for corresponding control, the number of progressive scan signals is reduced to only one, the circuit structure is simple, and fewer transistors are required, which is conducive to in-plane integration.
  • Figure 1 is a schematic diagram of the dual-gate field-effect transistor structure and the threshold voltage regulation of different width-to-length ratios
  • FIG. 2 is a structural diagram of a pixel compensation circuit for synchronous light emission in this application
  • 3A is a circuit diagram of a first embodiment of a pixel compensation circuit for synchronous light emission according to the present application
  • FIG. 3B is a driving timing diagram of the pixel compensation circuit shown in FIG. 3A;
  • 4A is a circuit diagram of a second embodiment of a pixel compensation circuit for synchronous light emission according to this application;
  • 4B is a driving timing diagram of the pixel compensation circuit shown in FIG. 4A;
  • FIG. 5 is a schematic diagram of the structure of the display panel of this application.
  • FIG. 1 is a schematic diagram of a dual-gate field effect transistor structure and threshold voltage regulation of different width-to-length ratios.
  • the dual gate field effect transistor 10 is a dual gate metal oxide field effect transistor, which includes a bottom gate electrode BG, a top gate electrode TG, a source electrode S, and a drain electrode D.
  • the threshold voltage Vth of the double gate metal oxide field effect transistor 10 can be adjusted by adjusting the bottom gate electrode BG of the double gate metal oxide field effect transistor 10.
  • the dual-gate metal oxide field effect transistor 10 may be an indium tin zinc oxide thin film transistor (ITZO TFT).
  • FIG. 2 is a structural diagram of a pixel compensation circuit that emits synchronously in the present application.
  • the pixel compensation circuit of the present application includes a plurality of pixel compensation units 20, and the pixel compensation unit 20 includes: a reset signal response module 21, a sensing signal response module 22, a scanning transistor T2, a driving transistor T1, and a light emitting device 29 .
  • the reset signal response module 21 is used to respond to a reset signal RESET to transmit an initialization voltage Vini; the sensing signal response module 22 is used to respond to a sensing signal SENSE to respectively transmit the initialization voltage Vini and a reference voltage Vref
  • the scan transistor T2 is used to respond to a scan signal SCAN to transmit a data voltage Vdata; the drive transistor T1 adopts a double-gate structure (Double-Gate), used according to the initialization voltage Vini and the reference voltage Vref,
  • the bottom gate electrode regulates and modulates the threshold voltage Vth of the driving transistor T1, and is used to generate a driving current according to the data voltage Vdata; and the light emitting device 29 is used to emit light according to the driving current.
  • the driving transistor T1 with a double gate structure, its bottom gate electrode (BG) is electrically connected to a first node Q1, its top gate electrode (TG) is electrically connected to a second node Q2, and its first electrode is electrically connected to a
  • the driving voltage terminal EVDD receives a driving voltage VDD, and its second electrode is electrically connected to a third node Q3.
  • the gate of the scan transistor T2 is used to receive the scan signal SCAN, its first electrode is electrically connected to a data signal line DATA to receive the data voltage Vdata, and its second electrode is electrically connected or coupled to the second Node Q2.
  • the light emitting device 29 is electrically connected between the third node Q3 and a common voltage terminal EVSS.
  • the driving transistor T1 is a double gate metal oxide field effect transistor.
  • the light emitting device 29 is a light emitting diode.
  • the driving voltage VDD output by the driving voltage terminal EVDD and the common voltage VSS output by the common voltage terminal EVSS are both AC voltage signals that can jump between high and low levels.
  • the reset signal response module 21 is electrically connected to the third node Q3, and is configured to transmit the initialization voltage Vini to the third node Q3 in response to the reset signal RESET.
  • the sensing signal response module 22 is electrically connected to the first node Q1, the second node Q2, and the third node Q3, respectively, for responding to the sensing signal SENSE to transmit the initialization on the third node Q3
  • the voltage Vini is transmitted to the second node Q2, and the reference voltage Vref is transmitted to the first node Q1.
  • the top gate electrode and the second electrode of the driving transistor T1 are reset to the initialization voltage Vini (the driving transistor T1 forms a diode-connect mode), and the bottom gate electrode of the driving transistor T1 is written into the reference Voltage Vref.
  • the voltage value of the reference voltage Vref is greater than the voltage value of the initialization voltage Vini, so that the reference voltage Vref and the initialization voltage Vini can modulate the threshold voltage Vth of the driving transistor T1 to a negative value;
  • the common voltage terminal EVSS outputs a high-level common voltage VSS, and the light emitting diode does not emit light.
  • the reset signal response module 21 no longer transmits the initialization voltage Vini, and the driving voltage terminal EVDD provides the driving voltage VDD to the second electrode of the driving transistor T1, so that its potential rises continuously.
  • the voltage difference Vbs between the bottom gate electrode and the second electrode is continuously reduced.
  • the threshold voltage Vth of the driving transistor T1 gradually changes from negative to zero, and finally the driving transistor T1 is stopped.
  • the Vgs of the driving transistor in the pixel compensation unit corresponding to each pixel is 0 V
  • the corresponding threshold voltage Vth is always zero, which realizes the function of constant equalization of the threshold voltage Vth in the global control panel, and also realizes the improvement of panel brightness.
  • the goal of uniformity is 0 V
  • the scan signal SCAN is a line-by-line scan signal, which is used to turn on the scan transistor T2 of the corresponding pixel compensation unit line by line within one frame time;
  • the sensing signal SENSE is a global signal, which is used to control all the pixel compensation units 20 in one frame.
  • the data voltage Vdata is compensated first through the timing design, and then light is realized; the 21% duty time is dedicated to the writing of the data voltage Vdata, and the light-emitting time of 79% duty is achieved; that is, The light-emitting time of the light-emitting device 29 accounts for basically 79%.
  • the reset signal RESET and the sensing signal SENSE control all the pixel compensation units 20 accordingly, specifically, controlling the corresponding transistors to be turned on or off at the same time; and the scan signal SCAN is turned on and scanned row by row. Pass the corresponding scan transistor T2.
  • the pixel compensation circuit of the present application can realize simultaneous light emission (simultaneous emission), and the number of progressive scan signals is reduced, and each pixel compensation unit contains only one scan signal.
  • the pixel compensation unit 20 further includes a combined signal response module 23 (the dashed frame indicates that it is an optional component).
  • the merging signal response module 23 is configured to respond to a merging signal MERGE to store and transmit the data voltage Vdata.
  • the data voltage Vdata of the previous frame is stored in the combined signal response module 23 during the light-emitting phase of this frame, so that almost 100% duty light is realized in the light-emitting phase of one frame time.
  • the merging signal MERGE is also a global signal, which is used to control all the pixel compensation units 20 in one frame time, specifically, to control the corresponding transistors to be turned on or off at the same time. Off.
  • the pixel compensation circuit of the present application adopts a double-gate structure transistor as the driving transistor, and regulates and modulates the threshold voltage of the driving transistor through the bottom gate electrode, so as to realize compensation for the positive and negative drift of the threshold voltage of the driving transistor, and solve the threshold voltage difference of the driving transistor.
  • Improve the uniformity of panel brightness by introducing synchronous lighting technology, using global signals for corresponding control, the number of progressive scan signals is reduced to only one, the circuit structure is simple, and fewer transistors are required, which is conducive to in-plane integration.
  • FIG. 3A is a circuit diagram of a first embodiment of a pixel compensation circuit for synchronous light emission in this application
  • FIG. 3B is a driving timing diagram of the pixel compensation circuit shown in FIG. 3A.
  • the pixel compensation unit of the pixel compensation circuit adopts a 5T2C structure, and the TFTs in the structure are all N-type thin film transistors (NTFT), and the drain electrode of the NTFT is used as the first electrode of the corresponding transistor. , The source electrode of the NTFT serves as the second electrode of the corresponding transistor.
  • the TFT structure and circuit implementation of this embodiment are universal.
  • the scan signal SCAN is a progressive scan signal, which turns on the gate electrode terminal of the corresponding scan transistor (T2) row by row within one frame time;
  • the reset signal RESET and the sensing signal SENSE are global signals, and
  • the corresponding transistors in all pixel compensation units in the pixel compensation circuit are controlled to be turned on or off at the same time during the frame time.
  • the driving transistor T1 adopts a double-gate metal oxide field effect transistor.
  • the driving transistor T1 has a bottom gate electrode electrically connected to a first node Q1, a top gate electrode electrically connected to a second node Q2, and a first electrode electrically connected to a driving voltage terminal EVDD to receive a driving voltage VDD.
  • the two electrodes are electrically connected to a third node Q3.
  • the gate of the scan transistor T2 is used to receive a scan signal SCAN, its first electrode is electrically connected to a data signal line DATA to receive a data voltage Vdata, and its second electrode is electrically connected to the second node Q2 .
  • the light-emitting device 29 adopts a light-emitting diode D1.
  • the anode of the light emitting diode D1 is electrically connected to the third node Q3, and the cathode of the light emitting diode D1 is electrically connected to a common voltage terminal EVSS.
  • the reset signal response module 21 includes a reset transistor TR; the gate of the reset transistor TR is used to receive a reset signal RESET, its first electrode is used to receive an initialization voltage Vini, and its second electrode is electrically connected to The third node Q3.
  • the reset transistor TR is configured to be turned on in response to the reset signal RESET, and transmit the initialization voltage Vini to the third node Q3.
  • the sensing signal response module 22 includes: a first sensing transistor TS1, a second sensing transistor TS2, a first capacitor C1, and a second capacitor C2.
  • the gate of the first sensing transistor TS1 is used to receive a sensing signal SENSE, the first electrode is used to receive a reference voltage Vref, and the second electrode is electrically connected to the first node Q1;
  • the sensing transistor TS1 is configured to be turned on in response to the sensing signal SENSE, and transmit the reference voltage Vref to the first node Q1.
  • the second sensing transistor TS2 has its gate for receiving the sensing signal SENSE, its first electrode is electrically connected to the third node Q3, and its second electrode is electrically connected to the second node Q2;
  • the second sensing transistor TS2 is configured to be turned on in response to the sensing signal SENSE to transmit the initialization voltage Vini on the third node Q3 to the second node Q2.
  • the first capacitor C1 is electrically connected between the first node Q1 and the third node Q3, and is used for storing between the bottom gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1 The voltage difference Vbs.
  • the second capacitor C2 is electrically connected between the second node Q2 and the third node Q3, and is used for storing between the top gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1 The voltage difference Vgs.
  • one frame time is divided into: a reset phase, a compensation phase, a data writing phase, and a light-emitting phase.
  • the written reference voltage Vref and the initialization voltage Vini can make the threshold voltage Vth of the driving transistor T1 a negative value.
  • the light-emitting phase of one frame time the data voltage Vdata is compensated for writing through the timing design, and then light is realized; the 21% duty time is dedicated to the writing of the data voltage Vdata, and the light-emitting time of 79% duty is achieved.
  • the reset signal RESET and the sensing signal SENSE control the corresponding transistors to be turned on or off at the same time; and the scan signal SCAN scans line by line to turn on the corresponding scan transistor T2.
  • the pixel compensation circuit of the present application can realize synchronous light emission and reduce the number of progressive scan signals. Each pixel compensation unit contains only one scan signal.
  • Reset phase A1 the reset signal RESET is at a high level, the reset transistor TR is turned on, and the third node Q3 writes the initialization voltage Vini signal to refresh the previous frame signal.
  • the sensing signal SENSE is at a high level, the first sensing transistor TS1 is turned on, and the first node Q1 writes the reference voltage Vref signal; the second sensing transistor TS2 is turned on, so that the top gate electrode of the driving transistor T1 and the first node Q1 are turned on.
  • the two electrodes (source electrodes) are connected to form a diode connection, and both the top gate electrode and the source electrode of the driving transistor T1 are written with the initialization voltage Vini signal.
  • the common voltage VSS output from the common voltage terminal EVSS is switched to a high level, and the light emitting diode D1 is reversely turned off and does not emit light. Since the test voltage Vref is greater than the initialization voltage Vini, at this time, the threshold voltage Vth of the driving crystal T1 is a negative value.
  • Compensation stage A2 The reset signal RESET jumps to a low level, and the reset transistor TR is turned off.
  • the driving voltage VDD output by the driving voltage terminal EVDD is at a high level, and the driving voltage VDD charges the source electrode of the driving transistor T1 so that the source electrode potential thereof continuously rises, so that the bottom gate electrode of the driving transistor T1 and its source The voltage difference Vbs between the electrodes continuously decreases.
  • the driving transistor T1 is turned off, the first sensing transistor TS1 and the second sensing transistor TS2 are turned off, the first capacitor C1 records the Vbs voltage at this time, and the second capacitor C2 stores the Vgs voltage.
  • the Vgs of the driving transistor in the pixel compensation unit corresponding to each pixel is 0 V, the corresponding threshold voltage Vth is always zero, realizing the function of global control panel threshold voltage Vth constant equalization, which also realizes the improvement of panel brightness uniformity sexual goals.
  • the light-emitting stage A4 includes a first light-emitting stage A41 and a second light-emitting stage A42: in the first light-emitting stage A41, the driving voltage VDD jumps to low level, the reset signal RESET jumps to high level, and the sensing signal SENSE jumps to low Level, the data voltage Vdata is written to the top gate electrode of the driving transistor T1; the scan signal SCAN scans line by line to turn on the corresponding scan transistor T2.
  • the driving voltage VDD jumps to a high level
  • the common voltage VSS jumps to a low level
  • the reset signal RESET jumps to a low level
  • the driving transistor T1 generates a driving current
  • the light emitting diode D1 emits light.
  • the data voltage Vdata is compensated first through the timing design, and then light is realized; it gives 21%
  • the duty time is dedicated to the writing of the data voltage Vdata (the first light-emitting stage A41), and the light-emitting time of 79% duty (the second light-emitting stage A42) is realized; that is, the light-emitting time ratio of the light-emitting device 29 is basically 79%.
  • FIG. 4A is a circuit diagram of a second embodiment of a pixel compensation circuit for synchronous light emission in this application
  • FIG. 4B is a driving timing diagram of the pixel compensation circuit shown in FIG. 4A.
  • the pixel compensation unit of the pixel compensation circuit adopts a 6T3C structure, and the TFTs in the structure are all N-type thin film transistors (NTFT), and the drain electrode of the NTFT is used as the first electrode of the corresponding transistor. , The source electrode of the NTFT serves as the second electrode of the corresponding transistor.
  • the TFT structure and circuit implementation of this embodiment are universal.
  • the scan signal SCAN is a progressive scan signal, which turns on the gate electrode terminal of the corresponding scan transistor (T2) row by row within one frame time;
  • the reset signal RESET, the sensing signal SENSE, and the combined signal MERGE are all global (Global ) Signal, which controls the corresponding transistors in all pixel compensation units in the pixel compensation circuit to be turned on or off at the same time in one frame time.
  • the driving transistor T1 adopts a double-gate metal oxide field effect transistor.
  • the driving transistor T1 has a bottom gate electrode electrically connected to a first node Q1, a top gate electrode electrically connected to a second node Q2, and a first electrode electrically connected to a driving voltage terminal EVDD to receive a driving voltage VDD.
  • the two electrodes are electrically connected to a third node Q3.
  • the gate of the scan transistor T2 is used to receive a scan signal SCAN, its first electrode is electrically connected to a data signal line DATA to receive a data voltage Vdata, and its second electrode is electrically connected to a fourth node Q4.
  • the light-emitting device 29 adopts a light-emitting diode D1.
  • the anode of the light emitting diode D1 is electrically connected to the third node Q3, and the cathode of the light emitting diode D1 is electrically connected to a common voltage terminal EVSS.
  • the reset signal response module 21 includes a reset transistor TR; the gate of the reset transistor TR is used to receive a reset signal RESET, its first electrode is used to receive an initialization voltage Vini, and its second electrode is electrically connected to The third node Q3.
  • the reset transistor TR is configured to be turned on in response to the reset signal RESET, and transmit the initialization voltage Vini to the third node Q3.
  • the sensing signal response module 22 includes: a first sensing transistor TS1, a second sensing transistor TS2, a first capacitor C1, and a second capacitor C2.
  • the gate of the first sensing transistor TS1 is used to receive a sensing signal SENSE, the first electrode is used to receive a reference voltage Vref, and the second electrode is electrically connected to the first node Q1;
  • the sensing transistor TS1 is configured to be turned on in response to the sensing signal SENSE, and transmit the reference voltage Vref to the first node Q1.
  • the second sensing transistor TS2 has its gate for receiving the sensing signal SENSE, its first electrode is electrically connected to the third node Q3, and its second electrode is electrically connected to the second node Q2;
  • the second sensing transistor TS2 is configured to be turned on in response to the sensing signal SENSE to transmit the initialization voltage Vini on the third node Q3 to the second node Q2.
  • the first capacitor C1 is electrically connected between the first node Q1 and the third node Q3, and is used for storing between the bottom gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1 The voltage difference Vbs.
  • the second capacitor C2 is electrically connected between the second node Q2 and the third node Q3, and is used for storing between the top gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1 The voltage difference Vgs.
  • the combined signal response module 23 includes: a combined transistor TM and a third capacitor C3.
  • the gate of the merging transistor TM is used to receive the merging signal MERGE, and the first electrode of the merging transistor TM is electrically connected to the fourth node Q4 (that is, connected to the scan transistor T2), and is used to receive the transmission of the scan transistor T2.
  • the second electrode of the data voltage Vdata is electrically connected to the second node Q2 (that is, the top gate electrode terminal of the driving transistor T1); the merging transistor TM is used to turn on in response to the merging signal MERGE, To transmit the data voltage Vdata on the fourth node Q4 to the second node Q2.
  • the first plate of the third capacitor C3 is electrically connected to the fourth node Q4 for receiving the data voltage Vdata, and the second plate of the third capacitor C3 is electrically connected to a common ground terminal for storing the data voltage Vdata.
  • one frame time is divided into: a reset phase, a compensation phase, a data writing phase, and a light-emitting phase.
  • the written reference voltage Vref and the initialization voltage Vini can make the threshold voltage Vth of the driving transistor T1 a negative value.
  • the light-emitting phase of one frame time since the data voltage Vdata of the previous frame is stored in the third capacitor C3 of the combined signal response module 23 during the light-emitting phase of this frame, a light-emitting time of almost 100% duty is realized.
  • the reset signal RESET, the sensing signal SENSE, and the combined signal MERGE control the corresponding transistors to be turned on or off at the same time; and the scan signal SCAN scans line by line to turn on the corresponding scan transistor T2.
  • the pixel compensation circuit of the present application can realize synchronous light emission and reduce the number of scanning transistors for line-by-line scanning. Each pixel compensation unit uses only one scanning transistor.
  • Reset phase A1 the reset signal RESET is at a high level, the reset transistor TR is turned on, and the third node Q3 writes the initialization voltage Vini signal to refresh the previous frame signal.
  • the sensing signal SENSE is at a high level, the first sensing transistor TS1 is turned on, and the first node Q1 writes the reference voltage Vref signal; the second sensing transistor TS2 is turned on, so that the top gate electrode of the driving transistor T1 and the first node Q1 are turned on.
  • the two electrodes (source electrodes) are connected to form a diode connection, and both the top gate electrode and the source electrode of the driving transistor T1 are written with the initialization voltage Vini signal.
  • the common voltage VSS output from the common voltage terminal EVSS is switched to a high level, and the light emitting diode D1 is reversely turned off and does not emit light. Since the test voltage Vref is greater than the initialization voltage Vini, at this time, the threshold voltage Vth of the driving crystal T1 is a negative value.
  • the reset signal RESET jumps to a low level, and the reset transistor TR is turned off.
  • the driving voltage VDD output by the driving voltage terminal EVDD is at a high level, and the driving voltage VDD charges the source electrode of the driving transistor T1 so that the source electrode potential thereof continuously rises, so that the bottom gate electrode of the driving transistor T1 and its source
  • the voltage difference Vbs between the electrodes continuously decreases.
  • the driving transistor T1 When the driving transistor T1 is turned off, the first sensing transistor TS1 and the second sensing transistor TS2 are turned off, the first capacitor C1 records the Vbs voltage at this time, and the second capacitor C2 stores the Vgs voltage. Since the Vgs of the driving transistor in the pixel compensation unit corresponding to each pixel is 0 V, the corresponding threshold voltage Vth is always zero, realizing the function of global control panel threshold voltage Vth constant equalization, which also realizes the improvement of panel brightness uniformity Sexual goals.
  • Data writing stage A3 the driving voltage VDD jumps to low level, the reset signal RESET jumps to high level, the sensing signal SENSE jumps to low level; the merge signal MERGE jumps to high level, the merge transistor TM Turning on, the data voltage Vdata of the previous frame stored in the third capacitor C3 is written to the top gate electrode of the driving transistor T1.
  • Light-emitting stage A4 the driving voltage VDD jumps to high level, the common voltage VSS jumps to low level, the reset signal RESET jumps to low level, the merge signal MERGE jumps to low level, the scanning signal SCAN is scanned line by line
  • the corresponding scanning transistor T2 is turned on; the driving transistor T1 generates a driving current, and the light emitting diode D1 emits light. That is, in the light-emitting stage A4 of one frame time, a light-emitting time of 100% duty is realized; that is, the light-emitting time of the light-emitting device 29 accounts for basically 100%.
  • the present application also provides a display panel.
  • FIG. 5 is a schematic diagram of the display panel structure of the present application.
  • the display panel 50 includes an array substrate 51, and the array substrate 51 includes a pixel compensation circuit 511.
  • the pixel compensation circuit 511 adopts the synchronously emitting pixel compensation circuit described in any one of FIG. 2, FIG. 3A, and FIG. 4A in this application.
  • the component connection mode and working principle of the pixel compensation circuit 511 have been described in detail above, and will not be repeated here.
  • the display panel adopting the pixel compensation circuit for synchronous light emission of the present application adjusts and modulates the threshold voltage of the driving transistor adopting the double-gate structure through the bottom gate electrode, realizes the compensation of the positive and negative drift of the threshold voltage of the driving transistor, and solves the difference in the threshold voltage of the driving transistor.
  • Improve the uniformity of panel brightness by introducing synchronous lighting technology, using global signals for corresponding control, the number of progressive scan signals is reduced to only one, the circuit structure is simple, and fewer transistors are required, which is conducive to in-plane integration.

Abstract

一种同步发光的像素补偿电路及显示面板。像素补偿电路包括多个像素补偿单元（20），像素补偿单元（20）包括复位信号响应模块（21）、感测信号响应模块（22）、扫描晶体管（T2）、驱动晶体管（T1）以及发光器件（29）。采用双栅结构晶体管作为驱动晶体管（T1），通过底栅电极（BG）调控调制驱动晶体管（T1）的阈值电压，实现驱动晶体管（T1）的阈值电压正负漂移的补偿；通过引入同步发光技术，采用全局信号进行相应控制，将逐行扫描信号的数量降低为只需要一个，电路结构简单，所需晶体管较少，利于面内集成。

Description

一种同步发光的像素补偿电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种同步发光的像素补偿电路及显示面板。
 背景技术
在采用薄膜晶体管(Thin Film Transistor，简称TFT)的像素补偿电路中，1)工艺发展成熟的非晶硅(A-Si)TFT大面积生产均匀性好，广泛应用于TFT-液晶显示器(Liquid Crystal Display，简称LCD)；2)低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)TFT迁移率高，稳定性较好，适用于中小尺寸面板；3)氧化物(Oxide)TFT迁移率较高，大面积生产均匀性好，制备温度低，透明性好，柔性高，因此可应用于大尺寸高清显示。
 技术问题
但是，非晶硅TFT迁移率低，难以满足更高分辨率需求；低温多晶硅TFT由于晶界的存在，大面积生产均匀性差；氧化物TFT的阈值电压(Vth)漂移量大，造成面板云纹(Mura)缺陷严重。
因此，如何解决由工艺制程引起的驱动(Driving)TFT的阈值电压差异带来的面板亮度不均一的缺陷，实现阈值电压正负漂移的补偿，并降低逐行扫描信号的数量，成为现有像素补偿电路技术发展需要改进的技术问题。
 技术解决方案
本申请实施例提供一种同步发光的像素补偿电路及显示面板，可以解决驱动TFT的阈值电压差异，实现阈值电压正负漂移的补偿，降低逐行扫描信号的数量，并实现同步发光。
本申请实施例提供了一种同步发光的像素补偿电路，所述电路包括多个像素补偿单元，所述像素补偿单元包括：一复位信号响应模块，用于响应一复位信号以传送一初始化电压；一感测信号响应模块，用于响应一感测信号以分别传送所述初始化电压以及一参考电压；一扫描晶体管，用于响应一扫描信号以传送一数据电压；一驱动晶体管，所述驱动晶体管采用双栅金属氧化物场效应晶体管，所述驱动晶体管的底栅电极电连接一第一节点以接收所述参考电压，其顶栅电极电连接一第二节点以接收所述初始化电压或所述数据电压，其第一电极电连接一驱动电压端，其第二电极电连接一第三节点以接收所述初始化电压；所述驱动晶体管用于根据所述初始化电压以及所述参考电压，通过底栅电极调控调制所述驱动晶体管的阈值电压，以及用于根据所述数据电压生成驱动电流；以及一发光器件，用于根据所述驱动电流发光；其中，在所述电路中，所述扫描信号为逐行扫描的信号，用于在一帧时间里逐行导通相应像素补偿单元的扫描晶体管；所述复位信号与所述感测信号为全局信号，用于在一帧时间里对所有所述像素补偿单元进行相应控制。
本申请实施例还提供了一种同步发光的像素补偿电路，所述电路包括多个像素补偿单元，所述像素补偿单元包括：一复位信号响应模块，用于响应一复位信号以传送一初始化电压；一感测信号响应模块，用于响应一感测信号以分别传送所述初始化电压以及一参考电压；一扫描晶体管，用于响应一扫描信号以传送一数据电压；一驱动晶体管，所述驱动晶体管采用双栅结构，所述驱动晶体管用于根据所述初始化电压以及所述参考电压，通过底栅电极调控调制所述驱动晶体管的阈值电压，以及用于根据所述数据电压生成驱动电流；以及一发光器件，用于根据所述驱动电流发光。
本申请实施例还提供了一种显示面板，所述显示面板包括阵列基板；所述阵列基板包括本申请所述的同步发光的像素补偿电路。
 有益效果
本申请像素补偿电路，通过采用双栅结构晶体管作为驱动晶体管，通过底栅电极调控调制所述驱动晶体管的阈值电压，实现驱动晶体管的阈值电压正负漂移的补偿，解决驱动晶体管的阈值电压差异，提升了面板亮度均一性；通过引入同步发光技术，采用全局信号进行相应控制，将逐行扫描信号的数量降低为只需要一个，电路结构简单，所需晶体管较少，利于面内集成。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为双栅场效应晶体管结构及不同宽长比的阈值电压调控示意图；
图2为本申请同步发光的像素补偿电路的结构图；
图3A为本申请同步发光的像素补偿电路第一实施例的电路图；
图3B为图3A所示像素补偿电路的驱动时序图；
图4A为本申请同步发光的像素补偿电路第二实施例的电路图；
图4B为图4A所示像素补偿电路的驱动时序图；
图5为本申请显示面板架构示意图。
 本发明的实施方式
请参阅图1，双栅场效应晶体管结构及不同宽长比的阈值电压调控示意图。
所述双栅场效应晶体管10为双栅金属氧化物场效应晶体管，其包括底栅电极BG、顶栅电极TG、源电极S以及漏电极D。可以通过调控所述双栅金属氧化物场效应晶体管10的底栅电极BG调控其阈值电压Vth。具体的，所述双栅金属氧化物场效应晶体管10可以为氧化铟锡锌薄膜晶体管(ITZO TFT)。
研究发现，不同宽长比的双栅金属氧化物场效应晶体管有着相接近的伽马基准电压值(Gam)，均可实现阈值电压Vth的调控。例如图示中，拟合线11的宽长比W/L为20/8，拟合公式为y=1.29564-0.4376x；拟合线12的宽长比W/L为600/8，拟合公式为y=3.37416-0.4393x；拟合线13的宽长比W/L为2560/8，拟合公式为y=1.3688-0.4419x。由图示可以看出，不同宽长比的双栅金属氧化物场效应晶体管有着相接近的Gam值。由于双栅金属氧化物场效应晶体管可以通过调控底栅电极调控其阈值电压Vth，且不同宽长比的双栅金属氧化物场效应晶体管均可实现阈值电压Vth的调控，这种性能赋予了双栅金属氧化物场效应晶体管灵活实现导通的能力，本申请利用其这一优点开发出新型像素内部补偿电路。
请参阅图2，本申请同步发光的像素补偿电路的结构图。本申请像素补偿电路包括多个像素补偿单元20，所述像素补偿单元20包括：一复位信号响应模块21、一感测信号响应模块22、一扫描晶体管T2、一驱动晶体管T1以及一发光器件29。
所述复位信号响应模块21用于响应一复位信号RESET以传送一初始化电压Vini；所述感测信号响应模块22用于响应一感测信号SENSE以分别传送所述初始化电压Vini以及一参考电压Vref；所述扫描晶体管T2用于响应一扫描信号SCAN以传送一数据电压Vdata；所述驱动晶体管T1采用双栅结构(Double-Gate)，用于根据所述初始化电压Vini以及所述参考电压Vref，通过底栅电极调控调制所述驱动晶体管T1的阈值电压Vth，以及用于根据所述数据电压Vdata生成驱动电流；以及所述发光器件29用于根据所述驱动电流发光。
具体的，双栅结构的所述驱动晶体管T1，其底栅电极(BG)电连接一第一节点Q1，其顶栅电极(TG)电连接一第二节点Q2，其第一电极电连接一驱动电压端EVDD以接收一驱动电压VDD，其第二电极电连接一第三节点Q3。所述扫描晶体管T2的栅极用于接收所述扫描信号SCAN，其第一电极电连接一数据信号线DATA以接收所述数据电压Vdata，其第二电极电连接或耦接至所述第二节点Q2。所述发光器件29电连接在所述第三节点Q3与一公共电压端EVSS之间。优选的，所述驱动晶体管T1采用双栅金属氧化物场效应晶体管。所述发光器件29采用发光二极管。其中，所述驱动电压端EVDD输出的驱动电压VDD以及所述公共电压端EVSS输出的公共电压VSS均为可在高低电平间跳变的交流电压信号。
具体的，所述复位信号响应模块21电连接所述第三节点Q3，用于响应所述复位信号RESET，传送所述初始化电压Vini至所述第三节点Q3。所述感测信号响应模块22分别电连接所述第一节点Q1、第二节点Q2以及第三节点Q3，用于响应所述感测信号SENSE以传送所述第三节点Q3上的所述初始化电压Vini至所述第二节点Q2，以及传送所述参考电压Vref至所述第一节点Q1。
在复位阶段，所述驱动晶体管T1的顶栅电极与第二电极复位为所述初始化电压Vini(所述驱动晶体管T1形成二极管连接(diode-connect)方式)，其底栅电极写入所述参考电压Vref。其中，所述参考电压Vref的电压值大于所述所述初始化电压Vini的电压值，从而所述参考电压Vref与所述初始化电压Vini能够使所述驱动晶体管T1的阈值电压Vth调制为负值；公共电压端EVSS输出高电平的公共电压VSS，发光二极管不发光。
在补偿阶段，所述复位信号响应模块21不再传送所述初始化电压Vini，而所述驱动电压端EVDD给所述驱动晶体管T1的第二电极提供所述驱动电压VDD，使其电位不断上升，使得底栅电极与第二电极之间的电压差Vbs不断降低。根据底栅电极调控阈值电压Vth原理，可知所述驱动晶体管T1的阈值电压Vth逐渐由负值变为零，最终使所述驱动晶体管T1载止，此时阈值电压Vth和顶栅电极与第二电极之间的电压差Vgs相等，即Vth=Vgs。由于各个像素对应的像素补偿单元中的驱动晶体管的Vgs均为0 V，则相应的各个阈值电压Vth恒为零，实现全局调控面板中阈值电压Vth恒相等的功能，也就实现了提升面板亮度均一性的目标。
进一步的实施例中，在所述电路中，所述扫描信号SCAN为逐行扫描的信号，用于在一帧时间里逐行导通相应像素补偿单元的扫描晶体管T2；所述复位信号RESET与所述感测信号SENSE为全局(Global)信号，用于在一帧时间里对所有所述像素补偿单元20进行相应控制。
在一帧时间的发光阶段内，通过时序设计上先进行补偿写入数据电压Vdata，再实现发光；给出21% duty时间专用于数据电压Vdata的写入，实现79%duty的发光时间；即所述发光器件29的发光时间占比基本为79%。在一帧时间里，所述复位信号RESET与所述感测信号SENSE对所有像素补偿单元20进行相应控制，具体为，控制相应的晶体管同时导通或关断；而扫描信号SCAN逐行扫描导通相应的扫描晶体管T2。本申请像素补偿电路可以实现同步发光(simultaneous emission)，且减少了逐行扫描信号的数量，每一像素补偿单元中只包含一个扫描信号。
进一步的实施例中，所述像素补偿单元20还包括一合并信号响应模块23(虚框示意其为可选组件)。所述合并信号响应模块23用于响应一合并信号MERGE以存储并传送所述数据电压Vdata。具体的，前一帧的数据电压Vdata在本帧的发光阶段存储在所述合并信号响应模块23中，使得在一帧时间的发光阶段内几乎实现了100%duty发光。具体的，在所述电路中，所述合并信号MERGE也为全局信号，用于在一帧时间里对所有所述像素补偿单元20进行相应控制，具体为，控制相应的晶体管同时导通或关断。
本申请像素补偿电路，通过采用双栅结构晶体管作为驱动晶体管，通过底栅电极调控调制所述驱动晶体管的阈值电压，实现驱动晶体管的阈值电压正负漂移的补偿，解决驱动晶体管的阈值电压差异，提升了面板亮度均一性；通过引入同步发光技术，采用全局信号进行相应控制，将逐行扫描信号的数量降低为只需要一个，电路结构简单，所需晶体管较少，利于面内集成。
请一并参阅图2，图3A-图3B，其中，图3A为本申请同步发光的像素补偿电路第一实施例的电路图，图3B为图3A所示像素补偿电路的驱动时序图。
如图3A所示，在本实施例中，所述像素补偿电路的像素补偿单元采用5T2C结构，结构中的TFT均为N型薄膜晶体管(NTFT)，NTFT的漏电极作为相应晶体管的第一电极，NTFT的源电极作为相应晶体管的第二电极。本实施例TFT结构、电路实现方式具有普适性。其中，扫描信号SCAN为逐行扫描的信号，在一帧时间里逐行导通相应的扫描晶体管(T2)的栅电极端；复位信号RESET与感测信号SENSE为全局(Global)信号，在一帧时间里控制像素补偿电路中所有像素补偿单元中的相应的晶体管同时导通或关断。
具体的，所述驱动晶体管T1采用双栅金属氧化物场效应晶体管。所述驱动晶体管T1，其底栅电极电连接一第一节点Q1，其顶栅电极电连接一第二节点Q2，其第一电极电连接一驱动电压端EVDD以接收一驱动电压VDD，其第二电极电连接一第三节点Q3。
具体的，所述扫描晶体管T2的栅极用于接收一扫描信号SCAN，其第一电极电连接一数据信号线DATA以接收一数据电压Vdata，其第二电极电连接至所述第二节点Q2。
具体的，所述发光器件29采用发光二极管D1。所述发光二极管D1的阳极电连接所述第三节点Q3，其阴极电连接一公共电压端EVSS。
具体的，所述复位信号响应模块21包括一复位晶体管TR；所述复位晶体管TR的栅极用于接收一复位信号RESET，其第一电极用于接收一初始化电压Vini，其第二电极电连接所述第三节点Q3。所述复位晶体管TR用于响应所述复位信号RESET以导通，传送所述初始化电压Vini至所述第三节点Q3。
具体的，所述感测信号响应模块22包括：一第一感测晶体管TS1、一第二感测晶体管TS2、一第一电容器C1以及一第二电容器C2。所述第一感测晶体管TS1，其栅极用于接收一感测信号SENSE，其第一电极用于接收一参考电压Vref，其第二电极电连接所述第一节点Q1；所述第一感测晶体管TS1用于响应所述感测信号SENSE以导通，传送所述参考电压Vref至所述第一节点Q1。所述第二感测晶体管TS2，其栅极用于接收所述感测信号SENSE，其第一电极电连接所述第三节点Q3，其第二电极电连接所述第二节点Q2；所述第二感测晶体管TS2用于响应所述感测信号SENSE以导通，以传送所述第三节点Q3上的所述初始化电压Vini至所述第二节点Q2。所述第一电容器C1，电连接在所述第一节点Q1与所述第三节点Q3之间，用于存储所述驱动晶体管T1的底栅电极与所述驱动晶体管T1的第二电极之间的电压差Vbs。所述第二电容器C2，电连接在所述第二节点Q2与所述第三节点Q3之间，用于存储所述驱动晶体管T1的顶栅电极与所述驱动晶体管T1的第二电极之间的电压差Vgs。
如图3B所示，将一帧时间分成：复位阶段、补偿阶段、数据写入阶段与发光阶段。在复位阶段，写入的参考电压Vref与初始化电压Vini能够使所述驱动晶体管T1的阈值电压Vth为负值。在一帧时间的发光阶段内，通过时序设计上先进行补偿写入数据电压Vdata，再实现发光；给出21% duty时间专用于数据电压Vdata的写入，实现79%duty的发光时间。在一帧时间里，所述复位信号RESET与所述感测信号SENSE控制相应的晶体管同时导通或关断；而扫描信号SCAN逐行扫描导通相应的扫描晶体管T2。本申请像素补偿电路可以实现同步发光，且减少了逐行扫描信号的数量，每一像素补偿单元中只包含一个扫描信号。
以下结合图3A-图3B，对本申请同步发光的像素补偿电路的工作原理作进一步解释说明。具体工作原理如下：
复位阶段A1：复位信号RESET为高电平，复位晶体管TR导通，第三节点Q3写入初始化电压Vini信号，刷新上一帧信号。感测信号SENSE为高电平，第一感测晶体管TS1导通，第一节点Q1写入参考电压Vref信号；第二感测晶体管TS2导通，使得所述驱动晶体管T1的顶栅电极与第二电极(源电极)相连，形成二极管连接，所述驱动晶体管T1的顶栅电极与源电极均写入所述初始化电压Vini信号。公共电压端EVSS输出的公共电压VSS切换为高电平，发光二极管D1反向截止而不发光。由于所述考电压Vref大于所述初始化电压Vini，故此时，所述驱动晶体T1的阈值电压Vth为负值。
补偿阶段A2：复位信号RESET跳变为低电平，复位晶体管TR关断。驱动电压端EVDD输出的驱动电压VDD为高电平，所述驱动电压VDD向所述驱动晶体管T1的源电极充电，使得其源电极电位不断上升，使得所述驱动晶体管T1的底栅电极与其源电极之间的电压差Vbs不断降低。
数据写入阶段A3：各信号的时序不变。根据底栅电极调控阈值电压Vth原理，可知所述驱动晶体T1的阈值电压Vth逐渐由负值逐渐变为零，最终使所述驱动晶体管T1载止，此时Vth=Vgs。所述驱动晶体管T1截止时，第一感测晶体管TS1与第二感测晶体管TS2关断，第一电容器C1记录此时的Vbs电压，第二电容器C2存储Vgs电压。由于各个像素对应的像素补偿单元中的驱动晶体管的Vgs均为0 V，则相应的各个阈值电压Vth恒为零，实现全局调控面板阈值电压Vth恒相等的功能，也就实现了提升面板亮度均一性的目标。
发光阶段A4包括第一发光阶段A41与第二发光阶段A42：第一发光阶段A41，驱动电压VDD跳变为低电平，复位信号RESET跳变为高电平，感测信号SENSE跳变为低电平，数据电压Vdata写入到所述驱动晶体管T1的顶栅电极；扫描信号SCAN逐行扫描导通相应的扫描晶体管T2。第二发光阶段A42，驱动电压VDD跳变为高电平，公共电压VSS跳变为低电平，复位信号RESET跳变为低电平，所述驱动晶体管T1生成驱动电流，发光二极管D1发光。即，在一帧时间的发光阶段A4内，通过时序设计上先进行补偿写入数据电压Vdata，再实现发光；给出21% duty时间专用于数据电压Vdata的写入(第一发光阶段A41)，实现79%duty的发光时间(第二发光阶段A42)；即所述发光器件29的发光时间占比基本为79%。
请一并参阅图2，图4A-图4B，其中，图4A为本申请同步发光的像素补偿电路第二实施例的电路图，图4B为图4A所示像素补偿电路的驱动时序图。
如图4A所示，在本实施例中，所述像素补偿电路的像素补偿单元采用6T3C结构，结构中的TFT均为N型薄膜晶体管(NTFT)，NTFT的漏电极作为相应晶体管的第一电极，NTFT的源电极作为相应晶体管的第二电极。本实施例TFT结构、电路实现方式具有普适性。其中，扫描信号SCAN为逐行扫描的信号，在一帧时间里逐行导通相应的扫描晶体管(T2)的栅电极端；复位信号RESET、感测信号SENSE、合并信号MERGE均为全局(Global)信号，在一帧时间里控制像素补偿电路中所有像素补偿单元中的相应的晶体管同时导通或关断。
具体的，所述驱动晶体管T1采用双栅金属氧化物场效应晶体管。所述驱动晶体管T1，其底栅电极电连接一第一节点Q1，其顶栅电极电连接一第二节点Q2，其第一电极电连接一驱动电压端EVDD以接收一驱动电压VDD，其第二电极电连接一第三节点Q3。
具体的，所述扫描晶体管T2的栅极用于接收一扫描信号SCAN，其第一电极电连接一数据信号线DATA以接收一数据电压Vdata，其第二电极电连接至一第四节点Q4。
具体的，所述发光器件29采用发光二极管D1。所述发光二极管D1的阳极电连接所述第三节点Q3，其阴极电连接一公共电压端EVSS。
具体的，所述复位信号响应模块21包括一复位晶体管TR；所述复位晶体管TR的栅极用于接收一复位信号RESET，其第一电极用于接收一初始化电压Vini，其第二电极电连接所述第三节点Q3。所述复位晶体管TR用于响应所述复位信号RESET以导通，传送所述初始化电压Vini至所述第三节点Q3。
具体的，所述感测信号响应模块22包括：一第一感测晶体管TS1、一第二感测晶体管TS2、一第一电容器C1以及一第二电容器C2。所述第一感测晶体管TS1，其栅极用于接收一感测信号SENSE，其第一电极用于接收一参考电压Vref，其第二电极电连接所述第一节点Q1；所述第一感测晶体管TS1用于响应所述感测信号SENSE以导通，传送所述参考电压Vref至所述第一节点Q1。所述第二感测晶体管TS2，其栅极用于接收所述感测信号SENSE，其第一电极电连接所述第三节点Q3，其第二电极电连接所述第二节点Q2；所述第二感测晶体管TS2用于响应所述感测信号SENSE以导通，以传送所述第三节点Q3上的所述初始化电压Vini至所述第二节点Q2。所述第一电容器C1，电连接在所述第一节点Q1与所述第三节点Q3之间，用于存储所述驱动晶体管T1的底栅电极与所述驱动晶体管T1的第二电极之间的电压差Vbs。所述第二电容器C2，电连接在所述第二节点Q2与所述第三节点Q3之间，用于存储所述驱动晶体管T1的顶栅电极与所述驱动晶体管T1的第二电极之间的电压差Vgs。
具体的，所述合并信号响应模块23包括：一合并晶体管TM以及一第三电容器C3。所述合并晶体管TM，其栅极用于接收所述合并信号MERGE，其第一电极电连接所述第四节点Q4(即接入所述扫描晶体管T2)，用于接收所述扫描晶体管T2传送的所述数据电压Vdata，其第二电极电连接所述第二节点Q2(即所述驱动晶体管T1的顶栅电极端)；所述合并晶体管TM用于响应所述合并信号MERGE以导通，以传送所述第四节点Q4上的所述数据电压Vdata至所述第二节点Q2。所述第三电容器C3，其第一极板电连接所述第四节点Q4用于接收所述数据电压Vdata，其第二极板电连接公共地端，用于存储所述数据电压Vdata。
如图4B所示，将一帧时间分成：复位阶段、补偿阶段、数据写入阶段与发光阶段。在复位阶段，写入的参考电压Vref与初始化电压Vini能够使所述驱动晶体管T1的阈值电压Vth为负值。在一帧时间的发光阶段内，由于前一帧的数据电压Vdata在本帧的发光阶段存储在所述合并信号响应模块23的第三电容器C3中，实现几乎100%duty的发光时间。在一帧时间里，所述复位信号RESET、所述感测信号SENSE、所述合并信号MERGE控制相应的晶体管同时导通或关断；而扫描信号SCAN逐行扫描导通相应的扫描晶体管T2。本申请像素补偿电路可以实现同步发光，且减少了逐行扫描的扫描晶体管的数量，每一像素补偿单元只采用一个扫描晶体管。
以下结合图4A-图4B，对本申请同步发光的像素补偿电路的工作原理作进一步解释说明。具体工作原理如下：
复位阶段A1：复位信号RESET为高电平，复位晶体管TR导通，第三节点Q3写入初始化电压Vini信号，刷新上一帧信号。感测信号SENSE为高电平，第一感测晶体管TS1导通，第一节点Q1写入参考电压Vref信号；第二感测晶体管TS2导通，使得所述驱动晶体管T1的顶栅电极与第二电极(源电极)相连，形成二极管连接，所述驱动晶体管T1的顶栅电极与源电极均写入所述初始化电压Vini信号。公共电压端EVSS输出的公共电压VSS切换为高电平，发光二极管D1反向截止而不发光。由于所述考电压Vref大于所述初始化电压Vini，故此时，所述驱动晶体T1的阈值电压Vth为负值。
补偿阶段A2：复位信号RESET跳变为低电平，复位晶体管TR关断。驱动电压端EVDD输出的驱动电压VDD为高电平，所述驱动电压VDD向所述驱动晶体管T1的源电极充电，使得其源电极电位不断上升，使得所述驱动晶体管T1的底栅电极与其源电极之间的电压差Vbs不断降低。根据底栅电极调控阈值电压Vth原理，可知所述驱动晶体T1的阈值电压Vth逐渐由负值逐渐变为零，最终使所述驱动晶体管T1载止，此时Vth=Vgs。所述驱动晶体管T1截止时，第一感测晶体管TS1与第二感测晶体管TS2关断，第一电容器C1记录此时的Vbs电压，第二电容器C2存储Vgs电压。由于各个像素对应的像素补偿单元中的驱动晶体管的Vgs均为0 V，则相应的各个阈值电压Vth恒为零，实现全局调控面板阈值电压Vth恒相等的功能，也就实现了提升面板亮度均一性的目标。
数据写入阶段A3：驱动电压VDD跳变为低电平，复位信号RESET跳变为高电平，感测信号SENSE跳变为低电平；合并信号MERGE跳变为高电平，合并晶体管TM导通，第三电容器C3存储的前一帧的数据电压Vdata写入到所述驱动晶体管T1的顶栅电极。
发光阶段A4：驱动电压VDD跳变为高电平，公共电压VSS跳变为低电平，复位信号RESET跳变为低电平，合并信号MERGE跳变为低电平，扫描信号SCAN逐行扫描导通相应的扫描晶体管T2；所述驱动晶体管T1生成驱动电流，发光二极管D1发光。即，在一帧时间的发光阶段A4内，实现100%duty的发光时间；即所述发光器件29的发光时间占比基本为100%。
基于同一发明构思，本申请还提供了一种显示面板。
请参阅图5，本申请显示面板架构示意图。所述显示面板50包括阵列基板51，所述阵列基板51包括像素补偿电路511。所述像素补偿电路511采用本申请图2、图3A、图4A任一所述的同步发光的像素补偿电路。所述像素补偿电路511的组件连接方式及工作原理已详述于前，此处不再赘述。
采用本申请同步发光的像素补偿电路的显示面板，通过底栅电极调控调制采用双栅结构的驱动晶体管的阈值电压，实现驱动晶体管的阈值电压正负漂移的补偿，解决驱动晶体管的阈值电压差异，提升了面板亮度均一性；通过引入同步发光技术，采用全局信号进行相应控制，将逐行扫描信号的数量降低为只需要一个，电路结构简单，所需晶体管较少，利于面内集成。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种同步发光的像素补偿电路，其中，所述电路包括多个像素补偿单元，所述像素补偿单元包括：
    一复位信号响应模块，用于响应一复位信号以传送一初始化电压；
    一感测信号响应模块，用于响应一感测信号以分别传送所述初始化电压以及一参考电压；
    一扫描晶体管，用于响应一扫描信号以传送一数据电压；
    一驱动晶体管，所述驱动晶体管采用双栅金属氧化物场效应晶体管，所述驱动晶体管的底栅电极电连接一第一节点以接收所述参考电压，其顶栅电极电连接一第二节点以接收所述初始化电压或所述数据电压，其第一电极电连接一驱动电压端，其第二电极电连接一第三节点以接收所述初始化电压；所述驱动晶体管用于根据所述初始化电压以及所述参考电压，通过底栅电极调控调制所述驱动晶体管的阈值电压，以及用于根据所述数据电压生成驱动电流；以及
    一发光器件，用于根据所述驱动电流发光；
    并且其中，在所述电路中，所述扫描信号为逐行扫描的信号，用于在一帧时间里逐行导通相应像素补偿单元的扫描晶体管；所述复位信号与所述感测信号为全局信号，用于在一帧时间里对所有所述像素补偿单元进行相应控制。
  2. 如权利要求1所述的同步发光的像素补偿电路，其中，在一帧时间的发光阶段内，所述发光器件的发光时间占比基本为79%。
  3. 如权利要求1所述的同步发光的像素补偿电路，其中，
    所述扫描晶体管的栅极用于接收所述扫描信号，其第一电极用于接收所述数据电压，其第二电极电连接或耦接至所述第二节点；
    所述发光器件电连接在所述第三节点与一公共电压端之间。
  4. 如权利要求1所述的同步发光的像素补偿电路，其中，所述复位信号响应模块包括一复位晶体管；所述复位晶体管的栅极用于接收所述复位信号，其第一电极用于接收所述初始化电压，其第二电极电连接所述第三节点。
  5. 如权利要求1所述的同步发光的像素补偿电路，其中，所述感测信号响应模块包括：
    一第一感测晶体管，其栅极用于接收所述感测信号，其第一电极用于接收所述参考电压，其第二电极电连接所述第一节点；
    一第二感测晶体管，其栅极用于接收所述感测信号，其第一电极电连接所述第三节点，其第二电极电连接所述第二节点；
    一第一电容器，电连接在所述第一节点与所述第三节点之间，用于存储所述驱动晶体管的底栅电极与所述驱动晶体管的第二电极之间的电压差；以及
    一第二电容器，电连接在所述第二节点与所述第三节点之间，用于存储所述驱动晶体管的顶栅电极与所述驱动晶体管的第二电极之间的电压差。
  6. 如权利要求1所述的同步发光的像素补偿电路，其中，所述像素补偿单元还包括一合并信号响应模块，所述合并信号响应模块用于响应一合并信号以存储并传送所述数据电压。
  7. 如权利要求6所述的同步发光的像素补偿电路，其中，在所述电路中，所述合并信号为全局信号，用于在一帧时间里对所有所述像素补偿单元进行相应控制；在一帧时间的发光阶段内，所述发光器件的发光时间占比基本为100%。
  8. 如权利要求6所述的同步发光的像素补偿电路，其中，所述合并信号响应模块包括：
    一合并晶体管，其栅极用于接收所述合并信号，其第一电极接入所述扫描晶体管用于接收所述数据电压，其第二电极电连接所述驱动晶体管的顶栅电极端；以及
    一第三电容器，其第一极板用于接收所述数据电压，其第二极板电连接公共地端，用于存储所述数据电压。
  9. 一种同步发光的像素补偿电路，其中，所述电路包括多个像素补偿单元，所述像素补偿单元包括：
    一复位信号响应模块，用于响应一复位信号以传送一初始化电压；
    一感测信号响应模块，用于响应一感测信号以分别传送所述初始化电压以及一参考电压；
    一扫描晶体管，用于响应一扫描信号以传送一数据电压；
    一驱动晶体管，所述驱动晶体管采用双栅结构，所述驱动晶体管用于根据所述初始化电压以及所述参考电压，通过底栅电极调控调制所述驱动晶体管的阈值电压，以及用于根据所述数据电压生成驱动电流；以及
    一发光器件，用于根据所述驱动电流发光。
  10. 如权利要求9所述的同步发光的像素补偿电路，其中，在所述电路中，所述扫描信号为逐行扫描的信号，用于在一帧时间里逐行导通相应像素补偿单元的扫描晶体管；所述复位信号与所述感测信号为全局信号，用于在一帧时间里对所有所述像素补偿单元进行相应控制。
  11. 如权利要求10所述的同步发光的像素补偿电路，其中，在一帧时间的发光阶段内，所述发光器件的发光时间占比基本为79%。
  12. 如权利要求9所述的同步发光的像素补偿电路，其中，所述驱动晶体管为双栅金属氧化物场效应晶体管。
  13. 如权利要求9所述的同步发光的像素补偿电路，其中，
    所述驱动晶体管的底栅电极电连接一第一节点以接收所述参考电压，其顶栅电极电连接一第二节点以接收所述初始化电压或所述数据电压，其第一电极电连接一驱动电压端，其第二电极电连接一第三节点以接收所述初始化电压；
    所述扫描晶体管的栅极用于接收所述扫描信号，其第一电极用于接收所述数据电压，其第二电极电连接或耦接至所述第二节点；
    所述发光器件电连接在所述第三节点与一公共电压端之间。
  14. 如权利要求13所述的同步发光的像素补偿电路，其中，所述复位信号响应模块包括一复位晶体管；所述复位晶体管的栅极用于接收所述复位信号，其第一电极用于接收所述初始化电压，其第二电极电连接所述第三节点。
  15. 如权利要求13所述的同步发光的像素补偿电路，其中，所述感测信号响应模块包括：
    一第一感测晶体管，其栅极用于接收所述感测信号，其第一电极用于接收所述参考电压，其第二电极电连接所述第一节点；
    一第二感测晶体管，其栅极用于接收所述感测信号，其第一电极电连接所述第三节点，其第二电极电连接所述第二节点；
    一第一电容器，电连接在所述第一节点与所述第三节点之间，用于存储所述驱动晶体管的底栅电极与所述驱动晶体管的第二电极之间的电压差；以及
    一第二电容器，电连接在所述第二节点与所述第三节点之间，用于存储所述驱动晶体管的顶栅电极与所述驱动晶体管的第二电极之间的电压差。
  16. 如权利要求9所述的同步发光的像素补偿电路，其中，所述像素补偿单元还包括一合并信号响应模块，所述合并信号响应模块用于响应一合并信号以存储并传送所述数据电压。
  17. 如权利要求16所述的同步发光的像素补偿电路，其中，在所述电路中，所述扫描信号为逐行扫描的信号，用于在一帧时间里逐行导通相应像素补偿单元的扫描晶体管；所述复位信号、所述感测信号、所述合并信号为全局信号，用于在一帧时间里对所有所述像素补偿单元进行相应控制。
  18. 如权利要求17所述的同步发光的像素补偿电路，其中，在一帧时间的发光阶段内，所述发光器件的发光时间占比基本为100%。
  19. 如权利要求16所述的同步发光的像素补偿电路，其中，所述合并信号响应模块包括：
    一合并晶体管，其栅极用于接收所述合并信号，其第一电极接入所述扫描晶体管用于接收所述数据电压，其第二电极电连接所述驱动晶体管的顶栅电极端；以及
    一第三电容器，其第一极板用于接收所述数据电压，其第二极板电连接公共地端，用于存储所述数据电压。
  20. 一种显示面板，所述显示面板包括阵列基板；其中，所述阵列基板包含同步发光的像素补偿电路，所述同步发光的像素补偿电路包括多个像素补偿单元，所述像素补偿单元包括：
    一复位信号响应模块，用于响应一复位信号以传送一初始化电压；
    一感测信号响应模块，用于响应一感测信号以分别传送所述初始化电压以及一参考电压；
    一扫描晶体管，用于响应一扫描信号以传送一数据电压；
    一驱动晶体管，所述驱动晶体管采用双栅结构，所述驱动晶体管用于根据所述初始化电压以及所述参考电压，通过底栅电极调控调制所述驱动晶体管的阈值电压，以及用于根据所述数据电压生成驱动电流；以及
    一发光器件，用于根据所述驱动电流发光。
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