WO2022001486A1 - 半导体结构的处理方法及形成方法 - Google Patents

半导体结构的处理方法及形成方法 Download PDF

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Publication number
WO2022001486A1
WO2022001486A1 PCT/CN2021/095582 CN2021095582W WO2022001486A1 WO 2022001486 A1 WO2022001486 A1 WO 2022001486A1 CN 2021095582 W CN2021095582 W CN 2021095582W WO 2022001486 A1 WO2022001486 A1 WO 2022001486A1
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Prior art keywords
semiconductor structure
mask layer
processing
semiconductor substrate
semiconductor
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PCT/CN2021/095582
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English (en)
French (fr)
Inventor
郗宁
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长鑫存储技术有限公司
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Priority to US17/438,454 priority Critical patent/US11978636B2/en
Publication of WO2022001486A1 publication Critical patent/WO2022001486A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

  • the present application relates to the field of semiconductors, and relates to a method for processing and forming a semiconductor structure.
  • HAR High Aspect Ratio
  • Embodiments of the present application provide a method for processing and forming a semiconductor structure, which effectively improves the problem of tilting of a structure with a high aspect ratio, and has a simple process and low cost.
  • embodiments of the present application provide a method for processing a semiconductor structure, including: providing a semiconductor substrate, a feature portion is provided on the semiconductor substrate, the aspect ratio of the feature portion is greater than a preset aspect ratio, and the top portion of the feature portion is located.
  • a mask layer is provided; ashing treatment is performed on the semiconductor structure, the semiconductor structure includes a semiconductor substrate, a feature part and a mask layer; cleaning treatment is performed on the semiconductor structure; drying treatment is performed on the semiconductor structure;
  • at least one mask layer in the adjacent group of mask layers is inclined toward the direction of the adjacent mask layer, and after the drying process, the gap between the inclined mask layer and the adjacent mask layer is The distance is smaller than the distance between the two before the drying process.
  • the feature part is a high aspect ratio structure, and the feature part is inclined, that is, the high aspect ratio structure is inclined, and the feature part is in a vertical state to avoid the high aspect ratio structure inclination.
  • the mask layer on the top of the feature is removed, and the feature is tilted by capillary force.
  • this solution does not remove the mask layer on the top of the feature portion during the ashing and cleaning process.
  • the mask layer is tilted by capillary force, and then after the mask layer is removed, the feature portion is removed. Restoring the initial state effectively improves the problem of inclination of the high aspect ratio structure when cleaning the high aspect ratio structure, and the process flow is simple and the cost is low.
  • performing ashing processing on the semiconductor structure includes: performing ashing processing on the semiconductor structure by using a first mixed gas that does not contain oxygen.
  • the first mixed gas includes at least hydrogen and nitrogen. The ashing treatment is performed by using the first mixed gas without oxygen to prevent the surface of the semiconductor structure from being oxidized during the ashing treatment.
  • performing ashing processing on the semiconductor structure includes: performing ashing processing on the surface of the feature portion by using a second mixed gas containing oxygen.
  • the second mixed gas includes at least hydrogen, nitrogen and oxygen. The second mixed gas containing oxygen is used for ashing treatment to speed up the time of the ashing treatment process, thereby improving the process efficiency of the semiconductor process.
  • performing a cleaning process on the semiconductor structure includes: performing a first cleaning process on the semiconductor structure, and after the first cleaning process, an oxide layer is formed on the surface of the semiconductor structure; performing a second cleaning process on the semiconductor structure, and the second cleaning process is used for Remove the oxide layer.
  • the first cleaning treatment using NH 4 OH, H 2 O 2 and H 2 O mixed liquid, and NH 4 OH, H 2 O 2 and H 2 O ratio (volume ratio) of NH 4 OH: H 2 O 2 : H 2 O 1:1 to 4:20 to 100.
  • a second cleaning process using a mixed liquid of 30% to 70% concentration of HF and H 2 O, and 30% to 70% concentration of HF and H 2 O volume ratio in the range of 30% to 70% concentration of HF: H2O 100 ⁇ 300:1.
  • drying the semiconductor structure includes: using isopropyl alcohol at a first temperature to dry the surface of the feature; while drying the surface of the feature, using deionized water at a second temperature to dry the bottom of the semiconductor substrate .
  • the process is to provide hot deionized water to the back of the wafer during the drying process, and to provide heated isopropanol to the front of the wafer at the same time.
  • the reason is that if Without heating the backside of the wafer, the temperature of isopropanol reaching the surface of the wafer will be lower, and the hot deionized water provided on the backside is used to control the temperature of the wafer to prevent the temperature difference between the center and edge of the wafer. This can further enhance the drying effect of isopropyl alcohol for better drying of the wafer.
  • the temperature range of the first temperature is 60°C to 80°C
  • the temperature range of the second temperature is 60°C to 80°C.
  • removing the mask layer includes: supplying a chemical gas to the mask layer, and chemically reacting with the mask layer at a third temperature; after performing the chemical reaction, thermally treating the mask layer at a fourth temperature and simultaneously adding a chemical gas to the mask layer.
  • the mask layer provides a carrier gas for evaporative removal of the mask layer.
  • the temperature range of the third temperature is 30°C to 150°C; the temperature range of the fourth temperature is 100°C to 200°C.
  • the etching selectivity ratio of the chemical gas to the mask layer and the features is greater than 500:1.
  • the chemical gas includes at least ammonia and hydrogen fluoride
  • the carrier includes at least nitrogen or argon.
  • the default aspect ratio is 10.
  • Embodiments of the present application further provide a method for forming a semiconductor structure, including: providing a semiconductor substrate and a mask layer on the semiconductor substrate; using the mask layer as a mask, etching the semiconductor substrate to form discrete features, The aspect ratio is greater than the preset aspect ratio; ashing, cleaning and drying are performed on the semiconductor structure in sequence, and the semiconductor structure includes a semiconductor substrate, a feature part and a mask layer; the mask layer is removed.
  • the method can form a high aspect ratio structure without collapse, effectively improves the problem of inclination of the high aspect ratio structure, and has simple process and low cost.
  • 1 to 6 are schematic cross-sectional structural diagrams corresponding to each step of a method for processing a semiconductor structure according to an embodiment of the present application;
  • FIG. 7 is a schematic diagram of a feature tilt in a method for processing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 and FIG. 9 are schematic flowcharts of chemical etching processing according to an embodiment of the present application.
  • High aspect ratio structures may be features with aspect ratios greater than 5:1, 10:1, or 20:1.
  • the capillary force will cause the HAR structure to tilt or even collapse. The higher it is, the more serious the tilt is.
  • an embodiment of the present application provides a method for processing a semiconductor structure, including: providing a semiconductor substrate, a feature portion is provided on the semiconductor substrate, the aspect ratio of the feature portion is greater than a preset aspect ratio, and the top portion of the feature portion is located.
  • a mask layer is provided; ashing treatment is performed on the semiconductor structure, the semiconductor structure includes a semiconductor substrate, a feature part and a mask layer; cleaning treatment is performed on the semiconductor structure; drying treatment is performed on the semiconductor structure;
  • at least one mask layer in the adjacent group of mask layers is inclined toward the direction of the adjacent mask layer, and after the drying process, the gap between the inclined mask layer and the adjacent mask layer is The distance is smaller than the distance between the two before the drying process.
  • FIG. 1 to 6 are schematic cross-sectional structural diagrams corresponding to each step of the processing method of the semiconductor structure provided by the embodiment of the present application, and the processing method of the semiconductor structure of the present embodiment will be described in detail below.
  • a semiconductor substrate 111 is provided on which features 112 are disposed, the top surfaces of the features 112 have a mask layer 200, and the aspect ratios of the features are greater than a predetermined aspect ratio.
  • a mask layer 200 is formed on a substrate 101 , and the substrate 101 is etched based on the mask layer 200 to form a semiconductor substrate 111 and discrete features 112 as shown in FIG. 2 , and a mask is provided on the feature 112 Layer 200.
  • the semiconductor substrate 111 is formed of materials such as silicon or germanium, and the mask layer 200 is formed of silicon dioxide.
  • the mask layer 200 may be formed of other insulating materials, such as silicon nitride or nitrogen. Silicon oxide etc.
  • the tilt of the feature portion 112 will cause the formed active region to tilt, that is, the feature portion 112 in the vertical state can avoid the tilt of the active region.
  • the height of the feature portion 112 is H
  • the gap between the discrete feature portions 112 is S
  • the preset aspect ratio in this embodiment is The ratio is 10, that is, the aspect ratio of the feature portion 112 is greater than 10.
  • the aspect ratio of the convex portion formed by the feature portion 112 and the mask layer 200 is greater than the aspect ratio of the feature portion 112; in other embodiments,
  • the preset aspect ratio can be 5, 8, 12, 15, etc., which can be set according to actual needs.
  • the inclination of the feature 112 may be caused only in a semiconductor process with a large aspect ratio of the feature.
  • Ashing is performed on the semiconductor structure.
  • the semiconductor structure includes a semiconductor substrate 111 , a feature portion 112 and a mask layer 120 ; in this embodiment, ashing treatment is performed on the semiconductor substrate 111 and the feature portion 112 .
  • the ashing process is used for ashing and etching the remaining etching gas or etching liquid to prevent the remaining etching gas or etching liquid from continuing to etch the semiconductor substrate 111 and the feature portion 112.
  • this embodiment provides two ashing treatment methods, which are as follows:
  • Oxygen-free ashing treatment the semiconductor substrate 111 and the feature portion 112 are ashed with a first mixed gas that does not contain oxygen.
  • the first mixed gas at least includes hydrogen and nitrogen, so as to remove the corrosive gas remaining on the surface after etching and polymer materials.
  • oxygen-free ashing treatment since the mixed gas does not contain oxygen, it will not cause damage to the surface of the semiconductor substrate and the feature 112 (the surface of the feature 112 and the semiconductor substrate 111 will not be oxidized, such as silicon will not be oxidized. ), so in this embodiment, oxygen-free ashing treatment is used for ashing treatment; in addition, the use of hydrogen can effectively remove corrosive gases and polymer materials remaining on the feature portion and the surface of the semiconductor substrate 111 .
  • Oxygen ashing treatment the semiconductor substrate 111 and the feature portion 112 are ashed with a second mixed gas containing oxygen, and the second mixed gas at least includes hydrogen, nitrogen and oxygen.
  • the mixed gas contains oxygen, the ashing efficiency is higher, and the corrosive gas and polymer materials remaining on the surface after etching can be removed more quickly.
  • ashing treatment may be performed by means of aerobic ashing treatment.
  • the semiconductor structure is cleaned.
  • the semiconductor structure includes a semiconductor substrate 111 , a feature portion 112 and a mask layer 120 ; in this embodiment, the semiconductor substrate 111 and the feature portion 112 are cleaned.
  • the cleaning process includes a first cleaning process and a second cleaning process.
  • the first cleaning process is used to repair defects on the surface of the feature portion 112 . Or a part of the sidewall is not completely etched to form a bump, thereby causing the surface of the feature portion 112 to be uneven, and the second cleaning process is used to remove the oxide layer generated in the first cleaning process.
  • a first cleaning process is performed on the semiconductor substrate 111 and the feature portion 112.
  • the first cleaning process is used to repair defects on the surface of the feature portion 112.
  • an oxide layer is formed on the surface of the semiconductor substrate 111 and the feature portion 112. ;
  • an oxide layer 120 will be formed on the surface of the feature portion 112 and the semiconductor substrate 111 .
  • the principle of the second cleaning treatment is SiO 2 +6HF ⁇ 2H + +SiF 6 2 ⁇ +2H 2 O ⁇ H 2 SiF 6 (dissolved)+2H 2 O.
  • the oxide layer (SiO 2 ) is converted into H 2 SiF 6 dissolved in water so as to etch and remove the oxide layer 120 .
  • the thicknesses of the remaining feature portion 112 and the remaining substrate 111 are thinner than those of the feature portion 112 and the semiconductor substrate 111. Since the thickness of the oxide layer 120 is smaller, the thickness variation of the feature portion 112 and the semiconductor substrate 111 is also smaller accordingly.
  • the thicknesses of the remaining features 112 and the remaining substrates 111 in the schematic diagrams shown in the drawings do not change significantly. According to the above explanation, those skilled in the art know that after the second cleaning process, the thicknesses of the features 112 and the semiconductor substrate 111 will change. Variety.
  • the semiconductor structure includes a semiconductor substrate 111 , a feature portion 112 and a mask layer 120 ; in this embodiment, the semiconductor substrate 111 and the feature portion 112 are dried. Specifically, the remaining substrate 111 and the remaining features 112 are subjected to a drying process.
  • the drying process includes: using isopropyl alcohol (IPA) at a first temperature to dry the surface of the remaining features 112 ; while drying the surface of the remaining features 112 , using deionized water at a second temperature to dry the bottom of the remaining substrate 111 . dry.
  • IPA isopropyl alcohol
  • the process is to provide hot deionized water to the back of the wafer during the drying process, and to provide heated isopropanol to the front of the wafer at the same time, because if the back of the wafer is not With heating, the temperature of the isopropyl alcohol to the wafer surface will be lower, while the backside provides hot deionized water to control the temperature of the wafer, preventing the temperature difference between the center and the edge of the wafer. This can further enhance the drying effect of isopropyl alcohol for better drying of the wafer.
  • the temperature range of the first temperature is 60°C to 80°C
  • the temperature range of the second temperature is 60°C to 80°C.
  • the first temperature or the second temperature can be 65°C, 70°C or 75°C.
  • At least one mask layer 200 in the adjacent group of mask layers 200 is inclined toward the direction of the adjacent mask layer 200, and after the drying process, the inclined mask layer 200 and the adjacent mask layer 200 are inclined.
  • the spacing of the layers 200 is smaller than the spacing between the two prior to the drying process.
  • the mask layers 200 on top of the inclined remaining features 112 are bonded to each other (the distance between the mask layers 200 is 0) as an example for description.
  • the capillary force of the chemical reagent can release a sufficiently large force during the drying process, thereby causing the remaining features to tilt.
  • the convex part includes the feature part and the mask layer on the top of the feature part, the convex part can be narrow at the top and wide at the bottom, equal width at the top and bottom, or wide at the top and narrow at the bottom.
  • the upper and lower equal widths are only for illustration. In the actual process, the bottom of the raised part is wider than the top.
  • Due to the existence of the width difference the surface tension at the top of the raised part is along the tangent ⁇ direction, and the ⁇ direction is different from the vertical direction.
  • the included angle of the direction is ⁇
  • the masking layer on the top surfaces of the remaining features 112 is removed.
  • the mask layer on the top of the remaining features 112 is bonded to form the bonding mask layer 210.
  • the inclination of the features at this time is not the same. Large, or even not tilted, to ensure that the subsequently formed active region is not tilted or tilted to a lesser extent.
  • a chemical method is used to remove the mask layer on the top surface of the remaining features 112 , and the chemical gas used in the chemical method has an etching selectivity ratio of the mask layer and the remaining features 112 greater than 500:1.
  • a relatively large chemical gas is selected for etching, and in the process of etching and removing the mask layer, the remaining features 112 are prevented from being etched as much as possible.
  • the chemical method used to remove the mask layer on the top surface of the remaining features 112 includes:
  • the semiconductor structure 400 is placed in the reaction chamber 300 as a whole.
  • the reaction chamber 300 includes at least two air inlets (a first air inlet 301 and a second air inlet 302), two air outlets (a first air outlet 303 and a second air outlet 304), and a On the stage 305 for carrying the entire semiconductor structure 400 .
  • a chemical gas is introduced into the reaction chamber 300, and the chemical gas at least includes: ammonia gas and hydrogen fluoride.
  • the chemical gas further includes argon.
  • ammonia gas is first introduced into the reaction chamber 300 through the first air inlet 301
  • hydrogen fluoride is introduced into the reaction chamber 300 through the second air inlet 302 .
  • the mask layer in the entire semiconductor structure 400 on the stage 305 reacts as follows:
  • reaction (1) hydrogen fluoride is used as a reaction gas to react with the mask layer in the whole semiconductor structure 400 to generate SiF 4
  • ammonia gas is used as a catalyst to accelerate the progress of the reaction.
  • reaction (2) ammonia gas and hydrogen fluoride are simultaneously used as reaction gases, and continue to react with SiF 4 generated in the first step reaction to generate volatile (NH 4 ) 2 SiF 6 solid.
  • argon can also be introduced as a carrier gas, and argon can prevent the hydrogen fluoride gas from condensing in the gas inlet pipe (in this embodiment, the second gas inlet 302 in particular), which is used to convert the hydrogen fluoride gas It is carried to the whole of the semiconductor structure 400 for reaction.
  • the third temperature ranges from 30°C to 150°C, for example, 50°C, 70°C, 90°C, 110°C or 130°C. In this embodiment, the third temperature is 35°C.
  • the mask layer is heat-treated at a fourth temperature while a carrier gas is supplied to the mask layer, that is, the evaporative removal reaction is generating (NH 4 ) 2 SiF 6 solid, referring to FIG. 9 , passing through the support stage 305
  • the entire semiconductor structure 400 is heated so that the temperature of the entire semiconductor structure 400 is at the fourth temperature.
  • the fourth temperature ranges from 100°C to 200°C, specifically 110°C, 130°C, 150°C, 170°C or 190°C. In this embodiment, the fourth temperature is 150°C.
  • the mask layer is heat-treated to accelerate the volatilization of the (NH 4 ) 2 SiF 6 solid, and at the same time, nitrogen gas is introduced into the first air inlet 301 and the second air inlet 302 as a carrier gas to convert the volatilized (NH 4 ) 2 SiF 6
  • the solids are brought into the vents (first vent 303 and second vent 304), thereby completing the etching of the mask layer on top of the remaining features 112.
  • the feature part is a high aspect ratio structure, and the feature part is inclined, that is, the high aspect ratio structure is inclined, and the feature part is in a vertical state to avoid the high aspect ratio structure inclination.
  • the mask layer on the top of the feature is removed, and the feature is tilted by capillary force.
  • this solution does not remove the mask layer on the top of the feature portion during the ashing and cleaning process.
  • the mask layer is tilted by capillary force, and then after the mask layer is removed, the feature portion is removed. Restoring the initial state effectively improves the problem of inclination of the high aspect ratio structure when cleaning the high aspect ratio structure, and the process flow is simple and the cost is low.
  • Another embodiment of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate and a mask layer on the semiconductor substrate; using the mask layer as a mask, etching the semiconductor substrate to form discrete features, the features The aspect ratio of the part is greater than the preset aspect ratio; ashing, cleaning and drying are performed on the semiconductor structure in sequence, and the semiconductor structure includes a semiconductor substrate, a feature part and a mask layer; the mask layer is removed.
  • a semiconductor substrate 111 is provided.
  • the top surface of the semiconductor substrate 111 has a mask layer 200 .
  • the semiconductor substrate 111 is etched to form discrete features 112 , and the depth and width of the features 112 are ratio is greater than the preset aspect ratio.
  • a mask layer 200 is formed on a substrate 101 , and the substrate 101 is etched based on the mask layer 200 to form a semiconductor substrate 111 and discrete features 112 as shown in FIG. 2 , and a mask is provided on the feature 112 Layer 200.
  • the semiconductor substrate 111 is formed of materials such as silicon or germanium
  • the mask layer 200 is formed of silicon dioxide.
  • the mask layer 200 may be formed of other insulating materials, such as silicon nitride or nitrogen. Silicon oxide etc.
  • the tilt of the feature portion 112 will cause the formed active region to tilt, that is, the feature portion 112 in the vertical state can avoid the tilt of the active region.
  • the height of the feature portion 112 is H
  • the gap between the discrete feature portions 112 is S
  • the preset aspect ratio in this embodiment is The ratio is 10, that is, the aspect ratio of the feature portion 112 is greater than 10.
  • the aspect ratio of the convex portion formed by the feature portion 112 and the mask layer 200 is greater than the aspect ratio of the feature portion 112; in other embodiments,
  • the preset aspect ratio can be 5, 8, 12, 15, etc., which can be set according to actual needs.
  • the inclination of the feature 112 may be caused only in a semiconductor process with a large aspect ratio of the feature.
  • Ashing is performed on the semiconductor structure.
  • the semiconductor structure includes a semiconductor substrate 111 , a feature portion 112 and a mask layer 120 ; in this embodiment, ashing treatment is performed on the semiconductor substrate 111 and the feature portion 112 .
  • the ashing process is used for ashing and etching the remaining etching gas or etching liquid, so as to prevent the remaining etching gas or etching liquid from continuing to etch the semiconductor substrate 111 and the feature portion 112 .
  • the semiconductor structure is cleaned.
  • the semiconductor structure includes a semiconductor substrate 111 , a feature portion 112 and a mask layer 120 ; in this embodiment, the semiconductor substrate 111 and the feature portion 112 are cleaned.
  • the cleaning process includes a first cleaning process and a second cleaning process.
  • the first cleaning process is used to repair defects on the surface of the feature portion 112
  • the second cleaning process is used to remove the oxide layer generated in the first cleaning process.
  • the semiconductor structure is subjected to drying treatment, and the semiconductor structure includes a semiconductor substrate 111 , a feature portion 112 and a mask layer 120 ; in this embodiment, a drying treatment is performed on the semiconductor substrate 111 and the feature portion 112 , specifically, the remaining The substrate 111 and the remaining features 112 are dried.
  • the masking layer on the top surfaces of the remaining features 112 is removed.
  • the mask layer on the top of the remaining features 112 is bonded to form the bonding mask layer 210.
  • the inclination of the features at this time is not the same. Large, or even not tilted, to ensure that the subsequently formed active region is not tilted or tilted to a lesser extent.

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Abstract

一种半导体结构的处理方法及形成方法，该半导体结构的处理方法包括：提供半导体基底(111)，半导体基底(111)上设置有特征部(112)，特征部(112)的深宽比大于预设深宽比，特征部(112)顶部设置有掩膜层(200)；对半导体结构进行灰化处理，半导体结构包括半导体基底(111)、特征部(112)以及掩膜层(200)；对半导体结构进行清洗处理；对半导体结构进行干燥处理；去除掩膜层(200)；在干燥处理过程中，至少相邻的一组掩膜层(200)中一掩膜层(200)向相邻掩膜层(200)的方向倾斜，且在干燥处理之后，倾斜的掩膜层(200)与相邻掩膜层(200)的间距小于在干燥处理之前二者的间距。

Description

半导体结构的处理方法及形成方法
交叉引用
本申请引用于2020年7月2日递交的名称为“半导体结构的处理方法及形成方法”的第202010634483.6号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，涉及一种半导体结构的处理方法及形成方法。
背景技术
在半导体制造过程中通常需要多道处理工序，例如材料沉积、平坦化、特征图案化、蚀刻、清洗等。随着集成电路制程持续缩小，制造工艺日益复杂，高深宽比结构愈发重要。由于制程的缩小，特征部深度不变或深度变深且宽度变小，导致了特征部的深宽比变大。高深宽比结构(HAR)的工艺极易产生侧向弯曲、顶部CD和底部CD的变化、颈缩、倾斜及图形扭曲等问题。如何提高HAR结构的质量，防止HAR结构倾斜是一个亟需解决的问题。
发明内容
本申请实施例提供一种半导体结构的处理方法及形成方法，有效的改善了高深宽比结构倾斜的问题，且流程简单、成本低廉。
为解决上述技术问题，本申请实施例提供了一种半导体结构的处理方法，包括：提供半导体基底，半导体基底上设置有特征部，特征部的深宽比大于预设深宽比，特征部顶部设置有掩膜层；对半导体结构进行灰化处理，半导体结构包括半导体基底、特征部以及掩膜层；对半导体结构进行清洗处理；对半导 体结构进行干燥处理；去除掩膜层；其中，在干燥处理过程中，至少相邻的一组掩膜层中一掩膜层朝向相邻的掩膜层的方向倾斜，且在干燥处理之后，倾斜的掩膜层与相邻的掩膜层之间的间距小于在干燥处理之前二者的间距。
特征部为高深宽比结构，特征部倾斜即高深宽比结构倾斜，特征部处于竖直状态可避免高深宽比结构倾斜。相关技术中，在刻蚀形成特征部后进行灰化处理和清洗处理过程中，去除特征部顶部的掩膜层，特征部受到毛细力作用而倾斜。与相关技术相比，本方案在灰化清洗处理时并不去除特征部顶部的掩膜层，在清洗处理结束后，掩膜层受到毛细力作用而倾斜，而后去除掩膜层后，特征部恢复初始状态，有效的改善了清洗高深宽比结构时产生的高深宽比结构倾斜的问题，且工艺流程简单、成本低廉。
另外，对半导体结构进行灰化处理，包括：采用不含氧的第一混合气体对半导体结构进行灰化处理。另外，第一混合气体至少包括氢气和氮气。采用不含氧气的第一混合气体进行灰化处理，防止灰化处理过程中，半导体结构表面被氧化。
另外，对半导体结构进行灰化处理，包括：采用含氧的第二混合气体对特征部的表面进行灰化处理。另外，第二混合气体至少包括氢气、氮气和氧气。采用含有氧气的第二混合气体进行灰化处理，加快灰化处理工艺的时间，从而提高半导体制程的制程效率。
另外，对半导体结构进行清洗处理，包括：对半导体结构进行第一清洗处理，进行第一清洗处理之后，半导体结构表面形成有氧化层；对半导体结构进行第二清洗处理，第二清洗处理用于去除氧化层。
另外，第一清洗处理采用NH 4OH、H 2O 2和H 2O的混合液体，且NH 4OH、 H 2O 2和H 2O的配比(体积比)范围为NH 4OH：H 2O 2：H 2O＝1:1～4:20～100。
另外，第二清洗处理采用30％～70％浓度的HF和H 2O的混合液体，且30％～70％浓度的HF和H 2O的体积比范围为30％～70％浓度的HF：H2O＝100～300：1。
另外，对半导体结构进行干燥处理，包括：采用第一温度的异丙醇对特征部表面进行干燥；在对特征部表面进行干燥的同时，采用第二温度的去离子水对半导体基底底部进行干燥。具体而言，以半导体基底为晶圆为例，该过程是在干燥的过程中向晶圆的背面提供热的去离子水，并同时向晶圆的正面提供加热的异丙醇,原因是如果不对晶圆背面进行加热，异丙醇达到晶圆表面的温度会变低，同时背面提供热的去离子水用于就是控制晶圆的温度，防止出现晶圆的中心和边缘的温度不同。如此能够进一步强化异丙醇的干燥效果，以便更好地干燥晶圆。
另外，第一温度的温度范围为60℃～80℃，第二温度的温度范围为60℃～80℃。
另外，去除掩膜层，包括：向掩膜层提供化学气体，在第三温度下与掩膜层发生化学反应；在进行化学反应后，在第四温度下对掩膜层进行热处理并同时向掩膜层提供载气，以蒸发去除掩膜层。
另外，第三温度的温度范围为30℃～150℃；第四温度的温度范围为100℃～200℃。
另外，化学气体对掩膜层和特征部的刻蚀选择比大于500：1。
另外，化学气体至少包括氨气和氟化氢，载体至少包括氮气或者氩气。
另外，预设深宽比为10。
本申请实施例还提供一种半导体结构的形成方法，包括：提供半导体基底以及位于半导体基底上的掩膜层；以掩膜层为掩膜，刻蚀半导体基底形成分立的特征部，特征部的深宽比大于预设深宽比；对半导体结构依次进行灰化处理、清洗处理和干燥处理，半导体结构包括半导体基底、特征部以及掩膜层；去除掩膜层。
该方法能够形成无塌陷的高深宽比结构，有效地改善了高深宽比结构倾斜的问题，且流程简单、成本低廉。
附图说明
图1至图6为本申请一实施例提供的半导体结构的处理方法各步骤对应的剖面结构示意图；
图7为本申请一实施例提供的半导体结构的处理方法中特征部倾斜的原理图；
图8和图9为本申请一实施例提供的化学方法刻蚀处理的流程示意图。
具体实施方式
由于毛细力产生的高深宽比结构倾斜是一个严重的问题并且会导致半导体缺陷的产生。随着半导体集成度的增加，高深宽比结构的使用也愈加普遍。高深宽比结构可以为具有大于5:1、10:1或20:1的深宽比的特征部。在高深宽比结构中，尤其是深宽比达到10以上的高深宽比结构的半导体制程中，在清洗以及干燥处理过程中，由于毛细作用力会造成HAR结构倾斜甚至塌陷，且深宽比越高，其倾斜的情况越严重。
然而申请人发现：减少HAR结构倾斜的方法已经开发并应用，例如，晶圆清洗过程中使用超临界二氧化碳来进行干燥处理，这种工艺及其昂贵并且 通常需要精确的控制，需要精确称重干燥处理所需的异丙醇的重量，同时超临界二氧化碳需要高压以达到临界点。
所以当前急需一种成本低并且简单的处理方法，以减少清洗高深宽比结构时产生的高深宽比结构倾斜问题。
为解决上述问题，本申请一实施例提供了一种半导体结构的处理方法，包括：提供半导体基底，半导体基底上设置有特征部，特征部的深宽比大于预设深宽比，特征部顶部设置有掩膜层；对半导体结构进行灰化处理，半导体结构包括半导体基底、特征部以及掩膜层；对半导体结构进行清洗处理；对半导体结构进行干燥处理；去除掩膜层；其中，在干燥处理过程中，至少相邻的一组掩膜层中一掩膜层朝向相邻的掩膜层的方向倾斜，且在干燥处理之后，倾斜的掩膜层与相邻的掩膜层之间的间距小于在干燥处理之前二者的间距。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1至图6为本申请实施例提供的半导体结构的处理方法各步骤对应的剖面结构示意图，下面对本实施例的半导体结构的处理方法进行具体说明。
参考图1以及图2，提供半导体基底111，半导体基底111上设置有特征部112，特征部112顶部表面具有掩膜层200，且特征部的深宽比大于预设深宽 比。
具体地，参考图1，在基底101上形成掩膜层200，基于掩膜层200刻蚀基底101形成如图2所示的半导体基底111以及分立的特征部112，特征部112上具有掩膜层200。
在本实施例中，半导体基底111采用硅或锗等材料形成，掩膜层200采用二氧化硅形成，在其他实施例中，掩膜层200可以采用其他绝缘材料形成，例如氮化硅或氮氧化硅等。
另外，对于本实施例中提供的特征部112，用于后续形成有源区，特征部112倾斜会导致形成的有源区倾斜，即特征部112处于竖直状态可避免有源区倾斜。
参考图2，特征部112的高度为H，分立的特征部112之间的间隙为S，特征部112的深宽比H/S＞预设深宽比，在本实施例中预设深宽比为10，即特征部112的深宽比＞10，相应地，特征部112与掩膜层200构成的凸起部的深宽比大于特征部112的深宽比；在其他实施例中，预设深宽比可以为5、8、12、15等，根据实际需求进行设置。在特征部的深宽比大的半导体工艺制程中，才可能造成特征部112的倾斜。本领域技术人员可知，在实施例中对特征部112深宽比的限定是为了保证后续的干燥工艺中，确保出现特征部112的倾斜，以深宽比的限定导致后续出现特征部112倾斜的技术方案，都应属于本申请的保护范围。
对半导体结构进行灰化处理，半导体结构包括半导体基底111、特征部112以及掩膜层120；在本实施例中，对半导体基底111以及特征部112进行灰化处理。灰化处理用于灰化刻蚀剩余的刻蚀气体或刻蚀液体，防止残留的刻蚀 气体或刻蚀液体继续刻蚀半导体基底111以及特征部112。
具体地，本实施例给出了两种灰化处理方式，具体如下：
无氧灰化处理：采用不含氧的第一混合气体对半导体基底111以及特征部112进行灰化处理，第一混合气体至少包括氢气和氮气，以便清除刻蚀后残留在表面的腐蚀性气体和高分子材料。对于无氧灰化处理，由于混合气体中不含有氧气，并不会对半导体基底和特征部112的表面造成损伤(不会氧化特征部112和半导体基底111的表面，如不会对硅进行氧化)，因此在本实施例中，采用无氧灰化处理的方式进行灰化处理；此外，使用氢气能够有效去除残留在特征部和半导体基底111表面的腐蚀性气体和高分子材料。
有氧灰化处理：采用含氧的第二混合气体对半导体基底111以及特征部112进行灰化处理，第二混合气体至少包括氢气、氮气和氧气。对于有氧灰化处理，由于混合气体中含有氧气，灰化效率更高，能更快地清除刻蚀后残留在表面的腐蚀性气体和高分子材料。在其他实施例中，可以采用有氧灰化处理的方式进行灰化处理。
参考图3及图4，对半导体结构进行清洗处理，半导体结构包括半导体基底111、特征部112以及掩膜层120；在本实施例中，对半导体基底111以及特征部112进行清洗处理。
清洗处理包括第一清洗处理以及第二清洗处理，第一清洗处理用于修复特征部112表面的缺陷，缺陷即在刻蚀形成特征部112的过程中，部分侧壁被过刻蚀形成的凹陷或者部分侧壁没被完全刻蚀形成的凸起，从而导致特征部112表面的不平整，第二清洗处理用于去除第一清洗处理中生成的氧化层。
具体地，对半导体基底111以及特征部112进行第一清洗处理，第一清 洗处理用于修复特征部112表面的缺陷，进行第一清洗处理之后，半导体基底111以及特征部112表面形成有氧化层；对半导体基底111以及特征部112进行第二清洗处理，第二清洗处理用于去除氧化层。
参考图3，第一清洗处理采用NH 4OH、H 2O 2和H 2O的混合液体(即SC-1混合液体)，且NH 4OH、H 2O 2和H 2O的配比(体积比)范围为NH 4OH：H 2O 2：H 2O＝1:1～4:20～100。
由于第一清洗处理使用的混合液体具有较强的氧化性，在清洗处理过程中，会在特征部112以及半导体基底111表面形成氧化层120。
参考图4，第二清洗处理采用采用30％～70％浓度的HF和H 2O的混合液体，且30％～70％浓度的HF和H 2O的配比(体积比)范围为30％～70％浓度的HF：H 2O＝100～300：1。在本实施例中，具体可采用例如40％、50％或60％浓度的HF和H 2O的混合液体。
第二清洗处理的原理即SiO 2+6HF→2H ++SiF 6 2-+2H 2O→H 2SiF 6(溶解)+2H 2O。通过化学去除的方式，将氧化层(SiO 2)转换为溶于水的H 2SiF 6从而刻蚀去除氧化层120。此时剩余特征部112以及剩余基底111相比于特征部112以及半导体基底111其厚度变薄，由于氧化层120的厚度较小，特征部112以及半导体基底111的厚度变化也相应较小，因此附图给出的示意图中剩余特征部112以及剩余基底111的厚度并没有显著改变，依据上述解释，本领域技术人员知晓在经过第二清洗处理后，特征部112以及半导体基底111的厚度发生的变化。
参考图5，进行清洗处理之后，对半导体结构进行干燥处理，半导体结构包括半导体基底111、特征部112以及掩膜层120；在本实施例中，对半导体 基底111以及特征部112进行干燥处理，具体地，对剩余基底111以及剩余特征部112进行干燥处理。
干燥处理包括：采用第一温度的异丙醇(IPA)对剩余特征部112表面进行干燥；在对剩余特征部112表面进行干燥的同时，采用第二温度的去离子水对剩余基底111底部进行干燥。
以半导体基底为晶圆为例，该过程是在干燥的过程中向晶圆的背面提供热的去离子水，并同时向晶圆的正面提供加热的异丙醇,原因是如果不对晶圆背面进行加热，异丙醇达到晶圆表面的温度会变低，同时背面提供热的去离子水用于控制晶圆的温度，防止出现晶圆的中心和边缘的温度不同。如此能够进一步强化异丙醇的干燥效果，以便更好地干燥晶圆。
其中，第一温度的温度范围为60℃～80℃，第二温度的温度范围为60℃～80℃。在本实施例中，第一温度或第二温度可采用65℃、70℃或75℃。
在干燥处理过程中，至少相邻的一组掩膜层200中一掩膜层200向相邻掩膜层200的方向倾斜，且在干燥处理之后，倾斜的掩膜层200与相邻掩膜层200的间距小于在干燥处理之前二者的间距。在本实施例中，以倾斜的剩余特征部112顶部的掩膜层200相互粘合(掩膜层200之间的间距为0)为例进行描述。
具体地，干燥处理过程中，化学试剂的毛细力可在干燥过程中释放足够大的作用力，从而造成剩余特征部的倾斜，其原理参考图7，如图所示，两个分立的凸起部(凸起部包括特征部以及特征部顶部的掩膜层，凸起部可以为上窄下宽、上下等宽、或上宽下窄结构，本实施例给出的附图中凸起部上下等宽仅为示意说明，实际过程中刻蚀出的凸起部的底部要比顶部宽)由于宽度差的 存在，此时凸起部顶部的表面张力沿切线γ方向，γ方向与竖直方向的夹角为θ，作用在凸起部两侧的毛细力F＝2γHDtcosθ/S，其中H、D、S分别为凸起部的高度、长度以及凸起部之间的间距，t为毛细力F的作用时间。
由上述的论述可知，当其他条件(γ、D、t、cosθ以及S)不变毛细力F与凸起部的高度H成正比，即凸起部越高的位置，受到的毛细力F越大，相应的倾斜程度也会越大。此时，位于凸起部顶端的掩膜层的倾斜程度最大以至于掩膜层粘合形成粘合掩膜层210，剩余特征部112虽也存在倾斜，但是倾斜程度远小于掩膜层，因此，图5中给出的剩余特征部112为竖直状，是为了体现剩余特征部112与掩膜层的倾斜程度不同。此外，本实施例中为了保证顶部粘合的部分一定为掩膜层，在形成掩膜层时，掩膜层的厚度大于50nm。
参考图6，进行干燥处理之后，去除剩余特征部112顶部表面的掩膜层。
在本实施例中，进行干燥处理之后，剩余特征部112顶部的掩膜层粘合形成粘合掩膜层210，在去除粘合掩膜层210之后，由于此时的特征部的倾斜程度不大，甚至不倾斜，确保后续形成的有源区不会倾斜或倾斜的程度较小。
具体地，去除剩余特征部112顶部表面的掩膜层采用化学方法，化学方法采用的化学气体对掩膜层和剩余特征部112的刻蚀选择比大于500：1。采用刻蚀选择比较大的化学气体，在刻蚀去除掩膜层的过程中，尽可能的避免剩余特征部112被刻蚀。
具体参考图8以及图9，去除剩余特征部112顶部表面的掩膜层采用的化学方法，包括：
将半导体结构400整体置于反应室300中。其中，反应室300至少包括两个进气口(第一进气口301和第二进气口302)，两个排气口(第一排气口303 和第二排气口304)以及用于承载半导体结构400整体的承载台305。
向反应室300中通入化学气体，化学气体至少包括：氨气、氟化氢。在本实施例中，化学气体还包括氩气。
具体地，参考图8，先通过第一进气口301向反应室300中通入氨气，通过第二进气口302向反应室300中通入氟化氢。
此时位于承载台305上的半导体结构400整体中的掩膜层发生如下反应：
SiO 2+4HF+4NH 3 ->SiF 4+2H 2O+4NH 3   (1)
SiF 4+2HF+2NH 3 ->(NH 4) 2SiF 6   (2)
其中，在(1)反应中，氟化氢作为反应气体与半导体结构400整体中的掩膜层进行反应生成SiF 4，氨气作为催化剂以加速反应的进行。在(2)反应中，氨气与氟化氢同时作为反应气体，与第一步反应中生成的SiF 4继续反应，生成易挥发的(NH 4) 2SiF 6固体。同时，在上述反应中，还可以通入氩气作为载气，氩气可以防止氟化氢气体冷凝在进气管道(本实施例中，具体为第二进气口302)中，用于将氟化氢气体运载至半导体结构400整体处进行反应。
上述反应发生时，需要保证反应室中的半导体结构400整体于第三温度，改变半导体结构400整体的温度通过承载台305实现。其中，第三温度的范围为30℃～150℃，具体可采用例如50℃、70℃、90℃110℃或130℃，在本实施例中，第三温度采用35℃。
在进行化学反应后，在第四温度下对掩膜层进行热处理并同时向掩膜层提供载气，即蒸发去除反应在生成(NH 4) 2SiF 6固体，参考图9，通过承载台305为半导体结构400整体加热，使半导体结构400整体的温度于第四温度。其中，第四温度的温度范围为100℃～200℃，具体可采用110℃、130℃、150℃、170℃ 或190℃，在本实施例中，第四温度采用150℃。对掩膜层进行热处理以加快(NH 4) 2SiF 6固体的挥发，同时第一进气口301与第二进气口302同时通入氮气作为载气，将挥发的(NH 4) 2SiF 6固体带入排气口(第一排气口303和第二排气口304)，从而完成了剩余特征部112顶部掩膜层的刻蚀。
特征部为高深宽比结构，特征部倾斜即高深宽比结构倾斜，特征部处于竖直状态可避免高深宽比结构倾斜。相关技术中，在刻蚀形成特征部后进行灰化处理和清洗处理过程中，去除特征部顶部的掩膜层，特征部受到毛细力作用而倾斜。与相关技术相比，本方案在灰化清洗处理时并不去除特征部顶部的掩膜层，在清洗处理结束后，掩膜层受到毛细力作用而倾斜，而后去除掩膜层后，特征部恢复初始状态，有效的改善了清洗高深宽比结构时产生的高深宽比结构倾斜的问题，且工艺流程简单、成本低廉。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例提供了一种半导体结构的形成方法，包括：提供半导体基底以及位于半导体基底上的掩膜层；以掩膜层为掩膜，刻蚀半导体基底形成分立的特征部，特征部的深宽比大于预设深宽比；对半导体结构依次进行灰化处理、清洗处理和干燥处理，半导体结构包括半导体基底、特征部以及掩膜层；去除掩膜层。
下面结合附图对本实施例的半导体结构的形成方法进行具体说明。
参考图1以及图2，提供半导体基底111，半导体基底111顶部表面具有 掩膜层200，以掩膜层200为掩膜，刻蚀半导体基底111形成分立的特征部112，特征部112的深宽比大于预设深宽比。
具体地，参考图1，在基底101上形成掩膜层200，基于掩膜层200刻蚀基底101形成如图2所示的半导体基底111以及分立的特征部112，特征部112上具有掩膜层200。在本实施例中，半导体基底111采用硅或锗等材料形成，掩膜层200采用二氧化硅形成，在其他实施例中，掩膜层200可以采用其他绝缘材料形成，例如氮化硅或氮氧化硅等。另外，对于本实施例中提供的特征部112，用于后续形成有源区，特征部112倾斜会导致形成的有源区倾斜，即特征部112处于竖直状态可避免有源区倾斜。
参考图2，特征部112的高度为H，分立的特征部112之间的间隙为S，特征部112的深宽比H/S＞预设深宽比，在本实施例中预设深宽比为10，即特征部112的深宽比＞10，相应地，特征部112与掩膜层200构成的凸起部的深宽比大于特征部112的深宽比；在其他实施例中，预设深宽比可以为5、8、12、15等，根据实际需求进行设置。在特征部的深宽比大的半导体工艺制程中，才可能造成特征部112的倾斜。本领域技术人员可知，在实施例中对特征部112深宽比的限定是为了保证后续的干燥工艺中，确保出现特征部112的倾斜，以深宽比的限定导致后续出现特征部112倾斜的技术方案，都应属于本申请的保护范围。
对半导体结构进行灰化处理，半导体结构包括半导体基底111、特征部112以及掩膜层120；在本实施例中，对半导体基底111以及特征部112进行灰化处理。灰化处理用于灰化刻蚀剩余的刻蚀气体或刻蚀液体，防止残留的刻蚀气体或刻蚀液体继续刻蚀半导体基底111以及特征部112。
参考图3及图4，对半导体结构进行清洗处理，半导体结构包括半导体基底111、特征部112以及掩膜层120；在本实施例中，对半导体基底111以及特征部112进行清洗处理。
清洗处理包括第一清洗处理以及第二清洗处理，第一清洗处理用于修复特征部112表面的缺陷，第二清洗处理用于去除第一清洗处理中生成的氧化层。
参考图5，对半导体结构进行干燥处理，半导体结构包括半导体基底111、特征部112以及掩膜层120；在本实施例中，对半导体基底111以及特征部112进行干燥处理，具体地，对剩余基底111以及剩余特征部112进行干燥处理。
参考图6，去除剩余特征部112顶部表面的掩膜层。
在本实施例中，进行干燥处理之后，剩余特征部112顶部的掩膜层粘合形成粘合掩膜层210，在去除粘合掩膜层210之后，由于此时的特征部的倾斜程度不大，甚至不倾斜，确保后续形成的有源区不会倾斜或倾斜的程度较小。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实 施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (17)

  1. 一种半导体结构的处理方法，其特征在于，包括：
    提供半导体基底，所述半导体基底上设置有特征部，所述特征部的深宽比大于预设深宽比，所述特征部顶部设置有掩膜层；
    对半导体结构进行灰化处理，所述半导体结构包括所述半导体基底、所述特征部以及所述掩膜层；
    对所述半导体结构进行清洗处理；
    对所述半导体结构进行干燥处理；
    去除所述掩膜层；
    其中，在所述干燥处理过程中，至少相邻的一组掩膜层中一所述掩膜层向相邻所述掩膜层的方向倾斜，且在所述干燥处理之后，倾斜的掩膜层与相邻掩膜层的间距小于在所述干燥处理之前二者的间距。
  2. 根据权利要求1所述的半导体结构的处理方法，其特征在于，所述对所述半导体结构进行灰化处理，包括：
    采用不含氧的第一混合气体对所述半导体结构进行灰化处理。
  3. 根据权利要求2所述的半导体结构的处理方法，其特征在于，所述第一混合气体至少包括氢气和氮气。
  4. 根据权利要求1所述的半导体结构的处理方法，其特征在于，所述对所述半导体结构进行灰化处理，包括：
    采用含氧的第二混合气体对所述半导体结构进行灰化处理。
  5. 根据权利要求4所述的半导体结构的处理方法，其特征在于，所述第二混合气体至少包括氢气、氮气和氧气。
  6. 根据权利要求1所述的半导体结构的处理方法，其特征在于，所述对所述半导体结构进行清洗处理，包括：
    对所述半导体结构进行第一清洗处理，进行第一清洗处理之后，所述半导 体结构表面形成有氧化层；
    对所述半导体结构进行第二清洗处理，所述第二清洗处理用于去除所述氧化层。
  7. 根据权利要求6所述的半导体结构的处理方法，其特征在于，所述第一清洗处理采用NH 4OH、H 2O 2和H 2O的混合液体，且NH 4OH、H 2O 2和H 2O的配比(体积比)范围为NH 4OH：H 2O 2：H 2O＝1:1～4:20～100。
  8. 根据权利要求6所述的半导体结构的处理方法，其特征在于，所述第二清洗处理采用30％～70％浓度的HF和H 2O的混合液体，且30％～70％浓度的HF和H 2O的体积比范围为30％～70％浓度的HF：H2O＝100～300：1。
  9. 根据权利要求1所述的半导体结构的处理方法，其特征在于，所述对所述半导体结构进行干燥处理，包括：
    采用第一温度的异丙醇对所述特征部表面进行干燥；
    在对所述特征部表面进行干燥的同时，采用第二温度的去离子水对所述半导体基底底部进行干燥。
  10. 根据权利要求9所述的半导体结构的处理方法，其特征在于，所述第一温度的温度范围为60℃～80℃，所述第二温度的温度范围为60℃～80℃。
  11. 根据权利要求1所述的半导体结构的处理方法，其特征在于，所述去除所述掩膜层，包括：
    向所述掩膜层提供化学气体，在第三温度下与所述掩膜层发生化学反应；
    在进行所述化学反应后，在第四温度下对所述掩膜层进行热处理并同时向所述掩膜层提供载气，以蒸发去除所述掩膜层。
  12. 根据权利要求11所述的半导体结构的处理方法，其特征在于，所述第三温度的温度范围为30℃～150℃；所述第四温度的温度范围为100℃～200℃。
  13. 根据权利要求11所述的半导体结构的处理方法，其特征在于，所述化学气体对所述掩膜层和所述特征部的刻蚀选择比大于500：1。
  14. 根据权利要求13所述的半导体结构的处理方法，其特征在于，所述化学气 体至少包括氨气和氟化氢，所述载气至少包括氮气或者氩气。
  15. 根据权利要求1所述的半导体结构的处理方法，其特征在于，所述预设深宽比为10。
  16. 一种半导体结构的形成方法，其特征在于，包括：
    提供半导体基底以及位于所述半导体基底上的掩膜层；
    以所述掩膜层为掩膜，刻蚀所述半导体基底形成分立的特征部，所述特征部的深宽比大于预设深宽比；
    对半导体结构依次进行灰化处理、清洗处理和干燥处理，所述半导体结构包括所述半导体基底、所述特征部以及所述掩膜层；
    去除所述掩膜层。
  17. 根据权利要求16所述的半导体结构的形成方法，其特征在于，所述预设深宽比为10。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101330035A (zh) * 2007-06-18 2008-12-24 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构及其制造方法
CN101606231A (zh) * 2007-02-05 2009-12-16 朗姆研究公司 超高纵横比电介质刻蚀
CN101908480A (zh) * 2009-06-04 2010-12-08 株式会社日立制作所 半导体器件的制造方法
US20140170853A1 (en) * 2012-12-14 2014-06-19 Lam Research Corporation Image reversal with ahm gap fill for multiple patterning
CN106856163A (zh) * 2016-11-22 2017-06-16 上海华力微电子有限公司 一种高深宽比图形结构的形成方法

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4961820A (en) 1988-06-09 1990-10-09 Fujitsu Limited Ashing method for removing an organic film on a substance of a semiconductor device under fabrication
JPH0637063A (ja) * 1992-07-15 1994-02-10 Yamaha Corp 半導体装置の製法
US6405399B1 (en) 1999-06-25 2002-06-18 Lam Research Corporation Method and system of cleaning a wafer after chemical mechanical polishing or plasma processing
US20050022839A1 (en) 1999-10-20 2005-02-03 Savas Stephen E. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
JP2004172573A (ja) 2002-10-29 2004-06-17 Dainippon Screen Mfg Co Ltd 基板処理装置及び基板処理方法
KR100666390B1 (ko) 2005-06-20 2007-01-09 삼성전자주식회사 패턴 제조 방법 및 이를 이용한 반도체 커패시터의 제조방법
KR100829597B1 (ko) * 2006-11-10 2008-05-14 삼성전자주식회사 반도체 장치의 세정 방법 및 제조 방법
US7838425B2 (en) 2008-06-16 2010-11-23 Kabushiki Kaisha Toshiba Method of treating surface of semiconductor substrate
JP5206622B2 (ja) 2009-08-07 2013-06-12 三菱瓦斯化学株式会社 金属微細構造体のパターン倒壊抑制用処理液及びこれを用いた金属微細構造体の製造方法
US8440573B2 (en) 2010-01-26 2013-05-14 Lam Research Corporation Method and apparatus for pattern collapse free wet processing of semiconductor devices
US8617993B2 (en) 2010-02-01 2013-12-31 Lam Research Corporation Method of reducing pattern collapse in high aspect ratio nanostructures
JP5622512B2 (ja) * 2010-10-06 2014-11-12 株式会社東芝 半導体装置の製造方法
KR101788323B1 (ko) * 2011-04-26 2017-11-16 에스케이하이닉스 주식회사 반도체 장치 및 비휘발성 메모리 소자 제조 방법
CN103050439B (zh) * 2012-12-19 2017-10-10 上海华虹宏力半导体制造有限公司 互连线结构及互连线结构的形成方法
CN104517813A (zh) * 2013-09-29 2015-04-15 中芯国际集成电路制造(上海)有限公司 双重图形的形成方法
JP6405958B2 (ja) 2013-12-26 2018-10-17 東京エレクトロン株式会社 エッチング方法、記憶媒体及びエッチング装置
JP6269467B2 (ja) 2013-12-27 2018-01-31 富士フイルム株式会社 カラーフィルターの製造方法および固体撮像素子の製造方法
US9449821B2 (en) 2014-07-17 2016-09-20 Macronix International Co., Ltd. Composite hard mask etching profile for preventing pattern collapse in high-aspect-ratio trenches
JP6315694B2 (ja) 2014-09-19 2018-04-25 東京エレクトロン株式会社 半導体装置の製造方法、ならびに皮膜の形成方法および形成装置
US10068781B2 (en) 2014-10-06 2018-09-04 Lam Research Corporation Systems and methods for drying high aspect ratio structures without collapse using sacrificial bracing material that is removed using hydrogen-rich plasma
JP6568769B2 (ja) 2015-02-16 2019-08-28 東京エレクトロン株式会社 基板処理方法及び基板処理装置
CN106486365B (zh) * 2015-08-26 2019-11-01 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
JP6466315B2 (ja) 2015-12-25 2019-02-06 東京エレクトロン株式会社 基板処理方法及び基板処理システム
JP6424183B2 (ja) 2016-03-18 2018-11-14 信越半導体株式会社 半導体ウェーハの洗浄方法
US10170591B2 (en) * 2016-06-10 2019-01-01 International Business Machines Corporation Self-aligned finFET formation
CN106229288B (zh) 2016-07-27 2019-06-28 上海华虹宏力半导体制造有限公司 有源区制备方法
KR102628534B1 (ko) 2016-09-13 2024-01-26 에스케이하이닉스 주식회사 반도체 기판의 처리 방법
JP7034634B2 (ja) 2017-08-31 2022-03-14 株式会社Ｓｃｒｅｅｎホールディングス 基板処理方法および基板処理装置
CN107863318B (zh) * 2017-11-22 2024-05-17 长鑫存储技术有限公司 基于间距倍增形成的集成电路图案及形成方法
JP6443524B2 (ja) * 2017-11-22 2018-12-26 日亜化学工業株式会社 窒化物半導体素子およびその製造方法
CN208142187U (zh) 2018-04-25 2018-11-23 长鑫存储技术有限公司 半导体结构
CN110911338A (zh) * 2018-09-14 2020-03-24 长鑫存储技术有限公司 半导体加工腔室以及晶圆处理方法
CN110931354B (zh) * 2018-09-19 2023-05-05 中芯国际集成电路制造(上海)有限公司 半导体结构以及半导体结构的制造方法
US10629489B2 (en) * 2018-09-24 2020-04-21 International Business Machines Corporation Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices
CN113394074A (zh) 2020-03-11 2021-09-14 长鑫存储技术有限公司 半导体结构的处理方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101606231A (zh) * 2007-02-05 2009-12-16 朗姆研究公司 超高纵横比电介质刻蚀
CN101330035A (zh) * 2007-06-18 2008-12-24 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构及其制造方法
CN101908480A (zh) * 2009-06-04 2010-12-08 株式会社日立制作所 半导体器件的制造方法
US20140170853A1 (en) * 2012-12-14 2014-06-19 Lam Research Corporation Image reversal with ahm gap fill for multiple patterning
CN106856163A (zh) * 2016-11-22 2017-06-16 上海华力微电子有限公司 一种高深宽比图形结构的形成方法

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