WO2023000465A1 - 半导体结构的处理方法 - Google Patents

半导体结构的处理方法 Download PDF

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Publication number
WO2023000465A1
WO2023000465A1 PCT/CN2021/117283 CN2021117283W WO2023000465A1 WO 2023000465 A1 WO2023000465 A1 WO 2023000465A1 CN 2021117283 W CN2021117283 W CN 2021117283W WO 2023000465 A1 WO2023000465 A1 WO 2023000465A1
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treatment
substrate
water vapor
semiconductor structure
barrier layer
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PCT/CN2021/117283
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English (en)
French (fr)
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郗宁
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长鑫存储技术有限公司
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Priority to US17/453,837 priority Critical patent/US20230022624A1/en
Publication of WO2023000465A1 publication Critical patent/WO2023000465A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B5/00—Cleaning by methods involving the use of air flow or gas flow
    • B08B5/02—Cleaning by the force of jets, e.g. blowing-out cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

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  • the present application relates to the field of semiconductor manufacturing, and relates to a method for processing a semiconductor structure.
  • High aspect ratio structures are prone to problems such as lateral bending, changes in top and bottom feature sizes, necking, tilting, and graphic distortion due to the influence of pressure during wet cleaning. How to improve the cleaning quality of the HAR structure and prevent the HAR structure from tilting is an urgent problem to be solved at present.
  • An embodiment of the present application provides a method for processing a semiconductor structure, including: providing a substrate with a characteristic portion on the substrate, the aspect ratio of the characteristic portion is greater than a preset aspect ratio, a barrier layer is provided on the top of the characteristic portion, and the characteristic portion A hydrophilic layer is provided on the side wall of the hydrophilic layer, and there are particulate impurities on the side wall of the hydrophilic layer; the substrate is cleaned at least once, and the cleaning process includes: passing initial water vapor into the side wall of the characteristic part, and performing cooling treatment, so that The initial water vapor attached to the surface of the hydrophilic layer is liquefied into water, and the water carries particles and impurities into the groove; the temperature is raised to make the water vaporize into water vapor, and the water vapor carries particles and impurities to escape.
  • 1 to 4 are structural schematic diagrams corresponding to each step in the processing method of a semiconductor structure provided by some embodiments;
  • FIG. 5 is a schematic diagram of an enlarged structure of a trench in a method for processing a semiconductor structure provided by some embodiments;
  • Figure 6 and Figure 7 are schematic structural diagrams corresponding to a hydrophilic treatment process provided by some embodiments.
  • Fig. 8 is a schematic structural diagram corresponding to another hydrophilic treatment process provided by some embodiments.
  • Fig. 9 is a schematic structural diagram corresponding to another hydrophilic treatment process provided by some embodiments.
  • 10 to 12 are schematic structural diagrams corresponding to each step in the cleaning process provided by some embodiments of the present application.
  • Fig. 13 is a schematic diagram of cleaning the particle impurities on the surface of the groove provided by some embodiments.
  • the feature part is the substrate between the trenches formed by the patterned part of the substrate, and the feature part is a ratio structure; specifically, the high aspect ratio structure is a semiconductor structure with an aspect ratio greater than at least 10:1.
  • the tilting of high aspect ratio structures due to capillary force is a serious problem and can lead to the generation of semiconductor defects; especially the semiconductor process of high aspect ratio structures with aspect ratios above 10
  • the high aspect ratio structure will tilt or even collapse due to capillary force, and the higher the aspect ratio, the more serious the tilt.
  • An embodiment of the present application provides a method for processing a semiconductor structure, including: providing a substrate, forming a barrier layer on the top surface of the substrate; patterning the barrier layer and a partial thickness of the substrate to form a groove, and particles exist in the groove Impurities; carry out hydrophilic treatment on the surface of the groove to improve the hydrophilicity of the surface of the groove; perform at least one cleaning treatment on the remaining substrate, and the cleaning treatment includes: introducing initial water vapor into the groove and performing cooling treatment , to liquefy the initial water vapor adhering to the surface of the groove into water, and the water carries particles and impurities into the groove; the temperature is raised to make the water vaporize into water vapor, and the water vapor carries particles and impurities to escape.
  • FIGS 1 to 4 are structural schematic diagrams corresponding to each step in the processing method of the semiconductor structure
  • Figure 5 is a schematic diagram of the enlarged structure of the groove in the processing method of the semiconductor structure
  • Figures 6 and 7 are corresponding to a hydrophilic treatment process
  • Schematic diagram of the structure Figure 8 is a schematic structural diagram corresponding to another hydrophilic treatment process
  • Figure 9 is a schematic structural diagram corresponding to another hydrophilic treatment process
  • Figures 10 to 12 are schematic structural diagrams corresponding to each step in the cleaning process
  • FIG. 13 is a schematic diagram of cleaning the particles and impurities on the surface of the groove.
  • a substrate 100 is provided, and a feature portion 150 is provided on the substrate 100.
  • the aspect ratio of the feature portion 150 is greater than a preset aspect ratio.
  • a barrier layer 101 is provided on the top of the feature portion 150.
  • the wall is provided with a hydrophilic layer 202 (refer to FIGS. 6 to 9 ), and the sidewall of the hydrophilic layer 202 is attached with particulate impurities 201 (refer to FIGS. 6 to 9 ).
  • the method for forming the characteristic portion 150 includes: providing a substrate 100, forming a barrier layer 101 on the top surface of the substrate, patterning the barrier layer 101 and a partial thickness of the substrate 100, and forming a groove 200. , the remaining substrate 100 between adjacent trenches 200 constitutes the feature 150 .
  • the substrate 100 is formed of semiconductor materials such as silicon or germanium. In this embodiment, the substrate 100 is formed of silicon material.
  • the material of the barrier layer 101 is BACL (boronamorphous carbon layer, boron-doped amorphous carbon layer); in other embodiments, the material of the barrier layer 101 can also be ACL (amorphous carbon layer, amorphous carbon layer ), SiO (silicon oxide) or SiN (silicon nitride).
  • the depth of the formed trench 200 is H, that is, the height of the feature portion 150 is H; the gap between adjacent trenches 200 is S, that is, the width of the feature portion 150 is S; that is, the formed feature
  • the aspect ratio of the portion 150 is H/S, and H/S is greater than the preset aspect ratio.
  • the preset aspect ratio is not less than 10, that is, the formed feature portion 150 is a high aspect ratio structure.
  • the preset aspect ratio is 10; in other embodiments, the preset aspect ratio can be 12, 15, 18 or 20, etc.; in specific applications, the aspect ratio of the characteristic part 150 is adjusted according to actual needs. set up.
  • the limitation of the aspect ratio of the characteristic part 150 in the embodiment of the present application is to ensure that in the subsequent drying process, the use of wet cleaning treatment may cause the characteristic part 150 to be inclined. All technical solutions to limit this problem shall belong to the protection scope of this application.
  • the preset aspect ratio may be any value, that is, the semiconductor structure processing method proposed in this application is suitable for cleaning structures with any aspect ratio.
  • forming the trench 200 specifically includes: forming a patterned mask layer 102 on the top surface of the barrier layer 101, based on the patterned mask layer 102, patterning the barrier layer 101 , until the surface of the substrate 100 is exposed, based on the patterned mask layer 102 , pattern the substrate 100 with a partial thickness to form the trench 200 .
  • the patterned mask layer 102 includes: a first mask layer 112, a second mask layer 122, a third mask layer 132, a fourth mask layer 132, and The film layer 142 and the fifth mask layer 152 .
  • the material of the first mask layer 112 is Poly (polysilicon)
  • the second mask layer 122 is ACL
  • the material of the third mask layer 132 and the fifth mask layer 152 is SiON (silicon oxynitride).
  • the fourth mask layer 143 is SOC (spin coat, spin coating), and the patterned mask layer 102 is used for selectively etching the barrier layer 101 and the substrate 100 .
  • the above description of the specific structure of the mask layer 102 is only used to illustrate the specific structure of the mask layer 102 provided in this embodiment, and does not constitute a limitation to other embodiments of the present application. In other embodiments Among them, mask layers of other structures may also be used, and mask layers of any structure used for patterning the feature portion 150 shall fall within the protection scope of the present application.
  • the barrier layer 101 is patterned until the surface of the substrate 100 is exposed.
  • the remaining barrier layer is the patterned barrier layer 101 , and the pattern in the patterned barrier layer 101 is consistent with the patterned mask layer 102 .
  • a partial thickness of the substrate 100 is patterned to form trenches 200 .
  • particle impurities 201 are attached to the sidewalls of the formed trench 200 , and the particle impurities 201 include impurities such as etching residues during the patterning process.
  • the patterned mask layer 102 is removed. It should be noted that the step of removing the patterned mask layer 102 may be performed after the trench 200 is formed, or may be performed after the patterned barrier layer 101 is formed. Because in this implementation, the material of the barrier layer 101 is BACL, the material of the first mask layer 112 is Poly (polysilicon), the etching selection of BACL and Poly is relatively large, according to the concentration of doped boron in BACL, the concentration of BACL and Poly The etch selectivity ratio is 50:1-300:1, that is, due to the large etch selectivity ratio of BACL and Poly, the process of patterning the substrate 100 with a partial thickness can be based on the patterned barrier layer 101 as a mask Etching is performed. Specifically, in some embodiments, by controlling the concentration of doped boron in BACL, the etching selectivity ratio of BACL to Poly is 100:1, 150:1, 200:1 or 250:1.
  • the method for forming the hydrophilic layer 202 includes: performing hydrophilic treatment on the sidewall of the feature portion 150 to form the hydrophilic layer 202 ; removing the barrier layer 101 , and injecting a purge gas.
  • the processes of hydrophilic treatment and removal of the barrier layer 101 may be performed in a distributed manner, or may be implemented in the same process step.
  • a hydrophilic layer 202 is formed; it should be noted that, in this embodiment, the material of the substrate 100 is silicon, and correspondingly, the material of the hydrophilic layer 202 is silicon oxide, and silicon oxide is hydrophilic, and its The surface easily absorbs water molecules.
  • the hydrophilic layer 202 is formed by performing hydrophilic treatment first, after the hydrophilic layer 202 is formed, and before the cleaning treatment, it also includes: removing the barrier layer 101, passing through purge gas.
  • performing hydrophilic treatment on the sidewall of the characteristic part 150 includes: passing water vapor and gas carrier into the sidewall of the characteristic part 150, and performing plasma treatment on the water vapor during the process of passing the water vapor.
  • the gas carrier may specifically be one of N 2 (nitrogen), Ar (argon) or He (helium), and in this example, the gas carrier is Ar (argon).
  • the flow rate of the gas carrier is 100 sccm-5000 sccm, specifically 1000 sccm, 2000 sccm, 3000 sccm or 4000 sccm; in this example, the flow rate of the gas carrier is 2500 sccm.
  • the processing power of the plasma treatment is 1000W-8000W, specifically 2000W, 4000W or 6000W; in this example, the processing power of the plasma treatment is 4500W.
  • the gas flow rate of the water vapor is in the range of 10 sccm-300 sccm, specifically 150 sccm, 200 sccm or 250 sccm; in this example, the gas flow rate of the water vapor is 155 sccm.
  • the etching gas for removing the barrier layer 101 includes: CF 4 , C 4 F 8 , C 4 F 6 , CHF 3 , CH 2 F 2 or CH 3 F.
  • the ambient pressure of the reaction ranges from 0mTorr to 10000mTorr, specifically 3000mTorr, 6000mTorr or 9000mTorr.
  • the ambient pressure of the reaction is 5000mTorr
  • the substrate 100 The temperature range of the water vapor is 20°C to 100°C, specifically 40mTorr, 60mTorr or 80mTorr, in this example, the temperature of the substrate 100 is 60°C; the temperature range of the water vapor is 100°C to 250°C, specifically 130mTorr, 170mTorr, 200mTorr or 230mTorr, in this example the temperature of the water vapor is 175°C.
  • the temperature of the substrate 100 is controlled by the tray, which is used to carry the substrate 100 in the reaction chamber.
  • the temperature of the substrate 100 placed on the tray is indirectly controlled.
  • the temperature range of the substrate 100 is 20°C to 100°C, that is, the temperature range of the tray is 20°C to 100°C; the temperature of the water vapor is controlled through the gas pipeline, and the gas pipeline is used to feed the substrate 100 into the reaction chamber.
  • the reaction gas thereby controlling the temperature of the gas pipeline, thereby indirectly controlling the temperature of the reaction gas passing into the reaction chamber, in this example, indirectly controlling the temperature of the water vapor
  • the temperature of the water vapor ranges from 100°C to 250°C, That is, the temperature range of the gas pipeline is 100°C to 250°C; in addition, in this example, the temperature of the wall of the reaction chamber is 100°C to 150°C to prevent water vapor from condensing on the wall of the reaction chamber, specifically
  • the temperature of the wall of the reaction chamber may be 110°C, 120°C, 130°C or 140°C, in this example, the temperature of the wall of the reaction chamber is 125°C.
  • the flow rate of the etching gas is 10 sccm-300 sccm, specifically 150 sccm, 200 sccm or 250 sccm; in this example, the flow rate of the etching gas is 155 sccm.
  • removing the barrier layer 101 and performing hydrophilic treatment on the sidewall of the characteristic portion 150 are implemented in the same process step, that is, performing hydrophilic treatment on the sidewall of the characteristic portion 150 and removing The barrier layer 101, in the process of removing the barrier layer 101, a hydrophilic layer 202 is produced.
  • the process of performing hydrophilic treatment and removing the barrier layer 101 on the sidewall of the characteristic part 150 includes: passing water vapor and gas carrier into the sidewall of the characteristic part 150, and in the process of passing water vapor, the water vapor Perform plasma treatment.
  • the flow rate of the gas carrier is 2500 sccm; the processing power of the plasma treatment is 4500 W; in this example, the gas flow rate of the water vapor is 155 sccm.
  • This example is based on the premise that the material of the barrier layer 101 is BACL, and simultaneously uses water vapor to perform hydrophilic treatment and remove the barrier layer 101.
  • the gas flow rate of the water vapor is in the range of 10 sccm to 300 sccm, specifically 150 sccm and 200 sccm or 250 sccm; in this example, the gas flow to water vapor is 155 sccm.
  • the ambient pressure of the reaction is 5000 mTorr
  • the temperature of the substrate 100 is 60° C.
  • the temperature of the water vapor is 175°C.
  • the hydrophilic treatment is first performed to generate a hydrophilic layer 202, and the process of removing the barrier layer 101 is added to the cycle of cleaning treatment and performed simultaneously, that is, part of the barrier is removed before each round of cleaning treatment. layer 101, the remaining barrier layer 101 is removed before the final round of cleaning process is performed.
  • the substrate 100 is cleaned at least once, and the cleaning process includes: injecting initial water vapor 203 into the sidewall of the characteristic portion 150, and performing a cooling treatment, so that The initial water vapor 203 attached to the surface of the hydrophilic layer 202 is liquefied into water 204, and the water 204 flows into the groove 200 carrying the particulate impurities 201; the temperature is raised to make the water vaporize into water vapor 203, and the water vapor 203 carries the particulate impurities 201 to escape. out.
  • water vapor 203 is introduced into the groove 200 and the temperature is lowered.
  • Water molecules adhere to the surface of the groove 200 and accumulate continuously, and slide down the side wall of the groove 200 in the form of liquid water, carrying the groove
  • the particulate impurities 201 on the side walls of the groove 200 flow into the bottom of the groove 200, thereby realizing the transfer of the particulate impurities 201 on the side walls of the groove 200 to the bottom of the groove 200; referring to FIG.
  • the liquid water 204 evaporates into water vapor 203 , and during the evaporation process, the escaping water vapor 203 carries impurity particles 201 and escapes together, thereby completing the cleaning of impurities on the sidewall of the trench 200 .
  • the temperature after cooling treatment ranges from 20°C to 60°C, specifically 30°C, 40°C or 50°C.
  • the temperature after cooling treatment is 20°C;
  • the final temperature range is 60°C to 100°C, specifically 70°C, 80°C or 90°C.
  • the temperature after the heating treatment is 100°C;
  • the temperature change rate of the cooling treatment ranges from 0.5s/°C to 1.5s/°C, it can be 0.8s/°C, 1.0s/°C or 1.2s/°C.
  • the temperature change rate of the cooling treatment is 1.0s/°C; the temperature change rate range of the heating treatment is 0.5s /°C ⁇ 1.5s/°C, specifically, it can be 0.8s/°C, 1.0s/°C or 1.2s/°C. In this example, the temperature change rate of the temperature rise treatment is 1.0s/°C.
  • the initial water vapor flow rate ranges from 1000 sccm to 20000 sccm, specifically 4000 sccm, 7000 sccm, 10000 sccm, 13000 sccm or 16000 sccm. In this example, the initial water vapor flow rate is 10000 sccm.
  • the purge gas fed is N 2 (nitrogen) or an inert gas
  • the purge time of the purge gas ranges from, specifically, 20s to 60s, specifically, 30s, 40s or 50s.
  • the purpose of feeding the purge gas is to clean the reaction gas or the impurity gas generated during the process of hydrophilic treatment and etching of the barrier layer 101 in the reaction chamber where the semiconductor structure is located.
  • performing at least one cleaning treatment on the substrate includes: performing cleaning treatment for a preset number of times in a cycle, so as to ensure complete cleaning of the particle impurities on the sidewall of the trench 200 by performing the cleaning treatment cycle.
  • the preset number of times can be 3, 5, 7, etc., and the specific number of cycles can be set according to the specific impurities; it should be noted that the examples of the above preset times do not constitute limitations on the above embodiments.
  • the post-cleaning process also includes: removing a part of the thickness of the barrier layer 101, and injecting a purge gas; performing the last During the cleaning process, removing part of the thickness of the barrier layer 101 is to remove the barrier layer 101; wherein, the patterned barrier layer 101 shown in FIG. 9 is the height after one etching process, and the remaining patterned barrier layer 101 is still Two etching processes are required, that is, in this example, a total of 3 rounds of cleaning processes are required, that is, the preset number of times is 3.
  • the hydrophilic layer 202 formed by the hydrophilic treatment on the surface of the trench 200 is removed.
  • a chemical method is used to remove the hydrophilic layer 202 , and the etching selectivity ratio of the chemical gas used in the chemical method to the hydrophilic layer 202 and the remaining substrate 100 is greater than 500:1.
  • a chemical gas with relatively large etching selection is used to prevent the remaining substrate 100 from being etched as much as possible during the process of removing the hydrophilic layer 202 .
  • the chemical method used to remove the hydrophilic layer 202 includes: feeding NH 3 and HF, and performing a first temperature treatment; feeding N 2 , and performing a second temperature treatment; wherein, the temperature range after the first temperature treatment 20°C to 40°C, and the temperature range of the first temperature treatment is 100°C to 200°C.
  • hydrophilic layer 202 reacts with NH and HF as follows:
  • reaction (1) HF is used as a reaction gas to react with the hydrophilic layer 202 to generate SiF 4
  • NH 3 is used as a catalyst to accelerate the reaction.
  • reaction (2) NH 3 and HF are used as reaction gases at the same time, and continue to react with SiF4 generated in the first step reaction to generate volatile (NH 4 ) 2 SiF 6 solid.
  • NH 3 ammonia
  • HF hydrogen fluoride
  • Ar argon
  • Ar is introduced as a carrier gas, which can prevent HF gas from condensing in the intake pipe.
  • the first temperature is the temperature range of 20° C. to 40° C. after the first temperature treatment; in some embodiments, the first temperature It can be 25°C, 30°C or 35°C, etc.
  • the first temperature is 30°C; during the process of feeding N 2 , it is necessary to ensure that the reactants are at the second temperature, so that (NH 4 ) 2 SiF 6 solid is sublimated, and the purpose of introducing N 2 is to introduce N 2 as a carrier gas to take out the volatilized (NH 4 ) 2 SiF 6 solid, and the second temperature is the temperature range after the second temperature treatment is 100 °C to 200 °C, in some embodiments, the second temperature may be 120 °C, 140 °C, 160 °C or 180 °C, etc., in this example, the second temperature is 150 °C.
  • the surface of the characteristic part has a hydrophilic layer
  • water molecules are easily attached to the surface of the hydrophilic layer; It accumulates on the surface of the hydrophilic layer, slides down the hydrophilic layer on the side wall of the feature part in the form of liquid water, and carries the particle impurities on the side wall of the hydrophilic layer into the gap between adjacent feature parts, so as to realize the The particle impurities on the sidewall of the feature part are transferred to the bottom of the gap between the adjacent feature parts; after a period of time, the temperature is raised, and the liquid water at the bottom of the gap between the adjacent feature parts evaporates into water vapor.
  • the released water vapor carries the impurity particles and escapes together, thereby completing the impurity cleaning of the side wall of the characteristic part.

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Abstract

本申请实施例涉及一种半导体结构的处理方法，应用于半导体制造领域，包括：提供衬底，衬底上具有特征部，特征部的深宽比大于预设深宽比，特征部顶部设置有阻挡层，特征部的侧壁设置有亲水层，亲水层的侧壁存在颗粒杂质；对衬底进行至少一次清洗处理，清洗处理包括：向特征部的侧壁通入初始水蒸气，并进行降温处理，使附着在亲水层表面的初始水蒸气液化为水，水携带颗粒杂质流入沟槽中；进行升温处理，使水气化为水蒸气，水蒸气携带颗粒杂质逸出；通过对水的状态变化进行沟槽侧壁的清洗，避免了高深宽比结构在清洗过程中发生倾斜的问题。

Description

半导体结构的处理方法
交叉引用
本申请要求于2021年07月20日递交的名称为“半导体结构的处理方法”、申请号为202110821481.2的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体制造领域，涉及一种半导体结构的处理方法。
背景技术
在半导体制造过程中通常需要多重处理工序，例如材料沉积、平坦化、特征图案化、蚀刻、清洗等。随着集成电路制程持续缩小，制造工艺日益复杂，高深宽比结构愈发重要。由于制程的缩小，特征部深度不变且宽度变小，或特征部深度变深且宽度变小，从而导致了特征部的深宽比变大。
高深宽比结构(HAR)在湿法清洗过程中由于压力影响极易产生侧向弯曲、顶部特征尺寸和底部特征尺寸的变化、颈缩、倾斜及图形扭曲等问题。如何提高对HAR结构的清洗质量，防止HAR结构倾斜是当前一个亟待解决的问题。
发明内容
本申请实施例提供了一种半导体结构的处理方法，包括：提供衬底，衬底上具有特征部，特征部的深宽比大于预设深宽比，特征部顶部设置有阻挡层，特征部的侧壁设置有亲水层，亲水层的侧壁存在颗粒杂质；对衬底进行至少一次清洗处理，清洗处理包括：向特征部的侧壁通入初始水蒸气，并进行降温处理，使附着在亲水层表面的初始水蒸气液化为水，水携带颗粒杂质流入沟槽中；进行升温处理，使水气化为水蒸气，水蒸气携带颗粒杂质逸出。
附图说明
图1至图4为一些实施例提供的半导体结构的处理方法中各步骤对应的结构示意图；
图5为一些实施例提供的半导体结构的处理方法中沟槽的放大结构示意图；
图6和图7为一些实施例提供的一种亲水性处理过程对应的结构示意图；
图8为一些实施例提供的另一种亲水性处理过程对应的结构示意图；
图9为一些实施例提供的又一种亲水性处理过程对应的结构示意图；
图10至图12为本申请一些实施例提供的清洗处理中各步骤对应的结构示意图；
图13为一些实施例提供的清洗沟槽表面颗粒杂质的原理图。
具体实施方式
随着半导体集成度的增加，高深宽比结构的使用也愈加普遍；在本申请各实施例中，特征部即图形化部分衬底形成的沟槽之间的衬底，且特征部为高深宽比结构；具体地，高深宽比结构为深宽比至少大于10：1的半导体结构。
在对高深宽比结构的清洗过程中，由于毛细力产生的高深宽比结构倾斜是一个严重的问题并且会导致半导体缺陷的产生；尤其是深宽比达到10以上的高深宽比结构的半导体制程中，在清洗以及干燥处理过程中，由于毛细作用力会造成高深宽比结构倾斜甚至塌陷，且深宽比越高，其倾斜的情况越严重。
减少高深宽比结构倾斜的方法已经开发并应用，例如，晶圆清洗过程中使用超临界二氧化碳来进行干燥处理，这种工艺及其昂贵并且通常需要精确的控制，并不适用于工业上的批量生产；所以当前亟待一种高深宽比的半导体结构的清洗方法，以减少清洗高深宽比结构时产生的结构倾斜问题，并适用于工业上的批量生产。
本申请实施例提供了一种半导体结构的处理方法，包括：提供衬底，在衬底的顶部表面形成阻挡层；图形化阻挡层和部分厚度的衬底，形成沟槽，沟槽内存在颗粒杂质；对沟槽表面进行亲水性处理，以提高沟槽表面的亲水性；对剩余衬底进行至少一次清洗处理，清洗处理包括：向沟槽中通入初始水蒸气，并进行降温处理，使附着在沟槽表面的初始水蒸气液化为水，水携带颗粒杂质流入沟槽中；进行升温处理，使水气化为水蒸气，水蒸气携带颗粒杂质逸出。
本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更 好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图4为半导体结构的处理方法中各步骤对应的结构示意图，图5为半导体结构的处理方法中沟槽的放大结构示意图，图6和图7为一种亲水性处理过程对应的结构示意图，图8为另一种亲水性处理过程对应的结构示意图，图9为又一种亲水性处理过程对应的结构示意图，图10至图12为清洗处理中各步骤对应的结构示意图，图13为清洗沟槽表面颗粒杂质的原理图，以下结合附图对本申请各实施例提供的半导体结构的处理方法作进一步详细说明，具体如下：
参考图1～图4，提供衬底100，衬底100上具有特征部150，特征部150的深宽比大于预设深宽比，特征部150顶部设置有阻挡层101，特征部150的侧壁设置有亲水层202(参考图6～图9)，亲水层202的侧壁附着有颗粒杂质201(参考图6～图9)。
具体地，参考图1～图3，形成特征部150的方法包括：提供衬底100，在衬底顶部表面形成阻挡层101，图形化阻挡层101和部分厚度的衬底100，形成沟槽200，相邻沟槽200之间的剩余衬底100构成特征部150。
在一些实施例中，衬底100采用硅或锗等半导体材料形成。在本实施例中，衬底100采用硅材料形成。
在本实施例中，阻挡层101的材质为BACL(boronamorphous carbon layer，掺硼非晶碳层)；在其他实施例中，阻挡层101的材质还可以为ACL(amorphous carbon layer，非晶碳层)、SiO(氧化硅)或SiN(氮化硅)。
在本实施例中，形成的沟槽200的深度为H，即特征部150的高度为H；相邻沟槽200之间的间隙为S，即特征部150的宽度为S；即形成的特征部150的深宽比为H/S，H/S大于预设深宽比，在一些实施例中，预设深宽比不小于10，即形成的特征部150为高深宽比结构，在本实施例中，预设深宽比为10；在其他实施例中，预设深宽比可以为12、15、18或20等；在具体应用中，特征部150的深宽比根据实际需求进行设置。
本领域技术人员可知，本申请实施例中对特征部150深宽比的限定是为了保证后续的干燥工艺中，采用湿法清洗处理有较大可能会造成特征部150的 倾斜，以深宽比的限定这一问题的技术方案，都应属于本申请的保护范围。另外，在另一些实施例中，预设深宽比还可以为任意值，即本申请提出的半导体结构的处理方法，适用于对任意深宽比结构的清洗。
对于图形化阻挡层101和部分厚度的衬底100，形成沟槽200，具体包括：在阻挡层101顶部表面形成图形化的掩膜层102，基于图形化的掩膜层102，图形化阻挡层101，直至暴露出衬底100的表面，基于图形化的掩膜层102，图形化部分厚度的衬底100，形成沟槽200。
对于在阻挡层101顶部表面形成图形化的掩膜层102。参考图1，在本实施例中，图形化的掩膜层102包括：依次位于阻挡层101上的第一掩膜层112、第二掩膜层122、第三掩膜层132、第四掩膜层142和第五掩膜层152。
具体地，第一掩膜层112的材料为Poly(多晶硅)，第二掩膜层122为ACL，第三掩膜层132和第五掩膜层152的材料为SiON(氮氧化硅)，第四掩膜层143为SOC(spin coat，旋转涂层)，图形化的掩膜层102用于对阻挡层101和衬底100进行选择性刻蚀。
需要说明的是，上述对掩膜层102具体结构的说明，仅用于对本实施例提供的掩膜层102的具体结构进行举例说明，并不构成对本申请其他实施例的限定，在其他实施例中，也可以采用其他结构的掩膜层，用于图形化形成特征部150的任意结构的掩膜层，都应属于本申请的保护范围。
对于基于图形化的掩膜层102，图形化阻挡层101，直至暴露出衬底100的表面。
其中，剩余阻挡层即图形化的阻挡层101，图形化的阻挡层101中的图形与图形化的掩膜层102一致。
对于基于图形化的掩膜层102，图形化部分厚度的衬底100，形成沟槽200。
参考图5，形成的沟槽200侧壁上附着有颗粒杂质201，颗粒杂质201包括图形化过程中的刻蚀残留物等杂质。
去除图形化的掩膜层102。需要说明的是，去除图形化的掩膜层102这一步骤，可以在形成沟槽200之后执行，也可以在形成图形化的阻挡层101之后执行。由于本实施中，阻挡层101的材料为BACL，第一掩膜层112的材料为 Poly(多晶硅)，BACL与Poly的刻蚀选择比较大，根据BACL中掺杂硼的浓度，BACL与Poly的刻蚀选择比与50：1～300：1，即由于BACL与Poly具有较大的刻蚀选择比，图形化部分厚度的衬底100这一过程，可以基于图形化的阻挡层101为掩膜进行刻蚀。具体地，在一些实施例中，通过控制BACL中掺杂硼的浓度，使BACL与Poly的刻蚀选择比为100：1、150：1、200：1或250：1。
参考图6～图9，形成亲水层202的方法包括：对特征部150的侧壁进行亲水性处理，生成亲水层202；并去除阻挡层101，通入吹扫气体。
其中，亲水性处理和去除阻挡层101的过程可以分布执行，也可以在同一工艺步骤中实现。亲水性处理后生成亲水层202；需要说明的是，在本实施例中，衬底100的材料为硅，相应地，亲水层202的材料为氧化硅，氧化硅亲水性，其表面容易吸附水分子。
在一个例子中，参考图6和图7，即先进行亲水性处理生成亲水层202，在形成亲水层202后，且在进行清洗处理前，还包括：去除阻挡层101，通入吹扫气体。
具体地，对特征部150的侧壁进行亲水性处理，包括：向特征部150的侧壁通入水蒸气和气体载体，在通入水蒸气的过程中，对水蒸气进行等离子体处理。
在一些实施例中，气体载体具体可以为N 2(氮气)、Ar(氩气)或He(氦气)的其中一者，在本示例中，气体载体为Ar(氩气)。通入气体载体的流量为100sccm～5000sccm，具体可以为1000sccm、2000sccm、3000sccm或4000sccm；在本示例中，通入气体载体的流量为2500sccm。
在一些实施例中，等离子体处理的处理功率为1000W～8000W，具体可以为2000W、4000W或6000W；在本示例中，等离子体处理的处理功率为4500W。
在一些实施例中，通入水蒸气的气体流量范围为10sccm～300sccm，具体可以为150sccm、200sccm或250sccm；在本示例中，通入水蒸气的气体流量为155sccm。
若阻挡层101的材料为BACL，继续通入水蒸气作为刻蚀气体以去除阻挡层101，若阻挡层101的材料为ACL、SiO或SiN，去除阻挡层101通入的刻蚀 气体包括：CF 4、C 4F 8、C 4F 6、CHF 3、CH 2F 2或CH 3F中的至少一者。
具体地，在去除阻挡层101的过程中，反应所处的环境压力范围为0mTorr～10000mTorr，具体可以为3000mTorr、6000mTorr或9000mTorr，在本示例中，反应所处的环境压力为5000mTorr，衬底100的温度范围为20℃～100℃，具体可以为40mTorr、60mTorr或80mTorr，在本示例中，衬底100的温度为60℃；水蒸气的温度范围为100℃～250℃，具体可以为130mTorr、170mTorr、200mTorr或230mTorr，在本示例中，水蒸气的温度为175℃。
具体地，衬底100的温度通过托盘进行控制，托盘用于在反应腔室中承载衬底100，通过控制托盘的温度，从而间接控制放置托盘上的衬底100的温度。衬底100的温度范围为20℃～100℃，即托盘的温度范围为20℃～100℃；水蒸气的温度通过气体管道进行控制，气体管道用于向反应腔室中通入与衬底100的反应气体，从而控制气体管道的温度，从而间接控制通入反应腔室中反应气体的温度，在该示例中，即间接控制水蒸气的温度，水蒸气的温度范围为100℃～250℃，即气体管道的温度范围为100℃～250℃；另外，在该示例中，反应腔室的腔壁的温度为100℃～150℃，以放置水蒸气冷凝在反应腔室的腔壁上，具体地，反应腔室的腔壁的温度可以为110℃、120℃、130℃或140℃，在该示例中，反应腔室的腔壁的温度为125℃。
在一些实施例中，通入刻蚀气体的流量范围为10sccm～300sccm，具体可以为150sccm、200sccm或250sccm；在本示例中，通入刻蚀气体的流量为155sccm。
在另一个例子中，参考图8，去除阻挡层101与对特征部150的侧壁进行亲水性处理于同一工艺步骤中实现，即同时对特征部150的侧壁进行亲水性处理且去除阻挡层101，在去除阻挡层101的过程中，产生亲水层202。
具体地，对特征部150的侧壁进行亲水性处理和去除阻挡层101的过程，包括：向特征部150的侧壁通入水蒸气和气体载体，在通入水蒸气的过程中，对水蒸气进行等离子体处理。
在本示例中，通入气体载体的流量为2500sccm；等离子体处理的处理功率为4500W；在本示例中，通入水蒸气的气体流量为155sccm。
该示例是以阻挡层101的材料为BACL的前提下，同时采用水蒸气进行亲水性处理和去除阻挡层101的过程，通入水蒸气的气体流量范围为 10sccm～300sccm，具体可以为150sccm、200sccm或250sccm；在本示例中，通入水蒸气的气体流量为155sccm。
在本示例中，在对特征部150的侧壁进行亲水性处理和去除阻挡层101的过程中，反应所处的环境压力为5000mTorr，衬底100的温度为60℃，水蒸气的温度为175℃。
在又一个例子中，参考图9，先进行亲水性处理生成亲水层202，去除阻挡层101的过程加入到清洗处理的循环过程中同时执行，即在每一轮清洗处理之前去除部分阻挡层101，执行最后一轮清洗处理之前，去除剩余阻挡层101。
参考图10～图13，在生成亲水层202后，对衬底100进行至少一次清洗处理，清洗处理包括：向特征部150的侧壁中通入初始水蒸气203，并进行降温处理，使附着在亲水层202表面的初始水蒸气203液化为水204，水204携带颗粒杂质201流入沟槽200中；进行升温处理，使水气化为水蒸气203，水蒸气203携带颗粒杂质201逸出。
具体地，参考图10，向沟槽200中通入水蒸气203且进行降温处理，水分子附着在沟槽200表面并不断积累，以液态水的形式沿着沟槽200侧壁下滑，并携带沟槽200侧壁的颗粒杂质201流入沟槽200底部，从而实现将沟槽200侧壁的颗粒杂质201转移到沟槽200底部；参考图11，一段时间后，进行升温处理，沟槽200底部的液态水204蒸发成水蒸气203，蒸发的过程中，逸出的水蒸气203携带杂质颗粒201一并逸出，从而完成对沟槽200侧壁杂质的清洗。
具体地，在一些实施例中，降温处理后的温度范围为20℃～60℃，具体可以是30℃、40℃或50℃，在本示例中，降温处理后的温度为20℃；升温处理后的温度范围为60℃～100℃，具体可以是70℃、80℃或90℃，在本示例中，升温处理后的温度为100℃；降温处理的温度变化速率范围为0.5s/℃～1.5s/℃，具体可以是0.8s/℃、1.0s/℃或1.2s/℃，在本示例中，降温处理的温度变化速率为1.0s/℃；升温处理的温度变化速率范围为0.5s/℃～1.5s/℃，具体可以是0.8s/℃、1.0s/℃或1.2s/℃，在本示例中，升温处理的温度变化速率为1.0s/℃。
在一些实施例中，通入初始水蒸气的流量范围为1000sccm～20000sccm，具体地可以为4000sccm、7000sccm、10000sccm、13000sccm或16000sccm，在本示例中，通入初始水蒸气的流量为10000sccm。
另外，在一些实施例中，通入的吹扫气体为N 2(氮气)或者惰性气体，吹扫气体的吹扫时间范围为，具体地可以为20s～60s，具体可以是30s、40s或50s，通入吹扫气体目的在于：清理半导体结构所在反应腔室中，进行亲水性处理和刻蚀阻挡层101的过程中通入的反应气体或反应生成的杂质气体。
参考图10和图12，进行清洗处理后，附着在亲水层202侧壁的颗粒杂质201得到了部分清洗。另外，在一些实施例中，对衬底进行至少一次清洗处理包括：循环执行预设次数的清洗处理，通过循环执行清洗处理的过程，保证对沟槽200侧壁的颗粒杂质的完全清洗。
具体地，预设次数可以为3、5、7等，具体循环次数可以根据具体杂质情况进行设置；需要说明的是，上述预设次数的举例，并不构成对上述各实施例的限定。
对于图9，应用于循环执行预设次数的清洗处理，其中，向沟槽200通入水蒸气之前，清洗后处理还包括：去除部分厚度的阻挡层101，通入吹扫气体；执行最后一次的清洗处理过程中，去除部分厚度的阻挡层101为去除阻挡层101；其中，图9所示的图形化的阻挡层101为经过一次刻蚀处理后的高度，剩余的图形化的阻挡层101还需经过两次刻蚀处理，即在该实例中，清洗处理一共需要执行3轮，即预设次数为3。
在一些实施例中，进行清洗处理之后，去除沟槽200表面由亲水性处理产生的亲水层202。
具体地，去除亲水层202采用化学方法，化学方法采用的化学气体对亲水层202和剩余衬底100的刻蚀选择比大于500：1。采用刻蚀选择比较大的化学气体，在去除亲水层202的过程中，尽可能的避免剩余衬底100被刻蚀。
去除亲水层202采用的化学方法，包括：通入NH 3和HF，并进行第一温度处理；通入N 2，并进行第二温度处理；其中，所述第一温度处理后的温度范围为20℃～40℃，所述第一温度处理的温度范围为100℃～200℃。
此时亲水层202与NH 3和HF发生如下反应：
SiO 2+4HF+4NH 3->SiF 4+2H 2O+4NH 3(1)
SiF 4+2HF+2NH 3->(NH 4) 2SiF 6(2)
其中，在(1)反应中，HF作为反应气体与亲水层202进行反应生成SiF 4，NH 3作为催化剂以加速反应的进行。在(2)反应中，NH 3和HF同时作为反应气体，与第一步反应中生成的SiF4继续反应，生成易挥发的(NH 4) 2SiF 6固体。
在一些实施例中，在通入NH 3(氨气)和HF(氟化氢)的过程中，还需要通入Ar(氩气)作为NH 3和HF的载体，通过融入Ar(氩气)载体，以保证NH 3和HF与亲水层202充分反应；另外，通入Ar作为载气，载气可以防止HF气体冷凝在进气管道中。
具体地，在(1)和(2)反应中，需保证反应物处于第一温度，第一温度即第一温度处理后的温度范围20℃～40℃；在一些实施例中，第一温度可以为25℃、30℃或35℃等，在本示例中，第一温度为30℃；在通入N 2的过程中，需保证反应物处于第二温度，以更好地使(NH 4) 2SiF 6固体升华，通入N 2的目的是：通入N 2作为载气，将挥发的(NH 4) 2SiF 6固体带出，第二温度即第二温度处理后的温度范围100℃～200℃，在一些实施例中，第二温度可以为120℃、140℃、160℃或180℃等，在本实例中，第二温度为150℃。
在对沟槽进行清洗的过程中，由于特征部的表面具有亲水层，亲水层表面极易附着水分子；在清洗过程中，向沟槽中通入水蒸气且进行降温处理，水分子附着在亲水层表面并不断积累，以液态水的形式沿着特征部侧壁的亲水层下滑，并携带亲水层侧壁的颗粒杂质流入相邻特征部之间的间隙中，从而实现将特征部侧壁的颗粒杂质转移到相邻特征部之间的间隙底部；一段时间后，进行升温处理，相邻特征部之间的间隙底部的液态水蒸发成水蒸气，蒸发的过程中，逸出的水蒸气携带杂质颗粒一并逸出，从而完成对特征部侧壁的杂质清洗。通过对水的状态变化进行对特征部侧壁的清洗，减小高深宽比结构在清洗过程中表面张力对结构的影响，从而避免了特征部在清洗过程中发生倾斜的问题。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内；本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种半导体结构的处理方法，包括：
    提供衬底，所述衬底上具有特征部，所述特征部的深宽比大于预设深宽比，所述特征部顶部设置有阻挡层，所述特征部的侧壁设置有亲水层，所述亲水层的侧壁存在颗粒杂质；
    对所述衬底进行至少一次清洗处理，所述清洗处理包括：
    向所述特征部的侧壁通入初始水蒸气，并进行降温处理，使附着在所述亲水层表面的所述初始水蒸气液化为水；
    进行升温处理，使所述水气化为水蒸气，所述水蒸气携带所述颗粒杂质逸出。
  2. 根据权利要求1所述的半导体结构的处理方法，其中，形成所述亲水层的方法包括：对所述特征部的侧壁进行亲水性处理，生成所述亲水层。
  3. 根据权利要求2所述的半导体结构的处理方法，其中，在形成所述亲水层后，且在进行所述清洗处理前，还包括：去除所述阻挡层，通入吹扫气体。
  4. 根据权利要求3所述的半导体结构的处理方法，其中，所述去除所述阻挡层与所述对所述特征部的侧壁进行亲水性处理于同一工艺步骤中实现。
  5. 根据权利要求4所述的半导体结构的处理方法，其中，所述对所述特征部的侧壁进行亲水性处理，包括：
    向所述特征部的侧壁通入所述水蒸气和气体载体；
    在通入所述水蒸气的过程中，对所述水蒸气进行等离子体处理。
  6. 根据权利要求5所述的半导体结构的处理方法，其中，包括：
    通入所述水蒸气的气体流量范围为10sccm～300sccm；
    通入所述气体载体的流量为100sccm～5000sccm。
  7. 根据权利要求5所述的半导体结构的处理方法，其中，在去除所述阻挡层的过程中：
    反应所处环境的压力范围为0mTorr～10000mTorr；
    所述衬底的温度范围为20℃～100℃；
    通入所述水蒸气的温度的范围为100℃～250℃。
  8. 根据权利要求1所述的半导体结构的处理方法，其中，所述预设深宽比不小于10。
  9. 根据权利要求1所述的半导体结构的处理方法，其中，在所述清洗处理过程中：
    通入所述初始水蒸气的流量范围为1000sccm～20000sccm；
    所述降温处理后的温度范围为20℃～60℃；
    所述升温处理后的温度范围为60℃～100℃；
    所述降温处理的温度变化速率范围0.5s/℃～1.5s/℃；
    所述升温处理的温度变化速率范围0.5s/℃～1.5s/℃。
  10. 根据权利要求1所述的半导体结构的处理方法，其中，包括：
    对所述衬底进行至少一次清洗处理，包括：循环执行预设次数的所述清洗处理；
    其中，向所述特征部的侧壁通入水蒸气之前，所述清洗处理还包括：去除部分厚度的所述阻挡层，通入吹扫气体；
    执行最后一次的所述清洗处理过程中，去除部分厚度的所述阻挡层为：去除所述阻挡层。
  11. 根据权利要求1～10任一项所述的半导体结构的处理方法，其中，所述阻挡层为掺杂硼原子的非晶碳层。
  12. 根据权利要求1所述的半导体结构的处理方法，其中，形成所述特征部的方法包括：
    提供所述衬底，在所述衬底的顶部表面形成阻挡层；
    图形化所述阻挡层和部分厚度的所述衬底，形成沟槽，相邻所述沟槽之间的剩余所述衬底构成所述特征部；
    对所述沟槽表面进行亲水性处理，生成所述亲水层。
  13. 根据权利要求12所述的半导体结构的处理方法，其中，所述图形化所述阻挡 层和部分厚度的所述衬底，形成沟槽，包括：
    在所述阻挡层顶部表面形成图形化的掩膜层；
    基于所述图形化的掩膜层，图形化所述阻挡层，直至暴露出所述衬底的表面；
    基于所述图形化的掩膜层，图形化部分厚度的所述衬底，形成所述沟槽；
    去除所述图形化的掩膜层。
  14. 根据权利要求1所述的半导体结构的处理方法，其中，在所述清洗处理后，还包括：去除所述亲水层，所述去除所述亲水层包括：
    通入NH3和HF，并进行第一温度处理；
    通入N2，并进行第二温度处理。
  15. 根据权利要求14所述的半导体结构的处理方法，其中，所述第一温度处理后的温度范围为20℃～40℃，所述第一温度处理的温度范围为100℃～200℃。
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