WO2021261520A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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WO2021261520A1
WO2021261520A1 PCT/JP2021/023792 JP2021023792W WO2021261520A1 WO 2021261520 A1 WO2021261520 A1 WO 2021261520A1 JP 2021023792 W JP2021023792 W JP 2021023792W WO 2021261520 A1 WO2021261520 A1 WO 2021261520A1
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Prior art keywords
metal layer
layer
lower metal
semiconductor substrate
semiconductor device
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English (en)
French (fr)
Japanese (ja)
Inventor
和夫 赤松
剛 藤原
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/153—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Definitions

  • the present disclosure relates to a semiconductor device in which electrodes connected to the semiconductor substrate are formed on the semiconductor substrate, and a method for manufacturing the same.
  • Patent Document 1 a semiconductor device in which an electrode connected to a semiconductor substrate is formed on a semiconductor substrate.
  • a MOSFET abbreviation of Metal Oxide Semiconductor Field Effect Transistor
  • the semiconductor device is provided with a first electrode connected to the channel layer and the source layer on one surface side of the semiconductor substrate, and a second electrode connected to the drain layer on the other surface side of the semiconductor substrate. ..
  • the first electrode side is connected to the connecting member via solder or the like. Therefore, an electroless nickel plating film or the like having high bondability with solder is arranged on the first electrode.
  • the first electrode is made of aluminum or an aluminum alloy in which an element is added to aluminum.
  • the first electrode when the electroless nickel plating film is arranged on the first electrode, the first electrode may be zincated in order to improve the adhesion between the electroless nickel plating film and the first electrode.
  • the first electrode when the first electrode is made of aluminum or an aluminum alloy, the hydroxyl group contained in the alkaline solution during the zincating treatment may react with the first electrode to erode the first electrode. When this erosion is large, the adhesion between the electroless nickel plating film and the first electrode may be low, and the interface strength between the electroless nickel plating film and the first electrode may be low.
  • An object of the present disclosure is to provide a semiconductor device capable of suppressing an increase in electrode erosion during a zincating process and a method for manufacturing the same.
  • the semiconductor device comprises a semiconductor substrate and an electrode arranged on the semiconductor substrate, and the electrodes are a lower metal layer arranged on the semiconductor substrate side and a lower metal layer. It has an upper metal layer arranged in and an intermediate layer arranged between the lower metal layer and the upper metal layer, and the lower metal layer and the upper metal layer have aluminum or an element added to the aluminum. It is made of an aluminum alloy, and the intermediate layer is made of a material that is less likely to react with hydroxyl groups than the upper metal layer and the lower metal layer.
  • the intermediate layer is composed of a material that does not easily react with hydroxyl groups, even if the upper metal layer is eroded when the zincate treatment is performed, the extension of the erosion is inhibited by the intermediate layer. Therefore, it is possible to suppress the increase in erosion. Therefore, when the electroless nickel plating film is subsequently formed, it is possible to suppress a decrease in the interfacial strength between the electroless nickel plating film and the electrode.
  • the method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having an electrode electrically connected to the semiconductor substrate, wherein the semiconductor substrate is prepared and the metal substrate is on the semiconductor substrate.
  • the lower metal layer is arranged on the semiconductor substrate
  • the intermediate layer is arranged on the lower metal layer
  • the upper metal layer is arranged on the intermediate layer.
  • the lower metal layer and the upper metal layer composed of aluminum or an aluminum alloy in which an element is added to aluminum are arranged and intermediate.
  • an intermediate layer made of a material that is less likely to react with the hydroxyl group than the upper metal layer and the lower metal layer is arranged.
  • the intermediate layer is composed of a material that does not easily react with hydroxyl groups. Therefore, when the zincate treatment is performed, it is possible to suppress the increase in erosion of the electrodes. Therefore, it is possible to manufacture a semiconductor device capable of suppressing a decrease in the interfacial strength between the electroless nickel plating film and the electrode when the electroless nickel plating film is subsequently formed.
  • the semiconductor device includes a semiconductor substrate 10 having a drain layer 11 composed of an n + type silicon (hereinafter referred to as Si) substrate.
  • An n- type drift layer 12 having a lower impurity concentration than the drain layer 11 is arranged on the drain layer 11.
  • a p-type channel layer 13 having a higher impurity concentration than the drift layer 12 is arranged on the drift layer 12.
  • An n-type source layer 14 having a higher impurity concentration than the drift layer 12 is formed on the surface layer of the channel layer 13.
  • a contact trench 15 is formed in the semiconductor substrate 10 so as to penetrate the source layer 14 and reach the channel layer 13. Therefore, the channel layer 13 is exposed at the bottom surface of the contact trench 15.
  • a p + type channel layer contact region 13a to be a contact is formed in a portion of the channel layer 13 exposed from the contact trench 15.
  • an n + type contact region 14a for the source layer to be a contact is formed in the portion of the source layer 14 exposed from the side surface of the contact trench 15.
  • a plurality of trenches 16 are formed between the channel layer 13 and the source layer 14.
  • Each trench 16 is formed in stripes at equal intervals along one of the surface directions of one surface 10a of the semiconductor substrate 10 (that is, the depth direction of the middle paper surface in FIG. 1), and penetrates the channel layer 13. It is formed so as to reach the drift layer 12.
  • the plurality of trenches 16 may have an annular structure by being routed at the tip end portion.
  • each trench 16 is embedded with a gate insulating film 17 formed so as to cover the wall surface of each trench 16 and a gate electrode 18 formed of polysilicon or the like formed on the gate insulating film 17. It has been. This constitutes a trench gate structure.
  • An interlayer insulating film 19 is formed on one surface 10a on the channel layer 13 side of the semiconductor substrate 10, and a contact hole 19a communicating with the contact trench 15 is formed in the interlayer insulating film 19. Then, on the interlayer insulating film 19, the contact hole 19a formed in the interlayer insulating film 19 and the contact trench 15 formed in the semiconductor substrate 10 are electrically connected to the source layer contact region 14a and the channel layer contact region 13a.
  • the upper electrode 20 to be connected is arranged. The configuration of the upper electrode 20 will be specifically described later.
  • a drain electrode 21 electrically connected to the drain layer 11 is formed on the other surface 10b side of the semiconductor substrate 10.
  • n-type, n - type, and n + type correspond to the first conductive type
  • p-type and p + type correspond to the second conductive type.
  • the semiconductor substrate 10 includes the drain layer 11, the drift layer 12, the channel layer 13, the source layer 14, and the like.
  • the configuration of the upper electrode 20 of the present embodiment will be specifically described.
  • the upper electrode 20 of the present embodiment has an embedded portion 200 arranged in the contact hole 19a and the contact trench 15 and connected to the contact region 13a for the channel layer and the contact region 14a for the source layer.
  • the upper electrode 20 has a main portion 210 arranged on the interlayer insulating film 19 and connected to the embedded portion 200.
  • the embedded portion 200 is composed of a tungsten plug or the like.
  • a base layer for improving the embedding property of tungsten may be formed on the wall surface of the contact hole 19a or the contact trench 15.
  • the base layer is made of, for example, titanium, titanium nitride, or the like.
  • the main portion 210 is configured by laminating a barrier metal layer 211, a lower metal layer 212, an intermediate layer 213, and an upper metal layer 214.
  • the barrier metal layer 211 is formed by laminating, for example, titanium nitride and titanium.
  • the lower metal layer 212 and the upper metal layer 214 are made of aluminum or an aluminum alloy in which an element is added to aluminum.
  • the aluminum alloy include AlSi, AlCu, AlSiCu and the like.
  • the intermediate layer 213 is made of a material that is less likely to react with hydroxyl groups than the lower metal layer 212 and the upper metal layer 214, and in this embodiment, it is made of, for example, an aluminum oxide film (Al 2 O 3 ) or the like. In the present embodiment, the intermediate layer 213 is formed on the entire surface between the lower metal layer 212 and the upper metal layer 214, and the thickness is substantially constant along the surface direction of the semiconductor substrate 10. ..
  • the intermediate layer 213 is arranged on the upper metal layer 214 side of the center in the stacking direction of the lower metal layer 212, the intermediate layer 213, and the upper metal layer 214 (hereinafter, also simply referred to as the stacking direction). Has been done.
  • the intermediate layer 213 is an extremely thin film having a size of about 2 to 10 nm.
  • an electroless nickel plating film is formed on the upper electrode 20 after the upper electrode 20 is zincated, and solder or the like is arranged on the electroless nickel plating film to electrically contact an external element. Connected to.
  • the upper electrode 20 of the present embodiment is configured by laminating the lower metal layer 212, the intermediate layer 213, and the upper metal layer 214.
  • the intermediate layer 213 is made of a material that is less likely to react with the hydroxyl group than the upper metal layer 214 and the lower metal layer 212. Therefore, as shown in FIG. 3, even if the upper metal layer 214 is eroded and the pores 214a are formed in the upper metal layer 214 when the zincate treatment is performed, the pores 214a (that is, erosion) are formed. Extension is inhibited by intermediate layer 213. Therefore, it is possible to suppress the increase in erosion. Therefore, when the electroless nickel plating film 30 is subsequently formed, it is possible to suppress a decrease in the bonding strength between the electroless nickel plating film 30 and the upper electrode 20.
  • a channel layer 13, a source layer 14, an interlayer insulating film 19, and the like are formed, and an embedded portion 200 of the upper electrodes 20 is formed.
  • titanium nitride, titanium, etc. are formed in order to form the barrier metal layer 211 by a CVD (abbreviation of Chemical Vapor Deposition) method or the like.
  • the semiconductor substrate 10 is arranged in the sputtering apparatus, and the lower metal layer 212 is formed by the sputtering method.
  • the semiconductor substrate 10 is taken out from the sputtering apparatus and the semiconductor substrate 10 is exposed to the atmosphere to form an intermediate layer 213 composed of an aluminum oxide film.
  • the semiconductor substrate 10 is vibrated by ultrasonic waves, and the scrubber cleaning is performed by injecting ultrapure water onto the surface of the lower metal layer 212 to perform brush cleaning. This makes it possible to remove foreign substances and whiskers that may be contained in the surface of the lower metal layer 212 and the intermediate layer 213.
  • the semiconductor substrate 10 is placed in the sputtering apparatus again, and the upper metal layer 214 is formed by the sputtering method. As described above, the upper electrode 20 is configured.
  • the upper electrode 20 is configured by laminating a lower metal layer 212, an intermediate layer 213, and an upper metal layer 214.
  • the intermediate layer 213 is made of a material that is less likely to react with the hydroxyl group than the lower metal layer 212 and the upper metal layer 214. Therefore, even if the upper metal layer 214 is eroded during the ginkating treatment, the extension of the erosion is inhibited by the intermediate layer 213. Therefore, it is possible to suppress the increase in erosion. Therefore, when the electroless nickel plating film 30 is subsequently formed, it is possible to prevent the interface strength between the electroless nickel plating film 30 and the upper electrode 20 from decreasing.
  • the intermediate layer 213 is arranged on the upper metal layer 214 side of the upper electrode 20 with respect to the center in the stacking direction. Therefore, as compared with the case where the intermediate layer 213 is arranged on the lower metal layer 212 side of the upper electrode 20 in the stacking direction, the erosion is extended when the upper metal layer 214 is eroded. It becomes possible to inhibit at an early stage. Therefore, it is possible to suppress the increase in erosion.
  • the intermediate layer 213 is formed by exposing it to the atmosphere, it is easily manufactured. Further, when forming the intermediate layer 213, scrubber cleaning is performed. Therefore, foreign matter and whiskers that may be contained in the surface of the lower metal layer 212 and the intermediate layer 213 can be removed.
  • the gate electrode 18 may have a double gate structure having a lower layer electrode and an upper layer electrode along the thickness direction of the semiconductor substrate 10.
  • the lower layer electrode is, for example, a shield electrode connected to a source electrode or the like
  • the upper layer electrode is a gate electrode connected to a gate drive circuit or the like.
  • the intermediate layer 213 does not have to be an aluminum oxide film.
  • the intermediate layer 213 may be configured by laminating a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN).
  • SiO 2 silicon oxide film
  • SiN silicon nitride film
  • the silicon oxide film and the silicon nitride film may be laminated in order by the CVD method or the like to form the intermediate layer 213.
  • the intermediate layer 213 may be composed of one of the silicon oxide film and the silicon nitride film.
  • the intermediate layer 213 may be made of an aluminum nitride film or the like.
  • the intermediate layer 213 is the lower metal layer 212 and the upper layer. It may be arranged at least in a part between the metal layer 214 and the metal layer 214. Even in such a semiconductor device, in the portion where the intermediate layer 213 is formed, the extension of erosion can be suppressed when the zinge treatment is performed, so that the same effect as that of the first embodiment can be obtained. Further, the intermediate layer 213 does not have to have a constant thickness along the plane direction of the semiconductor substrate 10.
  • the semiconductor device may have a planar gate structure in which the gate electrode 18 is arranged on the semiconductor substrate 10 instead of the trench gate structure.
  • a MOSFET having an n-channel type trench gate structure in which the first conductive type is n-type and the second conductive type is p-type has been described as an example of a semiconductor device.
  • a semiconductor device having another structure for example, a MOSFET having a p-channel type trench gate structure in which the conductive type of each component is inverted with respect to the n-channel type may be used.
  • the semiconductor device may have a configuration in which an IGBT having a similar structure is formed in addition to the MOSFET.
  • the semiconductor device may be a semiconductor device in which a diode or the like is formed.

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
PCT/JP2021/023792 2020-06-26 2021-06-23 半導体装置およびその製造方法 Ceased WO2021261520A1 (ja)

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JP2020110887A JP7447703B2 (ja) 2020-06-26 2020-06-26 半導体装置およびその製造方法

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Citations (4)

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JPS61127149A (ja) * 1984-11-26 1986-06-14 Hitachi Ltd 薄膜アルミニウム配線基板の製造方法とその製造装置
JP2000150653A (ja) * 1998-09-04 2000-05-30 Seiko Epson Corp 半導体装置の製造方法
JP2017135283A (ja) * 2016-01-28 2017-08-03 ローム株式会社 半導体装置および半導体装置の製造方法
JP2019040975A (ja) * 2017-08-24 2019-03-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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DE69625265T2 (de) * 1995-03-28 2003-09-04 Texas Instruments Inc., Dallas Halbleiterstrukturen
JP3645144B2 (ja) * 2000-02-24 2005-05-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2007266483A (ja) 2006-03-29 2007-10-11 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP4538490B2 (ja) 2007-11-26 2010-09-08 上村工業株式会社 アルミニウム又はアルミニウム合金上の金属置換処理液及びこれを用いた表面処理方法
JP6579989B2 (ja) 2016-04-05 2019-09-25 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2018064026A (ja) 2016-10-12 2018-04-19 富士電機株式会社 半導体装置
JP2019192687A (ja) 2018-04-19 2019-10-31 株式会社豊田中央研究所 半導体装置および半導体装置の製造方法
JP6969586B2 (ja) * 2019-04-23 2021-11-24 株式会社デンソー 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61127149A (ja) * 1984-11-26 1986-06-14 Hitachi Ltd 薄膜アルミニウム配線基板の製造方法とその製造装置
JP2000150653A (ja) * 1998-09-04 2000-05-30 Seiko Epson Corp 半導体装置の製造方法
JP2017135283A (ja) * 2016-01-28 2017-08-03 ローム株式会社 半導体装置および半導体装置の製造方法
JP2019040975A (ja) * 2017-08-24 2019-03-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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