WO2021254204A1 - 电容器结构及其制备方法 - Google Patents

电容器结构及其制备方法 Download PDF

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Publication number
WO2021254204A1
WO2021254204A1 PCT/CN2021/098706 CN2021098706W WO2021254204A1 WO 2021254204 A1 WO2021254204 A1 WO 2021254204A1 CN 2021098706 W CN2021098706 W CN 2021098706W WO 2021254204 A1 WO2021254204 A1 WO 2021254204A1
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Prior art keywords
conductive
layer
capacitor structure
dielectric layer
structure according
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PCT/CN2021/098706
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English (en)
French (fr)
Inventor
夏军
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长鑫存储技术有限公司
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Priority to US17/398,157 priority Critical patent/US11877432B2/en
Publication of WO2021254204A1 publication Critical patent/WO2021254204A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • This application relates to the field of integrated circuits, and in particular to a capacitor structure and a manufacturing method thereof.
  • DRAM Dynamic Random Access Memory
  • the DRAM In the DRAM manufacturing process below 20 nanometers (nm), the DRAM mostly adopts a stacked capacitor structure, and the capacitor is a vertical cylindrical shape with a high aspect ratio.
  • FIG. 1A is a schematic cross-sectional view of a cylindrical double-sided capacitor in a DRAM memory in the related art
  • FIG. 1B is a partial top view along line AA in FIG. 1A.
  • a bottom electrode 10 is formed on the bottom and sidewalls, the bottom electrode 10 is in contact with the bottom plate 14, a high-k dielectric material is deposited in the deep hole as the electrode dielectric layer 11, and the upper electrode 12 is formed on the electrode dielectric layer 11.
  • the upper electrode 12 is covered with an upper electrode plate 13.
  • the embodiments of the present application provide a capacitor structure and a manufacturing method thereof, which can increase the capacitance of the capacitor structure.
  • the embodiment of the present application provides a method for preparing a capacitor structure, including the following steps: providing a substrate, the substrate including conductive contact regions and insulating regions arranged at intervals; forming a stack on the substrate, the stack The layer includes a plurality of units stacked and a main dielectric layer located between two adjacent units; each of the units includes a conductive layer, the main dielectric layer and a sacrificial layer; and a plurality of layers penetrating the laminated layer are formed
  • a first via hole corresponds to the conductive contact area and exposes a part of the upper surface of the conductive contact area; part of the sacrificial layer on the sidewall of the first via hole is removed so as to A first groove is formed in the area corresponding to the sacrificial layer on the sidewall of the first via hole; a first supplementary dielectric layer is formed in the first groove;
  • a radius is set to form a plurality of second via holes penetrating through the stack.
  • the second via holes surround the conductive pillar one round, and the second via holes correspond to the insulating region and expose the Part of the upper surface of the insulating region, the conductive pillar and the conductive layer connected to the conductive pillar serve as a pillar-shaped lower electrode with a first pin; part of the conductive layer on the sidewall of the second via is removed so as to A second groove is formed in the area corresponding to the conductive layer on the sidewall of the second via hole; a second supplementary dielectric layer is formed in the second groove, the main dielectric layer, the first supplementary dielectric layer and the The second supplementary dielectric layer covers the bottom electrode; removes all the sacrificial layers on the sidewalls of the second via hole; fills the second via hole with a conductive material to form a ring-shaped top electrode with a second pin tooth .
  • the uppermost layer of the stack is a sacrificial layer; when removing part of the sacrificial layer on the sidewall of the first via hole, the sacrificial layer on the uppermost layer is removed to expose the sacrificial layer The main dielectric layer below the layer.
  • the forming a first supplementary dielectric layer in the first groove includes: filling a dielectric material in the first via hole; forming a dielectric material penetrating through the dielectric material A through hole, the through hole is coaxial with the first via, and the diameter of the through hole is greater than or equal to the diameter of the first via, and the retained dielectric material forms the first supplement Dielectric layer.
  • the filling a conductive material in the first via hole to form a conductive pillar includes: filling the conductive material in the first via hole, and the conductive material is filled with the conductive material.
  • the first via hole covers the upper surface of the main dielectric layer; part of the conductive material is removed to expose the upper surface of the main dielectric layer to form the conductive column, and the upper surface of the conductive column is connected to The conductive layer under the main dielectric layer is flush.
  • the method further includes: depositing a dielectric material, and the dielectric material is filled at least above the conductive pillar.
  • the dielectric material is further covered on the main dielectric layer, and after the dielectric material is deposited, the dielectric material is planarized.
  • the forming a second supplementary dielectric layer in the second groove includes: filling a dielectric material in the second via hole; forming a dielectric material penetrating through the dielectric material An annular through hole, the through hole is coaxial with the second via, and the width of the through hole is greater than or equal to the width of the second via, and the retained dielectric material forms the second Supplement the dielectric layer.
  • the conductive material when the second via hole is filled with a conductive material to form a ring-shaped upper electrode with a second spigot, covers the upper surface of the laminate to form a conductive connection Floor.
  • the method further includes: forming an upper electrode on the upper surface of the conductive connection layer plate.
  • An embodiment of the present application also provides a capacitor structure, including: a columnar bottom electrode, including a conductive column and a plurality of first pin teeth, each of the first pin teeth is connected to the outer surface of the conductive column and is perpendicular to the conductive column On the side of the column, a plurality of the first toothings are arranged in sequence along the axial direction of the conductive column; the ring-shaped upper electrode includes a ring-shaped body and a plurality of second toothings, and the second toothings are perpendicular to the ring-shaped body The axial direction of the ring body penetrates the annular body, and a plurality of the second toothings are arranged in sequence along the axial direction of the annular body, wherein the annular body is arranged around the columnar lower electrode, and the first toothing Alternately arranged with the second toothing; a dielectric layer is arranged between the columnar lower electrode and the ring-shaped upper electrode.
  • the first tooth and the second tooth partly overlap.
  • the first insert tooth makes a circle around the side surface of the conductive column.
  • the second toothing makes a circle around the side surface of the annular body.
  • the capacitor structure is disposed on a substrate, and the substrate includes conductive contact regions and insulating regions spaced apart, and the lower surface of the columnar lower electrode is connected to the conductive contact, so The lower surface of the ring-shaped upper electrode is connected to the insulating area.
  • the capacitor structure further includes a conductive connection layer disposed on the upper surface of the capacitor structure; the conductive connection layer is connected to the upper surface of the ring-shaped upper electrode, and the conductive connection layer The dielectric layer is located between the upper surface of the columnar lower electrode.
  • the capacitor structure further includes an upper electrode plate, and the upper electrode plate is disposed on the conductive connection layer.
  • the end surface of the columnar lower electrode is composed of the end surface of the conductive column and the surface of the first tooth.
  • the end surface of the ring-shaped upper electrode is constituted by the end surface of the ring-shaped main body.
  • the axis of the conductive column is taken as the axis of symmetry
  • the first toothing is arranged symmetrically
  • the axis of the ring body is taken as the axis of symmetry
  • the second toothing is arranged symmetrically .
  • the axial direction of the conductive column coincides with the axial direction of the annular body.
  • the advantages of the embodiments of the present application are that the upper electrode and the lower electrode of the capacitor structure have a larger cross area, the capacitance of the capacitor structure is increased, and the shape error of the upper electrode and the lower electrode is small, which meets the design requirements.
  • FIG. 1A is a schematic cross-sectional view of a cylindrical double-sided capacitor in a DRAM memory in the related art
  • Fig. 1B is a schematic partial top view along the line A-A in Fig. 1A;
  • FIG. 2 is a schematic diagram of steps of an embodiment of a method for manufacturing a capacitor structure according to an embodiment of the present application
  • 3-25 are process flow diagrams of an embodiment of a method for manufacturing a capacitor structure according to an embodiment of the present application.
  • Figure 26 is a partial plan view at the line A-A in Figure 25;
  • Figure 27 is a partial plan view at line B-B in Figure 25;
  • Figure 28 is a partial plan view at the line C-C in Figure 25;
  • Fig. 29 is a partial plan view at the line D-D in Fig. 25;
  • FIG. 2 is a schematic diagram of steps of an embodiment of a method for preparing a capacitor structure according to an embodiment of the present application
  • FIGS. 3-25 are process flow diagrams of an embodiment of a method for preparing a capacitor structure according to an embodiment of the present application.
  • the manufacturing method of the capacitor structure in the embodiment of the present application includes the following steps:
  • a substrate 300 is provided.
  • the substrate 300 includes conductive contact regions 301 and insulating regions 302 arranged at intervals.
  • a conductive contact pad may be formed in the substrate 300, the conductive contact pad is used as the conductive contact area 301, and the area where the conductive contact pad is not provided is used as the insulating area 302.
  • a laminated layer is formed on the substrate 300, and the laminated layer includes a plurality of cells 310 superimposed and a main dielectric layer 310B disposed between two adjacent cells, each
  • the cell 310 includes a conductive layer 310A, a main dielectric layer 310B, and a sacrificial layer 310C, and a main dielectric layer 310B is also formed between the cells 310.
  • the conductive layer 310A, the main dielectric layer 310B, and the sacrificial layer 310C are sequentially arranged.
  • the growth unit 310 can be repeated on the same machine.
  • the stack includes at least two of the units.
  • step S22 and FIG. 8 Please refer to step S22 and FIG. 8 to form a plurality of first via holes 320 penetrating the stack.
  • Each first via 320 corresponds to the conductive contact area 301 and exposes a portion of the conductive contact area 301 Upper surface.
  • two first via holes 302 are formed.
  • at least one first via hole penetrating the stack is formed.
  • the first via 320 is formed by photolithography and etching methods. described as follows:
  • a hard mask layer 400 and a photoresist layer 410 are formed on the stack.
  • the photoresist layer 410 is patterned to form a window 410A, and the window 410A is used to The pattern is transferred to the hard mask layer 400.
  • a dry etching process can be used to transfer the pattern to the hard mask layer 400, and the dry etching process includes a plasma etching process, a reactive ion etching process or an ion milling process.
  • FIG. 8 is a cross-sectional view
  • FIG. 9 is a partial top view at the line AA in FIG.
  • the first via 320 penetrates the stack.
  • the stack is etched with a high aspect ratio, and it is required that the etching rate of the etching material on the stack is greater than the etching rate of the hard mask layer 400 and the substrate 300.
  • the photoresist layer 410 and the hard mask layer 400 may be consumed. If the first via 320 is formed, the photoresist layer 410 and the hard mask layer 400 may be consumed. If the hard mask layer 400 still remains, a wet etching process is used to remove the photoresist layer 410 and the hard mask layer 400.
  • the diameter of the first via 320 is the same as the diameter of the conductive pillar 340 (shown in FIG. 14) that needs to be formed later, and the axis of the two adjacent first vias 320 is the same.
  • the distance between the two adjacent conductive pillars 340 is equal to the distance between the axial centers of the two adjacent conductive pillars 340.
  • the diameter of the first via 320 is smaller than the diameter of the conductive pillar 340 to be formed later.
  • step S23 and FIG. 10 Please refer to step S23 and FIG. 10 to remove part of the sacrificial layer 310C on the sidewall of the first via hole 320 to form a first groove 320A in the area corresponding to the sacrificial layer 310C on the sidewall of the first via hole 320.
  • the sacrificial layer 310C can be removed by a wet etching process.
  • the sacrificial layer 310C In the direction extending along the sacrificial layer 310C, the sacrificial layer 310C is partially removed, a part of the surface of the main dielectric layer 310B adjacent to the sacrificial layer 310C is exposed, and the two adjacent layers of the main dielectric The layer 310B and the sacrificial layer 310C enclose the first groove 320A.
  • the uppermost layer of the stack is the sacrificial layer 310C
  • the uppermost sacrificial layer 310C is also removed at the same time , The main dielectric layer 310B under the sacrificial layer 310C is exposed.
  • the uppermost sacrificial layer 310C may not be removed.
  • a first supplementary dielectric layer 330 is formed in the first groove 320A.
  • the first supplementary dielectric layer 330 fills the first groove 320A.
  • the material of the first supplementary dielectric layer 330 is the same as the material of the main dielectric layer 310B.
  • the embodiment of the present application lists a method of forming the first supplementary dielectric layer 330 in the first groove 320A. described as follows:
  • a dielectric material 500 is filled in the first via 320.
  • the dielectric material 500 fills the first via 320. It is understandable that due to process reasons, during the process of filling the dielectric material 500, the exposed main dielectric layer 310B of the uppermost layer is also covered by the dielectric material. After the dielectric material 500 is filled, The surface of the main dielectric layer 310B is chemically mechanically polished to remove the dielectric material on the surface of the main dielectric layer 310B. In some embodiments, the material of the main dielectric layer 310B and the dielectric material are the same material.
  • a through hole 501 penetrating the dielectric material 500 After the through hole 501 is formed, the dielectric material in the first groove 320A is retained, and the dielectric material in other regions is removed.
  • the dielectric material located in the first groove 320A serves as the first supplementary dielectric layer 330.
  • the sides of the conductive layer 310A and the main dielectric layer 310B are exposed to the sidewall of the through hole 501.
  • the side surface of the sacrificial layer 310C is covered by the first supplementary dielectric layer 330 and is not exposed to the sidewall of the through hole 501.
  • the through hole 501 is coaxial with the first through hole 320, and the diameter of the through hole 501 is greater than or equal to the diameter of the first through hole 320.
  • the diameters of the pillars 340 are the same.
  • a conductive material is filled in the first via 320 to form a conductive pillar 340, the conductive pillar 340 is connected to the conductive layer 310A, and the conductive pillar 340 is connected to the conductive contact area 301 connection.
  • the conductive material forming the conductive pillar 340 is the same as the material of the conductive layer 310A.
  • the embodiment of the present application provides a method for forming the conductive pillar 340, which is described as follows:
  • a conductive material 600 is filled in the first via 320, and the conductive material 600 fills the first via 320 and covers the upper surface of the main dielectric layer 310B.
  • a portion of the conductive material 600 is removed to expose the upper surface of the main dielectric layer 310B to form the conductive pillars 340, and the upper surface of the conductive pillars 340 and the lower surface of the main dielectric layer 310B
  • the conductive layer 310A is flush.
  • the conductive material 600 is etched back to form the conductive pillar 340.
  • the embodiment of the present application may further include the following steps: Referring to FIG. 15, after forming the conductive pillars 340, a dielectric material is deposited on the main dielectric layer 310B, and the dielectric The material is filled at least above the conductive pillar. In the embodiment of the present application, the dielectric material fills the gap between the uppermost main dielectric layer 310B and the conductive pillar 340 in the corresponding area.
  • the surface of the main dielectric layer 310B will also be covered with dielectric material, and a process such as chemical mechanical polishing can be used to remove the dielectric material on the surface of the main dielectric layer 310B, and make the The surface of the main dielectric layer 310B is flattened.
  • a plurality of second vias 350 penetrating the stack are formed at a predetermined radius.
  • the second via hole 350 surrounds the conductive pillar 340 one round, and the second via hole 350 corresponds to the insulating region 302 and exposes a part of the upper surface of the insulating region 302.
  • the conductive pillar 340 and the conductive layer 310A connected to the conductive pillar 340 serve as a columnar lower electrode 360 having a first pin 361 (marked in FIG. 25), wherein the conductive layer 310A serves as the first pin ⁇ 361.
  • at least one second via hole penetrating the stack is formed.
  • the embodiment of the present application provides a method of forming the second via 350. described as follows:
  • a hard mask layer 700 and a photoresist layer 710 are formed on the uppermost main dielectric layer 310B.
  • a dry etching process can be used to transfer the pattern to the hard mask layer 700.
  • the pattern transferred to the hard mask layer 700 is at a predetermined radius A ring pattern surrounding the conductive pillar 340 and corresponding to the insulating region 302.
  • the stack is etched to form a second via 350 penetrating the stack.
  • the shape of the second via hole 350 formed in this step is the same as the shape of the window 710A in FIG. 18.
  • high aspect ratio etching is performed on the stack, and it is required that the etching rate of the etching material to the stack is greater than the etching rate of the hard mask layer 700 and the substrate 300.
  • the photoresist layer 710 and the hard mask layer 700 may be consumed. If the second via hole 350 is formed, the photoresist layer 710 and the hard mask layer 700 may be consumed. If the hard mask layer 700 still remains, a wet etching process can be used to remove the photoresist layer 710 and the hard mask layer 700.
  • the axis of the second via hole 350 coincides with the axis of the annular body of the upper electrode to be formed later, and the width of the second via hole 350 is the same as the width of the annular body. In other implementation manners of the embodiment of the present application, the width of the second via hole 350 is smaller than the width of the annular body.
  • step S27 and FIG. 20 part of the conductive layer 310A on the sidewall of the second via hole 350 is removed to form a second groove 350A in the region corresponding to the conductive layer 310A on the sidewall of the second via hole 350.
  • the conductive layer 310A can be removed by a wet etching process, and the main dielectric layer 310B and the sacrificial layer 310C are not removed.
  • the second groove 350A is surrounded by an adjacent main dielectric layer 310B and a conductive layer 310A located between the two.
  • the width of the conductive layer 310A removed (along the extending direction of the conductive layer 310A, as shown in the X direction in FIG. 20) is smaller than the width of the sacrificial layer 310C, so as to be used in subsequent steps.
  • a first tooth 361 and a second tooth 382 are formed in an overlapping arrangement.
  • a second supplementary dielectric layer 331 is formed in the second groove 350A.
  • the main dielectric layer 310B, the first supplementary dielectric layer 330, and the second supplementary dielectric layer 331 include Cover the bottom electrode 360.
  • the second supplementary dielectric layer 331 fills the second groove 350A, so that the main dielectric layer 310B, the first supplementary dielectric layer 330, and the second supplementary dielectric layer 331 form a closed dielectric layer 370, so that the lower electrode 360 is electrically insulated from the subsequently formed upper electrode.
  • the material of the second supplementary dielectric layer 331 is the same as the material of the main dielectric layer 310B.
  • the embodiment of the present application also provides a method for forming the second supplementary dielectric layer 331. described as follows:
  • a dielectric material 800 is filled in the second via hole 350.
  • the dielectric material 800 fills the second via hole 350. It is understandable that, due to process reasons, during the process of filling the dielectric material 800, the exposed main dielectric layer 310B of the uppermost layer is also covered by the dielectric material. After the dielectric material 800 is filled, The surface of the main dielectric layer 310B is chemically mechanically polished to remove the dielectric material on the surface of the main dielectric layer 310B. In some embodiments, the material of the main dielectric layer 310B and the dielectric material are the same material.
  • an annular through hole 701 penetrating the dielectric material 800 is formed.
  • the dielectric material in the second groove 350A is retained, and the dielectric material in other regions is removed.
  • the dielectric material located in the second groove 350A serves as the second supplementary dielectric layer 331.
  • the sides of the main dielectric layer 310B, the sacrificial layer 310C, and the second supplementary dielectric layer 331 are exposed to the sidewalls of the through hole 701, and the conductive layer 310A
  • the side surface of is covered by the second supplementary dielectric layer 331 so as not to be exposed to the sidewall of the through hole 701.
  • the through hole 701 is coaxial with the second through hole 350, and the width of the through hole 701 is greater than or equal to the width of the second through hole 350.
  • the width of the annular body of the electrode is the same.
  • step S29 and FIG. 23 Please refer to step S29 and FIG. 23 to remove all the sacrificial layer 310C on the sidewall of the second via hole 350.
  • the sacrificial layer 310C can be removed by a wet etching process, and the area where the sacrificial layer 310C is located can be used as the second toothing area of the upper electrode.
  • a conductive material is filled in the second via hole 350 to form a ring-shaped upper electrode 380 with a second insert tooth 382.
  • the conductive material filled in the original sacrificial layer region forms the second pinion 382
  • the conductive material filled in the second via hole 350 forms the ring-shaped body 381 of the ring-shaped upper electrode.
  • step S30 when the second via hole is filled with a conductive material to form a ring-shaped upper electrode with a second spigot, the conductive material also covers the upper surface of the laminate to A conductive connection layer 383 is formed.
  • an upper electrode plate 390 is formed on the upper surface of the conductive connection layer 383.
  • the conductive connection layer 383 serves as a connection layer between the upper electrode 380 and the upper electrode plate 390.
  • first tooth 361 and the second tooth 382 may overlap. Wherein, the overlap amount of the first tooth 361 and the second tooth 382 can be controlled by controlling the depths of the first groove 320A and the second groove 350A.
  • the cross area of the upper electrode and the lower electrode of the capacitor structure prepared by the preparation method provided by the embodiment of the present application increases, the capacitance of the capacitor structure increases, and the shape error of the upper electrode and the lower electrode is small, which meets the design requirements.
  • the embodiment of the present application also provides a capacitor structure prepared by the above-mentioned preparation method. Please refer to Figure 25, Figure 26, Figure 27, Figure 28 and Figure 29, where Figure 26 is a partial plan view at the AA line in Figure 25, Figure 27 is a partial plan view at the BB line in Figure 25, and Figure 28 is 25 is a partial top view at the CC line, and FIG. 29 is a partial top view at the DD line in FIG. 25.
  • the capacitor structure includes a columnar lower electrode 360, a ring-shaped upper electrode 380, and a dielectric layer 370. Wherein, the capacitor structure is arranged on the substrate 300.
  • the substrate 300 includes conductive contact regions 301 and insulating regions 302 arranged at intervals.
  • the lower surface of the columnar lower electrode 360 is connected to the conductive contact area 301, and the lower surface of the ring-shaped upper electrode 380 is connected to the insulating area 302.
  • the columnar bottom electrode 360 includes a conductive column 340 and a plurality of first toothings 361.
  • Each of the first toothing 361 is connected to the outer side surface of the conductive column 340 and is perpendicular to the side surface of the conductive column 340.
  • the first toothing 361 is arranged in sequence along the axial direction of the conductive column 340 (the Y direction in FIG. 25).
  • the columnar lower electrode includes at least two of the first toothings.
  • the upper end surface and the lower end surface of the columnar lower electrode 360 are both formed by the end surface of the conductive column 340 and the surface of the first tooth 361.
  • the first tooth 361 surrounds the conductive column 340 once, and a plurality of the first tooth 361 are arranged at equal intervals. Taking the axial direction of the conductive pillar 340 as the symmetry axis, the first toothing 361 is symmetrically arranged.
  • the ring-shaped upper electrode 380 includes a ring-shaped body 381 and a plurality of second inserting teeth 382.
  • the second toothing 382 penetrates the annular body 381 in the axial direction perpendicular to the annular body 381 (the X direction in FIG. 25), that is, in the axial direction perpendicular to the annular body 381 (as shown in FIG. 25 In the X direction), the second toothing 382 is provided on both the inner side and the outer side of the annular body 381.
  • the ring-shaped upper electrode 380 includes at least one of the second pinion 382, and the second pinion 382 wraps around the outer and inner sides of the ring body 381.
  • the second toothing 382 is symmetrically arranged with the axial direction of the annular main body 381 (the Y direction in FIG. 25) as the symmetry axis.
  • a plurality of the second shaper teeth 382 are arranged in sequence along the axial direction of the annular main body 381, preferably arranged at equal intervals.
  • both the upper end surface and the lower end surface of the ring-shaped upper electrode 380 are formed by the end surface of the ring-shaped body 381, that is, the second pinion 382 is not in contact with the insulating region 302.
  • the ring-shaped main body 381 is disposed around the columnar lower electrode 360, and the dielectric layer 370 is disposed between the columnar lower electrode 360 and the ring-shaped upper electrode 380 to form the capacitor structure.
  • the first tooth 361 and the second tooth 382 are alternately arranged.
  • the ring body 381 and the second tooth 382 on the inner side of the ring body 381, the lower electrode 360 surrounded by the ring body 381 and the dielectric layer 370 between the two constitute a capacitor.
  • the first tooth 361 and the second tooth 382 partially overlap to increase The area of the capacitor structure further increases the capacitance of the capacitor structure.
  • the axial direction of the conductive column 340 coincides with the axial direction of the annular body 381.
  • the dielectric layer 370 is formed by joining the main dielectric layer 310B, the first supplementary dielectric layer 330 and the second supplementary dielectric layer 331.
  • the materials of the main dielectric layer 310B, the first supplementary dielectric layer 330 and the second supplementary dielectric layer 331 are the same.
  • the main dielectric layer 310B The materials of the first supplementary dielectric layer 330 and the second supplementary dielectric layer 331 may also be different.
  • the capacitor structure further includes a conductive connection layer 383 disposed on the upper surface of the capacitor structure, the conductive connection layer 383 is connected to the upper surface of the ring-shaped upper electrode 380, and the conductive connection layer A dielectric layer 370 is provided between 383 and the upper surface of the columnar lower electrode 360.
  • An upper electrode plate 390 is provided on the conductive connection layer 383, and the upper electrode plate 390 can be electrically connected to the outside, so as to realize the electrical connection between the upper electrode 380 and the outside.
  • a first pinion 361 is formed on the lower electrode 360, and a second pinion 382 is formed on the upper electrode 380, and the first pinion 361 and the second pinion 382 are alternately arranged.
  • the cross area of the capacitor structure is increased, so that the capacitance of the capacitor structure is greatly increased, and the storage capacity of the memory is provided.

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Abstract

本申请实施例提供一种电容器结构及其制备方法，所述方法包括：提供衬底，衬底包括间隔设置的导电接触区及绝缘区；在衬底上形成叠层，叠层包括叠加设置的多个单元和位于相邻两个单元之间的主介电层；每一单元包括导电层、主介电层和牺牲层；形成多个贯穿叠层的第一过孔，第一过孔暴露出导电接触区的部分上表面；在第一过孔中填充导电材料，形成导电柱；导电柱与导电接触区连接；以导电柱为轴心，在预设半径处，形成多个贯穿所述叠层的第二过孔，第二过孔环绕导电柱一周，且第二过孔暴露出绝缘区的部分上表面，导电柱及与导电柱连接的导电层作为具有第一插齿的柱状下电极；在第二过孔内填充导电材料，形成具有第二插齿的环形上电极。

Description

电容器结构及其制备方法
相关申请的交叉引用
本申请基于申请号为202010547452.7、申请日为2020年06月16日、发明名称为“电容器结构及其制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及集成电路领域，尤其涉及一种电容器结构及其制备方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在20纳米(nm)以下的DRAM制程中，DRAM大多采用堆栈式的电容构造，其电容器(Capacitor)是垂直的高深宽比的圆柱体形状。
目前，圆柱状双面电容为业界主要技术。图1A是相关技术中的DRAM存储器中圆柱状双面电容的截面示意图，图1B是沿图1A中A-A线的局部俯视示意图，请参阅图1A及图1B，在阵列区域圆柱状的深洞中底部和侧壁上形成下电极10，所述下电极10与下极板14接触，在深洞内沉积高k电介质材料作为电极介质层11，并在电极介质层11上形成上电极12，再采用上极板13覆盖所述上电极12。
随着DRAM存储器的发展，现有的圆柱状双面电容存储电荷的能力已经不能满足需求。
发明内容
本申请实施例提供一种电容器结构及其制备方法，能够提高电容器结构的电容。
本申请实施例提供了一种电容器结构的制备方法，包括如下步骤：提供衬底，所述衬底包括间隔设置的导电接触区及绝缘区；在所述衬底上形成叠层，所述叠层包括叠加设置的多个单元和位于相邻两个单元之间的主介质层；每一所述单元包括导电层、所述主介电层和牺牲层；形成多个贯穿所述叠层的第一过孔，所述第一过孔与所述导电接触区对应，并暴露出所述导电接触区的部分上表面；去除所述第一过孔侧壁的部分牺牲层，以在所述第一过孔侧壁的牺牲层对应区域形成第一凹槽；在所述第一凹槽内形成第一补充介电层；
在所述第一过孔中填充导电材料，形成导电柱，所述导电柱连接所述导电层，且所述导电柱与所述导电接触区连接；以所述导电柱为轴心，在预设半径处，形成多个贯穿所述叠层的第二过孔，所述第二过孔环绕所述导电柱一周，且所述第二过孔与所述绝缘区对应，并暴露出所述绝缘区的部分上表面，所述导电柱及与所述导电柱连接的导电层作为具有第一插齿的柱状下电极；去除所述第二过孔侧壁的部分导电层，以在所述第二过孔侧壁的导电层对应区域形成第二凹槽；在所述第二凹槽内形成第二补充介电层，所述主介电层、所述第一补充介电层及所述第二补充介电层包覆所述下电 极；去除所述第二过孔侧壁的所有牺牲层；在所述第二过孔内填充导电材料，形成具有第二插齿的环形上电极。
在本申请的一些实施例中，所述叠层的最上层为牺牲层；在去除所述第一过孔侧壁的部分牺牲层时，去除最上层的所述牺牲层，暴露出所述牺牲层下方的主介电层。
在本申请的一些实施例中，所述在所述第一凹槽内形成第一补充介电层，包括：在所述第一过孔内填充介电材料；形成贯穿所述介电材料的通孔，所述通孔与所述第一过孔同轴，且所述通孔的直径大于或者等于所述第一过孔的直径，被保留的所述介电材料形成所述第一补充介电层。
在本申请的一些实施例中，所述在所述第一过孔中填充导电材料，形成导电柱，包括：在所述第一过孔中填充所述导电材料，所述导电材料充满所述第一过孔，且覆盖在所述主介质层的上表面；去除部分所述导电材料，暴露出所述主介质层的上表面，形成所述导电柱，且所述导电柱的上表面与所述主介质层下方的导电层平齐。
在本申请的一些实施例中，在形成所述导电柱后，所述方法还包括：沉积介电材料，所述介电材料至少填充在所述导电柱上方。
在本申请的一些实施例中，所述介电材料还覆盖在所述主介质层之上，在沉积所述介电材料后，平坦化所述介电材料。
在本申请的一些实施例中，所述在所述第二凹槽内形成第二补充介电层，包括：在所述第二过孔内填充介电材料；形成贯穿所述介电材料的环形通孔，所述通孔与所述第二过孔同轴，且所述通孔的宽度大于或者等于所述第二过孔的宽度，被保留的所述介电材料形成所述第二补充介电层。
在本申请的一些实施例中，在所述第二过孔内填充导电材料，形成具有第二插齿的环形上电极时，所述导电材料覆盖所述叠层的上表面，以形成导电连接层。
在本申请的一些实施例中，在所述第二过孔内填充导电材料，形成具有第二插齿的环形上电极之后，所述方法还包括：在所述导电连接层上表面形成上极板。
本申请实施例还提供一种电容器结构，包括：柱状下电极，包括导电柱及多个第一插齿，每一所述第一插齿与所述导电柱外侧面连接，且垂直所述导电柱的侧面，多个所述第一插齿沿所述导电柱的轴向依次排列；环形上电极，包括环形主体及多个第二插齿，所述第二插齿沿垂直所述环形主体的轴向方向贯穿所述环形主体，且多个所述第二插齿沿所述环形主体的轴向依次排列，其中，所述环形主体环绕所述柱状下电极设置，所述第一插齿与所述第二插齿交替排列；介电层，设置在所述柱状下电极与所述环形上电极之间。
在本申请的一些实施例中，在沿所述导电柱的轴向方向上，所述第一插齿与所述第二插齿部分交叠。
在本申请的一些实施例中，所述第一插齿绕所述导电柱的侧面一周。
在本申请的一些实施例中，所述第二插齿绕所述环形主体的侧面一周。
在本申请的一些实施例中，所述电容器结构设置在衬底上，所述衬底包括间隔设置的导电接触区及绝缘区，所述柱状下电极的下表面与所述导电接触连接，所述环形上电极的下表面与所述绝缘区连接。
在本申请的一些实施例中，所述电容器结构还包括设置在所述电容器结构上表面的导电连接层；所述导电连接层与所述环形上电极的上表面连接，且所述导电连接层与所述柱状下电极的上表面之间具有所述介电层。
在本申请的一些实施例中，所述电容器结构还包括上极板，所述上极板设置在所述导电连接层上。
在本申请的一些实施例中，所述柱状下电极的端面由所述导电柱的端面及所述第 一插齿的表面共同构成。
在本申请的一些实施例中，所述环形上电极的端面由所述环形主体的端面构成。
在本申请的一些实施例中，以所述导电柱的轴向为对称轴，所述第一插齿对称设置，以所述环形主体的轴向为对称轴，所述第二插齿对称设置。
在本申请的一些实施例中，所述导电柱的轴向与所述环形主体的轴向重合。
本申请实施例的优点在于，电容器结构的上电极与下电极具有较大的交叉面积，电容器结构的电容增加，且上电极及下电极的形状误差小，满足设计要求。
附图说明
图1A是相关技术中的DRAM存储器中圆柱状双面电容的截面示意图；
图1B是沿图1A中A-A线的局部俯视示意图；
图2是本申请实施例电容器结构的制备方法的一实施方式的步骤示意图；
图3～图25是本申请实施例电容结构的制备方法的一实施方式的工艺流程图；
图26是在图25中A-A线处的局部俯视图；
图27是在图25中B-B线处的局部俯视图；
图28是在图25中C-C线处的局部俯视图；
图29是在图25中D-D线处的局部俯视图。
具体实施方式
下面结合附图对本申请实施例提供的电容器结构及其制备方法做详细说明。
本申请实施例提供一种电容器结构的制备方法。图2是本申请实施例电容器结构的制备方法的一实施方式的步骤示意图，图3～图25是本申请实施例电容结构的制备方法的一实施方式的工艺流程图。请参阅图2，本申请实施例电容器结构的制备方法包括如下步骤：
请参阅步骤S20及图3，提供衬底300，所述衬底300包括间隔设置的导电接触区301及绝缘区302。其中，可在所述衬底300中形成导电接触焊盘，所述导电接触焊盘作为所述导电接触区301，未设置所述导电接触焊盘的区域作为所述绝缘区302。
请参阅步骤S21及图4，在所述衬底300上形成叠层，所述叠层包括叠加设置的多个单元310和设置于相邻两个单元之间的主介电层310B，每一所述单元310包括导电层310A、主介电层310B及牺牲层310C，在所述单元310之间也形成有主介电层310B。在每一单元310中，所述导电层310A、主介电层310B及牺牲层310C依次设置。在一些实施例中，可以在同一机台上重复生长单元310。本申请实施例中，所述叠层包括至少两个所述单元。
请参阅步骤S22及图8，形成多个贯穿所述叠层的第一过孔320，每一第一过孔320与所述导电接触区301对应，并暴露出所述导电接触区301的部分上表面。本申请实施例中，形成了两个第一过孔302。本申请实施例中，形成了至少一个贯穿所述叠层的第一过孔。
在本申请实施例中，采用光刻及刻蚀的方法形成所述第一过孔320。说明如下：
请参阅图5，在所述叠层上形成硬掩膜层400及光阻层410。
请参阅图6及图7，其中，图6为截面图，图7为在图6中A-A线处的局部俯视图，图形化所述光阻层410，形成窗口410A，并利用所述窗口410A将图案转移至硬掩膜层400上。其中，在该步骤中，可采用干法刻蚀工艺将图案转移至所述硬掩膜层 400上，所述干法刻蚀工艺包括等离子刻蚀工艺、反应离子刻蚀工艺或者离子铣工艺。
请参阅图8及图9，其中，图8为截面图，图9为在图8中A-A线处的局部俯视图，以所述硬掩膜层400为掩膜，刻蚀所述叠层，形成贯穿所述叠层的第一过孔320。在该步骤中，对叠层进行高深宽比刻蚀，要求刻蚀材料对叠层的刻蚀速率大于对硬掩膜层400与衬底300的刻蚀速率。在一些实施例中，在刻蚀的过程中，所述光阻层410及所述硬掩膜层400可以被消耗，若形成所述第一过孔320后，所述光阻层410及所述硬掩膜层400还有残留，则采用湿法刻蚀工艺去除所述光阻层410及硬掩膜层400。
本申请实施例中，所述第一过孔320的直径与后续需要形成的导电柱340(绘示于图14中)的直径相同，相邻的两个所述第一过孔320轴心之间的距离与相邻的两个所述导电柱340的轴心之间的距离相等。在本申请实施例的其他实施方式中，所述第一过孔320的直径小于后续需要形成的导电柱340的直径。
请参阅步骤S23及图10，去除所述第一过孔320侧壁的部分牺牲层310C，以在所述第一过孔320侧壁的牺牲层310C对应区域形成第一凹槽320A。在该步骤中，可采用湿法刻蚀工艺去除所述牺牲层310C。在沿所述牺牲层310C延伸的方向，所述牺牲层310C被部分去除，与所述牺牲层310C相邻的主介电层310B的部分表面被暴露，相邻的两层所述主介电层310B与所述牺牲层310C围成所述第一凹槽320A。
本申请实施例中，由于所述叠层的最上层为牺牲层310C，则在去除所述第一过孔320侧壁的部分牺牲层310C的步骤中，最上层的牺牲层310C也同时被去除，暴露出所述牺牲层310C下方的主介电层310B。在本申请实施例的其他实施方式中，最上层的牺牲层310C也可以不被去除。
请参阅步骤S24及图12，在所述第一凹槽320A内形成第一补充介电层330。所述第一补充介电层330填充所述第一凹槽320A。在本申请实施例中，所述第一补充介电层330的材料与所述主介电层310B的材料相同。
本申请实施例列举一种在所述第一凹槽320A内形成第一补充介电层330的方法。说明如下：
请参阅图11，在所述第一过孔320内填充介电材料500。所述介电材料500充满所述第一过孔320。可以理解的是，由于工艺原因，在填充所述介电材料500的过程中，最上层暴露的主介电层310B也被所述介电材料覆盖，则在填充所述介电材料500后，对主介电层310B的表面进行化学机械研磨，以去除主介电层310B表面的介电材料。在一些实施例中，所述主介电层310B的材料与所述介电材料为同种材料。
请参阅图12，形成贯穿所述介电材料500的通孔501。形成所述通孔501后位于第一凹槽320A内的介电材料被保留，其他区域的介电材料被去除。位于第一凹槽320A内的介电材料作为所述第一补充介电层330。在形成所述通孔501后，所述导电层310A及主介电层310B的侧面暴露于所述通孔501的侧壁。所述牺牲层310C的侧面被所述第一补充介电层330覆盖，而并未暴露于所述通孔501的侧壁。所述通孔501与所述第一过孔320同轴，且所述通孔501的直径大于或者等于所述第一过孔320的直径，所述通孔501的直径与后续需要形成的导电柱340的直径相同。
请参阅步骤S25及图14，在所述第一过孔320中填充导电材料，形成导电柱340，所述导电柱340连接所述导电层310A，且所述导电柱340与所述导电接触区301连接。在本申请实施例中，形成所述导电柱340的导电材料与所述导电层310A的材料相同。
本申请实施例提供一种形成所述导电柱340的方法，说明如下：
请参阅图13，在所述第一过孔320中填充导电材料600，所述导电材料600充满所述第一过孔320，且覆盖所述主介电层310B的上表面。
请参阅图14，去除部分所述导电材料600，暴露出所述主介质层310B的上表面，形成所述导电柱340，且所述导电柱340的上表面与所述主介质层310B下方的导电层310A平齐。在该步骤中，回刻所述导电材料600，形成所述导电柱340。
在一些实施例中，由于所述导电柱340的上表面与所述主介质层310B下方的导电层310A平齐，则最上层的所述主介电层310B与所述导电柱340对应的区域未被填充，具有空隙，因此，本申请实施例还可以包括如下步骤：请参阅图15，在形成所述导电柱340后在所述主介电层310B上沉积介电材料，所述介电材料至少填充在所述导电柱上方。本申请实施例中，所述介电材料填充最上层的所述主介电层310B与导电柱340对应区域的空隙。可以理解的是，由于工艺原因，在所述主介电层310B的表面也会覆盖介电材料，则可采用化学机械研磨等工艺去除位于主介电层310B表面的介电材料，并使所述主介电层310B的表面平坦化。
请参阅步骤S26及图19，以所述导电柱340为轴心，在预设半径处，形成多个贯穿所述叠层的第二过孔350。所述第二过孔350环绕所述导电柱340一周，且所述第二过孔350与所述绝缘区302对应，并暴露出所述绝缘区302的部分上表面。所述导电柱340和与所述导电柱340连接的导电层310A作为具有第一插齿361(标示于图25中)的柱状下电极360，其中，所述导电层310A作为所述第一插齿361。本申请实施例中，形成了至少一个贯穿所述叠层的第二过孔。
本申请实施例提供了一种形成所述第二过孔350的方法。说明如下：
请参阅图16，在最上层的所述主介电层310B上形成硬掩膜层700及光阻层710。
请参阅图17及图18，其中，图17为截面图，图18为在图17中A-A线处的局部俯视图，图形化所述光阻层710，形成窗口710A，并利用所述窗口710A将图案转移至硬掩膜层700上。其中，在该步骤中，可采用干法刻蚀工艺将图案转移至所述硬掩膜层700上，在该步骤中，转移至所述硬掩膜层700上的图形为以预设半径处环绕所述导电柱340的环形图案，且与所述绝缘区302对应。
请参阅图19，以所述硬掩膜层700为掩膜，刻蚀所述叠层，形成贯穿所述叠层的第二过孔350。其中，在该步骤中形成的第二过孔350形状与图18中窗口710A的形状相同。在该步骤中，对叠层进行高深宽比刻蚀，要求刻蚀材料对叠层的刻蚀速率大于对硬掩膜层700与衬底300的刻蚀速率。在一些实施例中，在刻蚀的过程中，所述光阻层710及所述硬掩膜层700可以被消耗，若形成所述第二过孔350后，所述光阻层710及所述硬掩膜层700还有残留，则可以采用湿法刻蚀工艺去除所述光阻层710及硬掩膜层700。
在本申请实施例中，所述第二过孔350的轴心与后续形成的上电极的环形主体的轴心重合，且所述第二过孔350的宽度与所述环形主体的宽度相同。在本申请实施例的其他实施方式中，所述第二过孔350的宽度小于所述环形主体的宽度。
请参阅步骤S27及图20，去除所述第二过孔350侧壁的部分导电层310A，以在所述第二过孔350侧壁的导电层310A对应区域形成第二凹槽350A。在该步骤中，可采用湿法刻蚀工艺去除所述导电层310A，所述主介电层310B及所述牺牲层310C并未被去除。所述第二凹槽350A由相邻的主介电层310B及位于两者之间的导电层310A围成。在一些实施例中，在该步骤中，去除的所述导电层310A的宽度(沿所述导电层310A延伸方向，如图20中X方向)小于所述牺牲层310C的宽度，以在后续步骤中形成交叠排布的第一插齿361及第二插齿382。
请参阅步骤S28及图22，在所述第二凹槽350A内形成第二补充介电层331，所述主介电层310B、第一补充介电层330及第二补充介电层331包覆所述下电极360。所述第二补充介电层331填充所述第二凹槽350A，以使得所述主介电层310B、第一 补充介电层330及第二补充介电层331形成一闭合的介电层370，进而使得所述下电极360与后续形成的上电极电绝缘。在本申请实施例中，所述第二补充介电层331的材料与所述主介电层310B的材料相同。
本申请实施例还提供一种形成所述第二补充介电层331的方法。说明如下：
请参阅图21，在所述第二过孔350内填充介电材料800。所述介电材料800充满所述第二过孔350。可以理解的是，由于工艺原因，在填充所述介电材料800的过程中，最上层暴露的主介电层310B也被所述介电材料覆盖，则在填充所述介电材料800后，对主介电层310B的表面进行化学机械研磨，以去除主介电层310B表面的介电材料。在一些实施例中，所述主介电层310B的材料与所述介电材料为同种材料。
请参阅图22，形成贯穿所述介电材料800的环形通孔701。形成所述通孔701后位于第二凹槽350A内的介电材料被保留，其他区域的介电材料被去除。位于第二凹槽350A内的介电材料作为所述第二补充介电层331。在形成所述通孔701后，所述主介电层310B、所述牺牲层310C及所述第二补充介电层331的侧面暴露于所述通孔701的侧壁，所述导电层310A的侧面被所述第二补充介电层331覆盖为并未暴露于所述通孔701的侧壁。所述通孔701与所述第二过孔350同轴，且所述通孔701的宽度大于或者等于所述第二过孔350的宽度，所述通孔701的宽度与后续需要形成的上电极的环形主体的宽度相同。
请参阅步骤S29及图23，去除所述第二过孔350侧壁的所有牺牲层310C。在该步骤中，可采用湿法刻蚀工艺去除所述牺牲层310C，所述牺牲层310C所在区域可作为上电极的第二插齿区域。
请参阅步骤S30及图24，在所述第二过孔350内填充导电材料，形成具有第二插齿382的环形上电极380。其中，填充在原有的牺牲层区域的导电材料形成所述第二插齿382，填充在所述第二过孔350内的导电材料形成环形上电极的环形主体381。
在一些实施例中，在步骤S30中，在所述第二过孔内填充导电材料，形成具有第二插齿的环形上电极时，所述导电材料还覆盖所述叠层的上表面，以形成导电连接层383。在步骤S30之后，请参阅图25，在所述导电连接层383上表面形成上极板390。所述导电连接层383作为所述上电极380与所述上极板390的连接层。
在一些实施例中，所述第一插齿361与所述第二插齿382可交叠设置。其中，可通过控制第一凹槽320A及第二凹槽350A的深度来控制所述第一插齿361与所述第二插齿382的交叠量。
通过本申请实施例提供的制备方法所制备的电容器结构的上电极与下电极交叉面积增加，电容器结构的电容增加，且上电极及下电极的形状误差小，满足设计要求。
本申请实施例还提供一种采用上述制备方法制备的电容器结构。请参阅图25、图26、图27、图28及图29，其中，图26是在图25中A-A线处的局部俯视图，图27是在图25中B-B线处的局部俯视图，图28是在图25中C-C线处的局部俯视图，图29是在图25中D-D线处的局部俯视图，所述电容器结构包括柱状下电极360、环形上电极380及介电层370。其中，所述电容器结构设置在衬底300上。所述衬底300包括间隔设置的导电接触区301及绝缘区302。所述柱状下电极360的下表面与所述导电接触区301连接，所述环形上电极380的下表面与绝缘区302连接。
所述柱状下电极360包括导电柱340及多个第一插齿361，每一所述第一插齿361与所述导电柱340外侧面连接，且垂直所述导电柱340的侧面，多个所述第一插齿361沿所述导电柱340的轴向(如图25中Y方向)依次排列。本申请实施例中，所述柱状下电极包括至少两个所述第一插齿。所述柱状下电极360的上端面及下端面均由所述导电柱340的端面及所述第一插齿361的表面共同构成。
本申请实施例中，所述第一插齿361环绕所述导电柱340一周，且多个所述第一插齿361等间距设置。以所述导电柱340的轴向为对称轴，所述第一插齿361对称设置。
所述环形上电极380包括环形主体381及多个第二插齿382。所述第二插齿382沿垂直所述环形主体381的轴向方向(如图25中X方向)贯穿所述环形主体381，即在垂直所述环形主体381的轴心方向上(如图25中X方向)，在所述环形主体381的内侧面及外侧面均设置有所述第二插齿382。在本申请实施例中，所述环形上电极380包括至少一个所述第二插齿382，所述第二插齿382绕所述环形主体381的外侧面及内侧面一周。其中，所述第二插齿382以所述环形主体381的轴向(如图25中Y方向)为对称轴，对称设置。
本申请实施例中，多个所述第二插齿382沿所述环形主体381的轴向依次排列，优选为等间距排列。在一些实施例中，所述环形上电极380的上端面及下端面均由所述环形主体381的端面构成，即所述第二插齿382并未与所述绝缘区302接触。
所述环形主体381环绕所述柱状下电极360设置，所述介电层370设置在所述柱状下电极360与所述环形上电极380之间，形成所述电容器结构。
所述第一插齿361与所述第二插齿382交替排列。所述环形主体381及在所述环形主体381内侧面的第二插齿382与被所述环形主体381环绕的下电极360及两者之间的介电层370构成一个电容器。
在一些实施例中，在沿所述导电柱340的轴向方向(如图25所示Y方向)上，所述第一插齿361与所述第二插齿382部分交叠，以增大所述电容器结构的面积，进而增大所述电容器结构的电容。在一些实施例中，在本申请实施例中，所述导电柱340的轴向与所述环形主体381的轴向重合。
在一些实施例中，所述介电层370由主介电层310B、第一补充介电层330及第二补充介电层331接合而成。在本申请实施例中，所述主介电层310B、第一补充介电层330及第二补充介电层331的材料相同，在本申请实施例的其他实施方式中，主介电层310B、第一补充介电层330及第二补充介电层331的材料也可不相同。
本申请实施例中，所述电容器结构还包括设置在所述电容器结构上表面的导电连接层383，所述导电连接层383与所述环形上电极380的上表面连接，且所述导电连接层383与所述柱状下电极360的上表面之间具有介电层370。在所述导电连接层383上设置有上极板390，所述上极板390能够与外部电连接，以实现所述上电极380与外部的电连接。
本申请实施例提供的电容器结构，在下电极360上形成第一插齿361，在上电极380上形成第二插齿382，所述第一插齿361与所述第二插齿382交错排列，增加了所述电容器结构的交叉面积，使得所述电容器结构的电容大幅度增加，提供了存储器的存储容量。
以上所述仅是本申请实施例的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请实施例原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请实施例的保护范围。

Claims (20)

  1. 一种电容器结构的制备方法，包括：
    提供衬底，所述衬底包括间隔设置的导电接触区及绝缘区；
    在所述衬底上形成叠层，所述叠层包括叠加设置的多个单元和位于相邻两个单元之间的主介电层；每一所述单元包括导电层、所述主介电层和牺牲层；
    形成多个贯穿所述叠层的第一过孔，所述第一过孔与所述导电接触区对应，并暴露出所述导电接触区的部分上表面；
    去除所述第一过孔侧壁的部分牺牲层，以在所述第一过孔侧壁的牺牲层对应区域形成第一凹槽；
    在所述第一凹槽内形成第一补充介电层；
    在所述第一过孔中填充导电材料，形成导电柱，所述导电柱连接所述导电层，且所述导电柱与所述导电接触区连接；
    以所述导电柱为轴心，在预设半径处，形成多个贯穿所述叠层的第二过孔，所述第二过孔环绕所述导电柱一周，且所述第二过孔与所述绝缘区对应，并暴露出所述绝缘区的部分上表面，所述导电柱及与所述导电柱连接的导电层作为具有第一插齿的柱状下电极；
    去除所述第二过孔侧壁的部分导电层，以在所述第二过孔侧壁的导电层对应区域形成第二凹槽；
    在所述第二凹槽内形成第二补充介电层，所述主介电层、所述第一补充介电层及所述第二补充介电层包覆所述下电极；
    去除所述第二过孔侧壁的所有牺牲层；
    在所述第二过孔内填充导电材料，形成具有第二插齿的环形上电极。
  2. 根据权利要求1所述的电容器结构的制备方法，其中，所述叠层的最上层为所述牺牲层；在去除所述第一过孔侧壁的部分牺牲层时，去除最上层的所述牺牲层，暴露出所述牺牲层下方的主介电层。
  3. 根据权利要求1所述的电容器结构的制备方法，其中，所述在所述第一凹槽内形成第一补充介电层，包括：
    在所述第一过孔内填充介电材料；
    形成贯穿所述介电材料的通孔，所述通孔与所述第一过孔同轴，且所述通孔的直径大于或者等于所述第一过孔的直径，被保留的所述介电材料形成所述第一补充介电层。
  4. 根据权利要求2所述的电容器结构的制备方法，其中，所述在所述第一过孔中填充导电材料，形成导电柱，包括：
    在所述第一过孔中填充所述导电材料，所述导电材料充满所述第一过孔，且覆盖在所述主介质层的上表面；
    去除部分所述导电材料，暴露出所述主介质层的上表面，形成所述导电柱，且所述导电柱的上表面与所述主介质层下方的导电层平齐。
  5. 根据权利要求4所述的电容器结构的制备方法，其中，在形成所述导电柱后，所述还包括：沉积介电材料，所述介电材料至少填充在所述导电柱上方。
  6. 根据权利要求5所述的电容器结构的制备方法，其中，所述介电材料还覆盖在所述主介质层之上，在沉积所述介电材料后，平坦化所述介电材料。
  7. 根据权利要求1所述的电容器结构的制备方法，其中，所述在所述第二凹槽内形成第二补充介电层，包括：
    在所述第二过孔内填充介电材料；
    形成贯穿所述介电材料的环形通孔，所述通孔与所述第二过孔同轴，且所述通孔的宽度大于或者等于所述第二过孔的宽度，被保留的所述介电材料形成所述第二补充介电层。
  8. 根据权利要求1所述的电容器结构的制备方法，其中，在所述第二过孔内填充导电材料，形成具有第二插齿的环形上电极时，所述导电材料覆盖所述叠层的上表面，以形成导电连接层。
  9. 根据权利要求8所述的电容器结构的制备方法，其中，在所述第二过孔内填充导电材料，形成具有第二插齿的环形上电极之后，所述方法还包括：
    在所述导电连接层上表面形成上极板。
  10. 一种电容器结构，包括：
    柱状下电极，包括导电柱及多个第一插齿，每一所述第一插齿与所述导电柱外侧面连接，且垂直所述导电柱的侧面，多个所述第一插齿沿所述导电柱的轴向依次排列；
    环形上电极，包括环形主体及多个第二插齿，所述第二插齿沿垂直所述环形主体的轴向方向贯穿所述环形主体，且多个所述第二插齿沿所述环形主体的轴向依次排列，其中，所述环形主体环绕所述柱状下电极设置，所述第一插齿与所述第二插齿交替排列；
    介电层，设置在所述柱状下电极与所述环形上电极之间。
  11. 根据权利要求10所述的电容器结构，其中，在沿所述导电柱的轴向方向上，所述第一插齿与所述第二插齿部分交叠。
  12. 根据权利要求10所述的电容器结构，其中，所述第一插齿绕所述导电柱的侧面一周。
  13. 根据权利要求10所述的电容器结构，其中，所述第二插齿绕所述环形主体的侧面一周。
  14. 根据权利要求10所述的电容器结构，其中，所述电容器结构设置在衬底上，所述衬底包括间隔设置的导电接触区及绝缘区，所述柱状下电极的下表面与所述导电接触连接，所述环形上电极的下表面与所述绝缘区连接。
  15. 根据权利要求10所述的电容器结构，其中，所述电容器结构还包括设置在所述电容器结构上表面的导电连接层；所述导电连接层与所述环形上电极的上表面连接，且所述导电连接层与所述柱状下电极的上表面之间具有所述介电层。
  16. 根据权利要求15所述的电容器结构，其中，所述电容器结构还包括上极板，所述上极板设置在所述导电连接层上。
  17. 根据权利要求10所述的电容器结构，其中，所述柱状下电极的端面由所述导电柱的端面及所述第一插齿的表面共同构成。
  18. 根据权利要求10所述的电容器结构，其中，所述环形上电极的端面由所述环形主体的端面构成。
  19. 根据权利要求10所述的电容器结构，其中，以所述导电柱的轴向为对称轴，所述第一插齿对称设置，以所述环形主体的轴向为对称轴，所述第二插齿对称设置。
  20. 根据权利要求10所述的电容器结构，其中，所述导电柱的轴向与所述环形主体的轴向重合。
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