WO2021253513A1 - 一种用于三维集成电路封装的硅通孔结构及其制造方法 - Google Patents

一种用于三维集成电路封装的硅通孔结构及其制造方法 Download PDF

Info

Publication number
WO2021253513A1
WO2021253513A1 PCT/CN2020/099977 CN2020099977W WO2021253513A1 WO 2021253513 A1 WO2021253513 A1 WO 2021253513A1 CN 2020099977 W CN2020099977 W CN 2020099977W WO 2021253513 A1 WO2021253513 A1 WO 2021253513A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
integrated circuit
substrate
layer
metal material
Prior art date
Application number
PCT/CN2020/099977
Other languages
English (en)
French (fr)
Inventor
朱宝
陈琳
孙清清
张卫
Original Assignee
复旦大学
上海集成电路制造创新中心有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 复旦大学, 上海集成电路制造创新中心有限公司 filed Critical 复旦大学
Priority to US17/052,853 priority Critical patent/US11887912B2/en
Publication of WO2021253513A1 publication Critical patent/WO2021253513A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body

Definitions

  • the invention belongs to the technical field of integrated circuit packaging, and specifically relates to a through-silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof.
  • microelectronic packaging technology has gradually become the main factor restricting the development of semiconductor technology.
  • the three-dimensional packaging technology has good electrical performance and high reliability, and can achieve high packaging density, and is widely used in various high-speed circuits and miniaturized systems.
  • Through silicon via technology is a new technology for stacking chips in three-dimensional integrated circuits to achieve interconnection. Many vertical interconnection vias are made on silicon wafers to achieve electrical interconnection between different chips.
  • Through silicon via technology can maximize the stacking density of chips in the three-dimensional direction, the shortest interconnection lines between chips, and the smallest overall size, and greatly improve the performance of chip speed and low power consumption. It is currently the most eye-catching electronic packaging technology.
  • a technology is currently the most eye-catching electronic packaging technology.
  • the thinning of the silicon wafer In order to meet the requirements of the overall thickness of the package, for the traditional through silicon via manufacturing process, one of the most important steps is the thinning of the silicon wafer.
  • mechanical grinding is usually used. Among them, a considerable thickness of silicon material will be removed but cannot be recycled, resulting in a large amount of waste of silicon material.
  • the through-silicon via structure since the through-hole penetrates the entire silicon wafer, the through-hole is generally very deep.
  • the silicon wafer is usually etched on one side using a dry or wet etching process until the bottom of the silicon wafer penetrates. Since the silicon wafer is only etched on one side, the etching rate of this process is low, which affects the production efficiency.
  • the purpose of the present invention is to provide a through-silicon via structure for three-dimensional integrated circuit packaging with high etching rate, high production efficiency and low process complexity and a preparation method thereof.
  • the method for manufacturing a through-silicon via structure for three-dimensional integrated circuit packaging includes the following specific steps:
  • An insulating medium, a copper diffusion barrier layer and a seed layer are sequentially deposited on the sidewalls of the through silicon via and the upper and lower surfaces of the substrate, and a part of the copper diffusion barrier layer and the seed crystal are removed by photolithography and etching processes Layer, leaving only the copper diffusion barrier layer and the seed layer at the sidewalls of the through silicon vias;
  • a sacrificial layer is formed on the upper and lower surfaces of the above structure, the conductive metal material is completely filled in the through silicon hole, and then the sacrificial layer is removed, and the upper and lower surfaces of the conductive metal material respectively protrude from the upper and lower surfaces of the insulating medium;
  • a contact solder joint is formed on the surface of the conductive metal material.
  • the step of obtaining a substrate for preparing a through silicon via specifically includes:
  • a layer of SiO 2 film is grown on the surface of the silicon wafer by thermal oxidation
  • ion implantation is used to inject hydrogen ions into the silicon wafer, and the hydrogen ions diffuse into the silicon wafer through the silicon dioxide;
  • the silicon wafer is annealed, the hydrogen gas in the microcavity where the hydrogen is injected is foamed, and the silicon wafer is peeled off;
  • the silicon dioxide on the surface of the stripped silicon wafer is removed by a wet etching process, and the bottom of the silicon wafer is planarized by a chemical mechanical polishing method, thereby obtaining a substrate for making through-silicon vias.
  • the hydrogen ion implantation depth range is changed by changing the hydrogen ion implantation energy, and the selected hydrogen ion implantation energy is greater than 5000 KeV to obtain a through silicon hole with a depth greater than 50 microns.
  • the temperature range for annealing the silicon wafer is 300-400°C.
  • the conductive metal material is copper.
  • the invention also discloses a through-silicon via structure for three-dimensional integrated circuit packaging, including:
  • Insulating medium covering the sidewalls of through silicon vias and the upper and lower surfaces of the substrate
  • a copper diffusion barrier layer and a seed layer wherein the copper diffusion barrier layer covers the insulating medium on the sidewall of the through silicon via, and the seed layer covers the surface of the copper diffusion barrier layer;
  • Conductive metal material and contact solder joints wherein the conductive metal material completely fills the through silicon via, extends upward and downward, and protrudes from the upper and lower surfaces of the insulating medium;
  • the contact pads are placed on the top and bottom of the conductive metal material.
  • the conductive metal material is copper.
  • the insulating medium is at least one of SiO 2 , Si 3 N 4 , SiON, SiCOH, and SiCOFH.
  • the copper diffusion barrier layer is at least one of TaN, TiN, ZrN, and MnSiO 3.
  • the seed layer is at least one of Cu, Ru, Co, RuCo, CuRu, and CuCo.
  • the invention adopts the method of injecting hydrogen ions into the silicon wafer to peel off the silicon wafer to obtain a substrate for preparing through-silicon vias, which can make full use of silicon materials and save costs.
  • Performing double-sided plasma etching on the silicon substrate to obtain through silicon vias can increase the etching rate and improve production efficiency.
  • Figure 1 is a flow chart of a through silicon via structure manufacturing process for three-dimensional integrated circuit packaging.
  • 2 to 5 are schematic diagrams of each step of peeling off the silicon wafer to obtain the substrate.
  • 6 to 7 are schematic diagrams of each step of forming through silicon vias.
  • 8-9 are structural schematic diagrams of each step of forming an insulating medium, a copper diffusion barrier layer, and a seed layer.
  • 10 to 13 are schematic diagrams of each step of electroplating copper and forming contact solder joints.
  • FIG. 1 is a flow chart of a through silicon via structure manufacturing process for three-dimensional integrated circuit packaging
  • FIGS. 2-13 show schematic structural diagrams of various steps of the through silicon via structure manufacturing process for three-dimensional integrated circuit packaging. As shown in Figure 1, the specific preparation steps are:
  • Step S1 peeling off the silicon wafer to obtain a substrate for preparing through silicon vias.
  • a thermal oxidation method is used to grow a layer of SiO 2 film 201 on the surface of the silicon wafer 200 with a thickness ranging from 200 to 500 nm.
  • the resulting structure is shown in FIG. 2.
  • hydrogen ions 202 are implanted into the silicon wafer 200 by ion implantation, and the hydrogen ions 202 diffuse into the silicon wafer 200 through the silicon dioxide 201.
  • the resulting structure is shown in FIG. 3.
  • the hydrogen ion implantation energy By changing the hydrogen ion implantation energy, the depth range of the hydrogen ion implantation can be changed.
  • the hydrogen ion implantation energy is selected to be greater than 5000 KeV.
  • the annealing temperature range is 300 ⁇ 400°C; hydrogen foams in the microcavity at the hydrogen injection, the silicon wafer 200 peels off and splits into upper and lower parts, the upper part is the surface Silicon wafer A covered with silicon dioxide, and the lower part is silicon wafer B without silicon dioxide.
  • the resulting structure is shown in FIG. 4.
  • the silicon dioxide 201 on the surface of the silicon wafer A is removed by a wet etching process, and the bottom of the silicon wafer A is planarized by a chemical mechanical polishing method, thereby obtaining a substrate for making through-silicon vias.
  • the resulting structure is shown in FIG. 5.
  • the silicon wafer B the above process can be used to continue the stripping so as to obtain more substrates that can be used to make through silicon vias.
  • the silicon material can be fully utilized and the cost can be saved.
  • Step S2 forming a through silicon via.
  • the photoresist 203 is spin-coated on the upper and lower surfaces of the silicon substrate 200 obtained above, and the through-silicon via pattern is defined through the exposure and development process.
  • the resulting structure is shown in FIG. 6.
  • plasma etching is simultaneously performed on the upper and lower surface patterns of the silicon substrate 200 until the silicon substrate 200 penetrates.
  • the photoresist 203 is then dissolved or ashed in a solvent, and the resulting structure is shown in FIG. 7.
  • the plasma used can be at least one of CF 4 and SF 6. Performing double-sided plasma etching on the silicon substrate to obtain through silicon vias can increase the etching rate and improve production efficiency.
  • Step S3 forming an insulating medium, a copper diffusion barrier layer and a seed layer.
  • chemical vapor deposition method to deposit a layer of SiO 2 film as the insulating medium 205 on the sidewall of the through silicon hole and the upper and lower surfaces of the substrate; then using physical vapor deposition method to grow a layer of TaN film on the surface of the SiO 2 film 205 as a copper diffusion barrier layer 206;
  • a layer of Cu film is grown on the surface of the TaN film 206 as a seed layer 207 by using a physical vapor deposition method, and the resulting structure is shown in FIG. 8.
  • SiO 2 is used as the insulating medium
  • TaN is used as the copper diffusion barrier layer
  • the Cu film is used as the seed layer.
  • the present invention is not limited to this, and SiO 2 , Si 3 N 4 , SiON, SiCOH, SiCOFH can be selected.
  • At least one of TaN, TiN, ZrN, and MnSiO 3 can be selected as the insulating medium; at least one of TaN, TiN, ZrN, and MnSiO 3 can be selected as the copper diffusion barrier; and at least one of Cu, Ru, Co, RuCo, CuRu, and CuCo can be selected as the seed. ⁇ The crystal layer.
  • the growth mode of the copper diffusion barrier layer and the seed layer can also be chemical vapor deposition or atomic layer deposition.
  • the remaining TaN barrier layer 206 only covers the surface of the SiO 2 film 205 on the sidewall of the silicon via; accordingly, the remaining Cu seed layer 207 only covers the surface of the TaN barrier layer 206 on the sidewall of the via.
  • Step S4 Electroplating copper and forming contact solder joints. First, spin-coated photoresist on the surface of the above structure, and define the pattern through exposure and development. Then an electron beam evaporation process is used to grow a layer of metal Ni film as the sacrificial layer 208, and then the photoresist and the metal Ni film on the surface of the photoresist are removed in a solvent by a lift-off process. The resulting structure is shown in FIG. 10 . Subsequently, an electroplating process is used to electroplate the copper material 209 in the through silicon hole and completely fill the through silicon hole. The resulting structure is shown in FIG. 11.
  • the metal Ni film 208 is removed by photolithography and etching processes, and the resulting structure is shown in FIG. 12.
  • the conductive metal material 209 respectively extends from the through-silicon vias up and down, the upper surface of which is higher than the upper surface of the insulating medium 205, and the lower surface of which is lower than the upper surface of the insulating medium 205.
  • a metal Sn material is welded on the surface of the copper material 209 as a contact pad 210, and the resulting structure is shown in FIG. 13.
  • a metal Ni film is used as the sacrificial layer, but the present invention is not limited to this, and any one of Ni, Ti, Ta, and Cr may be selected as the sacrificial layer. There is no need to chemically and mechanically polish the copper material after the copper electroplating, which can greatly reduce the process complexity.
  • the through-silicon via structure for three-dimensional integrated circuit packaging of the present invention includes: through-silicon vias penetrating through the substrate; an insulating medium 205 covering the sidewalls of the through-silicon vias and the upper and lower surfaces of the substrate.
  • the copper diffusion barrier layer 206 and the seed layer 207 wherein the copper diffusion barrier layer 206 covers the insulating medium 205 on the sidewall of the through silicon via, and the seed layer 207 covers the surface of the copper diffusion barrier layer 206;
  • the metal material 209 and the contact solder joint 210 wherein the conductive metal material 209 completely fills the through silicon hole, extends upward and downward, and protrudes from the upper and lower surfaces of the insulating medium 205; the contact solder joint 210 is placed on the The top and bottom of the conductive metal material 209 are described.
  • the insulating medium 205 is at least one of SiO 2 , Si 3 N 4 , SiON, SiCOH, and SiCOFH.
  • the copper diffusion barrier layer 206 is at least one of TaN, TiN, ZrN, and MnSiO 3.
  • the seed layer 207 is at least one of Cu, Ru, Co, RuCo, CuRu, and CuCo.
  • the sacrificial layer 208 may be any one of Ni, Ti, Ta, and Cr.
  • the conductive metal material 209 is copper, for example.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明属于集成电路封装技术领域，具体为一种用于三维集成电路封装的硅通孔结构及其制造方法。本发明方法包括以下步骤：通过向硅片中注入氢离子剥离硅片获得制备硅通孔的基底；对基底进行双面等离子体刻蚀，从而将基底贯通形成硅通孔；沉积绝缘介质、铜扩散阻挡层和籽晶层，采用光刻和刻蚀工艺去除部分所述铜扩散阻挡层和所述籽晶层，仅保留硅通孔侧壁处的所述铜扩散阻挡层和所述籽晶层；在上述结构的上下表面形成牺牲层，在硅通孔中完全填充导电金属材料，然后去除牺牲层，所形成的导电金属材料的上下表面分别突出于绝缘介质的上下表面；在导电金属材料表面形成接触焊点。本发明能够有效提高生产效率，节约成本。

Description

一种用于三维集成电路封装的硅通孔结构及其制造方法 技术领域
本发明属于集成电路封装技术领域，具体涉及一种用于三维集成电路封装的硅通孔结构及其制造方法。
背景技术
随着集成电路工艺技术的高速发展，微电子封装技术逐渐成为制约半导体技术发展的主要因素。为了实现电子封装的高密度化，获得更优越的性能和更低的总体成本，技术人员研究出一系列先进的封装技术。其中三维封装技术具有良好的电学性能以及较高的可靠性，同时能实现较高的封装密度，被广泛应用于各种高速电路以及小型化系统中。硅通孔技术是三维集成电路中堆叠芯片实现互连的一种新技术，通过在硅圆片上制作出许多垂直互连通孔来实现不同芯片之间的电互连。硅通孔技术能够使芯片在三维方向堆叠的密度最大、芯片之间的互连线最短、外形尺寸最小，并且大大改善芯片速度和低功耗的性能，是目前电子封装技术中最引人注目的一种技术。
为了满足封装总体厚度的要求，对于传统的硅通孔制造工艺，其中很重要的一个步骤是硅片减薄。然而对于硅片减薄，通常都是采用机械磨削的方法，这其中相当厚度的硅材料会被去除却无法回收利用，导致硅材料的大量浪费。此外，对于硅通孔结构，由于通孔是贯通整个硅片的，所以通孔一般都非常深。在传统的硅通孔形成工艺中，对于已经减薄的硅片，通常都是单侧采用干法或者湿法刻蚀工艺刻蚀硅片，直到硅片底部穿通。由于只是单侧刻蚀硅片，所以这种工艺刻蚀速率较低，影响生产效率。
发明内容
本发明的目的在于提供一种刻蚀速率大、生产效率高、工艺复杂度低的用于三维集成电路封装的硅通孔结构及其制备方法。
本发明提供的用于三维集成电路封装的硅通孔结构制备方法，具体步骤 为：
通过向硅片中注入氢离子剥离硅片，获得制备硅通孔的基底；
对基底进行双面等离子体刻蚀，从而将基底贯通形成硅通孔；
在所述硅通孔的侧壁和所述基底的上下表面依次沉积绝缘介质、铜扩散阻挡层和籽晶层，采用光刻和刻蚀工艺去除部分所述铜扩散阻挡层和所述籽晶层，仅保留硅通孔侧壁处的所述铜扩散阻挡层和所述籽晶层；
在上述结构的上下表面形成牺牲层，在硅通孔中完全填充导电金属材料，然后去除牺牲层，导电金属材料的上下表面分别突出于所述绝缘介质的上下表面；
在导电金属材料表面形成接触焊点。
本发明制备方法中，优选为，所述获得制备硅通孔的基底的步骤，具体包括：
首先，采用热氧化方法在硅片表面生长一层SiO 2薄膜；
然后，采用离子注入方式向硅片中注入氢离子，氢离子通过二氧化硅向硅片内部扩散；
之后，对所述硅片进行退火，注氢处微空腔内氢气发泡，硅片发生剥离；
最后，通过湿法刻蚀工艺去除剥离后的硅片表面的二氧化硅，并采用化学机械抛光方法平坦化硅片的底部，从而获得用于制作硅通孔的基底。
本发明制备方法中，优选为，通过改变氢离子注入能量，改变氢离子注入深度范围，所选氢离子注入能量大于5000KeV，以获得深度大于50微米的硅通孔。
本发明制备方法中，优选为，对所述硅片进行退火的温度范围为300～400℃。
本发明制备方法中，优选为，所述导电金属材料为铜。
本发明还公开一种用于三维集成电路封装的硅通孔结构，包括：
贯通基底的硅通孔；
绝缘介质，覆盖硅通孔的侧壁以及基底的上下表面；
铜扩散阻挡层以及籽晶层，其中，所述铜扩散阻挡层覆盖硅通孔的侧壁上的所述绝缘介质，所述籽晶层覆盖铜扩散阻挡层表面；
导电金属材料以及接触焊点，其中，所述导电金属材料完全填充所述硅 通孔，并向上和向下延伸，突出于所述绝缘介质的上下表面；
接触焊点置于所述导电金属材料的顶部和底部。
本发明的硅通孔结构中，优选为，所述导电金属材料为铜。
本发明的硅通孔结构中，优选为，所述绝缘介质是SiO 2、Si 3N 4、SiON、SiCOH、SiCOFH中的至少一种。
本发明的硅通孔结构中，优选为，所述铜扩散阻挡层是TaN、TiN、ZrN、MnSiO 3中的至少一种。
本发明的硅通孔结构中，优选为，所述籽晶层是Cu、Ru、Co、RuCo、CuRu、CuCo中的至少一种。
本发明采用向硅片中注入氢离子剥离硅片的方式来获得制备硅通孔的基底，可以充分利用硅材料，节约成本。对硅基底进行双面等离子体刻蚀从而获得硅通孔，可以增大刻蚀速率，提高生产效率。在电镀铜之后的步骤中无需化学机械抛光铜材料，可以极大减少工艺复杂度。
附图说明
图1是用于三维集成电路封装的硅通孔结构制造工艺的流程图。
图2～图5是剥离硅片获得基底的各步骤的结构示意图。
图6～图7是形成硅通孔的各步骤的结构示意图。
图8～图9是形成绝缘介质、铜扩散阻挡层和籽晶层的各步骤的结构示意图。
图10～图13是电镀铜以及形成接触焊点的各步骤的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”、“垂直”“水 平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
以下结合附图1-13和实施例对本发明的技术方案做进一步的说明。图1是用于三维集成电路封装的硅通孔结构制造工艺的流程图，图2-13示出了用于三维集成电路封装的硅通孔结构制造工艺各步骤的结构示意图。如图1所示，具体制备步骤为：
步骤S1：剥离硅片获得制备硅通孔的基底。首先采用热氧化方法在硅片200表面生长一层SiO 2薄膜201，厚度范围为200～500nm，所得结构如图2所示。然后采用离子注入方式向硅片200中注入氢离子202，氢离子202通过二氧化硅201向硅片200内部扩散，所得结构如图3所示。通过改变氢离子注入能量，可以改变氢离子注入深度范围。为了获得厚度大于50微米的硅通孔，所选氢离子注入能量大于5000KeV。
紧接着将上述硅片放入管式炉中进行退火，退火温度范围为300～400℃；注氢处微空腔内氢气发泡，硅片200发生剥离，分裂为上下两部分，上部为表面覆盖二氧化硅的硅片A，下部为没有覆盖二氧化硅的硅片B，所得结构如图4所示。
通过湿法刻蚀工艺去除硅片A表面的二氧化硅201，并采用化学机械抛光方法平坦化硅片A的底部，从而获得用于制作硅通孔的基底，所得结构如图5所示。至于硅片B，可以采用上述工艺继续剥离从而可以获得更多片可以用于制作硅通孔的基底。采用向硅片中注入氢离子剥离硅片的方式来获得制备硅通孔的基底，可以充分利用硅材料，节约成本。
步骤S2：形成硅通孔。在上述所获得的硅基底200上下表面旋涂光刻胶203，并通过曝光和显影工艺定义出硅通孔的图形，所得结构如图6所示。请参照图6， 对硅基底200的上下表面图形处同时进行等离子体刻蚀，直到硅基底200贯通。随后在溶剂中溶解或灰化去除光刻胶203，所得结构如图7所示。其中所采用的等离子体可以选择CF 4、SF 6中的至少一种。对硅基底进行双面等离子体刻蚀从而获得硅通孔，可以增大刻蚀速率，提高生产效率。
步骤S3：形成绝缘介质、铜扩散阻挡层和籽晶层。采用化学气相沉积方法在硅通孔的侧壁及基底的上下表面沉积一层SiO 2薄膜作为绝缘介质205；然后采用物理气相沉积方法在SiO 2薄膜205表面生长一层TaN薄膜作为铜扩散阻挡层206；接着采用物理气相沉积方法在TaN薄膜206表面生长一层Cu薄膜作为籽晶层207，所得结构如图8所示。在本发明中采用SiO 2作为绝缘介质，采用TaN作为铜扩散阻挡层，采用Cu薄膜作为籽晶层，但是本发明不限定于此，可以选择SiO 2、Si 3N 4、SiON、SiCOH、SiCOFH中的至少一种作为绝缘介质；可以选择TaN、TiN、ZrN、MnSiO 3中的至少一种作为铜扩散阻挡层；可以选择Cu、Ru、Co、RuCo、CuRu、CuCo中的至少一种作为籽晶层。铜扩散阻挡层和籽晶层的生长方式也可以选择化学气相沉积或者原子层沉积。
最后采用光刻和刻蚀工艺去除部分TaN阻挡层206和部分Cu籽晶层207，所得结构如图9所示。其中剩余的TaN阻挡层206只覆盖硅通孔侧壁的SiO 2薄膜205表面；相应地，剩余的Cu籽晶层207只覆盖硅通孔侧壁的TaN阻挡层206表面。
步骤S4：电镀铜以及形成接触焊点。首先在上述结构表面旋涂光刻胶，并通过曝光和显影定义出图形。然后采用电子束蒸发工艺生长一层金属Ni薄膜作为牺牲层208，接着采用剥离(lift-off)工艺在溶剂中去除光刻胶以及光刻胶表面的金属Ni薄膜，所得结构如图10所示。随后采用电镀工艺在硅通孔中电镀铜材料209并完全填充硅通孔，所得结构如图11所示。进一步，采用光刻和刻蚀工艺去除金属Ni薄膜208，所得结构如图12所示。如图12所示，导电金属材料209分别下上下延伸出硅通孔的，其上表面高于绝缘介质205的上表面，其下表面低于绝缘介质205的上表面。
最后在铜材料209表面焊接金属Sn材料作为接触焊点210，所得结构如图13所示。在本发明中采用金属Ni薄膜作为牺牲层，但是本发明不限定于此，可以选择Ni、Ti、Ta、Cr中的任意一种作为牺牲层。在电镀铜之后无需化学机械抛光铜材料，可以极大减少工艺复杂度。
本发明的用于三维集成电路封装的硅通孔结构，如图13所示，包括：贯通基底的硅通孔；绝缘介质205，覆盖硅通孔的侧壁以及基底上下表面。铜扩散阻挡层206以及籽晶层207，其中，所述铜扩散阻挡层206覆盖硅通孔的侧壁上的所述绝缘介质205，所述籽晶层207覆盖铜扩散阻挡层206表面；导电金属材料209以及接触焊点210，其中，所述导电金属材料209完全填充所述硅通孔，并向上和向下延伸，突出于所述绝缘介质205的上下表面；接触焊点210置于所述导电金属材料209的顶部和底部。
优选地，绝缘介质205是SiO 2、Si 3N 4、SiON、SiCOH、SiCOFH中的至少一种。铜扩散阻挡层206是TaN、TiN、ZrN、MnSiO 3中的至少一种。籽晶层207是Cu、Ru、Co、RuCo、CuRu、CuCo中的至少一种。牺牲层208可以是Ni、Ti、Ta、Cr中的任意一种。导电金属材料209例如为铜。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。

Claims (10)

  1. 一种用于三维集成电路封装的硅通孔结构制造方法，其特征在于，具体步骤为：
    通过向硅片(200)中注入氢离子(202)剥离硅片，获得制备硅通孔的基底；
    对基底进行双面等离子体刻蚀，从而将基底贯通形成硅通孔；
    在所述硅通孔的侧壁和所述基底的上下表面依次沉积绝缘介质(205)、铜扩散阻挡层(206)和籽晶层(207)，采用光刻和刻蚀工艺去除部分所述铜扩散阻挡层(206)和所述籽晶层(207)，仅保留所述硅通孔的侧壁处的所述铜扩散阻挡层(206)和所述籽晶层(207)；
    在上述结构的上下表面形成牺牲层(208)，在所述硅通孔中完全填充导电金属材料(209)，然后去除所述牺牲层(208)，所述导电金属材料(209)的上下表面分别突出于所述绝缘介质(205)的上下表面；
    在所述导电金属材料(209)表面形成接触焊点(210)。
  2. 根据权利要求1所述的用于三维集成电路封装的硅通孔结构制造方法，其特征在于，所述获得制备硅通孔的基底的步骤，具体包括：
    首先，采用热氧化方法在硅片(200)表面生长一层二氧化硅薄膜(201)；
    然后，采用离子注入方式向所述硅片(200)中注入氢离子(202)，所述氢离子(202)通过所述二氧化硅(201)向所述硅片(200)内部扩散；
    之后，对所述硅片(200)进行退火，使注氢处微空腔内氢气发泡，硅片(200)发生剥离，成为上下两部分；
    最后，通过湿法刻蚀工艺去除剥离后的上部硅片表面的二氧化硅(201)，并采用化学机械抛光方法平坦化上部硅片的底部，从而获得用于制作硅通孔的基底。
  3. 根据权利要求2所述的用于三维集成电路封装的硅通孔结构制造方法，其特征在于，所选氢离子注入能量大于5000KeV，以获得深度大于50微米的硅通孔。
  4. 根据权利要求2所述的用于三维集成电路封装的硅通孔结构制造方法，其特征在于，对所述硅片进行退火的温度范围为300～400℃。
  5. 根据权利要求1所述的用于三维集成电路封装的硅通孔结构制造方法，其特征在于，所述导电金属材料为铜。
  6. 一种用于三维集成电路封装的硅通孔结构，其特征在于，包括：
    贯通基底的硅通孔；
    绝缘介质(205)，覆盖硅通孔的侧壁以及基底的上下表面；
    铜扩散阻挡层(206)以及籽晶层(207)，其中，所述铜扩散阻挡层(206)覆盖所述硅通孔的侧壁上的所述绝缘介质(205)表面，所述籽晶层(207)覆盖所述铜扩散阻挡层(206)表面；
    导电金属材料(209)以及接触焊点(210)，其中，所述导电金属材料(209)完全填充所述硅通孔，并向上和向下延伸，突出于所述绝缘介质(205)的上下表面；接触焊点(210)置于所述导电金属材料(209)的顶部和底部。
  7. 根据权利要求6所述的用于三维集成电路封装的硅通孔结构，其特征在于，所述导电金属材料(209)为铜。
  8. 根据权利要求6所述的用于三维集成电路封装的硅通孔结构，其特征在于，所述绝缘介质(205)是SiO 2、Si 3N 4、SiON、SiCOH、SiCOFH中的至少一种。
  9. 根据权利要求6所述的用于三维集成电路封装的硅通孔结构，其特征在于，所述铜扩散阻挡层(206)是TaN、TiN、ZrN、MnSiO 3中的至少一种。
  10. 根据权利要求6所述的用于三维集成电路封装的硅通孔结构，其特征在于，所述籽晶层(207)是Cu、Ru、Co、RuCo、CuRu、CuCo中的至少一种。
PCT/CN2020/099977 2020-06-18 2020-07-02 一种用于三维集成电路封装的硅通孔结构及其制造方法 WO2021253513A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/052,853 US11887912B2 (en) 2020-06-18 2020-07-02 Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010562310.8 2020-06-18
CN202010562310.8A CN111769077B (zh) 2020-06-18 2020-06-18 一种用于三维集成电路封装的硅通孔结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2021253513A1 true WO2021253513A1 (zh) 2021-12-23

Family

ID=72721196

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/099977 WO2021253513A1 (zh) 2020-06-18 2020-07-02 一种用于三维集成电路封装的硅通孔结构及其制造方法

Country Status (3)

Country Link
US (1) US11887912B2 (zh)
CN (1) CN111769077B (zh)
WO (1) WO2021253513A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112466842B (zh) * 2020-11-24 2022-10-21 复旦大学 一种多功能tsv结构及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426847A (zh) * 2012-05-22 2013-12-04 三星电子株式会社 具有通孔焊盘嵌件的硅通孔(tsv )半导体器件
CN104347492A (zh) * 2013-08-09 2015-02-11 上海微电子装备有限公司 具有高深宽比的通孔结构及多晶片互联的制造方法
CN105405838A (zh) * 2015-09-01 2016-03-16 苏州含光微纳科技有限公司 一种新型tsv转接板及制作方法
CN110010476A (zh) * 2018-10-10 2019-07-12 浙江集迈科微电子有限公司 一种系统级封装结构中的新型电镀填孔工艺
US20200066617A1 (en) * 2016-03-07 2020-02-27 Micron Technology, Inc. Low capacitance through substrate via structures

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
AU2002323388A1 (en) * 2001-08-24 2003-03-10 Mcnc Research & Development Institute Through-via vertical interconnects, through-via heat sinks and associated fabrication methods
JP4564342B2 (ja) * 2004-11-24 2010-10-20 大日本印刷株式会社 多層配線基板およびその製造方法
US9214398B2 (en) * 2013-09-09 2015-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Backside contacts for integrated circuit devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426847A (zh) * 2012-05-22 2013-12-04 三星电子株式会社 具有通孔焊盘嵌件的硅通孔(tsv )半导体器件
CN104347492A (zh) * 2013-08-09 2015-02-11 上海微电子装备有限公司 具有高深宽比的通孔结构及多晶片互联的制造方法
CN105405838A (zh) * 2015-09-01 2016-03-16 苏州含光微纳科技有限公司 一种新型tsv转接板及制作方法
US20200066617A1 (en) * 2016-03-07 2020-02-27 Micron Technology, Inc. Low capacitance through substrate via structures
CN110010476A (zh) * 2018-10-10 2019-07-12 浙江集迈科微电子有限公司 一种系统级封装结构中的新型电镀填孔工艺

Also Published As

Publication number Publication date
CN111769077B (zh) 2021-08-20
US20230099959A1 (en) 2023-03-30
CN111769077A (zh) 2020-10-13
US11887912B2 (en) 2024-01-30

Similar Documents

Publication Publication Date Title
CN111769097B (zh) 一种用于三维互连的硅通孔结构及其制造方法
TWI416679B (zh) 半導體結構及其製造方法
JP2004128063A (ja) 半導体装置及びその製造方法
US7427565B2 (en) Multi-step etch for metal bump formation
CN112466846B (zh) 一种tsv结构及其制备方法
WO2021253513A1 (zh) 一种用于三维集成电路封装的硅通孔结构及其制造方法
US10332850B2 (en) Method for producing contact areas on a semiconductor substrate
JP2013093499A (ja) 接続基板、半導体装置、接続基板の製造方法
CN109037149B (zh) 无缺陷穿硅通孔结构的制备方法
CN111883479B (zh) 一种用于系统级封装的tsv有源转接板制备方法
CN111769075B (zh) 一种用于系统级封装的tsv无源转接板及其制造方法
CN112151496B (zh) 一种内嵌电感的tsv结构及其制备方法
CN112466842B (zh) 一种多功能tsv结构及其制备方法
CN111769078B (zh) 一种用于系统级封装的tsv无源转接板制备方法
CN112018071B (zh) 一种多功能tsv结构及其制备方法
CN112466845B (zh) 一种硅通孔结构及其制备方法
KR100449026B1 (ko) 트렌치를 이용한 금속구조물 제조방법
CN111900127B (zh) 一种用于三维系统级封装的tsv无源转接板制备方法
US5804504A (en) Method for forming wiring of semiconductor device
CN112466840B (zh) 一种tsv结构及其制备方法
CN112466839B (zh) 一种锗硅-硅通孔结构及其制备方法
US11973046B2 (en) Semiconductor structure and method for preparing the same
CN113035810B (zh) 硅通孔结构、封装结构及其制造方法
CN107994023B (zh) 超细孔结构的制成工艺
CN117747542A (zh) 干法刻蚀聚酰亚胺层的方法、再布线层及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20940582

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20940582

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17.05.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20940582

Country of ref document: EP

Kind code of ref document: A1