WO2021248553A1 - 阵列基板及oled显示面板 - Google Patents

阵列基板及oled显示面板 Download PDF

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Publication number
WO2021248553A1
WO2021248553A1 PCT/CN2020/097353 CN2020097353W WO2021248553A1 WO 2021248553 A1 WO2021248553 A1 WO 2021248553A1 CN 2020097353 W CN2020097353 W CN 2020097353W WO 2021248553 A1 WO2021248553 A1 WO 2021248553A1
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WIPO (PCT)
Prior art keywords
layer
barrier
gate
trench
blocking
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Application number
PCT/CN2020/097353
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English (en)
French (fr)
Inventor
梁超
马亮
刘旭阳
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/980,095 priority Critical patent/US11984459B2/en
Publication of WO2021248553A1 publication Critical patent/WO2021248553A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and an OLED display panel.
  • OLED display panels have gradually become the mainstream technology in the display field due to their unique advantages such as low power consumption, high saturation, fast response time and wide viewing angles. In the future, they will have Broad application space.
  • the industry In order to reduce the frame width of the display panel, the industry generally bends the frame part of the display panel to the back side of the display panel to achieve the effect of narrow or no frame.
  • a stepped groove 12 is usually provided at the area to be bent on the film structure 11 of the display panel to reduce the bending stress.
  • the formation of the trench 12 requires the use of multiple photomasks, and the overall process flow is relatively long and the cost is relatively high.
  • the formation of the trench requires the use of multiple photomasks, and the overall process flow is relatively long and the cost is relatively high.
  • the present application provides an array substrate having a display area and a bending area located at a side of the display area, and the array substrate includes:
  • a second film layer group disposed on a side of the first film layer group away from the base substrate;
  • the bending area is provided with a first groove penetrating the first film layer group and a second groove penetrating the second film layer group; the first film layer group is close to the second film layer group.
  • a barrier portion is provided on one side of the film layer group, the barrier portion is provided with an etching opening corresponding to the first groove, the etching opening penetrates the barrier portion, and the bottom end of the etching opening is connected to the The top end of the first trench is connected; the bottom end of the second trench extends to the top surface of the blocking portion, and the orthographic projection of the second trench on the base substrate covers the etching opening in Orthographic projection on the base substrate.
  • the array substrate includes:
  • a buffer layer provided on the base substrate
  • An active layer disposed on the buffer layer
  • a first gate provided on the first gate insulating layer
  • a second gate provided on the second gate insulating layer
  • Source and drain provided on the interlayer dielectric layer
  • the first film layer group includes the buffer layer.
  • the blocking portion includes a blocking block provided in the same layer as at least one of the active layer, the first gate, and the second gate, and the etching opening penetrates through all the blocking blocks.
  • Block the blocking block extends in a first direction, the first direction is parallel to the length direction of the first groove.
  • the barrier block and the active layer when the barrier block and the active layer are arranged on the same layer, the barrier block arranged on the same layer as the active layer and the active layer are formed by the same process; the barrier block and the active layer When the first gate electrode is arranged in the same layer, the barrier block arranged in the same layer as the first gate electrode and the first gate electrode are formed by the same process; the barrier block and the second gate electrode are formed in the same layer During the setting, the barrier block provided on the same layer as the second gate electrode and the second gate electrode are formed by the same process.
  • a plurality of notches extending in the second direction are provided on the end of the blocking block away from the etching opening, and the plurality of notches are arranged at intervals along the first direction.
  • the blocking block includes a plurality of blocking strips arranged at intervals along the first direction.
  • the blocking portion includes a first blocking block and a second blocking block, and the first blocking block is connected to one of the active layer, the first gate, and the second gate. Are arranged in the same layer, and the second blocking block is arranged in the same layer as the other of the active layer, the first gate, and the second gate;
  • the first blocking block includes a plurality of first blocking strips arranged at intervals along a first direction, and a first gap is provided between adjacent first blocking strips;
  • the second blocking block includes a plurality of first blocking strips.
  • Second barrier strips arranged at intervals along the first direction, a second gap is provided between adjacent second barrier strips;
  • the orthographic projection of the first barrier strip on the base substrate covers the first barrier strip
  • the orthographic projection of the two gaps on the base substrate, and the orthographic projection of the second barrier strip on the base substrate covers the orthographic projection of the first gap on the base substrate.
  • the first trench and the second trench are formed by the same process.
  • the interlayer dielectric is provided with a via hole that penetrates the interlayer dielectric layer and extends to the active layer, and the source and drain fill the via hole and are connected to the active layer. Electrically connected, the via hole is formed with the first trench and the second trench through the same process.
  • the present application also provides an OLED display panel.
  • the OLED display panel includes an array substrate having a display area and a bending area located at a side of the display area, and the array substrate includes:
  • a second film layer group disposed on a side of the first film layer group away from the base substrate;
  • the bending area is provided with a first groove penetrating the first film layer group and a second groove penetrating the second film layer group; the first film layer group is close to the second film layer group.
  • a barrier portion is provided on one side of the film layer group, the barrier portion is provided with an etching opening corresponding to the first groove, the etching opening penetrates the barrier portion, and the bottom end of the etching opening is connected to the The top end of the first trench is connected; the bottom end of the second trench extends to the top surface of the blocking portion, and the orthographic projection of the second trench on the base substrate covers the etching opening in Orthographic projection on the base substrate;
  • the OLED display panel further includes:
  • An anode metal layer and a pixel definition layer provided on the array substrate;
  • a cathode layer disposed on the pixel defining layer, the supporting column, and the luminescent material layer.
  • the array substrate includes:
  • a buffer layer provided on the base substrate
  • An active layer disposed on the buffer layer
  • a first gate provided on the first gate insulating layer
  • a second gate provided on the second gate insulating layer
  • Source and drain provided on the interlayer dielectric layer
  • the first film layer group includes the buffer layer.
  • the blocking portion includes a blocking block provided in the same layer as at least one of the active layer, the first gate, and the second gate, and the etching opening penetrates through all the blocking blocks.
  • Block the blocking block extends in a first direction, the first direction is parallel to the length direction of the first groove.
  • the barrier block and the active layer when the barrier block and the active layer are arranged on the same layer, the barrier block arranged on the same layer as the active layer and the active layer are formed by the same process; the barrier block and the active layer When the first gate electrode is arranged in the same layer, the barrier block arranged in the same layer as the first gate electrode and the first gate electrode are formed by the same process; the barrier block and the second gate electrode are formed in the same layer During the setting, the barrier block provided on the same layer as the second gate electrode and the second gate electrode are formed by the same process.
  • a plurality of notches extending in the second direction are provided on the end of the blocking block away from the etching opening, and the plurality of notches are arranged at intervals along the first direction.
  • the blocking block includes a plurality of blocking strips arranged at intervals along the first direction.
  • the blocking portion includes a first blocking block and a second blocking block, and the first blocking block is connected to one of the active layer, the first gate, and the second gate. Are arranged in the same layer, and the second blocking block is arranged in the same layer as the other of the active layer, the first gate, and the second gate;
  • the first blocking block includes a plurality of first blocking strips arranged at intervals along a first direction, and a first gap is provided between adjacent first blocking strips;
  • the second blocking block includes a plurality of first blocking strips.
  • Second barrier strips arranged at intervals along the first direction, a second gap is provided between adjacent second barrier strips;
  • the orthographic projection of the first barrier strip on the base substrate covers the first barrier strip
  • the orthographic projection of the two gaps on the base substrate, and the orthographic projection of the second barrier strip on the base substrate covers the orthographic projection of the first gap on the base substrate.
  • the first trench and the second trench are formed by the same process.
  • the interlayer dielectric is provided with a via hole that penetrates the interlayer dielectric layer and extends to the active layer, and the source and drain fill the via hole and are connected to the active layer. Electrically connected, the via hole is formed with the first trench and the second trench through the same process.
  • the first groove extends along its length to penetrate through the front and back sides of the first film layer set, and the second groove extends along its length to penetrate the second film layer. The front and back sides of the group.
  • the first trench is in communication with the second trench, and the orthographic projection of the second trench on the base substrate covers the first trench on the base substrate. Orthographic projection on.
  • the barrier portion By using the barrier portion provided on the first film layer group, in the preparation process of the array substrate, after the second trench is formed by etching at the preset position of the second film layer group, the barrier portion can be used as a mask for the first film layer group.
  • the film layer group is etched, and at the same time, due to the blocking effect of the barrier portion, the etching solution can only flow into the first film layer group through the etching opening on the barrier portion, so that the first film layer group can be etched to form a predetermined shape of the first film layer group.
  • a trench, the first trench, the second trench, and the via hole connecting the source drain and the active layer can be formed in a single etching process, thereby reducing the mask without reducing the array performance of the array substrate. Quantity and illumination process shorten the overall process flow and reduce costs.
  • FIG. 1 is a schematic diagram of the structure of a display panel in the background art of this application.
  • FIG. 2 is a schematic diagram of the first structure of the array substrate in the specific embodiment of this application;
  • FIG. 3 is a schematic diagram of the second structure of the array substrate in the specific embodiment of this application.
  • FIG. 4 is a schematic diagram of a third structure of the array substrate in the specific embodiment of this application.
  • FIG. 5 is a schematic diagram of the first structure of the blocking block in the specific implementation of this application.
  • FIG. 6 is a schematic diagram of a fourth structure of the array substrate in the specific embodiment of this application.
  • FIG. 7 is a schematic diagram of the second structure of the blocking block in the specific implementation of this application.
  • FIG. 8 is a schematic diagram of the third structure of the blocking block in the specific implementation of this application.
  • 9 to 13 are schematic diagrams of the preparation process of the array substrate in an embodiment when the barrier includes a single-layer barrier in this application;
  • 14 to 17 are schematic diagrams of the preparation process of the array substrate in an embodiment when the barrier includes a double-layer barrier in this application;
  • FIG. 18 is a schematic diagram of the structure of an OLED display panel in an embodiment of the application.
  • the present application addresses the technical problems of the existing OLED display panel that the formation of the trench requires the use of multiple photomasks, the overall process flow is relatively long, and the cost is relatively high.
  • the array substrate 20 has a display area 21 and a bending area 22 located on the side of the display area 21; the display area 21 can be used for displaying images, and the bending area
  • the bending area 22 refers to the area that needs to be bent toward the back side of the array substrate 20.
  • the bending area 22 can be provided with connecting wires and binding terminals.
  • the connecting wires are used to connect the wires in the display area 21 (such as scanning lines). And data lines) and external drive chips, so as to transmit the drive signals output by the drive chips to the wiring in the display area 21; the binding terminals can connect the drive chips with the array substrate 20 and bind them on the array substrate 20.
  • the array substrate 20 includes a base substrate 23, a first film layer group 24 disposed on the base substrate 23, and a first film layer group 24 disposed on the first film layer group 24 away from the base substrate 23.
  • the second film layer group 25 on the side.
  • the base substrate 23 is a flexible substrate, and the preparation material of the base substrate 23 may be polyimide and other materials with high temperature resistance, wide application range, high insulation performance and stable dielectric constant; the first The film layer group 24 and the second film layer group 25 may be a single-layer film structure or a multi-layer functional film layer.
  • a first groove 241 penetrating the first film layer group 24 and a second groove 251 penetrating the second film layer group 25 are provided at the bending area 22; the first groove The groove 241 extends along its length to pass through the front and back sides of the first film layer set 24, and the second groove 251 extends along its length to pass through the front and back sides of the second film layer set 25, thereby
  • the first groove 241 and the second groove 251 are used to buffer and release the bending stress, so as to reduce the bending stress at the bending portion when the bending region 22 is bent, and improve the bending resistance of the array substrate 20.
  • the first trench 241 communicates with the second trench 251, and the orthographic projection of the second trench 251 on the base substrate 23 covers the first trench 241 on the substrate 23. Orthographic projection on the substrate 23.
  • a blocking portion 26 is provided on the side of the first film layer group 24 close to the second film layer group 25, and an etching corresponding to the first trench 241 is provided on the blocking portion 26.
  • An opening 261, the etching opening 261 penetrates the blocking portion 26, and the etching opening 261 is in communication with the first trench 241 and the second trench 242.
  • the bottom end of the etching opening 261 is connected to the top end of the first trench 241, that is, the orthographic projection of the bottom end of the etching opening 261 on the base substrate 23 and the first trench 241
  • the top end of the second groove 251 coincides with the orthographic projection on the base substrate 23; the bottom end of the second groove 251 extends to the top surface of the blocking portion 26, and the second groove 251 is on the base substrate 23
  • the upper orthographic projection covers the orthographic projection of the etching opening 261 on the base substrate 23.
  • the blocking portion 26 is formed on the first film layer set 24.
  • the blocking portion 26 can be formed at the same time by using techniques such as half mask.
  • the blocking portion 26 can be used as a mask to etch the first film layer group 24 without the need for a photomask, photoresist, etc.
  • a first trench 241 penetrating through the first film layer group 24 can be formed.
  • the etching solution can only flow into the first film layer group 24 through the etching opening 261, so that the first film layer group 24 can be
  • the group 24 is etched to form a first trench 241 of a preset shape, and the first trench 241 and the second trench 251 form a stepped structure, thereby reducing the photomask while ensuring that the array performance of the array substrate 20 is not reduced.
  • Quantity and illumination process shorten the overall process flow and reduce costs.
  • first trench 241 and the second trench 251 are formed by the same process.
  • the etching solution can still flow into the first film layer group 24 through the etching opening 261, so that it can be During the etching process, the first trench 241 penetrating the first film layer set 24 and the second trench 251 penetrating the second film layer set 25 are simultaneously etched, which further reduces the number of photomasks and shortens the overall process flow.
  • the vertical cross-section of the first trench 241 and the vertical cross-section of the second trench 251 may both be in the shape of an inverted trapezoid, and the acute angle formed by the sidewall of the first trench 241 and the horizontal plane is less than 70%.
  • the acute angle formed by the sidewall of the second trench 251 and the horizontal plane is less than 70 degrees; the depth of the first trench 241 may be 0.7 to 1.3 microns, and the depth of the second trench 251 may be 0.1 ⁇ 0.8 microns.
  • film layers may also be provided between the second film layer group 25 and the first film layer group 24.
  • the array substrate 20 includes a buffer layer 271 disposed on the base substrate 23; an active layer 272 disposed on the buffer layer 271; a first layer covering the active layer 272 A gate insulating layer 273; a first gate 274 disposed on the first gate insulating layer 273; a second gate insulating layer 275 covering the first gate 274; disposed on the second gate
  • the first film layer group 24 includes the buffer layer 271, and the first trench 241 penetrates the buffer layer 271.
  • the array substrate 20 further includes a protective layer 28 disposed on the base substrate 23, and the buffer layer 271 is disposed on the protective layer 28; the first trench 241 extends to In the protection layer 28, and the depth of the first trench 241 in the protection layer 28 is less than the thickness of the protection layer 28, the protection layer 28 is used to protect the base substrate 23 and prevent the first trench from being etched. The etching solution damages the base substrate 23 when the trench 241 is formed.
  • the interlayer dielectric is provided with a via 291 that penetrates the interlayer dielectric layer 277 and extends to the active layer 272, and the source and drain 278 fill the via 291 and are connected to the active layer 272.
  • the source layer 272 is electrically connected, and the via 291 is formed with the first trench 241 and the second trench 251 through the same process, so as to further reduce the number of photomasks and the illumination process, and reduce the production cost.
  • the via 291 penetrates the active layer 272 and extends into the buffer layer 271 to increase the contact area between the source and drain 278 and the active layer 272.
  • the flat layer 279 fills the first groove 241 and the second groove 251, and the flat layer 279 is made of organic material, so that the bending area 22 has strong bending resistance. At the same time, it prevents the small thickness at the bending zone 22 from causing cracks during bending.
  • the blocking portion 26 includes a blocking block 262 provided on the same layer as at least one of the active layer 272, the first gate 274, and the second gate 276, and the etching opening 261 Passing through all the blocking blocks 262; the blocking blocks 262 extend in a first direction, and the length directions of the first grooves 241 and the second grooves 251 are parallel to the first direction.
  • the blocking block 262 in the same layer as at least one of the active layer 272, the first gate 274, and the second gate 276, the blocking block can be used While 262 forms the first trench 241 with a predetermined shape, the blocking block 262 does not increase the overall thickness of the array substrate 20.
  • the blocking block 262 and the active layer 272 are arranged in the same layer, the blocking block 262 arranged in the same layer as the active layer 272 and the active layer 272 are formed by the same process;
  • the block 262 and the first gate electrode 274 are arranged in the same layer, the barrier block 262 arranged in the same layer as the first gate electrode 274 and the first gate electrode 274 are formed by the same process;
  • the second gate electrode 276 is arranged in the same layer, the blocking block 262 arranged in the same layer as the second gate electrode 276 and the second gate electrode 276 are formed by the same process.
  • a blocking block 262 can be formed in the same layer as the active layer 272, and when the first gate 274 is patterned, it can be formed in the same layer as the first gate 274.
  • the second gate electrode 276 can be patterned to form the stopper block 262 provided on the same layer as the second gate electrode 276, thereby further reducing the number of photomasks, shortening the overall process flow, and reducing costs.
  • the blocking portion 26 has a single-layer structure, that is, the blocking portion 26 includes only one layer of the blocking block 262.
  • the blocking block 262 may be connected to the active layer 272, the One of the first gate 274 and the second gate 276 is arranged in the same layer.
  • the second film layer group 25 includes the first gate insulating layer 273 and the second gate insulating layer 273.
  • the gate insulating layer 275 and the interlayer dielectric layer 277, and a part of the blocking block 262 is covered by the first gate insulating layer 273.
  • the blocking portion 26 has a double-layer structure, that is, the blocking portion 26 includes two layers of blocking blocks 262 located in different layers.
  • the blocking block 262 of one layer can be connected to the one layer.
  • One of the source layer 272, the first gate 274, and the second gate 276 is provided in the same layer, and the blocking block 262 of the other layer may be the same layer as the active layer 272 and the first gate. 274 and the other of the second gate 276 are arranged in the same layer.
  • the second film layer group 25 includes the second gate insulating layer 275 and the interlayer dielectric layer 277, and at least a part of the blocking block 262 provided close to the base substrate 23 is covered by the first gate electrode.
  • the insulating layer 273 is covered, the part of the stopper 262 that is away from the base substrate 23 is covered by the second gate insulating layer 275, and the etching opening 261 penetrates through the two layers of the stopper 262.
  • the blocking portion 26 has a three-layer structure, that is, the blocking portion 26 includes three layers of blocking blocks 262 located in different layers.
  • the blocking blocks 262 of the first layer can be connected to the active layer.
  • the layer 272 is arranged in the same layer
  • the blocking block 262 of the second layer may be arranged in the same layer as the first gate 274, and the blocking block 262 in the third layer may be arranged in the same layer as the second gate 276.
  • the second film layer group 25 includes the interlayer dielectric layer 277, and the part of the blocking block 262 with the largest distance from the base substrate 23 is covered by the second gate insulating layer 275.
  • a plurality of notches 262a extending in the second direction are provided on the end of the blocking block 262 away from the etching opening 261, and the plurality of notches 262a extend along the first direction.
  • One direction is arranged at intervals, and the second direction may be perpendicular to the first direction.
  • the etching solution will flow into the first film layer group 24 through the notch 262a, thereby A wiring groove 292 is etched in the buffer layer 271 under the notch 262a, so that a large amount of etching solution can be prevented from remaining in the array substrate 20, and at the same time, the wiring (such as a scan line) in the display area 21 can be routed from the notch 262a. Lead out from the wire slot 292, so that the wires in the display area 21 are connected to the connecting wires arranged at the bending area 22. At the same time, a gap 262a can be set to correspond to one wire to prevent multiple wires from being connected. A short circuit occurred between.
  • the orthographic projections of all the notches 262a on the blocking blocks 262 on the base substrate 23 may overlap, intersect or be spaced apart.
  • the blocking block 262 includes a plurality of blocking strips 262b arranged at intervals along the first direction, and gaps are provided between adjacent blocking strips 262b.
  • the orthographic projections of all the gaps on the blocking blocks 262 on the base substrate 23 may overlap, intersect or be spaced apart.
  • the blocking portion 26 when the blocking portion 26 includes two or three layers of the blocking blocks 262, the blocking portion 26 includes a first blocking block and a second blocking block, and the first blocking block is connected to the One of the active layer 272, the first gate 274, and the second gate 276 is provided in the same layer, and the second blocking block is the same layer as the active layer 272 and the first gate. 274 and the other of the second gate 276 are arranged in the same layer.
  • the first blocking block 262 includes a plurality of first blocking strips 263a arranged at intervals along the first direction, and a first gap 263b is provided between adjacent first blocking strips 263a; the second blocking strips 263a
  • the block 262 includes a plurality of second barrier strips 264a arranged at intervals along the first direction, and a second gap 264b is provided between adjacent second barrier strips 264a; the first barrier strips 263a are located on the substrate
  • the orthographic projection on the substrate 23 covers the orthographic projection of the second gap 264b on the base substrate 23, and the orthographic projection of the second barrier strip 264a on the base substrate 23 covers the first gap 263b
  • the orthographic projection on the base substrate 23 can form a plurality of spaced wiring grooves 292 on different film layers, which is convenient to lead the wiring in the display area 21, and at the same time can avoid a large amount of etching liquid in the first Etching the same part of the film layer group 24 causes the base substrate 23 to be damaged by the etching solution.
  • FIGS. 9 to 13 are schematic diagrams of the preparation process of the array substrate 20 in an embodiment when the blocking portion 26 includes a single-layer blocking block 262.
  • the blocking block 262 and the active layer 272 are arranged in the same layer as an example.
  • the protective layer 28 and the buffer layer 271 are sequentially stacked on the base substrate 23 using inorganic materials; the buffer layer 271 is used to form an amorphous layer covering the entire surface with an amorphous silicon material; laser processing is performed on the amorphous silicon layer Forming a polysilicon layer; patterning the amorphous silicon layer to form an active layer 272 and a barrier block 262 spaced apart; forming a layer covering the active layer 272, the barrier block 262 and the buffer layer 271 The first gate insulating layer 273.
  • a first metal layer is formed on the first gate insulating layer 273, and the first metal layer is patterned to form the first gate 274, and then ion implantation and doping is performed on the first gate 274. Miscellaneous process; forming a second gate insulating layer 275 covering the first gate 274 and the first gate insulating layer 273; forming a second metal layer on the second gate insulating layer 275, and The second metal layer is patterned to form a second gate 276; an interlayer dielectric layer 277 covering the second gate 276 and the second gate insulating layer 275 is formed.
  • an etching solution is used to etch a via 291 that penetrates the active layer 272 and extends to the buffer layer 271 on the interlayer dielectric layer 277, and at the same time, is etched on the interlayer dielectric layer 277
  • the first trench 241 that is located in the bending area 22 and penetrates the buffer layer 271 and the second trench 251 that penetrates the first gate insulating layer 273, the second gate insulating layer 275 and the interlayer dielectric layer 277, the via 291 and the first trench 241 and the second trench 251 are formed by the same etching process.
  • a third metal layer is formed on the interlayer dielectric layer 277, and the third metal layer is patterned to form the source and drain electrodes 278 filling the via holes 291.
  • the transfer terminal 293 located in the first trench 241 can be formed at the same time, and the transfer terminal 293 can be used to connect the driving chip and the display area 21. In order to facilitate the connection between the driver chip and the wiring in the display area 21.
  • a flat layer 279 covering the source and drain electrodes 278 and filling the first trench 241 and the second trench 251 is formed on the interlayer dielectric layer 277.
  • the blocking block 262 and the first gate 274 are arranged in the same layer, the blocking block 262 can be formed at the same time when the first metal layer is patterned to form the first gate 274;
  • the blocking block 262 and the second gate 276 are arranged in the same layer, the blocking block 262 can be formed at the same time when the second metal layer is patterned to form the second gate 276.
  • FIG. 14 to FIG. 17 are schematic diagrams of the preparation process of the array substrate 20 in an embodiment when the blocking portion 26 includes a double-layer blocking block 262.
  • one layer of the blocking block 262 and the active layer 272 is provided in the same layer, and the other layer of the blocking block 262 is provided in the same layer as the first gate 274 as an example.
  • the protective layer 28 and the buffer layer 271 are sequentially stacked using inorganic materials on the base substrate 23; an amorphous silicon material is used to form an entire surface-covered amorphous layer on the buffer layer 271; laser processing is performed on the amorphous silicon layer To form a polysilicon layer; pattern the amorphous silicon layer to form an active layer 272 spaced apart from the first layer of the barrier block 262; form to cover the active layer 272, the barrier block 262, and The first gate insulating layer 273 of the buffer layer 271.
  • a first metal layer is formed on the first gate insulating layer 273, and the first metal layer is patterned to form a first gate 274 and a space spaced from the first gate 274.
  • an ion implantation doping process is performed on the first gate 274; a second gate insulating layer 275 covering the first gate 274 and the first gate insulating layer 273 is formed;
  • a second metal layer is formed on the second gate insulating layer 275, and the second metal layer is patterned to form a second gate 276; forming a cover covering the second gate 276 and the second gate
  • the interlayer dielectric layer 277 of the polar insulating layer 275 is formed on the first gate insulating layer 273, and the first metal layer is patterned to form a first gate 274 and a space spaced from the first gate 274.
  • an ion implantation doping process is performed on the first gate 274; a second gate insulating layer 275 covering the first gate 274 and the first gate insulating layer 273 is formed;
  • an etching solution is used to etch through the active layer 272 and extend to the buffer layer 271 via holes 291 on the interlayer dielectric layer 277, while etching on the interlayer dielectric layer 277
  • the via 291 and the first trench 241 and the second trench 251 are formed by the same etching process.
  • a third metal layer is formed on the interlayer dielectric layer 277, and the third metal layer is patterned to form source and drain electrodes 278 filling the via holes 291;
  • a flat layer 279 covering the source and drain electrodes 278 and filling the first trench 241 and the second trench 251 is formed on the dielectric layer 277.
  • the present application also provides an OLED display panel.
  • the OLED display panel includes the array substrate 20 as described in any of the above-mentioned embodiments.
  • the OLED display panel further includes an anode metal layer 30 and a pixel definition layer 40 arranged on the array substrate 20, a luminescent material layer 50 arranged on the anode metal layer 30, and a pixel definition layer 50 arranged on the anode metal layer 30.
  • the anode metal layer 30 and the pixel definition layer 40 are disposed on the flat layer 279 of the array substrate 20.
  • the beneficial effect of the present application is that by using the blocking portion 26 provided on the first film layer group 24, during the preparation process of the array substrate 20, the second trench 251 is formed by etching at a preset position of the second film layer group 25 Afterwards, the blocking part 26 can be used as a mask to etch the first film layer group 24. At the same time, due to the blocking effect of the blocking part 26, the etching solution can only flow into the first film layer group 24 through the etching opening 261 on the blocking part 26. Therefore, a first trench 241 of a predetermined shape, a first trench 241, a second trench 251, and a via 291 connecting the source and drain electrodes 278 and the active layer 272 can be etched on the first film layer group 24. It can be formed in one etching process, so as to reduce the number of photomasks and the illumination process, shorten the overall process flow, and reduce the cost while ensuring that the array performance of the array substrate 20 is not reduced.

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Abstract

一种阵列基板(20)及OLED显示面板，阵列基板(20)包括衬底基板(23)以及层叠设置的第一膜层组(24)和第二膜层组(25)；阵列基板(20)的弯折区(22)处设置有贯穿第一膜层组(24)的第一沟槽(241)以及贯穿第二膜层组(25)的第二沟槽(251)；第一膜层组(24)上设置有带有蚀刻开口(261)的阻挡部(26)，蚀刻开口(261)的底端与第一沟槽(241)的顶端连接；第二沟槽(251)的底端延伸至阻挡部(26)的顶面。

Description

阵列基板及OLED显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及OLED显示面板。
 背景技术
有机电致发光（OLED）显示面板以其低功耗、高饱和度、快响应时间及宽视角等独特优势逐渐成为显示领域的主流技术，未来在车载、手机、平板、电脑及电视产品上具有广阔的应用空间。为了减少显示面板的边框宽度，行业内一般会将显示面板的边框部分弯折至显示面板的背侧，以达到窄边框或无边框的效果。如图1所示，为了便于显示面板的弯折，通常会在显示面板的膜层结构11上的待弯折区域处开设阶梯状的沟槽12，以减小弯曲应力。
然而，沟槽12的形成需要使用到多道光罩，整体的工艺流程较长，成本较高。
 技术问题
现有的OLED显示面板中，沟槽的形成需要使用到多道光罩，整体的工艺流程较长，成本较高的技术问题。
 技术解决方案
第一方面，本申请提供一种阵列基板，所述阵列基板具有显示区和位于所述显示区的侧部的弯折区，所述阵列基板包括：
衬底基板；
设置于所述衬底基板上的第一膜层组；
设置于所述第一膜层组远离所述衬底基板的一侧的第二膜层组；
其中，所述弯折区处设置有贯穿所述第一膜层组的第一沟槽以及贯穿所述第二膜层组的第二沟槽；所述第一膜层组靠近所述第二膜层组的一侧上设置有阻挡部，所述阻挡部上设置有与所述第一沟槽对应的蚀刻开口，所述蚀刻开口贯穿所述阻挡部，所述蚀刻开口的底端与所述第一沟槽的顶端连接；所述第二沟槽的底端延伸至所述阻挡部的顶面，所述第二沟槽在所述衬底基板上的正投影覆盖所述蚀刻开口在所述衬底基板上的正投影。
在一些实施例中，所述阵列基板包括：
设置于所述衬底基板上的缓冲层；
设置于所述缓冲层上的有源层；
覆盖所述有源层的第一栅极绝缘层；
设置于所述第一栅极绝缘层上的第一栅极；
覆盖所述第一栅极的第二栅极绝缘层；
设置于所述第二栅极绝缘层上的第二栅极；
覆盖所述第二栅极的层间介质层；
设置于所述层间介质层上的源漏极；
覆盖所述源漏极的平坦层；
其中，所述第一膜层组包括所述缓冲层。
在一些实施例中，所述阻挡部包括与所述有源层、所述第一栅极以及所述第二栅极中的至少一者同层设置的阻挡块，所述蚀刻开口贯穿所有阻挡块；所述阻挡块沿第一方向延伸，所述第一方向与所述第一沟槽的长度方向平行。
在一些实施例中，所述阻挡块与所述有源层同层设置时，与所述有源层同层设置的阻挡块与所述有源层通过同一道工艺形成；所述阻挡块与所述第一栅极同层设置时，与所述第一栅极同层设置的阻挡块与所述第一栅极通过同一道工艺形成；所述阻挡块与所述第二栅极同层设置时，与所述第二栅极同层设置的阻挡块与所述第二栅极通过同一道工艺形成。
在一些实施例中，所述阻挡块上远离所述蚀刻开口的一端设置有多条沿第二方向延伸的缺口，多条所述缺口沿第一方向相间隔排布。
在一些实施例中，所述阻挡块包括多条沿第一方向相间隔排布的阻挡条。
在一些实施例中，所述阻挡部包括第一阻挡块以及第二阻挡块，所述第一阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的一者同层设置，所述第二阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的另一者同层设置；
其中，所述第一阻挡块包括多条沿第一方向相间隔排布的第一阻挡条，相邻所述第一阻挡条之间设置有第一间隙；所述第二阻挡块包括多条沿第一方向相间隔排布的第二阻挡条，相邻所述第二阻挡条之间设置有第二间隙；所述第一阻挡条在所述衬底基板上的正投影覆盖所述第二间隙在所述衬底基板上的正投影，所述第二阻挡条在所述衬底基板上的正投影覆盖所述第一间隙在所述衬底基板上的正投影。
在一些实施例中，所述第一沟槽与所述第二沟槽通过同一道工艺形成。
在一些实施例中，所述层间介质上设置有贯穿所述层间介质层且延伸至所述有源层的过孔，所述源漏极填充所述过孔且与所述有源层电连接，所述过孔与所述第一沟槽和所述第二沟槽通过同一道工艺形成。
第二方面，本申请还提供一种OLED显示面板，所述OLED显示面板包括阵列基板，所述阵列基板具有显示区和位于所述显示区的侧部的弯折区，所述阵列基板包括：
衬底基板；
设置于所述衬底基板上的第一膜层组；
设置于所述第一膜层组远离所述衬底基板的一侧的第二膜层组；
其中，所述弯折区处设置有贯穿所述第一膜层组的第一沟槽以及贯穿所述第二膜层组的第二沟槽；所述第一膜层组靠近所述第二膜层组的一侧上设置有阻挡部，所述阻挡部上设置有与所述第一沟槽对应的蚀刻开口，所述蚀刻开口贯穿所述阻挡部，所述蚀刻开口的底端与所述第一沟槽的顶端连接；所述第二沟槽的底端延伸至所述阻挡部的顶面，所述第二沟槽在所述衬底基板上的正投影覆盖所述蚀刻开口在所述衬底基板上的正投影；
所述OLED显示面板还包括：
设置于所述阵列基板上的阳极金属层以及像素定义层；
设置于所述阳极金属层上的发光材料层；
设置于所述像素定义层上的支撑柱；
设置于所述像素定义层、所述支撑柱以及所述发光材料层上的阴极层。
在一些实施例中，所述阵列基板包括：
设置于所述衬底基板上的缓冲层；
设置于所述缓冲层上的有源层；
覆盖所述有源层的第一栅极绝缘层；
设置于所述第一栅极绝缘层上的第一栅极；
覆盖所述第一栅极的第二栅极绝缘层；
设置于所述第二栅极绝缘层上的第二栅极；
覆盖所述第二栅极的层间介质层；
设置于所述层间介质层上的源漏极；
覆盖所述源漏极的平坦层；
其中，所述第一膜层组包括所述缓冲层。
在一些实施例中，所述阻挡部包括与所述有源层、所述第一栅极以及所述第二栅极中的至少一者同层设置的阻挡块，所述蚀刻开口贯穿所有阻挡块；所述阻挡块沿第一方向延伸，所述第一方向与所述第一沟槽的长度方向平行。
在一些实施例中，所述阻挡块与所述有源层同层设置时，与所述有源层同层设置的阻挡块与所述有源层通过同一道工艺形成；所述阻挡块与所述第一栅极同层设置时，与所述第一栅极同层设置的阻挡块与所述第一栅极通过同一道工艺形成；所述阻挡块与所述第二栅极同层设置时，与所述第二栅极同层设置的阻挡块与所述第二栅极通过同一道工艺形成。
在一些实施例中，所述阻挡块上远离所述蚀刻开口的一端设置有多条沿第二方向延伸的缺口，多条所述缺口沿第一方向相间隔排布。
在一些实施例中，所述阻挡块包括多条沿第一方向相间隔排布的阻挡条。
在一些实施例中，所述阻挡部包括第一阻挡块以及第二阻挡块，所述第一阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的一者同层设置，所述第二阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的另一者同层设置；
其中，所述第一阻挡块包括多条沿第一方向相间隔排布的第一阻挡条，相邻所述第一阻挡条之间设置有第一间隙；所述第二阻挡块包括多条沿第一方向相间隔排布的第二阻挡条，相邻所述第二阻挡条之间设置有第二间隙；所述第一阻挡条在所述衬底基板上的正投影覆盖所述第二间隙在所述衬底基板上的正投影，所述第二阻挡条在所述衬底基板上的正投影覆盖所述第一间隙在所述衬底基板上的正投影。
在一些实施例中，所述第一沟槽与所述第二沟槽通过同一道工艺形成。
在一些实施例中，所述层间介质上设置有贯穿所述层间介质层且延伸至所述有源层的过孔，所述源漏极填充所述过孔且与所述有源层电连接，所述过孔与所述第一沟槽和所述第二沟槽通过同一道工艺形成。
在一些实施例中，所述第一沟槽沿其长度方向延伸以贯穿所述第一膜层组的前后两侧，所述第二沟槽沿其长度方向延伸以贯穿所述第二膜层组的前后两侧。
在一些实施例中，所述第一沟槽与所述第二沟槽连通，所述第二沟槽在所述衬底基板上的正投影覆盖所述第一沟槽在所述衬底基板上的正投影。
 有益效果
利用设置于第一膜层组上的阻挡部，在阵列基板的制备过程中，在第二膜层组的预设位置处蚀刻形成第二沟槽后，可以利用阻挡部充当掩模板对第一膜层组进行蚀刻，同时由于阻挡部的阻挡作用，蚀刻液只能通过阻挡部上的蚀刻开口流入到第一膜层组上，从而可以在第一膜层组上蚀刻形成预设形状的第一沟槽，第一沟槽、第二沟槽以及连接源漏极和有源层的过孔可以在一道蚀刻工序中形成，从而在保证阵列基板的阵列性能未降低的前提下，减少光罩数量和光照制程，缩短整体的工艺流程，降低成本。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请背景技术中显示面板的结构示意图；
图2为本申请具体实施方式中阵列基板的第一种结构示意图；
图3为本申请具体实施方式中阵列基板的第二种结构示意图；
图4为本申请具体实施方式中阵列基板的第三种结构示意图；
图5为本申请具体实施方式中阻挡块的第一种结构示意图；
图6为本申请具体实施方式中阵列基板的第四种结构示意图；
图7为本申请具体实施方式中阻挡块的第二种结构示意图；
图8为本申请具体实施方式中阻挡块的第三种结构示意图；
图9至图13为本申请中阻挡部包括单层的阻挡块时一实施方式中阵列基板的制备流程示意图；
图14至图17为本申请中阻挡部包括双层的阻挡块时一实施方式中阵列基板的制备流程示意图；
图18为本申请一实施方式中OLED显示面板的结构示意图。
附图标记：
11、膜层结构；12、沟槽；
20、阵列基板；21、显示区；22、弯折区；23、衬底基板；24、第一膜层组；241、第一沟槽；25、第二膜层组；251、第二沟槽；26、阻挡部；261、蚀刻开口；262、阻挡块；262a、缺口；262b、阻挡条；263a、第一阻挡条；263b、第一间隙；264a、第二阻挡条；264b、第二间隙；271、缓冲层；272、有源层；273、第一栅极绝缘层；274、第一栅极；275、第二栅极绝缘层；276、第二栅极；277、层间介质层；278、源漏极；279、平坦层；28、保护层；291、过孔；292、走线槽；293、转接端子；30、阳极金属层；40、像素定义层；50、发光材料层；60、支撑柱；70、阴极层。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有的OLED显示面板中，沟槽的形成需要使用到多道光罩，整体的工艺流程较长，成本较高的技术问题。
一种阵列基板，如图2所示，所述阵列基板20具有显示区21和位于所述显示区21的侧部的弯折区22；所述显示区21可以用于显示画面，所述弯折区22是指需要向阵列基板20的背侧弯折的区域，弯折区22处可以设置连接走线和绑定端子，连接走线用于连接显示区21中的走线（如扫描线和数据线）和外界驱动芯片，从而将驱动芯片输出的驱动信号传输给显示区21中的走线；绑定端子可以将驱动芯片与阵列基板20连接并绑定在阵列基板20上。
具体的，所述阵列基板20包括衬底基板23、设置于所述衬底基板23上的第一膜层组24以及设置于所述第一膜层组24远离所述衬底基板23的一侧的第二膜层组25。
其中，所述衬底基板23为柔性基板，所述衬底基板23的制备材料可以为聚酰亚胺等耐高温、使用范围广、高绝缘性能以及介电常数稳定的材料；所述第一膜层组24和所述第二膜层组25可以为单层膜层结构或多层功能膜层。
具体的，在所述弯折区22处设置有贯穿所述第一膜层组24的第一沟槽241以及贯穿所述第二膜层组25的第二沟槽251；所述第一沟槽241沿其长度方向延伸以贯穿所述第一膜层组24的前后两侧，所述第二沟槽251沿其长度方向延伸以贯穿所述第二膜层组25的前后两侧，从而利用第一沟槽241和第二沟槽251对弯曲应力进行缓冲和释放，以减小弯折区22弯折时弯折处的弯曲应力，提升阵列基板20的耐弯性。
其中，所述第一沟槽241与所述第二沟槽251连通，所述第二沟槽251在所述衬底基板23上的正投影覆盖所述第一沟槽241在所述衬底基板23上的正投影。
具体的，在所述第一膜层组24靠近所述第二膜层组25的一侧上设置有阻挡部26，所述阻挡部26上设置有与所述第一沟槽241对应的蚀刻开口261，所述蚀刻开口261贯穿所述阻挡部26，所述蚀刻开口261与所述第一沟槽241和所述第二沟槽242连通。
其中，所述蚀刻开口261的底端与所述第一沟槽241的顶端连接，即所述蚀刻开口261的底端在所述衬底基板23上的正投影与所述第一沟槽241的顶端在所述衬底基板23上的正投影重合；所述第二沟槽251的底端延伸至所述阻挡部26的顶面，所述第二沟槽251在所述衬底基板23上的正投影覆盖所述蚀刻开口261在所述衬底基板23上的正投影。
需要说明的是，阻挡部26形成于第一膜层组24上，在形成阵列基板20的其他膜层结构时可以利用半掩膜等技术同时形成阻挡部26，而在阵列基板20的制备过程中，在第二膜层组25的预设位置处蚀刻形成第二沟槽251后，可以利用阻挡部26充当掩模板对第一膜层组24进行蚀刻，无需光罩以及光刻胶等即可形成贯穿第一膜层组24的第一沟槽241，同时由于阻挡部26的阻挡作用，蚀刻液只能通过蚀刻开口261流入到第一膜层组24上，从而可以在第一膜层组24上蚀刻形成预设形状的第一沟槽241，并且第一沟槽241与第二沟槽251形成阶梯状结构，从而在保证阵列基板20的阵列性能未降低的前提下，减少光罩数量和光照制程，缩短整体的工艺流程，降低成本。
进一步的，所述第一沟槽241与所述第二沟槽251通过同一道工艺形成。
需要说明的是，在第二膜层组25的预设位置处蚀刻形成第二沟槽251后，此时蚀刻液仍然可以通过蚀刻开口261流入到第一膜层组24中，从而可以在一道蚀刻工艺中同时蚀刻出贯穿所述第一膜层组24的第一沟槽241以及贯穿所述第二膜层组25的第二沟槽251，进一步减少光罩数量，缩短整体的工艺流程。
具体的，所述第一沟槽241的竖向截面和所述第二沟槽251的竖向截面均可以呈倒梯形，所述第一沟槽241的侧壁与水平面所形成的锐角小于70度，所述第二沟槽251的侧壁与水平面所形成的锐角小于70度；所述第一沟槽241的深度可以为0.7～1.3微米，所述第二沟槽251的深度可以为0.1～0.8微米。
在图2中仅示意了所述第二膜层组25设置于所述第一膜层组24上的情况。
需要说明的是，还可以在所述第二膜层组25与所述第一膜层组24之间设置其他膜层。
如图3所示，所述阵列基板20包括设置于所述衬底基板23上的缓冲层271；设置于所述缓冲层271上的有源层272；覆盖所述有源层272的第一栅极绝缘层273；设置于所述第一栅极绝缘层273上的第一栅极274；覆盖所述第一栅极274的第二栅极绝缘层275；设置于所述第二栅极绝缘层275上的第二栅极276；覆盖所述第二栅极276的层间介质层277；设置于所述层间介质层277上的源漏极278以及覆盖所述源漏极278的平坦层279。
具体的，所述第一膜层组24包括所述缓冲层271，所述第一沟槽241贯穿所述缓冲层271。
在一实施方式中，所述阵列基板20还包括设置于所述衬底基板23上的保护层28，所述缓冲层271设置于所述保护层28上；所述第一沟槽241延伸至保护层28中，并且所述第一沟槽241在所述保护层28中的深度小于所述保护层28的厚度，所述保护层28用于保护所述衬底基板23，防止蚀刻第一沟槽241时蚀刻液损坏衬底基板23。
具体的，所述层间介质上设置有贯穿所述层间介质层277且延伸至所述有源层272的过孔291，所述源漏极278填充所述过孔291且与所述有源层272电连接，所述过孔291与所述第一沟槽241和所述第二沟槽251通过同一道工艺形成，以进一步减少光罩数量和光照制程，降低生产成本。
在一实施方式中，所述过孔291贯穿所述有源层272并延伸至所述缓冲层271中，以增加源漏极278与所述有源层272的接触面积。
具体的，所述平坦层279填充所述第一沟槽241和所述第二沟槽251，所述平坦层279由有机材料制成，以使得弯折区22处具有较强的耐弯性能，同时防止弯折区22处的厚度较小导致弯折时产生裂纹。
具体的，所述阻挡部26包括与所述有源层272、所述第一栅极274以及所述第二栅极276中的至少一者同层设置的阻挡块262，所述蚀刻开口261贯穿所有所述阻挡块262；所述阻挡块262沿第一方向延伸，所述第一沟槽241和所述第二沟槽251的长度方向与第一方向平行。
需要说明的是，通过将阻挡块262设置成与所述有源层272、所述第一栅极274以及所述第二栅极276中的至少一者同层设置，从而可以在利用阻挡块262形成预设形状的第一沟槽241的同时，阻挡块262不会增加阵列基板20的整体厚度。
进一步的，所述阻挡块262与所述有源层272同层设置时，与所述有源层272同层设置的阻挡块262与所述有源层272通过同一道工艺形成；所述阻挡块262与所述第一栅极274同层设置时，与所述第一栅极274同层设置的阻挡块262与所述第一栅极274通过同一道工艺形成；所述阻挡块262与所述第二栅极276同层设置时，与所述第二栅极276同层设置的阻挡块262与所述第二栅极276通过同一道工艺形成。
需要说明的是，对有源层272进行图案化时可以形成与有源层272同层设置的阻挡块262，对第一栅极274进行图案化时可以形成与第一栅极274同层设置的阻挡块262，对第二栅极276进行图案化时可以形成与第二栅极276同层设置的阻挡块262，从而可以进一步减少光罩数量，缩短整体的工艺流程，降低成本。
在第一种实施方式中，所述阻挡部26为单层结构，即所述阻挡部26仅包括一层所述阻挡块262，此时阻挡块262可以与所述有源层272、所述第一栅极274以及所述第二栅极276中的一者同层设置。
如图3所示，以所述阻挡块262与所述有源层272同层设置为例，此时所述第二膜层组25包括所述第一栅极绝缘层273、所述第二栅极绝缘层275和所述层间介质层277，所述阻挡块262的部分被所述第一栅极绝缘层273覆盖。
在第二种实施方式中，所述阻挡部26为双层结构，即所述阻挡部26包括二层位于不同层别的阻挡块262，此时一层所述阻挡块262可以与所述有源层272、所述第一栅极274以及所述第二栅极276中的一者同层设置，另一层所述阻挡块262可以与所述有源层272、所述第一栅极274以及所述第二栅极276中的另一者同层设置。
如图4所示，以一层所述阻挡块262与所述有源层272同层设置，另一层所述阻挡块262与所述第一栅极274同层设置为例，此时所述第二膜层组25包括所述第二栅极绝缘层275和所述层间介质层277，靠近所述衬底基板23设置的所述阻挡块262的至少一部分被所述第一栅极绝缘层273覆盖，远离所述衬底基板23设置的所述阻挡块262的部分被所述第二栅极绝缘层275覆盖，蚀刻开口261贯穿两层所述阻挡块262。
在第三种实施方式中，所述阻挡部26为三层结构，即所述阻挡部26包括三层位于不同层别的阻挡块262，第一层所述阻挡块262可以与所述有源层272同层设置，第二层所述阻挡块262可以与所述第一栅极274同层设置，第三层所述阻挡块262可以与所述第二栅极276同层设置，此时所述第二膜层组25包括所述层间介质层277，与所述衬底基板23距离最大的所述阻挡块262的部分被所述第二栅极绝缘层275覆盖。
如图5和图6所示，在一实施方式中，所述阻挡块262上远离所述蚀刻开口261的一端设置有多条沿第二方向延伸的缺口262a，多条所述缺口262a沿第一方向相间隔排布，所述第二方向可以与所述第一方向垂直。
参见图6，需要说明的是，利用阻挡块262在一道工序中同时形成第一沟槽241和第二沟槽251时，蚀刻液会通过缺口262a流入到第一膜层组24中，从而在位于缺口262a下方的缓冲层271中蚀刻形成一走线槽292，从而可以防止大量蚀刻液残留在阵列基板20内，同时可以将显示区21中的走线（如扫描线）从缺口262a和走线槽292中引出，从而便于显示区21中的走线与设置在弯折区22处的连接走线连接，同时也可以设置成一个缺口262a与一条走线对应，以防止多条走线之间发生短路。
在设置有多层所述阻挡块262的情况下，所有所述阻挡块262上的缺口262a在所述衬底基板23上的正投影可以重合、相交或相间隔。
如图7所示，在另一实施方式中，所述阻挡块262包括多条沿第一方向相间隔排布的阻挡条262b，相邻所述阻挡条262b之间设置有间隙。
在设置有多层所述阻挡块262的情况下，所有所述阻挡块262上的间隙在所述衬底基板23上的正投影可以重合、相交或相间隔。
如图8所示，在所述阻挡部26包括两层或三层所述阻挡块262的情况下，所述阻挡部26包括第一阻挡块以及第二阻挡块，所述第一阻挡块与所述有源层272、所述第一栅极274以及所述第二栅极276中的一者同层设置，所述第二阻挡块与所述有源层272、所述第一栅极274以及所述第二栅极276中的另一者同层设置。
其中，所述第一阻挡块262包括多条沿第一方向相间隔排布的第一阻挡条263a，相邻所述第一阻挡条263a之间设置有第一间隙263b；所述第二阻挡块262包括多条沿第一方向相间隔排布的第二阻挡条264a，相邻所述第二阻挡条264a之间设置有第二间隙264b；所述第一阻挡条263a在所述衬底基板23上的正投影覆盖所述第二间隙264b在所述衬底基板23上的正投影，所述第二阻挡条264a在所述衬底基板23上的正投影覆盖所述第一间隙263b在所述衬底基板23上的正投影，从而可以在不同膜层上形成多个相间隔的走线槽292，便于将显示区21中的走线引出，同时可以避免大量蚀刻液在第一膜层组24的同一部位进行蚀刻导致衬底基板23被蚀刻液损坏。
参见图9至图13所示，图9至图13为阻挡部26包括单层的阻挡块262时一实施方式中阵列基板20的制备流程示意图。
如图9所示，以所述阻挡块262与所述有源层272同层设置为例。在所述衬底基板23上使用无机材料依次层叠形成保护层28和缓冲层271；在缓冲层271上使用非晶硅材料形成整面覆盖的非晶层；对非晶硅层进行激光处理以形成多晶硅层；对所述非晶硅层进行图案化，以形成相间隔的有源层272和阻挡块262；形成覆盖所述有源层272、所述阻挡块262以及所述缓冲层271的第一栅极绝缘层273。
如图10所示，在第一栅极绝缘层273上形成第一金属层，并对第一金属层进行图案化，以形成第一栅极274后，对第一栅极274进行离子注入掺杂工艺；形成覆盖所述第一栅极274以及所述第一栅极绝缘层273的第二栅极绝缘层275；在所述第二栅极绝缘层275上形成第二金属层，并对第二金属层进行图案化，以形成第二栅极276；形成覆盖所述第二栅极276以及所述第二栅极绝缘层275的层间介质层277。
如图11所示，在所述层间介质层277上使用蚀刻液蚀刻出贯穿有源层272且延伸至所述缓冲层271的过孔291，同时在所述层间介质层277上蚀刻出位于弯折区22且贯穿缓冲层271的第一沟槽241以及贯穿第一栅极绝缘层273、第二栅极绝缘层275和层间介质层277的第二沟槽251，所述过孔291与所述第一沟槽241以及第二沟槽251通过同一道蚀刻工艺形成。
如图12所示，在所述层间介质层277上形成第三金属层，并对第三金属层进行图案化，以形成填充所述过孔291的源漏极278。
需要说明的是，对第三金属层进行图案化以形成源漏极278时，可以同时形成位于第一沟槽241中的转接端子293，可以利用转接端子293连接驱动芯片与显示区21中的走线，从而便于驱动芯片与显示区21中的走线的连接。
如图13所示，在所述层间介质层277上形成覆盖所述源漏极278并填充所述第一沟槽241和所述第二沟槽251的平坦层279。
需要说明的是，所述阻挡块262与所述第一栅极274同层设置时，对第一金属层进行图案化以形成第一栅极274时即可同时形成所述阻挡块262；所述阻挡块262与所述第二栅极276同层设置时，对第二金属层进行图案化以形成第二栅极276时即可同时形成所述阻挡块262。
参见图14图17所示，图14至图17为阻挡部26包括双层的阻挡块262时一实施方式中阵列基板20的制备流程示意图。
如图14所示，以一层所述阻挡块262与所述有源层272同层设置，且另一层所述阻挡块262与所述第一栅极274同层设置为例。在所述衬底基板23上使用无机材料依次层叠形成保护层28和缓冲层271后；在缓冲层271上使用非晶硅材料形成整面覆盖的非晶层；对非晶硅层进行激光处理以形成多晶硅层；对所述非晶硅层进行图案化，以形成相间隔的有源层272和第一层所述阻挡块262；形成覆盖所述有源层272、所述阻挡块262以及所述缓冲层271的第一栅极绝缘层273。
如图15所示，在第一栅极绝缘层273上形成第一金属层，并对第一金属层进行图案化，以形成第一栅极274和与所述第一栅极274相间隔的第二层所述阻挡块262，对第一栅极274进行离子注入掺杂工艺；形成覆盖所述第一栅极274以及所述第一栅极绝缘层273的第二栅极绝缘层275；在所述第二栅极绝缘层275上形成第二金属层，并对第二金属层进行图案化，以形成第二栅极276；形成覆盖所述第二栅极276以及所述第二栅极绝缘层275的层间介质层277。
如图16所示，在所述层间介质层277上使用蚀刻液蚀刻出贯穿有源层272且延伸至所述缓冲层271的过孔291，同时在所述层间介质层277上蚀刻出位于弯折区22且贯穿缓冲层271的第一沟槽241，以及，贯穿第一栅极绝缘层273、第二栅极绝缘层275和层间介质层277的第二沟槽251，所述过孔291与所述第一沟槽241以及第二沟槽251通过同一道蚀刻工艺形成。
如图17所示，在所述层间介质层277上形成第三金属层，并对第三金属层进行图案化，以形成填充所述过孔291的源漏极278；在所述层间介质层277上形成覆盖所述源漏极278并填充所述第一沟槽241和所述第二沟槽251的平坦层279。
基于上述阵列基板20，本申请还提供一种OLED显示面板，如图18所示，所述OLED显示面板包括如上述任一实施方式中所述的阵列基板20。
具体的，所述OLED显示面板还包括设置于所述阵列基板20上的阳极金属层30以及像素定义层40、设置于所述阳极金属层30上的发光材料层50、设置于所述像素定义层40上的支撑柱60、设置于所述像素定义层40、所述支撑柱60以及所述发光材料层50上的阴极层70。
其中，所述阳极金属层30以及所述像素定义层40设置于所述阵列基板20的平坦层279上。
本申请的有益效果为：利用设置于第一膜层组24上的阻挡部26，在阵列基板20的制备过程中，在第二膜层组25的预设位置处蚀刻形成第二沟槽251后，可以利用阻挡部26充当掩模板对第一膜层组24进行蚀刻，同时由于阻挡部26的阻挡作用，蚀刻液只能通过阻挡部26上的蚀刻开口261流入到第一膜层组24上，从而可以在第一膜层组24上蚀刻形成预设形状的第一沟槽241，第一沟槽241、第二沟槽251以及连接源漏极278和有源层272的过孔291可以在一道蚀刻工序中形成，从而在保证阵列基板20的阵列性能未降低的前提下，减少光罩数量和光照制程，缩短整体的工艺流程，降低成本。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板具有显示区和位于所述显示区的侧部的弯折区，所述阵列基板包括：
    衬底基板；
    设置于所述衬底基板上的第一膜层组；
    设置于所述第一膜层组远离所述衬底基板的一侧的第二膜层组；
    其中，所述弯折区处设置有贯穿所述第一膜层组的第一沟槽以及贯穿所述第二膜层组的第二沟槽；所述第一膜层组靠近所述第二膜层组的一侧上设置有阻挡部，所述阻挡部上设置有与所述第一沟槽对应的蚀刻开口，所述蚀刻开口贯穿所述阻挡部，所述蚀刻开口的底端与所述第一沟槽的顶端连接；所述第二沟槽的底端延伸至所述阻挡部的顶面，所述第二沟槽在所述衬底基板上的正投影覆盖所述蚀刻开口在所述衬底基板上的正投影。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括：
    设置于所述衬底基板上的缓冲层；
    设置于所述缓冲层上的有源层；
    覆盖所述有源层的第一栅极绝缘层；
    设置于所述第一栅极绝缘层上的第一栅极；
    覆盖所述第一栅极的第二栅极绝缘层；
    设置于所述第二栅极绝缘层上的第二栅极；
    覆盖所述第二栅极的层间介质层；
    设置于所述层间介质层上的源漏极；
    覆盖所述源漏极的平坦层；
    其中，所述第一膜层组包括所述缓冲层。
  3. 根据权利要求2所述的阵列基板，其中，所述阻挡部包括与所述有源层、所述第一栅极以及所述第二栅极中的至少一者同层设置的阻挡块，所述蚀刻开口贯穿所有阻挡块；所述阻挡块沿第一方向延伸，所述第一方向与所述第一沟槽的长度方向平行。
  4. 根据权利要求3所述的阵列基板，其中，所述阻挡块与所述有源层同层设置时，与所述有源层同层设置的阻挡块与所述有源层通过同一道工艺形成；所述阻挡块与所述第一栅极同层设置时，与所述第一栅极同层设置的阻挡块与所述第一栅极通过同一道工艺形成；所述阻挡块与所述第二栅极同层设置时，与所述第二栅极同层设置的阻挡块与所述第二栅极通过同一道工艺形成。
  5. 根据权利要求3所述的阵列基板，其中，所述阻挡块上远离所述蚀刻开口的一端设置有多条沿第二方向延伸的缺口，多条所述缺口沿第一方向相间隔排布。
  6. 根据权利要求3所述的阵列基板，其中，所述阻挡块包括多条沿第一方向相间隔排布的阻挡条。
  7. 根据权利要求3所述的阵列基板，其中，所述阻挡部包括第一阻挡块以及第二阻挡块，所述第一阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的一者同层设置，所述第二阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的另一者同层设置；
    其中，所述第一阻挡块包括多条沿第一方向相间隔排布的第一阻挡条，相邻所述第一阻挡条之间设置有第一间隙；所述第二阻挡块包括多条沿第一方向相间隔排布的第二阻挡条，相邻所述第二阻挡条之间设置有第二间隙；所述第一阻挡条在所述衬底基板上的正投影覆盖所述第二间隙在所述衬底基板上的正投影，所述第二阻挡条在所述衬底基板上的正投影覆盖所述第一间隙在所述衬底基板上的正投影。
  8. 根据权利要求1所述的阵列基板，其中，所述第一沟槽与所述第二沟槽通过同一道工艺形成。
  9. 根据权利要求2所述的阵列基板，其中，所述层间介质上设置有贯穿所述层间介质层且延伸至所述有源层的过孔，所述源漏极填充所述过孔且与所述有源层电连接，所述过孔与所述第一沟槽和所述第二沟槽通过同一道工艺形成。
  10. 一种OLED显示面板，其中，所述OLED显示面板包括阵列基板，所述阵列基板具有显示区和位于所述显示区的侧部的弯折区，所述阵列基板包括：
    衬底基板；
    设置于所述衬底基板上的第一膜层组；
    设置于所述第一膜层组远离所述衬底基板的一侧的第二膜层组；
    其中，所述弯折区处设置有贯穿所述第一膜层组的第一沟槽以及贯穿所述第二膜层组的第二沟槽；所述第一膜层组靠近所述第二膜层组的一侧上设置有阻挡部，所述阻挡部上设置有与所述第一沟槽对应的蚀刻开口，所述蚀刻开口贯穿所述阻挡部，所述蚀刻开口的底端与所述第一沟槽的顶端连接；所述第二沟槽的底端延伸至所述阻挡部的顶面，所述第二沟槽在所述衬底基板上的正投影覆盖所述蚀刻开口在所述衬底基板上的正投影；
    所述OLED显示面板还包括：
    设置于所述阵列基板上的阳极金属层以及像素定义层；
    设置于所述阳极金属层上的发光材料层；
    设置于所述像素定义层上的支撑柱；
    设置于所述像素定义层、所述支撑柱以及所述发光材料层上的阴极层。
  11. 根据权利要求10所述的OLED显示面板，其中，所述阵列基板包括：
    设置于所述衬底基板上的缓冲层；
    设置于所述缓冲层上的有源层；
    覆盖所述有源层的第一栅极绝缘层；
    设置于所述第一栅极绝缘层上的第一栅极；
    覆盖所述第一栅极的第二栅极绝缘层；
    设置于所述第二栅极绝缘层上的第二栅极；
    覆盖所述第二栅极的层间介质层；
    设置于所述层间介质层上的源漏极；
    覆盖所述源漏极的平坦层；
    其中，所述第一膜层组包括所述缓冲层。
  12. 根据权利要求11所述的OLED显示面板，其中，所述阻挡部包括与所述有源层、所述第一栅极以及所述第二栅极中的至少一者同层设置的阻挡块，所述蚀刻开口贯穿所有阻挡块；所述阻挡块沿第一方向延伸，所述第一方向与所述第一沟槽的长度方向平行。
  13. 根据权利要求12所述的OLED显示面板，其中，所述阻挡块与所述有源层同层设置时，与所述有源层同层设置的阻挡块与所述有源层通过同一道工艺形成；所述阻挡块与所述第一栅极同层设置时，与所述第一栅极同层设置的阻挡块与所述第一栅极通过同一道工艺形成；所述阻挡块与所述第二栅极同层设置时，与所述第二栅极同层设置的阻挡块与所述第二栅极通过同一道工艺形成。
  14. 根据权利要求12所述的OLED显示面板，其中，所述阻挡块上远离所述蚀刻开口的一端设置有多条沿第二方向延伸的缺口，多条所述缺口沿第一方向相间隔排布。
  15. 根据权利要求12所述的OLED显示面板，其中，所述阻挡块包括多条沿第一方向相间隔排布的阻挡条。
  16. 根据权利要求12所述的OLED显示面板，其中，所述阻挡部包括第一阻挡块以及第二阻挡块，所述第一阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的一者同层设置，所述第二阻挡块与所述有源层、所述第一栅极以及所述第二栅极中的另一者同层设置；
    其中，所述第一阻挡块包括多条沿第一方向相间隔排布的第一阻挡条，相邻所述第一阻挡条之间设置有第一间隙；所述第二阻挡块包括多条沿第一方向相间隔排布的第二阻挡条，相邻所述第二阻挡条之间设置有第二间隙；所述第一阻挡条在所述衬底基板上的正投影覆盖所述第二间隙在所述衬底基板上的正投影，所述第二阻挡条在所述衬底基板上的正投影覆盖所述第一间隙在所述衬底基板上的正投影。
  17. 根据权利要求10所述的OLED显示面板，其中，所述第一沟槽与所述第二沟槽通过同一道工艺形成。
  18. 根据权利要求11所述的OLED显示面板，其中，所述层间介质上设置有贯穿所述层间介质层且延伸至所述有源层的过孔，所述源漏极填充所述过孔且与所述有源层电连接，所述过孔与所述第一沟槽和所述第二沟槽通过同一道工艺形成。
  19. 根据权利要求10所述的OLED显示面板，其中，所述第一沟槽沿其长度方向延伸以贯穿所述第一膜层组的前后两侧，所述第二沟槽沿其长度方向延伸以贯穿所述第二膜层组的前后两侧。
  20. 根据权利要求10所述的OLED显示面板，其中，所述第一沟槽与所述第二沟槽连通，所述第二沟槽在所述衬底基板上的正投影覆盖所述第一沟槽在所述衬底基板上的正投影。
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