WO2019100874A1 - 显示基板及其制造方法以及对应显示面板及其封装方法 - Google Patents

显示基板及其制造方法以及对应显示面板及其封装方法 Download PDF

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Publication number
WO2019100874A1
WO2019100874A1 PCT/CN2018/110760 CN2018110760W WO2019100874A1 WO 2019100874 A1 WO2019100874 A1 WO 2019100874A1 CN 2018110760 W CN2018110760 W CN 2018110760W WO 2019100874 A1 WO2019100874 A1 WO 2019100874A1
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Prior art keywords
display
groove
package
wires
display substrate
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PCT/CN2018/110760
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English (en)
French (fr)
Inventor
刘亮亮
康峰
白妮妮
刘祺
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/346,355 priority Critical patent/US11075258B2/en
Publication of WO2019100874A1 publication Critical patent/WO2019100874A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display substrate and a method of fabricating the same, and a corresponding display panel and a method of packaging the same.
  • OLED display devices have been widely used due to their self-illumination, low driving voltage and fast response. Since the organic light-emitting materials used in OLED display devices are very sensitive to water and oxygen, packaging is critical for OLED display devices.
  • a laser sintered glass powder package also known as a Frit package.
  • Frit package a laser sintered glass powder package
  • a high-temperature sintering of the encapsulant between the display substrate and the display cover plate is required by using a laser to achieve a seal between the display substrate and the display cover plate, thereby ensuring the organic light-emitting material in the display substrate. It can work in an anhydrous, anaerobic environment.
  • the metal wires on the display substrate may be caused to be melted.
  • the soldered metal wire may cause a short circuit after contact with an adjacent metal wire, thereby causing display failure.
  • a display substrate includes a base substrate including a display region and a package region surrounding the display region, and an insulating layer and a plurality of wires disposed on the base substrate.
  • the insulating layer includes at least one groove in the package area.
  • At least one of the plurality of wires includes a first portion located in the display area and a second portion located in a corresponding groove in the package area. There is only one second portion in each groove.
  • each of the plurality of wires includes a first portion located in the display region and a corresponding groove located in the package region The second part.
  • the width of each groove increases as the line width of the second portion of the corresponding wire increases, and between the adjacent two grooves
  • the pitch increases as the spacing between the second portions of the corresponding two wires increases, wherein the width direction of each of the grooves is parallel to the line width direction of the second portion of the corresponding wire.
  • adjacent two grooves are spaced apart by the insulating block.
  • each of the grooves includes a bottom wall adjacent to the substrate substrate and two portions that intersect the bottom wall and are not in contact with the second portion of the corresponding wire Side walls.
  • the bottom wall of each of the grooves is formed by a portion of the substrate that is close to the surface of the groove or an insulating material.
  • the depth of each of the grooves is greater than the thickness of the second portion of the corresponding wire, wherein the depth direction of the groove and the second of the corresponding wire The thickness direction of the portion is perpendicular to the extended surface of the base substrate.
  • a width of each of the grooves is greater than a line width of a second portion of the corresponding wire, wherein a width direction of the groove is parallel to a corresponding wire.
  • the line width direction of the second part is not limited to a specific implementation manner.
  • each of the grooves includes two side walls that are not in contact with the second portion of the corresponding wire, wherein each of the side walls and the corresponding wire The second portions are spaced apart at a pitch greater than or equal to 1 micrometer in the width direction of the grooves.
  • each of the insulating blocks has a width greater than or equal to 3 micrometers, wherein a width direction of the insulating block is parallel to a width direction of the recess.
  • At least each of the second portions of the wires includes a plurality of conductive layers stacked in a stack, wherein the adjacent two conductive layers are made of different conductive materials. production.
  • a method of manufacturing a display substrate includes the steps of: providing a base substrate including a display region and a package region surrounding the display region; and forming an insulating layer and a plurality of wires on the base substrate.
  • the insulating layer is formed to include at least one groove in the package region; at least one of the plurality of wires is formed to include a first portion located in the display region and located in the package One of the regions corresponds to a second portion within the recess; and only one of the second portions is formed within each recess.
  • each of the plurality of wires is formed to include a first portion located in the display region and located in the package One of the regions corresponds to the second portion of the groove.
  • the insulating layer includes an interlayer insulating layer.
  • the method further includes the steps of: forming an active layer on a side of the interlayer insulating layer close to the substrate substrate and in a display region of the base substrate; using a contact hole a mask forming a contact via on a portion of the interlayer insulating layer located in a display region of the base substrate; and continuing to form a source/drain electrode on the base substrate on which the interlayer insulating layer is formed.
  • a packaging method for a display panel includes the steps of: providing a display substrate according to any of the preceding embodiments; providing a package cover having a package area corresponding to a package area of the display substrate; Forming an encapsulant in a package region of the board; aligning the display substrate on the package cover with two package areas aligned; and illuminating the encapsulant with a laser to complete the package.
  • a display panel is also provided.
  • the display panel includes: a package cover; and the display substrate according to any of the preceding embodiments, wherein the display substrate is sealed with the package cover by an encapsulant.
  • FIG. 1 is a schematic view showing a short circuit occurring between adjacent wires in a display substrate according to the related art
  • FIG. 2 is a cross-sectional view of a display substrate in accordance with an embodiment of the present disclosure
  • FIG. 3 is a top plan view of a display substrate in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of a display substrate in accordance with another embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view of a display substrate in accordance with still another embodiment of the present disclosure.
  • FIG. 6 is a flow chart of a method of manufacturing a display substrate in accordance with one embodiment of the present disclosure
  • FIG. 7 is a schematic view of an insulating layer formed on a base substrate in accordance with an embodiment of the present disclosure
  • FIG. 8 is a schematic view of a groove formed on an insulating layer, in accordance with an embodiment of the present disclosure.
  • FIG. 9 is a schematic view of a wire formed on a base substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of a display panel according to an embodiment of the present disclosure.
  • the display area of the display substrate may include a plurality of arrayed pixel units, wherein each of the pixel units may further include a driving transistor and an OLED device.
  • a plurality of wires may be disposed on the display substrate, wherein an input end of each wire may be connected to a driving chip located outside the display substrate, and an output end of each wire is in a corresponding pixel unit.
  • a drive transistor is coupled for providing a drive signal to the drive transistor. Since each of the wires needs to be connected to a driving chip other than the display substrate, a part of each of the wires will be located in the package area of the display substrate.
  • the sintering temperature can be 600 degrees Celsius (° C.) or even higher during the packaging of the display substrate using the Frit packaging method.
  • the wires in the display substrate are mainly made of aluminum (the melting point of aluminum is 660 ° C). Therefore, during the Frit packaging process, the wires in the display substrate may be blown and short-circuited with adjacent wires. Such a short between the wires may cause display defects, poor display panel vertical lines (also known as XLine), or display panel horizontal lines (also known as Y Line).
  • the wire a1 is adjacent to the wire a2.
  • the wire a1 is melted, the melted liquid flows to the adjacent wire a2, causing the wires a1 and a2 to be short-circuited and causing display failure.
  • the display substrate may include a base substrate 01, and an insulating layer 02 and a plurality of wires 03 disposed on the base substrate 01.
  • FIG. 3 is a plan view of a display substrate according to an embodiment of the present disclosure, and FIG. 2 is a cross-sectional view along the AA direction of FIG.
  • the base substrate 01 may include a display region S2 at the center and a package region S1 surrounding the display region S2.
  • the insulating layer 02 on the base substrate 01 may include at least one groove 021 located in the package region S1 of the base substrate 01, for example, five shown as an example in FIG. a groove.
  • each of the grooves 021 is in one-to-one correspondence with one of the plurality of wires 03. As shown in FIG.
  • each of the wires 03 may include a first portion 0301 located in the display area S2 and a second portion 0302 located in the package area. Further optionally, each of the wires 03 may further include a third portion 0303 located outside the entire base substrate 01. For each of the wires 03 in FIG. 3, the second portion 0302 located in the package region S1 may be disposed in a corresponding one of the grooves 021. In such a case, the adjacent wires 03 can be isolated by the recess 021.
  • wire 03 includes the second portion 0302 disposed in the corresponding groove 021, this It is not intended to limit any of the disclosure. In fact, in the embodiment of the present disclosure, there may be other wires 03, which may have a second portion 0302 located in the package region S1, but such a second portion 0302 is not necessarily disposed in the corresponding groove 021. .
  • each of the wires 03 is located outside the base substrate 01 is shown as an example in FIG. 3, this does not represent any limitation to the present disclosure, in fact, according to In other alternative embodiments, one or more of the wires 03 may also not include such a third portion 0303.
  • the wire 03 is electrically connected to the external unit by means of its end face at the edge of the base substrate 01. In this regard, those skilled in the art should readily appreciate it.
  • the package area S1 may refer to the following area: in the process of packaging the display substrate and the package cover by the encapsulant, the area on the display substrate that is in contact with the encapsulant is An orthographic projection on the base substrate.
  • the package region S1 may be a back-shaped region located around the periphery of the substrate.
  • the plurality of wires 03 may be wires for providing driving signals for the driving transistors on the substrate, and the input terminals of each of the wires may be connected to a driving chip located outside the substrate.
  • each of the wires may be any one of a gate line, a data line, a common electrode line, and a power signal line.
  • each of the grooves may have a one-to-one correspondence with a wire having a higher risk of a blown short circuit among the plurality of wires, and the wire having a higher risk of the blown short circuit may include a second wire disposed in a corresponding groove. section.
  • a display substrate in an embodiment of the present disclosure, is provided.
  • the insulating layer in the display substrate includes at least one recess in the package area.
  • at least one of the wires in the display substrate includes a second portion within a corresponding recess in the package region.
  • adjacent wires can be separated by grooves. In such a case, even if a certain wire located in the groove is melted due to high temperature during the packaging process, it will not be short-circuited with other adjacent wires. Thereby, the probability of occurrence of display failure is effectively reduced.
  • each of the grooves 021 of the insulating layer 02 in the package area S1 uniquely corresponds to the second part of one of the plurality of wires 03, that is, the groove 021 and The wires 03 (and their second portions) correspond one-to-one.
  • each of the wires 03 comprises a second portion in a corresponding groove in the package area. That is to say, among the plurality of wires that need to pass through the package region to be connected to the external chip in the display substrate, each of the wires may include a second portion disposed in the corresponding one of the grooves, thereby effectively reducing the wires The risk of a short circuit.
  • the width w1 of each groove may be positively correlated with the line width w2 of the second portion of the corresponding wire. That is, for any two grooves, if the line width of the second portion of the wire disposed in the first groove is greater than the line width of the second portion of the wire disposed in the second groove, then The width of the first groove may be greater than the width of the second groove.
  • the spacing w3 between any two adjacent grooves can be positively correlated with the spacing w4 between the second portions of the corresponding two wires. That is, if the spacing between adjacent two wires (specifically, the second portion thereof) is smaller, the spacing between the two grooves corresponding to the two wires is smaller. In contrast, if the spacing between adjacent two wires (specifically, the second portion thereof) is larger, the spacing between the two grooves corresponding to the two wires is larger. This means that the higher the density of the wires in the display substrate, the smaller the spacing between adjacent grooves.
  • the width direction of each groove may be parallel to the line width direction of the wire (eg, the second portion thereof), and the spacing between the two grooves may be Refers to the thickness of the insulating material between the two grooves, wherein the thickness direction is parallel to the line width direction of the wire (eg, the second portion thereof).
  • the insulating layer 02 further includes a plurality of spaced insulating blocks 022 located in the package region of the base substrate 01.
  • each of the grooves 021 may include two side walls that are not in contact with the second portion of the wire (for example, the left and right side walls in the drawing). Referring to FIG. 4, the two side walls may be respectively formed by the side walls of the corresponding two insulating blocks 022.
  • each of the grooves 021 may further include a bottom wall, wherein the bottom wall may be constituted by a portion of the upper surface of the base substrate 01. This means that each of the grooves 021 can penetrate the entire thickness of the insulating layer 02, and the second portion of each of the wires 03 can be formed on the upper surface of the base substrate 01 directly in the package region.
  • each of the grooves 021 may not penetrate through the entire thickness of the insulating layer 02. That is, the bottom wall of each of the grooves 021 is not the upper surface portion of the base substrate 01, but is instead formed of an insulating material.
  • the insulating material may be the same material used to form the insulating layer 02.
  • a second portion of each of the wires 03 located in the package region may be disposed in the corresponding groove 021 and formed on a side of the insulating material away from the substrate 101.
  • each of the insulating blocks 022 near the display region S2 can be connected to a portion of the insulating layer located in the display region S2. That is, each of the grooves 021 in the insulating layer may include three sequentially connected side walls, and one side of the side wall (ie, one side of the opening, for example, the upper side in FIG. 3) may be provided for The wire is connected to an external chip. As shown in FIG. 4, among the three side walls, the oppositely disposed side walls a and side walls b are not in contact with the wires (particularly, the second portion thereof).
  • the side wall a and the side wall b may be respectively formed by side walls of two adjacent insulating blocks 022.
  • the side wall c for connecting the side wall a and the side wall b may be constituted by a portion of the insulating layer located in the display region S2.
  • the side wall c is in contact with the wire (in particular, its second portion) and the wire can extend from the display area into the groove 021 across the side wall c.
  • the depth h1 of each of the grooves 021 may be greater than the thickness h2 of the corresponding wire 03 (particularly, the second portion thereof).
  • the depth direction of the groove 021 and the thickness direction of the wire 03 may be perpendicular to the extended surface of the base substrate 01.
  • the depth direction of the groove may be the X direction shown in FIG.
  • the width w1 of each of the grooves 021 may be greater than the line width w2 of the second portion 0302 of the corresponding wire 03.
  • the width direction Y of the groove may be parallel to the line width direction of the wire (particularly, the second portion thereof).
  • each of the grooves 021 may include two side walls (eg, side wall a and side wall b) that are not in contact with the second portion 0302 of the wire 03, and are not in line with the wire 03.
  • a spacing d1 in the width direction Y which may be greater than or equal to 1 micrometer ( ⁇ m). That is, there may be a certain gap between the second portion of each of the wires and the sidewall of the groove. The gap can be used to store the liquid produced after the wire is melted, thereby preventing the liquid from overflowing from the groove and flowing into the adjacent groove.
  • the spacing d1 between the side wall and the second portion of the wire may be positively correlated with the line width of the second portion of the wire. That is to say, the wider the line width of the second portion of the wire, the larger the pitch d1 can be. In this way, it is ensured that the gap between the second portion of the wire and the side wall can effectively store the liquid generated after the wire is melted to avoid liquid overflow.
  • the width w3 of each of the insulating blocks 022 may be greater than or equal to 3 microns.
  • the width direction Y of the insulating block 022 may be parallel to the width direction of the groove 021, or may be parallel to the width direction of the second portion 0302 of the wire 03.
  • the second portion 0302 of each of the wires 03 may include a plurality of conductive layers stacked in a stack. Specifically, among the plurality of conductive layers, the adjacent two conductive layers may be made of different conductive materials.
  • the second portion 0302 of each of the wires 03 may include three conductive layers 031, 032, and 033 stacked in layers, wherein the conductive layer 031 and the conductive layer 033 may be made of titanium metal It is made, and the conductive layer 032 can be made of metal aluminum.
  • the conductive layer 033 may have a thickness of 300 angstroms.
  • the thickness of the conductive layer 032 can be And the thickness of the conductive layer 031 can be
  • the total thickness h2 of the second portion 0302 of each of the wires 03 can be Correspondingly, the depth h1 of each groove 021 can be greater than
  • embodiments of the present disclosure provide a display substrate.
  • the insulating layer includes at least one recess in the package area
  • the at least one lead includes a second portion located in a corresponding recess in the package area.
  • FIG. 6 is a flow chart of a method of manufacturing a display substrate in accordance with an embodiment of the present disclosure. This method can be used to manufacture the display substrate provided in the above embodiments. Referring to Figure 6, the method can include the following steps.
  • Step 101 Providing a substrate.
  • the base substrate includes a display area and a package area surrounding the display area.
  • Step 102 forming an insulating layer and a plurality of wires on the base substrate.
  • the insulating layer is formed to include at least one groove in the package region; at least one of the plurality of wires is formed to include a first portion located in the display region and located in the package a second portion of the region corresponding to the groove; and forming only one of the second portions in each groove
  • the insulating layer may be an inter-layer dielectric (ILD).
  • ILD inter-layer dielectric
  • the active layer 04, the gate insulating layer 05, and the gate electrode 06 have been formed in the display region S2 of the base substrate 01.
  • the interlayer insulating layer 02 may be overlaid on the surface of the base substrate 01, that is, over the package region S1 and the display region S2.
  • a film of an insulating material may be first formed, and then a portion of the insulating film located in a package region of the substrate substrate is patterned to form the at least one groove.
  • the number of grooves to be formed may be determined based on the number of wires having a lower melting point and a higher risk of a blown short circuit among the plurality of wires. Further, the formation position of each groove may be determined based on the specific position of the second portion of each of the wires having a lower melting point in the package region.
  • a plurality of grooves corresponding to the plurality of wires may be formed in a portion of the insulating material film located in the package region. That is, the number of the grooves may be determined according to the number of wires in the display substrate that need to pass through the package region to be connected to the external chip. In addition, the formation position of each groove can also be determined according to the specific position of the second portion of each wire in the package area.
  • a conductive film layer may be deposited on the substrate substrate on which the insulating layer (including the recess in the package region) is formed, and the conductive film layer is patterned to form a plurality of wires.
  • the conductive film layer is patterned to form a plurality of wires.
  • at least one of the wires may include a second portion disposed in a corresponding groove.
  • such at least one wire may be a wire having a lower melting point and a higher risk of a blown short circuit among the plurality of wires.
  • embodiments of the present disclosure provide a method of manufacturing a display substrate.
  • the insulating layer is made to include at least one groove in the package area, and the at least one wire includes a second portion located in a corresponding groove in the package area.
  • adjacent wires particularly, the second portion thereof
  • adjacent wires can be isolated by the grooves.
  • a certain wire located in the groove particularly, the second portion thereof
  • it will not be short-circuited with other adjacent wires, thereby effectively reducing Shows the probability of a bad occurrence.
  • a plurality of grooves corresponding to the plurality of wires may be formed in a portion of the insulating material film located in the package region.
  • each of the plurality of wires formed includes a second portion within a corresponding recess in the package area.
  • the insulating layer 02 may be selected as an interlayer insulating layer.
  • the above manufacturing method may further include the step of forming a contact via on the portion of the interlayer insulating layer located in the display region of the base substrate using the contact hole mask.
  • the contact via 023 may penetrate the interlayer insulating layer 02 and the gate insulating layer 05 for connecting the active layer 04 and the source and drain electrodes in the driving transistor.
  • the contact via 023 when the contact via 023 is formed on the portion where the interlayer insulating layer 02 is located in the display region S2 by using the contact hole mask, it may be synchronously located at the interlayer insulating layer 02.
  • At least one groove 021 is formed on a portion in the package region S1 (only one groove is shown in FIG. 8). Further, in conjunction with Figure 3, it can be seen that each of the grooves can include three side walls.
  • two oppositely disposed side walls a and side walls b located in the package area S1 may be constituted by side walls of two adjacent insulating blocks, and located on the side in the display area S2
  • the wall c may be constituted by a portion of the insulating layer located in the display region S2.
  • the bottom wall of the recess 021 may be a surface portion of the base substrate 01.
  • the manufacturing method for the display substrate may further include the step of continuing to form the source/drain electrodes and the plurality of wires on the substrate substrate on which the insulating layer is formed.
  • a conductive film layer may be formed on the base substrate 01 on which the interlayer insulating layer 02 is formed, and then the conductive film layer is patterned by using a mask to obtain a source/drain electrode and Multiple wires. A second portion of the plurality of wires located in the package area may be formed in the corresponding groove.
  • FIG. 9 is a cross-sectional view along the BB direction in FIG. 3, according to an embodiment of the present disclosure.
  • the source-drain electrode 06 located in the display region S2 may be connected to the active layer 05 through the contact via 023, and the wire 03 may be connected to the source-drain electrode 06.
  • a second portion of the wire 03 located in the package region S1 is formed in the groove 021. It can also be seen from Figure 9 that the wire 03 can extend from the display area S2 into the groove 021 across the side wall c.
  • the conductive film layer formed in the above process may include a plurality of conductive layers.
  • adjacent two conductive layers may be made of different conductive materials.
  • the conductive film layer may include three conductive layers stacked in a stack, wherein the three conductive layers may be sequentially made of titanium metal, aluminum metal, and titanium metal.
  • the width of each groove is required to be larger than the line width of the second portion of the corresponding wire, and it is also required that the depth of each groove is greater than the second of the corresponding wire. Part of the thickness to ensure that the groove can effectively isolate adjacent wires.
  • the patterning process applied in the above manufacturing method may specifically include steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • the type of the insulating layer may be different depending on the structure of the driving transistor formed in the display substrate.
  • the insulating layer may also be a gate insulating layer or the like for isolating the gate electrode and the active layer, and the embodiment of the present disclosure does not limit this.
  • the execution order of the steps of the manufacturing method for displaying the substrate may be appropriately adjusted.
  • the steps can also be increased or decreased according to the situation.
  • one step can be performed before, after, or at the same time.
  • a wire may be formed first, and then a groove may be formed.
  • embodiments of the present disclosure provide a method of manufacturing a display substrate.
  • the insulating layer can include at least one recess in the package area, and the at least one wire includes a second portion in a corresponding recess in the package area.
  • adjacent wires can be isolated by grooves. In such a case, even if a certain wire located in the groove (particularly, the second portion thereof) is melted at a high temperature during the packaging process, it does not short-circuit with other adjacent wires, thereby effectively Reduce the probability of poor display.
  • a packaging method for a display panel is also provided.
  • the packaging method can include the following steps.
  • Step S1 provides a display substrate.
  • the display substrate may be selected as the display substrate described in any of the above embodiments.
  • Step S2 providing a package cover.
  • the package cover has a package area corresponding to a package area of the display substrate.
  • Step S3 forming an encapsulant in a package area of the package cover.
  • the encapsulant can be a glass glue.
  • the package area of the package cover is orthographically projected on the base substrate of the display substrate, and coincides with the package area of the base substrate.
  • Step S4 aligning the display substrate on the package cover with the two package areas aligned.
  • a side of the display substrate on which the film layer is formed may be directed toward the package cover, and the display substrate is aligned on the package cover such that the film layer on the display substrate and the package The encapsulant on the cover is in contact.
  • Step S5 irradiating the encapsulant with a laser to complete the encapsulation.
  • the encapsulant may be irradiated with a laser such that the encapsulant is sintered at a high temperature to seal the display substrate and the display cover together.
  • the display panel formed by the display substrate and the display cover after sealing can be as shown in FIG.
  • Embodiments of the present disclosure also provide a display panel.
  • the display panel may include a package cover 100 and a display substrate 000.
  • the display substrate 000 may be the display substrate shown in any of FIGS. 2 to 5 and 9. Referring to FIG. 10, it can be seen that the display substrate 000 can be sealed with the package cover 100 by the encapsulant 200.
  • Embodiments of the present disclosure also provide a display device.
  • the display device may include a display panel as shown in FIG.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

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Abstract

本公开涉及显示技术领域，并且提供了显示基板及其制造方法、以及对应的显示面板及其封装方法。该显示基板包括：衬底基板，所述衬底基板包括显示区域和围绕所述显示区域的封装区域；以及设置在所述衬底基板上的绝缘层和多条导线。所述绝缘层包括位于所述封装区域中的至少一个凹槽。所述多条导线中的至少一个包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分。每一个凹槽内仅存在一个所述第二部分。

Description

显示基板及其制造方法以及对应显示面板及其封装方法
对相关申请的交叉引用
本申请要求2017年11月27日提交的中国专利申请号201711202350.6的优先权，该中国专利申请以其整体通过引用并入本文。
技术领域
本公开涉及显示技术领域，特别涉及显示基板及其制造方法、以及对应的显示面板及其封装方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置因其自发光、驱动电压低、响应快等特点而得到了广泛的应用。由于OLED显示装置中所采用的有机发光材料对于水和氧气非常敏感，因此封装对于OLED显示装置至关重要。
常用的封装过程一般采用激光烧结玻璃粉封装(也称为Frit封装)而完成。当采用Frit封装方法进行封装时，需要采用激光对显示基板与显示盖板之间的封装胶进行高温烧结，以实现显示基板与显示盖板之间的密封，从而保证显示基板中的有机发光材料能够在无水、无氧的环境中工作。
然而，在采用激光进行高温烧结的过程中，由于烧结温度较高，所以可能导致该显示基板上的金属导线被烧熔。被烧熔的金属导线在与相邻的金属导线接触之后会导致线路短路，从而引起显示不良。
发明内容
根据本公开的一方面，提供了一种显示基板。所述显示基板包括：衬底基板，所述衬底基板包括显示区域和围绕所述显示区域的封装区域；以及设置在所述衬底基板上的绝缘层和多条导线。所述绝缘层包括位于所述封装区域中的至少一个凹槽。所述多条导线中的至少一个包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分。每一个凹槽内仅存在一个所述第二部分。
根据具体实现方式，在由本公开的实施例提供的显示基板中，所述多条导线中的每一个都包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分。
根据具体实现方式，在由本公开的实施例提供的显示基板中，每一个凹槽的宽度随着对应导线的第二部分的线宽的增大而增大，并且相邻两个凹槽之间的间距随着对应两条导线的第二部分之间的间距的增大而增大，其中，每一个凹槽的宽度方向平行于对应导线的第二部分的线宽方向。
根据具体实现方式，在由本公开的实施例提供的显示基板中，相邻两个凹槽通过绝缘块间隔开。
根据具体实现方式，在由本公开的实施例提供的显示基板中，每一个凹槽包括靠近所述衬底基板的底壁以及与所述底壁相交并且不与对应导线的第二部分接触的两个侧壁。
根据具体实现方式，在由本公开的实施例提供的显示基板中，每一个凹槽的底壁由所述衬底基板靠近所述凹槽的表面的部分或者绝缘材料形成。
根据具体实现方式，在由本公开的实施例提供的显示基板中，每一个所述凹槽的深度大于对应导线的第二部分的厚度，其中，所述凹槽的深度方向和对应导线的第二部分的厚度方向均垂直于所述衬底基板的延伸面。
根据具体实现方式，在由本公开的实施例提供的显示基板中，每一个所述凹槽的宽度大于对应导线的第二部分的线宽，其中，所述凹槽的宽度方向平行于对应导线的第二部分的线宽方向。
根据具体实现方式，在由本公开的实施例提供的显示基板中，每一个所述凹槽包括不与对应导线的第二部分接触的两个侧壁，其中，每一个所述侧壁与对应导线的第二部分在所述凹槽的宽度方向上以大于或等于1微米的间距隔开。
根据具体实现方式，在由本公开的实施例提供的显示基板中，每一个所述绝缘块的宽度大于或等于3微米，其中，所述绝缘块的宽度方向平行于所述凹槽的宽度方向。
根据具体实现方式，在由本公开的实施例提供的显示基板中，至少每一条所述导线的第二部分包括层叠设置的多个导电层，其中，相 邻的两个导电层由不同的导电材料制成。
根据本公开的另一方面，还提供了一种用于显示基板的制造方法。所述制造方法包括以下步骤：提供衬底基板，所述衬底基板包括显示区域和围绕所述显示区域的封装区域；以及在衬底基板上形成绝缘层和多条导线。具体地，所述绝缘层被形成为包括位于所述封装区域中的至少一个凹槽；所述多条导线中的至少一个被形成为包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分；并且在每一个凹槽内仅形成一个所述第二部分。
根据具体实现方式，在由本公开的实施例提供的用于显示基板的制造方法中，所述多条导线中的每一个都被形成为包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分。
根据具体实现方式，在由本公开的实施例提供的用于显示基板的制造方法中，所述绝缘层包括层间绝缘层。在这样的情况下，所述方法还包括以下步骤：在所述层间绝缘层靠近所述衬底基板的一侧上并且在所述衬底基板的显示区域中形成有源层；采用接触孔掩膜板在所述层间绝缘层位于所述衬底基板的显示区域中的部分上形成接触过孔；以及在形成有所述层间绝缘层的衬底基板上继续形成源漏电极。
根据本公开的又一方面，还提供了一种用于显示面板的封装方法。所述封装方法包括以下步骤：提供根据前面任一个实施例所述的显示基板；提供封装盖板，所述封装盖板具有与所述显示基板的封装区域对应的封装区域；在所述封装盖板的封装区域中形成封装胶；在两个封装区域对齐的情况下将所述显示基板对准在所述封装盖板上；以及采用激光照射所述封装胶以完成封装。
根据本公开的再一方面，还提供了一种显示面板。所述显示面板包括：封装盖板；以及根据前面任一个实施例所述的显示基板，其中，所述显示基板通过封装胶与所述封装盖板密封在一起。
附图说明
为了更清楚地说明本公开的实施例中的技术方案，下面将对实施例的描述中需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例。对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下，还可以根据这些附图获得其它的实施例。
图1是根据相关技术的显示基板中的相邻导线之间发生短路的示意图；
图2是根据本公开的一个实施例的显示基板的剖视图；
图3是根据本公开的一个实施例的显示基板的俯视图；
图4是根据本公开的另一个实施例的显示基板的剖视图；
图5是根据本公开的又一个实施例的显示基板的剖视图；
图6是根据本公开的一个实施例的用于显示基板的制造方法的流程图；
图7是根据本公开的一个实施例的形成在衬底基板上的绝缘层的示意图；
图8是根据本公开的一个实施例的形成在绝缘层上的凹槽的示意图；
图9是根据本公开的一个实施例的形成在衬底基板上的导线的示意图；以及
图10是根据本公开的一个实施例的显示面板的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开的实施方式作进一步地详细描述。
在相关技术中，显示基板的显示区域可以包括多个阵列排布的像素单元，其中，每一个像素单元还可以包括一个驱动晶体管和一个OLED器件。此外，该显示基板上还可以设置有多条导线，其中，每一条导线的输入端可以与位于该显示基板之外的驱动芯片相连，并且每一条导线的输出端与一个对应的像素单元中的驱动晶体管相连，以用于为该驱动晶体管提供驱动信号。由于每一条导线需要与显示基板之外的驱动芯片相连，因此每一条导线的一部分将会位于显示基板的封装区域内。典型地，在采用Frit封装方法对显示基板进行封装的过程中，烧结温度可以达到600摄氏度(℃)或者甚至更高。而且，显示基板中的导线又主要由铝制成(铝的熔点为660℃)。因此，在Frit封装过程中，显示基板中的导线可能会被烧熔并且与相邻导线发生短 路。导线之间的这种短路可能引起显示缺陷、显示面板竖线(也称为XLine)不良或者显示面板横线(也称为Y Line)不良等情况。
示例性地，如图1所示，在显示基板中，导线a1与导线a2相邻。当导线a1被烧熔时，烧熔的液体会流向相邻的导线a2，从而导致导线a1与a2发生短路并且引起显示不良。例如，在图1所示的示意图中，导线a1和导线a2之间可以存在s1和s2这两个短路点。
图2是根据本公开的实施例的一种显示基板的剖视图。如图2所示，该显示基板可以包括：衬底基板01，以及设置在该衬底基板01上的绝缘层02和多条导线03。
图3是根据本公开的实施例的一种显示基板的俯视图，并且图2为沿着图3中的AA方向的剖视图。如图3所示，衬底基板01可以包括位于中心的显示区域S2和围绕显示区域S2的封装区域S1。进一步地，参照图3，位于衬底基板01上的绝缘层02可以包括位于该衬底基板01的封装区域S1中的至少一个凹槽021，例如，在图3中作为示例而示出的五个凹槽。此外，每一个凹槽021与多条导线03中的一条导线一一对应。如图3所示，每一条导线03可以包括位于显示区域S2中的第一部分0301和位于封装区域中的第二部分0302。进一步可选地，每一条导线03还可以包括位于整个衬底基板01之外的第三部分0303。对于图3中的每一条导线03中，其位于该封装区域S1中的第二部分0302可以设置在对应的一个凹槽021内。在这样的情况下，可以通过该凹槽021将相邻的导线03隔离开。
此处，需要指出的是，虽然在图3中示出了与每一条导线03对应地存在一个凹槽021，并且该导线03包括布置于对应的凹槽021内的第二部分0302，但是这并不代表对本公开的任何限制。事实上，在本公开的实施例中，还可以存在其它的导线03，其也许可能具有位于封装区域S1中的第二部分0302，但是这样的第二部分0302未必设置在对应的凹槽021内。
而且，还需要说明的是，虽然在图3中作为示例示出了每一个导线03位于衬底基板01之外的第三部分0303，但是这并不代表对本公开的任何限制，实际上，根据其它可选的实施例，导线03中的一个或多个也可以不包括这样的第三部分0303。这意味着，导线03借助于其在衬底基板01的边缘处的端面而与外界单元电气连接。对此，本领域 技术人员应当是容易领会到的。
进一步地，在本文的描述中，封装区域S1可以指的是以下区域：在通过封装胶将显示基板与封装盖板进行封装的过程中，该显示基板上的膜层与封装胶接触的区域在该衬底基板上的正投影。从图3可以看出，该封装区域S1可以为位于衬底基板周边的回字形区域。作为示例，该多条导线03可以为用于为衬底基板上的驱动晶体管提供驱动信号的导线，并且每一条导线的输入端可以与位于衬底基板之外的驱动芯片连接。示例性地，每一条导线可以为栅线、数据线、公共电极线和电源信号线中的任一种。
需要说明的是，如果在显示基板中需要穿过封装区域S1以与外部芯片连接的多条导线当中，存在熔点较高且烧熔短路风险较低的导线，则这样的导线的第二部分可以无需设置在凹槽中。也就是说，每一个凹槽可以与多条导线当中烧熔短路风险较高的一条导线一一对应，并且这一条烧熔短路风险较高的导线可以包括设置在一个对应凹槽内的第二部分。
综上所述，在本公开的实施例中，提供了一种显示基板。具体地，该显示基板中的绝缘层包括位于封装区域中的至少一个凹槽。此外，显示基板中的至少一条导线包括位于封装区域中的一个对应凹槽内的第二部分。以这样的方式，可以通过凹槽将相邻的导线隔开。在这样的情况下，即使位于凹槽内的某一条导线在封装的过程中由于高温而烧熔，它也不会与其他相邻的导线发生短路。由此，有效地降低了显示不良的发生概率。
可选地，如图2和图3所示，绝缘层02位于封装区域S1中的每一个凹槽021都唯一地对应于多条导线03中的一个的第二部分，即，凹槽021与导线03(及其第二部分)一一对应。这意味着，在该多条导线03中，每一条导线03都包括位于封装区域中的一个对应凹槽内的第二部分。也就是说，在该显示基板中需要穿过封装区域以与外部芯片连接的多条导线当中，每一条导线均可以包括设置在对应的一个凹槽内的第二部分，从而可以有效地降低导线发生短路的风险。
进一步地，依照本公开的实施例，在多个凹槽021当中，每一个凹槽的宽度w1可以与对应导线的第二部分的线宽w2正相关。也就是说，对于任意两个凹槽而言，如果设置在第一凹槽中的导线的第二部 分的线宽大于设置在第二凹槽中的导线的第二部分的线宽，则相应地，该第一凹槽的宽度就可以大于该第二凹槽的宽度。
而且，任意两个相邻凹槽之间的间距w3可以与对应的两条导线的第二部分之间的间距w4正相关。也就是说，如果相邻两条导线(具体地，其第二部分)之间的间距越小，则与这两条导线对应的两个凹槽之间的间距也就越小。与此相反，如果相邻两条导线(具体地，其第二部分)之间的间距越大，则与这两条导线对应的两个凹槽之间的间距也就越大。这意味着，显示基板中的导线的密度越高，相邻凹槽之间的间距就越小。
此处，需要说明的是，在本公开的描述中，每一个凹槽的宽度方向可以平行于导线(例如，其第二部分)的线宽方向，并且两个凹槽之间的间距可以是指两个凹槽之间的绝缘材料的厚度，其中，该厚度方向平行于导线(例如，其第二部分)的线宽方向。
作为一种可选的实现方式，如图4所示，绝缘层02还包括位于该衬底基板01的封装区域中的多个间隔设置的绝缘块022。进一步地，每一个凹槽021可以包括两个不与导线的第二部分接触的侧壁(例如，图中的左右两个侧壁)。参照图4，这两个侧壁可以由对应的两个绝缘块022的侧壁分别构成。相应地，每一个凹槽021还可以包括一个底壁，其中，该底壁可以由衬底基板01的上表面的部分构成。这意味着，每一个凹槽021可以贯穿该绝缘层02的整个厚度，并且每一条导线03的第二部分可以直接在封装区域中形成于衬底基板01的上表面上。
作为另一种可选的实现方式，如图5所示，每一个凹槽021也可以不贯穿通过绝缘层02的整个厚度。也就是说，每一个凹槽021的底壁并不是衬底基板01的上表面部分，而是相反地，同样由绝缘材料形成。例如，该绝缘材料可以为用于形成绝缘层02的相同材料。在这样的情况下，进一步地，每一条导线03位于封装区域中的第二部分可以设置在对应的凹槽021内，并且形成在绝缘材料远离衬底基板01的一侧上。
此外，结合图3和图4，还可以看出，每一个绝缘块022靠近显示区域S2的一端可以与位于该显示区域S2中的绝缘层的部分相连。也就是说，该绝缘层中的每一个凹槽021可以包括三个依次连接的侧壁，并且未设置侧壁的一侧(即开口的一侧，例如，图3中的上侧)可以 供导线与外部芯片连接。如图4所示，在这三个侧壁当中，相对设置的侧壁a和侧壁b不与导线(特别地，其第二部分)接触。具体地，该侧壁a和侧壁b可以由相邻的两个绝缘块022的侧壁分别构成。此外，用于连接该侧壁a和侧壁b的侧壁c可以由位于显示区域S2中的绝缘层的部分构成。此外，该侧壁c与导线(特别地，其第二部分)接触，并且导线可以跨过该侧壁c而从显示区域延伸至凹槽021内。
进一步地，如图4所示，每一个凹槽021的深度h1可以大于对应导线03(特别地，其第二部分)的厚度h2。以这样的方式，当设置在某个凹槽内的导线03的第二部分0302被高温烧熔时，烧熔的液体将不会流入到相邻的凹槽内，由此实现了相邻导线的有效隔离。具体地，凹槽021的深度方向和导线03(特别地，其第二部分0302)的厚度方向可以均垂直于该衬底基板01的延伸表面。例如，该凹槽的深度方向可以为图4所示的X方向。
可选地，每一个凹槽021的宽度w1可以大于对应导线03的第二部分0302的线宽w2。由此，可以保证在形成导线时，每一条导线的第二部分能够完全形成在对应的凹槽内。进一步地，有利于促进通过凹槽对相邻导线的有效隔离。具体地，如图4所示，凹槽的宽度方向Y可以平行于导线(特别地，其第二部分)的线宽方向。
进一步地，继续参考图4，每一个凹槽021可以包括两个不与导线03的第二部分0302接触的侧壁(例如，侧壁a和侧壁b)，并且在不与导线03的第二部分0302接触的每一个侧壁和对应导线03的第二部分0302之间，存在宽度方向Y上的间距d1，其可以大于或等于1微米(μm)。也就是说，在每一条导线的第二部分与凹槽的侧壁之间，可以存在一定的间隙。该间隙可以用于存储导线烧熔后所产生的液体，进而可以避免液体从凹槽溢出并且流入到相邻的凹槽内。
可选地，在各个凹槽中，侧壁与导线的第二部分之间的间距d1可以与该导线的第二部分的线宽正相关。也就是说，导线的第二部分的线宽越宽，该间距d1就可以越大。以这样的方式，可以保证导线的第二部分与侧壁之间的间隙能够有效地存储导线烧熔后所产生的液体，以避免液体溢出。
可选地，每一个绝缘块022的宽度w3可以大于或等于3微米。通过将每一个绝缘块022的宽度w3设置得较宽，可以避免绝缘块被烧熔 的导线穿透，从而保证通过该绝缘块的良好隔离效果。具体地，绝缘块022的宽度方向Y可以平行于凹槽021的宽度方向，或者说，可以平行于导线03的第二部分0302的宽度方向。
进一步地，如图4所示，每一条导线03的第二部分0302可以包括层叠设置的多个导电层。具体地，在这多个导电层中，相邻的两个导电层可以由不同的导电材料制成。
示例性地，在图4所示的结构中，每一条导线03的第二部分0302可以包括层叠设置的三个导电层031、032和033，其中，导电层031和导电层033可以由金属钛制成，并且导电层032可以由金属铝制成。此外，在这三个导电层中，导电层033的厚度可以为300埃
Figure PCTCN2018110760-appb-000001
导电层032的厚度可以为
Figure PCTCN2018110760-appb-000002
并且导电层031的厚度可以为
Figure PCTCN2018110760-appb-000003
由此，每一条导线03的第二部分0302的总厚度h2可以为
Figure PCTCN2018110760-appb-000004
相应地，每一个凹槽021的深度h1可以大于
Figure PCTCN2018110760-appb-000005
综上所述，本公开的实施例提供了一种显示基板。在该显示基板中，绝缘层包括位于封装区域中的至少一个凹槽，并且至少一条导线包括位于封装区域中的一个对应凹槽内的第二部分。由此，可以通过凹槽将相邻的导线(特别地，其第二部分)隔离开。在这样的情况下，即使位于凹槽内的某一条导线(特别地，其第二部分)在封装的过程中被高温烧熔，它也不会与其他相邻的导线发生短路，从而有效地降低了显示不良发生的概率。
图6是根据本公开的实施例的一种用于显示基板的制造方法的流程图。该方法可以用于制造在上述实施例中提供的显示基板。参考图6，该方法可以包括以下步骤。
步骤101、提供衬底基板。
具体地，该衬底基板包括显示区域和围绕所述显示区域的封装区域。
步骤102、在衬底基板上形成绝缘层和多条导线。
具体地，所述绝缘层被形成为包括位于所述封装区域中的至少一个凹槽；所述多条导线中的至少一个被形成为包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分；并且在每一个凹槽内仅形成一个所述第二部分
在本公开的实施例中，该绝缘层可以为层间绝缘层(inter-layer  Dielectric，ILD)。如图7所示，在形成该层间绝缘层02之前，该衬底基板01的显示区域S2内已经形成有有源层04、栅绝缘层05和栅电极06。该层间绝缘层02可以整层覆盖在衬底基板01的表面之上，即，覆盖在封装区域S1以及显示区域S2之上。
在本公开的实施例中，可以首先形成绝缘材料膜，并且然后对该绝缘材料膜位于该衬底基板的封装区域中的部分进行图形化处理，以形成所述至少一个凹槽。
可选地，可以根据多条导线当中熔点较低且烧熔短路风险较高的导线的数量来确定需要形成的凹槽的数量。此外，还可以根据熔点较低的每一条导线的第二部分在该封装区域中的具体位置来确定每个凹槽的形成位置。
可替换地，也可以在绝缘材料膜位于封装区域中的部分形成与多条导线一一对应的多个凹槽。也就是说，可以根据该显示基板中需要穿过封装区域以与外部芯片连接的导线的数量来确定该凹槽的数量。此外，还可以根据每一条导线的第二部分在该封装区域中的具体位置来确定每一个凹槽的形成位置。
进一步地，可以在形成有绝缘层(包括位于封装区域中的凹槽)的衬底基板上沉积导电膜层，并且对该导电膜层进行图形化处理，以形成多条导线。在这样的多条导线当中，至少一条导线可以包括设置在一个对应凹槽内的第二部分。作为示例，这样的至少一条导线可以为多条导线当中熔点较低且烧熔短路风险较高的导线。
综上所述，本公开的实施例提供了一种用于显示基板的制造方法。通过该制造方法，使得绝缘层包括位于封装区域中的至少一个凹槽，并且至少一条导线包括位于封装区域中的一个对应凹槽内的第二部分。以这样的方式，可以通过凹槽将相邻的导线(特别地，其第二部分)隔离开。在这样的情况下，即使位于凹槽中的某条导线(特别地，其第二部分)在封装的过程中被高温烧熔，它也不会与其他相邻的导线短路，从而有效地降低了显示不良发生的概率。
可选地，在上述制造方法中，还可以在绝缘材料膜位于封装区域中的部分形成与多条导线一一对应的多个凹槽。以这样的方式，使得在所形成的多条导线当中，每一条导线都包括位于封装区域中的一个对应凹槽内的第二部分。由此，可以实现导线之间的有效隔离，并且 进一步降低导线之间发生短路的风险。
可选地，如图7所示，绝缘层02可以选择为层间绝缘层。在这样的情况下，上述制造方法还可以包括以下步骤：采用接触孔掩膜板在层间绝缘层位于该衬底基板的显示区域中的部分上形成接触过孔。
在用于形成显示基板中的驱动晶体管的过程中，需要通过接触孔掩膜板在层间绝缘层02上形成接触过孔023。该接触过孔023可以贯穿层间绝缘层02和栅绝缘层05，以用于连接驱动晶体管中的有源层04和源漏电极。
在本公开的实施例中，参考图8，当采用接触孔掩膜板在层间绝缘层02位于显示区域S2中的部分上形成接触过孔023时，可以同步地在层间绝缘层02位于封装区域S1中的部分上形成至少一个凹槽021(图8中仅示出了一个凹槽)。进一步地，结合图3，可以看出，每一个凹槽可以包括三个侧壁。在该三个侧壁当中，位于该封装区域S1中的两个相对设置的侧壁a和侧壁b可以由两个相邻的绝缘块的侧壁构成，并且位于该显示区域S2中的侧壁c可以由位于该显示区域S2中的绝缘层部分构成。此外，该凹槽021的底壁可以为该衬底基板01的表面部分。
通过在采用该接触孔掩膜板于显示区域S2中形成接触孔的过程中同步地形成该至少一个凹槽，可以避免增加显示基板的制造工艺流程并且由此降低制造成本。
相应地，用于显示基板的制造方法还可以包括以下步骤：在形成有绝缘层的衬底基板上继续形成源漏电极和多条导线。
在本公开的实施例中，可以在形成有层间绝缘层02的衬底基板01上形成导电膜层，然后再采用掩膜板对该导电膜层进行图形化处理，以得到源漏电极和多条导线。多条导线中的至少一条导线位于封装区域的第二部分可以形成在对应的凹槽内。
示例性地，图9是根据本公开的实施例的沿着图3中的BB方向的剖视图。如图9所示，位于显示区域S2中的源漏电极06可以通过该接触过孔023与有源层05连接，并且导线03可以与该源漏电极06连接。此外，导线03位于封装区域S1中的第二部分形成在该凹槽021内。从图9还可以看出，导线03可以跨过侧壁c而从显示区域S2延伸至凹槽021内。
可选地，在上述过程中形成的导电膜层可以包括多个导电层。在该多个导电层中，相邻的两个导电层可以由不同的导电材料制成。例如，该导电膜层可以包括层叠设置的三个导电层，其中，该三个导电层可以依次由金属钛、金属铝和金属钛制成。
可选地，在以上描述的用于形成凹槽的过程中，要求每一个凹槽的宽度大于对应导线的第二部分的线宽，并且还要求每一个凹槽的深度大于对应导线的第二部分的厚度，以保证该凹槽能够对相邻导线进行有效隔离。
需要说明的是，在上述制造方法中应用的图形化处理工艺具体可以包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等步骤。
还需要说明的是，在本公开的实施例中，根据显示基板中所形成的驱动晶体管的结构的不同，该绝缘层的类型也可以有所不同。例如，该绝缘层还可以为用于隔离栅电极和有源层的栅绝缘层等，并且本公开的实施例对此不做限定。
还需要说明的是，在本公开的实施例中，用于显示基板的制造方法的步骤的执行顺序可以进行适当调整。此外，步骤也可以根据情况进行相应增减。例如，一个步骤可以在另一个步骤之前、之后或者同时执行。具体地，作为示例，可以先形成导线，并且然后再形成凹槽。熟悉本技术领域的任何技术人员在本申请揭露的技术范围内可容易设想到的各种变化，都应涵盖在本申请的保护范围之内，因此不再赘述。
综上所述，本公开的实施例提供了一种用于显示基板的制造方法。通过该制造方法，可以使绝缘层包括位于封装区域中的至少一个凹槽，并且至少一条导线包括位于封装区域中的一个对应凹槽内的第二部分。以这样的方式，可以通过凹槽将相邻的导线隔离开。在这样的情况下，即使位于凹槽内的某条导线(特别地，其第二部分)在封装的过程中被高温烧熔，它也不会与其他相邻的导线发生短路，从而有效地降低了显示不良的概率。
根据本公开的实施例，还提供了一种用于显示面板的封装方法。该封装方法可以包括以下步骤。
步骤S1、提供显示基板。
具体地，该显示基板可以选择为以上在任一个实施例中描述的显示基板。
步骤S2、提供封装盖板。
具体地，该封装盖板具有与显示基板的封装区域对应的封装区域。
步骤S3、在封装盖板的封装区域形成封装胶。
作为示例，该封装胶可以为玻璃胶。当将该封装盖板放置在显示基板上时，该封装盖板的封装区域在显示基板的衬底基板上的正投影，与该衬底基板的封装区域相重合。
步骤S4、在两个封装区域对齐的情况下将显示基板对准在该封装盖板上。
在本公开的实施例中，可以将显示基板上形成有膜层的一侧朝向该封装盖板，并且将该显示基板对准在该封装盖板上，使得显示基板上的膜层与该封装盖板上的封装胶接触。
步骤S5、采用激光照射该封装胶以完成封装。
进一步地，可以采用激光照射该封装胶，使得该封装胶在高温下烧结，进而将显示基板与显示盖板密封在一起。显示基板与显示盖板在密封后形成的显示面板可以如图10所示。
在该封装胶烧结的过程中，由于每一条导线位于封装区域中的第二部分都设置在绝缘层的凹槽内，因此即使某一条导线被高温烧熔，被烧熔的这条导线也不会与相邻导线接触。以这样的方式，可以有效地避免相邻导线之间发生短路，从而导致显示不良等现象。
本公开的实施例还提供了一种显示面板。参考图10，该显示面板可以包括：封装盖板100和显示基板000。具体地，该显示基板000可以为在图2至图5以及图9中任一个所示的显示基板。参考图10，可以看出，该显示基板000可以通过封装胶200与该封装盖板100密封在一起。
本公开的实施例还提供了一种显示装置。该显示装置可以包括如图10所示的显示面板。该显示装置可以为诸如液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等等具有显示功能的任何产品或部件。
以上所述仅为本公开的较佳实施例，并且不用以限制本公开。凡在本公开的精神和原则之内所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种显示基板，包括：
    衬底基板，所述衬底基板包括显示区域和围绕所述显示区域的封装区域；以及
    设置在所述衬底基板上的绝缘层和多条导线，其中，
    所述绝缘层包括位于所述封装区域中的至少一个凹槽；
    所述多条导线中的至少一个包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分；并且
    每一个凹槽内仅存在一个所述第二部分。
  2. 根据权利要求1所述的显示基板，其中，
    所述多条导线中的每一个都包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分。
  3. 根据权利要求2所述的显示基板，其中，
    每一个凹槽的宽度随着对应导线的第二部分的线宽的增大而增大；以及
    相邻两个凹槽之间的间距随着对应两条导线的第二部分之间的间距的增大而增大，
    其中，每一个凹槽的宽度方向平行于对应导线的第二部分的线宽方向。
  4. 根据权利要求2所述的显示基板，其中，
    相邻两个凹槽通过绝缘块间隔开。
  5. 根据权利要求1所述的显示基板，其中，
    每一个凹槽包括靠近所述衬底基板的底壁以及与所述底壁相交并且不与对应导线的第二部分接触的两个侧壁。
  6. 根据权利要求5所述的显示基板，其中，
    每一个凹槽的底壁由所述衬底基板靠近所述凹槽的表面的部分或者绝缘材料形成。
  7. 根据权利要求1至6中任一所述的显示基板，其中，
    每一个所述凹槽的深度大于对应导线的第二部分的厚度，其中，所述凹槽的深度方向和对应导线的第二部分的厚度方向均垂直于所述衬底基板的延伸面。
  8. 根据权利要求1至6中任一所述的显示基板，其中，
    每一个所述凹槽的宽度大于对应导线的第二部分的线宽，其中，所述凹槽的宽度方向平行于对应导线的第二部分的线宽方向。
  9. 根据权利要求8所述的显示基板，其中，
    每一个所述凹槽包括不与对应导线的第二部分接触的两个侧壁，其中，每一个所述侧壁与对应导线的第二部分在所述凹槽的宽度方向上以大于或等于1微米的间距隔开。
  10. 根据权利要求4所述的显示基板，其中，
    每一个所述绝缘块的宽度大于或等于3微米，其中，所述绝缘块的宽度方向平行于所述凹槽的宽度方向。
  11. 根据权利要求1至6中任一所述的显示基板，其中，
    至少每一条所述导线的第二部分包括层叠设置的多个导电层，其中，相邻的两个导电层由不同的导电材料制成。
  12. 一种用于显示基板的制造方法，包括：
    提供衬底基板，所述衬底基板包括显示区域和围绕所述显示区域的封装区域；以及
    在衬底基板上形成绝缘层和多条导线，其中，
    所述绝缘层被形成为包括位于所述封装区域中的至少一个凹槽；
    所述多条导线中的至少一个被形成为包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分；并且
    在每一个凹槽内仅形成一个所述第二部分。
  13. 根据权利要求12所述的方法，其中，
    所述多条导线中的每一个都被形成为包括位于所述显示区域中的第一部分和位于所述封装区域中的一个对应凹槽内的第二部分。
  14. 根据权利要求12所述的方法，其中，
    所述绝缘层包括层间绝缘层；以及
    所述方法还包括以下步骤：
    在所述层间绝缘层靠近所述衬底基板的一侧上并且在所述衬底基板的显示区域中形成有源层；
    采用接触孔掩膜板在所述层间绝缘层位于所述衬底基板的显示区域中的部分上形成接触过孔；以及
    在形成有所述层间绝缘层的衬底基板上继续形成源漏电极。
  15. 一种用于显示面板的封装方法，包括：
    提供根据权利要求1至11中任一所述的显示基板；
    提供封装盖板，所述封装盖板具有与所述显示基板的封装区域对应的封装区域；
    在所述封装盖板的封装区域中形成封装胶；
    在两个封装区域对齐的情况下将所述显示基板对准在所述封装盖板上；以及
    采用激光照射所述封装胶以完成封装。
  16. 一种显示面板，包括：
    封装盖板；以及
    根据权利要求1至11中任一所述的显示基板，其中，
    所述显示基板通过封装胶与所述封装盖板密封在一起。
PCT/CN2018/110760 2017-11-27 2018-10-18 显示基板及其制造方法以及对应显示面板及其封装方法 WO2019100874A1 (zh)

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