WO2021232989A1 - 晶体管以及集成电路 - Google Patents

晶体管以及集成电路 Download PDF

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Publication number
WO2021232989A1
WO2021232989A1 PCT/CN2021/086023 CN2021086023W WO2021232989A1 WO 2021232989 A1 WO2021232989 A1 WO 2021232989A1 CN 2021086023 W CN2021086023 W CN 2021086023W WO 2021232989 A1 WO2021232989 A1 WO 2021232989A1
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Prior art keywords
transistor
area
contact holes
source
drain
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PCT/CN2021/086023
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English (en)
French (fr)
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刘君
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Oppo广东移动通信有限公司
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Publication of WO2021232989A1 publication Critical patent/WO2021232989A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

Definitions

  • This application relates to the technical field of semiconductor devices, in particular to a transistor and an integrated circuit.
  • a metal oxide semiconductor field effect transistor that can drive a larger output current is required.
  • the size of the metal oxide semiconductor field effect transistor is usually Larger.
  • the embodiments of the present application expect to provide a transistor and an integrated circuit, and the transistor has a smaller size.
  • the technical solutions of the embodiments of the present application are implemented as follows:
  • One aspect of the embodiments of the present application provides a transistor, including:
  • the mesh grid is located on the substrate.
  • the mesh grid includes a first portion spaced apart along a first direction and a second portion spaced apart along a second direction, a plurality of the first portions and a plurality of Staggered distribution of the second part divides the substrate into a plurality of separate areas, wherein the first direction is perpendicular to the second direction;
  • the drain electrode, the source electrode and the drain electrode are alternately distributed in the separation area along a first direction, and the source electrode and the drain electrode are alternately distributed in the separation area along a second direction.
  • the area of the adjacent source electrode and the area of the drain electrode are not equal.
  • the transistor includes a contact hole located in the separated area, and the number of the contact hole in at least one of the separated area is multiple.
  • the transistor is an N-type metal oxide semiconductor field effect transistor, and the total area of the drain is larger than the total area of the source.
  • the number of the contact holes in at least one of the drains is multiple, and the multiple contact holes in the drains are distributed along a first direction and a second direction.
  • the total number of the contact holes in the drain electrode is greater than the total number of the contact holes in the source electrode.
  • the transistor is a P-type metal oxide semiconductor field effect transistor, and the total area of the source electrode is larger than the total area of the drain electrode.
  • the number of the contact holes in at least one of the source electrodes is multiple, and the multiple contact holes in the source electrodes are distributed along a first direction and a second direction.
  • the total number of the contact holes in the source electrode is greater than the total number of the contact holes in the drain electrode.
  • the total number of the first part is not equal to the total number of the second part.
  • the embodiments of the present application also provide an integrated circuit, which includes any of the above-mentioned transistors.
  • the transistor provided by the embodiment of the present application can not only drive a larger output current, but also has a smaller area. In this way, the parasitic resistance and parasitic capacitance of the transistor can be effectively reduced.
  • the integrated circuit provided by this embodiment includes the above-mentioned transistors. Because the transistors provided by the embodiments of the present application have a small area, it can avoid occupying too much area of the integrated circuit, making the integrated circuit layout more compact, with higher integration, and the integrated circuit occupies The area is smaller.
  • FIG. 1 is a schematic plan view of a metal oxide semiconductor field effect transistor in a first embodiment of the prior art
  • FIG. 2 is a schematic plan view of a metal oxide semiconductor field effect transistor in a second embodiment of the prior art
  • FIG. 3 is a schematic plan view of the transistor in the first embodiment of the application.
  • FIG. 4 is a schematic plan view of the smallest unit of the transistor in FIG. 3;
  • FIG. 6 is a schematic plan view of the smallest unit of the transistor in FIG. 5.
  • the application will be further described in detail below in conjunction with the drawings and specific embodiments.
  • the “ ⁇ m” in the embodiments of this application refers to the international unit micron.
  • the orientation or positional relationship is based on the orientation or positional relationship in FIG. 3 and FIG. 5. It should be understood that these orientation terms are only It is for the convenience of describing the application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and the structural dimensions of the embodiments of this application are expanded for ease of presentation.
  • the size in does not represent the actual size, and therefore cannot be understood as a limitation of the application.
  • the transistor 100 includes a substrate, a mesh gate 10, a source 20 and a drain 30.
  • the mesh gate 10 is located on the substrate.
  • the mesh grid 10 includes first portions 11 spaced apart along the first direction and second portions 12 spaced apart along the second direction.
  • the plurality of first parts 11 and the plurality of second parts 12 are distributed alternately to partition the substrate into a plurality of separate regions.
  • the first direction is perpendicular to the second direction.
  • the source electrode 20 and the drain electrode 30 are alternately distributed in the partition area along the first direction, and the source electrode 20 and the drain electrode 30 are alternately distributed in the partition area along the second direction.
  • the transistor 100 may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor), which refers to the diffusion of ions on a substrate to form a drain (Drain) and a source ( Source), there is an insulating layer between the gate dielectric and the substrate, the insulating layer and the gate dielectric together form a gate (Gate), the substrate under the insulating layer is formed with a channel, and the drain and source are located on both sides of the channel .
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the drain electrode, the source electrode, and the gate electrode are electrically connected to the metal layer through the contact hole to realize the conduction of the integrated circuit.
  • the length of the gate electrode is the length of the channel.
  • the gate dielectric may be polysilicon.
  • the substrate may be a semiconductor such as monocrystalline silicon, polycrystalline silicon, gallium arsenide, etc., and the form of the substrate in the embodiment of the present application is not limited.
  • the insulating layer between the gate dielectric and the substrate can be oxide or other insulating materials.
  • the insulating layer can be silicon dioxide, silicon oxynitride, etc.
  • the material of the insulating layer is not limited in the embodiments of the present application.
  • the metal oxide semiconductor field effect transistor usually includes a P type metal oxide semiconductor field effect transistor and an N type metal oxide semiconductor field effect transistor.
  • P-type metal oxide semiconductor field effect transistor refers to a metal oxide semiconductor field effect transistor that uses holes as channel carriers.
  • the substrate of a P-type metal oxide semiconductor field effect transistor is an N-type substrate.
  • An N-well can be formed on a P-type substrate, and then ions can be diffused on the N-well to form a drain and a source.
  • the source of the P-type metal oxide semiconductor field effect transistor is connected to the output terminal.
  • An N-type metal oxide semiconductor field effect transistor refers to a metal oxide semiconductor field effect transistor that uses electrons as channel carriers.
  • the substrate of a P-type metal oxide semiconductor field effect transistor is an N-type substrate.
  • the drain of the N-type metal oxide semiconductor field effect transistor is connected to the output terminal.
  • the adjacent first portion 11 and the second portion 12 are jointly enclosed to form a separate area (please refer to FIG. 4 and FIG. 6).
  • the source electrode 20 and the drain electrode 30 are alternately distributed in the partition area along the first direction, and the source electrode 20 and the drain electrode 30 are alternately distributed in the partition area along the second direction. That is, the two sides of the first part 11 along the first direction are the source 20 and the drain 30 respectively, and the two sides of the second part 12 along the second direction are the source 20 and the drain 30 respectively. In this way, a longer channel can be formed on a smaller area substrate, so that a transistor capable of driving a larger output current can be formed on a smaller area substrate.
  • the transistor 100 provided by the embodiment of the present application can not only drive a larger output current, but also has a smaller area. In this way, the parasitic resistance and parasitic capacitance of the transistor 100 can be effectively reduced. Since the transistor 100 provided by the embodiment of the present application has a small area, it can avoid occupying too much area of the integrated circuit, so that the layout of the integrated circuit is more compact, the integration level is higher, and the area occupied by the integrated circuit is smaller.
  • the first part 11 and the second part 12 may be elongated structures.
  • all the source and all the contact holes on the drain are not shown in FIGS. 3 to 6, and those skilled in the art can directly obtain the results that cannot be shown according to the solutions described in the embodiments of the present application. The distribution of the contact holes on the source and drain will not be repeated here.
  • the area of the adjacent source electrode 20 and the area of the drain electrode 30 are not equal.
  • the source 20 and the drain 30 have an asymmetric structure. In this way, the area of the transistor 100 can be further reduced.
  • the area of the adjacent source electrode 20 is equal to the area of the drain electrode 30.
  • the source 20 and the drain 30 have a symmetrical structure.
  • the transistor 100 includes a contact hole 40 located in a separate area, and the number of contact holes 40 in at least one separate area is multiple.
  • a plurality of contact holes 40 are provided so that the source electrode 20 and/or the drain electrode 30 are better electrically connected to the metal layer. That is to say, there may be multiple contact holes 40 in at least one source 20; it may also be multiple contact holes 40 in at least one drain 30; and it may also be multiple sources 20 and multiple drains 30. Each has a plurality of contact holes 40.
  • the transistor 100 is an N-type metal oxide semiconductor field effect transistor, and the total area of the drain 30 is larger than the total area of the source 20. That is, the sum of the areas of all the drains 30 is greater than the sum of the areas of all the sources 30. Since the drain 30 of the N-type metal oxide semiconductor field effect transistor is electrically connected to the output terminal, the total area of the drain 30 is greater than the total area of the source 20, which ensures that the N-type metal oxide semiconductor field effect transistor has a smaller size. Under the condition of the area, the area of the drain 30 is larger, so that the drain 30 is better electrically connected to the output terminal.
  • the number of contact holes 40 in at least one drain 30 is multiple, and the multiple contact holes 40 in the drain 30 are distributed along the first direction and the second direction.
  • the total number of contact holes 40 in the drain 30 is greater than the total number of contact holes 40 in the source 20. That is, the sum of the number of contact holes 40 in all the drain electrodes 30 is greater than the sum of the number of contact holes 40 in all the source electrodes 20. Since the drain 30 of the N-type metal oxide semiconductor field effect transistor is electrically connected to the output terminal, the more contact holes 40 of the drain 30, the larger the area of electrical connection with the pad of the external device, thereby better preventing electrostatic discharge The N-type metal oxide semiconductor field effect transistor is damaged, so that the N-type metal oxide semiconductor field effect transistor has better withstand voltage.
  • the transistor 100 is a P-type metal oxide semiconductor field effect transistor, and the total area of the source electrode 20 is larger than the total area of the drain electrode 30. That is, the sum of the areas of all the source electrodes 20 is greater than the sum of the areas of all the drains 30. Since the source 20 of the P-type metal oxide semiconductor field effect transistor is electrically connected to the output terminal, the total area of the source 20 is greater than the total area of the drain 30, which ensures that the P-type metal oxide semiconductor field effect transistor has a smaller size. Under the condition of the area, the area of the source electrode 20 is larger, so that the source electrode 20 is better electrically connected to the output terminal.
  • the number of contact holes 40 in at least one source electrode 20 is multiple, and the multiple contact holes 40 in the source electrode 20 are distributed along the first direction and the second direction.
  • one and/or more than one source 20 has multiple contact holes 40, and the multiple contact holes 40 of the source 20 are distributed in a two-dimensional matrix along the first direction and the second direction. More contact holes 40 are provided in the electrode 20 so that the source electrode 20 is better electrically connected to the metal layer.
  • the total number of contact holes 40 in the source electrode 20 is greater than the total number of contact holes 40 in the drain electrode 30. That is, the sum of the number of contact holes 40 in all the source electrodes 20 is greater than the sum of the number of contact holes 40 in all the drain electrodes 30. Since the source electrode 20 of the P-type metal oxide semiconductor field effect transistor is electrically connected to the output terminal, the more contact holes 40 of the source electrode 20, the larger the electrical connection area with the pad of the external device, thereby better preventing electrostatic discharge The P-type metal oxide semiconductor field effect transistor is damaged, so that the voltage resistance of the P-type metal oxide semiconductor field effect transistor is better.
  • the minimum distance between two adjacent contact holes 40 is A
  • the minimum width of the contact hole 40 is B
  • the distance between two adjacent first parts 11 is L
  • the total number of the first part 11 is not equal to the total number of the second part 12. That is, the sum of the numbers of all the first parts 11 is not equal to the sum of the numbers of all the second parts 12. In this way, the arrangement of the first part 11 and the second part 12 is more flexible.
  • the total number of the first parts 11 is equal to the total number of the second parts 12. That is, the sum of the numbers of all the first parts 11 is equal to the sum of the numbers of all the second parts 12. In this way, the area of the transistor 100 can be further reduced.
  • An embodiment of the present application also provides an integrated circuit.
  • the integrated circuit includes the transistor 100 in any one of the foregoing embodiments. Since the transistor area provided by the embodiments of the present application is small, it can avoid occupying too much area of the integrated circuit, so that the integrated circuit layout is more compact, the integration level is higher, and the area occupied by the integrated circuit is smaller.
  • Multiple transistors 100 provided in the embodiments of the present application can be provided on the same substrate, and multiple transistors 100 are connected in parallel, so that a larger output current can be further driven.
  • Each transistor 100 can be surrounded by shallow trench isolation (STI, Shallow Trench Isolation) or local oxidation of silicon (LOCOS, Local Oxidation of Silicon), so as to avoid problems such as leakage and latch-up effects among multiple transistors 100 .
  • STI shallow trench isolation
  • LOCOS Local Oxidation of Silicon
  • the minimum spacing A between adjacent contact holes 40, the minimum width B of the contact hole 40, and the minimum spacing C between the contact hole 40 and the mesh gate 10 listed in the embodiments of the present application are only for example, and are not for this purpose.
  • the transistor 100 provided in the application embodiment is limited, and each embodiment will be described in detail below.
  • the minimum distance between two adjacent contact holes 104 is 0.26 ⁇ m
  • the minimum width of the contact hole 104 is 0.24 ⁇ m
  • the minimum distance between the contact hole 104 and the strip gate 101 is 0.8.
  • the N-type metal oxide semiconductor field effect transistor 1001 in the first embodiment of the prior art has a width of 46 ⁇ m and a length of 0.5 ⁇ m, and the number of strip gates 101 is 180.
  • the strip gates are defined
  • the length direction of the pole 101 is the first direction
  • the width direction of the strip-shaped gate 101 is the second direction.
  • the numerical unit is omitted.
  • 180 strip-shaped gates 101 are along the first direction. Interval distribution.
  • a contact hole 104 is provided in the drain electrode 103 and the source electrode 102, and the N-type metal oxide semiconductor field effect transistor 1001 formed in the first embodiment of the prior art
  • the area of the N-type metal oxide semiconductor field effect transistor 1001 of one embodiment is denoted as 100%.
  • the second embodiment of the prior art is to add a contact hole 104 in the drain 103 on the basis of the first embodiment of the prior art, that is, the second embodiment of the prior art
  • the difference between this embodiment and the first embodiment of the prior art is: in the second embodiment of the prior art, the number of contact holes 104 in the drain 103 of the N-type metal oxide semiconductor field effect transistor 1002 is two.
  • I ds is the current between the drain and the source when the guide is on
  • ⁇ n refers to the mobility of electrons
  • Cox refers to the capacitance of the channel
  • W refers to the width of the gate
  • L refers to the width of the gate.
  • V gs refers to the gate-source voltage
  • V th refers to the threshold voltage
  • V gs -V th is also called the driving voltage or the effective voltage.
  • the threshold voltage V th is the same, that is, the N-type metal oxide semiconductor field effect transistor 100 ′ of the first embodiment of the present application is the same as the N-type metal oxide semiconductor field effect transistor of the first embodiment of the prior art
  • the field effect transistor 1001 is an equivalent transistor.
  • the ratio of the area of the type MOS field effect transistor 100' to the area of the N type MOS field effect transistor 1001 of the first embodiment of the prior art is 66.4%.
  • the mesh grid 10 includes 191 first parts 11 spaced apart along the first direction, and 8 second parts spaced apart along the second direction
  • the 12,191 first parts 11 and the 8 second parts 12 are alternately distributed, and the area of the adjacent source electrode 20 and the area of the drain electrode 30 are not equal, that is, the source electrode 20 and the drain electrode 30 have an asymmetric structure.
  • the width of the mesh gate 10 of the second embodiment of the application is The width of the strip gate 101 in the first embodiment of the prior art is equal, and the length of the mesh gate 10 in the second embodiment of the present application is the same as that of the strip gate in the first embodiment of the prior art.
  • the length of the electrode 101 is equal, that is, the N-type MOSFET 100" of the second embodiment of the present application is the same as the N-type MOSFET of the first embodiment of the prior art 1001 is also an equivalent transistor.
  • Example name Area ( ⁇ m 2 ) percentage The first embodiment of the prior art 19375.2 100%
  • the transistor 100 of the embodiment of the present application can effectively reduce the area of the transistor.
  • the transistor 100 provided by the embodiment of the present application can be used not only in a low dropout linear regulator (LDO, Low Dropout Regulator), but also in a direct current (voltage) to direct current (voltage) converter (DCDC). direct current), it can also be used for other electronic devices or integrated circuits that need to drive a larger output current.
  • LDO Low Dropout linear regulator
  • DCDC direct current
  • direct current it can also be used for other electronic devices or integrated circuits that need to drive a larger output current.

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Abstract

一种晶体管（100），包括衬底、网状栅极（10）、源极（20）以及漏极（30），网状栅极（10）位于所述衬底上，所述网状栅极（10）包括沿第一方向间隔分布的第一部分（11）和沿第二方向间隔分布的第二部分（12），多个所述第一部分（11）和多个所述第二部分（12）交错分布将所述衬底分隔成多个分隔区域，其中，第一方向与第二方向垂直，所述源极（20）和所述漏极（30）沿第一方向交替分布于所述分隔区域中，且所述源极（20）和所述漏极（30）沿第二方向交替分布于所述分隔区域中。所述晶体管（100）不仅能够驱动较大的输出电流，还具有较小的面积。还提供一种集成电路，包括上述晶体管（100）。

Description

晶体管以及集成电路
相关申请的交叉引用
本申请基于申请号为202010437158.0、申请日为2020年05月21日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体器件技术领域，尤其涉及一种晶体管以及集成电路。
背景技术
在很多电路中需要用到能够驱动较大输出电流的金属氧化物半导体场效应晶体管，现有的金属氧化物半导体场效应晶体管为了达到合适的输出电流驱动能力，金属氧化物半导体场效应晶体管尺寸通常较大。
发明内容
有鉴于此，本申请实施例期望提供一种晶体管以及集成电路，晶体管具有较小尺寸。为实现上述效果，本申请实施例的技术方案是这样实现的：
本申请实施例一方面提供一种晶体管，包括：
衬底；
网状栅极，位于所述衬底上，所述网状栅极包括沿第一方向间隔分布的第一部分和沿第二方向间隔分布的第二部分，多个所述第一部分和多个所述第二部分交错分布将所述衬底分隔成多个分隔区域，其中，第一方向与第二方向垂直；
源极；以及
漏极，所述源极和所述漏极沿第一方向交替分布于所述分隔区域中，且所述源极和所述漏极沿第二方向交替分布于所述分隔区域中。
进一步地，相邻的所述源极的面积与所述漏极的面积不相等。
进一步地，所述晶体管包括位于所述分隔区域内的接触孔，至少一个所述分隔区域内的所述接触孔的数量为多个。
进一步地，所述晶体管为N型金属氧化物半导体场效应晶体管，所述漏极的总面积大于所述源极的总面积。
进一步地，至少一个所述漏极内的所述接触孔的数量为多个，所述漏极内的多个所述接触孔沿第一方向和第二方向分布。
进一步地，所述漏极内的所述接触孔的总数量大于所述源极内的所述接触孔的总数量。
进一步地，所述晶体管为P型金属氧化物半导体场效应晶体管，所述源极的总面积大于所述漏极的总面积。
进一步地，至少一个所述源极内的所述接触孔的数量为多个，所述源极内的多个所述接触孔沿第一方向和第二方向分布。
进一步地，所述源极内的所述接触孔的总数量大于所述漏极内的所述接触孔的总数量。
进一步地，所述第一部分的总数量与第二部分的总数量不相等。
本申请实施例另一方面还提供一种集成电路，包括上述任一项所述的晶体管。
本申请实施例提供的晶体管不仅能够驱动较大的输出电流，还具有较小的面积，如此，可以有效减小晶体管的寄生电阻和寄生电容。本实施例提供的集成电路包括上述晶体管，由于本申请实施例提供的晶体管面积较小，因此，能避免占据集成电路过多的面积，使得集成电路布局更加紧凑，集成度更高，集成电路占据的面积更小。
附图说明
图1为现有技术的第一个实施例中的金属氧化物半导体场效应晶体管的平面示意图；
图2为现有技术的第二个实施例中的金属氧化物半导体场效应晶体管的平面示意图；
图3为本申请的第一个实施例中的晶体管的平面示意图；
图4为图3中晶体管的最小单元的平面示意图；
图5为本申请的第二个实施例中的晶体管的平面示意图；
图6为图5中晶体管的最小单元的平面示意图。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的技术特征可以相互组合，具体实施方式中的详细描述应理解为本申请宗旨的解释说明，不应视为对本申请的不当限制。
下面结合附图及具体实施例对本申请再作进一步详细的说明。本申请实施例中的“μm”是指国际单位微米，在本申请的描述中方位或位置关系为基于附图3和附图5中的方位或位置关系，需要理解的是，这些方位术语仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，本申请实施例为便于展示，结构尺寸进行了扩大，图中的尺寸并不代表真实尺寸，因此不能理解为对本申请的限制。
请参见图3～图6，本申请实施例一方面提供一种晶体管，晶体管100包括衬底、网状栅极10、源极20以及漏极30。网状栅极10位于衬底上。网状栅极10包括沿第一方向间隔分布的第一部分11和沿第二方向间隔分布的第二部分12。多个第一部分11和多个第二部分12交错分布将衬底分隔成多个分隔区域。其中，第一方向与第二方向垂直。源极20和漏极30沿第一方向交替分布于分隔区域中，且源极20和漏极30沿第二方向交替分布于分隔区域中。
本申请实施例中为便于表述，图3～图6中，未展示出衬底、有源区、网状栅极的接触孔等结构，本领域技术人员能够理解的是，本申请实施例的晶体管100可以为金属氧化物半导体场效应晶体管(MOSFET，Metal-Oxide-Semiconductor Field-Effect Transistor)，金属氧化物半导体场效应晶 体管是指在衬底上扩散离子形成漏极(Drain)和源极(Source)，在栅介质和衬底之间具有绝缘层，绝缘层和栅介质共同构成栅极(Gate)，绝缘层下方的衬底形成有沟道，漏极和源极位于沟道的两侧。通过接触孔将漏极、源极、栅极分别与金属层电连接，从而实现集成电路的导通，栅极的长度即为沟道的长度。栅介质可以为多晶硅。衬底可以为单晶硅、多晶硅、砷化镓等半导体，本申请实施例中衬底的形式不限。在栅介质和衬底之间的绝缘层可以为氧化物也可以其他绝缘物质，示例性的，绝缘层可以为二氧化硅、氮氧化硅等，本申请实施例中绝缘层的材质不限。
根据栅极下的沟道的载流子的极性的不同，金属氧化物半导体场效应晶体管通常包括P型金属氧化物半导体场效应晶体管和N型金属氧化物半导体场效应晶体管。P型金属氧化物半导体场效应晶体管是指以空穴作为沟道载流子的金属氧化物半导体场效应晶体管，通常P型金属氧化物半导体场效应晶体管的衬底为N型衬底，当然也可以在P型衬底上形成N阱，再在N阱上扩散离子以形成漏极和源极。P型金属氧化物半导体场效应晶体管的源极连接输出端。N型金属氧化物半导体场效应晶体管是指以电子作为沟道载流子的金属氧化物半导体场效应晶体管，通常P型金属氧化物半导体场效应晶体管的衬底为N型衬底。当然也可以在N型衬底上形成P阱，再在P阱上扩散离子以形成漏极和源极。N型金属氧化物半导体场效应晶体管的漏极连接输出端。
本申请实施例中，相邻的第一部分11和第二部分12共同围设成一个分隔区域(请参见图4和图6)。源极20和漏极30沿第一方向交替分布于分隔区域中，且源极20和漏极30沿第二方向交替分布于分隔区域中。也就是说，第一部分11沿第一方向的两侧分别为源极20和漏极30，第二部分12沿第二方向的两侧分别为源极20和漏极30。如此，可以在较小面积的衬底上形成较长的沟道，以便在较小面积的衬底上形成能够驱动较大的输出电流的晶体管。本申请实施例提供的晶体管100不仅能够驱动较大的输出电流，还具有较小的面积，如此，可以有效减小晶体管100的寄生电阻和寄生电容。由于本申请实施例提供的晶体管100面积较小，还能避免占据集成电路过多的面积，使得集成电路 布局更加紧凑，集成度更高，集成电路占据的面积更小。
需要说明的是，本申请实施例中的多个是指数量为两个或两个以上。本申请实施例中，第一部分11和第二部分12可以为长条状结构。为便于清楚展示，图3～图6中未能展示出所有源极和所有漏极上的接触孔，本领域技术人员可以根据本申请实施例中写明的方案直接得出未能展示出的接触孔在源极和漏极上的分布，在此不再赘述。
在一实施例中，请参见图5和图6，相邻的源极20的面积与漏极30的面积不相等。也就是说，源极20与漏极30为非对称结构。如此，可以进一步减小晶体管100的面积。
在另一实施例中，请参见图3和图4，相邻的源极20的面积与漏极30的面积相等。也就是说，源极20与漏极30为对称结构。
在一实施例中，请参见图3～图6，晶体管100包括位于分隔区域内的接触孔40，至少一个分隔区域内的接触孔40的数量为多个。多个接触孔40以便源极20和/或漏极30更好地与金属层电连接。也就是说，可以是至少一个源极20内有多个接触孔40；也可以是至少一个漏极30内有多个接触孔40；还可以是多个源极20和多个漏极30内均有多个接触孔40。
在一实施例中，请参见图3～图6，晶体管100为N型金属氧化物半导体场效应晶体管，漏极30的总面积大于源极20的总面积。即所有漏极30的面积之和大于所有源极30的面积之和。由于N型金属氧化物半导体场效应晶体管的漏极30与输出端电连接，如此，漏极30的总面积大于源极20的总面积，在保证N型金属氧化物半导体场效应晶体管具有较小面积的条件下，漏极30面积更大，以便漏极30更好地与输出端电连接。
在一实施例中，请参见图3～图6，至少一个漏极30内的接触孔40的数量为多个，漏极30内的多个接触孔40沿第一方向和第二方向分布。也就是说，一个和/或一个以上漏极30内有多个接触孔40，漏极30的多个接触孔40沿第一方向和第二方向呈二维矩阵分布。如此，能够在漏极30内设置更多地接触孔40，以便漏极30更好地与金属层电连接。
在一实施例中，请参见图3～图6，漏极30内的接触孔40的总数量大于源极20内的接触孔40的总数量。即，所有漏极30内的接触孔40的数量之和大于所有源极20内的接触孔40的数量之和。由于N型金属氧化物半导体场效应晶体管的漏极30与输出端电连接，漏极30的接触孔40越多，与外部器件的焊盘的电连接面积更大，从而更好地防止静电放电损伤N型金属氧化物半导体场效应晶体管，使得N型金属氧化物半导体场效应晶体管的耐压性越好。
在一未示出的实施例中，晶体管100为P型金属氧化物半导体场效应晶体管，源极20的总面积大于漏极30的总面积。即，所有源极20的面积之和大于所有漏极30的面积之和。由于P型金属氧化物半导体场效应晶体管的源极20与输出端电连接，如此，源极20的总面积大于漏极30的总面积，在保证P型金属氧化物半导体场效应晶体管具有较小面积的条件下，源极20面积更大，以便源极20更好地与输出端电连接。
在一未示出的实施例中，至少一个源极20内的接触孔40的数量为多个，源极20内的多个接触孔40沿第一方向和第二方向分布。也就是说，一个和/或一个以上的源极20内有多个接触孔40，源极20的多个接触孔40沿第一方向和第二方向呈二维矩阵分布，如此，能够在源极20内设置更多地接触孔40，以便源极20更好地与金属层电连接。
在一未示出的实施例中，源极20内的接触孔40的总数量大于漏极30内的接触孔40的总数量。即所有源极20内的接触孔40的数量之和大于所有漏极30内的接触孔40的数量之和。由于P型金属氧化物半导体场效应晶体管的源极20与输出端电连接，源极20的接触孔40越多，与外部器件的焊盘的电连接面积更大，从而更好地防止静电放电损伤P型金属氧化物半导体场效应晶体管，使得P型金属氧化物半导体场效应晶体管的耐压性越好。
在一实施例中，请参见图6，相邻的两个接触孔40之间的最小间距为A，接触孔40的最小宽度为B，接触孔40与网状栅极20之间的最小间距为C，相邻的两个第一部分11之间的间距为L，一个分隔区域内沿第一方向分布的接触孔40的数量为N，其中，L＝C*2+N*B+(N-1)*A。也就是说，相邻的两个第一 部分11之间的间距按照符合版图设计规则的最小间距设置，如此，可以在符合版图设计规则的条件下，尽量减小晶体管100的面积。
在一实施例中，请参见图6，相邻的两个第二部分12之间的间距为H，一个分隔区域内沿第二方向分布的接触孔40的数量为S，其中，H＝C*2+S*B+(S-1)*A。也就是说，相邻的两个第二部分12之间的间距按照符合版图设计规则的最小间距设置，如此，可以在符合版图设计规则的条件下，尽量减小晶体管100。
在一实施例中，请参见图3～图6，第一部分11的总数量与第二部分12的总数量不相等。即所有第一部分11的数量之和与所有第二部分12的数量之和不相等。如此，使得第一部分11和第二部分12的设置更加灵活。
在另一未示出的实施例中，第一部分11的总数量与第二部分12的总数量相等。即所有第一部分11的数量之和与所有第二部分12的数量之和相等。如此，能够进一步减小晶体管100的面积。
本申请实施例还提供一种集成电路，集成电路包括上述任意一项实施例中的晶体管100。由于本申请实施例提供的晶体管面积较小，能避免占据集成电路过多的面积，使得集成电路布局更加紧凑，集成度更高，集成电路占据的面积更小。
可以在同一衬底上设置多个本申请实施例提供的晶体管100，多个晶体管100之间并联，如此，可以进一步驱动更大的输出电流。每个晶体管100的周围可以设置浅沟槽隔离(STI，Shallow Trench Isolation)或局部硅氧化隔离(LOCOS即Local Oxidation of Silicon)，如此，避免多个晶体管100之间产生漏电、闩锁效应等问题。
本申请实施例中，为进一步阐明采用本申请实施例的晶体管100具有更小的面积，以下示例性的说明，本领域技术人员可以理解的是，不同的工艺条件下，相邻的接触孔40之间的最小间距A、接触孔40的最小宽度B以及接触孔40与网状栅极10之间的最小间距C为不同的数值；相同的工艺条件下，相邻的接触孔40之间的最小间距A、接触孔40的最小宽度B以及接触孔40与网 状栅极10之间的最小间距C为相同的数值。本申请实施例中列举的相邻的接触孔40之间的最小间距A、接触孔40的最小宽度B以及接触孔40与网状栅极10之间的最小间距C仅用于示例，不对本申请实施例提供的晶体管100进行限定，下面对各个实施例进行具体说明。
示例性的，以现有技术的第一个实施例中的N型金属氧化物半导体场效应晶体管1001为例，假设，根据工艺条件要求，相邻的两个接触孔104之间的最小间距为0.26μm，接触孔104的最小宽度为0.24μm，接触孔104与条状栅极101之间的最小间距为0.8。可以理解的是，由于现有技术的第一个实施例、现有技术的第二个实施例、本申请的第一个实施例、本申请的第二个实施例采用相同的工艺，因此，上述实施例中的相邻的两个接触孔之间的最小间距，接触孔的最小宽度，接触孔与条状栅极或网状栅极之间的最小间距均相同。
现有技术的第一个实施例中的N型金属氧化物半导体场效应晶体管1001的宽为46μm，长为0.5μm，条状栅极101的数量为180个，为便于表述，定义条状栅极101的长度方向为第一方向，条状栅极101的宽度方向为第二方向，在以下计算式中，省略了数值的单位，现有技术中180个条状栅极101沿第一方向间隔分布。
现有技术的第一个实施例，具体说明如下：
请参见图1，在第一方向上，漏极103内和源极102内均设置一个接触孔104，则现有技术的第一个实施例形成的N型金属氧化物半导体场效应晶体管1001的面积为：4.68*180/2*46＝19375.2μm 2，假设将现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001的面积作为参考标准，即将现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001的面积记为100％。
现有技术的第二个实施例，具体说明如下：
请参见图2，现有技术的第二个实施例是在现有技术第一个实施例的基础上增加了一个漏极103内的接触孔104，也就是说，现有技术的第二个实施例与现有技术第一个实施例的区别为：现有技术的第二个实施例中，N型金属氧 化物半导体场效应晶体管1002的漏极103内的接触孔104的数量为两个，两个漏极103的接触孔104沿第一方向间隔分布，则现有技术的第二个实施例形成的N型金属氧化物半导体场效应晶体管1002的面积为：5.18*180/2*46＝21445.2μm 2，现有技术的第二个实施例的N型金属氧化物半导体场效应晶体管1002的面积与现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001的面积的比值为110.68％。
本申请的第一个实施例，具体说明如下：
本申请的第一个实施例中，请参见图3和图4，网状栅极10包括沿第一方向间隔分布的330个第一部分11，以及沿第二方向间隔分布的4个第二部分12，330个第一部分11和4个第二部分12交错分布，相邻的源极20的面积与漏极30的面积相等，即源极20与漏极30为对称结构，由于4*(0.5*330+2.3*4331)+13.7*330＝180*46，因此，本申请的第一个实施例的网状栅极10的宽度与现有技术的第一个实施例的条状栅极101的宽度相等，本申请的第一个实施例的网状栅极10的长度与现有技术的第一个实施例的条状栅极101的长度相等。公式
Figure PCTCN2021086023-appb-000001
其中：I ds是指导通时漏极和源极之间的电流，μ n是指电子的迁移率，C ox是指沟道的电容，W是指栅极的宽度，L是指栅极的长度，V gs是指栅源电压，V th是指阈值电压，V gs-V th也被称之为驱动电压或有效电压。根据上述计算公式可知，由于本申请的第一个实施例的N型金属氧化物半导体场效应晶体管100’与现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001相比，由于两者的栅极的宽度、长度均相等，而，在相同的衬底、相同的工艺条件下，上述两个晶体管的电子的迁移率μ n、沟道的电容C ox、栅源电压V gs，阈值电压V th相同，也就是说，本申请的第一个实施例的N型金属氧化物半导体场效应晶体管100’与现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001为等效晶体管。本申请的第一个实施例的N型金属氧化物半导体场效应晶体管100’的面积为：(2.34*331+0.5*330)*13.7＝12871.7μm 2，本申请的第一个实施例的N型金属氧 化物半导体场效应晶体管100’的面积与现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001的面积的比值为66.4％。
本申请的第二个实施例，具体说明如下：
本申请的第二个实施例中，请参见图5和图6，网状栅极10包括沿第一方向间隔分布的191个第一部分11、以及沿第二方向间隔分布的8个第二部分12，191个第一部分11和8个第二部分12交错分布，相邻的源极20的面积与漏极30的面积不相等，即源极20与漏极30为非对称结构。
由于8*(2.34*0.5*191+1.84(1+0.5*191)+0.5*191)+22.56*191＝180*46，因此，本申请的第二个实施例的网状栅极10的宽度与现有技术的第一个实施例的条状栅极101的宽度相等，本申请的第二个实施例的网状栅极10的长度与现有技术的第一个实施例的条状栅极101的长度相等，也就是说，本申请的第二个实施例的N型金属氧化物半导体场效应晶体管100”与现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001也为等效晶体管。本申请的第二个实施例的N型金属氧化物半导体场效应晶体管100”的面积为：(2.34*331+0.5*330)*13.7＝12871.7μm 2，本申请的第二个实施例的N型金属氧化物半导体场效应晶体管100”的面积与现有技术的第一个实施例的N型金属氧化物半导体场效应晶体管1001的面积的比值为57.6％。
为更直观的获取上述四个实施例中的N型金属氧化物半导体场效应晶体管的面积之间的关系，请参见表1：
表1
实施例名称 面积(μm 2) 百分比
现有技术的第一个实施例 19375.2 100％
现有技术的第二个实施例 21445.2 110.68％
本申请的第一个实施例 12871.7 66.4％
本申请的第二个实施例 11160.21 57.6％
由上述实施例的陈述以及表1可知，在不影响电学特性的情况下，采用本 申请实施例的晶体管100，能够有效减小晶体管的面积。
本申请实施例提供的晶体管100不仅可以用于低压差线性稳压器(LDO，Low Dropout Regulator)，还可以用于直流电流(电压)到直流电流(电压)的转换器(DCDC，Direct current to direct current)，还可以用于其他需要驱动较大输出电流的电子器件或集成电路。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不仅限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种晶体管，包括：
    衬底；
    网状栅极，位于所述衬底上，所述网状栅极包括沿第一方向间隔分布的第一部分和沿第二方向间隔分布的第二部分，多个所述第一部分和多个所述第二部分交错分布将所述衬底分隔成多个分隔区域，其中，第一方向与第二方向垂直；
    源极；以及
    漏极，所述源极和所述漏极沿第一方向交替分布于所述分隔区域中，且所述源极和所述漏极沿第二方向交替分布于所述分隔区域中。
  2. 根据权利要求1所述的晶体管，相邻的所述源极的面积与所述漏极的面积不相等。
  3. 根据权利要求1或2所述的晶体管，所述晶体管包括位于所述分隔区域内的接触孔，至少一个所述分隔区域内的所述接触孔的数量为多个。
  4. 根据权利要求3所述的晶体管，所述晶体管为N型金属氧化物半导体场效应晶体管，所述漏极的总面积大于所述源极的总面积。
  5. 根据权利要求4所述的晶体管，至少一个所述漏极内的所述接触孔的数量为多个，所述漏极内的多个所述接触孔沿第一方向和第二方向分布。
  6. 根据权利要求4所述的晶体管，所述漏极内的所述接触孔的总数量大于所述源极内的所述接触孔的总数量。
  7. 根据权利要求3所述的晶体管，所述晶体管为P型金属氧化物半导体场效应晶体管，所述源极的总面积大于所述漏极的总面积。
  8. 根据权利要求7所述的晶体管，至少一个所述源极内的所述接触孔的数量为多个，所述源极内的多个所述接触孔沿第一方向和第二方向分布。
  9. 根据权利要求7所述的晶体管，所述源极内的所述接触孔的总数量 大于所述漏极内的所述接触孔的总数量。
  10. 根据权利要求1或2所述的晶体管，所述第一部分的总数量与所述第二部分的总数量不相等。
  11. 一种集成电路，包括：如权利要求1至10中任一项所述的晶体管。
PCT/CN2021/086023 2020-05-21 2021-04-08 晶体管以及集成电路 WO2021232989A1 (zh)

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CN116344530A (zh) * 2021-12-24 2023-06-27 长鑫存储技术有限公司 晶体管单元及其阵列、集成电路
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