WO2021218779A1 - 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器电路及其驱动方法、栅极驱动电路、显示装置 Download PDF

Info

Publication number
WO2021218779A1
WO2021218779A1 PCT/CN2021/089081 CN2021089081W WO2021218779A1 WO 2021218779 A1 WO2021218779 A1 WO 2021218779A1 CN 2021089081 W CN2021089081 W CN 2021089081W WO 2021218779 A1 WO2021218779 A1 WO 2021218779A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
coupled
terminal
voltage
circuit
Prior art date
Application number
PCT/CN2021/089081
Other languages
English (en)
French (fr)
Inventor
商广良
卢江楠
张洁
刘利宾
史世明
王大巍
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21796531.8A priority Critical patent/EP4068263A4/en
Priority to US17/779,845 priority patent/US12002407B2/en
Priority to KR1020227017500A priority patent/KR20230002265A/ko
Priority to JP2022540526A priority patent/JP2023522803A/ja
Publication of WO2021218779A1 publication Critical patent/WO2021218779A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register circuit and a driving method thereof, a gate driving circuit, and a display device.
  • OLED Organic Light Emitting Diode
  • a shift register circuit in the first aspect, includes a de-noising control sub-circuit and a de-noising sub-circuit.
  • the denoising control sub-circuit is coupled to the first voltage terminal, the first clock signal terminal, the second clock signal terminal and the first denoising control node.
  • the denoising control sub-circuit is configured to generate an alternating voltage signal according to the voltage of the first voltage terminal and the signal of the second clock signal terminal in response to the signal of the first clock signal terminal, and output the alternating voltage signal after rectification
  • the voltage of the first denoising control node is maintained at a voltage that enables the denoising sub-circuit to turn on.
  • the denoising sub-circuit is coupled to the first denoising control node and the scan signal output terminal.
  • the denoising sub-circuit is configured to denoise the scan signal output terminal in response to the voltage of the first denoising control node being a voltage for turning on the denoising sub-circuit.
  • the denoising sub-circuit includes a first turn-on control sub-circuit and a second turn-on control sub-circuit.
  • the first turn-on control sub-circuit is coupled to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and the second denoising control node, and is configured to respond periodically to the first clock signal terminal Signal, outputting the voltage of the first voltage terminal to the second denoising control node, and pulling the voltage of the second denoising control node according to the signal of the second clock signal terminal, so that the second denoising control node provides an alternating voltage signal;
  • the second turn-on control sub-circuit is coupled to the first denoising control node and the second denoising control node, and is configured to respond to the alternating voltage signal provided by the second denoising control node to rectify the alternating voltage signal and output it to the first
  • a denoising control node keeps the voltage of the first denoising control node at the voltage that enables the denoising sub-circuit to
  • the first turn-on control sub-circuit includes a first transistor and a first capacitor; and/or, the second turn-on control sub-circuit includes a second transistor and a second capacitor.
  • the control electrode of the first transistor is coupled to the first clock signal terminal, the first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the second denoising control node.
  • the first terminal of the first capacitor is coupled to the second clock signal terminal, and the second terminal of the first capacitor is coupled to the second denoising control node.
  • the control electrode of the second transistor is coupled to the second denoising control node, the first electrode of the second transistor is coupled to the first denoising control node, and the second electrode of the second transistor is coupled to the second denoising control node.
  • the first terminal of the second capacitor is coupled to the first signal terminal, and the second terminal of the second capacitor is coupled to the first denoising control node.
  • the denoising control sub-circuit is further coupled to the cascaded signal output terminal, and is further configured to transmit the signal of the second signal terminal to the first denoising control node in response to the voltage of the cascaded signal output terminal, To control the denoising sub-circuit to close.
  • the shift register circuit further includes a third transistor and a fourth transistor.
  • the control electrode of the third transistor is coupled to the cascade signal output terminal, the first electrode of the third transistor is coupled to the control signal terminal, and the second electrode of the third transistor is coupled to the second denoising control node.
  • the control electrode of the fourth transistor is coupled to the cascade signal output terminal, the first electrode of the fourth transistor is coupled to the control signal terminal, and the second electrode of the fourth transistor is coupled to the first denoising control node.
  • the first turn-on control sub-circuit further includes a fifth transistor.
  • the first terminal of the first capacitor is coupled to the second clock signal terminal through the fifth transistor.
  • the control electrode of the fifth transistor is coupled to the scan signal output end, the first electrode of the fifth transistor is coupled to the second clock signal end, and the second electrode of the fifth transistor is coupled to the first end of the first capacitor.
  • the first signal terminal is a first voltage terminal or a first clock signal terminal.
  • the denoising sub-circuit includes a sixth transistor.
  • the control electrode of the sixth transistor is coupled to the first denoising control node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the scan signal output terminal.
  • the shift register circuit further includes an input sub-circuit and an output sub-circuit.
  • the input sub-circuit is coupled to the cascaded signal output terminal and the output sub-circuit, and is configured to control the voltage of the cascaded signal output terminal, and is also configured to transmit a turn-on signal to the output sub-circuit.
  • the output sub-circuit is also coupled to the second voltage terminal or the fifth clock signal terminal, and the output sub-circuit is also coupled to the scan signal output terminal.
  • the output sub-circuit is configured to transmit the signal of the second voltage terminal or the fifth clock signal terminal to the scan signal output terminal in response to the turn-on signal transmitted by the input sub-circuit.
  • the input sub-circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third capacitor, an eleventh transistor, a fourth capacitor, a twelfth transistor, a thirteenth transistor, and a third capacitor. Fourteen transistors.
  • the control electrode of the seventh transistor is coupled to the third clock signal terminal, the first electrode of the seventh transistor is coupled to the input signal terminal, and the second electrode of the seventh transistor is coupled to the first node.
  • the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the third clock signal terminal, and the second electrode of the eighth transistor is coupled to the second node.
  • the control electrode of the ninth transistor is coupled to the third clock signal terminal, the first electrode of the ninth transistor is coupled to the first voltage terminal, and the second electrode of the ninth transistor is coupled to the second node.
  • the control electrode of the tenth transistor is coupled to the second node, the first electrode of the tenth transistor is coupled to the second voltage terminal, and the second electrode of the tenth transistor is coupled to the cascade signal output terminal.
  • the first terminal of the third capacitor is coupled to the second node, and the second terminal of the third capacitor is coupled to the first electrode and the second voltage terminal of the tenth transistor.
  • the control electrode of the eleventh transistor is coupled to the third node, the first electrode of the eleventh transistor is coupled to the fourth clock signal terminal, and the second electrode of the eleventh transistor is coupled to the cascade signal output terminal.
  • the first end of the fourth capacitor is coupled to the third node, and the second end of the fourth capacitor is coupled to the second electrode of the eleventh transistor and the cascade signal output end.
  • the control electrode of the twelfth transistor is coupled to the first voltage terminal, the first electrode of the twelfth transistor is coupled to the third node, and the second electrode of the twelfth transistor is coupled to the first node.
  • the control electrode of the thirteenth transistor is coupled to the fourth clock signal terminal, the first electrode of the thirteenth transistor is coupled to the first node, and the second electrode of the thirteenth transistor is coupled to the fourth node.
  • the control electrode of the fourteenth transistor is coupled to the second node, the first electrode of the fourteenth transistor is coupled to the second voltage terminal, and the second electrode of the fourteenth transistor is coupled to the fourth node.
  • the output sub-circuit includes a fifteenth transistor.
  • the control electrode of the fifteenth transistor is coupled to the cascade signal output terminal or the third node, the first electrode of the fifteenth transistor is coupled to the second voltage terminal or the fifth clock signal terminal, and the second electrode of the fifteenth transistor Coupled with the scan signal output terminal.
  • the second signal terminal is a second voltage terminal, or the second signal terminal is coupled to the second node.
  • the third clock signal terminal and the first clock signal terminal are the same signal terminal, and the fourth clock signal terminal and the second clock signal terminal are the same signal terminal.
  • a gate driving circuit in the second aspect, includes a plurality of cascaded shift register circuits.
  • the shift register circuit is the shift register circuit described in any of the above embodiments.
  • a display device in a third aspect, includes a plurality of gate lines, and the gate driving circuit as described in the above-mentioned second aspect.
  • Each shift register circuit in the gate driving circuit is coupled to at least one gate line.
  • the scan signal output terminal of each shift register circuit in the gate driving circuit is coupled to at least one gate line.
  • the plurality of gate lines includes a plurality of first gate lines and a plurality of second gate lines; the scan signal output terminal of each shift register circuit in the gate driving circuit is connected to at least one first gate line.
  • the cascade signal output terminal of each shift register circuit in the gate driving circuit is coupled to at least one second gate line.
  • a driving method of the shift register circuit as described in any of the above embodiments includes: in the holding phase, the denoising control sub-circuit of the shift register circuit responds to the signal of the first clock signal terminal, generates an alternating voltage signal according to the voltage of the first voltage terminal and the signal of the second clock signal terminal, and combines The generated alternating voltage signal is rectified and output to the first denoising control node, so that the voltage of the first denoising control node is maintained at a voltage that enables the denoising sub-circuit to turn on.
  • the denoising sub-circuit denoises the scan signal output terminal in response to the voltage of the first denoising control node being a voltage for turning on the denoising sub-circuit.
  • the driving method further includes: in the case that the shift register circuit further includes an input sub-circuit and an output sub-circuit, in the input phase, the input sub-circuit controls the cascade in response to the signal of the third clock signal terminal.
  • the voltage at the signal output terminal is the first control voltage, so that the denoising control sub-circuit turns on the de-noising sub-circuit; and the turn-on signal is transmitted to the output sub-circuit.
  • the input sub-circuit controls the voltage at the output terminal of the cascade signal to the second control voltage, so that the de-noising control sub-circuit turns off the de-noising sub-circuit; and continues to transmit the turn-on signal to the output sub-circuit.
  • FIG. 1A is a structural diagram of a display panel provided by an embodiment of the disclosure.
  • FIG. 1B is a diagram of a gate driving structure of a display panel provided by an embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit in the related art
  • Fig. 3 is a partial structure diagram of a shift register circuit in the related art
  • Figure 5 is a graph of output noise of a shift register circuit in the related art
  • FIG. 6 is a structural diagram of a shift register circuit provided by an embodiment of the disclosure.
  • FIG. 7 is a structural diagram of yet another shift register circuit provided by an embodiment of the disclosure.
  • FIG. 8 is a structural diagram of another shift register circuit provided by an embodiment of the disclosure.
  • FIG. 9 is a structural diagram of another shift register circuit provided by an embodiment of the disclosure.
  • FIG. 10 is a structural diagram of another shift register circuit provided by an embodiment of the disclosure.
  • FIG. 11 is a structural diagram of another shift register circuit provided by an embodiment of the disclosure.
  • FIG. 12 is a driving timing diagram of a shift register circuit provided by an embodiment of the disclosure.
  • FIG. 13 is a structural diagram of another shift register circuit provided by an embodiment of the disclosure.
  • FIG. 14 is a structural diagram of another shift register circuit provided by an embodiment of the disclosure.
  • FIG. 15 is a driving timing diagram of a shift register circuit provided by an embodiment of the disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the display device refers to a product with an image display function.
  • the display device may be: a TV, a mobile phone, a computer, a notebook computer, a tablet computer, a personal digital assistant (personal digital assistant).
  • the display device includes a frame, a display panel set in the frame, a circuit board, and a display driver integrated circuit (integrated circuit, referred to as IC) and other electronic accessories.
  • IC display driver integrated circuit
  • the above-mentioned display panels may be: Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display panels, Quantum Dot Light Emitting Diodes (QLED) display panels, micro LED (including: miniLED or microLED) display panels, etc., are not specifically limited in the present disclosure.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • micro LED including: miniLED or microLED
  • the above-mentioned display panel 100 includes a display area AA (Active Area) and a peripheral area BB located on at least one side of the display area AA.
  • the peripheral area BB surrounds the display area AA for illustration.
  • the above-mentioned display panel 100 includes multiple-color sub-pixels P arranged in the display area AA, and the multiple-color sub-pixels at least include first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels ,
  • the first color, the second color, and the third color may be three primary colors (for example, red, green, and blue).
  • the above-mentioned multiple sub-pixels P in the present disclosure are described by taking a matrix arrangement as an example.
  • the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row; the sub-pixels P arranged in a row along the vertical direction Y are called sub-pixels in the same column.
  • each sub-pixel P is provided with a pixel circuit (also referred to as a pixel driving circuit) S, and the pixel circuit S includes a plurality of transistors (in FIG. 1B, it is illustrated as including two transistors).
  • the pixel circuit S is coupled to the light emitting device L, and is used to drive the light emitting device L to emit light.
  • the pixel circuits S located in the same row are connected (ie, coupled) to the same gate line GL (Gate Line), and the pixel circuits S located in the same column are connected to the same data line DL (Data Line).
  • the arrangement of the plurality of sub-pixels P depends on the arrangement of the pixel circuits S in the plurality of sub-pixels P, and has nothing to do with the position of the light-emitting device L in the sub-pixels P.
  • the transistors included in the pixel circuit S may all be N-type transistors or P-type transistors, and may also include N-type and P-type transistors, which can be designed according to actual needs.
  • the pixel circuit S may include at least one of a low temperature polysilicon (LTPS) transistor and an oxide (Oxide) transistor.
  • LTPS low temperature polysilicon
  • Oxide oxide
  • the transistors in the pixel circuit S may be all LTPS transistors, or both It is an oxide transistor, and it can also include an LTPS transistor and an oxide transistor at the same time.
  • the voltage for controlling the brightness of the sub-pixel may change with time due to the leakage of the transistor in the pixel circuit S
  • the data still needs to be refreshed when displaying a static image.
  • reducing the refresh frequency is a more effective method, but while reducing the refresh rate, it is necessary to maintain the display quality, which requires reducing the leakage speed of the transistors in the pixel circuit S.
  • oxide semiconductors have ultra-low leakage characteristics
  • the transistors in the pixel circuit S can be configured as oxide transistors, so that the display panel can reduce the leakage of the transistors in the pixel circuit S during the process of displaying images.
  • Low-temperature polysilicon has high carrier mobility.
  • the use of LTPS transistors in the pixel circuit S can greatly improve the response speed of the transistors, thereby ensuring the charging speed of the sub-pixels, and the LTPS transistors are automatically aligned by ion implantation to form source and drain electrodes. Therefore, the parasitic capacitance generated between the gate and the source and drain is much smaller than that of amorphous silicon transistors, which greatly reduces the capacitive coupling effect.
  • the pixel circuit S includes two types of transistors, an LTPS transistor and an oxide transistor.
  • the pixel circuit S includes a P-type LTPS transistor and an N-type oxide transistor.
  • the display device may further include: a gate driving circuit 01 and a data driving circuit 02.
  • the gate driving circuit 01 may be arranged in the peripheral area BB of the display panel 100; for example, it may be arranged on the side of the peripheral area BB located at one end of the gate line GL (for example, the left side of the peripheral area BB in FIG. 1A).
  • the data driving circuit 02 may be disposed in the peripheral area BB of the display panel 100; for example, the data driving circuit 02 may be disposed in the peripheral area BB on the side of one end of the data line DL (for example, the peripheral area BB in FIG. 1A The lower side), to drive the pixel circuit S in the display panel 100, and then drive the light-emitting device L to emit light, so that the corresponding sub-pixel P presents the color to be displayed.
  • the above-mentioned gate driving circuit 01 may be a gate driving IC, and the gate driving IC is bound to an array substrate (also referred to as a driving backplane) in the display panel 100.
  • the gate driver circuit 01 may be a GOA (Gate Driver on Array, gate driver integrated on an array substrate) circuit, which is included in the display panel 100.
  • the gate driver circuit 01 is directly integrated in the array substrate of the display panel 100.
  • arranging the gate driving circuit 01 in the array substrate is compared to binding with the array substrate in the form of a gate driving IC.
  • the manufacturing cost of the display panel 100 can be reduced; on the other hand, the display can be narrowed.
  • the width of the frame of the device The following embodiments are all described by taking the gate driving circuit 01 as a GOA circuit as an example.
  • gate driving circuit 01 is provided on a single side of the peripheral area BB of the display panel 100, and the gate lines GL are driven row by row from the single side, that is, the single side driving is taken as an example.
  • gate driving circuits may be respectively provided on the two sides along the extension direction of the gate line GL in the peripheral area BB of the display panel 100, and the two gate driving circuits are simultaneously arranged row by row from both sides.
  • Each gate line GL is driven, that is, double-sided driving.
  • gate driving circuits may be respectively provided on two sides along the extension direction of the gate line GL in the peripheral area BB of the display panel 100, and the two gate driving circuits alternately from both sides,
  • the gate lines GL are driven row by row, for example, one gate driving circuit drives odd-numbered rows of gate lines GL, and another gate driving circuit drives even-numbered rows of gate lines GL, that is, cross-driving.
  • the following embodiments of the present disclosure are all described by taking single-side driving as an example.
  • the gate driving circuit 01 includes N-stage cascaded shift register circuits (RS1, RS2...RS(N)), and the above-mentioned N-stage cascaded shift register circuit
  • the bit register circuits (RS1, RS2...RS(N)) are respectively connected with N gate lines (G1, G2...G(N)) in a one-to-one correspondence, where N is a positive integer.
  • the circuit structures of the above-mentioned shift register circuits (RS1, RS2...RS(N)) at all levels can be the same, and the shift register circuits (RS1, RS2...RS(N)) at all levels are connected in sequence, In order to make the shift register circuits of each stage output the turn-on voltage (also called the effective level in the scan signal, such as high level) in sequence, so as to realize the progressive scan of the multiple gate lines in the display panel, so that the gate lines The coupled rows of sub-pixels are charged.
  • the turn-on voltage also called the effective level in the scan signal, such as high level
  • the shift register circuit RS(i) includes a scan signal output terminal Output (Output is abbreviated as Oput in the following and the drawings), so that the scan signal output terminal Oput outputs a gate scan signal to the gate line GL connected to it through the scan signal output terminal Oput.
  • the shift register circuit RS(i) of each stage of the gate drive circuit 01 is also provided with a signal input terminal Input (the drawings and the following are abbreviated as Iput) to provide the starting point for the shift register circuit RS(i) of each stage. Signal.
  • each stage of the shift register circuit RS(i) of the gate drive circuit 01 also includes a cascaded signal output terminal GP, which can be connected to the shift register circuit of the lower stage to the shift register of the lower stage.
  • the circuit transmits the cascade signal as the start signal of the shift register circuit of the lower stage.
  • each level of shift register circuit RS(i) in the gate drive circuit 01 can be:
  • the signal input terminal Iput of the first stage shift register circuit RS1 is connected to the start signal terminal STV; except for the first stage shift register circuit RS1, the signal input terminal Iput of any other stage shift register circuit RS(i) It is connected to the cascade signal output terminal GP of the shift register circuit RS(i-1) at the previous stage.
  • the scanning signal output terminal Oput of the shift register circuit RS(i) of each stage is coupled to at least one gate line GL.
  • the cascade signal output terminal GP may also be connected to the P in the pixel circuit S through a gate line.
  • the type transistor is connected to transmit a signal to the P-type transistor (the signal may be referred to as a control signal) to control the P-type transistor to turn on or off.
  • connection relationship between the various levels of shift register circuits (RS1, RS2...RS(N)) in the gate drive circuit 01 and the multiple gate lines GL can be:
  • the pixel circuits in the same row may be coupled to at least two gate lines, and the at least two gate lines include: at least one first gate line and at least one second gate line.
  • the scan signal output terminal Oput of each shift register circuit in the gate drive circuit is coupled to at least one first gate line
  • the cascade signal output terminal GP of each shift register circuit in the gate drive circuit is coupled to At least one second gate line is coupled.
  • the gate line coupled to the scan signal output terminal Oput and the gate line connected to the cascade signal output terminal GP are not the same, for the convenience of distinction, the gate line coupled to the scan signal output terminal Oput is called the first gate.
  • the gate line coupled to the cascade signal output terminal GP is called the second gate line.
  • the transistors D3 and D4 are N-type transistors, such as N-type oxide transistors
  • the transistors D2 and D7 are P-type transistors, such as P-type LTPS transistors.
  • the transistors D3 and D4 can be connected to the scan signal output terminal Oput(i) of the current stage and the scan signal output terminal Oput of the previous stage through the two first gate lines.
  • the transistors D2 and D7 can be connected to the cascade signal output terminal GP(i) of the current stage and the cascade signal output terminal GP(i-1) of the previous stage through the two second gate lines respectively Coupling.
  • the shift register circuit can respectively control the oxide transistor and the LTPS transistor in the LTPO type pixel circuit, so that the response time of the control process is greatly improved.
  • the first-stage shift register circuit first outputs the turn-on voltage (also called effective voltage or operating voltage) in the scan signal to the gate line to which it is coupled. ), so that a row of sub-pixels coupled to the gate line is turned on.
  • This stage is called the output stage; after that, the shift register circuit of this stage will output the off voltage in the scan signal (also It is called a non-operating voltage) to ensure that the sub-pixels coupled to the gate line are turned off, that is, the holding phase is entered.
  • the scan signal output terminal coupled to the gate line in the shift register circuit has relatively high noise, which may cause the image displayed by the display device to be unstable.
  • FIG. 3 shows a partial circuit structure of the shift register circuit RS' in some related technologies
  • FIG. 4 shows a partial driving timing of the shift register circuit RS'.
  • 30' is a de-noising sub-circuit
  • the de-noising sub-circuit 30' includes a transistor T03.
  • the potential of the cascade signal output terminal GP is low, the transistor T04 is turned on, and the scanning signal output terminal Oput outputs a high level, that is, the scanning signal is output.
  • the transistor T02 is turned on, and the potential of the node PD-ox' is high, so that the transistor T03 in the denoising sub-circuit 30' is turned off.
  • the potential of the clock signal terminal CK1 is low, the transistor T01 is turned on, and the potential of the node PD-ox' is the low potential VSS+
  • the potential of the clock signal terminal CK1 is high, the transistor T01 is turned off, and because the potential of the cascade signal output terminal GP is high, the transistor T02 is also turned off, so the node PD-ox'
  • the potential of the clock signal terminal CB1 becomes a low potential. Due to the coupling effect of the capacitor C01, the potential of the node PD_ox' will be further pulled down, so that the transistor T03 in the denoising sub-circuit 30' further Turning on, the potential of the scanning signal output terminal Oput becomes a low potential, realizing a further reset of the scanning signal output terminal Oput.
  • the threshold voltage V th of the PMOS transistor is generally negative. Therefore, for the transistor T01, its The gate-source voltage difference V gs > V th , and because the PMOS transistor is turned on when V gs ⁇ V th , the transistor T01 is turned off at this time.
  • the transistors T02 and T04 are also turned off, so the potentials of the node PD-ox' and the output terminal Oput are in a floating state; the potential of the clock signal terminal CB1 is high Due to the coupling effect of the capacitor C01, the potential of the node PD_ox' will be slightly pulled up, so that the transistor T03 in the denoising sub-circuit 30' is turned off, and the scanning signal output terminal Oput cannot be denoised.
  • the shift register RS includes: a de-noising control sub-circuit 20 and a de-noising sub-circuit 30.
  • the denoising control sub-circuit 20 is coupled to the first voltage terminal VSS, the first clock signal terminal CK1, the second clock signal terminal CB1 and the first denoising control node PD-ox.
  • the denoising control sub-circuit 20 is configured to rectify the charge of the first voltage terminal VSS to the first denoising control node PD-ox under the control of the signal of the first clock signal terminal CK1, so that it can be adjusted (pulled up or Pull down) the voltage of the first denoising control node PD-ox, so that the voltage of the first denoising control node PD-ox is maintained at the voltage at which the denoising sub-circuit 30 is turned on.
  • the denoising control sub-circuit 20 is configured to generate an alternating voltage signal (or in other words, according to the voltage of the first voltage terminal VSS and the signal of the second clock signal terminal CB1 Is an oscillating signal), and the generated alternating voltage signal is rectified and output to the first denoising control node PD-ox, so that the voltage of the first denoising control node PD-ox is maintained at the level that makes the denoising sub-circuit 30 turn on
  • the voltage for example, causes the voltage of the first denoising control node PD-ox to gradually change (pull up or down gradually), and finally, for example, may reach a stable state.
  • the alternating voltage signal refers to a signal whose voltage magnitude periodically changes.
  • the alternating voltage signal may be a signal with alternating high and low voltages, for example, a square wave signal.
  • the duration of the high voltage and the duration of the low voltage within a cycle may be the same or different.
  • the amplitude of the alternating voltage signal can remain unchanged, for example, the high voltage can be equal in multiple cycles, and the low voltage can also be equal.
  • Rectification refers to outputting an alternating voltage signal as a direct current voltage signal.
  • the DC voltage signal is defined in comparison with the alternating voltage signal, which may be a signal whose voltage does not change with time; it may also include a signal whose amplitude (voltage) gradually increases or decreases with time.
  • the signal for example, can finally reach a steady state (that is, the voltage does not change anymore).
  • a DC voltage signal may include multiple cycles, the voltage in each cycle remains the same, and the voltage of any cycle is higher than the voltage of the previous cycle, or the voltage of any cycle is higher than the voltage of the previous cycle. The value is low.
  • the “voltage that enables the denoising sub-circuit 30 to turn on” refers to a voltage that can make the de-noising sub-circuit 30 work, and the voltage specifically depends on the polarity of the transistor included in the de-noising sub-circuit 30. For example, if the transistor included in the denoising sub-circuit 30 is a P-type, the voltage is a low-level voltage; if the transistor included in the de-noising sub-circuit 30 is an N-type, the voltage is a high-level voltage .
  • the denoising sub-circuit 30 is coupled to the first denoising control node PD-ox and the scanning signal output terminal Oput.
  • the denoising sub-circuit 30 is configured to denoise the scanning signal output terminal Oput in response to the voltage of the first denoising control node being a voltage for turning on the denoising sub-circuit.
  • the denoising control sub-circuit 20 can be controlled by the signal of the first clock signal terminal CK1 according to the received signal (for example, it may include the signal of the first voltage terminal VSS, the second clock signal The signal at the terminal CB1, etc.) regulates the voltage of the first denoising control node PD-ox, that is, the voltage of the first denoising control node PD-ox is stabilized at the voltage that makes the denoising sub-circuit 30 turn on (high voltage Level or low level).
  • the denoising control sub-circuit 20 outputs the adjusted voltage to the de-noising sub-circuit 30, and controls the de-noising sub-circuit 30 to remain continuously turned on, so that the de-noising sub-circuit 30 continues to output a stable non-operating voltage, which realizes the scanning
  • the signal output terminal Oput continuously de-noises, thereby improving the stability of the screen display.
  • the aforementioned denoising control sub-circuit 20 includes an opening control unit 21 and a closing control unit 22.
  • the turn-on control unit 21 is coupled to the first voltage terminal VSS, the first clock signal terminal CK1, the second clock signal terminal CB1, and the first denoising control node PD-ox.
  • the turn-on control unit 21 is configured to, under the control of the signal of the first clock signal terminal CK1, rectify the charge of the first voltage terminal VSS to the first denoising control node PD-ox, so as to pull up or pull down the first denoising control node PD-ox.
  • the voltage of the denoising control node PD-ox keeps the voltage of the first denoising control node PD-ox at the voltage at which the denoising sub-circuit 30 is turned on.
  • the turn-on control unit 21 is configured to, in response to the signal of the first clock signal terminal CK1, generate an alternating voltage signal according to the voltage of the first voltage terminal VSS and the signal of the second clock signal terminal CB1, and combine the generated The alternating voltage signal is rectified and output to the first denoising control node PD-ox, so that the voltage of the first denoising control node PD-ox is maintained at a voltage that enables the denoising sub-circuit 30 to turn on.
  • the turn-on control unit 21 may also be coupled to the second denoising control node PD-ox-i, and the generated alternating voltage signal is the signal of the second denoising control node PD-ox-i.
  • the first voltage terminal VSS is configured to transmit a DC low-level signal.
  • the first voltage terminal VSS is grounded.
  • the turn-on control unit 21 of the denoising control sub-circuit 20 includes: a first turn-on control sub-circuit 211 and a second turn-on control sub-circuit 212.
  • the first turn-on control sub-circuit 211 is coupled to the first clock signal terminal CK1, the second clock signal terminal CB1, the first voltage terminal VSS, and the second denoising control node PD-ox-i, and is configured to periodically In response to the signal of the first clock signal terminal CK1, the voltage of the first voltage terminal VSS is output to the second denoising control node PD-ox-i, and according to the signal of the second clock signal terminal CB1, the second denoising control is pulled The voltage of the node PD-ox-i makes the second denoising control node PD-ox-i provide an alternating voltage signal.
  • the first turn-on control sub-circuit 211 includes: a first transistor T1 and a first capacitor C1.
  • control electrode of the first transistor T1 is coupled to the first clock signal terminal CK1
  • first electrode of the first transistor T1 is coupled to the first voltage terminal VSS
  • second electrode of the first transistor T1 is coupled to the second denoising control The node CB1 is coupled.
  • the first terminal of the first capacitor C1 is coupled to the second clock signal terminal CB1, and the second terminal of the first capacitor C1 is coupled to the second denoising control node PD-ox-i.
  • the voltage of the first voltage terminal VSS may be transmitted to the second denoising control node PD-ox-i through the first transistor T1;
  • the signal of the first clock signal terminal CK1 controls the first transistor T1 to be turned off
  • the voltage of the first voltage terminal VSS cannot be transmitted to the second denoising control node PD-ox-i, but in response to the signal of the second clock signal terminal CB1 Signal, and through the coupling effect of the first capacitor C1
  • the second clock signal terminal CB1 outputs a low level.
  • the second clock signal terminal CB1 When the signal of the first clock signal terminal CK1 controls the first transistor T1 to be turned off, the second clock signal terminal CB1 outputs a high level to turn the second denoising control node PD- The voltage of ox-i is pulled up. Since the signal of the first clock signal terminal CK1 controls the first transistor T1 to be turned on and off periodically, the second clock signal terminal CB1 periodically pulls the voltage of the second denoising control node PD-ox-i, and the two work together , So that the voltage of the second denoising control node PD-ox-i is an alternating voltage.
  • the second turn-on control sub-circuit 212 is coupled to the first denoising control node PD-ox and the second denoising control node PD-ox-i, and rectifies the alternating voltage signal and outputs it to the first denoising control Node, the voltage of the first denoising control node PD-ox is maintained at the voltage at which the denoising sub-circuit 30 is turned on.
  • the second turn-on control sub-circuit 212 includes: a second transistor T2 and a second capacitor C2.
  • control electrode of the second transistor T2 is coupled to the second denoising control node PD-ox-i
  • first electrode of the second transistor T2 is coupled to the first denoising control node PD-ox
  • second transistor T2 The second pole is coupled to the second denoising control node PD-ox-i.
  • the first terminal of the second capacitor C2 is coupled to the first signal terminal ST, and the second terminal of the second capacitor C2 is coupled to the first denoising control node PD-ox.
  • the alternating voltage signal provided by the second denoising control node PD-ox-i can periodically turn on the second transistor T2, for example, when the alternating voltage signal is at a high level, the second transistor T2 is turned off. When the alternating voltage signal is at a low level, the second transistor T2 is turned on.
  • the second transistor T2 When the second transistor T2 is turned off, the charge on the second end of the first capacitor C1 cannot be transferred to the second end of the second capacitor C2 through the second transistor T2, and when the second transistor T2 is turned on, because the first capacitor The voltage of the second terminal of C1 is pulled down by the second clock signal terminal CB1, so that the amount of charge on the second terminal of the first capacitor C1 is less than the amount of charge on the second terminal of the second capacitor C2, then the second capacitor C2 The charge on the second terminal can be transferred to the second terminal of the first capacitor C1 through the second transistor T2.
  • the charge on the second end of the second capacitor C2 is continuously transferred to the second end of the first capacitor C1, so that the charge on the second end of the second capacitor C2 is gradually reduced, and finally stabilized.
  • the charge on the second terminal of the first capacitor C1 is equal to the voltage on the second terminal of the first capacitor C1 when the voltage of the second terminal of the first capacitor C1 is pulled down by the second clock signal terminal CB1, so that the charge on the second terminal of the first capacitor C1 is equal to that of the second capacitor C2
  • the voltage of the coupled first denoising control node PD-ox is stabilized at a fixed voltage, and the fixed voltage enables the denoising sub-circuit 30 to be continuously turned on.
  • the first denoising control node PD-ox, the second denoising control node PD-ox-i, and the cascade signal output terminal GP and
  • the first node n1, the second node n2, the third node n3, and the fourth node n4 mentioned below do not represent actual components, but represent the junction of related electrical connections in the circuit diagram, that is, these nodes It is a node equivalent to the junction of related electrical connections in the circuit diagram.
  • the above-mentioned first signal terminal (also referred to as a voltage stabilizing signal terminal) ST may be the first voltage terminal VSS or the first clock signal terminal CK1.
  • the first signal terminal ST is the first voltage terminal VSS
  • the first terminal of the second capacitor C2 is connected to the first voltage terminal VSS, so that the second capacitor C2 is the first denoising control node PD-ox
  • the first signal terminal ST is the first clock signal terminal CK1
  • the first terminal of the second capacitor C2 is connected to the first clock signal terminal CK1, except that the second capacitor C2 can stabilize the first denoising control
  • the second capacitor C2 can further adjust the voltage of the first denoising control node PD-ox when the voltage of the signal of the first clock signal terminal CK1 changes, so that the first denoising control node PD
  • the voltage of -ox quickly stabilizes at a potential capable of turning on the denoising sub-circuit 30, which is beneficial to improve the de-noising speed of the denoising sub-circuit 30.
  • the second capacitor C2 can further pull down the first denoising control node PD-ox.
  • the potential of is beneficial to improve the de-noising speed of the de-noising sub-circuit 30.
  • the first transistor T1, the first capacitor C1, the second transistor T2, and the second capacitor C2 included in the above-mentioned turn-on control unit 21 form a charge pump structure, and the voltage regulation effect of the charge pump structure is used to make the first denoising control node PD
  • the voltage of -ox is stabilized at a voltage capable of turning on the denoising sub-circuit 30, thereby ensuring that the denoising sub-circuit 30 is continuously turned on during the holding phase of the driving process of a row of gate lines, thereby continuously denoising the scanning signal output terminal Oput .
  • the closing control unit 22 of the denoising control sub-circuit 30 is connected to the cascade signal output terminal GP, the second signal terminal (also referred to as the control signal terminal) CN, the first denoising control node PD-ox, and The second denoising control node PD-ox-i is coupled.
  • the shutdown control unit 22 is configured to, in response to the voltage of the cascade signal output terminal GP, transmit the signal of the second signal terminal CN to the first denoising control node PD-ox to control the denoising sub-circuit 30 to turn off.
  • the shutdown control unit 22 includes a third transistor T3 and a fourth transistor T4.
  • control electrode of the third transistor T3 is coupled to the cascade signal output terminal GP
  • first electrode of the third transistor T3 is coupled to the second signal terminal CN
  • second electrode of the third transistor T3 is coupled to the second denoising control
  • the node PD-ox-i is coupled.
  • the control electrode of the fourth transistor T4 is coupled to the cascade signal output terminal GP, the first electrode of the fourth transistor T4 is coupled to the second signal terminal CN, and the second electrode of the fourth transistor T4 is coupled to the first denoising control node PD -ox coupling.
  • the above-mentioned second signal terminal CN may be the second voltage terminal VDD or the second node n2.
  • the second voltage terminal VDD is configured to transmit a DC high-level signal; for example, the voltage value of the DC high-level signal is greater than the voltage value of the DC low-level signal transmitted by the first voltage terminal VSS.
  • the second node n2 is a node in the input sub-circuit 10 that will be mentioned later. For example, the voltage of this node is high during the output phase of the driving process of a row of gate lines, and is low during the holding phase. Level.
  • the third transistor T3 and the fourth transistor T4 are turned on under the control of the voltage of the cascaded signal output terminal GP, and the first goes to
  • the voltages of the noise control node PD-ox and the second denoising control node PD-ox-i both become the voltage of the second voltage terminal VDD, that is, the high level, so that the denoising sub-circuit 30 remains closed during the output phase. Affect the output of the scan signal at the scan signal output terminal Oput.
  • the third transistor T3 and the fourth transistor T4 remain closed under the control of the voltage of the cascade signal output terminal GP, and the high level of the second signal terminal CN affects the first denoising control node PD-ox and
  • the voltage of the second denoising control node PD-ox-i has basically no effect.
  • the third transistor T3 and the fourth transistor T4 are P-type transistors as an example, when the second signal terminal CN is the second node n2, since the voltage of the second node n2 is high in the output stage In the holding phase, it is low level. Therefore, in the output phase, the third transistor T3 and the fourth transistor T4 are turned on under the control of the voltage of the cascade signal output terminal GP, and the first denoising control node PD-ox and the second The voltage of the denoising control node PD-ox-i is changed to the voltage of the second node n2 and high level, so that the denoising sub-circuit 30 remains closed during the output stage, and does not affect the scanning signal output at the scanning signal output terminal Oput.
  • the third transistor T3 and the fourth transistor T4 are kept off under the control of the voltage of the cascade signal output terminal GP, and the voltage of the second signal terminal CN is low, which is beneficial to reduce the third transistor T3.
  • the leakage of the fourth transistor T4 thereby reducing the impact of the leakage of the third transistor T3 and the fourth transistor T4 on the voltage of the first denoising control node PD-ox, so that the first denoising control node PD-ox
  • the voltage adjustment speed is faster, so that the voltage of the first denoising control node PD-ox can reach a stable voltage value in a shorter time, thereby increasing the denoising speed of the denoising sub-circuit 30.
  • the first turn-on control sub-circuit 211 further includes a fifth transistor T5.
  • the first terminal of the first capacitor C1 is coupled to the second clock signal terminal CB1 through the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is coupled to the scan signal output terminal Oput, the first electrode of the fifth transistor T5 is coupled to the second clock signal terminal CB1, and the second electrode of the fifth transistor T5 is coupled to the first capacitor C1. ⁇ Coupled.
  • the fifth transistor T5 since the control electrode of the fifth transistor T5 is coupled to the scan signal output terminal Oput, in the output stage, the fifth transistor T5 outputs a high voltage at the scan signal output terminal Oput. It is turned off under the control of the level signal, thereby cutting off the connection between the second clock signal terminal CB1 and the first capacitor C1, so that the potential change of the second clock signal terminal CB1 will not affect the first capacitor C1, thereby eliminating the first capacitor
  • the non-coupling of C1 under the change of the potential of the second clock signal terminal CB1 also eliminates the effect of this on the potential of the second denoising control node PD-ox-i.
  • the denoising sub-circuit 30 includes a sixth transistor T6.
  • the control electrode of the sixth transistor T6 is coupled to the first denoising control node PD-ox, the first electrode of the sixth transistor T6 is coupled to the first voltage terminal VSS, and the second electrode of the sixth transistor T6 is coupled to the scan signal output terminal Oput coupling.
  • the denoising control sub-circuit 20 can keep the voltage of the first denoising control node PD-ox at a stable voltage at which the denoising sub-circuit 30 is turned on during the holding phase, the de-noising sub-circuit 30
  • the sixth transistor T6 is continuously turned on, so that the voltage of the first voltage terminal VSS can be continuously transmitted to the scan signal output terminal Oput, which ensures the continuous denoising of the scan signal output terminal Oput.
  • the shift register circuit RS further includes an input sub-circuit 10 and an output sub-circuit 40.
  • the input sub-circuit 10 is coupled to the cascaded signal output terminal GP and the output sub-circuit 40, is configured to control the voltage GP of the cascaded signal output terminal, and is also configured to transmit a turn-on signal to the output sub-circuit 40.
  • the input sub-circuit 10 can control the voltage of the cascade signal output terminal GP to be the voltage that makes the shutdown control unit 22 turn on.
  • the shutdown control unit 22 turns the second
  • the signal of the signal terminal CN is transmitted to the first denoising control node PD-ox to close the denoising sub-circuit 30 to ensure that the output of the scanning signal at the scanning signal output terminal Oput is not affected; in the holding phase, the input sub-circuit 10 can
  • the voltage of the control cascade signal output terminal GP is a voltage that causes the closing control unit 22 to close, so that the denoising sub-circuit 30 is continuously turned on under the action of the opening control unit 21.
  • the input sub-circuit 10 is also coupled to the input signal terminal Iput, the third clock signal terminal CK3, the fourth clock signal terminal CB3, the first voltage terminal VSS, and the second voltage terminal VDD. Under the control of the signal of the third clock signal terminal CK3, the input sub-circuit 10 can also write the signal of the input signal terminal Iput; and, under the control of the voltage of the first voltage terminal VSS, according to the written signal, The output sub-circuit 40 transmits a turn-on signal.
  • the signal transmitted by the third clock signal terminal CK3 coupled to the input sub-circuit 10 may be the same as the signal transmitted by the first clock signal terminal CK1.
  • the third clock signal terminal CK3 is connected to the first clock signal terminal CK1.
  • the clock signal terminal CK1 is coupled;
  • the signal transmitted by the fourth clock signal terminal CB3 may be the same as the signal transmitted by the second clock signal terminal CB1, for example, the fourth clock signal terminal CB3 is coupled to the second clock signal terminal CB1.
  • the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 are the first clock signal terminal CK1 and the second clock signal terminal CB1.
  • the signal transmitted by the third clock signal terminal CK3 coupled to the input sub-circuit 10 is different from the signal transmitted by the first clock signal terminal CK1, and the signal transmitted by the fourth clock signal terminal CB3 is different from the signal transmitted by the second clock signal
  • the signal transmitted by the terminal CB1 is different. That is, as shown in FIG. 10, the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 are coupled to the first clock signal terminal CK1 and the second clock signal terminal CK1 and the second clock signal terminal CK1 coupled to the denoising control sub-circuit 20.
  • the clock signal terminal CB1 is different.
  • the input sub-circuit 10 and the de-noising control sub-circuit 20 are respectively controlled by different groups of clock signals, so that independent control of the input sub-circuit 10 and the de-noising control sub-circuit 20 can be realized, thereby further ensuring the de-noising
  • the control sub-circuit 20 effectively controls the voltage of the first denoising control node PD-ox.
  • the falling edge of the signal of the first clock signal terminal CK1 can be aligned with the rising edge of the signal of the fourth clock signal terminal CB3 and the falling edge of the signal of the scan output signal output terminal Oput, so that the scan output signal can be output After the terminal Oput outputs the scan signal, the voltage of the scan output signal output terminal Oput can be reset in time.
  • the output sub-circuit 40 is coupled to the second voltage terminal VDD or the fifth clock signal terminal CK2.
  • the output sub-circuit 40 is coupled to the fifth clock signal terminal CK2 for illustration; the output sub-circuit 40 is also connected to the scan signal output terminal Oput coupling.
  • the output sub-circuit 40 is configured to, in response to the control of the turn-on signal transmitted by the input sub-circuit 10, transmit the signal of the second voltage terminal VDD or the fifth clock signal terminal CK2 to the scanning signal output terminal Oput, so as to align and scan
  • the gate line coupled to the signal output terminal Oput performs scanning.
  • the input sub-circuit 10 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third capacitor C3, an eleventh transistor T11, a fourth capacitor C4, The twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14.
  • control electrode of the seventh transistor T7 is coupled to the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is coupled to the input signal terminal Iput, and the second electrode of the seventh transistor T7 is coupled to the first node n1 .
  • the control electrode of the eighth transistor T8 is coupled to the first node n1, the first electrode of the eighth transistor T8 is coupled to the third clock signal terminal CK3, and the second electrode of the eighth transistor T8 is coupled to the second node n2.
  • the control electrode of the ninth transistor T9 is coupled to the third clock signal terminal CK3, the first electrode of the ninth transistor T9 is coupled to the first voltage terminal VSS, and the second electrode of the ninth transistor T9 is coupled to the second node n2.
  • the control electrode of the tenth transistor T10 is coupled to the second node n2, the first electrode of the tenth transistor T10 is coupled to the second voltage terminal VDD, and the second electrode of the tenth transistor T10 is coupled to the cascade signal output terminal GP.
  • the first terminal of the third capacitor C3 is coupled to the second node n2, and the second terminal of the third capacitor C3 is coupled to the first electrode of the tenth transistor T10 and the second voltage terminal VDD.
  • the control electrode of the eleventh transistor T11 is coupled to the third node n3, the first electrode of the eleventh transistor T11 is coupled to the fourth clock signal terminal CB3, and the second electrode of the eleventh transistor T11 is coupled to the cascade signal output terminal GP coupling.
  • the first terminal of the fourth capacitor C4 is coupled to the third node n3, and the second terminal of the fourth capacitor C4 is coupled to the second electrode of the eleventh transistor T11 and the cascade signal output terminal GP.
  • the control electrode of the twelfth transistor T12 is coupled to the first voltage terminal VSS, the first electrode of the twelfth transistor T12 is coupled to the third node n3, and the second electrode of the twelfth transistor T12 is coupled to the first node n1 .
  • the control electrode of the thirteenth transistor T13 is coupled to the fourth clock signal terminal CB3, the first electrode of the thirteenth transistor T13 is coupled to the first node n1, and the second electrode of the thirteenth transistor T13 is coupled to the fourth node n4 catch.
  • the control electrode of the fourteenth transistor T14 is coupled to the second node n2, the first electrode of the fourteenth transistor T14 is coupled to the second voltage terminal VDD, and the second electrode of the fourteenth transistor T14 is coupled to the fourth node n4 .
  • the signal transmitted by the third clock signal terminal CK3 coupled to the input sub-circuit 10 is the same as the signal transmitted by the first clock signal terminal CK1
  • the signal transmitted by the fourth clock signal terminal CB3 is the same as the signal transmitted by the second clock signal terminal CB3.
  • the signals transmitted by the clock signal terminal CB1 are the same, that is, when the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 are the first clock signal terminal CK1 and the second clock signal terminal CB1, As shown in FIG.
  • the control electrode of the seventh transistor T7 included in the input sub-circuit 10 is coupled to the first clock signal terminal CK1
  • the first electrode of the eighth transistor T8 is coupled to the first clock signal terminal CK1
  • the ninth transistor T8 is coupled to the first clock signal terminal CK1.
  • the control electrode of the transistor T9 is coupled to the first clock signal terminal CK1
  • the control electrode of the thirteenth transistor T13 is coupled to the second clock signal terminal CB1.
  • the connection relationship of other poles of the above-mentioned transistor and other transistors included in the input sub-circuit 10 can refer to the above-mentioned embodiment corresponding to FIG. 11.
  • the output sub-circuit 40 includes a fifteenth transistor T15.
  • the control electrode of the fifteenth transistor T15 is coupled to the cascade signal output terminal GP or the third node n3 (FIG. 11 shows the case where the control electrode of the fifteenth transistor T15 is coupled to the third node n3), and the tenth
  • the first electrode of the five transistor T15 is coupled to the second voltage terminal VDD or the fifth clock signal terminal CK2 (FIG. 11 shows the case where the control electrode of the fifteenth transistor T15 is coupled to the fifth clock signal terminal CK2)
  • the second electrode of the fifteenth transistor T15 is coupled to the scanning signal output terminal Oput.
  • the transistors used in the shift register circuit RS provided by the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (metal oxide semiconductor, MOS) or other characteristics.
  • TFT thin film transistors
  • MOS metal oxide semiconductor
  • thin film transistors are used as an example for description in the embodiments of the present disclosure.
  • the control pole of each thin film transistor used in the shift register circuit RS is the gate of the transistor, the first pole is one of the source and drain of the thin film transistor, and the second pole is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain of the thin film transistor can be structurally indistinguishable, that is, the first electrode of the thin film transistor in the embodiment of the present disclosure There can be no difference in structure from the second pole.
  • the first electrode of the thin film transistor is a source and the second electrode is a drain; for example, when the thin film transistor is an N-type transistor, the first electrode of the transistor is Drain, the second pole is the source.
  • the thin film transistor is a P-type transistor as an example for description. It should be noted that the embodiments of the present disclosure include but are not limited to this.
  • one or more thin film transistors in the shift register circuit RS provided by the embodiments of the present disclosure may also adopt N-type transistors, and it is only necessary to refer to the corresponding poles of the selected types of thin film transistors in the embodiments of the present disclosure.
  • Each pole of the thin film transistor is connected correspondingly, and the corresponding voltage terminal provides a corresponding high-level voltage or a low-level voltage.
  • the specific implementation manners of the input sub-circuit 10, the denoising control sub-circuit 20, the de-noising sub-circuit 30, and the output sub-circuit 40 are not limited to the above-described manners, and they can be implemented arbitrarily.
  • the conventional connection method well known to those skilled in the art only needs to ensure that the corresponding function is realized.
  • the above examples cannot limit the protection scope of the present disclosure.
  • the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation.
  • Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • the capacitors may be separately manufactured capacitor devices through a process, such as Capacitor devices are realized by making special capacitor electrodes, and each capacitor electrode of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), and the like.
  • the capacitance can also be the parasitic capacitance between the transistors, or it can be realized by the transistor itself and other devices or lines, or it can be realized by the parasitic capacitance between the circuit itself.
  • some embodiments of the present disclosure provide a driving method of the shift register circuit RS.
  • the driving process of a row of gate lines includes an input phase P1, an output phase P2, and a holding phase P3.
  • the input sub-circuit 10 controls the cascade signal output terminal GP
  • the voltage is the first control voltage, so that the denoising control sub-circuit 20 turns on the de-noising sub-circuit 30, where the first control voltage means that the cascaded signal output terminal GP can de-noise through the control of the de-noising control sub-circuit 20.
  • the voltage at which the circuit 30 is turned on for example, the first control voltage is equal to the voltage value output from the second voltage terminal, so that the denoising control sub-circuit 20 controls the voltage of the first denoising control node PD-ox to turn on the denoising circuit 30 Voltage to turn on the denoising circuit 30.
  • the input sub-circuit 10 also transmits a turn-on signal to the output sub-circuit 40.
  • the input sub-circuit 10 writes the signal of the input signal terminal Iput under the control of the signal of the third clock signal terminal CK3, and turns on the output sub-circuit 40 according to the written signal of the signal terminal Iput.
  • the input sub-circuit 10 controls the voltage of the cascade signal output terminal GP to the second control voltage, so that the de-noising control sub-circuit 20 turns off the de-noising sub-circuit 30.
  • the second control voltage refers to the voltage at which the denoising circuit 30 can be turned off by controlling the denoising control sub-circuit 20 at the cascade signal output terminal GP.
  • the second control voltage is equal to the voltage value output from the first voltage terminal.
  • the denoising control sub-circuit 20 controls the voltage of the first denoising control node PD-ox to be the voltage at which the denoising circuit 30 is turned off.
  • the input sub-circuit 10 continues to transmit the turn-on signal to the output sub-circuit 40.
  • the output sub-circuit 40 can connect the second voltage terminal VDD or the fifth clock signal terminal CK2 (the output sub-circuit 40 and the fifth clock signal terminal CK2 are shown in FIG.
  • the terminal CK2 is coupled, the signal is transmitted to the scan signal output terminal Oput to scan the gate line coupled with the scan signal output terminal Oput.
  • the denoising control sub-circuit 20 In the holding phase P3, in response to the signal of the first clock signal terminal CK1, the denoising control sub-circuit 20 generates an alternating voltage signal according to the voltage of the first voltage terminal VSS and the signal of the second clock signal terminal CB1, and combines the generated alternating voltage signal.
  • the variable voltage signal is rectified and output to the first denoising control node PD-ox, so that the voltage of the first denoising control node PD-ox is maintained at the voltage that enables the denoising sub-circuit 30;
  • the noise control node PD-ox is continuously turned on under the control of the voltage, and the scanning signal output terminal Oput is denoised.
  • each transistor in the shift register circuit RS is a P-type transistor (without considering the influence of the threshold voltage of the transistor), the voltage transmitted by the first voltage terminal VSS is a low-level voltage, and the second voltage terminal The voltage transmitted by VDD is a high-level voltage as an example for description.
  • control electrode of the fifteenth transistor T15 is coupled to the third node n3, and the first electrode of the fifteenth transistor T15 is coupled to the fifth clock signal terminal CK2 as an example.
  • control electrode and the first electrode of the fifteenth transistor T15 may also be coupled to other nodes or signal terminals.
  • control electrode of the fifteenth transistor T15 is coupled to the cascade signal output terminal GP,
  • the first electrode of the fifteenth transistor T15 is coupled to the second voltage terminal VDD.
  • the driving process of a row of gate lines includes at least an input phase P1, an output phase P2, and a holding phase P3.
  • the holding phase P3 includes at least a first holding period P31 and a second holding period P32.
  • the seventh transistor T7 is turned on under the control of the low-level signal of the third clock signal terminal CK3, and the input signal terminal Iput outputs a low-level signal to the first node n1; the eighth transistor T8 is at the first node n1
  • the ninth transistor T9 is turned on under the control of the low-level signal of the third clock signal terminal CK3, and therefore the voltage of the second node n2 is the low-level voltage.
  • the tenth transistor T10 is turned on under the control of the low-level voltage of the second node n2, and the high-level voltage VDD of the second voltage terminal VDD is transmitted to the cascade signal output terminal GP through the tenth transistor T10; the twelfth transistor T12 is The first voltage terminal VSS is turned on under the control of the first node n1 to transmit the low-level voltage of the first node n1 to the third node n3 and the eleventh transistor T11.
  • the eleventh transistor T11 is turned on, so that the eleventh transistor T11 turns on the fourth clock
  • the high level signal of the signal terminal CB3 is transmitted to the cascade signal output terminal GP; therefore, the voltage of the cascade signal output terminal GP is the high level voltage VDD.
  • the fourth capacitor C4 is charged, the voltage at its end coupled to the third node n3 is a low-level voltage, and the voltage at its end coupled to the eleventh transistor T11 is a high-level voltage, which realizes the input Write the signal transmitted by the signal terminal Iput.
  • the third transistor T3 and the fourth transistor T4 are both turned off under the control of the high-level voltage of the cascade signal output terminal GP.
  • the first transistor T1 is turned on under the control of the low-level signal output from the first clock signal terminal CK1
  • the voltage of the second denoising control node PD-ox-i is the low-level voltage VSS
  • the second transistor T2 is in the second de-noising control node.
  • the noise control node PD-ox-i is turned on under the control of the low-level voltage VSS
  • the voltage of the first denoising control node PD-ox is the low-level voltage VSS
  • the sixth transistor T6 is turned on, and the scanning signal output terminal Oput
  • the voltage is a low-level voltage VSS, which realizes the denoising of the scanning signal output terminal Oput by the denoising sub-circuit 30.
  • the fourteenth transistor T14 is turned on under the control of the low-level voltage VSS of the second node n2, and the fourteenth transistor T14 transmits the high-level voltage of the second voltage terminal VDD coupled to the first pole of the fourteenth transistor T14 to the fourth node.
  • the thirteenth transistor T13 is turned off under the control of the high-level signal of the fourth clock signal terminal CB3 at this time, so that the voltage of the fourth node n4 is the high-level voltage VDD.
  • the fifteenth transistor T15 is turned on under the control of the low-level voltage of the third node n3, and the low-level voltage output by the fifth clock signal terminal CK2 is transmitted to the scan signal output terminal Oput through the fifteenth transistor T15, so that the scan signal is output The terminal Oput does not output scan signals.
  • the seventh transistor T7 is turned off under the control of the high-level signal of the third clock signal terminal CK3, and the voltage of the first node n1 is still a low-level voltage; the eighth transistor T8 is low at the first node n1.
  • the high-level signal of the third clock signal terminal CK3 is transmitted to the second node n2 through the eighth transistor T8, and the ninth transistor T9 is under the control of the high-level signal of the third clock signal terminal CK3 It is off, so the voltage of the second node n2 is a high-level voltage.
  • the tenth transistor T10 is turned off under the control of the high-level voltage of the second node n2; the twelfth transistor T12 is turned on under the control of the first voltage terminal VSS, and transmits the low-level voltage of the first node n1 to the third node n3 and the eleventh transistor T11 and the eleventh transistor T11 are turned on, so that the eleventh transistor T11 transmits the low-level signal of the fourth clock signal terminal CB3 to the cascade signal output terminal GP; therefore, the cascade signal output terminal GP
  • the voltage is a low-level voltage.
  • the voltage at the end of the fourth capacitor C4 coupled to the eleventh transistor T11 is a low-level voltage, assuming that the voltage of the low-level signal of the fourth clock signal terminal CB3 is VSS, and the voltage of the high-level signal is VDD, the voltage at one end of the fourth capacitor C4 coupled to the eleventh transistor T11 drops from VDD in the input stage P1 to VSS, and the voltage drop is VDD-VSS. Due to the capacitance bootstrap effect of the fourth capacitor C4, the voltage of the third node n3 coupled to the other end of the fourth capacitor C4 is further pulled down by VDD-VSS, and the voltage of the third node n3 is changed by the input stage The VSS of P1 drops to 2VSS-VDD.
  • the fifteenth transistor T15 is turned on under the control of the low-level voltage of the third node n3, and the high-level voltage output by the fifth clock signal terminal CK2 is transmitted to the scan signal output terminal Oput through the fifteenth transistor T15, so that the scan signal is output
  • the terminal Oput outputs the scanning signal to realize the scanning of the gate line.
  • the third transistor T3 and the fourth transistor T4 are both turned on under the control of the low-level voltage of the cascade signal output terminal GP, and the signal of the second signal terminal CN is transmitted to the second denoising control node PD- through the third transistor T3.
  • ox-i is transmitted to the first denoising control node PD-ox via the fourth transistor T4. Since the second signal terminal CN is the second voltage terminal VDD or the second node n2 (the voltage of the second node n2 in the output phase P2 is a high-level voltage), the second denoising control node PD-ox-i and the first The voltages of the denoising control node PD-ox are all high-level voltages. Therefore, the sixth transistor T6 is turned off, which does not affect the output of the scan signal at the scan signal output terminal Oput.
  • the first transistor T1 is turned off under the control of the high-level signal output from the first clock signal terminal CK1, and the second transistor T2 is also under the control of the high-level voltage of the second denoising control node PD-ox-i. closure.
  • the fourteenth transistor T14 is turned off under the control of the high-level voltage of the second node n2, and the thirteenth transistor T13 is turned on under the control of the low-level signal of the fourth clock signal terminal CB3, so the fourth node n4
  • the voltage is equal to the voltage of the first node n1, that is, a low-level voltage.
  • the seventh transistor T7 is turned on under the control of the low-level signal of the third clock signal terminal CK3, and the high-level signal of the input signal terminal Iput is transmitted to the first node n1 through the seventh transistor T7, so that the first The voltage of the node n1 becomes a high-level voltage; the eighth transistor T8 is turned off under the control of the high-level voltage of the first node n1; the ninth transistor T9 is turned on under the control of the low-level signal of the third clock signal terminal CK3 , The low-level signal VSS of the first signal terminal VSS is transmitted to the second node n2 through the ninth transistor T9, so that the voltage of the second node n2 is the low-level voltage VSS.
  • the tenth transistor T10 is turned on under the control of the low-level voltage of the second node n2, and the high-level voltage of the second voltage terminal VDD is transmitted to the cascade signal output terminal GP through the tenth transistor T10; the twelfth transistor T12 is A voltage terminal VSS is turned on under the control of the first node n1 to transmit the high-level voltage of the first node n1 to the third node n3 and the eleventh transistor T11, and the eleventh transistor T11 is turned off; therefore, the voltage of the cascade signal output terminal GP is high Level voltage.
  • the third transistor T3 and the fourth transistor T4 are both turned off under the control of the high-level voltage of the cascade signal output terminal GP.
  • the first transistor T1 is turned on under the control of the low-level signal output from the first clock signal terminal CK1, and the voltage of the second denoising control node PD-ox-i is the low-level voltage VSS.
  • the voltage at the end of the first capacitor C1 connected to the second denoising control node PD-ox-i is the low-level voltage VSS, and the voltage at the end of the first capacitor C1 connected to the second clock signal terminal CB1 is the second clock The voltage of the high-level signal of the signal terminal CB1.
  • the voltage of the high-level signal output by the second clock signal terminal CB1 is the high-level voltage VDD
  • the voltage of the end of the first capacitor C1 connected to the second clock signal terminal CB1 The voltage is the high-level voltage VDD.
  • the second transistor T2 is turned on under the control of the low-level voltage VSS of the second denoising control node PD-ox-i, and the voltage of the first denoising control node PD-ox is the low-level voltage VSS; thus the sixth transistor T6 When it is turned on, the voltage of the scan signal output terminal Oput is the low-level voltage VSS, which realizes the denoising of the scan signal output terminal Oput by the denoising sub-circuit 30.
  • the fourteenth transistor T14 is turned on under the control of the low-level voltage VSS of the second node n2, and the fourteenth transistor T14 transmits the high-level voltage VDD of the second voltage terminal VDD coupled to the first pole of the fourteenth transistor T14 to the second node n2.
  • the fourth node n4 At this time, the thirteenth transistor T13 is turned off under the control of the high-level signal of the fourth clock signal terminal CB3, so that the voltage of the fourth node n4 is the high-level voltage VDD.
  • the fifteenth transistor T15 is turned off under the control of the high-level voltage of the third node n3.
  • the seventh transistor T7 is turned off under the control of the high-level signal of the third clock signal terminal CK3, and the voltage of the first node n1 is still the high-level voltage; the eighth transistor T8 is at the high level of the first node n1. It is still turned off under the control of the level voltage; the ninth transistor T9 is turned off under the control of the high-level signal of the third clock signal terminal CK3, and the voltage of the second node n2 is still the low-level voltage.
  • the tenth transistor T10 is turned on under the control of the low-level voltage of the second node n2, and the high-level voltage of the second voltage terminal VDD is transmitted to the cascade signal output terminal GP through the tenth transistor T10; the twelfth transistor T12 is A voltage terminal VSS is turned on under the control of the first node n1 to transmit the high-level voltage of the first node n1 to the third node n3 and the eleventh transistor T11, and the eleventh transistor T11 is turned off; therefore, the voltage of the cascade signal output terminal GP is high Level voltage.
  • the third transistor T3 and the fourth transistor T4 are both turned off under the control of the high-level voltage of the cascade signal output terminal GP.
  • the first transistor T1 is turned off under the control of the high-level signal output from the first clock signal terminal CK1, and the second denoising control node PD-ox-i is in a floating state.
  • the voltage at one end of the first capacitor C1 connected to the second clock signal terminal CB1 is the voltage of the low-level signal of the second clock signal terminal CB1, that is, the low-level voltage VSS, then the voltage of the first capacitor C1 and the second clock
  • the voltage of the end connected to the signal terminal CB1 drops from VDD in the first holding period P31 to the low-level voltage VSS, and the voltage drops by VSS-VDD.
  • C PD-ox-i is the total capacitance of each device (including transistors T1, T2, T3 and capacitor C1) connected to the second denoising control node PD-ox-i
  • C1 is the capacitance of the first capacitor C1 Therefore, the voltage of the second denoising control node PD-ox-i drops from VSS in the first holding period P31 to
  • the voltage of the first denoising control node PD-ox is the low-level voltage VSS
  • the voltage of the second denoising control node PD-ox-i is Therefore, the second transistor T2 is turned on, and about half of the charge flows from the first denoising control node PD-ox into the second denoising control node PD-ox-i. That is, the first denoising control node PD-ox and the second denoising control node PD-ox-i perform voltage equalization, so that the voltage of the first denoising control node PD-ox becomes In other words, the voltage of the first denoising control node PD-ox is pulled down from VSS in the first holding period P31 to
  • the first denoising control node PD-ox and the second denoising control node PD-ox-i will be coupled multiple times, and the voltage will be averaged multiple times, and finally the voltage of the first denoising control node PD-ox will be stable Near a certain voltage, the voltage change of the first denoising control node PD-ox is shown in the waveform in Figure 12, so that the sixth transistor T6 is continuously turned on during the holding phase P3, and the scanning signal output terminal Oput is continuously deactivated. noise.
  • C1 is large enough, it is considered that C PD-ox-i ⁇ C1 (it can be understood that C1 accounts for a relatively large proportion of C PD-ox-i , such as greater than or equal to 90%), the above derivation Refer to the description below for the values involved in the process.
  • the offset of the voltage of the second denoising control node PD-ox-i is VSS-VDD, so the voltage of the second denoising control node PD-ox-i is maintained by the first
  • the first denoising control node PD-ox and the second denoising control node PD-ox-i will be coupled multiple times, and the voltage will be averaged multiple times, and finally the voltage of the first denoising control node PD-ox will be stable In the vicinity of 2VSS-VDD, the sixth transistor T6 is continuously turned on during the holding phase P3 to continuously denoise the scan signal output terminal Oput.
  • the fourteenth transistor T14 is turned on under the control of the low-level voltage of the second node n2, and the fourteenth transistor T14 connects its first pole to the high voltage of the second voltage terminal VDD.
  • the level voltage VDD is transmitted to the fourth node n4.
  • the thirteenth transistor T13 is turned on under the control of the low level signal of the fourth clock signal terminal CB3, so that the voltage of the fourth node n4 is the high level voltage VDD.
  • the thirteenth transistor T13 and the fourteenth transistor T14 jointly control the second voltage terminal VDD to charge the first node n1, keep the first node n1 at a high level voltage, and ensure that the eleventh transistor T11 is in the off state.
  • the fifteenth transistor T15 is turned off under the control of the high-level voltage of the third node n3.
  • the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 in the shift register circuit RS are the first clock signal
  • the driving timing of the shift register circuit RS can be as shown in FIG.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electroluminescent Light Sources (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of El Displays (AREA)

Abstract

一种移位寄存器电路（RS）包括去噪控制子电路（20）和去噪子电路（30），去噪控制子电路（20）被配置为响应于第一时钟信号端（CK1）的信号，根据第一电压端（VSS）的电压和第二时钟信号端（CB1）的信号生成交变电压信号，并将该交变电压信号整流后输出至第一去噪控制节点（PD-ox），使第一去噪控制节点（PD-ox）的电压保持为令去噪子电路（30）开启的电压；去噪子电路（30）被配置为在第一去噪控制节点（PD-ox）的电压的控制下持续开启，以对扫描信号输出端（Oput）去噪。

Description

移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
本申请要求于2020年4月29日提交的、申请号为202010356184.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器电路及其驱动方法、栅极驱动电路、显示装置。
背景技术
随着显示技术的进步，作为显示装置核心的半导体元件技术也随之取得了很大的进步。有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点，而越来越多地被应用于高性能显示装置当中。
发明内容
第一方面，提供了一种移位寄存器电路。所述移位寄存器电路包括去噪控制子电路和去噪子电路。其中，去噪控制子电路与第一电压端、第一时钟信号端、第二时钟信号端和第一去噪控制节点耦接。去噪控制子电路被配置为在响应于所述第一时钟信号端的信号，根据所述第一电压端的电压和第二时钟信号端的信号生成交变电压信号，并将交变电压信号整流后输出至第一去噪控制节点，使第一去噪控制节点的电压保持为令去噪子电路开启的电压。去噪子电路与第一去噪控制节点和扫描信号输出端耦接。去噪子电路被配置为响应于第一去噪控制节点的电压为令去噪子电路开启的电压，对扫描信号输出端去噪。
在一些实施例中，去噪子电路包括第一开启控制子电路和第二开启控制子电路。其中，第一开启控制子电路与第一时钟信号端、第二时钟信号端、第一电压端以及第二去噪控制节点耦接，被配置为周期性地响应于所述第一时钟信号端的信号，将第一电压端的电压输出至第二去噪控制节点，并根据第二时钟信号端的信号，拉动第二去噪控制节点的电压，使得第二去噪控制节点提供交变电压信号；第二开启控制子电路与第一去噪控制节点和第二去噪控制节点耦接，被配置为响应于第二去噪控制节点提供的交变电压信号，将交变电压信号整流后输出至第一去噪控制节点，使第一去噪控制节点的电压保持为令去噪子电路开启的电压。
在一些实施例中，第一开启控制子电路包括第一晶体管和第一电容；和/ 或，第二开启控制子电路包括第二晶体管和第二电容。第一晶体管的控制极与第一时钟信号端耦接，第一晶体管的第一极与第一电压端耦接，第一晶体管的第二极与第二去噪控制节点耦接。第一电容的第一端与第二时钟信号端耦接，第一电容的第二端与第二去噪控制节点耦接。第二晶体管的控制极与第二去噪控制节点耦接，第二晶体管的第一极与第一去噪控制节点耦接，第二晶体管的第二极与第二去噪控制节点耦接。第二电容的第一端与第一信号端耦接，第二电容的第二端与第一去噪控制节点耦接。
在一些实施例中，去噪控制子电路还与级联信号输出端耦接，还被配置为，响应于级联信号输出端的电压，将第二信号端的信号传输至第一去噪控制节点，以控制去噪子电路关闭。
在一些实施例中，移位寄存器电路还包括第三晶体管和第四晶体管。第三晶体管的控制极与级联信号输出端耦接，第三晶体管的第一极与控制信号端耦接，第三晶体管的第二极与第二去噪控制节点耦接。第四晶体管的控制极与级联信号输出端耦接，第四晶体管的第一极与控制信号端耦接，第四晶体管的第二极与第一去噪控制节点耦接。
在一些实施例中，第一开启控制子电路还包括第五晶体管。第一电容的第一端通过第五晶体管与第二时钟信号端耦接。第五晶体管的控制极与扫描信号输出端耦接，第五晶体管的第一极与第二时钟信号端耦接，第五晶体管的第二极与第一电容的第一端耦接。
在一些实施例中，第一信号端为第一电压端或者第一时钟信号端。
在一些实施例中，去噪子电路包括第六晶体管。第六晶体管的控制极与第一去噪控制节点耦接，第六晶体管的第一极与第一电压端耦接，第六晶体管的第二极与扫描信号输出端耦接。
在一些实施例中，移位寄存器电路还包括输入子电路和输出子电路。其中，输入子电路与级联信号输出端和输出子电路耦接，被配置为控制级联信号输出端的电压，还被配置为向输出子电路传输开启信号。输出子电路还与所述第二电压端或第五时钟信号端耦接，所述输出子电路还与所述扫描信号输出端耦接。输出子电路被配置为响应于输入子电路所传输的开启信号，将所述第二电压端或第五时钟信号端的信号传输至扫描信号输出端。
在一些实施例中，输入子电路包括第七晶体管、第八晶体管、第九晶体管、第十晶体管、第三电容、第十一晶体管、第四电容、第十二晶体管、第十三晶体管和第十四晶体管。第七晶体管的控制极与第三时钟信号端耦接，第七晶体管的第一极与输入信号端耦接，第七晶体管的第二极与第一节点耦 接。
第八晶体管的控制极与第一节点耦接，第八晶体管的第一极与第三时钟信号端耦接，第八晶体管的第二极与第二节点耦接。
第九晶体管的控制极与第三时钟信号端耦接，第九晶体管的第一极与第一电压端耦接，第九晶体管的第二极与第二节点耦接。
第十晶体管的控制极与第二节点耦接，第十晶体管的第一极与第二电压端耦接，第十晶体管的第二极与级联信号输出端耦接。
第三电容的第一端与第二节点耦接，第三电容的第二端与第十晶体管的第一极和第二电压端耦接。
第十一晶体管的控制极与第三节点耦接，第十一晶体管的第一极与第四时钟信号端耦接，第十一晶体管的第二极与级联信号输出端耦接。
第四电容的第一端与第三节点耦接，第四电容的第二端与第十一晶体管的第二极和级联信号输出端耦接。
第十二晶体管的控制极与第一电压端耦接，第十二晶体管的第一极与第三节点耦接，第十二晶体管的第二极与第一节点耦接。
第十三晶体管的控制极与第四时钟信号端耦接，第十三晶体管的第一极与第一节点耦接，第十三晶体管的第二极与第四节点耦接。
第十四晶体管的控制极与第二节点耦接，第十四晶体管的第一极与第二电压端耦接，第十四晶体管的第二极与第四节点耦接。
输出子电路包括第十五晶体管。第十五晶体管的控制极与级联信号输出端或第三节点耦接，第十五晶体管的第一极与第二电压端或第五时钟信号端耦接，第十五晶体管的第二极与扫描信号输出端耦接。
在一些实施例中，第二信号端为第二电压端，或者第二信号端与第二节点耦接。
在一些实施例中，所述第三时钟信号端与所述第一时钟信号端为相同的信号端，所述第四时钟信号端与所述第二时钟信号端为相同的信号端。
第二方面，提供了一种栅极驱动电路。所述栅极驱动电路包括多个级联的移位寄存器电路。所述移位寄存器电路为如上述任一实施例中所述的移位寄存器电路。
第三方面，提供了一种显示装置。所述显示装置包括多条栅线，和如上述第二方面所述的栅极驱动电路。所述栅极驱动电路中的每个移位寄存器电路与至少一条栅线耦接。
在一些实施例中，栅极驱动电路中的每个移位寄存器电路的扫描信号输出端与至少一条栅线耦接。
在一些实施例中，所述多条栅线包括多条第一栅线和多条第二栅线；栅极驱动电路中的每个移位寄存器电路的扫描信号输出端与至少一条第一栅线耦接，并且，栅极驱动电路中的每个移位寄存器电路的级联信号输出端与至少一条第二栅线耦接。
第四方面，提供了一种如上述任一实施例中所述的移位寄存器电路的驱动方法。所述驱动方法包括：在保持阶段，移位寄存器电路的去噪控制子电路响应于第一时钟信号端的信号，根据第一电压端的电压和第二时钟信号端的信号生成交变电压信号，并将生成的交变电压信号整流并输出至第一去噪控制节点，使第一去噪控制节点的电压保持为令去噪子电路开启的电压。去噪子电路响应于第一去噪控制节点的电压为令去噪子电路开启的电压，对扫描信号输出端去噪。
在一些实施例中，所述驱动方法还包括：在移位寄存器电路还包括输入子电路和输出子电路的情况下，在输入阶段，输入子电路响应于第三时钟信号端的信号，控制级联信号输出端的电压为第一控制电压，使得去噪控制子电路将去噪子电路开启；并且向输出子电路传输开启信号。在输出阶段，输入子电路控制级联信号输出端的电压为第二控制电压，使得去噪控制子电路将去噪子电路关闭；并且，继续向输出子电路传输开启信号。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为本公开实施例提供的一种显示面板的结构图；
图1B为本公开实施例提供的一种显示面板的栅极驱动架构图；
图2为相关技术中的一种像素电路的结构图；
图3为相关技术中的一种移位寄存器电路的部分结构图；
图4为相关技术中的一种移位寄存器电路的部分驱动时序图；
图5为相关技术中的一种移位寄存器电路的输出噪声图；
图6为本公开实施例提供的一种移位寄存器电路的结构图；
图7为本公开实施例提供的又一种移位寄存器电路的结构图；
图8为本公开实施例提供的另一种移位寄存器电路的结构图；
图9为本公开实施例提供的另一种移位寄存器电路的结构图；
图10为本公开实施例提供的另一种移位寄存器电路的结构图；
图11为本公开实施例提供的另一种移位寄存器电路的结构图；
图12为本公开实施例提供的一种移位寄存器电路的驱动时序图；
图13为本公开实施例提供的另一种移位寄存器电路的结构图；
图14为本公开实施例提供的另一种移位寄存器电路的结构图；
图15为本公开实施例提供的一种移位寄存器电路的驱动时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以 上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供一种显示装置，显示装置是指具有图像显示功能的产品，示例性地，该显示装置可以为:电视、手机、电脑、笔记本电脑、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑、显示器、广告牌、数码相框、具有显示功能的激光打印机、电话、数码相机、便携式摄录机、取景器、监视器、导航仪、车辆、大面积墙壁、家电、信息查询设备(如电子政务、银行、医院、电力等部门的业务查询设备、监视器等。 显示装置包括框架、设置于框架内的显示面板、电路板、显示驱动集成电路(integrated circuit，简称IC)以及其他电子配件等。
上述显示面板可以为：液晶显示面板(Liquid Crystal Display，简称LCD)有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示面板、微LED(包括：miniLED或microLED)显示面板等，本公开对此不做具体限定。
本公开以下实施例以上述显示面板为OLED显示面板为例进行说明。
如图1A所示，上述显示面板100包括：显示区AA(Active Area，有效显示区)和位于显示区AA的至少一侧的周边区BB。图1A中以周边区BB围绕显示区AA一圈进行示意。
上述显示面板100包括设置在显示区AA中的多种颜色的亚像素(sub pixel)P，该多种颜色的亚像素至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素，第一颜色、第二颜色和第三颜色可以为三基色(例如红色、绿色和蓝色)。
为了方便说明，本公开中上述多个亚像素P是以矩阵形式排列为例进行的说明。在此情况下，沿水平方向X排列成一排的亚像素P称为同一行亚像素；沿竖直方向Y排列成一排的亚像素P称为同一列亚像素。
如图1B所示，每一亚像素P中均设置有像素电路(也可称为像素驱动电路)S，该像素电路S包括多个晶体管(图1B中以包括两个晶体管进行示意)。该像素电路S与发光器件L耦接，用于驱动发光器件L发光。其中，位于同一行的像素电路S与同一条栅线GL(Gate Line)连接(即耦接)，位于同一列的像素电路S与同一条数据线DL(Data Line)连接。此外，上述多个亚像素P的排列方式取决于多个亚像素P中像素电路S的排列方式，而与亚像素P中发光器件L的位置无关。
像素电路S中所包括的晶体管可以均为N型晶体管，也可以均为P型晶体管，还可以包括N型和P型两种晶体管，可视实际需要设计。
另外，像素电路S可以包括低温多晶硅(Low Temperature Poly-silicon，简称LTPS)晶体管和氧化物(Oxide)晶体管中的至少一种，例如，像素电路S中的晶体管可以均为LTPS晶体管，也可以均为氧化物晶体管，也可以同时包括LTPS晶体管和氧化物晶体管。
在一些实施例中，由于控制亚像素亮度的电压会由于像素电路S中晶体管漏电而随时间变化，因此为了使保持像素亮度波动在合理的范围内，在显 示静态画面时仍然需要刷新数据。为了降低显示静态画面时的功耗，降低刷新频率是比较有效的方法，但在降低刷新率的同时还需要保持显示质量，这就需要减少像素电路S中晶体管的漏电速度。由于氧化物半导体具有超低漏电的特性，因此可将像素电路S中的晶体管设置为氧化物晶体管，以使得显示面板在显示画面的过程中减少像素电路S中的晶体管的漏电。低温多晶硅的载流子迁移率高，在像素电路S中使用LTPS晶体管可以大大提高晶体管的响应速度，从而保证亚像素的充电速度，并且，LTPS晶体管是以离子注入自动对准来形成源漏极的，因此在栅极与源漏极之间所产生的寄生电容会比非晶硅型晶体管小很多，进而大幅降低电容耦合效应。为了减少像素电路中晶体管的漏电，同时保证亚像素的充电速度和较小的寄生电容，可结合LTPS和Oxide的优势，采用低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)工艺，示例性地，像素电路S中包括LTPS晶体管和氧化物晶体管这两种晶体管，例如，像素电路S中包括P型的LTPS晶体管和N型的氧化物晶体管。
继续参考图1A和图1B，显示装置还可以包括：栅极驱动电路01和数据驱动电路02。示例性地，栅极驱动电路01可以设置在显示面板100的周边区BB；例如，可以设置在周边区BB中位于栅线GL一端的侧边(例如，图1A中周边区BB的左侧边)。示例性地，数据驱动电路02可以设置在显示面板100的周边区BB；例如，数据驱动电路02可以设置在周边区BB中位于数据线DL一端的侧边(例如，图1A中周边区BB的下侧边)，以驱动显示面板100中的像素电路S，进而驱动发光器件L发光，以使相应亚像素P呈现出所要显示的颜色。
在一些实施例中，上述栅极驱动电路01可以为栅极驱动IC，该栅极驱动IC与显示面板100中的阵列基板(也可称为驱动背板)绑定。在另一些实施例中，上述栅极驱动电路01可以为GOA(Gate Driver on Array，栅极驱动集成在阵列基板上)电路，包含在显示面板100中，在此情况下，上述栅极驱动电路01直接集成在显示面板100的阵列基板中。其中，将栅极驱动电路01设置在阵列基板中相比于以栅极驱动IC的形式与阵列基板绑定，一方面，可以降低显示面板100的制作成本；另一方面，还可以窄化显示装置的边框宽度。以下实施例均是以栅极驱动电路01为GOA电路为例进行说明。
需要说明的是，图1A和图1B仅以在显示面板100的周边区BB的单侧设置栅极驱动电路01，从单侧逐行驱动各栅线GL，即以单侧驱动为例进行示意。在另一些实施例中，可以在显示面板100的周边区BB中沿栅线GL的延 伸方向上的两个侧边分别设置栅极驱动电路，通过两个栅极驱动电路同时从两侧逐行驱动各栅线GL，即双侧驱动。在另一些实施例中，可以在显示面板100的周边区BB中沿栅线GL的延伸方向上的两个侧边，分别设置栅极驱动电路，通过两个栅极驱动电路交替从两侧，逐行驱动各栅线GL，例如，一个栅极驱动电路驱动奇数行栅线GL，另一个栅极驱动电路驱动偶数行栅线GL，即交叉驱动。本公开以下实施例均是以单侧驱动为例进行说明的。
本公开的一些实施例中，如图1B所示，栅极驱动电路01中包括N级级联的移位寄存器电路(RS1、RS2……RS(N))，并且上述N级级联的移位寄存器电路(RS1、RS2……RS(N))分别与N条栅线(G1、G2……G(N))一一对应地连接，其中，N为正整数。
示例性地，上述各级移位寄存器电路(RS1、RS2……RS(N))的电路结构可以相同，并且各级移位寄存器电路(RS1、RS2……RS(N))依序连接，以使各级移位寄存器电路依序输出开启电压(也称为扫描信号中的有效电平，例如高电平)，从而实现对显示面板中多条栅线的逐行扫描，使与栅线耦接的各行子像素充电。
例如，如图1B所示，栅极驱动电路01的每一级移位寄存器电路记为RS(i)，其中i＝1,2,…,N。移位寄存器电路RS(i)包括扫描信号输出端Output(下文以及附图均将Output简写为Oput)，从而通过扫描信号输出端Oput向与其连接的栅线GL输出栅极扫描信号。
栅极驱动电路01的各级移位寄存器电路RS(i)中还设置有信号输入端Input(附图以及下文均简写为Iput)，以向各级移位寄存器电路RS(i)提供起始信号。
此外，栅极驱动电路01的各级移位寄存器电路RS(i)还包括级联信号输出端GP，该级联信号输出端GP可连接下级的移位寄存器电路，以向下级的移位寄存器电路传输级联信号，作为下级的移位寄存器电路的起始信号。
在此基础上，栅极驱动电路01中各级移位寄存器电路RS(i)的级联结构可为：
第一级移位寄存器电路RS1的信号输入端Iput与起始信号端STV连接；除与第一级移位寄存器电路RS1以外，其他任一级移位寄存器电路RS(i)的信号输入端Iput与位于其前一级的移位寄存器电路RS(i-1)的级联信号输出端GP连接。
在上述级联结构的基础上，各级移位寄存器电路RS(i)的扫描信号输出端Oput均与至少一条栅线GL耦接。
在一些实施例中，例如，在像素电路S中既包括P型的LTPS晶体管又包括N型的氧化物晶体管的情况下，级联信号输出端GP还可以通过栅线与像素电路S中的P型晶体管连接，以向P型晶体管传输信号(该信号可以称为控制信号)，控制P型晶体管打开或关闭。
在此基础上，栅极驱动电路01中各级移位寄存器电路(RS1、RS2……RS(N))与多条栅线GL的连接关系可为：
同一行的像素电路可以与至少两条栅线耦接，这至少两条栅线包括：至少一条第一栅线和至少一条第二栅线。栅极驱动电路中的每个移位寄存器电路的扫描信号输出端Oput与至少一条第一栅线耦接，并且，栅极驱动电路中的每个移位寄存器电路的级联信号输出端GP与至少一条第二栅线耦接。其中，由于与扫描信号输出端Oput连接的栅线和与级联信号输出端GP连接的栅线不是同一根，为了便于区分，将与扫描信号输出端Oput耦接的栅线称为第一栅线，将与级联信号输出端GP耦接的栅线称为第二栅线。
参照图2所示的7T1C像素电路，并以该像素电路为例说明LTPO型像素电路的控制方法。如图2所示，像素电路S’包括七个晶体管D1～D7，和一个电容器Cst。其中，晶体管D3、D4为N型晶体管，例如N型的氧化物晶体管，晶体管D2、D7为P型晶体管，例如，P型的LTPS晶体管。那么，在第i行的任一像素电路S’中，晶体管D3、D4可以通过两条第一栅线分别与本级的扫描信号输出端Oput(i)、上一级的扫描信号输出端Oput(i-1)耦接，晶体管D2、D7可以通过两条第二栅线分别与本级的级联信号输出端GP(i)、上一级的级联信号输出端GP(i-1)耦接。
通过第一栅线、第二栅线，移位寄存器电路可以分别对LTPO型像素电路中的氧化物晶体管和LTPS晶体管进行控制，使得该控制过程的响应时间大大提升。
在一些相关技术中，在一个帧周期内一行栅线的驱动过程中，一级移位寄存器电路首先向其所耦接的栅线输出扫描信号中的开启电压(也称为有效电压或工作电压)，以使该栅线所耦接的一排子像素打开，此阶段称为输出阶段；之后，该级移位寄存器电路会向其所耦接的栅线输出扫描信号中的关闭电压(也称为非工作电压)，以保证该栅线所耦接的子像素关闭，即进入保持阶段。然而，在保持阶段，移位寄存器电路中与栅线耦接的扫描信号输出端的噪声较大，会导致显示装置所显示的画面不稳定。
本公开的发明人经研究发现造成上述问题的原因之一在于：
如图3和图4所示，图3示出了一些相关技术中移位寄存器电路RS＇的 部分电路结构，图4示出了该移位寄存器电路RS＇的部分驱动时序。在图3中，30＇为去噪子电路，该去噪子电路30＇包括晶体管T03。
在一行栅线的驱动过程中，在输出阶段P2＇，级联信号输出端GP的电位为低电位，晶体管T04打开，扫描信号输出端Oput输出高电平，即输出扫描信号。晶体管T02打开，节点PD-ox＇的电位为高电位，从而去噪子电路30＇中的晶体管T03关闭。
在保持阶段P3＇的P31＇时段，时钟信号端CK1的电位为低电位，晶体管T01打开，节点PD-ox＇的电位为低电位VSS+|V th|，其中，V th为晶体管T01的阈值电压，从而去噪子电路30＇中的晶体管T03打开，扫描信号输出端Oput的电位变为低电位VSS+|V th|，实现了对扫描信号输出端Oput的复位。
在保持阶段P3＇的P32＇时段，时钟信号端CK1的电位为高电位，晶体管T01关闭，并且由于级联信号输出端GP的电位为高电位，晶体管T02也关闭，因此节点PD-ox＇的电位处于浮空状态(floating)，时钟信号端CB1的电位变为低电位，由于电容C01的耦合作用，节点PD_ox＇的电位会被进一步拉低，从而去噪子电路30＇中的晶体管T03进一步开启，扫描信号输出端Oput的电位变为低电位，实现了对扫描信号输出端Oput的进一步复位。
在保持阶段P3＇的P33＇时段，虽然时钟信号端CK1的电位为低电位，而PD_ox’也为低电位，而PMOS晶体管的阈值电压V th一般为负值，因此对于晶体管T01而言，其栅源电压差V gs＞V th，而因为PMOS晶体管是在V gs﹤V th的情况下会导通，所以此时晶体管T01关闭。并且由于级联信号输出端GP的电位为高电位，晶体管T02、T04也关闭，因此节点PD-ox＇和输出端Oput的电位处于浮空状态(floating)；时钟信号端CB1的电位为高电位，由于电容C01的耦合作用，节点PD_ox＇的电位会被稍微拉高，从而去噪子电路30＇中的晶体管T03关闭，不能对扫描信号输出端Oput去噪。
由上述可知，由于时钟信号CK1和CB1交替为高电平和低电平，因此此后P32＇时段和P33＇时段会交替出现，从而在保持阶段，去噪子电路30＇将近一半的时间(即保持阶段P3＇的P33＇时段)不能对扫描信号输出端Oput去噪，这导致受到外界干扰的情况下，移位寄存器电路RS＇在保持阶段P3＇不能及时去噪，扫描信号输出端Oput可能会产生较大噪声。如图5所示，经过模拟测试，在保持阶段P3＇扫描信号输出端Oput的噪声可达2V。
本公开的一些实施例提供一种移位寄存器电路，用以解决在保持阶段，移位寄存器电路中与栅线耦接的扫描信号输出端噪声较大，使画面显示不稳定的问题。如图6所示，移位寄存器RS包括：去噪控制子电路20和去噪子 电路30。
其中，去噪控制子电路20与第一电压端VSS、第一时钟信号端CK1、第二时钟信号端CB1和第一去噪控制节点PD-ox耦接。去噪控制子电路20被配置为，在第一时钟信号端CK1的信号的控制下，将第一电压端VSS的电荷整流至第一去噪控制节点PD-ox，从而可以调整(拉高或拉低)第一去噪控制节点PD-ox的电压，使第一去噪控制节点PD-ox的电压保持为令去噪子电路30开启的电压。具体而言，去噪控制子电路20被配置为，响应于第一时钟信号端CK1的信号，根据第一电压端VSS的电压和第二时钟信号端CB1的信号生成交变电压信号(或者说是振荡信号)，并将所生成的交变电压信号整流后输出至第一去噪控制节点PD-ox，使第一去噪控制节点PD-ox的电压保持为令去噪子电路30开启的电压，例如，使得第一去噪控制节点PD-ox的电压逐渐变化(逐渐拉高或拉低)，最终例如可以到达稳定状态。
其中，交变电压信号是指电压大小周期性变化的信号，示例性地，交变电压信号可以是高低电压交替出现的信号，例如，方波信号。其中，一周期内高电压的时长和低电压的时长可以相同，也可以不同。此外，交变电压信号的幅值可以保持不变，例如，多个周期中高电压可以相等，低电压也可以相等。
整流是指将交变电压信号输出为直流电压信号。在本公开的实施例中，直流电压信号是对比于交变电压信号而定义的，其可以是电压不随时间变化的信号；还可以包括幅值(电压)随时间逐渐增大或逐渐减小的信号，该信号最终例如可以到稳定状态(即电压不再变化)。例如，直流电压信号可以包括多个周期，每个周期中的电压大小不变，且任一周期的电压比前一周期的电压的数值高，或者，任一周期的电压比前一周期的电压的数值低。
应当理解的是，所述“令去噪子电路30开启的电压”是指，能够令去噪子电路30工作的电压，该电压具体取决于去噪子电路30所包括的晶体管的极性。例如，若去噪子电路30所包括的晶体管为P型，则该电压为低电平的电压；若若去噪子电路30所包括的晶体管为N型，则该电压为高电平的电压。去噪子电路30与第一去噪控制节点PD-ox和扫描信号输出端Oput耦接。去噪子电路30被配置为，响应于所述第一去噪控制节点的电压为令所述去噪子电路开启的电压，对扫描信号输出端Oput去噪。
上述移位寄存器电路RS中，去噪控制子电路20能够在第一时钟信号端CK1的信号的控制下，根据接收到的信号(例如，可以包括第一电压端VSS的信号、第二时钟信号端CB1的信号等)对第一去噪控制节点PD-ox的电压 进行稳压调节，即使得第一去噪控制节点PD-ox的电压稳定在令去噪子电路30开启的电压(高电平或低电平)。去噪控制子电路20将调节后的电压输出至去噪子电路30，并控制去噪子电路30保持持续开启的状态，使去噪子电路30持续输出稳定的非工作电压，实现了对扫描信号输出端Oput持续去噪，从而提高了画面显示的稳定性。
在一些实施例中，如图7所示，上述去噪控制子电路20包括开启控制单元21和关闭控制单元22。其中，开启控制单元21与第一电压端VSS、第一时钟信号端CK1、第二时钟信号端CB1、和第一去噪控制节点PD-ox耦接。该开启控制单元21被配置为，在第一时钟信号端CK1的信号的控制下，将第一电压端VSS的电荷整流至第一去噪控制节点PD-ox，以拉高或拉低第一去噪控制节点PD-ox的电压，使第一去噪控制节点PD-ox的电压保持为令去噪子电路30开启的电压。
具体地，开启控制单元21被配置为，响应于第一时钟信号端CK1的信号，根据第一电压端VSS的电压和第二时钟信号端CB1的信号生成交变电压信号，并将所生成的交变电压信号整流后输出至第一去噪控制节点PD-ox，使第一去噪控制节点PD-ox的电压保持为令去噪子电路30开启的电压。示例性地，开启控制单元21还可以和第二去噪控制节点PD-ox-i耦接，生成的上述交变电压信号为第二去噪控制节点PD-ox-i的信号。
此处，例如，第一电压端VSS被配置为传输直流低电平信号。例如，该第一电压端VSS接地。在一些实施例中，去噪控制子电路20的开启控制单元21包括：第一开启控制子电路211和第二开启控制子电路212。
其中，第一开启控制子电路211与第一时钟信号端CK1、第二时钟信号端CB1、第一电压端VSS以及第二去噪控制节点PD-ox-i耦接，被配置为周期性地响应于第一时钟信号端CK1的信号，将第一电压端VSS的电压输出至第二去噪控制节点PD-ox-i，并根据第二时钟信号端CB1的信号，拉动第二去噪控制节点PD-ox-i的电压，使得第二去噪控制节点PD-ox-i提供交变电压信号。
示例性地，参见图8，第一开启控制子电路211包括：第一晶体管T1和第一电容C1。
其中，第一晶体管T1的控制极与第一时钟信号端CK1耦接，第一晶体管T1的第一极与第一电压端VSS耦接，第一晶体管T1的第二极与第二去噪控制节点CB1耦接。
第一电容C1的第一端与第二时钟信号端CB1耦接，第一电容C1的第二 端与第二去噪控制节点PD-ox-i耦接。
示例性地，当第一时钟信号端CK1的信号控制第一晶体管T1被打开时，第一电压端VSS的电压可以通过第一晶体管T1传输至第二去噪控制节点PD-ox-i；当第一时钟信号端CK1的信号控制第一晶体管T1被关断时，第一电压端VSS的电压无法传输至第二去噪控制节点PD-ox-i，但是响应于第二时钟信号端CB1的信号，并且通过第一电容C1的耦合作用，可以进一步拉动第二去噪控制节点PD-ox-i的电压，例如，当第一时钟信号端CK1的信号控制第一晶体管T1被打开时，第二时钟信号端CB1输出低电平，当第一时钟信号端CK1的信号控制第一晶体管T1被关断时，第二时钟信号端CB1输出高电平，以将第二去噪控制节点PD-ox-i的电压拉高。由于第一时钟信号端CK1的信号控制第一晶体管T1周期性地打开与关断，第二时钟信号端CB1周期性地拉动第二去噪控制节点PD-ox-i的电压，二者共同作用，使得第二去噪控制节点PD-ox-i的电压为交变电压。
第二开启控制子电路212与第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i耦接，并将该交变电压信号整流后输出至所述第一去噪控制节点，使第一去噪控制节点PD-ox的电压保持为令去噪子电路30开启的电压。
示例性地，参见图8，第二开启控制子电路212包括：第二晶体管T2和第二电容C2。
其中，第二晶体管T2的控制极与第二去噪控制节点PD-ox-i耦接，第二晶体管T2的第一极与第一去噪控制节点PD-ox耦接，第二晶体管T2的第二极与第二去噪控制节点PD-ox-i耦接。
第二电容C2的第一端与第一信号端ST耦接，第二电容C2的第二端与第一去噪控制节点PD-ox耦接。
示例性地，第二去噪控制节点PD-ox-i提供的交变电压信号可以周期性地开启第二晶体管T2，例如，当交变电压信号为高电平将第二晶体管T2关断，当交变电压信号为低电平时将第二晶体管T2打开。当第二晶体管T2关断时，第一电容器C1的第二端上的电荷无法通过第二晶体管T2传输至第二电容器C2的第二端，而当第二晶体管T2打开时，由于第一电容器C1的第二端的电压被第二时钟信号端CB1拉低，使得第一电容器C1的第二端上的电荷量小于第二电容器C2的第二端上的电荷量，那么，第二电容器C2的第二端上的电荷可以通过第二晶体管T2传输至第一电容器C1的第二端。并且，由于上述过程周期性循环，第二电容器C2的第二端上的电荷不断地向第一电容器C1的第二端传输，使得第二电容器C2的第二端上的电荷逐渐减少，最终稳 定在一个固定值，例如，稳定在与第一电容器C1的第二端的电压被第二时钟信号端CB1拉低时的第一电容器C1的第二端上的电荷相等，进而使得与第二电容器C2相耦接的第一去噪控制节点PD-ox的电压稳定在一个固定电压，该固定的电压使去噪子电路30持续开启。
需要说明的是，在本公开的实施例提供的移位寄存器电路RS中，第一去噪控制节点PD-ox、第二去噪控制节点PD-ox-i和级联信号输出端GP，以及下面会提及的第一节点n1、第二节点n2、第三节点n3和第四节点n4，并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。需要说明的是，上述第一信号端(也可称为稳压信号端)ST可以为第一电压端VSS或者第一时钟信号端CK1。
示例性地，在第一信号端ST为第一电压端VSS的情况下，第二电容C2的第一端连接第一电压端VSS，使得第二电容C2为第一去噪控制节点PD-ox提供稳压功能，防止第一去噪控制节点PD-ox发生漏电。
示例性地，在第一信号端ST为第一时钟信号端CK1的情况下，第二电容C2的第一端连接第一时钟信号端CK1，除了使得第二电容C2能够稳定第一去噪控制节点PD-ox的电压外，还使得第二电容C2在第一时钟信号端CK1的信号的电压变化时能够进一步调整第一去噪控制节点PD-ox的电压，使第一去噪控制节点PD-ox的电压迅速稳定在能够令去噪子电路30开启的电位，有利于提高去噪子电路30的去噪速度。例如，在令去噪子电路30开启的电位为低电位的情况下，当第一时钟信号端CK1的信号的电压降低时，第二电容C2能够进一步拉低第一去噪控制节点PD-ox的电位，有利于提高去噪子电路30的去噪速度。
上述开启控制单元21所包括的第一晶体管T1、第一电容C1、第二晶体管T2和第二电容C2形成电荷泵结构，利用电荷泵结构对电压的调节作用，使得第一去噪控制节点PD-ox的电压被稳定在能够令去噪子电路30开启的电压，从而保证了去噪子电路30在一行栅线的驱动过程中的保持阶段持续开启，从而持续为扫描信号输出端Oput去噪。
在一些实施例中，去噪控制子电路30的关闭控制单元22与级联信号输出端GP、第二信号端(也可以称为控制信号端)CN、第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i耦接。该关闭控制单元22被配置为，响应于级联信号输出端GP的电压，将第二信号端CN的信号传输至第一去噪控制节点PD-ox，以控制去噪子电路30关闭。
示例性地，请继续参阅图8，关闭控制单元22包括第三晶体管T3和第四晶体管T4。
其中，第三晶体管T3的控制极与级联信号输出端GP耦接，第三晶体管T3的第一极与第二信号端CN耦接，第三晶体管T3的第二极与第二去噪控制节点PD-ox-i耦接。
第四晶体管T4的控制极与级联信号输出端GP耦接，第四晶体管T4的第一极与第二信号端CN耦接，第四晶体管T4的第二极与第一去噪控制节点PD-ox耦接。
需要说明的是，上述第二信号端CN可以为第二电压端VDD或者第二节点n2。此处，例如，第二电压端VDD被配置为传输直流高电平信号；例如，该直流高电平信号的电压值大于第一电压端VSS所传输的直流低电平信号的电压值。此处，第二节点n2为后续将会提到的输入子电路10中的一个节点，例如，该节点的电压在一行栅线的驱动过程中的输出阶段为高电平，在保持阶段为低电平。
示例性地，在第二信号端CN为第二电压端VDD的情况下，在输出阶段，第三晶体管T3和第四晶体管T4在级联信号输出端GP的电压的控制下打开，第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i的电压都变为第二电压端VDD的电压，即高电平，从而使得去噪子电路30在输出阶段保持关闭，不影响扫描信号输出端Oput处扫描信号的输出。在保持阶段，第三晶体管T3和第四晶体管T4在级联信号输出端GP的电压的控制下保持关闭状态，则第二信号端CN的高电平对第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i的电压基本无影响。
示例性地，以第三晶体管T3和第四晶体管T4均为P型晶体管为例，在第二信号端CN为第二节点n2的情况下，由于第二节点n2的电压在输出阶段为高电平，在保持阶段为低电平，因此在输出阶段，第三晶体管T3和第四晶体管T4在级联信号输出端GP的电压的控制下打开，第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i的电压都变为第二节点n2的电压，及高电平，从而使得去噪子电路30在输出阶段保持关闭，不影响扫描信号输出端Oput处扫描信号的输出。在保持阶段，第三晶体管T3和第四晶体管T4在级联信号输出端GP的电压的控制下保持关闭状态，则第二信号端CN的电压为低电平，这有利于减少第三晶体管T3和第四晶体管T4的漏电量，从而减小了第三晶体管T3和第四晶体管T4的漏电对第一去噪控制节点PD-ox的电压的影响，使得第一去噪控制节点PD-ox的电压的调节速度更快，从而能够使得第 一去噪控制节点PD-ox的电压在更短时间内达到一个稳定电压值，进而提高了去噪子电路30的去噪速度。
在一些实施例中，如图9所示，第一开启控制子电路211还包括第五晶体管T5。第一电容C1的第一端通过第五晶体管T5与第二时钟信号端CB1耦接。第五晶体管T5的控制极与扫描信号输出端Oput耦接，第五晶体管T5的第一极与第二时钟信号端CB1耦接，第五晶体管T5的第二极与第一电容C1的第一端耦接。
以第五晶体管T5为P型晶体管为例，由于上述第五晶体管T5的控制极与扫描信号输出端Oput耦接，因此，在输出阶段，第五晶体管T5在扫描信号输出端Oput输出的高电平信号的控制下关闭，从而切断了第二时钟信号端CB1与第一电容C1之间的连接，使得第二时钟信号端CB1的电位变化不会影响第一电容C1，从而消除了第一电容C1在第二时钟信号端CB1的电位变化下的不耦合，也就消除了由此对第二去噪控制节点PD-ox-i的电位的影响。
在一些实施例中，如图11所示，去噪子电路30包括第六晶体管T6。第六晶体管T6的控制极与第一去噪控制节点PD-ox耦接，第六晶体管T6的第一极与第一电压端VSS耦接，第六晶体管T6的第二极与扫描信号输出端Oput耦接。
在上述实施例中，由于在保持阶段，去噪控制子电路20能够使第一去噪控制节点PD-ox的电压保持为稳定的令去噪子电路30开启的电压，因此去噪子电路30的第六晶体管T6持续开启，从而能够将第一电压端VSS的电压持续传输到扫描信号输出端Oput，保证了对扫描信号输出端Oput持续去噪。
在一些实施例中，如图10所示，移位寄存器电路RS还包括输入子电路10和输出子电路40。
输入子电路10与级联信号输出端GP和输出子电路40耦接，被配置为控制级联信号输出端的电压GP，还被配置为向输出子电路40传输开启信号。
示例性地，在输出阶段，输入子电路10可以控制级联信号输出端GP的电压为令关闭控制单元22开启的电压，响应于级联信号输出端GP的电压，关闭控制单元22将第二信号端CN的信号传输至第一去噪控制节点PD-ox，以将去噪子电路30关闭，保证扫描信号输出端Oput处扫描信号的输出不受影响；在保持阶段，输入子电路10可以控制级联信号输出端GP的电压为令关闭控制单元22关闭的电压，以将去噪子电路30在开启控制单元21的作用下持续开启。
此外，输入子电路10还与输入信号端Iput、第三时钟信号端CK3、第四 时钟信号端CB3、第一电压端VSS、第二电压端VDD耦接。在第三时钟信号端CK3的信号的控制下，输入子电路10还可以写入输入信号端Iput的信号；及，在第一电压端VSS的电压的控制下，根据所写入的信号，向输出子电路40传输开启信号。
其中，示例性地，输入子电路10所耦接的第三时钟信号端CK3所传输的信号可以与第一时钟信号端CK1所传输的信号相同，例如，将第三时钟信号端CK3与第一时钟信号端CK1耦接；第四时钟信号端CB3所传输的信号可以与第二时钟信号端CB1所传输的信号相同，例如，将第四时钟信号端CB3与第二时钟信号端CB1耦接。在此情况下，如图13所示，可以认为输入子电路10所耦接的第三时钟信号端CK3和第四时钟信号端CB3即为第一时钟信号端CK1和第二时钟信号端CB1。
示例性地，输入子电路10所耦接的第三时钟信号端CK3所传输的信号与第一时钟信号端CK1所传输的信号不同，第四时钟信号端CB3所传输的信号与第二时钟信号端CB1所传输的信号不同。即，如图10所示，输入子电路10所耦接的第三时钟信号端CK3和第四时钟信号端CB3，与去噪控制子电路20所耦接的第一时钟信号端CK1和第二时钟信号端CB1不同。也就是说，输入子电路10与去噪控制子电路20分别受控于不同组的时钟信号，这样可实现对输入子电路10与去噪控制子电路20各自的独立控制，从而进一步保证去噪控制子电路20对于第一去噪控制节点PD-ox的电压的有效控制。此外，可以使第一时钟信号端CK1的信号的下降沿，与第四时钟信号端CB3的信号的上升沿，及扫描输出信号输出端Oput的信号的下降沿对齐，这样可以在扫描输出信号输出端Oput输出扫描信号后实现对扫描输出信号输出端Oput的电压进行及时复位。
输出子电路40与第二电压端VDD或第五时钟信号端CK2耦接，图10中以输出子电路40与第五时钟信号端CK2耦接进行示意；输出子电路40还与扫描信号输出端Oput耦接。输出子电路40被配置为，响应于输入子电路10所传输的开启信号的控制下，将第二电压端VDD或第五时钟信号端CK2的信号传输至扫描信号输出端Oput，以对与扫描信号输出端Oput耦接的栅线进行扫描。
示例性地，请参阅图11，输入子电路10包括第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第三电容C3、第十一晶体管T11、第四电容C4、第十二晶体管T12、第十三晶体管T13和第十四晶体管T14。
其中，第七晶体管T7的控制极与第三时钟信号端CK3耦接，第七晶体 管T7的第一极与输入信号端Iput耦接，第七晶体管T7的第二极与第一节点n1耦接。
第八晶体管T8的控制极与第一节点n1耦接，第八晶体管T8的第一极与第三时钟信号端CK3耦接，第八晶体管T8的第二极与第二节点n2耦接。
第九晶体管T9的控制极与第三时钟信号端CK3耦接，第九晶体管T9的第一极与第一电压端VSS耦接，第九晶体管T9的第二极与第二节点n2耦接。
第十晶体管T10的控制极与第二节点n2耦接，第十晶体管T10的第一极与第二电压端VDD耦接，第十晶体管T10的第二极与级联信号输出端GP耦接。
第三电容C3的第一端与第二节点n2耦接，第三电容C3的第二端与第十晶体管T10的第一极和第二电压端VDD耦接。
第十一晶体管T11的控制极与第三节点n3耦接，第十一晶体管T11的第一极与第四时钟信号端CB3耦接，第十一晶体管T11的第二极与级联信号输出端GP耦接。
第四电容C4的第一端与第三节点n3耦接，第四电容C4的第二端与第十一晶体管T11的第二极和级联信号输出端GP耦接。
第十二晶体管T12的控制极与第一电压端VSS耦接，第十二晶体管T12的第一极与第三节点n3耦接，第十二晶体管T12的第二极与第一节点n1耦接。
第十三晶体管T13的控制极与第四时钟信号端CB3耦接，第十三晶体管T13的第一极与第一节点n1耦接，第十三晶体管T13的第二极与第四节点n4耦接。
第十四晶体管T14的控制极与第二节点n2耦接，第十四晶体管T14的第一极与第二电压端VDD耦接，第十四晶体管T14的第二极与第四节点n4耦接。
基于上述实施例，在输入子电路10所耦接的第三时钟信号端CK3所传输的信号与第一时钟信号端CK1所传输的信号相同，第四时钟信号端CB3所传输的信号与第二时钟信号端CB1所传输的信号相同，即输入子电路10所耦接的第三时钟信号端CK3和第四时钟信号端CB3为第一时钟信号端CK1和第二时钟信号端CB1的情况下，如图13所示，输入子电路10所包括的第七晶体管T7的控制极与第一时钟信号端CK1耦接，第八晶体管T8的第一极与第一时钟信号端CK1耦接，第九晶体管T9的控制极与第一时钟信号端CK1耦接，第十三晶体管T13的控制极与第二时钟信号端CB1耦接。此外，上述晶 体管的其他极，及输入子电路10所包括的其他晶体管的连接关系可参见图11所对应的上述实施例。
示例性地，请继续参阅图11，输出子电路40包括第十五晶体管T15。第十五晶体管T15的控制极与级联信号输出端GP或第三节点n3耦接(图11中示出了第十五晶体管T15的控制极与第三节点n3耦接的情况)，第十五晶体管T15的第一极与第二电压端VDD或第五时钟信号端CK2耦接(图11中示出了第十五晶体管T15的控制极与第五时钟信号端CK2耦接的情况)，第十五晶体管T15的第二极与扫描信号输出端Oput耦接。
需要说明的是，本公开的实施例提供的移位寄存器电路RS中所采用的晶体管可以为薄膜晶体管(Thin Film Transistor)，简称TFT)、场效应晶体管(metal oxide semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
移位寄存器电路RS所采用的各薄膜晶体管的控制极为晶体管的栅极，第一极为薄膜晶体管的源极和漏极中一者，第二极为薄膜晶体管的源极和漏极中另一者。由于薄膜晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的薄膜晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在薄膜晶体管为P型晶体管的情况下，薄膜晶体管的第一极为源极，第二极为漏极；示例性的，在薄膜晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的移位寄存器电路RS中，均以薄膜晶体管为P型晶体管为例进行说明。需要说明的是，本公开的实施例包括但不限于此。例如，本公开的实施例提供的移位寄存器电路RS中的一个或多个薄膜晶体管也可以采用N型晶体管，只需将选定类型的薄膜晶体管的各极参照本公开的实施例中的相应薄膜晶体管的各极相应连接，并且使相应的电压端提供对应的高电平电压或低电平电压即可。
在本公开的实施例中，输入子电路10、去噪控制子电路20、去噪子电路30和输出子电路40的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
另外，在本公开的实施例中，电容(例如图11中的第一电容C1、第二 电容C2、第三电容C3、和第四电容C4)可以是通过工艺制程单独制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。电容也可以是晶体管之间的寄生电容，或者通过晶体管本身与其他器件、线路来实现，又或者利用电路自身线路之间的寄生电容来实现。
基于上述实施例所述的移位寄存器电路RS的结构，本公开的一些实施例提供了一种移位寄存器电路RS的驱动方法。
如图10和图12所示，一行栅线的驱动过程包括输入阶段P1、输出阶段P2和保持阶段P3。
在移位寄存器电路RS包括输入子电路10、去噪控制子电路20、去噪子电路30和输出子电路40的情况下，在输入阶段P1，输入子电路10控制级联信号输出端GP的电压为第一控制电压，使得去噪控制子电路20将去噪子电路30开启，其中，第一控制电压是指级联信号输出端GP通过对去噪控制子电路20的控制可以将去噪电路30打开的电压，例如，第一控制电压与第二电压端输出的电压值相等，使得去噪控制子电路20控制第一去噪控制节点PD-ox的电压为令去噪电路30打开的电压，以将去噪电路30打开。同时，输入子电路10还向输出子电路40传输开启信号。例如，输入子电路10在第三时钟信号端CK3的信号的控制下，写入输入信号端Iput的信号，根据写入的信号端Iput的信号，将输出子电路40开启。
在输出阶段P2，输入子电路10控制级联信号输出端GP的电压为第二控制电压，使得去噪控制子电路20将去噪子电路30关闭。其中，第二控制电压是指级联信号输出端GP通过对去噪控制子电路20的控制可以将去噪电路30关闭的电压，例如，第二控制电压与第一电压端输出的电压值相等，使得去噪控制子电路20控制第一去噪控制节点PD-ox的电压为令去噪电路30关闭的电压。并且，输入子电路10继续，向输出子电路40传输开启信号。
示例性地，在输出阶段，输出子电路40在该开启信号的控制下，可以将第二电压端VDD或第五时钟信号端CK2(图10中示出了输出子电路40与第五时钟信号端CK2耦接的情况)的信号传输至扫描信号输出端Oput，以对与扫描信号输出端Oput耦接的栅线进行扫描。
在保持阶段P3，去噪控制子电路20响应于第一时钟信号端CK1的信号，根据第一电压端VSS的电压和第二时钟信号端CB1的信号生成交变电压信号，并将生成的交变电压信号整流并输出至第一去噪控制节点PD-ox，使第一去噪控制节点PD-ox的电压保持为令去噪子电路30开启的电压；去噪子电路 30在第一去噪控制节点PD-ox的电压的控制下持续开启，对扫描信号输出端Oput去噪。
示例性的，以下结合图12对图11所示的移位寄存器电路RS在一行栅线的驱动过程中的具体工作过程进行详细地说明。在下面的描述中，以移位寄存器电路RS中的各个晶体管为P型晶体管(不考虑晶体管的阈值电压的影响)，第一电压端VSS所传输的电压为低电平电压，第二电压端VDD所传输的电压为高电平电压为例进行说明。
此外，在下面的描述中，以第十五晶体管T15的控制极耦接第三节点n3，第十五晶体管T15的第一极耦接第五时钟信号端CK2为例进行说明。在一些其它的实施例中，第十五晶体管T15的控制极和第一极也可耦接其它的节点或信号端，例如，第十五晶体管T15的控制极耦接级联信号输出端GP，第十五晶体管T15的第一极耦接第二电压端VDD。
如图12所示，一行栅线的驱动过程至少包括输入阶段P1、输出阶段P2和保持阶段P3。其中，保持阶段P3包括至少包括第一保持时段P31和第二保持时段P32。
示例性的，在下面的描述中，“0”表示低电平，“1”表示高电平。
在输入阶段P1，Iput＝0，CK1＝0，CB1＝1，CK2＝0，CK3＝0，CB3＝1。
在此情况下，第七晶体管T7在第三时钟信号端CK3的低电平信号的控制下打开，输入信号端Iput输出低电平信号至第一节点n1；第八晶体管T8在第一节点n1的低电平电压的控制下打开，第九晶体管T9在第三时钟信号端CK3的低电平信号的控制下打开，因此第二节点n2的电压为低电平电压。
第十晶体管T10在第二节点n2的低电平电压的控制下打开，第二电压端VDD的高电平电压VDD经第十晶体管T10传输至级联信号输出端GP；第十二晶体管T12在第一电压端VSS的控制下打开，将第一节点n1的低电平电压传输至第三节点n3以及第十一晶体管T11，第十一晶体管T11打开，从而第十一晶体管T11将第四时钟信号端CB3的高电平信号传输至级联信号输出端GP；因此级联信号输出端GP的电压为高电平电压VDD。
此时，第四电容C4充电，其与第三节点n3耦接的一端的电压为低电平电压，其与第十一晶体管T11耦接的一端的电压为高电平电压，实现了对输入信号端Iput所传输的信号的写入。
第三晶体管T3和第四晶体管T4在级联信号输出端GP的高电平电压的控制下均关闭。
第一晶体管T1在第一时钟信号端CK1输出的低电平信号的控制下 打开，第二去噪控制节点PD-ox-i的电压为低电平电压VSS，第二晶体管T2在第二去噪控制节点PD-ox-i的低电平电压VSS的控制下打开，第一去噪控制节点PD-ox的电压为低电平电压VSS；从而第六晶体管T6打开，扫描信号输出端Oput的电压为低电平电压VSS，实现了去噪子电路30对扫描信号输出端Oput的去噪。
此外，第十四晶体管T14在第二节点n2的低电平电压VSS的控制下打开，第十四晶体管T14将其第一极耦接的第二电压端VDD的高电平电压传输至第四节点n4，此时第十三晶体管T13在第四时钟信号端CB3的高电平信号的控制下关闭，从而第四节点n4的电压为高电平电压VDD。
第十五晶体管T15在第三节点n3的低电平电压的控制下打开，第五时钟信号端CK2输出的低电平电压经第十五晶体管T15传输至扫描信号输出端Oput，使得扫描信号输出端Oput不输出扫描信号。
在输出阶段P2，Iput＝1，CK1＝1，CB1＝0，CK2＝1，CK3＝1，CB3＝0。
在此情况下，第七晶体管T7在第三时钟信号端CK3的高电平信号的控制下关闭，第一节点n1的电压仍然为低电平电压；第八晶体管T8在第一节点n1的低电平电压的控制下打开，第三时钟信号端CK3的高电平信号经第八晶体管T8传输至第二节点n2，第九晶体管T9在第三时钟信号端CK3的高电平信号的控制下关闭，因此第二节点n2的电压为高电平电压。
第十晶体管T10在第二节点n2的高电平电压的控制下关闭；第十二晶体管T12在第一电压端VSS的控制下打开，将第一节点n1的低电平电压传输至第三节点n3以及第十一晶体管T11，第十一晶体管T11打开，从而第十一晶体管T11将第四时钟信号端CB3的低电平信号传输至级联信号输出端GP；因此级联信号输出端GP的电压为低电平电压。
此时，第四电容C4的与第十一晶体管T11耦接的一端的电压为低电平电压，假设第四时钟信号端CB3的低电平信号的电压为VSS，高电平信号的电压为VDD，则第四电容C4的与第十一晶体管T11耦接的一端的电压，由输入阶段P1的VDD下降为VSS，电压下降量为VDD-VSS。由于第四电容C4的电容自举效应，因此与第四电容C4另一端耦接的第三节点n3的电压被进一步拉低，拉低量为VDD-VSS，第三节点n3的电压由输入阶段P1的VSS下降至2VSS-VDD。
第十五晶体管T15在第三节点n3的低电平电压的控制下打开，第五时钟信号端CK2输出的高电平电压经第十五晶体管T15传输至扫描信号 输出端Oput，使得扫描信号输出端Oput输出扫描信号，实现对栅线的扫描。
第三晶体管T3和第四晶体管T4在级联信号输出端GP的低电平电压的控制下均打开，则第二信号端CN的信号经第三晶体管T3传输至第二去噪控制节点PD-ox-i，经第四晶体管T4传输至第一去噪控制节点PD-ox。由于第二信号端CN为第二电压端VDD或者第二节点n2(第二节点n2在输出阶段P2的电压为高电平电压)，因此第二去噪控制节点PD-ox-i和第一去噪控制节点PD-ox的电压均为高电平电压。从而第六晶体管T6关闭，不影响扫描信号输出端Oput输出扫描信号。
此时，第一晶体管T1在第一时钟信号端CK1输出的高电平信号的控制下关闭，第二晶体管T2在第二去噪控制节点PD-ox-i的高电平电压的控制下也关闭。
此外，第十四晶体管T14在第二节点n2的高电平电压的控制下关闭，第十三晶体管T13在第四时钟信号端CB3的低电平信号的控制下打开，因此第四节点n4的电压等于第一节点n1的电压，即，为低电平电压。
在保持阶段P3的第一保持时段P31，Iput＝1，CK1＝0，CB1＝1，CK2＝0，CK3＝0，CB3＝1。
在此情况下，第七晶体管T7在第三时钟信号端CK3的低电平信号的控制下打开，输入信号端Iput的高电平信号经第七晶体管T7传输至第一节点n1，使第一节点n1的电压变为高电平电压；第八晶体管T8在第一节点n1的高电平电压的控制下关闭；第九晶体管T9在第三时钟信号端CK3的低电平信号的控制下打开，第一信号端VSS的低电平信号VSS经第九晶体管T9传输至第二节点n2，使第二节点n2的电压为低电平电压VSS。
第十晶体管T10在第二节点n2的低电平电压的控制下打开，第二电压端VDD的高电平电压经第十晶体管T10传输至级联信号输出端GP；第十二晶体管T12在第一电压端VSS的控制下打开，将第一节点n1的高电平电压传输至第三节点n3以及第十一晶体管T11，第十一晶体管T11关闭；因此级联信号输出端GP的电压为高电平电压。
此时，第三晶体管T3和第四晶体管T4在级联信号输出端GP的高电平电压的控制下均关闭。
第一晶体管T1在第一时钟信号端CK1输出的低电平信号的控制下打开，则第二去噪控制节点PD-ox-i的电压为低电平电压VSS。第一电容C1的与第二去噪控制节点PD-ox-i连接的一端的电压为低电平电压 VSS，第一电容C1的与第二时钟信号端CB1连接的一端的电压为第二时钟信号端CB1的高电平信号的电压，假设第二时钟信号端CB1输出的高电平信号的电压为高电平电压VDD，则第一电容C1的与第二时钟信号端CB1连接的一端的电压为高电平电压VDD。
第二晶体管T2在第二去噪控制节点PD-ox-i的低电平电压VSS的控制下打开，第一去噪控制节点PD-ox的电压为低电平电压VSS；从而第六晶体管T6打开，扫描信号输出端Oput的电压为低电平电压VSS，实现了去噪子电路30对扫描信号输出端Oput的去噪。
此外，第十四晶体管T14在第二节点n2的低电平电压VSS的控制下打开，第十四晶体管T14将其第一极耦接的第二电压端VDD的高电平电压VDD传输至第四节点n4，此时第十三晶体管T13在第四时钟信号端CB3的高电平信号的控制下关闭，从而第四节点n4的电压为高电平电压VDD。
第十五晶体管T15在第三节点n3的高电平电压的控制下关闭。
在保持阶段P3的第二保持阶段P32，Iput＝1，CK1＝1，CB1＝0，CK2＝1，CK3＝1，CB3＝0。
在此情况下，第七晶体管T7在第三时钟信号端CK3的高电平信号的控制下关闭，第一节点n1的电压仍为高电平电压；第八晶体管T8在第一节点n1的高电平电压的控制下仍关闭；第九晶体管T9在第三时钟信号端CK3的高电平信号的控制下关闭，第二节点n2的电压仍为低电平电压。
第十晶体管T10在第二节点n2的低电平电压的控制下打开，第二电压端VDD的高电平电压经第十晶体管T10传输至级联信号输出端GP；第十二晶体管T12在第一电压端VSS的控制下打开，将第一节点n1的高电平电压传输至第三节点n3以及第十一晶体管T11，第十一晶体管T11关闭；因此级联信号输出端GP的电压为高电平电压。
此时，第三晶体管T3和第四晶体管T4在级联信号输出端GP的高电平电压的控制下均关闭。
第一晶体管T1在第一时钟信号端CK1输出的高电平信号的控制下关闭，第二去噪控制节点PD-ox-i处于浮空状态。第一电容C1的与第二时钟信号端CB1连接的一端的电压为第二时钟信号端CB1的低电平信号的电压，即为低电平电压VSS，则第一电容C1的与第二时钟信号端CB1连接的一端的电压由第一保持时段P31的VDD下降为低电平电压VSS，电压下降量为VSS-VDD。
由于第一电容C1的耦合作用，因此第二去噪控制节点PD-ox-i的电压发生偏移，偏移量为
Figure PCTCN2021089081-appb-000001
其中，C PD-ox-i为第二去噪控制节点PD-ox-i所连接的各器件(包括晶体管T1、T2、T3和电容C1)的总电容，C1为第一电容C1的电容，从而第二去噪控制节点PD-ox-i的电压由第一保持时段P31的VSS下降至
Figure PCTCN2021089081-appb-000002
此时，由于第一去噪控制节点PD-ox的电压为低电平电压VSS，第二去噪控制节点PD-ox-i的电压为
Figure PCTCN2021089081-appb-000003
因此第二晶体管T2打开，约一半的电荷由第一去噪控制节点PD-ox流入第二去噪控制节点PD-ox-i。即，第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i进行电压的均分，从而第一去噪控制节点PD-ox的电压变为
Figure PCTCN2021089081-appb-000004
也就是说，第一去噪控制节点PD-ox的电压被由第一保持时段P31的VSS下拉至
Figure PCTCN2021089081-appb-000005
在此之后，由于第一时钟信号端CK1和第二时钟信号端CB1的信号交替为高电平信号和低电平信号，即在保持阶段P3，第一保持时段P31和第二保持时段P32交替进行，因此第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i的会进行多次耦合，电压进行多次平均，最终第一去噪控制节点PD-ox的电压稳定在某一电压附近，第一去噪控制节点PD-ox的电压变化情况如图12中所示的波形，从而使得第六晶体管T6在保持阶段P3持续开启，对扫描信号输出端Oput进行持续去噪。
例如，在C1足够大，认为C PD-ox-i≈C1(可以理解为C1在C PD-ox-i中的占比较大，例如占比大于或等于90％)的情况下，上面的推导过程所涉及的数值可参见下面的描述。
由于第一电容C1的耦合作用，因此第二去噪控制节点PD-ox-i的电 压的偏移量为VSS-VDD，从而第二去噪控制节点PD-ox-i的电压由第一保持时段P31的VSS下降至VSS+(VSS-VDD)＝2VSS-VDD。
此时，由于第一去噪控制节点PD-ox的电压为低电平电压VSS，第二去噪控制节点PD-ox-i的电压为2VSS-VDD，因此第二晶体管T2打开，约一半的电荷由第一去噪控制节点PD-ox流入第二去噪控制节点PD-ox-i，从而第一去噪控制节点PD-ox的电压变为[(2VSS-VDD)+VSS]/2＝(3VSS-VDD)/2，即第一去噪控制节点PD-ox的电压被由第一保持时段P31的VSS下拉至(3VSS-VDD)/2。
在此之后，由于第一时钟信号端CK1和第二时钟信号端CB1的信号交替为高电平信号和低电平信号，即在保持阶段P3，第一保持时段P31和第二保持时段P32交替进行，因此第一去噪控制节点PD-ox和第二去噪控制节点PD-ox-i的会进行多次耦合，电压进行多次平均，最终第一去噪控制节点PD-ox的电压稳定在2VSS-VDD附近，从而使得第六晶体管T6在保持阶段P3持续开启，对扫描信号输出端Oput进行持续去噪。
此外，在第二保持时段P32，第十四晶体管T14在第二节点n2的低电平电压的控制下打开，第十四晶体管T14将其第一极耦接的第二电压端VDD的高电平电压VDD传输至第四节点n4，此时第十三晶体管T13在第四时钟信号端CB3的低电平信号的控制下打开，从而第四节点n4的电压为高电平电压VDD，这样通过第十三晶体管T13和第十四晶体管T14共同控制第二电压端VDD对第一节点n1充电，保持第一节点n1为高电平电压，保证第十一晶体管T11处于关闭状态。
第十五晶体管T15在第三节点n3的高电平电压的控制下关闭。
在另外一些实施例中，如图13和图14所示，对于移位寄存器电路RS中的输入子电路10所耦接的第三时钟信号端CK3和第四时钟信号端CB3为第一时钟信号端CK1和第二时钟信号端CB1的情况，该移位寄存器电路RS的驱动时序可如图15所示，电路具体驱动过程可参见前面的描述，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器电路，包括：去噪控制子电路和去噪子电路；
    所述去噪控制子电路与第一电压端、第一时钟信号端、第二时钟信号端和第一去噪控制节点耦接；
    所述去噪控制子电路被配置为，响应于所述第一时钟信号端的信号，根据所述第一电压端的电压和第二时钟信号端的信号生成交变电压信号，并将所述交变电压信号整流后输出至所述第一去噪控制节点，使所述第一去噪控制节点的电压保持为令所述去噪子电路开启的电压；所述去噪子电路与所述第一去噪控制节点和扫描信号输出端耦接；
    所述去噪子电路被配置为，响应于所述第一去噪控制节点的电压为令所述去噪子电路开启的电压，对所述扫描信号输出端去噪。
  2. 根据权利要求1所述的移位寄存器电路，其中，
    所述去噪控制子电路包括：
    第一开启控制子电路，所述第一开启控制子电路与所述第一时钟信号端、所述第二时钟信号端、所述第一电压端以及第二去噪控制节点耦接，被配置为周期性地响应于所述第一时钟信号端的信号，将所述第一电压端的电压输出至所述第二去噪控制节点，并根据所述第二时钟信号端的信号，拉动所述第二去噪控制节点的电压，使得所述第二去噪控制节点提供交变电压信号；
    第二开启控制子电路，所述第二开启控制子电路与所述第一去噪控制节点和所述第二去噪控制节点耦接，被配置为响应于所述第二去噪控制节点提供的交变电压信号，将所述交变电压信号整流后输出至所述第一去噪控制节点，使所述第一去噪控制节点的电压保持为令所述去噪子电路开启的电压。
  3. 根据权利要求1或2所述的移位寄存器电路，其中，
    所述第一开启控制子电路包括：
    第一晶体管，所述第一晶体管的控制极与所述第一时钟信号端耦接，所述第一晶体管的第一极与所述第一电压端耦接，所述第一晶体管的第二极与所述第二去噪控制节点耦接；
    第一电容，所述第一电容的第一端与所述第二时钟信号端耦接，所述第一电容的第二端与所述第二去噪控制节点耦接；
    和/或，
    所述第二开启控制子电路包括：
    第二晶体管，所述第二晶体管的控制极与所述第二去噪控制节点耦接，所述第二晶体管的第一极与所述第一去噪控制节点耦接，所述第二晶体管的 第二极与所述第二去噪控制节点耦接；
    第二电容，所述第二电容的第一端与所述第一信号端耦接，所述第二电容的第二端与所述第一去噪控制节点耦接。
  4. 根据权利要求1至3中的任一项所述的移位寄存器电路，其中，
    所述去噪控制子电路还与级联信号输出端耦接，还被配置为，响应于所述级联信号输出端的电压，将第二信号端的信号传输至所述第一去噪控制节点，以控制所述去噪子电路关闭。
  5. 根据权利要求4所述的移位寄存器电路，其中，
    所述移位寄存器电路还包括：
    第三晶体管，所述第三晶体管的控制极与所述级联信号输出端耦接，所述第三晶体管的第一极与所述第二信号端耦接，所述第三晶体管的第二极与所述第二去噪控制节点耦接；
    第四晶体管，所述第四晶体管的控制极与所述级联信号输出端耦接，所述第四晶体管的第一极与所述第二信号端耦接，所述第四晶体管的第二极与所述第一去噪控制节点耦接。
  6. 根据权利要求3所述的移位寄存器电路，其中，
    所述第一开启控制子电路还包括：
    第五晶体管，所述第一电容的第一端通过所述第五晶体管与所述第二时钟信号端耦接；
    所述第五晶体管的控制极与所述扫描信号输出端耦接，所述第五晶体管的第一极与所述第二时钟信号端耦接，所述第五晶体管的第二极与所述第一电容的第一端耦接。
  7. 根据权利要求2所述的移位寄存器电路，其中，
    所述第一信号端为所述第一电压端或者所述第一时钟信号端。
  8. 根据权利要求1至7中的任一项所述的移位寄存器电路，其中，
    所述去噪子电路包括：
    第六晶体管，所述第六晶体管的控制极与所述第一去噪控制节点耦接，所述第六晶体管的第一极与所述第一电压端耦接，所述第六晶体管的第二极与所述扫描信号输出端耦接。
  9. 根据权利要求1至8中的任一项所述的移位寄存器电路，其中，
    所述移位寄存器电路还包括：
    输入子电路，所述输入子电路与级联信号输出端和所述输出子电路耦接，被配置为控制所述级联信号输出端的电压，还被配置为向所述输出子电路传 输开启信号；
    输出子电路，所述输出子电路与第二电压端或第五时钟信号端耦接，所述输出子电路还与所述扫描信号输出端耦接，被配置为，响应于所述输入子电路所传输的开启信号，将所述第二电压端或所述第五时钟信号端的信号传输至所述扫描信号输出端。
  10. 根据权利要求9所述的移位寄存器电路，其中，
    所述输入子电路包括：
    第七晶体管，所述第七晶体管的控制极与第三时钟信号端耦接，所述第七晶体管的第一极与输入信号端耦接，所述第七晶体管的第二极与第一节点耦接；
    第八晶体管，所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管的第一极与所述第三时钟信号端耦接，所述第八晶体管的第二极与第二节点耦接；
    第九晶体管，所述第九晶体管的控制极与所述第三时钟信号端耦接，所述第九晶体管的第一极与所述第一电压端耦接，所述第九晶体管的第二极与所述第二节点耦接；
    第十晶体管，所述第十晶体管的控制极与所述第二节点耦接，所述第十晶体管的第一极与所述第二电压端耦接，所述第十晶体管的第二极与所述级联信号输出端耦接；
    第三电容，所述第三电容的第一端与所述第二节点耦接，所述第三电容的第二端与所述第十晶体管的第一极和所述第二电压端耦接；
    第十一晶体管，所述第十一晶体管的控制极与第三节点耦接，所述第十一晶体管的第一极与第四时钟信号端耦接，所述第十一晶体管的第二极与所述级联信号输出端耦接；
    第四电容，所述第四电容的第一端与所述第三节点耦接，所述第四电容的第二端与所述第十一晶体管的第二极和所述级联信号输出端耦接；
    第十二晶体管，所述第十二晶体管的控制极与所述第一电压端耦接，所述第十二晶体管的第一极与所述第三节点耦接，所述第十二晶体管的第二极与所述第一节点耦接；
    第十三晶体管，所述第十三晶体管的控制极与所述第四时钟信号端耦接，所述第十三晶体管的第一极与所述第一节点耦接，所述第十三晶体管的第二极与第四节点耦接；
    第十四晶体管，所述第十四晶体管的控制极与所述第二节点耦接，所述 第十四晶体管的第一极与所述第二电压端耦接，所述第十四晶体管的第二极与所述第四节点耦接；
    所述输出子电路包括：
    第十五晶体管，所述第十五晶体管的控制极与所述级联信号输出端或所述第三节点耦接，所述第十五晶体管的第一极与所述第二电压端或所述第五时钟信号端耦接，所述第十五晶体管的第二极与所述扫描信号输出端耦接。
  11. 根据权利要求4或5所述的移位寄存器电路，其中，
    所述第二信号端为所述第二电压端，或者所述第二信号端与所述第二节点耦接。
  12. 根据权利要求10所述的移位寄存器电路，其中，
    所述第三时钟信号端与所述第一时钟信号端为相同的信号端，所述第四时钟信号端与所述第二时钟信号端为相同的信号端。
  13. 一种移位寄存器电路，包括：
    第一晶体管，所述第一晶体管的控制极与第一时钟信号端耦接，所述第一晶体管的第一极与第一电压端耦接，所述第一晶体管的第二极与第二去噪控制节点耦接；
    第一电容，所述第一电容的第一端与第二时钟信号端耦接，所述第一电容的第二端与所述第二去噪控制节点耦接；
    第二晶体管，所述第二晶体管的控制极与所述第二去噪控制节点耦接，所述第二晶体管的第一极与第一去噪控制节点耦接，所述第二晶体管的第二极与所述第二去噪控制节点耦接；
    第二电容，所述第二电容的第一端与第一信号端耦接，所述第二电容的第二端与所述第一去噪控制节点耦接；
    第六晶体管，所述第六晶体管的控制极与所述第一去噪控制节点耦接，所述第六晶体管的第一极与所述第一电压端耦接，所述第六晶体管的第二极与扫描信号输出端耦接。
  14. 根据权利要求13所述的移位寄存器电路，还包括：
    第三晶体管，所述第三晶体管的控制极与级联信号输出端耦接，所述第三晶体管的第一极与第二信号端耦接，所述第三晶体管的第二极与所述第二去噪控制节点耦接；
    第四晶体管，所述第四晶体管的控制极与所述级联信号输出端耦接，所述第四晶体管的第一极与所述第二信号端耦接，所述第四晶体管的第二极与所述第一去噪控制节点耦接。
  15. 一种栅极驱动电路，包括多个级联的移位寄存器电路，其中，
    所述移位寄存器电路为如权利要求1至14中的任一项所述的移位寄存器电路。
  16. 一种显示装置，包括：
    多条栅线；
    如权利要求15所述的栅极驱动电路；
    其中，所述栅极驱动电路中的每个移位寄存器电路与至少一条栅线耦接。
  17. 根据权利要求16所述的显示装置，其中，
    所述栅极驱动电路中的每个移位寄存器电路的扫描信号输出端与至少一条栅线耦接。
  18. 根据权利要求16所述的显示装置，其中，
    所述多条栅线包括多条第一栅线和多条第二栅线；
    所述栅极驱动电路中的每个移位寄存器电路的扫描信号输出端与至少一条第一栅线耦接，并且，所述栅极驱动电路中的每个移位寄存器电路的级联信号输出端与至少一条第二栅线耦接。
  19. 一种如权利要求1至14中的任一项所述移位寄存器电路的驱动方法，包括：
    在保持阶段：
    所述移位寄存器电路的去噪控制子电路响应于第一时钟信号端的信号，根据第一电压端的电压和第二时钟信号端的信号生成交变电压信号，并将生成的所述交变电压信号整流并输出至第一去噪控制节点，使所述第一去噪控制节点的电压保持为令去噪子电路开启的电压；
    所述去噪子电路响应于所述第一去噪控制节点的电压为令所述去噪子电路开启的电压，对扫描信号输出端去噪。
  20. 根据权利要求19所述的驱动方法，还包括：
    在所述移位寄存器电路还包括输入子电路和输出子电路的情况下，
    在输入阶段：
    所述输入子电路响应于第三时钟信号端的信号，控制级联信号输出端的电压为第一控制电压，使得所述去噪控制子电路将所述去噪子电路开启；并且向所述输出子电路传输开启信号；
    在输出阶段：
    所述输入子电路控制级联信号输出端的电压为第二控制电压，使得所述去噪控制子电路将所述去噪子电路关闭；并且，继续向所述输出子电路传输 开启信号。
PCT/CN2021/089081 2020-04-29 2021-04-22 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置 WO2021218779A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP21796531.8A EP4068263A4 (en) 2020-04-29 2021-04-22 SHIFT REGISTER CIRCUIT AND METHODS OF DRIVE THEREOF, AND GATE DRIVE CIRCUIT AND INDICATOR
US17/779,845 US12002407B2 (en) 2020-04-29 2021-04-22 Shift register circuit including denoising control sub-circuit and method for driving same, and gate driving circuit and display apparatus
KR1020227017500A KR20230002265A (ko) 2020-04-29 2021-04-22 시프트 레지스터 회로 및 그 구동 방법, 게이트 구동 회로, 디스플레이 장치
JP2022540526A JP2023522803A (ja) 2020-04-29 2021-04-22 シフトレジスタ回路及びその駆動方法、ゲート駆動回路、表示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010356184.0 2020-04-29
CN202010356184.0A CN111415624B (zh) 2020-04-29 2020-04-29 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置

Publications (1)

Publication Number Publication Date
WO2021218779A1 true WO2021218779A1 (zh) 2021-11-04

Family

ID=71495111

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/089081 WO2021218779A1 (zh) 2020-04-29 2021-04-22 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置

Country Status (6)

Country Link
US (1) US12002407B2 (zh)
EP (1) EP4068263A4 (zh)
JP (1) JP2023522803A (zh)
KR (1) KR20230002265A (zh)
CN (1) CN111415624B (zh)
WO (1) WO2021218779A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111415624B (zh) 2020-04-29 2021-05-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
US11922877B2 (en) * 2020-07-22 2024-03-05 Sharp Kabushiki Kaisha Display device enabling both high-frequency drive and low-frequency drive
CN114203081B (zh) * 2020-09-02 2023-12-22 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
CN114255701B (zh) 2020-09-25 2022-12-20 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、驱动电路和显示装置
EP4131243A4 (en) * 2021-03-19 2023-07-26 BOE Technology Group Co., Ltd. SHIFT REGISTER UNIT AND DRIVE METHOD, SO GATE DRIVER CIRCUIT AND DISPLAY DEVICE
US20230351970A1 (en) * 2021-03-24 2023-11-02 Boe Technology Group Co., Ltd. Display Substrate and Preparation Method thereof, and Display Apparatus
CN115798413B (zh) * 2021-03-24 2023-09-22 京东方科技集团股份有限公司 显示基板和显示装置
WO2022246756A1 (zh) * 2021-05-27 2022-12-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113436580B (zh) 2021-06-18 2022-06-10 武汉华星光电半导体显示技术有限公司 栅极驱动电路及显示面板
CN113920937B (zh) * 2021-07-09 2022-09-09 北京京东方技术开发有限公司 显示基板及显示装置
WO2023028749A1 (zh) * 2021-08-30 2023-03-09 京东方科技集团股份有限公司 显示面板及其移位寄存器单元的驱动方法、移位寄存器
CN115394235A (zh) * 2022-10-13 2022-11-25 武汉天马微电子有限公司 一种移位寄存器、显示面板及显示装置

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101364392A (zh) * 2007-08-06 2009-02-11 三星电子株式会社 栅极驱动电路和具有该栅极驱动电路的显示装置
US20100164915A1 (en) * 2008-12-29 2010-07-01 Hak-Gyu Kim Gate driving circuit and display device having the gate driving circuit
CN102654969A (zh) * 2011-12-31 2012-09-05 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
US20140346520A1 (en) * 2013-05-27 2014-11-27 Samsung Display Co., Ltd. Gate driver and display apparatus having the same
CN105810166A (zh) * 2016-05-23 2016-07-27 信利（惠州）智能显示有限公司 移位寄存器单元电路、移位寄存器及其液晶显示器
CN106157874A (zh) * 2016-09-12 2016-11-23 合肥鑫晟光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106297624A (zh) * 2015-06-11 2017-01-04 南京瀚宇彩欣科技有限责任公司 移位寄存器和显示装置
US20180357965A1 (en) * 2017-06-13 2018-12-13 Samsung Display Co., Ltd. Scan driver and display apparatus having the same
US20180366067A1 (en) * 2017-06-15 2018-12-20 Lg Display Co., Ltd. Shift register and display apparatus including the same
CN111048032A (zh) * 2020-01-14 2020-04-21 信利(仁寿)高端显示科技有限公司 一种7t2c结构栅极驱动电路的驱动方法
CN111415624A (zh) * 2020-04-29 2020-07-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285168A (ja) * 2004-03-29 2005-10-13 Alps Electric Co Ltd シフトレジスタ及びそれを用いた液晶駆動回路
TWI278183B (en) * 2005-07-01 2007-04-01 Au Optronics Corp Shift register and level shifter thereof
EP2189987B1 (en) 2007-09-12 2013-02-13 Sharp Kabushiki Kaisha Shift register
KR101641312B1 (ko) 2009-12-18 2016-07-21 삼성디스플레이 주식회사 표시 패널
CN102646387B (zh) 2011-05-19 2014-09-17 京东方科技集团股份有限公司 移位寄存器及行扫描驱动电路
KR102050581B1 (ko) * 2013-06-21 2019-12-02 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 유기전계발광 표시장치
KR20150016706A (ko) * 2013-08-05 2015-02-13 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 유기전계발광 표시장치
US10223975B2 (en) 2013-10-18 2019-03-05 Apple Inc. Organic light emitting diode displays with improved driver circuitry
CN104299590B (zh) 2014-10-30 2016-08-24 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN104318904B (zh) * 2014-11-20 2017-08-01 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器、显示装置
CN104766580B (zh) * 2015-04-23 2017-08-01 合肥京东方光电科技有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN105118418B (zh) 2015-09-25 2017-08-11 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
KR102519822B1 (ko) 2015-12-31 2023-04-12 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN105609058B (zh) * 2016-01-04 2018-09-04 京东方科技集团股份有限公司 背光源及显示装置
CN105957470B (zh) * 2016-07-07 2019-01-11 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示器件
CN108231032B (zh) 2018-02-26 2021-01-26 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置
CN108389542B (zh) 2018-03-19 2021-01-22 京东方科技集团股份有限公司 一种移位寄存器单元及其驱动方法、栅极驱动电路
CN108564930B (zh) 2018-05-04 2020-03-13 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN111243517B (zh) 2018-05-07 2021-09-07 上海天马微电子有限公司 发光控制信号生成电路、显示面板和显示装置
CN108806630B (zh) * 2018-07-03 2021-10-15 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN108682398B (zh) * 2018-08-08 2020-05-29 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN108962330B (zh) * 2018-08-21 2020-12-11 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110176204B (zh) * 2018-08-24 2021-01-26 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110972504B (zh) * 2019-01-04 2022-05-13 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路、显示装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101364392A (zh) * 2007-08-06 2009-02-11 三星电子株式会社 栅极驱动电路和具有该栅极驱动电路的显示装置
US20100164915A1 (en) * 2008-12-29 2010-07-01 Hak-Gyu Kim Gate driving circuit and display device having the gate driving circuit
CN102654969A (zh) * 2011-12-31 2012-09-05 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
US20140346520A1 (en) * 2013-05-27 2014-11-27 Samsung Display Co., Ltd. Gate driver and display apparatus having the same
CN106297624A (zh) * 2015-06-11 2017-01-04 南京瀚宇彩欣科技有限责任公司 移位寄存器和显示装置
CN105810166A (zh) * 2016-05-23 2016-07-27 信利（惠州）智能显示有限公司 移位寄存器单元电路、移位寄存器及其液晶显示器
CN106157874A (zh) * 2016-09-12 2016-11-23 合肥鑫晟光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US20180357965A1 (en) * 2017-06-13 2018-12-13 Samsung Display Co., Ltd. Scan driver and display apparatus having the same
US20180366067A1 (en) * 2017-06-15 2018-12-20 Lg Display Co., Ltd. Shift register and display apparatus including the same
CN111048032A (zh) * 2020-01-14 2020-04-21 信利(仁寿)高端显示科技有限公司 一种7t2c结构栅极驱动电路的驱动方法
CN111415624A (zh) * 2020-04-29 2020-07-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置

Also Published As

Publication number Publication date
EP4068263A4 (en) 2023-04-26
CN111415624B (zh) 2021-05-14
KR20230002265A (ko) 2023-01-05
EP4068263A1 (en) 2022-10-05
US12002407B2 (en) 2024-06-04
JP2023522803A (ja) 2023-06-01
US20230005415A1 (en) 2023-01-05
CN111415624A (zh) 2020-07-14

Similar Documents

Publication Publication Date Title
WO2021218779A1 (zh) 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
WO2021258915A1 (zh) 像素驱动电路及其驱动方法、显示面板及显示装置
WO2021218918A1 (zh) 像素驱动电路及其驱动方法、显示基板、显示装置
US20210358365A1 (en) Shift Register Unit and Driving Method Thereof, Gate Driving Circuit, and Display Device
US10950320B2 (en) Shift register unit, gate driving circuit, display device and driving method
WO2021223579A1 (zh) 像素驱动电路及驱动方法、移位寄存器电路、显示装置
WO2020228628A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2023006100A1 (zh) 像素电路及其驱动方法、显示装置
US10657917B2 (en) Shift register and display device including same
US10089949B2 (en) Display device
JP5538765B2 (ja) 液晶表示装置
WO2022222408A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2022227453A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2019010956A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2021174675A1 (zh) Goa电路、tft基板、显示装置及电子设备
WO2022183489A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
WO2021179329A1 (zh) 移位寄存器、驱动方法、栅极驱动电路及显示装置
WO2021128470A1 (zh) 像素驱动电路及其驱动方法、显示面板
WO2022198427A1 (zh) 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
US11900883B2 (en) Shift register unit, method for driving shift register unit, gate driving circuit, and display device
KR20150002250A (ko) 게이트 구동부 및 이를 포함하는 평판표시장치
US20240221850A1 (en) Shift register and driving method therefor, gate driver circuit, and display apparatus
WO2023184279A1 (zh) 显示装置及其驱动方法
US11763724B2 (en) Shift register unit and method for driving shift register unit, gate drive circuit, and display device
WO2024119503A1 (zh) 像素电路及其驱动方法、阵列基板、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21796531

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022540526

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2021796531

Country of ref document: EP

Effective date: 20220628

NENP Non-entry into the national phase

Ref country code: DE