WO2022198427A1 - 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器电路及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2022198427A1
WO2022198427A1 PCT/CN2021/082241 CN2021082241W WO2022198427A1 WO 2022198427 A1 WO2022198427 A1 WO 2022198427A1 CN 2021082241 W CN2021082241 W CN 2021082241W WO 2022198427 A1 WO2022198427 A1 WO 2022198427A1
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WIPO (PCT)
Prior art keywords
voltage
control
terminal
clock signal
node
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PCT/CN2021/082241
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English (en)
French (fr)
Inventor
商广良
卢江楠
韩龙
王丽
刘利宾
殷新社
史世明
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000551.6A priority Critical patent/CN115668342A/zh
Priority to GB2217256.3A priority patent/GB2609869A/en
Priority to US17/765,045 priority patent/US20240071312A1/en
Priority to PCT/CN2021/082241 priority patent/WO2022198427A1/zh
Publication of WO2022198427A1 publication Critical patent/WO2022198427A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register circuit and a driving method thereof, a gate driving circuit, and a display device.
  • the pixel driving circuit in the display device receives the data signal, and the pixel voltage carried by the data signal can be used to control the light-emitting brightness of each pixel. Due to the leakage phenomenon of the pixel driving circuit, the pixel voltage will change with time.
  • a shift register circuit including a first control subcircuit and a first output subcircuit.
  • the first control sub-circuit is coupled to the first clock signal terminal, the second clock signal terminal and the first node; the first control sub-circuit is configured to be at the first DC voltage from the first clock signal terminal signal, and under the influence of the second DC voltage signal from the second clock signal terminal, the voltage of the first node is adjusted to the turn-on voltage; and, under the influence of the first clock signal from the first clock signal terminal, and Under the influence of the second clock signal from the second clock signal terminal, the voltage of the first node is maintained at the turn-on voltage.
  • the first output sub-circuit is coupled to the first node, the first voltage terminal and the signal output terminal; the first output sub-circuit is configured to be turned on under the control of the turn-on voltage of the first node, and the output from the first node is The first voltage signal of the first voltage terminal is transmitted to the signal output terminal.
  • the shift register circuit further includes a second control subcircuit and a second output subcircuit.
  • the second control sub-circuit is connected to the first node, the first voltage terminal, the first control signal terminal, the second control signal terminal, the fourth clock signal terminal, the second voltage terminal, the second node and the a first control subcircuit is coupled; the second control subcircuit is configured to, under the control of a first control signal from the first control signal terminal and a second control signal from the second control signal terminal, and Under the influence of the first control sub-circuit, the first voltage signal from the first voltage terminal, and the fourth clock signal from the fourth clock signal terminal, the voltage of the second node is adjusted to a turn-on voltage.
  • the second output sub-circuit is coupled to the second node, the second voltage terminal and the signal output terminal; the second output sub-circuit is configured to be under the control of the turn-on voltage of the second node Turn on, and transmit the second voltage signal from the second voltage terminal to the signal output terminal.
  • the first control subcircuit includes a holding unit and a first control unit.
  • the holding unit is coupled to the first clock signal terminal, the first node and the initial signal terminal; the holding unit is configured to, when the first DC voltage signal from the first clock signal terminal and from the first DC voltage signal Turning off under the influence of the initial voltage signal of the initial signal terminal; and turning on under the control of the first clock signal from the first clock signal terminal, keeping the voltage of the first node at the turn-on voltage.
  • the first control unit is coupled to the second clock signal terminal and the first node; the first control unit is configured to, under the influence of the second DC voltage signal from the second clock signal terminal, convert the The voltage of the first node is adjusted to a turn-on voltage; and, under the influence of the second clock signal from the second clock signal terminal, the voltage of the first node is adjusted.
  • the holding unit includes a first transistor, a control electrode of the first transistor is coupled to the first clock signal terminal, and a first electrode of the first transistor is coupled to the initial signal terminal connected, the second electrode of the first transistor is coupled to the first node.
  • the first control unit includes a first capacitor, a first end of the first capacitor is coupled to the second clock signal end, and a second end of the first capacitor is coupled to the first node.
  • the first control sub-circuit further includes a first anti-leakage unit coupled to the first voltage terminal, and the holding unit is connected to the first node through the first anti-leakage unit coupling; the first anti-leakage unit is configured to maintain the voltage of the first node under the control of a first voltage signal from the first voltage terminal.
  • the first anti-leakage unit includes an eleventh transistor, a control electrode of the eleventh transistor is coupled to the first voltage terminal, and a first electrode of the eleventh transistor is connected to the first voltage terminal.
  • the first node is coupled, and the second pole of the eleventh transistor is coupled to the holding unit.
  • the first control subcircuit further includes a second control unit coupled to the holding unit, the second control subcircuit, a fourth clock signal terminal and the second voltage terminal; the The second control unit is configured to, under the control of the fourth clock signal from the fourth clock signal terminal and the second control sub-circuit, transmit the second voltage signal from the second voltage terminal to the the holding unit.
  • the second control unit includes a second transistor and a third transistor.
  • control electrode of the second transistor is coupled to the second control sub-circuit, and the first electrode of the second transistor is coupled to the second voltage terminal.
  • the control electrode of the third transistor is coupled to the fourth clock signal terminal, the first electrode of the third transistor is coupled to the second electrode of the second transistor, and the second electrode of the third transistor coupled to the holding unit.
  • the second control subcircuit includes a third control unit, a fourth control unit, an adjustment unit, and a fifth control unit.
  • the third control unit is coupled to the first control sub-circuit, the first control signal terminal and the first voltage terminal; the third control unit is configured to Under the control of the first control signal of the terminal, the first voltage signal from the first voltage terminal is transmitted to the first control sub-circuit.
  • a fourth control unit is coupled to the third control unit, the fourth clock signal terminal and the third node; the fourth control unit is configured to, under the control of the third control unit The fourth clock signal at the fourth clock signal terminal is transmitted to the third node.
  • the adjustment unit is coupled to the third control unit and the third node; the adjustment unit is configured to adjust the voltage output by the third control unit according to the voltage of the third node.
  • a fifth control unit is coupled to the first node, the second node, the third node, the second voltage terminal and the second control signal terminal; the fifth control unit is configured to Under the control of the second control signal at the second control signal terminal, the voltage of the third node is transmitted to the second node; and, under the control of the voltage of the first node, the voltage from the first node is transmitted.
  • the second voltage signal of the two voltage terminals is transmitted to the second node.
  • the third control unit includes a fourth transistor and a fifth transistor.
  • the control electrode of the fourth transistor is coupled to the first control sub-circuit, the first electrode of the fourth transistor is coupled to the first control signal terminal, and the second electrode of the fourth transistor is coupled to the first control sub-circuit.
  • the control electrode of the fifth transistor is coupled to the first control signal terminal, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the first voltage terminal.
  • the first control subcircuit is coupled.
  • the fourth control unit includes a sixth transistor, the control electrode of the sixth transistor is coupled to the second electrode of the fourth transistor, and the first electrode of the sixth transistor is coupled to the fourth clock signal terminal connected, the second electrode of the sixth transistor is coupled to the third node.
  • the adjustment unit includes a second capacitor, a first end of the second capacitor is coupled to the third node, and a second end of the second capacitor is coupled to a second pole of the fourth transistor.
  • the fifth control unit includes a seventh transistor and an eighth transistor.
  • the control electrode of the seventh transistor is coupled to the second control signal terminal, the first electrode of the seventh transistor is coupled to the third node, and the second electrode of the seventh transistor is coupled to the third node.
  • the second node is coupled.
  • the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the second voltage terminal Node coupling.
  • the second control sub-circuit further includes a second leakage prevention unit coupled to the first voltage terminal, and the third control unit communicates with the first leakage prevention unit through the second leakage prevention unit.
  • Four control units are coupled; the second anti-leakage unit is configured to keep the fourth control unit turned on under the control of the first voltage signal from the first voltage terminal.
  • the second anti-leakage unit includes a twelfth transistor, a control electrode of the twelfth transistor is coupled to the first voltage terminal, and a first electrode of the twelfth transistor is connected to the first voltage terminal.
  • the fourth control unit is coupled, and the second pole of the twelfth transistor is coupled to the third control unit.
  • the first control signal terminal is a first clock signal terminal or a third clock signal terminal; and/or the second control signal terminal is a second clock signal terminal or a fourth clock signal terminal.
  • the first clock signal terminal is configured to output the first clock signal in the data refresh phase of one frame period, output the first DC voltage signal in the denoising sub-phase of the data retention phase of one frame period, and output the first DC voltage signal in the data refresh phase of one frame period.
  • the denoising enhancement sub-stage of the data retention stage outputs the first clock signal.
  • the second clock signal terminal is configured to output a second clock signal during the data refresh phase, output a second DC voltage signal during the denoising sub-phase of the data retention phase, and output a second DC voltage signal during the denoising phase of the data retention phase
  • the boost sub-stage outputs a second clock signal.
  • the third clock signal terminal is configured to output a third clock signal during the data refresh phase, and output a third DC voltage signal during the data retention phase.
  • the fourth clock signal terminal is configured to output a fourth clock signal during the data refresh phase, and output a fourth DC voltage signal during the data retention phase.
  • the first clock signal and the second clock signal are substantially inversion signals of each other, and the third clock signal and the fourth clock signal are substantially inversion signals of each other; the first clock signal and the fourth clock signal are substantially inversion signals of each other;
  • the DC voltage signal and the second DC voltage signal are both low-level signals, and the third DC voltage signal and the fourth DC voltage signal are both high-level signals.
  • the second output subcircuit includes a ninth transistor and a third capacitor.
  • the control electrode of the ninth transistor is coupled to the second node, the first electrode of the ninth transistor is coupled to the second voltage end, and the second electrode of the ninth transistor is coupled to the second node.
  • the signal output terminal is coupled.
  • the first terminal of the third capacitor is coupled to the second voltage terminal, and the second terminal of the third capacitor is coupled to the second node.
  • the first output sub-circuit includes a tenth transistor, a control electrode of the tenth transistor is coupled to the first node, and a first electrode of the tenth transistor is connected to the first voltage terminal is coupled, and the second pole of the tenth transistor is coupled to the signal output terminal.
  • a gate driving circuit which includes a plurality of shift register circuits as described in any of the above embodiments, and the plurality of shift register circuits are cascaded in sequence.
  • the gate driving circuit further includes three or four clock signal lines coupled to each shift register circuit of the gate driving circuit.
  • a display device comprising the gate driving circuit according to any of the above embodiments and a plurality of control signal lines, wherein each shift register circuit in the gate driving circuit is associated with at least one control signal line coupling.
  • a method for driving a shift register circuit is provided, which is applied to the shift register circuit according to any one of the above embodiments.
  • the driving method includes: a frame period includes a data holding phase, and the data holding phase It includes multiple denoising sub-stages and multiple denoising enhancement sub-stages that appear alternately.
  • the first control sub-circuit of the shift register circuit under the influence of the first DC voltage signal from the first clock signal terminal and the second DC voltage signal from the second clock signal terminal, controls The voltage of the first node is adjusted to the turn-on voltage.
  • the first control sub-circuit under the influence of the first clock signal from the first clock signal terminal and the second clock signal from the second clock signal terminal, controls the The voltage of the first node remains at the turn-on voltage.
  • the first output sub-circuit of the shift register circuit is turned on under the control of the turn-on voltage of the first node, and transmits the first voltage signal from the first voltage terminal to the signal output terminal.
  • the first control sub-circuit includes a holding unit and a first control unit, the first control sub-circuit is connected between the first DC voltage signal from the first clock signal terminal and the first DC voltage signal from the second clock signal terminal Under the influence of the two DC voltage signals, the voltage of the first node is adjusted to the turn-on voltage, including:
  • the holding unit is turned off under the influence of the first DC voltage signal from the first clock signal terminal and the initial voltage signal from the initial signal terminal; the first control unit is turned off by the first DC voltage signal from the second clock signal terminal. Under the influence of two DC voltage signals, the voltage of the first node is adjusted to the turn-on voltage.
  • the first control sub-circuit maintains the voltage of the first node at the voltage of the first node under the influence of the first clock signal from the first clock signal terminal and the second clock signal from the second clock signal terminal Turn-on voltage, including:
  • the first control unit adjusts the voltage of the first node under the influence of the second clock signal from the second clock signal terminal; the holding unit adjusts the voltage of the first node from the first clock signal terminal of the first clock signal terminal. Turn on under control, and keep the voltage of the first node at the turn-on voltage.
  • a frame period further includes a data refresh phase including a first phase, a second phase, a third phase, and a fourth phase.
  • the second control sub-circuit of the shift register circuit includes a third control unit, a fourth control unit, a fifth control unit and an adjustment unit, and in the first stage and the third stage, the third control unit Under the control of the first control signal from the first control signal terminal, the first voltage signal from the first voltage terminal is transmitted to the first control sub-circuit; the fourth control unit is in the third control unit Under the control of the third node, the fourth clock signal from the fourth clock signal terminal is transmitted to the third node.
  • the adjustment unit adjusts the voltage output by the third control unit according to the voltage of the third node; the fourth control unit is in the third control Under the control of the unit, the fourth clock signal from the fourth clock signal terminal is transmitted to the third node; the fifth control unit, under the control of the second control signal from the second control signal terminal, will The voltage of the third node is transmitted to the second node; the second output sub-circuit is turned on under the control of the turn-on voltage of the second node, and transmits the second voltage signal from the second voltage terminal to the second node signal output.
  • FIG. 1 is a structural diagram of a display device according to some embodiments of the present disclosure
  • FIG. 2A is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • 2B is another structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 3 is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of a shift register circuit according to some embodiments of the present disclosure.
  • FIG. 5 is another structural diagram of a shift register circuit according to some embodiments of the present disclosure.
  • FIG. 6 is another structural diagram of a shift register circuit according to some embodiments of the present disclosure.
  • FIG. 7 is a circuit diagram of a shift register circuit according to some embodiments of the present disclosure.
  • FIG. 8 is a circuit diagram of another shift register circuit according to some embodiments of the present disclosure.
  • FIG. 9 is another structural diagram of a shift register circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a circuit diagram of yet another shift register circuit according to some embodiments of the present disclosure.
  • FIG. 11 is a circuit diagram of yet another shift register circuit according to some embodiments of the present disclosure.
  • FIG. 12 is a timing diagram of a driving method of a shift register circuit according to some embodiments of the present disclosure.
  • FIG. 13 is a simulation diagram of a simulation experiment of a driving method of a shift register circuit according to some embodiments of the present disclosure
  • FIG. 14 is a timing diagram of a driving method of a shift register circuit in a data refresh stage according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • Coupled and its derivatives may be used.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display device 200 may be an organic electroluminescence (Organic Light-Emitting Diode, OLED for short) display device.
  • OLED Organic Light-Emitting Diode
  • the above-described display device 200 may be any device that displays images whether in motion (eg, video) or stationary (eg, still images) and whether text or images. More specifically, it is contemplated that the embodiments may be implemented in or associated with a wide variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel monitors, computer monitors, automotive monitors (e.g., odometer displays, etc.), navigators, cockpit controls and/or displays, displays of camera views (eg, displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, building structures, packaging and aesthetic structures (eg, a display for an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • handheld or portable computers GPS receivers/navigators
  • the above-mentioned display panel 100 includes: a display area AA (Active Area, active display area) and a peripheral area BB located on at least one side of the display area AA.
  • the peripheral area BB surrounds the display area AA for illustration.
  • the above-mentioned display panel 100 includes sub-pixels (sub pixels) P of multiple colors arranged in the display area AA, and the sub-pixels of the multiple colors include at least a first color sub-pixel, a second color sub-pixel and a third color sub-pixel.
  • the first color, the second color and the third color may be three primary colors (eg red, green and blue).
  • the above-mentioned plurality of sub-pixels P are arranged in a matrix form as an example for description.
  • the sub-pixels P arranged in a row along the horizontal direction X are called a row of sub-pixels; the sub-pixels P arranged in a row along the vertical direction Y are called a column of sub-pixels.
  • each sub-pixel P is provided with a pixel driving circuit S, and the pixel driving circuit S includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5 , a sixth transistor T6, a seventh transistor T7 and a capacitor Cst.
  • the sub-pixel P further includes a light-emitting device D, the first electrode of the light-emitting device D is coupled to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting device D is coupled to the second voltage signal terminal VSS.
  • the pixel driving circuits S located in the same row are coupled to the same control signal line L, and the pixel driving circuits S located in the same column are coupled to the same data line DL (Data Line) to drive the light-emitting devices in the sub-pixels P D glows.
  • the pixel driving circuit S is not limited to the circuit structure shown in FIG. 3 , but may also have other circuit structures, which will not be listed here.
  • the transistors included in the pixel driving circuit S may all be N-type transistors or P-type transistors, and may also include both N-type and P-type transistors, which can be designed according to actual needs.
  • the transistors included in the pixel driving circuit S may be all low temperature polysilicon (Low Temperature Poly-silicon, referred to as LTPS) transistors, may also be oxide (Oxide) transistors, and may also include low temperature polysilicon and oxide transistors. .
  • the voltage for controlling the sub-pixel brightness varies with time due to transistor leakage in the pixel driving circuit S
  • data still needs to be refreshed when displaying a static image.
  • it is an effective method to reduce the refresh frequency, and at the same time to maintain the display quality, it is necessary to reduce the leakage speed of the transistors in the pixel driving circuit S.
  • the low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, referred to as LTPO) process can be combined with the excellent characteristics of low temperature polysilicon and oxide, and the transistor used for driving in the pixel driving circuit S is used.
  • the first transistor T1, the fifth transistor T5 and the sixth transistor T6 in FIG. 3 which are set as oxide transistors, and the ultra-low leakage characteristics of oxide semiconductors can be used to improve the phenomenon of transistor leakage;
  • the transistors used for switching in S eg, the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are set as low temperature polysilicon transistors to ensure the charging speed of the sub-pixel P and small parasitic capacitance.
  • the peripheral area BB of the display panel 100 is provided with at least one gate driving circuit G and a data driving circuit DD.
  • the gate driving circuit G may be disposed on the side along the extending direction of the control signal line L
  • the data driving circuit DD may be disposed on the side along the extending direction of the data line DL to drive the display panel
  • the pixel driving circuit S in the 100 drives the light-emitting device to emit light, so that the display panel 100 displays.
  • the gate driving circuit G may be a gate driving circuit for transmitting the light emission control signal Em to the pixel driving circuit S, and may also be a gate driving circuit for transmitting the scanning signal Gate to the pixel driving circuit S.
  • the peripheral region BB of the display panel 100 is provided with a first gate driving circuit 01 , a second gate driving circuit 02 and a third gate driving circuit 03 .
  • the first gate driving circuit G is configured to transmit the light emission control signal Em to the light emission control signal terminal EM of the pixel driving circuit S;
  • the second gate driving circuit 02 is configured to scan the pixel driving circuit S for the second time
  • the signal terminal GATE2 transmits the second scan signal Gate2, and transmits the third scan signal Gate3 to the third scan signal terminal GATE3;
  • the third gate driving circuit 03 is configured to transmit the first scan signal to the first scan signal terminal GATE1 of the pixel driving circuit S.
  • the scanning signal Gate1, and the fourth scanning signal Gate4 is transmitted to the fourth scanning signal terminal GATE4.
  • the number of the gate driving circuits G included in the display panel 100 may be determined according to specific conditions, and the above are just examples.
  • the gate driving circuit G may be a GOA (English full name: Gate Driver on Array, Chinese full name: array substrate row driver) circuit, that is, the gate driving circuit G is directly integrated on the array substrate of the display panel 100 .
  • GOA Gate Driver on Array
  • the gate driving circuit G is directly integrated on the array substrate of the display panel 100 .
  • the following embodiments are all described by taking the gate driving circuit G as the GOA circuit as an example.
  • FIG. 2A is only schematic, so that the gate driving circuit G is arranged on one side of the peripheral area BB of the display panel 100 to sequentially drive the control signal lines L row by row from one side, that is, one-side driving illustrated as an example.
  • gate driving circuits G may be provided on two sides of the peripheral area BB of the display panel 100 along the extending direction of the control signal line L, respectively, and the gate driving circuits G can On both sides, the control signal lines L are sequentially driven row by row, that is, double-sided driving.
  • gate driving circuits G may be provided on two sides of the peripheral region BB of the display panel 100 along the extending direction of the control signal line L, respectively, and the gate driving circuits G alternately On both sides, the control signal lines L are sequentially driven row by row, that is, cross driving.
  • the following embodiments of the present disclosure are all described by taking single-side driving as an example.
  • the gate driving circuit G includes a plurality of shift register circuits cascaded in sequence, and each stage of the shift register circuit is coupled to at least one control signal line L.
  • N-stage shift register circuits (RS1, RS2...RS(N)) are coupled to N control signal lines (L1, L2...L(N)) in one-to-one correspondence
  • each stage of the shift register circuit is coupled to a control signal line L
  • each control signal line L is coupled to a row of sub-pixels P, that is, each stage of the shift register circuit drives a row of sub-pixels P.
  • N is a positive integer.
  • each control signal line L can be coupled to two adjacent rows of sub-pixels P, that is, except for the first and last shift register circuits, each shift register circuit can drive two rows Subpixel P.
  • each stage of the shift register circuit drives the sub-pixels P in two adjacent rows.
  • each stage of the shift register circuit drives the sub-pixels P in two adjacent rows.
  • the shift register circuits ( RS1 , RS2 . , and output the scan signal to the control signal line L coupled thereto through the signal output terminal Oput.
  • the shift register circuits ( RS1 , RS2 . Iput), and the circuit structure of each shift register circuit in the gate drive circuit G is the same.
  • each shift register circuit in the gate drive circuit G can be as follows:
  • the signal input terminal Iput of the first-stage shift register circuit RS1 is connected to the start signal terminal STV; except for the first-stage shift register circuit RS1, the signal input terminal Iput of other shift register circuits is connected to the shift register circuit located in front of it.
  • the signal output terminal Oput of the register circuit is connected.
  • the shift register circuits ( RS1 , RS2 ?? RS(N) ) of the gate driving circuit G are further provided with a first clock signal terminal CK1 , a second clock signal terminal CB1 , The third clock signal terminal CK2 and the fourth clock signal terminal CB2 are respectively coupled to the signal lines to receive the voltage signals transmitted by the signal lines.
  • the display device works in a low frequency mode, and the gate drive circuit in the display device is driven by means of clock retention, so as to ensure that the potential of the control signal output by the gate drive circuit is valid when the display device displays a picture.
  • the clock signal required to drive the clock is an AC voltage signal switched between high and low levels, which leads to a large power consumption of the display device.
  • due to the leakage phenomenon of the transistors in the gate drive circuit it will also Affects the validity of the potential of the scan signal it outputs.
  • some embodiments of the present disclosure further provide a shift register circuit RS, which includes a first control subcircuit 11 and a first output subcircuit 12 .
  • the first control sub-circuit 11 is coupled to the first clock signal terminal CK1, the second clock signal terminal CB1 and the first node N1.
  • the first control sub-circuit 11 is configured to change the voltage of the first node N1 under the influence of the first DC voltage signal from the first clock signal terminal CK1 and the second DC voltage signal from the second clock signal terminal CB1. adjusting to the turn-on voltage; and, under the influence of the first clock signal from the first clock signal terminal CK1 and the second clock signal from the second clock signal terminal CB1, maintaining the voltage of the first node N1 to the turn-on voltage.
  • adjusting the voltage of the first node N1 to the turn-on voltage refers to changing the voltage of the first node N1 from not equal to the turn-on voltage to equal to the turn-on voltage.
  • Mainntaining the voltage of the first node N1 at the turn-on voltage means keeping the voltage of the first node N1 at the turn-on voltage without changing the voltage of the first node N1.
  • a frame period includes a data retention phase
  • the data retention phase includes multiple denoising sub-phases and multiple denoising enhancement sub-phases, and the de-noising sub-phases and denoising enhancement sub-phases alternate.
  • the first clock signal terminal CK1 is configured to output the first DC voltage signal in the de-noising sub-stage, and output the first clock signal in the de-noising and strengthening sub-stage.
  • the second clock signal terminal CB1 is configured to output a second DC voltage signal in the de-noising sub-stage, and output a second clock signal in the de-noising and enhancing sub-stage.
  • the first DC voltage signal and the second DC voltage signal may both be low-level signals, and the first clock signal and the second clock signal are approximately mutually inverse signals.
  • the first control sub-circuit 11 is configured to, in the de-noising sub-stage, under the influence of the first DC voltage signal and the second DC voltage signal, adjust the voltage of the first node N1 to the turn-on voltage; and, in the de-noising enhancement In the sub-stage, under the influence from the first clock signal and the second clock signal, the voltage of the first node N1 is kept as the turn-on voltage.
  • the first output sub-circuit 12 is coupled to the first node N1 , the first voltage terminal VSS and the signal output terminal Oput.
  • the first output sub-circuit 12 is configured to be turned on under the control of the turn-on voltage of the first node N1, and to transmit the first voltage signal from the first voltage terminal VSS to the signal output terminal Oput.
  • first voltage terminal VSS is configured to transmit a DC level signal, that is, the first voltage signal is a DC level signal.
  • the first voltage terminal VSS may be coupled to the VSS line used for transmitting the first voltage signal in the display device 200 to receive the first voltage signal.
  • the first voltage signal may be a DC low level signal or a DC high level signal.
  • the turn-on or turn-off of the first output sub-circuit 12 is controlled by the voltage of the first node N1.
  • the voltage of the first node N1 is the “turn-on voltage”.
  • the first output sub-circuit 12 is configured to be turned on under the control of the turn-on voltage of the first node N1 in the data holding phase, and to transmit the first voltage signal from the first voltage terminal VSS to the signal output terminal Oput, and the signal
  • the first voltage signal output by the output terminal Oput is the scan signal, which is used to drive the pixel driving circuit S in the display panel 100 to drive the light-emitting device to emit light, so that the display panel 100 displays.
  • the first voltage signal is a DC low level signal or a DC high level signal, depending on whether the effective potential of the scan signal is a low level or a high level.
  • the first control sub-circuit 11 receives the first DC voltage signal from the first clock signal terminal CK1, and the first DC voltage signal from the second clock signal terminal CB1 The second DC voltage signal, and under the influence of the first DC voltage signal and the second DC voltage signal, adjusts the voltage of the first node N1 to the turn-on voltage to control the first output sub-circuit 12 to turn on and output the scan signal. Since the power consumption of the display device 200 for generating the DC voltage signal is smaller than the power consumption for generating the AC voltage signal, the first control sub-circuit 11 uses the first DC voltage signal and the second DC voltage signal rather than the AC voltage signal. , and the first DC voltage signal and the second DC voltage signal are both low-level signals, which can reduce the power consumption of the display device 200 .
  • the first control sub-circuit 11 under the influence of the first clock signal from the first clock signal terminal CK1 and the second clock signal from the second clock signal terminal CB1, the first clock signal
  • the voltage of the node N1 is kept at the turn-on voltage, which can prevent the voltage of the first node N1 from changing due to the leakage of the transistor in the shift register circuit RS, thereby ensuring the stable turn-on of the first output sub-circuit 12 .
  • the shift register circuit RS further includes a second control sub-circuit 13 and a second output sub-circuit 14 .
  • the second control sub-circuit 13 is connected to the first node N1, the first voltage terminal VSS, the first control signal terminal CON1, the second control signal terminal CON2, the fourth clock signal terminal CB2, the second voltage terminal VDD, the second node N2 is coupled to the first control sub-circuit 11 .
  • the second control sub-circuit 13 is configured to, under the control of the first control signal from the first control signal terminal CON1 and the second control signal from the second control signal terminal CON2, and under the control of the first control sub-circuit 11, Under the influence of the first voltage signal from the first voltage terminal VSS and the fourth clock signal from the fourth clock signal terminal CB2, the voltage of the second node N2 is adjusted to the turn-on voltage.
  • first control signal terminal CON1 is either the first clock signal terminal CK1 or the third clock signal terminal CK2
  • second control signal terminal CON2 is the second clock signal terminal CB1 or One of the fourth clock signal terminal CB2.
  • one frame period further includes a data refresh phase S preceding the data retention phase.
  • the first clock signal terminal CK1 is configured to output the first clock signal in the data refresh phase S.
  • the second clock signal terminal CB1 is configured to output the second clock signal in the data refresh phase S.
  • the third clock signal terminal CK2 is configured to output a third clock signal during the data refresh phase S, and output a third DC voltage signal during the data retention phase.
  • the fourth clock signal terminal CB2 is configured to output a fourth clock signal during the data refresh phase S, and output a fourth DC voltage signal during the data retention phase.
  • the third DC voltage signal and the fourth DC voltage signal are both high-level signals.
  • FIG. 7 shows a situation in which the "first control signal terminal CON1" is the third clock signal terminal CK2, and the "second control signal terminal CON2" is the fourth clock signal terminal CB2. That is, the second control sub-circuit 13 is connected with the first node N1, the first voltage terminal VSS, the third clock signal terminal CK2, the fourth clock signal terminal CB2, the second voltage terminal VDD, the second node N2 and the first control sub-circuit 11 Coupling.
  • the second control sub-circuit 13 is configured to, under the control of the third clock signal from the third clock signal terminal CK2 and the fourth clock signal from the fourth clock signal terminal CB2, and under the control of the first control sub-circuit 11, Under the influence of the first voltage signal from the first voltage terminal VSS and the fourth clock signal from the fourth clock signal terminal CB2, the voltage of the second node N2 is adjusted to the turn-on voltage.
  • FIG. 8 shows a situation in which the “first control signal terminal CON1” is the first clock signal terminal CK1, and the “second control signal terminal CON2” is the second clock signal terminal CB1. That is, the second control sub-circuit 13 is connected to the first node N1, the first voltage terminal VSS, the first clock signal terminal CK1, the second clock signal terminal CB1, the fourth clock signal terminal CB2, the second voltage terminal VDD, the second node N2 is coupled to the first control sub-circuit 11 .
  • the second control sub-circuit 13 is configured to, under the control of the first clock signal from the first clock signal terminal CK1 and the second clock signal from the second clock signal terminal CB1, and under the control of the first control sub-circuit 11, Under the influence of the first voltage signal from the first voltage terminal VSS and the fourth clock signal from the fourth clock signal terminal CB2, the voltage of the second node N2 is adjusted to the turn-on voltage.
  • the second output sub-circuit 14 is coupled to the second node N2 , the second voltage terminal VDD and the signal output terminal Oput.
  • the second output sub-circuit 14 is configured to be turned on under the control of the turn-on voltage of the second node N2, and to transmit the second voltage signal from the second voltage terminal VDD to the signal output terminal Oput.
  • the "second voltage terminal VDD" is configured to transmit a DC level signal, that is, the second voltage signal is a DC level signal.
  • the second voltage terminal VDD may be coupled to the VDD line for transmitting the second voltage signal in the display device 200 to receive the second voltage signal.
  • the second voltage signal may be a DC high level signal or a DC low level signal.
  • the turn-on or turn-off of the second output sub-circuit 14 is controlled by the voltage of the second node N2.
  • the voltage of the second node N2 is the "turn-on voltage”.
  • the second output sub-circuit 14 is configured to be turned off under the control of the voltage of the second node N2 in the data retention stage; and, in the data refresh stage S, under the control of the turn-on voltage of the second node N2 turn on, the signal output terminal Oput outputs a second voltage signal from the second voltage terminal VDD, the second voltage signal is used to drive the pixel driving circuit S in the display panel 100 to turn off, thereby driving the light-emitting device to stop emitting light, so that the display panel 100 Stop showing.
  • the second voltage signal is a DC high level signal or a DC low level signal, depending on whether the effective potential of the driving pixel driving circuit S to be turned off is a high level or a low level.
  • the first control sub-circuit 11 includes a holding unit 111 and a first control unit 112 .
  • the holding unit 111 is coupled to the first clock signal terminal CK1, the first node N1 and the initial signal terminal STV.
  • the holding unit 111 is configured to be turned off under the influence of the first DC voltage signal from the first clock signal terminal CK1 and the initial voltage signal from the initial signal terminal STV; It is turned on under the control of the clock signal, and the voltage of the first node N1 is kept as the turn-on voltage.
  • the first control unit 112 is coupled to the second clock signal terminal CB1 and the first node N1.
  • the first control unit 112 is configured to, under the influence of the second DC voltage signal from the second clock signal terminal CB1, adjust the voltage of the first node N1 to the turn-on voltage; and, under the influence of the second DC voltage signal from the second clock signal terminal CB1; Under the influence of the second clock signal, the voltage of the first node N1 is adjusted.
  • the holding unit 111 is configured to be turned off under the influence of the first DC voltage signal and the initial voltage signal in the denoising sub-phase; and the first control unit 112 is configured to be turned off when the second DC voltage signal Under the influence of , the voltage of the first node N1 is adjusted to the turn-on voltage, thereby controlling the first output sub-circuit 12 to turn on in the denoising sub-stage.
  • the first control unit 112 is configured to adjust the voltage of the first node N1 under the influence of the second clock signal in the denoising enhancement sub-stage; and the holding unit 111 is configured to, under the control of the first clock signal Turning on, the voltage of the first node N1 is kept as the turn-on voltage, so that the first output sub-circuit 12 is kept turned on in the denoising enhancement sub-stage.
  • the first output sub-circuit 12 can be guaranteed to be stably turned on in the data holding phase.
  • the holding unit 111 includes a first transistor T1, the control electrode of the first transistor T1 is coupled to the first clock signal terminal CK1, and the first electrode of the first transistor T1 is connected to the first clock signal terminal CK1.
  • the initial signal terminal STV is coupled, and the second pole of the first transistor T1 is coupled to the first node N1 (fourth node N4 ).
  • the first transistor T1 is configured to be turned off under the influence of the first DC voltage signal and the initial voltage signal in the denoising sub-stage; The voltage of the first node N1 is maintained at the turn-on voltage.
  • the first control unit 112 includes a first capacitor C1, a first end of the first capacitor C1 is coupled to the second clock signal end CB1, and a second end of the first capacitor C1 is connected to the first node N1 is coupled.
  • the first capacitor C1 is configured to adjust the voltage of the first node N1 to the turn-on voltage under the action of the second DC voltage signal according to the bootstrap effect of the capacitor in the denoising sub-stage; and, in the denoising booster In the stage, under the action of the second clock signal, the voltage of the first node N1 is adjusted.
  • the first DC voltage signal received at the first clock signal terminal CK1 is at a low level.
  • the second DC voltage signal received at the second clock signal terminal CB1 is a low-level signal, and the initial voltage signal received at the initial signal terminal STV is a low-level signal.
  • the voltage of the first DC voltage signal is the same as the voltage of the initial voltage signal.
  • the threshold voltage Vth of the P-type transistor is negative, and the conduction condition of the P-type transistor is the gate-source voltage difference of the transistor (the voltage difference between the control electrode and the first electrode of the transistor, or the control electrode and the first electrode of the transistor)
  • the first capacitor C1 is configured to adjust the voltage of the first node N1 to the turn-on voltage under the action of the second DC voltage signal according to the bootstrap effect of the capacitor in the denoising sub-stage, so that the turn-on voltage is the same as the second DC voltage.
  • the voltages of the voltage signals are approximately equal and are low.
  • the first output sub-circuit 12 is turned on under the control of the low level of the first node N1.
  • the transistors in the shift register circuit RS have a leakage phenomenon. For example, when the turn-on voltage of the first node N1 is at a low level, the leakage of the first transistor T1 will cause the voltage of the first node N1 to rise. , the first output sub-circuit 12 controlled by the voltage of the first node N1 is turned off or cannot be turned on completely.
  • the clock signal is a low-level signal
  • the second clock signal received at the second clock signal terminal CB1 is a high-level signal.
  • the first capacitor C1 is configured to pull up the voltage of the first node N1 under the action of the second clock signal in the denoising and strengthening sub-stage, so that the gate-source voltage difference of the first transistor T1 (the control of the first transistor T1 The voltage difference between the pole and the second pole) V gs ⁇ V th ⁇ 0, the first transistor T1 is turned on, so as to rectify the charge of the first node N1 to the initial signal terminal STV through the first transistor T1, and pull down the first node N1
  • the voltage of the first node N1 is kept as the turn-on voltage, so as to ensure the stable turn-on of the first output sub-circuit 12 .
  • the first control sub-circuit 11 further includes a first anti-leakage unit 114 , the first anti-leakage unit 114 is coupled to the first voltage terminal VSS, and the holding unit 111 is coupled to the first node N1 through the first anti-leakage unit 114 .
  • the first anti-leakage unit 114 is configured to maintain the voltage of the first node N1 under the control of the first voltage signal from the first voltage terminal VSS.
  • the holding unit 111 is coupled to the first node N1 through the first anti-leakage unit 114, and the first anti-leakage unit 114 can be used to block the connection between the holding unit 111 and the first node N1 to avoid
  • the first transistor T1 in 111 leaks electricity, which causes the voltage of the first node N1 to change, thereby maintaining the voltage of the first node N1.
  • the first anti-leakage unit 114 includes an eleventh transistor T11, the control electrode of the eleventh transistor T11 is coupled to the first voltage terminal VSS, and the first The pole is coupled to the first node N1, and the second pole of the eleventh transistor T11 is coupled to the holding unit 111 (the fourth node N4).
  • the eleventh transistor T11 is configured to be turned off under the control of the first voltage signal in the denoising sub-phase to block the connection of the first node N1 with the first transistor T1.
  • the first voltage signal received at the first voltage terminal VSS is a DC low level signal
  • the turn-on voltage of the first node N1 is low level
  • the voltage of the first voltage signal is approximately equal to the turn-on voltage.
  • the eleventh transistor T11 is turned off, to block the connection between the first node N1 and the first transistor T1.
  • the first control sub-circuit 11 further includes a second control unit 113, the second control unit 113 and the holding unit 111, the second control sub-circuit 13, the fourth clock signal terminal CB2 and The second voltage terminal VDD is coupled.
  • the second control unit 113 is configured to transmit the second voltage signal from the second voltage terminal VDD to the holding unit under the control of the fourth clock signal from the fourth clock signal terminal CB2 and the second control sub-circuit 13 111.
  • a frame cycle further includes: a data refresh stage S, which includes a first stage t1, a second stage t2, and a third stage t3 before the data retention stage and the fourth stage t4.
  • the holding unit 111 is further configured to transmit the initial signal from the initial signal terminal STV to the first node under the control of the first clock signal from the first clock signal terminal CK1 N1.
  • the first output sub-circuit 12 is also configured to be turned off under the control of the voltage of the first node N1.
  • the second control unit 113 is configured to, under the control of the fourth clock signal from the fourth clock signal terminal CB2 and the second control sub-circuit 13, convert the voltage from the second voltage
  • the second voltage signal of the terminal VDD is transmitted to the holding unit 111 .
  • the second control unit 113 transmits the second voltage signal from the second voltage terminal VDD to the holding unit 111 and the first node N1, so that the voltage of the first node N1 is the second voltage voltage of the signal.
  • the voltage of the second voltage signal is approximately equal to the voltage of the initial signal in the first stage t1 and the third stage t3, so that the voltage of the first node N1 in the second stage t2 and the fourth stage t4 is the same as that in the first stage.
  • the voltages of t1 and the third stage t3 are approximately equal, so that in the data refresh stage S, the first output sub-circuit 12 is continuously turned off under the control of the second voltage signal of the first node N1.
  • the second control unit 113 includes a second transistor T2 and a third transistor T3, the control electrode of the second transistor T2 is coupled to the second control sub-circuit 13, the second The first pole of the transistor T2 is coupled to the second voltage terminal VDD.
  • the control electrode of the third transistor T3 is coupled to the fourth clock signal terminal CB2, the first electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the second electrode of the third transistor T3 is coupled to the holding unit 111 ( The fourth node N4) is coupled.
  • the second transistor T2 is configured to be turned on under the control of the voltage signal output by the second control sub-circuit 13 during the second phase t2 and the fourth phase t4 of the data refresh phase S.
  • the third transistor T3 is configured to be turned on under the control of the fourth clock signal during the second phase t2 and the fourth phase t4 of the data refresh phase S.
  • the second voltage signal received at the second voltage terminal VDD is transmitted to the holding unit 111 through the second transistor T2 and the third transistor T3.
  • the first output sub-circuit 12 includes a tenth transistor T10, the control electrode of the tenth transistor T10 is coupled to the first node N1, and the first electrode of the tenth transistor T10 is It is coupled to the first voltage terminal VSS, and the second pole of the tenth transistor T10 is coupled to the signal output terminal Oput.
  • the tenth transistor T10 is configured to be turned off under the control of the second voltage signal of the first node N1 in the data refresh stage S; and turned on under the control of the turn-on voltage of the first node N1 in the data retention stage, The first voltage signal from the first voltage terminal VSS is transmitted to the signal output terminal Oput.
  • the second control sub-circuit 13 includes a third control unit 131 , an adjustment unit 132 , a fourth control unit 133 and a fifth control unit 134 .
  • the third control unit 131 is coupled to the first control sub-circuit 11 , the first control signal terminal CON1 and the first voltage terminal VSS.
  • the third control unit 131 is configured to transmit the first voltage signal from the first voltage terminal VSS to the first control sub-circuit 11 under the control of the first control signal from the first control signal terminal CON1.
  • the third control unit 131 is configured to, in the first stage t1 and the third stage t3 of the data refresh stage S, under the control of the first control signal, convert the first voltage from the first voltage terminal VSS to The signal is transmitted to the first control subcircuit 11 .
  • FIG. 7 and FIG. 10 show a situation in which the “first control signal terminal CON1” is the third clock signal terminal CK2. That is, the third control unit 131 is coupled to the first control sub-circuit 11 , the third clock signal terminal CK2 and the first voltage terminal VSS. The third control unit 131 is configured to, in the first phase t1 and the third phase t3 of the data refresh phase S, under the control of the third clock signal from the third clock signal terminal CK2, convert the voltage from the first voltage terminal VSS to The first voltage signal is transmitted to the first control sub-circuit 11 .
  • the third control unit 131 is further configured to, in the data holding phase, under the control of the holding unit 111 of the first control sub-circuit 11 (or, under the control of the voltage of the first node N1 ), the output from the third The third clock signal of the clock signal terminal CK2 is used to control the second control unit 113 of the first control sub-circuit 11 to be turned off.
  • FIG. 8 and FIG. 11 show a situation in which the “first control signal terminal CON1” is the first clock signal terminal CK1. That is, the third control unit 131 is coupled to the first control sub-circuit 11 , the first clock signal terminal CK1 and the first voltage terminal VSS. The third control unit 131 is configured to, in the first phase t1 and the third phase t3 of the data refresh phase S, under the control of the first clock signal from the first clock signal terminal CK1, convert the voltage from the first voltage terminal VSS to The first voltage signal is transmitted to the first control sub-circuit 11 .
  • the third clock signal terminal CK2 is replaced with the first clock
  • the signal terminal CK1 reduces the number of clock signal terminals set in the shift register circuit RS to three, which are the first clock signal terminal CK1, the second clock signal terminal CB1 and the fourth clock signal terminal CB2 respectively.
  • the fourth control unit 133 is coupled to the third control unit 131 , the fourth clock signal terminal CB2 and the third node N3 .
  • the fourth control unit 133 is configured to, under the control of the third control unit 131, transmit the fourth clock signal from the fourth clock signal terminal CB2 to the third node N3.
  • the fourth control unit 133 is configured to, in the first stage t1 and the third stage t3 of the data refresh stage S, under the control of the first voltage signal output by the third control unit 131
  • the fourth clock signal of the clock signal terminal CB2 is transmitted to the third node N3.
  • the third control unit 131 is coupled to the first control sub-circuit 11 , the third clock signal terminal CK2 and the first voltage terminal VSS.
  • the fourth control unit 133 is further configured to be turned off under the control of the third clock signal from the third clock signal terminal CK2 output by the third control unit 131 in the data retention phase.
  • the adjustment unit 132 is coupled to the third control unit 131 and the third node N3.
  • the adjusting unit 132 is configured to adjust the voltage output by the third control unit 131 according to the voltage of the third node N3.
  • the adjustment unit 132 is coupled to the output terminal of the third control unit 131 and the third node N3.
  • the adjustment unit 132 is configured to, in the second phase t2 and the fourth phase t4 of the data refresh phase S, adjust the voltage of the output of the third control unit 131 according to the voltage of the third node N3 to ensure that the fourth control unit 133 is in the It is stably turned on under the control of the voltage signal output by the third control unit 131 .
  • the fifth control unit 134 is coupled to the first node N1 , the second node N2 , the third node N3 , the second voltage terminal VDD and the second control signal terminal CON2 .
  • the fifth control unit 134 is configured to, under the control of the second control signal from the second control signal terminal CON2, transmit the voltage of the third node N3 to the second node N2; and, under the control of the voltage of the first node N1 Under the control, the second voltage signal from the second voltage terminal VDD is transmitted to the second node N2.
  • the fifth control unit 134 is configured to, under the control of the second control signal, transmit the voltage of the third node N3 to the second stage t2 and the fourth stage t4 of the data refresh stage S. node N2, to adjust the voltage of the second node N2 to the turn-on voltage.
  • the second output sub-circuit 14 is configured to be turned on under the control of the turn-on voltage of the second node N2.
  • the fifth control unit 134 is further configured to, in the data holding phase, under the control of the voltage of the first node N1, transmit the second voltage signal from the second voltage terminal VDD to the second node N2 to control the second output Subcircuit 14 is closed.
  • FIG. 7 and FIG. 10 show a situation in which the “second control signal terminal CON2” is the fourth clock signal terminal CB2. That is, the fifth control unit 134 is coupled to the first node N1, the second node N2, the third node N3, the second voltage terminal VDD and the fourth clock signal terminal CB2. The fifth control unit 134 is configured to, in the second phase t2 and the fourth phase t4 of the data refresh phase S, transmit the voltage of the third node N3 under the control of the fourth clock signal from the fourth clock signal terminal CB2 to the second node N2.
  • FIG. 8 and FIG. 11 show a situation in which the “second control signal terminal CON2” is the second clock signal terminal CB1. That is, the fifth control unit 134 is coupled to the first node N1, the second node N2, the third node N3, the second voltage terminal VDD and the second clock signal terminal CB1. The fifth control unit 134 is configured to transmit the voltage of the third node N3 under the control of the second clock signal from the second clock signal terminal CB1 in the second stage t2 and the fourth stage t4 of the data refresh stage S to the second node N2.
  • the third control unit 131 includes a fourth transistor T4 and a fifth transistor T5, and the control electrode of the fourth transistor T4 is connected to the first control sub-circuit 11 (the fourth node N4 ) is coupled, the first pole of the fourth transistor T4 is coupled to the first control signal terminal CON1, and the second pole of the fourth transistor T4 is coupled to the first control sub-circuit 11 (the fifth node N5).
  • the fourth transistor T4 is configured to be turned on under the control of the first control sub-circuit 11 in the data retention phase, and transmit the first control signal from the first control signal terminal CON1 to the second control signal of the first control sub-circuit 11 .
  • control unit 113 controls the third control unit 131 .
  • the control electrode of the fourth transistor T4 is coupled to the holding unit 111 of the first control sub-circuit 11, and the first electrode of the fourth transistor T4 is coupled to the third clock signal terminal CK2. Then, the second pole of the fourth transistor T4 is coupled to the second control unit 113 of the first control sub-circuit 11 .
  • the fourth transistor T4 is configured to be turned on under the control of the holding unit 111 of the first control sub-circuit 11 in the data holding phase, and transmit the third clock signal from the third clock signal terminal CK2 to the first control sub-circuit 11 of the second control unit 113 to control the second control unit 113 to turn off.
  • the control electrode of the fourth transistor T4 is coupled to the holding unit 111 of the first control sub-circuit 11, and the first electrode of the fourth transistor T4 is coupled to the first clock signal terminal CK1. Then, the second pole of the fourth transistor T4 is coupled to the second control unit 113 of the first control sub-circuit 11 .
  • the fourth transistor T4 is configured to be turned on under the control of the holding unit 111 of the first control sub-circuit 11 in the data holding phase, to transmit the first DC voltage signal or the first clock signal from the first clock signal terminal CK1 to the second control unit 113 of the first control subcircuit 11 .
  • the control electrode of the fifth transistor T5 is coupled to the first control signal terminal CON1
  • the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VSS
  • the second electrode of the fifth transistor T5 is coupled to the first voltage terminal VSS.
  • the pole is coupled to the first control sub-circuit 11 (the fifth node N5).
  • the fifth transistor T5 is configured to be turned on under the control of the first control signal from the first control signal terminal CON1 in the first phase t1 and the third phase t3 of the data refresh phase S, and turn on the voltage from the first voltage terminal VSS
  • the first voltage signal is transmitted to the first control sub-circuit 11 .
  • the control electrode of the fifth transistor T5 is coupled to the third clock signal terminal CK2, the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VSS, and the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VSS.
  • the diode is coupled to the second control unit 113 of the first control sub-circuit 11 .
  • the fifth transistor T5 is configured to be turned on under the control of the third clock signal from the third clock signal terminal CK2 in the first phase t1 and the third phase t3 of the data refresh phase S, to turn on the voltage from the first voltage terminal VSS
  • the first voltage signal is transmitted to the first control sub-circuit 11 .
  • the control electrode of the fifth transistor T5 is coupled to the first clock signal terminal CK1
  • the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VSS
  • the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VSS.
  • the diode is coupled to the second control unit 113 of the first control sub-circuit 11 .
  • the fifth transistor T5 is configured to be turned on under the control of the first clock signal from the first clock signal terminal CK1 in the first phase t1 and the third phase t3 of the data refresh phase S, and turn on the voltage from the first voltage terminal VSS
  • the first voltage signal is transmitted to the first control sub-circuit 11 .
  • the fourth control unit 133 includes a sixth transistor T6, the control electrode of the sixth transistor T6 is coupled to the second electrode (the fifth node N5) of the fourth transistor T4, and the control electrode of the sixth transistor T6
  • the first pole is coupled to the fourth clock signal terminal CB2
  • the second pole of the sixth transistor T6 is coupled to the third node N3.
  • the sixth transistor T6 is configured to be turned on under the control of the first voltage signal output by the third control unit 131 in the first stage t1 and the third stage t3 of the data refresh stage S, and the fourth clock signal terminal CB2 is turned on.
  • the fourth clock signal is transmitted to the third node N3 ; and, in the second stage t2 and the fourth stage t4 of the data refresh stage S, it is kept on under the control of the voltage output by the third control unit 131 .
  • the adjustment unit 132 includes a second capacitor C2, a first end of the second capacitor C2 is coupled to the third node N3, and a second end of the second capacitor C2 is connected to the second end of the fourth transistor T4
  • the pole (the fifth node N5) is coupled.
  • the second capacitor C2 is configured to adjust the output of the third control unit 131 under the action of the voltage of the third node N3 according to the bootstrap action of the capacitor in the second stage t2 and the fourth stage t4 of the data refresh stage S voltage.
  • the fourth clock signal terminal CB2 receives The fourth clock signal is a low level signal.
  • the first voltage signal output by the third control unit 131 is at a low level, according to the bootstrap action of the second capacitor C2, under the action of the fourth clock signal of the third node N3, the third control unit is further pulled down
  • the voltage output by the unit 131 ensures that the sixth transistor T6 is turned on in the second stage t2 and the fourth stage t4 of the data refresh stage S.
  • the fifth control unit 134 includes a seventh transistor T7 and an eighth transistor T8, the control electrode of the seventh transistor T7 is coupled to the second control signal terminal CON2, and the first electrode of the seventh transistor T7 Coupled to the third node N3, the second pole of the seventh transistor T7 is coupled to the second node N2.
  • the seventh transistor T7 is configured to be turned on under the control of the second control signal from the second control signal terminal CON2 in the second phase t2 and the fourth phase t4 of the data refresh phase S, to turn on the voltage of the third node N3 transmitted to the second node N2.
  • the control electrode of the seventh transistor T7 is coupled to the fourth clock signal terminal CB2, the first electrode of the seventh transistor T7 is coupled to the third node N3, and the second electrode of the seventh transistor T7 is coupled to the third node N3.
  • the pole is coupled to the second node N2.
  • the seventh transistor T7 is configured to be turned on under the control of the fourth clock signal from the fourth clock signal terminal CB2 in the second stage t2 and the fourth stage t4 of the data refresh stage S, to turn on the voltage of the third node N3 transmitted to the second node N2.
  • the control electrode of the seventh transistor T7 is coupled to the second clock signal terminal CB1, the first electrode of the seventh transistor T7 is coupled to the third node N3, and the second electrode of the seventh transistor T7 is coupled to the third node N3.
  • the pole is coupled to the second node N2.
  • the seventh transistor T7 is configured to be turned on under the control of the second clock signal from the second clock signal terminal CB1 in the second phase t2 and the fourth phase t4 of the data refresh phase S, to turn on the voltage of the third node N3 transmitted to the second node N2.
  • the control electrode of the eighth transistor T8 is coupled to the first node N1
  • the first electrode of the eighth transistor T8 is coupled to the second voltage terminal VDD
  • the second electrode of the eighth transistor T8 is coupled to the second voltage terminal VDD.
  • the second node N2 is coupled.
  • the eighth transistor T8 is configured to be turned on under the control of the voltage of the first node N1 in the data holding phase, and transmit the second voltage signal from the second voltage terminal VDD to the second node N2 to control the second output Subcircuit 14 is closed.
  • the second output sub-circuit 14 includes a ninth transistor T9 and a third capacitor C3, the control electrode of the ninth transistor T9 is coupled to the second node N2, and the ninth transistor T9 The first pole of T9 is coupled to the second voltage terminal VDD, and the second pole of the ninth transistor T9 is coupled to the signal output terminal Oput.
  • the ninth transistor T9 is configured to be turned on under the control of the turn-on voltage of the second node N2 in the second stage t2, the third stage t3 and the fourth stage t4 of the data refresh stage S, so as to turn on the voltage from the second voltage terminal
  • the second voltage signal of VDD is transmitted to the signal output terminal Oput; and, in the data holding phase, it is turned off under the control of the voltage of the second node N2.
  • the first terminal of the third capacitor C3 is coupled to the second voltage terminal VDD, and the second terminal of the third capacitor C3 is coupled to the second node N2.
  • the third capacitor C3 is configured to maintain the voltage of the second node N2 under the action of the second voltage signal from the second voltage terminal VDD according to the bootstrap effect of the capacitor in the data holding phase, thereby ensuring the ninth transistor T9 deadline.
  • the second control sub-circuit 13 further includes a second anti-leakage unit 135 , the second anti-leakage unit 135 is coupled to the first voltage terminal VSS, and the third control unit 131 passes through the first voltage terminal VSS.
  • the second anti-leakage unit 135 is coupled to the fourth control unit 133 .
  • the second anti-leakage unit 135 is configured to keep the fourth control unit 133 turned on under the control of the first voltage signal from the first voltage terminal VSS.
  • the principle of the first anti-leakage unit 114 is the same, because the fourth transistor T4 and the fifth transistor T5 have leakage problems, the second anti-leakage unit 135 acts to block the fourth transistor T4 and the fifth transistor T5 and the fourth control unit.
  • the function of 133 connection can prevent the control voltage received by the fourth control unit 133 from changing due to the leakage of the fourth transistor T4 and the fifth transistor T5, thereby keeping the fourth control unit 133 stably turned on.
  • the second anti-leakage unit 135 includes a twelfth transistor T12, the control electrode of the twelfth transistor T12 is coupled to the first voltage terminal VSS, and the first The pole is coupled to the fourth control unit 133 (sixth node N6 ), and the second pole of the twelfth transistor T12 is coupled to the third control unit 131 (fifth node N5 ).
  • the twelfth transistor T12 is configured to be turned off under the control of the first voltage signal from the first voltage terminal VSS in the data refresh stage S to block the fourth transistor T4 and the fifth transistor T5 and the fourth control unit 133 Connection.
  • the first voltage terminal VSS receives
  • the first voltage signal is a DC low-level signal
  • the fourth clock signal received at the fourth clock signal terminal CB2 is a low-level signal.
  • the second capacitor C2 is configured to pull down the voltage received by the fourth control unit 133 from the third control unit 131 under the action of the fourth clock signal of the third node N3 according to the bootstrap effect of the capacitor, so that the first The gate-source voltage difference of the twelfth transistor T12 (the voltage difference between the control electrode and the first electrode of the twelfth transistor T12) V gs ⁇ 0, the twelfth transistor T12 is turned off to block the fourth transistor T4 and the fifth transistor T5 Connection to the fourth control unit 133 .
  • the shift register circuit RS includes: a first control sub-circuit 11 , a first output sub-circuit 12 , a second control sub-circuit 13 and a second output sub-circuit 14 .
  • the first control sub-circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1.
  • the second control sub-circuit 13 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a second capacitor C2.
  • the second output subcircuit 14 includes a ninth transistor T9 and a third capacitor C3.
  • the first output sub-circuit 12 includes a tenth transistor T10.
  • the control electrode of the first transistor T1 is coupled to the first clock signal terminal CK1, the first electrode of the first transistor T1 is coupled to the initial signal terminal STV, and the second electrode of the first transistor T1 is coupled to the first node N1.
  • the first transistor T1 is configured to be turned on under the control of the first clock signal to keep the voltage of the first node N1 at the turn-on voltage.
  • the first end of the first capacitor C1 is coupled to the second clock signal end CB1, and the second end of the first capacitor C1 is coupled to the first node N1.
  • the first capacitor C1 is configured to adjust the voltage of the first node N1 to the turn-on voltage under the action of the second DC voltage signal according to the bootstrap action of the capacitor; and, under the action of the second clock signal, to adjust the voltage of the first node N1 The voltage of a node N1.
  • the control electrode of the second transistor T2 is coupled to the second control sub-circuit 13, and the first electrode of the second transistor T2 is coupled to the second voltage terminal VDD.
  • the second transistor T2 is configured to be turned on under the control of the voltage signal output by the second control sub-circuit 13 .
  • the control electrode of the third transistor T3 is coupled to the fourth clock signal terminal CB2, the first electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the second electrode of the third transistor T3 is coupled to the holding unit 111 catch.
  • the third transistor T3 is configured to be turned on under the control of the fourth clock signal.
  • the second voltage signal received at the second voltage terminal VDD is transmitted to the holding unit 111 through the second transistor T2 and the third transistor T3.
  • the control electrode of the fourth transistor T4 is coupled to the first control sub-circuit 11 , the first electrode of the fourth transistor T4 is coupled to the first control signal terminal CON1 , and the second electrode of the fourth transistor T4 is coupled to the first control sub-circuit 11 coupled.
  • the fourth transistor T4 is configured to be turned on under the control of the holding unit 111 of the first control sub-circuit 11 to transmit the first control signal from the first control signal terminal CON1 to the second control of the first control sub-circuit 11 unit 113.
  • the control electrode of the fifth transistor T5 is coupled to the first control signal terminal CON1, the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VSS, and the second electrode of the fifth transistor T5 is coupled to the first control sub-circuit 11 catch.
  • the fifth transistor T5 is configured to be turned on under the control of the first control signal from the first control signal terminal CON1 to transmit the first voltage signal from the first voltage terminal VSS to the first control sub-circuit 11 .
  • the control electrode of the sixth transistor T6 is coupled to the second electrode of the fourth transistor T4, the first electrode of the sixth transistor T6 is coupled to the fourth clock signal terminal CB2, and the second electrode of the sixth transistor T6 is coupled to the third node N3 coupled.
  • the sixth transistor T6 is configured to be turned on under the control of the first voltage signal output by the third control unit 131 to transmit the fourth clock signal from the fourth clock signal terminal CB2 to the third node N3.
  • the first end of the second capacitor C2 is coupled to the third node N3, and the second end of the second capacitor C2 is coupled to the second pole of the fourth transistor T4.
  • the second capacitor C2 is configured to adjust the voltage output by the third control unit 131 under the action of the voltage of the third node N3 according to the bootstrap action of the capacitor.
  • the control electrode of the seventh transistor T7 is coupled to the second control signal terminal CON2, the first electrode of the seventh transistor T7 is coupled to the third node N3, and the second electrode of the seventh transistor T7 is coupled to the second node N2.
  • the seventh transistor T7 is configured to be turned on under the control of the second control signal from the second control signal terminal CON2 to transmit the voltage of the third node N3 to the second node N2.
  • the control electrode of the eighth transistor T8 is coupled to the first node N1, the first electrode of the eighth transistor T8 is coupled to the second voltage terminal VDD, and the second electrode of the eighth transistor T8 is coupled to the second node N2.
  • the eighth transistor T8 is configured to be turned on under the control of the voltage of the first node N1 to transmit the second voltage signal from the second voltage terminal VDD to the second node N2 to control the second output sub-circuit 14 to be turned off.
  • the control electrode of the ninth transistor T9 is coupled to the second node N2, the first electrode of the ninth transistor T9 is coupled to the second voltage terminal VDD, and the second electrode of the ninth transistor T9 is coupled to the signal output terminal Oput.
  • the ninth transistor T9 is configured to be turned on under the control of the turn-on voltage of the second node N2 to transmit the second voltage signal from the second voltage terminal VDD to the signal output terminal Oput; and, at the second node N2 Cut off under voltage control.
  • the first terminal of the third capacitor C3 is coupled to the second voltage terminal VDD, and the second terminal of the third capacitor C3 is coupled to the second node N2.
  • the third capacitor C3 is configured to maintain the voltage of the second node N2 under the action of the second voltage signal from the second voltage terminal VDD according to the bootstrap effect of the capacitor, thereby ensuring the cut-off of the ninth transistor T9.
  • the control electrode of the tenth transistor T10 is coupled to the first node N1, the first electrode of the tenth transistor T10 is coupled to the first voltage terminal VSS, and the second electrode of the tenth transistor T10 is coupled to the signal output terminal Oput.
  • the tenth transistor T10 is configured to be turned off under the control of the voltage of the first node N1; and turned on under the control of the turn-on voltage of the first node N1 to transmit the first voltage signal from the first voltage terminal VSS to Signal output Oput.
  • the specific implementation manners of the first control subcircuit 11 , the first output subcircuit 12 , the second control subcircuit 13 and the second output subcircuit 14 are not limited to the manners described above, which may be Any implementation manners used, such as conventional connection manners well known to those skilled in the art, only need to ensure that the corresponding functions are implemented.
  • the above examples do not limit the scope of protection of the present disclosure. In practical applications, the skilled person can choose to use or not apply one or more of the above circuits according to the situation, and the various combinations and modifications of the above circuits do not depart from the principles of the present disclosure, and will not be repeated here.
  • the gate driving circuit G provided by some embodiments of the present disclosure further includes three or four clock signal lines, which are coupled to each shift register circuit of the gate driving circuit G.
  • the clock signal line may be coupled to the timing controller TCON in the display device 200 for transmitting the voltage signal from the timing controller TCON to each shift register circuit.
  • the gate driving circuit G includes four clock signal lines, which are the first clock signal line CLK1 , the second clock signal line CLK2 , the third clock signal line CLK3 and the fourth clock signal line CLK4 respectively. .
  • the first clock signal terminal CK1 of the 2N-1 stage shift register circuit is coupled to the first clock signal line CLK1; the second clock signal terminal CB1 of the 2N-1 stage shift register circuit is connected to the second clock signal
  • the signal line CLK2 is coupled;
  • the third clock signal terminal CK2 of the 2N-1 stage shift register circuit is coupled to the third clock signal line CLK3;
  • the fourth clock signal terminal CB2 of the 2N-1 stage shift register circuit is coupled to the fourth clock signal line CLK4.
  • first clock signal terminal CK1 of the 2N-stage shift register circuit is coupled to the second clock signal line CLK2; the second clock signal terminal CB1 of the 2N-stage shift register circuit is coupled to the first clock signal line CLK1
  • the third clock signal terminal CK2 of the 2N-stage shift register circuit is coupled to the fourth clock signal line CLK4; the fourth clock signal terminal CB2 of the 2N-stage shift register circuit is coupled to the third clock signal line CLK3 connected; N is a positive integer.
  • the first clock signal terminal CK1 in the odd-numbered stage shift register circuit and the second clock signal terminal CB1 in the even-numbered stage shift register circuit are both coupled to the first clock signal line CLK1. Then, the signal from the first clock signal line CLK1 is input. On the contrary, the first clock signal terminal CK1 in the even-numbered stage shift register circuit and the second clock signal terminal CB1 in the odd-numbered stage shift register circuit are both coupled to the second clock signal line CLK2, and the input is from the second clock signal line CLK2. signal of the clock signal line CLK2.
  • the third clock signal terminal CK2 in the odd-numbered stage shift register circuit and the fourth clock signal terminal CB2 in the even-numbered stage shift register circuit are both coupled to the third clock signal line CLK3, and the input comes from the third clock signal line CLK3. signal of the clock signal line CLK3.
  • the third clock signal terminal CK2 in the even-numbered stage shift register circuit and the fourth clock signal terminal CB2 in the odd-numbered stage shift register circuit are both coupled to the fourth clock signal line CLK4, and the input comes from the fourth clock signal line CLK4. signal of the clock signal line CLK4.
  • the third clock signal terminal CK2 is replaced with the first clock signal terminal. CK1, so that the number of clock signal terminals set in the shift register circuit RS is reduced to three, which are the first clock signal terminal CK1, the second clock signal terminal CB1 and the fourth clock signal terminal CB2 respectively.
  • the third clock signal line CLK3 can be canceled in the gate driving circuit G, that is, the gate driving circuit G includes three clock signal lines.
  • Some embodiments of the present disclosure also provide a driving method of a shift register circuit. Before introducing the driving method, the display process of the display device is first introduced.
  • one frame of image refers to "drawing" an image on the display screen by means of progressive scanning or interlaced scanning.
  • the plurality of sub-pixels P included in the display panel 100 are arranged in an array, including N rows and M columns.
  • the first control signal line L1 to the Nth control signal line L(N) sequentially input scanning signals to the first row of sub-pixels P to the Nth row of sub-pixels P, so as to control the sub-pixels P row by row.
  • the data line DL inputs the corresponding data signal into each sub-pixel (including M sub-pixels in total) in the row of sub-pixels P, so as to convert the plurality of sub-pixels P from the first Lines to the Nth line are sequentially lit to display the corresponding images, thus completing the "drawing" or display of a frame of images.
  • the plurality of sub-pixels P are re-lit in sequence from the first row to the Nth row to display the corresponding image, thus completing the "drawing" or display of the next frame of image.
  • the refresh frequency of the display device may be 60 Hz, that is, the display device may display 60 frames of images in one second, and the display period of each frame of image is 1/60 second. Due to the phenomenon of persistence of vision in the human eye, it may happen that when a still picture is displayed, although the human eye cannot perceive any change in the image on the display device within one second, in fact, The image on the display unit has been repeated 60 times. When the refresh rate of the display device is high enough, the human eye will not perceive the flicker caused by the screen switching.
  • the display process of the display device includes a plurality of frame periods, and each frame period completes the scanning of N rows of sub-pixels P, so as to display one frame of image.
  • the N-stage shift register circuit included in the gate driving circuit outputs the scanning signals in sequence, that is, the scanning signals are sequentially output from the first-stage shift register to the N-th stage shift register, so as to scan each control signal line L line by line.
  • the following takes the first-stage shift register circuit RS1 in the gate drive circuit G shown in FIG. 2B (which is formed by cascading the shift register circuits of FIG. 7 ) as an example, and combines FIG. 12 and FIG.
  • the timing chart in FIG. 14 illustrates the driving method of the shift register circuit of the present disclosure within one image frame (one frame period).
  • the driving method of the shift register circuit RS includes: a frame period includes a data holding stage, and the data holding stage includes a plurality of denoising sub-stages and a plurality of denoising and enhancing sub-stages.
  • the denoising sub-stage alternates with the denoising and strengthening sub-stage, which is equivalent to inserting multiple de-noising and strengthening sub-stages in the data retention stage.
  • the first control sub-circuit 11 of the shift register circuit RS is under the influence of the first DC voltage signal from the first clock signal terminal CK1 and the second DC voltage signal from the second clock signal terminal CB1 , the voltage of the first node N1 is adjusted to the turn-on voltage.
  • the first control sub-circuit 11 uses the first DC voltage signal and the second DC voltage signal, which can reduce the power consumption of the display device 200 .
  • the first control sub-circuit 11 controls the voltage of the first node N1 to The voltage is kept as the turn-on voltage, which can prevent the voltage of the first node N1 from changing due to the leakage of the transistor in the shift register circuit RS, thereby ensuring the stable turn-on of the first output sub-circuit 12 .
  • the voltage of the first node N1 is maintained at the turn-on voltage
  • the first output sub-circuit 12 of the shift register circuit RS is turned on under the control of the turn-on voltage of the first node N1, and transmits the signal from the first node N1 to the signal output terminal Oput.
  • the first voltage signal of the voltage terminal VSS is the first voltage signal of the voltage terminal VSS.
  • the duration of the denoising sub-stage in the data retention stage should be as long as possible relative to the duration of the de-noising enhancement sub-stage, so as to achieve the effect of reducing the power consumption of the display device 200 .
  • the duration of the denoising sub-phase may be 0.1ms ⁇ 1000ms, eg, 0.1ms, 10ms, 500ms, 800ms or 1000ms.
  • the leakage level of the transistors in the shift register circuit RS the number of the denoising and enhancing sub-stages inserted in the data retention stage can be adjusted.
  • the stable turn-on of the circuit 12 can reduce the power consumption of the display device 200 .
  • 1-20 denoising and enhancing sub-stages may be inserted every 1 ms, for example, 1 de-noising and enhancing sub-stage is inserted every 1 ms, 5 de-noising and enhancing sub-stages are inserted every 1 ms, and every 1 ms. Insert 10 denoising enhancement sub-stages, 15 denoising enhancement sub-stages every 1ms, or 20 denoising enhancement sub-stages every 1ms.
  • insertion pulse refers to the above-mentioned drive method of the shift register circuit RS of the present disclosure
  • 60Hz Clock refers to the drive method of the shift register circuit in the related art, that is, when the refresh frequency of the display device is 60Hz, Adopt the clock signal (AC voltage signal) to drive the shift register circuit
  • VSS refers to the method of driving the shift register circuit RS with the first voltage signal from the first voltage terminal VSS
  • VDD refers to the method of using the first voltage signal from the first voltage terminal VSS to drive the shift register circuit RS
  • a method of driving the shift register circuit RS with the second voltage signal of the two voltage terminals VDD A method of driving the shift register circuit RS with the second voltage signal of the two voltage terminals VDD.
  • the voltage of the output noise of the shift register circuit RS is also 0V, and the gate driving circuit
  • the overall power consumption is 9.5mW, which is 52mW compared to the "60Hz Clock" driving method, and the energy saving ratio reaches 82%. Therefore, the method for driving the shift register circuit RS of the present disclosure can reduce the power consumption of the display device 200 while ensuring that the output noise of the shift register circuit RS is small.
  • the shift register circuit RS is driven by the DC voltage signal, that is, the shift register circuit RS is driven by the first voltage signal from the first voltage terminal VSS, and the shift register circuit RS outputs noise.
  • the voltage is
  • the shift register circuit RS is driven by the second voltage signal from the second voltage terminal VDD, and the voltage range of the output noise of the shift register circuit RS is
  • the first control sub-circuit 11 includes a holding unit 111 and a first control unit 112, and the first control sub-circuit 11 receives the first DC voltage signal from the first clock signal terminal CK1 and the second clock signal Under the influence of the second DC voltage signal of the terminal CB1, the voltage of the first node is adjusted to the turn-on voltage, including:
  • the holding unit 111 is turned off under the influence of the first DC voltage signal from the first clock signal terminal CK1 and the initial voltage signal from the initial signal terminal STV.
  • the first control unit 112 adjusts the voltage of the first node N1 to the turn-on voltage under the influence of the second DC voltage signal from the second clock signal terminal CB1.
  • the denoising sub-stage includes:
  • the first DC voltage signal is a low level signal
  • the second DC voltage signal is a low level signal.
  • the first transistor T1 is turned off under the control of the first DC voltage signal, and the first capacitor C1 adjusts the voltage of the first node N1 to the turn-on voltage under the action of the second DC voltage signal according to the bootstrap action of the capacitor.
  • the first control sub-circuit 11 maintains the voltage of the first node N1 as an on voltage, including :
  • the first control unit 112 adjusts the voltage of the first node N1 under the influence of the second clock signal from the second clock signal terminal CB1.
  • the holding unit 111 is turned on under the control of the first clock signal from the first clock signal terminal CK1, and keeps the voltage of the first node N1 at the turn-on voltage.
  • the denoising and enhancing sub-stage includes:
  • the second clock signal is a high-level signal
  • the first clock signal is a low-level signal.
  • the first capacitor C1 adjusts the voltage of the first node N1 under the action of the second clock signal.
  • the first transistor T1 is turned on under the control of the first clock signal, and keeps the voltage of the first node N1 at the turn-on voltage.
  • the data retention stage includes:
  • the tenth transistor T10 is turned on under the control of the turn-on voltage of the first node N1, and transmits the first voltage signal from the first voltage terminal VSS to the signal output terminal Oput.
  • one frame period further includes: a data refresh phase S before the data retention phase.
  • the data refresh stage S includes a first stage t1 , a second stage t2 , a third stage t3 and a fourth stage t4 .
  • the second control sub-circuit 13 of the shift register circuit RS includes a third control unit 131, an adjustment unit 132, a fourth control unit 133 and a fifth control unit 134.
  • the third control unit 131 Under the control of the first control signal (third clock signal) from the first control signal terminal CON1 (third clock signal terminal CK2), the first voltage signal from the first voltage terminal VSS is transmitted to the first controller. circuit 11.
  • the fourth control unit 133 transmits the fourth clock signal from the fourth clock signal terminal CB2 to the third node N3 under the control of the third control unit 131 .
  • the third control unit 131 includes the fourth transistor T4 and the fifth transistor T5
  • the fourth control unit 133 includes the sixth transistor T6
  • the first stage t1 and the third stage t3 includes:
  • the fourth transistor T4 is turned off under the control of the first control sub-circuit 11. It can also be said that the first control sub-circuit 11 controls the voltage of the first node N1 to be at a high level, and the fourth transistor T4 is at the voltage of the first node N1. Controlled cutoff.
  • the third clock signal is a low level signal
  • the fifth transistor T5 is turned on under the control of the third clock signal from the third clock signal terminal CK2, and transmits the first voltage signal from the first voltage terminal VSS to the first control Subcircuit 11.
  • the first voltage signal output by the third control unit 131 is a low level signal
  • the sixth transistor T6 is turned on under the control of the first voltage signal output by the third control unit 131
  • the fourth clock signal terminal CB2 from the fourth clock signal terminal CB2 is turned on.
  • the clock signal is transmitted to the third node N3. Since the fourth clock signal is a high level signal, the voltage of the third node N3 is a high level.
  • the adjustment unit 132 adjusts the voltage output by the third control unit 131 according to the voltage of the third node N3.
  • the fourth control unit 133 is kept on under the control of the third control unit 131, and transmits the fourth clock signal from the fourth clock signal terminal CB2 to the third node N3.
  • the fifth control unit 134 transmits the voltage of the third node N3 to the second node N2 under the control of the second control signal from the second control signal terminal CON2.
  • the second output sub-circuit 14 is turned on under the control of the turn-on voltage of the second node N2, and transmits the second voltage signal from the second voltage terminal VDD to the signal output terminal Oput.
  • the second stage t2 and the fourth stage t4 include:
  • the second capacitor C2 adjusts the voltage output by the third control unit 131 under the action of the voltage of the third node N3 according to the bootstrap action of the capacitor.
  • the first voltage signal output by the third control unit 131 is a low level signal.
  • the fourth clock signal is a low level signal, therefore, the voltage of the third node N3 is a low level, and the second capacitor C2 pulls down under the action of the voltage of the third node N3
  • the voltage output by the third control unit 131 keeps the sixth transistor T6 turned on, so as to transmit the fourth clock signal from the fourth clock signal terminal CB2 to the third node N3.
  • the seventh transistor T7 is turned on under the control of the fourth clock signal from the fourth clock signal terminal CB2, and transmits the voltage of the third node N3 to the second node N2, so that the voltage of the second node N2 is at a low level.
  • the ninth transistor T9 is turned on under the control of the turn-on voltage of the second node N2, and transmits the second voltage signal from the second voltage terminal VDD to the signal output terminal Oput.
  • each transistor used in the shift register circuit in the embodiment of the present disclosure may be a thin film transistor, a field effect transistor, or other switching devices with the same characteristics.
  • the control electrode of the transistor is the gate of the transistor
  • the first electrode is one of the source electrode and the drain electrode of the transistor
  • the second electrode is the other one of the source electrode and the drain electrode of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure Diodes may be indistinguishable in structure.
  • the transistors are all described by taking a P-type transistor as an example. It should be noted that the embodiments of the present disclosure include but are not limited to this.
  • one or more transistors in the shift register provided by the embodiments of the present disclosure may also adopt N-type transistors, and it is only necessary to refer to the respective poles of the transistors of the selected type with respect to the respective poles of the corresponding transistors in the embodiments of the present disclosure Corresponding connections, and the corresponding high voltage or low voltage can be provided at the corresponding voltage terminal.
  • the first capacitor C1 , the second capacitor C2 and the third capacitor C3 may be capacitor devices that are separately fabricated through technological processes, for example, the capacitor devices are realized by fabricating special capacitor electrodes. This can be achieved by metal layers, semiconductor layers (eg, doped polysilicon), and the like.
  • the capacitor can also be a parasitic capacitance between the thin film transistors, or realized by the thin film transistor itself and other devices and lines, or realized by using the parasitic capacitance between the lines of the circuit itself.
  • the first node N1 , the second node N2 , the third node N3 , the fourth node N4 , the fifth node N5 and the sixth node N6 do not represent actual components, but represent The meeting point of the relevant electrical connections in the circuit diagram, that is, the nodes are nodes equivalent to the meeting points of the relevant electrical connections in the circuit diagram.

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Abstract

一种移位寄存器电路(RS)，包括第一控制子电路(11)和第一输出子电路(12)，第一控制子电路(11)与第一时钟信号端(CK1)、第二时钟信号端(CB1)和第一节点(N1)耦接；第一控制子电路(11)被配置为，在来自第一时钟信号端(CK1)的第一直流电压信号和来自第二时钟信号端(CB1)的第二直流电压信号的影响下，将第一节点(N1)的电压调整为开启电压；以及在来自第一时钟信号端(CK1)的第一时钟信号和来自第二时钟信号端(CB1)的第二时钟信号的影响下，将第一节点(N1)的电压保持为开启电压；第一输出子电路(12)与第一节点(N1)、第一电压端(VSS)和信号输出端(Oput)耦接；第一输出子电路(12)被配置为，在第一节点(N1)的开启电压的控制下开启，将来自第一电压端(VSS)的第一电压信号传输至信号输出端(Oput)。

Description

移位寄存器电路及其驱动方法、栅极驱动电路、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器电路及其驱动方法、栅极驱动电路、显示装置。
背景技术
显示装置中的像素驱动电路接收数据信号，数据信号所携带的像素电压可用于控制每个像素的发光亮度。由于像素驱动电路存在漏电的现象，会导致像素电压随时间变化。
目前，为保证静态画面的亮度在合理的范围内波动，需要刷新输入像素驱动电路的数据信号。通过降低数据信号的刷新频率，可降低显示面板的功耗。
公开内容
一方面，提供一种移位寄存器电路，包括第一控制子电路和第一输出子电路。
其中，第一控制子电路与第一时钟信号端、第二时钟信号端和第一节点耦接；所述第一控制子电路被配置为，在来自所述第一时钟信号端的第一直流电压信号，和来自所述第二时钟信号端的第二直流电压信号的影响下，将所述第一节点的电压调整为开启电压；以及，在来自所述第一时钟信号端的第一时钟信号，和来自所述第二时钟信号端的第二时钟信号的影响下，将所述第一节点的电压保持为所述开启电压。
第一输出子电路与所述第一节点、第一电压端和信号输出端耦接；所述第一输出子电路被配置为，在所述第一节点的开启电压的控制下开启，将来自所述第一电压端的第一电压信号传输至所述信号输出端。
在一些实施例中，移位寄存器电路还包括第二控制子电路和第二输出子电路。
其中，第二控制子电路与所述第一节点、所述第一电压端、第一控制信号端、第二控制信号端、第四时钟信号端、第二电压端、第二节点和所述第一控制子电路耦接；所述第二控制子电路被配置为，在来自所述第一控制信号端的第一控制信号和来自所述第二控制信号端的第二控制信号的控制下，并在所述第一控制子电路、来自所述第一电压端的第一电压信号和来自所述第四时钟信号端的第四时钟信号的影响下，将所述第二节点的电压调整为开启电压。
第二输出子电路与所述第二节点、所述第二电压端和所述信号输出端耦接；所述第二输出子电路被配置为，在所述第二节点的开启电压的控制下开启，将来自所述第二电压端的第二电压信号传输至所述信号输出端。
在一些实施例中，所述第一控制子电路包括保持单元和第一控制单元。
其中，保持单元与所述第一时钟信号端、所述第一节点和初始信号端耦接；所述保持单元被配置为，在来自所述第一时钟信号端的第一直流电压信号，和来自所述初始信号端的初始电压信号的影响下关闭；以及，在来自所述第一时钟信号端的第一时钟信号的控制下开启，将所述第一节点的电压保持为所述开启电压。
第一控制单元与所述第二时钟信号端和所述第一节点耦接；所述第一控制单元被配置为，在来自所述第二时钟信号端的第二直流电压信号的影响下，将所述第一节点的电压调整为开启电压；以及，在来自所述第二时钟信号端的第二时钟信号的影响下，调整所述第一节点的电压。
在一些实施例中，所述保持单元包括第一晶体管，所述第一晶体管的控制极与所述第一时钟信号端耦接，所述第一晶体管的第一极与所述初始信号端耦接，所述第一晶体管的第二极与所述第一节点耦接。
所述第一控制单元包括第一电容器，所述第一电容器的第一端与所述第二时钟信号端耦接，所述第一电容器的第二端与所述第一节点耦接。
在一些实施例中，所述第一控制子电路还包括第一防漏电单元，与所述第一电压端耦接，且所述保持单元通过所述第一防漏电单元与所述第一节点耦接；所述第一防漏电单元被配置为，在来自所述第一电压端的第一电压信号的控制下，保持所述第一节点的电压。
在一些实施例中，所述第一防漏电单元包括第十一晶体管，所述第十一晶体管的控制极与所述第一电压端耦接，所述第十一晶体管的第一极与所述第一节点耦接，所述第十一晶体管的第二极与所述保持单元耦接。
在一些实施例中，所述第一控制子电路还包括第二控制单元，与所述保持单元、所述第二控制子电路、第四时钟信号端和所述第二电压端耦接；所述第二控制单元被配置为，在来自所述第四时钟信号端的第四时钟信号，和所述第二控制子电路的控制下，将来自所述第二电压端的第二电压信号传输至所述保持单元。
在一些实施例中，所述第二控制单元包括第二晶体管和第三晶体管。
其中，所述第二晶体管的控制极与所述第二控制子电路耦接，所述第二晶体管的第一极与所述第二电压端耦接。所述第三晶体管的控制极与所述第 四时钟信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第二极耦接，所述第三晶体管的第二极与所述保持单元耦接。
在一些实施例中，所述第二控制子电路包括第三控制单元、第四控制单元、调整单元和第五控制单元。
其中，第三控制单元与所述第一控制子电路、所述第一控制信号端和所述第一电压端耦接；所述第三控制单元被配置为，在来自所述第一控制信号端的第一控制信号的控制下，将来自所述第一电压端的第一电压信号传输至所述第一控制子电路。
第四控制单元与所述第三控制单元、所述第四时钟信号端和第三节点耦接；所述第四控制单元被配置为，在所述第三控制单元的控制下，将来自所述第四时钟信号端的第四时钟信号传输至所述第三节点。
调整单元与所述第三控制单元和所述第三节点耦接；所述调整单元被配置为，根据所述第三节点的电压，调整所述第三控制单元所输出的电压。
第五控制单元与所述第一节点、所述第二节点、所述第三节点、所述第二电压端和第二控制信号端耦接；所述第五控制单元被配置为，在来自所述第二控制信号端的第二控制信号的控制下，将所述第三节点的电压传输至所述第二节点；以及，在所述第一节点的电压的控制下，将来自所述第二电压端的第二电压信号传输至所述第二节点。
在一些实施例中，所述第三控制单元包括第四晶体管和第五晶体管。
其中，所述第四晶体管的控制极与所述第一控制子电路耦接，所述第四晶体管的第一极与所述第一控制信号端耦接，所述第四晶体管的第二极与所述第一控制子电路耦接。所述第五晶体管的控制极与所述第一控制信号端耦接，所述第五晶体管的第一极与所述第一电压端耦接，所述第五晶体管的第二极与所述第一控制子电路耦接。
所述第四控制单元包括第六晶体管，所述第六晶体管的控制极与所述第四晶体管的第二极耦接，所述第六晶体管的第一极与所述第四时钟信号端耦接，所述第六晶体管的第二极与所述第三节点耦接。
所述调整单元包括第二电容器，所述第二电容器的第一端与所述第三节点耦接，所述第二电容器的第二端与所述第四晶体管的第二极耦接。
所述第五控制单元包括第七晶体管和第八晶体管。
其中，所述第七晶体管的控制极与所述第二控制信号端耦接，所述第七晶体管的第一极与所述第三节点耦接，所述第七晶体管的第二极与所述第二节点耦接。所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管 的第一极与所述第二电压端耦接，所述第八晶体管的第二极与所述第二节点耦接。
在一些实施例中，所述第二控制子电路还包括第二防漏电单元，与所述第一电压端耦接，且所述第三控制单元通过所述第二防漏电单元与所述第四控制单元耦接；所述第二防漏电单元被配置为，在来自所述第一电压端的第一电压信号的控制下，保持所述第四控制单元的开启。
在一些实施例中，所述第二防漏电单元包括第十二晶体管，所述第十二晶体管的控制极与所述第一电压端耦接，所述第十二晶体管的第一极与所述第四控制单元耦接，所述第十二晶体管的第二极与所述第三控制单元耦接。
在一些实施例中，所述第一控制信号端为第一时钟信号端或第三时钟信号端；和/或，所述第二控制信号端为第二时钟信号端或第四时钟信号端。
所述第一时钟信号端被配置为，在一个帧周期的数据刷新阶段输出第一时钟信号，在一个帧周期的数据保持阶段的去噪子阶段输出第一直流电压信号，在一个帧周期的数据保持阶段的去噪加强子阶段输出第一时钟信号。所述第二时钟信号端被配置为，在所述数据刷新阶段输出第二时钟信号，在所述数据保持阶段的去噪子阶段输出第二直流电压信号，在所述数据保持阶段的去噪加强子阶段输出第二时钟信号。所述第三时钟信号端被配置为，在所述数据刷新阶段输出第三时钟信号，在所述数据保持阶段输出第三直流电压信号。所述第四时钟信号端被配置为，在所述数据刷新阶段输出第四时钟信号，在所述数据保持阶段输出第四直流电压信号。
在一些实施例中，所述第一时钟信号与所述第二时钟信号大致互为反相信号，所述第三时钟信号和所述第四时钟信号大致互为反相信号；所述第一直流电压信号与所述第二直流电压信号均为低电平信号，所述第三直流电压信号与所述第四直流电压信号均为高电平信号。
在一些实施例中，所述第二输出子电路包括第九晶体管和第三电容器。
其中，所述第九晶体管的控制极与所述第二节点耦接，所述第九晶体管的第一极与所述第二电压端耦接，所述第九晶体管的第二极与所述信号输出端耦接。所述第三电容器的第一端与所述第二电压端耦接，所述第三电容器的第二端与所述第二节点耦接。
在一些实施例中，所述第一输出子电路包括第十晶体管，所述第十晶体管的控制极与所述第一节点耦接，所述第十晶体管的第一极与所述第一电压端耦接，所述第十晶体管的第二极与所述信号输出端耦接。
另一方面，提供一种栅极驱动电路，包括多个如上述任一实施例所述的 移位寄存器电路，多个所述移位寄存器电路依次级联。
在一些实施例中，栅极驱动电路还包括三条或四条时钟信号线，与所述栅极驱动电路的各移位寄存器电路耦接。
另一方面，提供一种显示装置，包括如上述任一实施例所述的栅极驱动电路和多条控制信号线，所述栅极驱动电路中的每个移位寄存器电路与至少一条控制信号线耦接。
另一方面，提供一种移位寄存器电路的驱动方法，应用于如上述任一实施例所述的移位寄存器电路，所述驱动方法包括：一个帧周期包括数据保持阶段，所述数据保持阶段包括交替出现的多个去噪子阶段和多个去噪加强子阶段。
在所述去噪子阶段，所述移位寄存器电路的第一控制子电路在来自第一时钟信号端的第一直流电压信号，和来自第二时钟信号端的第二直流电压信号的影响下，将第一节点的电压调整为开启电压。
在所述去噪加强子阶段，所述第一控制子电路在来自所述第一时钟信号端的第一时钟信号，和来自所述第二时钟信号端的第二时钟信号的影响下，将所述第一节点的电压保持为所述开启电压。
在所述数据保持阶段，所述移位寄存器电路的第一输出子电路在所述第一节点的开启电压的控制下开启，向信号输出端传输来自所述第一电压端的第一电压信号。
在一些实施例中，所述第一控制子电路包括保持单元和第一控制单元，所述第一控制子电路在来自第一时钟信号端的第一直流电压信号，和来自第二时钟信号端的第二直流电压信号的影响下，将第一节点的电压调整为开启电压，包括：
所述保持单元在来自所述第一时钟信号端的第一直流电压信号，和来自所述初始信号端的初始电压信号的影响下关闭；所述第一控制单元在来自所述第二时钟信号端的第二直流电压信号的影响下，将所述第一节点的电压调整为所述开启电压。
所述第一控制子电路在来自所述第一时钟信号端的第一时钟信号，和来自所述第二时钟信号端的第二时钟信号的影响下，将所述第一节点的电压保持为所述开启电压，包括：
所述第一控制单元在来自所述第二时钟信号端的第二时钟信号的影响下，调整所述第一节点的电压；所述保持单元在来自所述第一时钟信号端的第一时钟信号的控制下开启，将所述第一节点的电压保持为所述开启电压。
在一些实施例中，一个帧周期还包括数据刷新阶段，所述数据刷新阶段包括第一阶段、第二阶段、第三阶段和第四阶段。
所述移位寄存器电路的第二控制子电路包括第三控制单元、第四控制单元、第五控制单元和调整单元，在所述第一阶段和所述第三阶段，所述第三控制单元在来自第一控制信号端的第一控制信号的控制下，将来自所述第一电压端的第一电压信号传输至所述第一控制子电路；所述第四控制单元在所述第三控制单元的控制下，将来自所述第四时钟信号端的第四时钟信号传输至所述第三节点。
在所述第二阶段和所述第四阶段，所述调整单元根据所述第三节点的电压，调整所述第三控制单元所输出的电压；所述第四控制单元在所述第三控制单元的控制下，将来自所述第四时钟信号端的第四时钟信号传输至所述第三节点；所述第五控制单元在来自所述第二控制信号端的第二控制信号的控制下，将所述第三节点的电压传输至所述第二节点；第二输出子电路在所述第二节点的开启电压的控制下开启，将来自所述第二电压端的第二电压信号传输至所述信号输出端。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开的一些实施例的显示装置的结构图；
图2A为根据本公开的一些实施例的显示面板的一种结构图；
图2B为根据本公开的一些实施例的显示面板的另一种结构图；
图3为根据本公开的一些实施例的像素驱动电路的电路图；
图4为根据本公开的一些实施例的移位寄存器电路的一种结构图；
图5为根据本公开的一些实施例的移位寄存器电路的另一种结构图；
图6为根据本公开的一些实施例的移位寄存器电路的又一种结构图；
图7为根据本公开的一些实施例的一种移位寄存器电路的电路图；
图8为根据本公开的一些实施例的另一种移位寄存器电路的电路图；
图9为根据本公开的一些实施例的移位寄存器电路的又一种结构图；
图10为根据本公开的一些实施例的又一种移位寄存器电路的电路图；
图11为根据本公开的一些实施例的又一种移位寄存器电路的电路图；
图12为根据本公开的一些实施例的移位寄存器电路的驱动方法的时序图；
图13为根据本公开的一些实施例的移位寄存器电路的驱动方法的仿真实验的模拟图；
图14为根据本公开的一些实施例的移位寄存器电路的驱动方法在数据刷新阶段的时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员 考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
如图1所示，本公开的一些实施例提供一种显示装置200，包括显示面板100。该显示装置200可以为有机电致发光(Organic Light-Emitting Diode，简称OLED)显示装置。
上述显示装置200可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
本公开以下实施例以上述显示面板100为OLED显示面板为例进行说明。
如图2A所示，上述显示面板100包括：显示区AA(Active Area，有效显示区)和位于显示区AA的至少一侧的周边区BB。图1中以周边区BB围绕显示区AA一圈进行示意。
上述显示面板100包括设置在显示区AA中的多种颜色的亚像素(sub pixel)P，该多种颜色的亚像素至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素，第一颜色、第二颜色和第三颜色可以为三基色(例如红色、绿色和蓝色)。
为了方便说明，本公开中上述多个亚像素P是以矩阵形式排列为例进行的说明。在此情况下，沿水平方向X排列成一排的亚像素P称为一行亚像素；沿竖直方向Y排列成一排的亚像素P称为一列亚像素。
如图3所示，每一亚像素P中均设置有像素驱动电路S，该像素驱动电路S包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和电容器Cst。
其中，第一晶体管T1的控制极与第二节点N2耦接，第一晶体管T1的第一极与第一节点N1耦接；第二晶体管T2的控制极与第一扫描信号端GATE1耦接，第二晶体管T2的第一极与数据信号端DATA耦接，第二晶体管T2的第二极与第一节点N1耦接；第三晶体管T3的控制极与第二扫描信号端GATE2耦接，第三晶体管T3的第一极与第二节点N2耦接，第三晶体管T3的第二极与第一晶体管T1的第二极耦接；第四晶体管T4的控制极与第三扫描信号端GATE3耦接，第四晶体管T4的第一极与初始信号端VINT耦接，第四晶体管T4的第二极与第二节点N2耦接；第五晶体管T5的控制极与发光控制信号端EM耦接，第五晶体管T5的第一极与第一电压信号端VDD耦接，第五晶体管T5的第二极与第一节点N1耦接；第六晶体管T6的控制极与发光控制信号端EM耦接，第六晶体管T6的第一极与第一晶体管T1的第二极耦接；第七晶体管T7的控制极与第四扫描信号端GATE4耦接，第七晶体管T7的第一极与初始信号端VINT耦接，第七晶体管T7的第二极与第六晶体管T6的第二极耦接；电容器Cst的第一端与第一电压信号端VDD耦接，电容器Cst的第二端与第二节点N2耦接。
亚像素P还包括发光器件D，发光器件D的第一极与第六晶体管T6的第二极耦接，发光器件D的第二极与第二电压信号端VSS耦接。其中，位于同一行的像素驱动电路S与同一条控制信号线L耦接，位于同一列的像素驱动电路S与同一条数据线DL(Data Line)耦接，以驱动亚像素P中的发光器件D发光。
需要说明的是，像素驱动电路S不限于图3中示出的电路结构，还可以是其它电路结构，此处不再列举。
像素驱动电路S中所包括的晶体管可以均为N型晶体管，也可以均为P型晶体管，还可以包括N型和P型两种晶体管，可视实际需要设计。另外，像素驱动电路S中所包括的晶体管可以均为低温多晶硅(Low Temperature Poly-silicon，简称LTPS)晶体管，也可以均为氧化物(Oxide)晶体管，还可以包括低温多晶硅和氧化物两种晶体管。
在一些实施例中，由于控制亚像素亮度的电压会由于像素驱动电路S中晶体管漏电而随时间变化，因此为了使保持像素亮度波动在合理的范围内，在显示静态画面时仍然需要刷新数据。为了降低显示静态画面时的功耗，降 低刷新频率是比较有效的方法，同时还需要保持显示质量，就需要减少像素驱动电路S中晶体管的漏电速度。
为解决上述问题，在一些实施例中，可结合低温多晶硅和氧化物的优良特性，采用低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)工艺，将像素驱动电路S中用于驱动的晶体管(例如图3中的第一晶体管T1、第五晶体管T5和第六晶体管T6)，设置为氧化物晶体管，利用氧化物半导体具有超低漏电的特性，可改善晶体管漏电的现象；将像素驱动电路S中用于开关的晶体管(例如第二晶体管T2、第三晶体管T3、第四晶体管T4和第七晶体管T7)，设置为低温多晶硅晶体管，保证亚像素P的充电速度和较小的寄生电容。
参考图2A所示，显示面板100的周边区BB设置有至少一个栅极驱动电路G和数据驱动电路DD。在一些实施例中，栅极驱动电路G可以设置在沿控制信号线L的延伸方向上的侧边，数据驱动电路DD可以设置在沿数据线DL的延伸方向上的侧边，以驱动显示面板100中的像素驱动电路S，从而驱动发光器件发光，使显示面板100进行显示。
示例性地，栅极驱动电路G可以是用于向像素驱动电路S传输发光控制信号Em的栅极驱动电路，也可以是用于向像素驱动电路S传输扫描信号Gate的栅极驱动电路。
例如，如图2A所示，显示面板100的周边区BB设置有第一栅极驱动电路01、第二栅极驱动电路02和第三栅极驱动电路03。结合图3，第一栅极驱动电路G被配置为向像素驱动电路S的发光控制信号端EM传输发光控制信号Em；第二栅极驱动电路02被配置为向像素驱动电路S的第二扫描信号端GATE2传输第二扫描信号Gate2，以及向第三扫描信号端GATE3传输第三扫描信号Gate3；第三栅极驱动电路03被配置为向像素驱动电路S的第一扫描信号端GATE1传输第一扫描信号Gate1，以及向第四扫描信号端GATE4传输第四扫描信号Gate4。
显示面板100所包括的栅极驱动电路G的数量可以视具体情况而定，以上仅是示例。
在一些实施例中，栅极驱动电路G可以为GOA(英文全称：Gate Driver on Array，中文全称：阵列基板行驱动)电路，即，栅极驱动电路G直接集成在显示面板100的阵列基板上。以下实施例均是以栅极驱动电路G为GOA电路为例进行说明。
需要说明的是的，图2A仅是示意的，以在显示面板100的周边区BB的 单侧设置栅极驱动电路G，从单侧逐行依次驱动各控制信号线L，即以单侧驱动为例进行说明的。在另一些实施例中，可以在显示面板100的周边区BB中沿控制信号线L的延伸方向上的两个侧边，分别设置栅极驱动电路G，通过两个栅极驱动电路G同时从两侧，逐行依次驱动各控制信号线L，即双侧驱动。在另一些实施例中，可以在显示面板100的周边区BB中沿控制信号线L的延伸方向上的两个侧边，分别设置栅极驱动电路G，通过两个栅极驱动电路G交替从两侧，逐行依次驱动各控制信号线L，即交叉驱动。本公开以下实施例均是以单侧驱动为例进行说明的。
本公开的一些实施例中，栅极驱动电路G包括多个依次级联的移位寄存器电路，每级移位寄存器电路与至少一条控制信号线L耦接。
示例性地，如图2A所示，N级移位寄存器电路(RS1、RS2……RS(N))，与N条控制信号线(L1、L2……L(N))一一对应耦接，每级移位寄存器电路与一条控制信号线L耦接，每条控制信号线L与一行亚像素P耦接，即每级移位寄存器电路驱动一行亚像素P。其中，N为正整数。在另一些实施例中，每条控制信号线L可与相邻两行亚像素P耦接，即除第一级和最后一级移位寄存器电路外，每级移位寄存器电路可驱动两行亚像素P。
例如，如图2A所示，沿控制信号线L的延伸方向，在第二栅极驱动电路02位于第一栅极驱动电路01和第三栅极驱动电路03之间的情况下，第二栅极驱动电路02中除第一级和最后一级移位寄存器电路外，每级移位寄存器电路驱动相邻两行亚像素P。并且，第三栅极驱动电路03中除第一级和最后一级移位寄存器电路外，每级移位寄存器电路驱动相邻两行亚像素P。
又例如，沿控制信号线L的延伸方向，在第三栅极驱动电路03位于第一栅极驱动电路01和第二栅极驱动电路02之间的情况下，第二栅极驱动电路02中的每级移位寄存器电路驱动一行亚像素P，且第三栅极驱动电路03中的每级移位寄存器电路驱动一行亚像素P。
在一些实施例中，如图2B所示，栅极驱动电路G的移位寄存器电路(RS1、RS2……RS(N))中设置有信号输出端Output(下文以及附图均简写为Oput)，通过信号输出端Oput向与其耦接的控制信号线L输出扫描信号。
另外，在一些实施例中，如图2B所示，栅极驱动电路G的移位寄存器电路(RS1、RS2……RS(N))还设置有信号输入端Input(下文以及附图均简写为Iput)，并且栅极驱动电路G中各个移位寄存器电路的电路结构相同。
在此基础上，栅极驱动电路G中各个移位寄存器电路的级联结构可为：
第一级移位寄存器电路RS1的信号输入端Iput与起始信号端STV连接； 除第一级移位寄存器电路RS1以外，其它移位寄存器电路的信号输入端Iput与位于其前一个的移位寄存器电路的信号输出端Oput连接。
在一些实施例中，如图2B所示，栅极驱动电路G的移位寄存器电路(RS1、RS2……RS(N))还设置有第一时钟信号端CK1、第二时钟信号端CB1、第三时钟信号端CK2和第四时钟信号端CB2，分别与信号线耦接，以接收信号线传输的电压信号。
在相关技术中，显示装置工作在低频模式下，显示装置中的栅极驱动电路采用时钟保持的方式驱动，以确保在显示装置显示画面的情况下，栅极驱动电路输出的控制信号的电位有效。但是，采用时钟保持的方式驱动所需要的时钟信号，为高低电平切换的交流电压信号，导致显示装置的功耗较大；并且，由于栅极驱动电路中的晶体管存在漏电的现象，也会影响其输出的扫描信号的电位的有效性。
为解决上述问题，如图4所示，本公开的一些实施例还提供了一种移位寄存器电路RS，包括第一控制子电路11和第一输出子电路12。
其中，第一控制子电路11与第一时钟信号端CK1、第二时钟信号端CB1和第一节点N1耦接。第一控制子电路11被配置为，在来自第一时钟信号端CK1的第一直流电压信号，和来自第二时钟信号端CB1的第二直流电压信号的影响下，将第一节点N1的电压调整为开启电压；以及，在来自第一时钟信号端CK1的第一时钟信号，和来自第二时钟信号端CB1的第二时钟信号的影响下，将第一节点N1的电压保持为开启电压。
可以理解的是，“将第一节点N1的电压调整为开启电压”是指，使第一节点N1的电压由不等于开启电压，变化为等于开启电压。“将第一节点N1的电压保持为开启电压”是指，使第一节点N1的电压保持为开启电压，第一节点N1的电压不发生变化。
需要说明的是，如图12所示，一个帧周期包括数据保持阶段，数据保持阶段包括多个去噪子阶段和多个去噪加强子阶段，去噪子阶段与去噪加强子阶段交替。
其中，第一时钟信号端CK1被配置为，在去噪子阶段输出第一直流电压信号，在去噪加强子阶段输出第一时钟信号。第二时钟信号端CB1被配置为，在去噪子阶段输出第二直流电压信号，在去噪加强子阶段输出第二时钟信号。并且，第一直流电压信号与第二直流电压信号可均为低电平信号，第一时钟信号与第二时钟信号大致互为反相信号。
第一控制子电路11被配置为，在去噪子阶段，在第一直流电压信号和第 二直流电压信号的影响下，将第一节点N1的电压调整为开启电压；以及，在去噪加强子阶段，在来自第一时钟信号和第二时钟信号的影响下，将第一节点N1的电压保持为开启电压。
如图4所示，第一输出子电路12与第一节点N1、第一电压端VSS和信号输出端Oput耦接。第一输出子电路12被配置为，在第一节点N1的开启电压的控制下开启，将来自第一电压端VSS的第一电压信号传输至信号输出端Oput。
需要说明的是，“第一电压端VSS”被配置为传输直流电平信号，即第一电压信号为直流电平信号。第一电压端VSS可以与显示装置200中用于传输第一电压信号的VSS线耦接，以接收第一电压信号。第一电压信号可以为直流低电平信号或直流高电平信号。
可以理解的是，第一输出子电路12的开启或关闭，受第一节点N1的电压的控制。在第一节点N1的电压能够控制第一输出子电路12开启的情况下，该第一节点N1的电压即为“开启电压”。
并且，第一输出子电路12被配置为，在数据保持阶段，在第一节点N1的开启电压的控制下开启，将来自第一电压端VSS的第一电压信号传输至信号输出端Oput，信号输出端Oput输出的第一电压信号即为扫描信号，用于驱动显示面板100中的像素驱动电路S，从而驱动发光器件发光，使显示面板100进行显示。
由上可见，第一电压信号为直流低电平信号或直流高电平信号，取决于扫描信号的有效电位是低电平还是高电平。
本公开的上述实施例中的移位寄存器电路RS，在去噪子阶段，第一控制子电路11接收来自第一时钟信号端CK1的第一直流电压信号，和来自第二时钟信号端CB1的第二直流电压信号，并在第一直流电压信号和第二直流电压信号的影响下，将第一节点N1的电压调整为开启电压，以控制第一输出子电路12开启并输出扫描信号。由于显示装置200生成直流电压信号的功耗要小于生成交流电压信号的功耗，因此，相较于采用交流电压信号，上述第一控制子电路11采用第一直流电压信号和第二直流电压信号，且第一直流电压信号和第二直流电压信号均为低电平信号，可降低显示装置200的功耗。
并且，在去噪加强子阶段，通过第一控制子电路11在来自第一时钟信号端CK1的第一时钟信号，和来自第二时钟信号端CB1的第二时钟信号的影响下，将第一节点N1的电压保持为开启电压，可避免由于移位寄存器电路RS中的晶体管漏电而导致第一节点N1的电压发生变化，从而保证了第一输出子 电路12的稳定开启。
在此基础上，在一些实施例中，如图5、图7和图8所示，移位寄存器电路RS还包括第二控制子电路13和第二输出子电路14。
其中，第二控制子电路13与第一节点N1、第一电压端VSS、第一控制信号端CON1、第二控制信号端CON2、第四时钟信号端CB2、第二电压端VDD、第二节点N2和第一控制子电路11耦接。第二控制子电路13被配置为，在来自第一控制信号端CON1的第一控制信号，和来自第二控制信号端CON2的第二控制信号的控制下，并在第一控制子电路11、来自第一电压端VSS的第一电压信号和来自第四时钟信号端CB2的第四时钟信号的影响下，将第二节点N2的电压调整为开启电压。
需要说明的是，“第一控制信号端CON1”为第一时钟信号端CK1或第三时钟信号端CK2二者中的一者，“第二控制信号端CON2”为第二时钟信号端CB1或第四时钟信号端CB2二者中的一者。
如图12所示，一个帧周期还包括在数据保持阶段之前的数据刷新阶段S。第一时钟信号端CK1被配置为，在数据刷新阶段S输出第一时钟信号。第二时钟信号端CB1被配置为，在数据刷新阶段S输出第二时钟信号。第三时钟信号端CK2被配置为，在数据刷新阶段S输出第三时钟信号，在数据保持阶段输出第三直流电压信号。第四时钟信号端CB2被配置为，在数据刷新阶段S输出第四时钟信号，在数据保持阶段输出第四直流电压信号。其中，第三直流电压信号与第四直流电压信号均为高电平信号。
示例性地，图7示出了“第一控制信号端CON1”为第三时钟信号端CK2，“第二控制信号端CON2”为第四时钟信号端CB2的情形。即，第二控制子电路13与第一节点N1、第一电压端VSS、第三时钟信号端CK2、第四时钟信号端CB2、第二电压端VDD、第二节点N2和第一控制子电路11耦接。第二控制子电路13被配置为，在来自第三时钟信号端CK2的第三时钟信号，和来自第四时钟信号端CB2的第四时钟信号的控制下，并在第一控制子电路11、来自第一电压端VSS的第一电压信号和来自第四时钟信号端CB2的第四时钟信号的影响下，将第二节点N2的电压调整为开启电压。
示例性地，图8示出了“第一控制信号端CON1”为第一时钟信号端CK1，“第二控制信号端CON2”为第二时钟信号端CB1的情形。即，第二控制子电路13与第一节点N1、第一电压端VSS、第一时钟信号端CK1、第二时钟信号端CB1、第四时钟信号端CB2、第二电压端VDD、第二节点N2和第一控制子电路11耦接。第二控制子电路13被配置为，在来自第一时钟信号端 CK1的第一时钟信号，和来自第二时钟信号端CB1的第二时钟信号的控制下，并在第一控制子电路11、来自第一电压端VSS的第一电压信号和来自第四时钟信号端CB2的第四时钟信号的影响下，将第二节点N2的电压调整为开启电压。
如图5、图7和图8所示，第二输出子电路14与第二节点N2、第二电压端VDD和信号输出端Oput耦接。第二输出子电路14被配置为，在第二节点N2的开启电压的控制下开启，将来自第二电压端VDD的第二电压信号传输至信号输出端Oput。
需要说明的是，“第二电压端VDD”被配置为传输直流电平信号，即第二电压信号为直流电平信号。第二电压端VDD可以与显示装置200中用于传输第二电压信号的VDD线耦接，以接收第二电压信号。第二电压信号可以为直流高电平信号或直流低电平信号。
可以理解的是，第二输出子电路14的开启或关闭，受第二节点N2的电压的控制。在第二节点N2的电压能够控制第二输出子电路14开启的情况下，该第二节点N2的电压即为“开启电压”。
需要说明的是，第二输出子电路14被配置为，在数据保持阶段，在第二节点N2的电压的控制下关闭；以及，在数据刷新阶段S，在第二节点N2的开启电压的控制下开启，信号输出端Oput输出来自第二电压端VDD的第二电压信号，该第二电压信号用于驱动显示面板100中的像素驱动电路S关闭，从而驱动发光器件停止发光，使显示面板100停止显示。
由上可见，第二电压信号为直流高电平信号或直流低电平信号，取决于驱动像素驱动电路S关闭的有效电位是高电平还是低电平。
在此基础上，下面依次对第一控制子电路11和第二控制子电路13的具体结构进行描述。
在一些实施例中，如图6所示，第一控制子电路11包括保持单元111和第一控制单元112。
其中，保持单元111与第一时钟信号端CK1、第一节点N1和初始信号端STV耦接。保持单元111被配置为，在来自第一时钟信号端CK1的第一直流电压信号，和来自初始信号端STV的初始电压信号的影响下关闭；以及，在来自第一时钟信号端CK1的第一时钟信号的控制下开启，将第一节点N1的电压保持为开启电压。
第一控制单元112与第二时钟信号端CB1和第一节点N1耦接。第一控制单元112被配置为，在来自第二时钟信号端CB1的第二直流电压信号的影 响下，将第一节点N1的电压调整为开启电压；以及，在来自第二时钟信号端CB1的第二时钟信号的影响下，调整第一节点N1的电压。
需要说明的是，保持单元111被配置为，在去噪子阶段，在第一直流电压信号和初始电压信号的影响下关闭；并且，第一控制单元112被配置为，在第二直流电压信号的影响下，将第一节点N1的电压调整为开启电压，从而控制第一输出子电路12在去噪子阶段开启。
第一控制单元112被配置为，在去噪加强子阶段，在第二时钟信号的影响下，调整第一节点N1的电压；并且，保持单元111被配置为，在第一时钟信号的控制下开启，将第一节点N1的电压保持为开启电压，从而使第一输出子电路12在去噪加强子阶段保持开启。
综上所述，通过设置第一控制子电路11包括保持单元111和第一控制单元112，可保证第一输出子电路12在数据保持阶段的稳定开启。
在一些实施例中，如图7和图8所示，保持单元111包括第一晶体管T1，第一晶体管T1的控制极与第一时钟信号端CK1耦接，第一晶体管T1的第一极与初始信号端STV耦接，第一晶体管T1的第二极与第一节点N1(第四节点N4)耦接。第一晶体管T1被配置为，在去噪子阶段，在第一直流电压信号和初始电压信号的影响下截止；以及，在去噪加强子阶段，在第一时钟信号的控制下导通，将第一节点N1的电压保持为开启电压。
如图7和图8所示，第一控制单元112包括第一电容器C1，第一电容器C1的第一端与第二时钟信号端CB1耦接，第一电容器C1的第二端与第一节点N1耦接。第一电容器C1被配置为，在去噪子阶段，根据电容器的自举作用，在第二直流电压信号的作用下，将第一节点N1的电压调整为开启电压；以及，在去噪加强子阶段，在第二时钟信号的作用下，调整第一节点N1的电压。
示例性地，以第一晶体管T1的导通/关断类型为P型为例，结合图12，在去噪子阶段，第一时钟信号端CK1处接收的第一直流电压信号为低电平信号，第二时钟信号端CB1处接收的第二直流电压信号为低电平信号，初始信号端STV处接收的初始电压信号为低电平信号。其中，第一直流电压信号的电压与初始电压信号的电压相同。
由于P型的晶体管的阈值电压V th为负值，且P型的晶体管的导通条件为晶体管的栅源电压差(晶体管的控制极与第一极的电压差，或晶体管的控制极与第二极的电压差)V gs小于晶体管的阈值电压V th，即V gs＜V th＜0。因此，在去噪子阶段，第一晶体管T1的栅源电压差(第一晶体管T1的控制极与第 一极的电压差)V gs＝0，第一晶体管T1是截止的。
第一电容器C1被配置为，在去噪子阶段，根据电容器的自举作用，在第二直流电压信号的作用下，将第一节点N1的电压调整为开启电压，使开启电压与第二直流电压信号的电压大致相等，且为低电平。在此情况下，第一输出子电路12在第一节点N1的低电平的控制下开启。
根据前文可知，移位寄存器电路RS中的晶体管存在漏电的现象，例如，在第一节点N1的开启电压为低电平的情况下，第一晶体管T1漏电会导致第一节点N1的电压抬高，导致受第一节点N1的电压控制的第一输出子电路12关闭或无法完全开启。
为避免出现上述问题，示例性地，以第一晶体管T1的导通/关断类型为P型为例，结合图12，在去噪加强子阶段，第一时钟信号端CK1处接收的第一时钟信号为低电平信号，第二时钟信号端CB1处接收的第二时钟信号为高电平信号。
第一电容器C1被配置为，在去噪加强子阶段，在第二时钟信号的作用下，拉高第一节点N1的电压，使得第一晶体管T1的栅源电压差(第一晶体管T1的控制极与第二极的电压差)V gs＜V th＜0，第一晶体管T1导通，以将第一节点N1的电荷通过第一晶体管T1整流至初始信号端STV，拉低第一节点N1的电压，将第一节点N1的电压保持为开启电压，从而保证第一输出子电路12的稳定开启。
为进一步提高第一节点N1的电压的稳定性，保证第一输出子电路12的稳定开启，在一些实施例中，如图9所示，第一控制子电路11还包括第一防漏电单元114，第一防漏电单元114与第一电压端VSS耦接，且保持单元111通过第一防漏电单元114与第一节点N1耦接。第一防漏电单元114被配置为，在来自第一电压端VSS的第一电压信号的控制下，保持第一节点N1的电压。
可以理解的是，保持单元111通过第一防漏电单元114与第一节点N1耦接，第一防漏电单元114可用于阻断保持单元111与第一节点N1之间的连接，避免由于保持单元111中的第一晶体管T1漏电，而导致第一节点N1的电压发生变化，从而保持第一节点N1的电压。
在一些实施例中，如图10所示，第一防漏电单元114包括第十一晶体管T11，第十一晶体管T11的控制极与第一电压端VSS耦接，第十一晶体管T11的第一极与第一节点N1耦接，第十一晶体管T11的第二极与保持单元111(第四节点N4)耦接。第十一晶体管T11被配置为，在去噪子阶段，在第一电压信号的控制下截止，以阻断第一节点N1与第一晶体管T1的连接。
示例性地，以第十一晶体管T11的导通/关断类型为P型为例，第一电压端VSS处接收的第一电压信号为直流低电平信号，第一节点N1的开启电压为低电平，且第一电压信号的电压与开启电压大致相等。在此情况下，在去噪子阶段，第十一晶体管T11的栅源电压差(第十一晶体管T11的控制极与第一极的电压差)V gs＝0，第十一晶体管T11截止，以阻断第一节点N1与第一晶体管T1的连接。
在一些实施例中，如图6所示，第一控制子电路11还包括第二控制单元113，第二控制单元113与保持单元111、第二控制子电路13、第四时钟信号端CB2和第二电压端VDD耦接。第二控制单元113被配置为，在来自第四时钟信号端CB2的第四时钟信号，和第二控制子电路13的控制下，将来自第二电压端VDD的第二电压信号传输至保持单元111。
需要说明的是，如图12和图14所示，一个帧周期还包括：数据刷新阶段S，数据刷新阶段S在数据保持阶段之前，包括第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4。
在第一阶段t1和第三阶段t3，保持单元111还被配置为，在来自第一时钟信号端CK1的第一时钟信号的控制下，将来自初始信号端STV的初始信号传输至第一节点N1。第一输出子电路12还被配置为，在第一节点N1的电压的控制下关闭。
在第二阶段t2和第四阶段t4，第二控制单元113被配置为，在来自第四时钟信号端CB2的第四时钟信号，和第二控制子电路13的控制下，将来自第二电压端VDD的第二电压信号传输至保持单元111。
可以理解的是，如图6所示，第二控制单元113将来自第二电压端VDD的第二电压信号传输至保持单元111以及第一节点N1，使得第一节点N1的电压为第二电压信号的电压。并且，第二电压信号的电压，与第一阶段t1和第三阶段t3的初始信号的电压大致相等，使得第一节点N1在第二阶段t2和第四阶段t4的电压，与在第一阶段t1和第三阶段t3的电压大致相等，从而在数据刷新阶段S，使第一输出子电路12在第一节点N1的第二电压信号的控制下持续关闭。
在一些实施例中，如图7和图8所示，第二控制单元113包括第二晶体管T2和第三晶体管T3，第二晶体管T2的控制极与第二控制子电路13耦接，第二晶体管T2的第一极与第二电压端VDD耦接。
第三晶体管T3的控制极与第四时钟信号端CB2耦接，第三晶体管T3的第一极与第二晶体管T2的第二极耦接，第三晶体管T3的第二极与保持单元 111(第四节点N4)耦接。
第二晶体管T2被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，在第二控制子电路13输出的电压信号的控制下导通。第三晶体管T3被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，在第四时钟信号的控制下导通。通过第二晶体管T2和第三晶体管T3，将第二电压端VDD处接收的第二电压信号传输至保持单元111。
在一些实施例中，如图7和图8所示，第一输出子电路12包括第十晶体管T10，第十晶体管T10的控制极与第一节点N1耦接，第十晶体管T10的第一极与第一电压端VSS耦接，第十晶体管T10的第二极与信号输出端Oput耦接。第十晶体管T10被配置为，在数据刷新阶段S，在第一节点N1的第二电压信号的控制下截止；以及，在数据保持阶段，在第一节点N1的开启电压的控制下导通，将来自第一电压端VSS的第一电压信号传输至信号输出端Oput。
接下来，对第二控制子电路13的具体结构进行描述。
在一些实施例中，如图6所示，第二控制子电路13包括第三控制单元131、调整单元132、第四控制单元133和第五控制单元134。
其中，第三控制单元131与第一控制子电路11、第一控制信号端CON1和第一电压端VSS耦接。第三控制单元131被配置为，在来自第一控制信号端CON1的第一控制信号的控制下，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
需要说明的是，第三控制单元131被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在第一控制信号的控制下，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
示例性地，图7和图10示出了“第一控制信号端CON1”为第三时钟信号端CK2的情形。即，第三控制单元131与第一控制子电路11、第三时钟信号端CK2和第一电压端VSS耦接。第三控制单元131被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在来自第三时钟信号端CK2的第三时钟信号的控制下，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
并且，第三控制单元131还被配置为，在数据保持阶段，在第一控制子电路11的保持单元111的控制下(或，在第一节点N1的电压的控制下)，输出来自第三时钟信号端CK2的第三时钟信号，以控制第一控制子电路11的第二控制单元113关闭。
示例性地，图8和图11示出了“第一控制信号端CON1”为第一时钟信号端CK1的情形。即，第三控制单元131与第一控制子电路11、第一时钟信号端CK1和第一电压端VSS耦接。第三控制单元131被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在来自第一时钟信号端CK1的第一时钟信号的控制下，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
在一些实施例中，相较于图7和图10示出的移位寄存器电路RS，图8和图11示出的移位寄存器电路RS中，将第三时钟信号端CK2替换为第一时钟信号端CK1，使得移位寄存器电路RS中设置时钟信号端的数量减少为三个，分别为第一时钟信号端CK1、第二时钟信号端CB1和第四时钟信号端CB2。
如图6所示，第四控制单元133与第三控制单元131、第四时钟信号端CB2和第三节点N3耦接。第四控制单元133被配置为，在第三控制单元131的控制下，将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3。
需要说明的是，第四控制单元133被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在第三控制单元131输出的第一电压信号的控制下，将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3。
并且，如图7和图10所示，第三控制单元131与第一控制子电路11、第三时钟信号端CK2和第一电压端VSS耦接。在此情况下，第四控制单元133还被配置为，在数据保持阶段，在第三控制单元131输出的来自第三时钟信号端CK2的第三时钟信号的控制下关闭。
如图6所示，调整单元132与第三控制单元131和第三节点N3耦接。调整单元132被配置为，根据第三节点N3的电压，调整第三控制单元131所输出的电压。
可以理解的是，调整单元132与第三控制单元131的输出端和第三节点N3耦接。调整单元132被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，根据第三节点N3的电压，调整第三控制单元131的输出的电压，以保证第四控制单元133在第三控制单元131输出的电压信号的控制下稳定开启。
如图6所示，第五控制单元134与第一节点N1、第二节点N2、第三节点N3、第二电压端VDD和第二控制信号端CON2耦接。第五控制单元134被配置为，在来自第二控制信号端CON2的第二控制信号的控制下，将第三节点N3的电压传输至第二节点N2；以及，在第一节点N1的电压的控制下，将来自第二电压端VDD的第二电压信号传输至第二节点N2。
需要说明的是，第五控制单元134被配置为，在数据刷新阶段S的第二 阶段t2和第四阶段t4，在第二控制信号的控制下，将第三节点N3的电压传输至第二节点N2，以将第二节点N2的电压调整为开启电压。在此情况下，第二输出子电路14被配置为，在第二节点N2的开启电压的控制下开启。
第五控制单元134还被配置为，在数据保持阶段，在第一节点N1的电压的控制下，将来自第二电压端VDD的第二电压信号传输至第二节点N2，以控制第二输出子电路14关闭。
示例性地，图7和图10示出了“第二控制信号端CON2”为第四时钟信号端CB2的情形。即，第五控制单元134与第一节点N1、第二节点N2、第三节点N3、第二电压端VDD和第四时钟信号端CB2耦接。第五控制单元134被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，在来自第四时钟信号端CB2的第四时钟信号的控制下，将第三节点N3的电压传输至第二节点N2。
示例性地，图8和图11示出了“第二控制信号端CON2”为第二时钟信号端CB1的情形。即，第五控制单元134与第一节点N1、第二节点N2、第三节点N3、第二电压端VDD和第二时钟信号端CB1耦接。第五控制单元134被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，在来自第二时钟信号端CB1的第二时钟信号的控制下，将第三节点N3的电压传输至第二节点N2。
在一些实施例中，如图7和图8所示，第三控制单元131包括第四晶体管T4和第五晶体管T5，第四晶体管T4的控制极与第一控制子电路11(第四节点N4)耦接，第四晶体管T4的第一极与第一控制信号端CON1耦接，第四晶体管T4的第二极与第一控制子电路11(第五节点N5)耦接。第四晶体管T4被配置为，在数据保持阶段，在第一控制子电路11的控制下导通，将来自第一控制信号端CON1的第一控制信号传输至第一控制子电路11的第二控制单元113。
示例性地，如图7和图10所示，第四晶体管T4的控制极与第一控制子电路11的保持单元111耦接，第四晶体管T4的第一极与第三时钟信号端CK2耦接，第四晶体管T4的第二极与第一控制子电路11的第二控制单元113耦接。第四晶体管T4被配置为，在数据保持阶段，在第一控制子电路11的保持单元111的控制下导通，将来自第三时钟信号端CK2的第三时钟信号传输至第一控制子电路11的第二控制单元113，以控制第二控制单元113关闭。
示例性地，如图8和图11所示，第四晶体管T4的控制极与第一控制子电路11的保持单元111耦接，第四晶体管T4的第一极与第一时钟信号端CK1 耦接，第四晶体管T4的第二极与第一控制子电路11的第二控制单元113耦接。第四晶体管T4被配置为，在数据保持阶段，在第一控制子电路11的保持单元111的控制下导通，将来自第一时钟信号端CK1的第一直流电压信号或第一时钟信号传输至第一控制子电路11的第二控制单元113。
如图7和图8所示，第五晶体管T5的控制极与第一控制信号端CON1耦接，第五晶体管T5的第一极与第一电压端VSS耦接，第五晶体管T5的第二极与第一控制子电路11(第五节点N5)耦接。第五晶体管T5被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在来自第一控制信号端CON1的第一控制信号的控制下导通，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
示例性地，如图7所示，第五晶体管T5的控制极与第三时钟信号端CK2耦接，第五晶体管T5的第一极与第一电压端VSS耦接，第五晶体管T5的第二极与第一控制子电路11的第二控制单元113耦接。第五晶体管T5被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在来自第三时钟信号端CK2的第三时钟信号的控制下导通，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
示例性地，如图8所示，第五晶体管T5的控制极与第一时钟信号端CK1耦接，第五晶体管T5的第一极与第一电压端VSS耦接，第五晶体管T5的第二极与第一控制子电路11的第二控制单元113耦接。第五晶体管T5被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在来自第一时钟信号端CK1的第一时钟信号的控制下导通，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
如图7和图8所示，第四控制单元133包括第六晶体管T6，第六晶体管T6的控制极与第四晶体管T4的第二极(第五节点N5)耦接，第六晶体管T6的第一极与第四时钟信号端CB2耦接，第六晶体管T6的第二极与第三节点N3耦接。第六晶体管T6被配置为，在数据刷新阶段S的第一阶段t1和第三阶段t3，在第三控制单元131输出的第一电压信号的控制下导通，将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3；以及，在数据刷新阶段S的第二阶段t2和第四阶段t4，在第三控制单元131输出的电压的控制下保持导通。
如图7和图8所示，调整单元132包括第二电容器C2，第二电容器C2的第一端与第三节点N3耦接，第二电容器C2的第二端与第四晶体管T4的第二极(第五节点N5)耦接。第二电容器C2被配置为，在数据刷新阶段S 的第二阶段t2和第四阶段t4，根据电容器的自举作用，在第三节点N3的电压的作用下，调整第三控制单元131所输出的电压。
示例性地，以第六晶体管T6的导通/关断类型为P型为例，结合图14，在数据刷新阶段S的第二阶段t2和第四阶段t4，第四时钟信号端CB2处接收的第四时钟信号为低电平信号。在第三控制单元131输出的第一电压信号为低电平的情况下，根据第二电容器C2的自举作用，在第三节点N3的第四时钟信号的作用下，进一步拉低第三控制单元131所输出的电压，从而在数据刷新阶段S的第二阶段t2和第四阶段t4，保证第六晶体管T6的导通。
如图7和图8所示，第五控制单元134包括第七晶体管T7和第八晶体管T8，第七晶体管T7的控制极与第二控制信号端CON2耦接，第七晶体管T7的第一极与第三节点N3耦接，第七晶体管T7的第二极与第二节点N2耦接。第七晶体管T7被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，在来自第二控制信号端CON2的第二控制信号的控制下导通，将第三节点N3的电压传输至第二节点N2。
示例性地，如图7所示，第七晶体管T7的控制极与第四时钟信号端CB2耦接，第七晶体管T7的第一极与第三节点N3耦接，第七晶体管T7的第二极与第二节点N2耦接。第七晶体管T7被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，在来自第四时钟信号端CB2的第四时钟信号的控制下导通，将第三节点N3的电压传输至第二节点N2。
示例性地，如图8所示，第七晶体管T7的控制极与第二时钟信号端CB1耦接，第七晶体管T7的第一极与第三节点N3耦接，第七晶体管T7的第二极与第二节点N2耦接。第七晶体管T7被配置为，在数据刷新阶段S的第二阶段t2和第四阶段t4，在来自第二时钟信号端CB1的第二时钟信号的控制下导通，将第三节点N3的电压传输至第二节点N2。
如图7和图8所示，第八晶体管T8的控制极与第一节点N1耦接，第八晶体管T8的第一极与第二电压端VDD耦接，第八晶体管T8的第二极与第二节点N2耦接。第八晶体管T8被配置为，在数据保持阶段，在第一节点N1的电压的控制下导通，将来自第二电压端VDD的第二电压信号传输至第二节点N2，以控制第二输出子电路14关闭。
在一些实施例中，如图7和图8所示，第二输出子电路14包括第九晶体管T9和第三电容器C3，第九晶体管T9的控制极与第二节点N2耦接，第九晶体管T9的第一极与第二电压端VDD耦接，第九晶体管T9的第二极与信号输出端Oput耦接。第九晶体管T9被配置为，在数据刷新阶段S的第二阶段 t2、第三阶段t3和第四阶段t4，在第二节点N2的开启电压的控制下导通，以将来自第二电压端VDD的第二电压信号传输至信号输出端Oput；以及，在数据保持阶段，在第二节点N2的电压的控制下截止。
第三电容器C3的第一端与第二电压端VDD耦接，第三电容器C3的第二端与第二节点N2耦接。第三电容器C3被配置为，在数据保持阶段，根据电容器的自举作用，在来自第二电压端VDD的第二电压信号的作用下，保持第二节点N2的电压，从而保证第九晶体管T9的截止。
在一些实施例中，如图9所示，第二控制子电路13还包括第二防漏电单元135，第二防漏电单元135与第一电压端VSS耦接，且第三控制单元131通过第二防漏电单元135与第四控制单元133耦接。第二防漏电单元135被配置为，在来自第一电压端VSS的第一电压信号的控制下，保持第四控制单元133的开启。
与第一防漏电单元114的原理相同，由于第四晶体管T4和第五晶体管T5存在漏电的问题，第二防漏电单元135起到阻断第四晶体管T4和第五晶体管T5与第四控制单元133连接的作用，可避免第四控制单元133所接收的控制电压，因第四晶体管T4和第五晶体管T5的漏电而发生变化，从而保持第四控制单元133的稳定开启。
在一些实施例中，如图10所示，第二防漏电单元135包括第十二晶体管T12，第十二晶体管T12的控制极与第一电压端VSS耦接，第十二晶体管T12的第一极与第四控制单元133(第六节点N6)耦接，第十二晶体管T12的第二极与第三控制单元131(第五节点N5)耦接。第十二晶体管T12被配置为，在数据刷新阶段S，在来自第一电压端VSS的第一电压信号的控制下截止，以阻断第四晶体管T4和第五晶体管T5与第四控制单元133的连接。
示例性地，以第十二晶体管T12的导通/关断类型为P型为例，结合图14，在数据刷新阶段S的第二阶段t2和第四阶段t4，第一电压端VSS处接收的第一电压信号为直流低电平信号，第四时钟信号端CB2处接收的第四时钟信号为低电平信号。第二电容器C2被配置为，根据电容器的自举作用，在第三节点N3的第四时钟信号的作用下，拉低第四控制单元133所接收的来自第三控制单元131的电压，使第十二晶体管T12的栅源电压差(第十二晶体管T12的控制极与第一极的电压差)V gs≥0，第十二晶体管T12截止，以阻断第四晶体管T4和第五晶体管T5与第四控制单元133的连接。
请再次参见图7和图8，以下对本公开的一些实施例所提供的一种移位寄存器电路RS的结构做整体性、示例性的介绍。
移位寄存器电路RS包括：第一控制子电路11、第一输出子电路12、第二控制子电路13和第二输出子电路14。
其中，第一控制子电路11包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容器C1。第二控制子电路13包括第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8和第二电容器C2。第二输出子电路14包括第九晶体管T9和第三电容器C3。第一输出子电路12包括第十晶体管T10。
第一晶体管T1的控制极与第一时钟信号端CK1耦接，第一晶体管T1的第一极与初始信号端STV耦接，第一晶体管T1的第二极与第一节点N1耦接。第一晶体管T1被配置为，在第一时钟信号的控制下导通，将第一节点N1的电压保持为开启电压。
第一电容器C1的第一端与第二时钟信号端CB1耦接，第一电容器C1的第二端与第一节点N1耦接。第一电容器C1被配置为，根据电容器的自举作用，在第二直流电压信号的作用下，将第一节点N1的电压调整为开启电压；以及，在第二时钟信号的作用下，调整第一节点N1的电压。
第二晶体管T2的控制极与第二控制子电路13耦接，第二晶体管T2的第一极与第二电压端VDD耦接。第二晶体管T2被配置为，在第二控制子电路13输出的电压信号的控制下导通。
第三晶体管T3的控制极与第四时钟信号端CB2耦接，第三晶体管T3的第一极与第二晶体管T2的第二极耦接，第三晶体管T3的第二极与保持单元111耦接。第三晶体管T3被配置为，在第四时钟信号的控制下导通。通过第二晶体管T2和第三晶体管T3，将第二电压端VDD处接收的第二电压信号传输至保持单元111。
第四晶体管T4的控制极与第一控制子电路11耦接，第四晶体管T4的第一极与第一控制信号端CON1耦接，第四晶体管T4的第二极与第一控制子电路11耦接。第四晶体管T4被配置为，在第一控制子电路11的保持单元111的控制下导通，将来自第一控制信号端CON1的第一控制信号传输至第一控制子电路11的第二控制单元113。
第五晶体管T5的控制极与第一控制信号端CON1耦接，第五晶体管T5的第一极与第一电压端VSS耦接，第五晶体管T5的第二极与第一控制子电路11耦接。第五晶体管T5被配置为，在来自第一控制信号端CON1的第一控制信号的控制下导通，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
第六晶体管T6的控制极与第四晶体管T4的第二极耦接，第六晶体管T6的第一极与第四时钟信号端CB2耦接，第六晶体管T6的第二极与第三节点N3耦接。第六晶体管T6被配置为，在第三控制单元131输出的第一电压信号的控制下导通，将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3。
第二电容器C2的第一端与第三节点N3耦接，第二电容器C2的第二端与第四晶体管T4的第二极耦接。第二电容器C2被配置为，根据电容器的自举作用，在第三节点N3的电压的作用下，调整第三控制单元131所输出的电压。
第七晶体管T7的控制极与第二控制信号端CON2耦接，第七晶体管T7的第一极与第三节点N3耦接，第七晶体管T7的第二极与第二节点N2耦接。第七晶体管T7被配置为，在来自第二控制信号端CON2的第二控制信号的控制下导通，将第三节点N3的电压传输至第二节点N2。
第八晶体管T8的控制极与第一节点N1耦接，第八晶体管T8的第一极与第二电压端VDD耦接，第八晶体管T8的第二极与第二节点N2耦接。第八晶体管T8被配置为，在第一节点N1的电压的控制下导通，将来自第二电压端VDD的第二电压信号传输至第二节点N2，以控制第二输出子电路14关闭。
第九晶体管T9的控制极与第二节点N2耦接，第九晶体管T9的第一极与第二电压端VDD耦接，第九晶体管T9的第二极与信号输出端Oput耦接。第九晶体管T9被配置为，在第二节点N2的开启电压的控制下导通，以将来自第二电压端VDD的第二电压信号传输至信号输出端Oput；以及，在第二节点N2的电压的控制下截止。
第三电容器C3的第一端与第二电压端VDD耦接，第三电容器C3的第二端与第二节点N2耦接。第三电容器C3被配置为，根据电容器的自举作用，在来自第二电压端VDD的第二电压信号的作用下，保持第二节点N2的电压，从而保证第九晶体管T9的截止。
第十晶体管T10的控制极与第一节点N1耦接，第十晶体管T10的第一极与第一电压端VSS耦接，第十晶体管T10的第二极与信号输出端Oput耦接。第十晶体管T10被配置为，在第一节点N1的电压的控制下截止；以及，在第一节点N1的开启电压的控制下导通，将来自第一电压端VSS的第一电压信号传输至信号输出端Oput。
在本公开的实施例中，第一控制子电路11、第一输出子电路12、第二控 制子电路13和第二输出子电路14的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
本公开的一些实施例所提供的栅极驱动电路G，还包括三条或四条时钟信号线，与栅极驱动电路G的各移位寄存器电路耦接。
需要说明的是，如图2B所示，时钟信号线可与显示装置200中的时序控制器TCON耦接，用于向各移位寄存器电路传输来自时序控制器TCON的电压信号。
示例性地，如图2B所示，栅极驱动电路G包括四条时钟信号线，分别为第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3和第四时钟信号线CLK4。
其中，第2N-1级移位寄存器电路的第一时钟信号端CK1，与第一时钟信号线CLK1耦接；第2N-1级移位寄存器电路的第二时钟信号端CB1，与第二时钟信号线CLK2耦接；第2N-1级移位寄存器电路的第三时钟信号端CK2，与第三时钟信号线CLK3耦接；第2N-1级移位寄存器电路的第四时钟信号端CB2，与第四时钟信号线CLK4耦接。
并且，第2N级移位寄存器电路的第一时钟信号端CK1，与第二时钟信号线CLK2耦接；第2N级移位寄存器电路的第二时钟信号端CB1，与第一时钟信号线CLK1耦接；第2N级移位寄存器电路的第三时钟信号端CK2，与第四时钟信号线CLK4耦接；第2N级移位寄存器电路的第四时钟信号端CB2，与第三时钟信号线CLK3耦接；N为正整数。
可以理解的是，上述示例中，第奇数级移位寄存器电路中的第一时钟信号端CK1与第偶数级移位寄存器电路中的第二时钟信号端CB1，均与第一时钟信号线CLK1耦接，输入来自第一时钟信号线CLK1的信号。相反地，第偶数级移位寄存器电路中的第一时钟信号端CK1与第奇数级移位寄存器电路中的第二时钟信号端CB1，均与第二时钟信号线CLK2耦接，输入来自第二时钟信号线CLK2的信号。
同理，第奇数级移位寄存器电路中的第三时钟信号端CK2与第偶数级移位寄存器电路中的第四时钟信号端CB2，均与第三时钟信号线CLK3耦接，输入来自第三时钟信号线CLK3的信号。相反地，第偶数级移位寄存器电路 中的第三时钟信号端CK2与第奇数级移位寄存器电路中的第四时钟信号端CB2，均与第四时钟信号线CLK4耦接，输入来自第四时钟信号线CLK4的信号。
示例性地，相比于图7和图9示出的移位寄存器电路RS，图8和图10示出的移位寄存器电路RS中，将第三时钟信号端CK2替换为第一时钟信号端CK1，使得移位寄存器电路RS中设置时钟信号端的数量减少为三个，分别为第一时钟信号端CK1、第二时钟信号端CB1和第四时钟信号端CB2。相应的，栅极驱动电路G中可取消设置第三时钟信号线CLK3，即栅极驱动电路G包括三条时钟信号线，通过减少设置信号线的数量，可降低在显示面板100的周边区BB布置信号线的难度，并且，减少了信号线占用周边区BB的面积，有利于实现显示装置200的窄边框化。
本公开的一些实施例还提供了一种移位寄存器电路的驱动方法，在介绍该驱动方法之前，首先对显示装置的显示过程进行介绍。
在显示技术领域，例如对于液晶显示装置来说，一帧图像指的是通过逐行扫描或者隔行扫描的方式在显示屏幕上“绘制”一幅图像。示例性地，如图2A和图2B所示，在显示面板100中，显示面板100所包括的多个亚像素P呈阵列式排布，包括N行M列，在显示过程中，通过逐行扫描的方式，第一条控制信号线L1至第N条控制信号线L(N)逐行对第一行亚像素P至第N行亚像素P依次输入扫描信号，以逐行控制亚像素P开启，在每一行亚像素P打开时，数据线DL将相应的数据信号输入该行亚像素P中的每个亚像素(一共包括M个亚像素)，以将多个亚像素P从第一行至第N行依次点亮以显示相应的图像，这样，就完成了一帧图像的“绘制”或显示。接着，同样以逐行扫描的方式，重新将多个亚像素P从第一行至第N行依次点亮以显示相应的图像，这样就完成下一帧图像的“绘制”或显示。
通常，显示装置的刷新频率可以为60HZ，即显示装置一秒钟可以显示60帧图像，每帧图像的显示周期为1/60秒。由于人眼存在视觉暂留现象，可能会出现这样的情况，当显示一幅静止的画面时，虽然在一秒钟之内人眼感觉不出显示装置上的图像发生了任何变化，但实际上显示装置上的图像已经重复显示了60次。在显示装置的刷新频率足够高的情况下，人眼不会感受到画面切换所造成的闪烁。
也就是说，显示装置的显示过程包括多个帧周期，每个帧周期完成N行亚像素P的扫描，从而进行一帧图像的显示，对于栅极驱动电路来说，在每个帧周期中，栅极驱动电路所包括的N级移位寄存器电路依次输出扫描信号， 即从第一级移位寄存器至第N级移位寄存器依次输出扫描信号，从而逐行扫描各条控制信号线L。
在此基础上，以下以图2B中示出的栅极驱动电路G(由图7的移位寄存器电路级联而成)中的第一级移位寄存器电路RS1为例，并结合图12和图14中的时序图，对本公开的移位寄存器电路在一图像帧(一个帧周期)内的驱动方法进行说明。
如图12所示，移位寄存器电路RS的驱动方法包括：一个帧周期包括数据保持阶段，数据保持阶段包括多个去噪子阶段和多个去噪加强子阶段。去噪子阶段与去噪加强子阶段交替，相当于，在数据保持阶段插入多个去噪加强子阶段。
在去噪子阶段，移位寄存器电路RS的第一控制子电路11在来自第一时钟信号端CK1的第一直流电压信号，和来自第二时钟信号端CB1的第二直流电压信号的影响下，将第一节点N1的电压调整为开启电压。相较于采用交流电压信号，第一控制子电路11采用第一直流电压信号和第二直流电压信号，可降低显示装置200的功耗。
在去噪加强子阶段，第一控制子电路11在来自第一时钟信号端CK1的第一时钟信号，和来自第二时钟信号端CB1的第二时钟信号的影响下，将第一节点N1的电压保持为开启电压，可避免由于移位寄存器电路RS中的晶体管漏电而导致第一节点N1的电压发生变化，从而保证了第一输出子电路12的稳定开启。
在数据保持阶段，第一节点N1的电压保持为开启电压，移位寄存器电路RS的第一输出子电路12在第一节点N1的开启电压的控制下开启，向信号输出端Oput传输来自第一电压端VSS的第一电压信号。
可以理解的是，数据保持阶段内的去噪子阶段的时长，相对于去噪加强子阶段时长，应该尽可能的延长，从而达到降低显示装置200的功耗的效果。
示例性地，去噪子阶段的时长可为0.1ms～1000ms，例如，0.1ms、10ms、500ms、800ms或1000ms。
并且，可根据移位寄存器电路RS内的晶体管的漏电水平，调节在数据保持阶段插入去噪加强子阶段的数量，插入去噪加强子阶段的数量应该尽可能的少，以保证第一输出子电路12的稳定开启，且可以降低显示装置200的功耗。
示例性地，在数据保持阶段，可在每1ms插入1～20个去噪加强子阶段，例如，每1ms插入1个去噪加强子阶段、每1ms插入5个去噪加强子阶段、 每1ms插入10个去噪加强子阶段、每1ms插入15个去噪加强子阶段，或每1ms插入20个去噪加强子阶段。
为验证上述驱动方法所带来的效果，对由上述移位寄存器电路RS级联而成的发光控制电路进行仿真实验。如图13所示，按照上述驱动方法驱动发光控制电路的各级移位寄存器电路RS，并检测移位寄存器电路RS的信号输出端Oput的输出噪声。实验结果如下表1所示：
驱动方法 输出噪音 GOA功耗 节能比例
插入脉冲 0V 9.5mW 82％
60Hz Clock 0V 52mW 0
VSS NG(|V th|) - -
VDD NG(|V th|～VDD) - -
表1
其中，“插入脉冲”是指本公开的上述移位寄存器电路RS驱动方法；“60Hz Clock”是指相关技术中移位寄存器电路的驱动方法，即在显示装置的刷新频率为60Hz的情况下，采用时钟信号(交流电压信号)驱动移位寄存器电路的方式；“VSS”是指采用来自第一电压端VSS的第一电压信号驱动移位寄存器电路RS的方法；“VDD”是指采用来自第二电压端VDD的第二电压信号驱动移位寄存器电路RS的方法。
可见，相较于采用相关技术中移位寄存器电路的驱动方法，采用本公开的上述移位寄存器电路RS驱动方法，移位寄存器电路RS的输出噪声的电压同样为0V，并且，栅极驱动电路总体的功耗为9.5mW，相对于“60Hz Clock”的驱动方法的功耗为52mW，节能比例达到82％。因此，本公开的移位寄存器电路RS驱动方法，可保证移位寄存器电路RS的输出噪声较小的同时，降低显示装置200的功耗。
并且，在不插入脉冲的情况下，采用直流电压信号驱动移位寄存器电路RS，即采用来自第一电压端VSS的第一电压信号驱动移位寄存器电路RS的方法，移位寄存器电路RS输出噪声的电压为|V th|。或者，采用来自第二电压端VDD的第二电压信号驱动移位寄存器电路RS的方法，移位寄存器电路RS 输出噪声的电压的范围为|V th|～VDD。可以理解的是，由于移位寄存器电路RS中的晶体管存在漏电的问题，仅采用直流电压信号驱动移位寄存器电路RS虽然可以降低显示装置的功耗，但是无法解决移位寄存器电路RS输出噪声的问题。
在一些实施例中，第一控制子电路11包括保持单元111和第一控制单元112，第一控制子电路11在来自第一时钟信号端CK1的第一直流电压信号，和来自第二时钟信号端CB1的第二直流电压信号的影响下，将第一节点的电压调整为开启电压，包括：
保持单元111在来自第一时钟信号端CK1的第一直流电压信号，和来自初始信号端STV的初始电压信号的影响下关闭。第一控制单元112在来自第二时钟信号端CB1的第二直流电压信号的影响下，将第一节点N1的电压调整为开启电压。
示例性地，参考图7和图12，在第一控制子电路11的保持单元111包括第一晶体管T1，第一控制单元112包括第一电容器C1的情况下，去噪子阶段包括：
第一直流电压信号为低电平信号，第二直流电压信号为低电平信号。第一晶体管T1在第一直流电压信号的控制下截止，第一电容器C1根据电容器的自举作用，在第二直流电压信号的作用下，将第一节点N1的电压调整为开启电压。
第一控制子电路11在来自第一时钟信号端CK1的第一时钟信号，和来自第二时钟信号端CB1的第二时钟信号的影响下，将第一节点N1的电压保持为开启电压，包括：
第一控制单元112在来自第二时钟信号端CB1的第二时钟信号的影响下，调整第一节点N1的电压。保持单元111在来自第一时钟信号端CK1的第一时钟信号的控制下开启，将第一节点N1的电压保持为开启电压。
示例性地，参考图7和图11，在第一控制子电路11的保持单元111包括第一晶体管T1，第一控制单元112包括第一电容器C1的情况下，去噪加强子阶段包括：
第二时钟信号为高电平信号，第一时钟信号为低电平信号。第一电容器C1在第二时钟信号的作用下，调整第一节点N1的电压。第一晶体管T1在第一时钟信号的控制下导通，将第一节点N1的电压保持为开启电压。
示例性地，在第一输出子电路12包括第十晶体管T10的情况下，数据保持阶段包括：
第十晶体管T10在第一节点N1的开启电压的控制下开启，向信号输出端Oput传输来自第一电压端VSS的第一电压信号。
在一些实施例中，如图12所示，一个帧周期还包括：数据刷新阶段S，在数据保持阶段之前。如图14所示，数据刷新阶段S包括第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4。
移位寄存器电路RS的第二控制子电路13包括第三控制单元131、调整单元132、第四控制单元133和第五控制单元134，在第一阶段t1和第三阶段t3，第三控制单元131在来自第一控制信号端CON1(第三时钟信号端CK2)的第一控制信号(第三时钟信号)的控制下，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。第四控制单元133在第三控制单元131的控制下，将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3。
示例性地，参考图7和图14，在第三控制单元131包括第四晶体管T4和第五晶体管T5，第四控制单元133包括第六晶体管T6的情况下，第一阶段t1和第三阶段t3包括：
第四晶体管T4在第一控制子电路11的控制下截止，也可以讲，第一控制子电路11控制第一节点N1的电压为高电平，第四晶体管T4在第一节点N1的电压的控制下截止。
第三时钟信号为低电平信号，第五晶体管T5在来自第三时钟信号端CK2的第三时钟信号的控制下导通，将来自第一电压端VSS的第一电压信号传输至第一控制子电路11。
第三控制单元131输出的第一电压信号为低电平信号，第六晶体管T6在第三控制单元131输出的第一电压信号的控制下导通，将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3。由于第四时钟信号为高电平信号，因此，第三节点N3的电压为高电平。
在第二阶段t2和第四阶段t4，调整单元132根据第三节点N3的电压，调整第三控制单元131所输出的电压。且，第四控制单元133在第三控制单元131的控制下保持开启，将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3。
第五控制单元134在来自第二控制信号端CON2的第二控制信号的控制下，将第三节点N3的电压传输至第二节点N2。
第二输出子电路14在第二节点N2的开启电压的控制下开启，将来自第二电压端VDD的第二电压信号传输至信号输出端Oput。
示例性地，参考图7和图14，在调整单元132包括第二电容器C2，第五 控制单元134包括第七晶体管T7和第八晶体管T8，第二输出子电路14包括第九晶体管T9的情况下，第二阶段t2和第四阶段t4包括：
第二电容器C2根据电容器的自举作用，在第三节点N3的电压的作用下，调整第三控制单元131所输出的电压。
可以理解的是，在第一阶段t1和第三阶段t3，第三控制单元131输出的第一电压信号为低电平信号。在第二阶段t2和第四阶段t4，第四时钟信号为低电平信号，因此，第三节点N3的电压为低电平，第二电容器C2在第三节点N3的电压的作用下，下拉第三控制单元131输出的电压，使第六晶体管T6保持导通，以将来自第四时钟信号端CB2的第四时钟信号传输至第三节点N3。
第七晶体管T7在来自第四时钟信号端CB2的第四时钟信号的控制下导通，将第三节点N3的电压传输至第二节点N2，使第二节点N2的电压为低电平。
第九晶体管T9在第二节点N2的开启电压的控制下开启，将来自第二电压端VDD的第二电压信号传输至信号输出端Oput。
需要说明的是，本公开实施例中的移位寄存器电路所采用的各晶体管可为薄膜晶体管、场效应晶体管或其他特性相同的开关器件。
本公开中的晶体管，晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。
在本公开的实施例提供的移位寄存器中，晶体管均以P型晶体管为例进行说明。需要说明的是，本公开的实施例包括但不限于此。例如，本公开的实施例提供的移位寄存器中的一个或多个晶体管也可以采用N型晶体管，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。
本公开的实施例中，第一电容器C1、第二电容器C2和第三电容器C3可以是通过工艺制程单独制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容器的各个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。电容器也可以是薄膜晶体管之间的寄生电容，或者通过薄膜晶体管本身与其他器件、线路来实现，又或者利用电路自身线路之间的寄生电容来实现。
在本公开的实施例提供的电路中，第一节点N1、第二节点N2、第三节点N3、第四节点N4、第五节点N5和第六节点N6并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种移位寄存器电路，包括：
    第一控制子电路，与第一时钟信号端、第二时钟信号端和第一节点耦接；所述第一控制子电路被配置为，在来自所述第一时钟信号端的第一直流电压信号，和来自所述第二时钟信号端的第二直流电压信号的影响下，将所述第一节点的电压调整为开启电压；以及，在来自所述第一时钟信号端的第一时钟信号，和来自所述第二时钟信号端的第二时钟信号的影响下，将所述第一节点的电压保持为所述开启电压；和
    第一输出子电路，与所述第一节点、第一电压端和信号输出端耦接；所述第一输出子电路被配置为，在所述第一节点的开启电压的控制下开启，将来自所述第一电压端的第一电压信号传输至所述信号输出端。
  2. 根据权利要求1所述的移位寄存器电路，还包括：
    第二控制子电路，与所述第一节点、所述第一电压端、第一控制信号端、第二控制信号端、第四时钟信号端、第二电压端、第二节点和所述第一控制子电路耦接；所述第二控制子电路被配置为，在来自所述第一控制信号端的第一控制信号和来自所述第二控制信号端的第二控制信号的控制下，并在所述第一控制子电路、来自所述第一电压端的第一电压信号和来自所述第四时钟信号端的第四时钟信号的影响下，将所述第二节点的电压调整为开启电压；
    第二输出子电路，与所述第二节点、所述第二电压端和所述信号输出端耦接；所述第二输出子电路被配置为，在所述第二节点的开启电压的控制下开启，将来自所述第二电压端的第二电压信号传输至所述信号输出端。
  3. 根据权利要求2所述的移位寄存器电路，其中，所述第一控制子电路包括：
    保持单元，与所述第一时钟信号端、所述第一节点和初始信号端耦接；所述保持单元被配置为，在来自所述第一时钟信号端的第一直流电压信号，和来自所述初始信号端的初始电压信号的影响下关闭；以及，在来自所述第一时钟信号端的第一时钟信号的控制下开启，将所述第一节点的电压保持为所述开启电压；和
    第一控制单元，与所述第二时钟信号端和所述第一节点耦接；所述第一控制单元被配置为，在来自所述第二时钟信号端的第二直流电压信号的影响下，将所述第一节点的电压调整为开启电压；以及，在来自所述第二时钟信号端的第二时钟信号的影响下，调整所述第一节点的电压。
  4. 根据权利要求3所述的移位寄存器电路，其中，所述保持单元包括：
    第一晶体管，所述第一晶体管的控制极与所述第一时钟信号端耦接，所 述第一晶体管的第一极与所述初始信号端耦接，所述第一晶体管的第二极与所述第一节点耦接；
    所述第一控制单元包括：
    第一电容器，所述第一电容器的第一端与所述第二时钟信号端耦接，所述第一电容器的第二端与所述第一节点耦接。
  5. 根据权利要求3或4所述的移位寄存器电路，其中，所述第一控制子电路还包括：
    第一防漏电单元，与所述第一电压端耦接，且所述保持单元通过所述第一防漏电单元与所述第一节点耦接；所述第一防漏电单元被配置为，在来自所述第一电压端的第一电压信号的控制下，保持所述第一节点的电压。
  6. 根据权利要求5所述的移位寄存器电路，其中，所述第一防漏电单元包括：
    第十一晶体管，所述第十一晶体管的控制极与所述第一电压端耦接，所述第十一晶体管的第一极与所述第一节点耦接，所述第十一晶体管的第二极与所述保持单元耦接。
  7. 根据权利要求3～6中任一项所述的移位寄存器电路，其中，所述第一控制子电路还包括：
    第二控制单元，与所述保持单元、所述第二控制子电路、第四时钟信号端和所述第二电压端耦接；所述第二控制单元被配置为，在来自所述第四时钟信号端的第四时钟信号，和所述第二控制子电路的控制下，将来自所述第二电压端的第二电压信号传输至所述保持单元。
  8. 根据权利要求7所述的移位寄存器电路，其中，所述第二控制单元包括：
    第二晶体管，所述第二晶体管的控制极与所述第二控制子电路耦接，所述第二晶体管的第一极与所述第二电压端耦接；
    第三晶体管，所述第三晶体管的控制极与所述第四时钟信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第二极耦接，所述第三晶体管的第二极与所述保持单元耦接。
  9. 根据权利要求2～8中任一项所述的移位寄存器电路，其中，所述第二控制子电路包括：
    第三控制单元，与所述第一控制子电路、所述第一控制信号端和所述第一电压端耦接；所述第三控制单元被配置为，在来自所述第一控制信号端的第一控制信号的控制下，将来自所述第一电压端的第一电压信号传输至所述 第一控制子电路；
    第四控制单元，与所述第三控制单元、所述第四时钟信号端和第三节点耦接；所述第四控制单元被配置为，在所述第三控制单元的控制下，将来自所述第四时钟信号端的第四时钟信号传输至所述第三节点；
    调整单元，与所述第三控制单元和所述第三节点耦接；所述调整单元被配置为，根据所述第三节点的电压，调整所述第三控制单元所输出的电压；
    第五控制单元，与所述第一节点、所述第二节点、所述第三节点、所述第二电压端和第二控制信号端耦接；所述第五控制单元被配置为，在来自所述第二控制信号端的第二控制信号的控制下，将所述第三节点的电压传输至所述第二节点；以及，在所述第一节点的电压的控制下，将来自所述第二电压端的第二电压信号传输至所述第二节点。
  10. 根据权利要求9所述的移位寄存器电路，其中，
    所述第三控制单元包括：
    第四晶体管，所述第四晶体管的控制极与所述第一控制子电路耦接，所述第四晶体管的第一极与所述第一控制信号端耦接，所述第四晶体管的第二极与所述第一控制子电路耦接；
    第五晶体管，所述第五晶体管的控制极与所述第一控制信号端耦接，所述第五晶体管的第一极与所述第一电压端耦接，所述第五晶体管的第二极与所述第一控制子电路耦接；
    所述第四控制单元包括：
    第六晶体管，所述第六晶体管的控制极与所述第四晶体管的第二极耦接，所述第六晶体管的第一极与所述第四时钟信号端耦接，所述第六晶体管的第二极与所述第三节点耦接；
    所述调整单元包括：
    第二电容器，所述第二电容器的第一端与所述第三节点耦接，所述第二电容器的第二端与所述第四晶体管的第二极耦接；
    所述第五控制单元包括：
    第七晶体管，所述第七晶体管的控制极与所述第二控制信号端耦接，所述第七晶体管的第一极与所述第三节点耦接，所述第七晶体管的第二极与所述第二节点耦接；
    第八晶体管，所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管的第一极与所述第二电压端耦接，所述第八晶体管的第二极与所述第二节点耦接。
  11. 根据权利要求9或10所述的移位寄存器电路，其中，所述第二控制子电路还包括：
    第二防漏电单元，与所述第一电压端耦接，且所述第三控制单元通过所述第二防漏电单元与所述第四控制单元耦接；所述第二防漏电单元被配置为，在来自所述第一电压端的第一电压信号的控制下，保持所述第四控制单元的开启。
  12. 根据权利要求11所述的移位寄存器电路，其中，所述第二防漏电单元包括：
    第十二晶体管，所述第十二晶体管的控制极与所述第一电压端耦接，所述第十二晶体管的第一极与所述第四控制单元耦接，所述第十二晶体管的第二极与所述第三控制单元耦接。
  13. 根据权利要求2～12中任一项所述的移位寄存器电路，其中，
    所述第一控制信号端为第一时钟信号端或第三时钟信号端；和/或，
    所述第二控制信号端为第二时钟信号端或第四时钟信号端；
    所述第一时钟信号端被配置为，在一个帧周期的数据刷新阶段输出第一时钟信号，在一个帧周期的数据保持阶段的去噪子阶段输出第一直流电压信号，在一个帧周期的数据保持阶段的去噪加强子阶段输出第一时钟信号；
    所述第二时钟信号端被配置为，在所述数据刷新阶段输出第二时钟信号，在所述数据保持阶段的去噪子阶段输出第二直流电压信号，在所述数据保持阶段的去噪加强子阶段输出第二时钟信号；
    所述第三时钟信号端被配置为，在所述数据刷新阶段输出第三时钟信号，在所述数据保持阶段输出第三直流电压信号；
    所述第四时钟信号端被配置为，在所述数据刷新阶段输出第四时钟信号，在所述数据保持阶段输出第四直流电压信号。
  14. 根据权利要求13所述的移位寄存器电路，其中，所述第一时钟信号与所述第二时钟信号大致互为反相信号，所述第三时钟信号和所述第四时钟信号大致互为反相信号；所述第一直流电压信号与所述第二直流电压信号均为低电平信号，所述第三直流电压信号与所述第四直流电压信号均为高电平信号。
  15. 根据权利要求2～14中任一项所述的移位寄存器电路，所述第二输出子电路包括：
    第九晶体管，所述第九晶体管的控制极与所述第二节点耦接，所述第九晶体管的第一极与所述第二电压端耦接，所述第九晶体管的第二极与所述信 号输出端耦接；
    第三电容器，所述第三电容器的第一端与所述第二电压端耦接，所述第三电容器的第二端与所述第二节点耦接。
  16. 根据权利要求1～15中任一项所述的移位寄存器电路，其中，所述第一输出子电路包括：
    第十晶体管，所述第十晶体管的控制极与所述第一节点耦接，所述第十晶体管的第一极与所述第一电压端耦接，所述第十晶体管的第二极与所述信号输出端耦接。
  17. 一种栅极驱动电路，包括：
    多个如权利要求1～16中任一项所述的移位寄存器电路，多个所述移位寄存器电路依次级联。
  18. 根据权利要求17所述的栅极驱动电路，还包括：
    三条或四条时钟信号线，与所述栅极驱动电路的各移位寄存器电路耦接。
  19. 一种显示装置，包括：
    如权利要求17或18所述的栅极驱动电路；
    多条控制信号线，所述栅极驱动电路中的每个移位寄存器电路与至少一条控制信号线耦接。
  20. 一种移位寄存器电路的驱动方法，应用于如权利要求1～15中任一项所述的移位寄存器电路；所述驱动方法包括：
    一个帧周期包括：数据保持阶段，所述数据保持阶段包括交替出现的多个去噪子阶段和多个去噪加强子阶段；
    在所述去噪子阶段，所述移位寄存器电路的第一控制子电路在来自第一时钟信号端的第一直流电压信号，和来自第二时钟信号端的第二直流电压信号的影响下，将第一节点的电压调整为开启电压；
    在所述去噪加强子阶段，所述第一控制子电路在来自所述第一时钟信号端的第一时钟信号，和来自所述第二时钟信号端的第二时钟信号的影响下，将所述第一节点的电压保持为所述开启电压；
    在所述数据保持阶段，所述移位寄存器电路的第一输出子电路在所述第一节点的开启电压的控制下开启，向信号输出端传输来自所述第一电压端的第一电压信号。
  21. 根据权利要求20所述的驱动方法，其中，所述第一控制子电路包括保持单元和第一控制单元，
    所述第一控制子电路在来自第一时钟信号端的第一直流电压信号，和来 自第二时钟信号端的第二直流电压信号的影响下，将第一节点的电压调整为开启电压，包括：
    所述保持单元在来自所述第一时钟信号端的第一直流电压信号，和来自所述初始信号端的初始电压信号的影响下关闭；
    所述第一控制单元在来自所述第二时钟信号端的第二直流电压信号的影响下，将所述第一节点的电压调整为所述开启电压；
    所述第一控制子电路在来自所述第一时钟信号端的第一时钟信号，和来自所述第二时钟信号端的第二时钟信号的影响下，将所述第一节点的电压保持为所述开启电压，包括：
    所述第一控制单元在来自所述第二时钟信号端的第二时钟信号的影响下，调整所述第一节点的电压；
    所述保持单元在来自所述第一时钟信号端的第一时钟信号的控制下开启，将所述第一节点的电压保持为所述开启电压。
  22. 根据权利要求20或21所述的驱动方法，其中，一个帧周期还包括：数据刷新阶段，所述数据刷新阶段包括第一阶段、第二阶段、第三阶段和第四阶段；
    所述移位寄存器电路的第二控制子电路包括第三控制单元、第四控制单元、第五控制单元和调整单元；
    在所述第一阶段和所述第三阶段，所述第三控制单元在来自第一控制信号端的第一控制信号的控制下，将来自所述第一电压端的第一电压信号传输至所述第一控制子电路；所述第四控制单元在所述第三控制单元的控制下，将来自所述第四时钟信号端的第四时钟信号传输至所述第三节点；
    在所述第二阶段和所述第四阶段，所述调整单元根据所述第三节点的电压，调整所述第三控制单元所输出的电压；所述第四控制单元在所述第三控制单元的控制下，将来自所述第四时钟信号端的第四时钟信号传输至所述第三节点；所述第五控制单元在来自所述第二控制信号端的第二控制信号的控制下，将所述第三节点的电压传输至所述第二节点；第二输出子电路在所述第二节点的开启电压的控制下开启，将来自所述第二电压端的第二电压信号传输至所述信号输出端。
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