WO2023028749A1 - 显示面板及其移位寄存器单元的驱动方法、移位寄存器 - Google Patents

显示面板及其移位寄存器单元的驱动方法、移位寄存器 Download PDF

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Publication number
WO2023028749A1
WO2023028749A1 PCT/CN2021/115307 CN2021115307W WO2023028749A1 WO 2023028749 A1 WO2023028749 A1 WO 2023028749A1 CN 2021115307 W CN2021115307 W CN 2021115307W WO 2023028749 A1 WO2023028749 A1 WO 2023028749A1
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Prior art keywords
transistor
potential
terminal
coupled
signal
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PCT/CN2021/115307
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English (en)
French (fr)
Inventor
张�浩
卢江楠
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京东方科技集团股份有限公司
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Priority to PCT/CN2021/115307 priority Critical patent/WO2023028749A1/zh
Priority to CN202180002327.0A priority patent/CN116097340A/zh
Publication of WO2023028749A1 publication Critical patent/WO2023028749A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display panel and a driving method for a shift register unit thereof, and a shift register.
  • the shift register usually includes a plurality of cascaded shift register units, and each shift register unit can provide a light emission control signal to a row of pixel units, and the plurality of cascaded shift register units can realize the control of each row of pixels in the display device.
  • the unit is driven row by row to display an image.
  • the shift register unit includes: two shift circuits.
  • a shift circuit is respectively coupled to a plurality of signal terminals and the shift node, and is used for controlling the potential of the shift node based on signals provided by each signal terminal.
  • Another shift circuit is coupled to the plurality of signal terminals, shift nodes and output terminals respectively, and is used to control the potential of the output terminal based on the signal provided by each signal terminal and the potential of the shift node, and the output terminal is connected to a row of pixels unit coupling.
  • the shift register unit in the related art has poor flexibility in controlling the potential of its output terminal.
  • Embodiments of the present disclosure provide a display panel, a driving method of a shift register unit thereof, and a shift register. Described technical scheme is as follows:
  • a display panel is provided, and the display panel includes:
  • a base substrate having a display area and a non-display area surrounding the display area
  • the shift register unit includes: a first shift circuit and a second shift circuit
  • the first shift circuit is respectively coupled to the first clock terminal, the second clock terminal, the input signal terminal, the first power supply terminal, the second power supply terminal and the shift node, and the first shift circuit is used for responding to The first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the input signal provided by the input signal terminal, the first power supply signal provided by the first power supply terminal and the The second power supply signal provided by the second power supply terminal controls the potential of the shift node;
  • the second shift circuit is respectively connected to the shift node, the first clock terminal, the second clock terminal, the third clock terminal, an enable control terminal, an output control terminal, the first power supply terminal
  • the second power supply terminal is coupled to the output terminal
  • the second shift circuit is configured to respond to the potential of the shift node, the first clock signal, the second clock signal, and the first power supply signal and the second power supply signal, control the on-off of the first power supply terminal and the output terminal, and control the on-off of the third clock terminal and the output terminal in response to the output control signal provided by the output control terminal and in response to the enable control signal provided by the enable control terminal, control the on-off of the second power supply terminal and the output terminal.
  • the second shift circuit is configured to: in the display phase of the pixel circuit coupled to the shift register unit, in response to the enable control signal of the second potential, control the second power supply terminal is disconnected from the output terminal; and, in the blanking phase of the pixel circuit coupled to the shift register unit, in response to the enable control signal of the first potential, control the connection between the second power supply terminal and The output terminal is turned on.
  • the second shift circuit includes: a first output control subcircuit, a second output control subcircuit, and a first output subcircuit;
  • the first output control subcircuit is respectively coupled to the shift node, the first clock terminal, the second clock terminal, the first power supply terminal, the second power supply terminal and the output terminal , the first output control subcircuit is configured to control On-off of the first power supply terminal and the output terminal;
  • the second output control subcircuit is respectively coupled to the enable control terminal, the second power supply terminal and the output terminal, and the second output control subcircuit is configured to respond to the enable control signal, controlling the on-off of the second power supply terminal and the output terminal;
  • the first output subcircuit is respectively coupled to the output control terminal, the third clock terminal and the output terminal, and the first output subcircuit is used for controlling the first output control signal in response to the output control signal.
  • the second output control subcircuit includes: a first transistor
  • the gate of the first transistor is coupled to the enable control terminal, the first pole of the first transistor is coupled to the second power supply terminal, and the second pole of the first transistor is coupled to the output terminal coupling.
  • the first output sub-circuit includes: a second transistor, and the second transistor is a single-gate transistor;
  • the gate of the second transistor is coupled to the output control terminal, the first pole of the second transistor is coupled to the third clock terminal, the second pole of the second transistor is coupled to the output terminal coupling.
  • the first output control subcircuit includes: a first noise reduction control subcircuit, a second noise reduction control subcircuit, and a noise reduction subcircuit;
  • the first noise reduction control sub-circuit is respectively coupled to the shift node, the first clock terminal, the second clock terminal, the first power supply terminal, the second power supply terminal and a pull-down reference node , the first noise reduction control subcircuit is used to control the on-off of the second power supply terminal and the pull-down reference node in response to the potential of the shift node, and control the on-off of the pull-down reference node in response to the first clock signal. On-off of the first power supply terminal and the pull-down reference node, and based on the second clock signal, control the potential of the pull-down reference node;
  • the second noise reduction control subcircuit is respectively coupled to the shift node, the first power supply terminal, the second power supply terminal, the pull-down reference node and the first pull-down node, and the second noise reduction
  • the noise control subcircuit is used to control the on-off of the second power supply terminal and the first pull-down node in response to the potential of the shift node, and control the pull-down reference node in response to the potential of the pull-down reference node. On-off of the node and the first pull-down node, and controlling the potential of the first pull-down node based on the first power supply signal;
  • the noise reduction sub-circuit is respectively coupled to the first pull-down node, the first power supply terminal and the output terminal, and the noise reduction sub-circuit is configured to respond to the potential of the first pull-down node, and controlling the on-off of the first power supply terminal and the shift node.
  • the noise reduction sub-circuit includes: a third transistor, and the third transistor is a single-gate transistor;
  • the gate of the third transistor is coupled to the first pull-down node, the first pole of the third transistor is coupled to the first power supply terminal, and the second pole of the third transistor is coupled to the The output is coupled.
  • the first noise reduction control subcircuit includes: a fourth transistor, a fifth transistor, and a first capacitor;
  • the second noise reduction control subcircuit includes: a sixth transistor, a seventh transistor, and a second capacitor;
  • Both the gate of the fourth transistor and the gate of the sixth transistor are coupled to the shift node, and the first poles of the fourth transistor and the first pole of the sixth transistor are both connected to the shift node.
  • the second power supply terminal is coupled, the second pole of the fourth transistor is coupled to the pull-down reference node, and the second pole of the sixth transistor is coupled to the first pull-down node;
  • the gate of the fifth transistor is coupled to the first clock terminal, the first pole of the fifth transistor is coupled to the first power supply terminal, and the second pole of the fifth transistor is coupled to the pull-down Reference node coupling;
  • Both the gate and the first pole of the seventh transistor are coupled to the pull-down reference node, and the second pole of the seventh transistor is coupled to the first pull-down node;
  • One end of the first capacitor is coupled to the pull-down reference node, and the other end of the first capacitor is coupled to the second clock end;
  • One end of the second capacitor is coupled to the first pull-down node, and the other end of the second capacitor is coupled to the first power supply end.
  • the first shift circuit includes: an input subcircuit, a control subcircuit and a second output subcircuit;
  • the input sub-circuit is respectively coupled to the first clock terminal, the first power supply terminal, the input signal terminal, a pull-up node and a second pull-down node, and the input sub-circuit is configured to respond to the first A clock signal, controlling the on-off of the first power supply terminal and the pull-up node, and controlling the on-off of the input signal terminal and the second pull-down node;
  • the control subcircuit is respectively coupled to the pull-up node, the second pull-down node, the first clock terminal, the second clock terminal and the second power supply terminal, and the control subcircuit is used for In response to the potential of the pull-up node and the second clock signal, control the on-off of the second power supply terminal and the second pull-down node, and in response to the potential of the second pull-down node, control the On-off of the first clock terminal and the pull-up node;
  • the second output sub-circuit is respectively coupled to the pull-up node, the second pull-down node, the first power supply terminal, the second power supply terminal, the second clock terminal and the shift node , the second output subcircuit is used to control the on-off of the second power supply terminal and the shift node in response to the potential of the pull-up node, and in response to the potential of the second pull-down node and the
  • the first power supply signal is used to control the on-off of the second clock terminal and the shift node.
  • the input subcircuit includes: an eighth transistor and a ninth transistor;
  • the control subcircuit includes: a tenth transistor, an eleventh transistor, and a twelfth transistor;
  • the second output subcircuit includes: The thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the third capacitor and the fourth capacitor;
  • Both the gate of the eighth transistor and the gate of the ninth transistor are coupled to the first clock terminal, the first pole of the eighth transistor is coupled to the first power supply terminal, and the first The second pole of the eighth transistor is coupled to the pull-up node, the first pole of the ninth transistor is coupled to the input signal terminal, and the second pole of the ninth transistor is coupled to the second pull-down node catch;
  • the gate of the tenth transistor is coupled to the second pull-down node, the first pole of the tenth transistor is coupled to the first clock terminal, and the second pole of the tenth transistor is coupled to the upper pull node coupling;
  • the gate of the eleventh transistor is coupled to the pull-up node, the first pole of the eleventh transistor is coupled to the second power supply terminal, the second pole of the eleventh transistor is coupled to the The first pole of the twelfth transistor is coupled, the gate of the twelfth transistor is coupled to the second clock terminal, and the second pole of the twelfth transistor is coupled to the second pull-down node ;
  • the gate of the thirteenth transistor is coupled to the pull-up node, the first pole of the thirteenth transistor is coupled to the second power supply terminal, and the second pole of the thirteenth transistor is coupled to the pull-up node.
  • the gate of the fourteenth transistor is coupled to the first power supply terminal, the first pole of the fourteenth transistor is coupled to the second pull-down node, and the second pole of the fourteenth transistor is coupled to the The gate of the fifteenth transistor is coupled, the first pole of the fifteenth transistor is coupled to the second clock terminal, and the second pole of the fifteenth transistor is coupled to the shift node ;
  • One end of the third capacitor is coupled to the pull-up node, and the other end of the third capacitor is coupled to the second power supply end;
  • One end of the fourth capacitor is coupled to the gate of the fifteenth transistor, and the other end of the fourth capacitor is coupled to the shift node.
  • the output control terminal is coupled to the gate of the fifteenth transistor.
  • the transistors included in the shift register unit are all N-type transistors.
  • the shift register unit includes: a semiconductor layer located on one side of the base substrate, a first conductive layer, a second conductive layer and a third conductive layer;
  • the semiconductor layer at least includes: a channel region, a source region and a drain region of at least one transistor in the shift register unit;
  • the first conductive layer includes at least: a gate of at least one transistor in the shift register unit and a first capacitor electrode of at least one capacitor, and the gate of the at least one transistor overlaps the channel region;
  • the second conductive layer includes at least: a second capacitor electrode of at least one capacitor in the shift register unit, and the second capacitor electrode of the at least one capacitor overlaps the first capacitor electrode;
  • the third conductive layer at least includes: a plurality of signal lines, and the source and drain of at least one transistor in the shift register unit, and the source of the at least one transistor is coupled to the source region, the The drain of at least one transistor is coupled to the drain region, and the plurality of signal lines are respectively coupled to the respective signal terminals coupled to the shift register unit.
  • the plurality of signal lines include: a first group of signal lines, a second group of signal lines, and a third group of signal lines arranged at intervals along the first direction;
  • the first group of signal lines includes: a first power line coupled to the first power terminal;
  • the second group of signal lines includes: an enable control line coupled to the enable control terminal,
  • the third group of signal lines includes: the first power line;
  • the first group of signal lines, the first group of transistors in the shift register unit, the first group of capacitors in the shift register unit, the second group of signal lines, the shift register unit The second group of transistors in the shift register unit, the second group of capacitors in the shift register unit, and the third group of signal lines are arranged in sequence along the first direction; and at least one signal line in the plurality of signal lines Extending along a second direction, the first direction is a direction from the non-display area to the display area, and the second direction intersects the first direction.
  • the first group of signal lines further includes: an input signal line coupled to the input signal terminal, a first clock signal line coupled to the first clock terminal, and a second clock signal line coupled to the second clock terminal. clock signal line;
  • the second group of signal lines further includes: a second power line coupled to the second power terminal, the first clock signal line and the second clock signal line;
  • the third group of signal lines further includes: a third clock signal line coupled to the third clock terminal;
  • the input signal line, the first clock signal line, the second clock signal line and the first power line in the first group of signal lines are arranged in sequence, and the second group of signal lines
  • the second power line, the enable control line, the second clock signal line and the first clock signal line are arranged in sequence; the first power line and the third clock signal line in the third group of signal lines are arranged in sequence.
  • the first group of transistors includes: a fifth transistor, a sixth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor in the shift register unit and a fifteenth transistor;
  • the first group of capacitors includes: a third capacitor and a fourth capacitor in the shift register unit;
  • the second group of transistors includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a seventh transistor in the shift register unit;
  • the second group of capacitors includes: the first capacitor and the second capacitor in the shift register unit.
  • the fourth capacitor is located between the tenth transistor and the thirteenth transistor, and the edges of the tenth transistor, the fourth capacitor, and the thirteenth transistor are close to the second
  • the direction of the group signal lines is arranged in sequence;
  • the fifteenth transistor, the ninth transistor, the sixth transistor and the third capacitor are sequentially arranged along a direction close to the second group of signal lines;
  • the eleventh transistor is located between the fifteenth transistor and the tenth transistor, and is far away from the first group of signal lines relative to the fifteenth transistor;
  • the twelfth transistor and the eighth transistor are located between the ninth transistor and the fourth capacitor, and are arranged in sequence along a direction close to the second group of signal lines, and are all opposite to the first Eleven transistors are adjacent to the tenth transistor.
  • the fourth transistor is located between the first capacitor and the second capacitor, and edges of the first capacitor, the fourth transistor, and the second capacitor are close to the third group of signals
  • the directions of the lines are arranged in sequence;
  • the fifth transistor, the first transistor and the first capacitor are sequentially arranged along the second direction; the seventh transistor and the fourteenth transistor are located between the fifth transistor and the first between the transistors, and arranged in sequence along a direction close to the third group of signal lines;
  • the second transistor and the third transistor are arranged in sequence along the second direction, and are located on a side of the fourteenth transistor away from the second group of signal lines, and the second transistor is opposite to the The third transistor is far away from the fourth transistor.
  • the semiconductor layer of the fifth transistor, the semiconductor layer of the seventh transistor, and the semiconductor layer of the fourteenth transistor are integrated;
  • the semiconductor layer of the second transistor and the semiconductor layer of the third transistor are integrally structured.
  • the gate of the fifteenth transistor and the gate of the ninth transistor are integrated;
  • the first capacitor electrode of the third capacitor, the gate of the eighth transistor, and the gate of the second transistor are integrated;
  • the gate of the seventh transistor and the gate of the fourteenth transistor are integrated;
  • the gate of the third transistor and the first capacitor electrode of the second capacitor have an integral structure
  • the gate of the fourth transistor and the first capacitor electrode of the first capacitor have an integral structure
  • the gate of the tenth transistor is integrated with the first capacitor electrode of the fourth capacitor.
  • the orthographic projection of the gate of the second transistor and/or the gate of the third transistor on the base substrate is strip-shaped, and along the first extending in one direction; and, the orthographic projections of the gates of the other transistors on the base substrate are U-shaped except for the transistors whose gates are strip-shaped.
  • a method for driving a shift register unit in a display panel which is applied to the shift register unit as described in the above aspect, and the method includes:
  • the first shift circuit responds to the first clock signal of the first potential, the second clock signal of the second potential, the input signal of the first potential, the first power signal of the first potential and the second
  • the power signal controls the potential of the shift node to be the second potential
  • the second shift circuit responds to the second potential of the shift node, the first clock signal of the first potential, and the second clock signal of the second potential
  • the clock signal, the first power supply signal and the second power supply signal control the conduction between the first power supply terminal and the output terminal, and control the third clock terminal and the output terminal in response to the first potential output control signal
  • the terminal is turned on, and the second power supply terminal is controlled to be disconnected from the output terminal in response to the enable control signal of the second potential, and the potential of the third clock signal provided by the third clock terminal is the first potential;
  • the first shift circuit responds to the first clock signal of the second potential, the second clock signal of the first potential, the input signal of the second potential, the first power supply signal and the second power supply signal , controlling the potential of the shift node to be a first potential;
  • the second shift circuit responds to the first potential of the shift node, the first clock signal of the second potential, and the first clock signal of the first potential.
  • the second clock signal, the first power supply signal and the second power supply signal control the disconnection of the first power supply terminal from the output terminal, and control the third power supply terminal in response to the output control signal of the first potential
  • the clock terminal is connected to the output terminal, and in response to the enable control signal of the second potential, the second power supply terminal is controlled to be disconnected from the output terminal, and the potential of the third clock signal is the second potential ;
  • the first shift circuit responds to the first clock signal of the first potential, the second clock signal of the second potential, the input signal of the second potential, the first power supply signal and the first Two power supply signals, controlling the potential of the shift node to be a second potential;
  • the second shift circuit responds to the second potential of the shift node, the first clock signal of the first potential, and the first clock signal of the first potential
  • the second clock signal of two potentials, the first power supply signal and the second power supply signal control the conduction between the first power supply terminal and the output terminal, and control the
  • the third clock terminal is disconnected from the output terminal, and the second power supply terminal is controlled to be disconnected from the output terminal in response to the enable control signal of the second potential, and the potential of the third clock signal is: first potential;
  • the input phase, the output phase and the first pull-down phase are performed in a display phase of the pixel circuit coupled to the shift register unit.
  • the method further includes:
  • the first shift circuit responds to the first clock signal of the second potential, the second clock signal of the second potential, the input signal of the first potential, the first power supply signal and the second The power signal controls the potential of the shift node to be a second potential;
  • the second shift circuit responds to the second potential of the shift node, the first clock signal of the second potential, and the second The second clock signal of the potential, the first power supply signal and the second power supply signal, control the disconnection of the first power supply terminal from the output terminal, and control the output control signal of the second potential in response to the
  • the third clock terminal is disconnected from the output terminal, and in response to the enable control signal of the first potential, the second power supply terminal is controlled to be turned on with the output terminal, and the potential of the third clock signal is the first potential.
  • the second pull-down phase is performed in a blanking phase of the pixel circuit.
  • the period of the second clock signal is the same as the period of the third clock signal, and in the output stage, the duty cycle of the second clock signal is greater than the duty cycle of the third clock signal Compare.
  • a shift register in another aspect, includes: at least two cascaded shift register units; the shift register unit includes the shift register in the display panel as described in the above aspect unit;
  • the shift node of each stage of the shift register unit is coupled to the input signal end of the cascaded next stage of the shift register unit, and the output end of each stage of the shift register unit is connected to the target
  • the signal line is coupled, and the target signal line is the light emission control line coupled to the pixel circuit in the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a second shift circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another second shift circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another second shift circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a first shift circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another first shift circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 9 is a structural layout of a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 10 is a structural layout of an active layer included in a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 11 is a structural layout of a first conductive layer included in a shift register unit provided by an embodiment of the present disclosure
  • Fig. 12 is a structural layout of a second conductive layer included in a shift register unit provided by an embodiment of the present disclosure
  • FIG. 13 is a structural layout of a third conductive layer included in a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 14 is a structural layout of an interlayer intermediary layer included in a shift register unit provided by an embodiment of the present disclosure
  • FIG. 15 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 19 is a timing diagram of signal terminals coupled to a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 20 is a flowchart of a driving method for a shift register unit provided by an embodiment of the present disclosure
  • FIG. 21 is a flowchart of another driving method for a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 22 is a timing diagram of a signal terminal coupled to a shift register unit provided by an embodiment of the present disclosure
  • FIG. 23 is a comparison diagram of waveforms before and after improvement of an output terminal of a shift register unit provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure can be field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in circuits. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is called the first pole, and the drain is called the second pole, or the drain is called the first pole, and the source is called the second pole. According to the form in the accompanying drawings, it is stipulated that the middle terminal of the transistor is the gate, the signal input terminal is the source terminal, and the signal output terminal is the drain terminal.
  • the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is at a high level, and is turned off when the gate is at a low level.
  • multiple signals in various embodiments of the present disclosure correspond to effective potentials and ineffective potentials. Effective potentials and inactive potentials only mean that the potential of the signal has two state quantities, and it does not mean that the effective potential or ineffective potential in the full text has a specific value.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes: a base substrate 10 having a display area A0 and a non-display area B0 , and a shift register unit 00 located in the non-display area B0 .
  • the display area A0 and the non-display area B0 surrounding the display area A0 surrounding the display area A0. That is, the display area A0 is surrounded by the non-display area B0.
  • the non-display area B0 may only partially surround the display area A0. For example, referring to FIG. 1 , only three of the four sides of the display area A0 are surrounded by the non-display area B0 .
  • Fig. 2 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit 00 includes: a first shift circuit 01 and a second shift circuit 02 .
  • the first shift circuit 01 is respectively coupled to the first clock terminal CK, the second clock terminal CB, the input signal terminal IN, the first power supply terminal VGH, the second power supply terminal VGL and the shift node GO.
  • the first shift circuit 01 is used to respond to the first clock signal provided by the first clock terminal CK, the second clock signal provided by the second clock terminal CB, the input signal provided by the input signal terminal IN, and the first power supply terminal VGH provided
  • the first power supply signal provided by the second power supply terminal VGL and the second power supply signal provided by the second power supply terminal VGL control the potential of the shift node GO.
  • the first power supply terminal VGH and the second power supply terminal VGL may be DC power supply terminals, and the potential of the first power supply signal may be the first potential, and the potential of the second power supply signal may be the second potential.
  • the first potential may be an effective potential
  • the second potential may be an ineffective potential
  • the first potential may be a higher potential than the second potential. That is, the first potential may be greater than the second potential.
  • the first shift circuit 01 can control the shift node when the potential of the first clock signal and the potential of the input signal are both the first potential and the potential of the second clock signal is the second potential.
  • the potential of GO is the second potential.
  • the first shift circuit 01 can control the potential of the shift node GO to be the second potential when the potential of the first clock signal and the potential of the input signal are both the second potential, and the potential of the second clock signal is the first potential. a potential.
  • the second shift circuit 02 is respectively connected to the shift node GO, the first clock terminal CK, the second clock terminal CB, the third clock terminal CBO, the enable control terminal EN, the output control terminal CN_O, the first power supply terminal VGH, the second The power supply terminal VGL is coupled to the output terminal Eout.
  • the second shift circuit 02 is used to control the communication between the first power supply terminal VGH and the output terminal Eout in response to the potential of the shift node GO, the first clock signal, the second clock signal, the first power supply signal and the second power supply signal.
  • the second shift circuit 02 can control the first power supply terminal VGH and The output terminal Eout is turned on. At this time, the first power supply terminal VGH may transmit the first power supply signal of the first potential to the output terminal Eout. And, the second shift circuit 02 can control the first power supply terminal VGH and The output Eout is disconnected.
  • the second shift circuit 02 may also control the third clock terminal CBO to conduct with the output terminal Eout when the potential of the output control signal is the first potential. At this time, the third clock terminal CBO can transmit the third clock signal to the output terminal Eout. And, the second shift circuit 02 can also control the third clock terminal CBO to be disconnected from the output terminal Eout when the potential of the output control signal is the second potential.
  • the second shift circuit 02 may also control the second power supply terminal VGL and the output terminal Eout to conduct when the potential of the enable control signal is the first potential.
  • the second power supply terminal VGL can transmit the second power supply signal of the second potential to the output terminal Eout.
  • the second shift circuit 02 can also control the second power supply terminal VGL to be disconnected from the output terminal Eout when the potential of the enable control signal is the second potential.
  • the embodiments of the present disclosure provide a display panel.
  • the shift register unit in the display panel includes a first shift circuit and a second shift circuit, and the second shift circuit is connected to the enable control terminal respectively.
  • the second power supply terminal is coupled to the output terminal, and the second shift circuit can control the second power supply terminal to conduct with the output terminal under the control of the enable control terminal, that is, control the second power supply terminal to provide the second power supply signal to the output terminal .
  • the flexibility of the shift register unit to control the potential of its output terminal is improved.
  • the second shift circuit 02 provided by the embodiment of the present disclosure may be configured to: in the display stage of the pixel circuit coupled to the shift register unit, respond to the second The potential enable control signal controls the second power supply terminal VGL to be disconnected from the output terminal Eout. At this time, the second power supply terminal VGL cannot provide the second power supply signal of the second potential to the output terminal Eout. And, in the blanking phase of the pixel circuit coupled to the shift register unit, in response to the enable control signal of the first potential, the second power supply terminal VGL is controlled to conduct with the output terminal Eout.
  • the second power supply terminal VGL can be The second power signal of the second potential is transmitted to the output terminal Eout. That is, in the display phase, the enabling control terminal EN can be controlled to provide the enabling control signal of the second potential; and in the blanking phase, the enabling control terminal EN can be controlled to provide the enabling control signal of the first potential to realize the output
  • the flexible control of the potential of the terminal Eout ensures that the signal of the second potential is reliably provided to the output terminal Eout during the blanking phase.
  • FIG. 3 is a schematic structural diagram of a second shift circuit provided by an embodiment of the present disclosure.
  • the second shift circuit 02 may include: a first output control subcircuit 021 , a second output control subcircuit 022 and a first output subcircuit 023 .
  • the first output control sub-circuit 021 can be respectively coupled to the shift node GO, the first clock terminal CK, the second clock terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the output terminal Eout.
  • the first output control subcircuit 021 can be used to control the first power supply terminal VGH and the output terminal Eout in response to the potential of the shift node GO, the first clock signal, the second clock signal, the first power supply signal and the second power supply signal on and off.
  • the first output control subcircuit 021 can control the first power supply terminal VGH when the potential of the shift node GO and the potential of the first clock signal are both the second potential, and the potential of the second clock signal is the first potential. Conducted with the output terminal Eout. And, the first output control subcircuit 021 can control the first power supply terminal VGH when the potential of the shift node GO and the potential of the second clock signal are both the first potential, and the potential of the first clock signal is the second potential. Disconnect from output Eout.
  • the second output control sub-circuit 022 can be respectively coupled to the enable control terminal EN, the second power supply terminal VGL and the output terminal Eout.
  • the second output control sub-circuit 022 can be used to control the on-off of the second power supply terminal VGL and the output terminal Eout in response to the enable control signal.
  • the second output control sub-circuit 022 can control the second power supply terminal VGL and the output terminal Eout to conduct when the potential of the enable control signal is the first potential.
  • the first output control sub-circuit 021 can control the second power supply terminal VGL to be disconnected from the output terminal Eout when the potential of the enable control signal is the second potential.
  • the first output sub-circuit 023 may be respectively coupled to the output control terminal CN_O, the third clock terminal CBO and the output terminal Eout.
  • the first output sub-circuit 023 may be configured to control the on-off of the third clock terminal CBO and the output terminal Eout in response to the output control signal.
  • the first output sub-circuit 023 may control the third clock terminal CBO to conduct with the output terminal Eout when the potential of the output control signal is the first potential. And, the first output sub-circuit 023 can control the third clock terminal CBO to be disconnected from the output terminal Eout when the potential of the output control signal is the second potential.
  • FIG. 4 is a schematic structural diagram of another second shift circuit provided by an embodiment of the present disclosure.
  • the first output control subcircuit 021 may include: a first noise reduction control subcircuit 0211 , a second noise reduction control subcircuit 0212 and a noise reduction subcircuit 0213 .
  • the first noise reduction control sub-circuit 0211 can be respectively coupled to the shift node GO, the first clock terminal CK, the second clock terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the pull-down reference node PD0.
  • the first noise reduction control subcircuit 0211 can be used to control the on-off of the second power supply terminal VGL and the pull-down reference node PD0 in response to the potential of the shift node GO, and can control the first power supply terminal VGH in response to the first clock signal
  • the on-off of the pull-down reference node PD0 and the potential of the pull-down reference node PD0 can be controlled based on the second clock signal.
  • the first noise reduction control sub-circuit 0211 can control the second power supply terminal VGL to conduct with the pull-down reference node PD0 when the potential of the shift node GO is the first potential, at this time, the second power supply terminal VGL can be pulled down
  • the reference node PD0 transmits the second power signal of the second potential.
  • the first noise reduction control sub-circuit 0211 can control the second power supply terminal VGL to disconnect from the pull-down reference node PD0 when the potential of the shift node GO is the second potential.
  • the first noise reduction control sub-circuit 0211 can control the first power supply terminal VGH to conduct with the pull-down reference node PD0 when the potential of the first clock signal is the first potential, at this time, the first power supply terminal VGH can be pulled down
  • the reference node PD0 transmits a first power signal of a first potential.
  • the first noise reduction control sub-circuit 0211 can control the first power supply terminal VGH to disconnect from the pull-down reference node PD0 when the potential of the first clock signal is the second potential.
  • the second noise reduction control sub-circuit 0212 can be coupled to the shift node GO, the first power supply terminal VGH, the second power supply terminal VGL, the pull-down reference node PD0 and the first pull-down node PD1 respectively.
  • the second noise reduction control subcircuit 0212 can be used to control the on-off of the second power supply terminal VGL and the first pull-down node PD1 in response to the potential of the shift node GO, and to control
  • the pull-down reference node PD0 is connected to and disconnected from the first pull-down node PD1, and is used to control the potential of the first pull-down node PD1 based on the first power signal.
  • the second noise reduction control sub-circuit 0212 can control the second power supply terminal VGL to conduct with the pull-down reference node PD0 when the potential of the shift node GO is the first potential. At this time, the second power supply terminal VGL can be pulled down The reference node PD0 transmits the second power signal of the second potential. And the second noise reduction control sub-circuit 0212 can control the second power supply terminal VGL to be disconnected from the pull-down reference node PD0 when the potential of the shift node GO is the second potential.
  • the second noise reduction control sub-circuit 0212 can control the pull-down reference node PD0 to conduct with the first pull-down node PD1 when the potential of the pull-down reference node PD0 is the first potential. At this time, the potential of the pull-down reference node PD0 can be transmitted to the first pull-down node PD1. And the second noise reduction control sub-circuit 0212 can control the pull-down reference node PD0 to disconnect from the first pull-down node PD1 when the potential of the pull-down reference node PD0 is the second potential.
  • the noise reduction sub-circuit 0213 can be coupled to the first pull-down node PD1, the first power supply terminal VGH and the output terminal Eout respectively.
  • the noise reduction sub-circuit 0213 can be used to control the on-off of the first power supply terminal VGH and the shift node GO in response to the potential of the first pull-down node PD1.
  • the noise reduction sub-circuit 0213 can control the first power supply terminal VGH to conduct with the shift node GO when the potential of the first pull-down node PD1 is the first potential. At this time, the first power supply terminal VGH can be shifted to Node GO transmits a first power signal of a first potential.
  • the noise reduction sub-circuit 0213 can control the first power supply terminal VGH to be disconnected from the shift node GO when the potential of the first pull-down node PD1 is at the second potential.
  • FIG. 5 is a schematic structural diagram of another second shift circuit provided by an embodiment of the present disclosure.
  • the second output control sub-circuit 022 may include: a first transistor T1.
  • the first output sub-circuit 023 may include: a second transistor T2.
  • the noise reduction sub-circuit 0213 may include: a third transistor T3.
  • the first noise reduction control sub-circuit 0211 may include: a fourth transistor T4, a fifth transistor T5 and a first capacitor C1.
  • the second noise reduction control sub-circuit 0212 may include: a sixth transistor T6, a seventh transistor T7 and a second capacitor C2.
  • the gate of the first transistor T1 may be coupled to the enable control terminal EN, the first pole of the first transistor T1 may be coupled to the second power supply terminal VGL, and the second pole of the first transistor T1 may be coupled to the output terminal Eout coupling.
  • the gate of the second transistor T2 may be coupled to the output control terminal CN_O, the first terminal of the second transistor T2 may be coupled to the third clock terminal CBO, and the second terminal of the second transistor T2 may be coupled to the output terminal Eout.
  • the gate of the third transistor T3 may be coupled to the first pull-down node PD1, the first pole of the third transistor T3 may be coupled to the first power supply terminal VGH, and the second pole of the third transistor T3 may be coupled to the output terminal Eout. catch.
  • the gate of the fourth transistor T4 and the gate of the sixth transistor T6 can both be coupled to the shift node GO, and the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6 can both be connected to the second power supply terminal VGL
  • the second pole of the fourth transistor T4 may be coupled to the pull-down reference node PD0, and the second pole of the sixth transistor T6 may be coupled to the first pull-down node PD1.
  • the gate of the fifth transistor T5 may be coupled to the first clock terminal CK, the first pole of the fifth transistor T5 may be coupled to the first power supply terminal VGH, and the second pole of the fifth transistor T5 may be coupled to the pull-down reference node PD0. catch.
  • Both the gate and the first pole of the seventh transistor T7 may be coupled to the pull-down reference node PD0, and the second pole of the seventh transistor T7 may be coupled to the first pull-down node PD1.
  • One end of the first capacitor C1 may be coupled to the pull-down reference node PD0, and the other end of the first capacitor C1 may be coupled to the second clock terminal CB.
  • One terminal of the second capacitor C2 may be coupled to the first pull-down node PD1, and the other terminal of the second capacitor C2 may be coupled to the first power supply terminal VGH.
  • the second transistor T2 and/or the third transistor T3 may be single-gate transistors.
  • other transistors included in the shift register unit may all be double-gate transistors.
  • the second transistor T2 After testing, if the second transistor T2 is a double-gate transistor, the capacitance between the gate and the drain of the second transistor T2 will be larger, and correspondingly, the second transistor T2 will turn on slowly and insufficiently. In this way, the third clock signal at the first potential cannot be transmitted to the output terminal Eout quickly and completely at one time, and the first potential of the output terminal Eout has a step phenomenon. Therefore, by setting the second transistor T2 as a single-gate transistor, the capacitance value between the gate and the drain of the second transistor T2 can be effectively reduced, and correspondingly, the second transistor T2 can be quickly and fully turn on, to avoid step phenomenon in the first potential transmitted to the output terminal Eout through the second transistor T2. Thus, the problem of poor output of the output terminal Eout is improved.
  • the beneficial effect of setting the third transistor T3 as a double-gate transistor is the same, and will not be repeated here.
  • the output terminal Eout of the shift register unit may be coupled to the light emission control line.
  • the light emission control line is generally coupled with the pixel circuit, and in the light emission stage when the pixel circuit drives the coupled light emitting element to emit light, the light emission control line needs to provide a light emission control signal of the first potential, so that the pixel circuit can reliably transmit the light emission control signal to the light emitting element. driving current to drive the light emitting element to emit light. In other stages except the light-emitting stage, the light-emitting control line needs to provide a light-emitting control signal of the second potential.
  • the output terminal Eout of the shift register unit needs to transmit the signal of the first potential to the light-emitting control line, and in other phases except the light-emitting phase, the output terminal Eout of the shift register unit needs to transmit the signal of the second potential to the light control line.
  • the second shift circuit 02 also includes a second output control sub-circuit 022 (that is, the first transistor T1), and setting the second output control sub-circuit 022 to respond to the enable control signal to the output terminal Eout directly transmits the second power signal of the second potential.
  • a second output control sub-circuit 022 that is, the first transistor T1
  • setting the second output control sub-circuit 022 to respond to the enable control signal to the output terminal Eout directly transmits the second power signal of the second potential.
  • FIG. 6 is a schematic structural diagram of a first shift circuit provided by an embodiment of the present disclosure.
  • the first shift circuit 01 may include: an input subcircuit 011 , a control subcircuit 012 and a second output subcircuit 013 .
  • the input sub-circuit 011 can be respectively coupled to the first clock terminal CK, the first power supply terminal VGH, the input signal terminal IN, the pull-up node PU and the second pull-down node PD2.
  • the input sub-circuit 011 can be used to control the on-off of the first power supply terminal VGH and the pull-up node PU, and control the on-off of the input signal terminal IN and the second pull-down node PD2 in response to the first clock signal.
  • the input sub-circuit 011 may control the first power supply terminal VGH to conduct with the pull-up node PU, and control the input signal terminal IN to conduct with the second pull-down node PD2 when the potential of the first clock signal is the first potential.
  • the first power terminal VGH can transmit the first power signal of the first potential to the pull-up node PU
  • the input signal terminal IN can transmit the input signal to the second pull-down node PD2.
  • the input sub-circuit 011 can control the first power supply terminal VGH to be disconnected from the pull-up node PU, and control the input signal terminal IN to be disconnected from the second pull-down node PD2 when the potential of the first clock signal is the second potential. connect.
  • the control sub-circuit 012 can be respectively coupled to the pull-up node PU, the second pull-down node PD2, the first clock terminal CK, the second clock terminal CB and the second power supply terminal VGL.
  • the control subcircuit 012 can be used to control the on-off of the second power supply terminal VGL and the second pull-down node PD2 in response to the potential of the pull-up node PU and the second clock signal, and can respond to the potential of the second pull-down node PD2, Controlling the on-off of the first clock terminal CK and the pull-up node PU.
  • control subcircuit 012 can control the second power supply terminal VGL to conduct with the second pull-down node PD2 when the potential of the pull-up node PU and the potential of the second clock signal are both at the first potential.
  • the second power supply The terminal VGL can transmit the second power signal of the second potential to the second pull-down node PD2.
  • control subcircuit 012 can control the second power supply terminal VGL to disconnect from the second pull-down node PD2 when the potential of the pull-up node PU and/or the potential of the second clock signal is the second potential.
  • control subcircuit 012 can control the first clock terminal CK to conduct with the pull-up node PU when the potential of the second pull-down node PD2 is the first potential, and at this time, the first clock terminal CK can transmit to the pull-up node PU first clock signal. And the control subcircuit 012 can control the first clock terminal CK to disconnect from the pull-up node PU when the potential of the second pull-down node PD2 is the second potential.
  • the second output sub-circuit 013 can be respectively coupled to the pull-up node PU, the second pull-down node PD2, the first power supply terminal VGH, the second power supply terminal VGL, the second clock terminal CB and the shift node GO.
  • the second output sub-circuit 013 can be used to control the on-off of the second power supply terminal VGL and the shift node GO in response to the potential of the pull-up node PU, and can respond to the potential of the second pull-down node PD2 and the first power signal , to control the on-off of the second clock terminal CB and the shift node GO.
  • the second output sub-circuit 013 may control the second power supply terminal VGL to conduct with the shift node GO when the potential of the pull-up node PU is the first potential. At this time, the second power supply terminal VGL can transmit the second power supply signal of the second potential to the shift node GO. And the second output sub-circuit 013 can control the second power supply terminal VGL to disconnect from the shift node GO when the potential of the pull-up node PU is the second potential.
  • the second output sub-circuit 013 can control the second clock terminal CB in response to the potential of the second pull-down node PD2 and the first power signal of the first potential when the potential of the second pull-down node PD2 is the first potential. conducts with shift node GO. At this time, the second clock terminal CB can transmit the second clock signal to the shift node GO. And the second output sub-circuit 013 can control the second clock terminal CB and Shift node GO disconnects.
  • FIG. 7 is a schematic structural diagram of another first shift circuit provided by an embodiment of the present disclosure.
  • the input sub-circuit 011 may include: an eighth transistor T8 and a ninth transistor T9 .
  • the control sub-circuit 012 may include: a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12.
  • the second output sub-circuit 013 may include: a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a third capacitor C3 and a fourth capacitor C4.
  • the gate of the eighth transistor T8 and the gate of the ninth transistor T9 may both be coupled to the first clock terminal CK, the first pole of the eighth transistor T8 may be coupled to the first power supply terminal VGH, and the eighth transistor T8
  • the second pole of the ninth transistor T9 may be coupled to the pull-up node PU, the first pole of the ninth transistor T9 may be coupled to the input signal terminal IN, and the second pole of the ninth transistor T9 may be coupled to the second pull-down node PD2.
  • the gate of the tenth transistor T10 may be coupled to the second pull-down node PD2, the first pole of the tenth transistor T10 may be coupled to the first clock terminal CK, and the second pole of the tenth transistor T10 may be coupled to the pull-up node PU. catch.
  • the gate of the eleventh transistor T11 may be coupled to the pull-up node PU, the first pole of the eleventh transistor T11 may be coupled to the second power supply terminal VGL, and the second pole of the eleventh transistor T11 may be coupled to the twelfth power supply terminal VGL.
  • the first pole of the transistor T12 is coupled, the gate of the twelfth transistor T12 may be coupled to the second clock terminal CB, and the second pole of the twelfth transistor T12 may be coupled to the second pull-down node PD2.
  • the gate of the thirteenth transistor T13 can be coupled to the pull-up node PU, the first pole of the thirteenth transistor T13 can be coupled to the second power supply terminal VGL, and the second pole of the thirteenth transistor T13 can be coupled to the shift node GO coupling.
  • the gate of the fourteenth transistor T14 may be coupled to the first power supply terminal VGH, the first pole of the fourteenth transistor T14 may be coupled to the second pull-down node PD2, and the second pole of the fourteenth transistor T14 may be coupled to the tenth
  • the gate of the fifth transistor T15 is coupled, the first terminal of the fifteenth transistor T15 may be coupled to the second clock terminal CB, and the second terminal of the fifteenth transistor T15 may be coupled to the shift node GO.
  • One end of the third capacitor C3 can be coupled to the pull-up node PU, and the other end of the third capacitor C3 can be coupled to the second power supply terminal VGL.
  • One end of the fourth capacitor C4 may be coupled to the gate of the fifteenth transistor T15, and the other end of the fourth capacitor C4 may be coupled to the shift node GO.
  • FIG. 8 shows a schematic diagram of an overall structure of another shift register unit provided by an embodiment of the present disclosure.
  • the output control terminal CN_O coupled to the first output sub-circuit 023 ie, the second transistor T2
  • the output control terminal CN_O may be coupled to the gate of the fifteenth transistor T15 . That is, the potential of the output control signal provided by the output control terminal CN_O may be the same as the potential at the gate of the fifteenth transistor T15. In this way, the number of signal terminals that need to be set can be simplified and the cost can be saved.
  • the transistors included in the shift register unit described in the embodiments of the present disclosure may all be N-type transistors.
  • each transistor may also be a P-type transistor, and if it is a P-type transistor, the first potential may be a lower potential than the second potential.
  • FIG. 9 shows a structural layout of a shift register unit
  • FIG. 10 to FIG. 14 respectively show the Show the layout of different layers in the structure layout. 9 to 14, it can be seen that the shift register unit may include: a semiconductor layer on one side of the base substrate, a first conductive layer, a second conductive layer and a third conductive layer.
  • the semiconductor layer at least includes: a channel region, a source region and a drain region of at least one transistor in the shift register unit.
  • the semiconductor layer at least includes: a channel region a11 , a source region a21 and a drain region a31 of the first transistor T1 .
  • the first conductive layer may at least include: a gate of at least one transistor in the shift register unit and a first capacitor electrode of at least one capacitor, and the gate of at least one transistor overlaps with the channel region.
  • the first conductive layer at least includes: the gate b1 of the first transistor T1, the gate b2 of the second transistor T2, the gate b3 of the third transistor T3, and the gate of the fourth transistor T4.
  • the gate of each transistor overlaps with its channel region.
  • the second conductive layer may at least include: a second capacitor electrode of at least one capacitor in the shift register unit, and the second capacitor electrode of the at least one capacitor overlaps with the first capacitor electrode.
  • the second conductive layer at least includes: the second capacitor electrode c11 of the first capacitor C1, the second capacitor electrode c21 of the second capacitor C2, the second capacitor electrode c31 of the third capacitor C3, and The second capacitor electrode c41 of the fourth capacitor C4.
  • the first capacitor electrode of each capacitor overlaps with its second capacitor electrode.
  • the first capacitor electrode c10 of the first capacitor C1 overlaps with the second capacitor electrode c11.
  • the third conductive layer may at least include: a plurality of signal lines, and the source and drain of at least one transistor in the shift register unit, and the source of the at least one transistor is coupled to the source region, and the drain of the at least one transistor is connected to the source region.
  • the drain region is coupled, and a plurality of signal lines are respectively coupled to each signal terminal coupled to the shift register unit.
  • the third conductive layer includes: a first power line vgh1 .
  • the source of each transistor is coupled to its source region
  • the drain is coupled to its drain region
  • the multiple signal lines are respectively coupled to each of the shift register units.
  • the signal terminal is coupled.
  • the first power line vgh1 is coupled to the first power supply terminal VGH
  • the input signal line in1 is coupled to the input signal terminal IN
  • the first clock signal line ck1 is coupled to the first clock terminal CK
  • the second clock signal line cb1 is coupled to the first clock terminal CK.
  • the second clock terminal CB is coupled
  • the enable control line en1 is coupled to the enable control terminal EN
  • the second power supply line vgl2 is coupled to the second power supply terminal VGL
  • the third clock signal line cbo1 is coupled to the third clock terminal CBO. catch.
  • the shift register unit provided by the embodiment of the present disclosure further includes: an interlayer intermediary layer for forming via holes.
  • the via hole is used to expose the conductive layers stacked in sequence and to be coupled, so that the conductive layers are coupled to each other.
  • the multiple signal lines provided by the embodiments of the present disclosure may include: a first group of signal lines L01, a second group of signal lines L02, and a third group of signal lines arranged at intervals along the first direction X1.
  • the first group of signal lines L01 may include: a first power line vgh1 coupled to the first power supply terminal VGH, an input signal line in1 coupled to the input signal terminal IN, and a first clock signal line coupled to the first clock terminal CK ck1, and the second clock signal line cb1 coupled to the second clock terminal CB.
  • the second group of signal lines L02 may include: an enable control line en1 coupled to the enable control terminal EN, a second power supply line vgl2 coupled to the second power supply terminal VGL, a first clock signal line ck1 and a second clock signal line cb1 .
  • the third group of signal lines L03 may include: a first power line vgh1, and a third clock signal line cbo1 coupled to the third clock terminal CBO.
  • the first group of signal lines L01, the first group of transistors in the shift register unit 00, the first group of capacitors in the shift register unit 00, and the second group of signal lines may be sequentially arranged along the first direction X1 . At least one signal line among the plurality of signal lines extends along the second direction X2.
  • the input signal line in1, the first clock signal line ck1, the second clock signal line cb1 and the first power line vgh1 in the first group of signal lines L02 are arranged in sequence, and the second group of signal lines L02
  • the second power line vgl2, the enable control line en1, the second clock signal line cb1 and the first clock signal line ck1 are arranged in sequence.
  • the first power line vgh1 and the third clock signal line cbo1 in the third group of signal lines L03 are arranged in sequence.
  • the first direction X1 is a direction from the non-display area B0 to the display area A0
  • the second direction X2 intersects the first direction X1.
  • FIG. 9 and FIG. 13 it can be seen that the first direction X1 and the second direction X2 shown therein are perpendicular to each other.
  • the first group of transistors may include: the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 in the shift register unit 00 , the twelfth transistor T12, the thirteenth transistor T13 and the fifteenth transistor T15.
  • the first group of capacitors may include: a third capacitor C3 and a fourth capacitor C4 in the shift register unit 00 .
  • the second group of transistors may include: a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 and a seventh transistor T7 in the shift register unit 00 .
  • the second group of capacitors may include: a first capacitor C1 and a second capacitor C2 in the shift register unit 00 .
  • the fourth capacitor C4 may be located between the tenth transistor T10 and the thirteenth transistor T13, and the tenth transistor T10, the fourth capacitor C4, and the thirteenth transistor T13 may be located close to The directions of the second group of signal lines L02 are arranged sequentially.
  • the fifteenth transistor T15 , the ninth transistor T9 , the sixth transistor T6 and the third capacitor C3 may be sequentially arranged along a direction close to the second group of signal lines L02 .
  • the eleventh transistor T11 may be located between the fifteenth transistor T15 and the tenth transistor T10 , and is farther away from the first group of signal lines L01 than the fifteenth transistor T15 .
  • the twelfth transistor T12 and the eighth transistor T8 may be located between the ninth transistor T9 and the fourth capacitor C4, and are arranged in sequence along the direction close to the second group of signal lines L02, and are closer to the eleventh transistor T11 than the eleventh transistor T11.
  • the fourth transistor T4 may be located between the first capacitor C1 and the second capacitor C2, and the edges of the first capacitor C1, the fourth transistor T4, and the second capacitor C2 are close to the third group
  • the directions of the signal lines L03 are arranged sequentially.
  • the fifth transistor T5, the first transistor T1 and the first capacitor C1 may be arranged in sequence along the second direction X2.
  • the seventh transistor T7 and the fourteenth transistor T14 may be located between the fifth transistor T5 and the first transistor T1 and arranged in sequence along a direction close to the third group of signal lines L03 .
  • the second transistor T2 and the third transistor T3 can be arranged in sequence along the second direction, and are located on the side of the fourteenth transistor T14 away from the second group of signal lines L02, and the second transistor T2 is farther away from the fourth transistor T3 than the third transistor T3.
  • the semiconductor layer of the fifth transistor T5 , the semiconductor layer of the seventh transistor T7 and the semiconductor layer of the fourteenth transistor T14 may have an integrated structure.
  • the semiconductor layer of the second transistor T2 and the semiconductor layer of the third transistor T3 may be of an integral structure.
  • the gate b15 of the fifteenth transistor T15 and the gate b9 of the ninth transistor T9 may have an integral structure.
  • the first capacitor electrode c30 of the third capacitor C3, the gate b8 of the eighth transistor T8 and the gate b2 of the second transistor T2 may be of an integral structure.
  • the gate b7 of the seventh transistor T7 and the gate b14 of the fourteenth transistor T14 may have an integral structure.
  • the gate b3 of the third transistor T3 and the first capacitor electrode c20 of the second capacitor C2 may have an integral structure.
  • the gate b4 of the fourth transistor T4 and the first capacitor electrode c10 of the first capacitor C1 may have an integral structure.
  • the gate b10 of the tenth transistor T10 and the first capacitor electrode c40 of the fourth capacitor C4 may be integrated.
  • the orthographic projection of the gate b2 of the second transistor T2 and/or the gate b3 of the third transistor T3 on the base substrate 10 may be strip-shaped, and along the The first direction X1 extends.
  • the orthographic projections of the gates of the other transistors on the base substrate 10 except for the transistors whose gates are strip-shaped may all be U-shaped, that is, a double-gate structure.
  • the integral structure may be formed by one patterning process, and the patterning process may include film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. Any one or more of sputtering, evaporation and chemical vapor deposition can be used for deposition, any one or more of spray coating and spin coating can be used for coating, and any of dry etching and wet etching can be used for etching. one or more.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate. If the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a "layer”. If the "film” requires a patterning process during the entire production process, it is called a "film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the embodiments of the present disclosure provide a display panel.
  • the shift register unit in the display panel includes a first shift circuit and a second shift circuit, and the second shift circuit is connected to the enable control terminal respectively.
  • the second power supply terminal is coupled to the output terminal, and the second shift circuit can control the second power supply terminal to conduct with the output terminal under the control of the enable control terminal, that is, control the second power supply terminal to provide the second power supply signal to the output terminal .
  • the flexibility of the shift register unit to control the potential of its output terminal is improved.
  • Fig. 15 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register 000 includes: at least two cascaded shift register units 00 as shown in any one of FIG. 2 , FIG. 8 and FIG. 9 .
  • the shift node GO of each stage of shift register unit 00 can be coupled to the input signal terminal IN of the cascaded next stage of shift register unit 00, and the output terminal Eout of each stage of shift register unit 00 can be connected to the target Signal lines are coupled (not shown in the figure).
  • the shift register unit 00 of each stage can transmit a driving signal to the coupled target signal line through its output terminal Eout, and the target signal line can be coupled with the pixel circuit in the display panel, and the pixel circuit can be based on the signal provided by the target signal line. signal to drive the coupled light-emitting element to emit light.
  • the target signal line may be a lighting control line.
  • the shift register unit 00 of each stage can also be connected with the first clock terminal CK, the second clock terminal CB, the third clock terminal CBO, the first power supply terminal VGH, the second power supply terminal VGL and the enable
  • the control terminal EN is coupled (not shown in FIG. 15 ).
  • the input signal terminal IN of the first-stage shift register unit 00 may be coupled to the frame start signal terminal STV shown in FIG. 15 for receiving the frame start signal from the frame start signal terminal STV.
  • FIG. 16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device may include: the display panel 100 described in the above-mentioned embodiments.
  • the display panel 100 may further include multiple pixel circuits 1001 and multiple target signal lines L1, the multiple pixel circuits 1001 are coupled to the multiple target signal lines L1 one by one, and each pixel circuit 1001 is also coupled to a light emitting element. connection (not shown in the figure).
  • the shift register 000 can be coupled to multiple target signal lines L1, and the shift register 000 can be used to provide driving signals for the multiple target signal lines L1.
  • the pixel circuit 1001 can be used to drive the coupled light emitting element to emit light based on the driving signal.
  • FIG. 17 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit 1001 may include: a switch subcircuit 10011 , a drive subcircuit 10012 , a light emission control subcircuit 10013 , an external compensation subcircuit 10014 and an adjustment subcircuit 10015 .
  • the switch sub-circuit 10011 can be respectively coupled to the gate line G1, the data line D1 and the first node P1.
  • the switch sub-circuit 10011 can be used for controlling the on-off of the data line D1 and the first node P1 in response to the gate driving signal from the gate line G1.
  • the switch subcircuit 10011 can control the data line D1 to conduct with the first node P1 when the potential of the gate driving signal is the first potential, and at this time, the data line D1 can transmit data signals to the first node P1. And, the switching sub-circuit 1001 can control the data line D1 to be disconnected from the first node P1 when the potential of the gate driving signal is the second potential.
  • the driving sub-circuit 10012 can be respectively coupled to the first node P1, the driving power supply terminal Vdd and the second node P2, and the driving sub-circuit 10012 can be used to provide the driving power supply signal based on the potential of the first node P1 and the driving power supply terminal Vdd to The second node P2 transmits a driving signal.
  • the driving sub-circuit 10012 can transmit the driving current to the second node P2 based on the potential of the first node P1 and the driving power signal.
  • the light emission control sub-circuit 10013 may be coupled to the light emission control line EM, the second node P2 and the light emitting element L0 respectively.
  • the light emission control sub-circuit 10013 can be used for controlling the on/off of the second node P2 and the light emitting element L0 in response to the light emission control signal from the light emission control line EM.
  • the light emission control sub-circuit 10013 can be coupled to the anode of the light emitting element L0, and the cathode of the light emitting element L0 can also be coupled to the pull-down power supply terminal ELVss.
  • the light emission control subcircuit 10013 can control the second node P2 to conduct with the light emitting element L0 when the potential of the light emission control signal is the first potential.
  • the driving current transmitted to the second node P2 by the driving subcircuit 10012 can be passed
  • the light emission control sub-circuit 10013 transmits to the light emitting element L0 to drive the light emitting element L0 to emit light.
  • the light emission control subcircuit 10013 can control the second node P2 to be disconnected from the light emitting element L0 when the potential of the light emission control signal is the second potential.
  • the external compensation sub-circuit 10014 can be coupled to the scanning signal line S1, the second node P2 and the detection signal line S0 respectively.
  • the external compensation sub-circuit 10014 can be used to control the connection between the second node P2 and the detection signal line S0 in response to the scan signal provided by the scan signal line S1 .
  • the external compensation sub-circuit 10014 can control the second node P2 to conduct with the detection signal line S0 when the potential of the scanning signal is the first potential, at this time, the detection signal line S0 can transmit the detection signal to the second node P2, And the detection signal line S0 can collect the potential of the second node P2. And, the external compensation sub-circuit 10014 can control the second node P2 to be disconnected from the detection signal line S0 when the potential of the scanning signal is the second potential.
  • the regulating sub-circuit 10015 may be coupled to the first node P1 and the second node P2 respectively.
  • the adjusting sub-circuit 10015 can be used to adjust the potential of the first node P1 and the potential of the second node P2.
  • the adjustment subcircuit 10015 can adjust the potential of the first node P1 and the potential of the second node P2 through a bootstrap function.
  • FIG. 18 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the switch subcircuit 10011 may include: a switch transistor K1.
  • the driving sub-circuit 10012 may include: a driving transistor K2.
  • the light emission control sub-circuit 10013 may include: a light emission control transistor K3.
  • the external compensation sub-circuit 10014 may include: a compensation transistor K4.
  • the adjustment sub-circuit 10015 may include: a storage capacitor C0.
  • the gate of the switching transistor K1 may be coupled to the gate line G1
  • the first pole of the switching transistor K1 may be coupled to the data line
  • the second pole of the switching transistor K1 may be coupled to the first node P1.
  • the gate of the driving transistor K2 can be coupled to the driving power supply terminal Vdd, the first pole of the driving transistor K2 can be coupled to the first node P1, and the second pole of the driving transistor K2 can be coupled to the second node P2.
  • the gate of the light emission control transistor K3 can be coupled to the light emission control line EM, the first pole of the light emission control transistor K3 can be coupled to the second node P2, and the second pole of the light emission control transistor K3 can be coupled to the light emitting element L0.
  • the gate of the compensation transistor K4 can be coupled to the scanning signal line S1, the first pole of the compensation transistor K4 can be coupled to the second node P2, and the second pole of the compensation transistor K4 can be coupled to the detection signal line S0.
  • One end of the storage capacitor C0 may be coupled to the first node P1, and the other end of the storage capacitor C0 may be coupled to the second node P2.
  • the target signal line coupled to the shift register 000 described in the embodiments of the present disclosure may be the light emission control line EM. That is, the output terminal Eout of each stage of the shift register unit 00 included in the shift register 000 can be coupled to the light emission control line EM for providing the required light emission control signal to the light emission control line EM.
  • the detection signal line S0 coupled to the compensation transistor K4 may also be coupled to an external compensation circuit
  • the data line D1 may also be coupled to a source driving circuit.
  • the external compensation circuit can determine the threshold voltage of the driving transistor K2 based on the potential of the second node P2 collected by the detection signal line S0, and transmit the threshold voltage to the source driving circuit.
  • the source driving circuit can flexibly adjust and provide required data signals to the coupled data line D1 based on the received threshold voltage, so as to avoid adverse effects of threshold voltage drift on the light emitting effect of the light emitting element L1. This process can also be called external compensation.
  • FIG. 19 shows a driving timing diagram of each signal terminal in a pixel circuit. It includes two stages, a display stage T100 and a blanking stage T200. Wherein, the display phase T100 may further include an initialization phase t01 , a data writing phase t02 and a light emitting phase t03 .
  • the potential of the scanning signal provided by the scanning signal line S1 may be the first potential, and the compensation transistor K4 is turned on.
  • the detection signal line S0 can transmit the detection signal of the second potential to the second node P2 through the turned-on compensation transistor K4, so as to realize the reset of the second node P2.
  • the shift register unit 00 can provide the light emission control signal of the second potential to the light emission control line EM, that is, the potential of the light emission control signal provided by the light emission control line EM is the second potential, and the light emission control transistor K3 is turned off.
  • the potential of the gate driving signal provided by the gate line G1 is the second potential, and the switching transistor K1 is turned off.
  • the driving transistor K2 is also turned off.
  • the shift register unit 00 still provides the light emission control signal of the second potential to the light emission control line EM, that is, the potential of the light emission control signal remains at the second potential, and the light emission control transistor K3 remains turned off.
  • the potential of the scanning signal jumps to the second potential, and the compensation transistor K4 is turned off.
  • the potential of the gate driving signal jumps to the first potential, and the switching transistor K1 is turned on.
  • the data signal provided by the data line D1 can be transmitted to the first node P1 through the turned-on switching transistor K1, so as to realize charging of the first node P1.
  • the shift register unit 00 can provide the light emission control signal of the first potential to the light emission control line EM, that is, the potential of the light emission control signal jumps to the first potential, and the light emission control transistor K3 is turned on.
  • the potential of the first node P1 is maintained at the first potential under the bootstrap effect of the storage capacitor C0, and the driving transistor K2 is turned on.
  • the driving transistor K2 transmits the driving current to the second node P2 based on the potential of the first node P1 and the driving power signal provided by the driving power terminal Vdd.
  • the driving current is then transmitted to the light-emitting element L1 through the turned-on light-emitting control transistor K3, and the light-emitting element L1 emits light.
  • the shift register unit 00 can provide the light emission control signal of the second potential to the light emission control line EM, that is, the potential of the light emission control signal jumps to the second potential, and the light emission control transistor K3 is turned off.
  • the potential of the gate driving signal remains at the second potential, and the switching transistor K1 is turned off.
  • the potential of the scan signal jumps to the first potential, and the compensation transistor K4 is turned on.
  • the potential of the second node P2 can be transmitted to the detection signal line S0 through the turned-on compensation transistor K4, and the detection signal line S0 transmits the collected potential of the second node P2 to the coupled external compensation circuit, so that the external The compensation circuit externally compensates the data signal supplied to the data line D1 based on the potential of the second node P2.
  • FIG. 19 also shows the timing of the enable control terminal EN coupled to the shift register unit.
  • the enable control terminal EN can continuously provide the enable control signal of the second potential, and in the blanking phase, the potential of the enable control signal can jump to the first potential.
  • the first transistor T1 in the shift register unit 00 is turned on, and the second power signal of the second potential can be reliably transmitted to the output terminal Eout through the turned-on first transistor T1 . Since the output terminal Eout of the shift register unit 00 is coupled to the light emission control line EM, it is effectively ensured that in the blanking phase, the light emission control line EM can reliably receive the light emission control signal at the second potential, that is, ensure that the light emission control signal Able to maintain a stable low level during the blanking phase.
  • FIG. 20 is a flow chart of a method for driving a shift register unit in a display panel provided by an embodiment of the present disclosure, and the method can be applied to the shift register unit 00 shown in the above-mentioned drawings. As shown in Figure 20, the method may include:
  • Step 2001 input stage, the first shift circuit responds to the first clock signal of the first potential, the second clock signal of the second potential, the input signal of the first potential, the first power signal of the first potential and the second potential
  • the second power supply signal controls the potential of the shift node to be the second potential
  • the second shift circuit responds to the second potential of the shift node, the first clock signal of the first potential, the second clock signal of the second potential
  • the first power supply signal and the second power supply signal control the conduction of the first power supply terminal and the output terminal, control the conduction of the third clock terminal and the output terminal in response to the output control signal of the first potential, and respond to the enabling of the second potential
  • the control signal controls the second power supply terminal to be disconnected from the output terminal.
  • Step 2002 output stage, the first shift circuit responds to the first clock signal of the second potential, the second clock signal of the first potential, the input signal of the second potential, the first power signal and the second power signal, and controls the shifting
  • the potential of the bit node is a first potential
  • the second shift circuit responds to the first potential of the shift node, the first clock signal of the second potential, the second clock signal of the first potential, the first power supply signal and the second power supply signal to control the disconnection of the first power supply terminal from the output terminal, to control the conduction of the third clock terminal to the output terminal in response to the output control signal of the first potential, and to control the second The power supply terminal is disconnected from the output terminal.
  • Step 2003 the first pull-down stage, the first shift circuit responds to the first clock signal of the first potential, the second clock signal of the second potential, the input signal of the second potential, the first power supply signal and the second power supply signal , the potential of the shift node is controlled to be the second potential, and the second shift circuit responds to the second potential of the shift node, the first clock signal of the first potential, the second clock signal of the second potential, the first power supply signal and
  • the second power supply signal controls the first power supply terminal to be turned on with the output terminal, controls the third clock terminal to be disconnected from the output terminal in response to the output control signal of the second potential, and responds to the enable control signal of the second potential,
  • the second power supply terminal is controlled to be disconnected from the output terminal.
  • the input phase, the output phase and the first pull-down phase can be executed sequentially in the display phase T100 of the pixel circuit.
  • the method may further include:
  • Step 2004, the second pull-down stage, the first shift circuit responds to the first clock signal of the second potential, the second clock signal of the second potential, the input signal of the first potential, the first power signal and the second power signal, Controlling the potential of the shift node to be a second potential, the second shift circuit responds to the second potential of the shift node, the first clock signal of the second potential, the second clock signal of the second potential, the first power supply signal and the second Two power supply signals, controlling the disconnection of the first power supply terminal from the output terminal, controlling the disconnection of the third clock terminal from the output terminal in response to the output control signal of the second potential, and responding to the enable control signal of the first potential,
  • the second power supply terminal is controlled to conduct with the output terminal.
  • the potential of the third clock signal provided by the third clock terminal is the first potential.
  • the potential of the third clock signal is the second potential.
  • the potential of the third clock signal is the first potential.
  • the potential of the third clock signal is the second potential.
  • the second pull-down phase can be performed in the blanking phase T200 of the pixel circuit.
  • FIG. 22 shows a timing diagram of various signal terminals coupled to a shift register unit and a shift node GO.
  • the potential of the input signal provided by the input signal terminal IN, the potential of the first clock signal provided by the first clock terminal CK, and the potential of the third clock signal provided by the third clock terminal CBO are all the first potential; the potential of the second clock signal provided by the second clock terminal CB and the potential of the enable control signal provided by the enable control terminal EN are both the second potential.
  • the fifth transistor T5 , the eighth transistor T8 and the ninth transistor T9 are all turned on, and the first transistor T1 and the twelfth transistor T12 are all turned off.
  • the fourteenth transistor T14 is turned on under the control of the first power signal of the first potential.
  • the first power signal of the first potential is transmitted to the pull-up node PU through the turned-on eighth transistor T8, the thirteenth transistor T13 is turned on, and the second power signal of the second potential is passed through the turned-on thirteenth transistor T8.
  • Transistor T13 transmits to shift node GO.
  • the input signal of the first potential is transmitted to the second pull-down node PD2 through the turned-on ninth transistor T9.
  • the tenth transistor T10 is turned on, and the first clock signal of the first potential is transmitted to the pull-up node PU through the turned-on tenth transistor T10 .
  • the input signal of the first potential written into the second pull-down node PD2 continues to be transmitted to the gate of the fifteenth transistor T15 through the turned-on fourteenth transistor T14.
  • the fifteenth transistor T15 is turned on, and the second clock signal at the second potential is transmitted to the shift node GO through the turned-on fifteenth transistor T15 .
  • Both the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the first power signal of the first potential is transmitted to the pull-down reference node PD0 through the turned-on fifth transistor T5, and correspondingly, the seventh transistor T7 is turned on.
  • the first power signal of the first potential written into the pull-down reference node PD0 continues to be transmitted to the first pull-down node PD1 through the turned-on seventh transistor T7.
  • the third transistor T3 is turned on.
  • the first power signal of the first potential is transmitted to the output terminal Eout through the turned-on third transistor T3.
  • the output control terminal CN_O is coupled to the gate of the fifteenth transistor T15, the potential of the input control signal provided by the output control terminal CN_O is also the first potential, the second transistor T2 is turned on, and the third clock of the first potential The signal is transmitted to the output terminal Eout through the turned-on second transistor T2.
  • the potential of the second clock signal jumps to the first potential, the potential of the input signal, the potential of the first clock signal, and the potential of the third clock signal all jump to the second potential, enabling the control signal
  • the potential is maintained at the second potential.
  • the first transistor T1 , the fifth transistor T5 , the eighth transistor T8 and the ninth transistor T9 are all turned off, and the twelfth transistor T12 is turned on.
  • the first potential at the gate of the fifteenth transistor T15 is maintained at a higher first potential under the bootstrap action of the fourth capacitor C4, and at this time the first potential at the gate of the fifteenth transistor T15 is greater than the first potential at the gate of the fifteenth transistor T15.
  • a power signal provides the first potential, so the fourteenth transistor T14 is turned off, and the second transistor T2 is kept on.
  • the second clock signal of the first potential can be transmitted to the shift node GO through the turned-on fifteenth transistor T15, and correspondingly, the fourth transistor T4 and the first All six transistors T6 are turned on.
  • the second power signal of the second potential is transmitted to the pull-down reference node PD0 through the turned-on fourth transistor T4, and is transmitted to the first pull-down node PD1 through the turned-on sixth transistor T6.
  • the seventh transistor T7 and the third transistor T3 are turned off.
  • the third clock signal at the second potential is transmitted to the output terminal Eout through the turned-on second transistor T2.
  • the potential of the input signal and the potential of the enable control signal remain at the second potential
  • the potential of the first clock signal and the potential of the third clock signal jump to the first potential
  • the second clock signal The potential jumps to the second potential.
  • the fifth transistor T5 , the eighth transistor T8 and the ninth transistor T9 are all turned on
  • the first transistor T1 and the twelfth transistor T12 are all turned off.
  • the fourteenth transistor T14 is turned on under the control of the first power signal of the first potential.
  • the input signal of the second potential is transmitted to the second pull-down node PD2 through the turned-on ninth transistor T9, and the tenth transistor T10 is turned off.
  • the input signal of the second potential continues to be transmitted to the gate of the fifteenth transistor T15 through the turned-on fourteenth transistor T14, and both the fifteenth transistor T15 and the second transistor T2 are turned off.
  • the first power signal of the first potential is transmitted to the pull-up node PU through the turned-on eighth transistor T8, and both the thirteenth transistor T13 and the eleventh transistor T11 are turned on.
  • the second power signal of the second potential is transmitted to the shift node GO through the turned-on thirteenth transistor T13, and correspondingly, both the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the first power signal of the first potential is transmitted to the pull-down reference node PD0 through the turned-on fifth transistor T5, and correspondingly, the seventh transistor T7 is turned on.
  • the first power signal of the first potential written into the pull-down reference node PD0 continues to be transmitted to the first pull-down node PD1 through the turned-on seventh transistor T7.
  • the third transistor T3 is turned on.
  • the first power signal of the first potential is transmitted to the output terminal Eout through the turned-on third transistor T3.
  • the potential of the enabling control signal jumps to the first potential, and the potentials of the other signals are all the second potential.
  • the first transistor T1 is turned on, and the second power signal of the second potential is transmitted to the output terminal Eout through the turned-on first transistor T1 .
  • a noise reduction stage t5 may also be included between the first pull-down stage t3 and the second pull-down stage t4.
  • the potential of the input signal and the potential of the enable control signal are kept at the first potential
  • the potential of the first clock signal and the potential of the third clock signal jump to the second potential
  • the second clock signal The potential jumps to the first potential.
  • the first transistor T1 , the fifth transistor T5 , the eighth transistor T8 and the ninth transistor T9 are all turned off, and the twelfth transistor T12 is turned on.
  • the fourteenth transistor T14 is turned on under the control of the first power signal of the first potential.
  • the fourteenth transistor T14 is turned on under the control of the first power signal of the first potential.
  • the first power signal written to the pull-up node PU at the first potential becomes higher under the bootstrap action of the second capacitor C2, that is, remains at the first potential.
  • both the thirteenth transistor T13 and the eleventh transistor T11 are turned on.
  • the second power signal of the second potential is transmitted to the second pull-down node PD2 through the turned-on eleventh transistor T11 and the twelfth transistor T12 .
  • the second power signal written to the second potential of the second pull-down node PD2 continues to be transmitted to the gate of the fifteenth transistor T15 through the turned-on fourteenth transistor T14 . Both the second transistor T2 and the fifteenth transistor T15 are turned off.
  • the second power signal of the second potential is transmitted to the shift node GO through the turned-on thirteenth transistor T13 .
  • both the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the first power signal written to the first potential of the pull-down reference node PD0 in the previous stage becomes higher, that is, the potential of the pull-down reference node PD0 remains at the first potential in this stage. a potential.
  • the seventh transistor T7 is turned on.
  • the first power signal that pulls down the first potential of the reference node PD0 continues to be transmitted to the first pull-down node PD1 through the turned-on seventh transistor T7.
  • the third transistor T3 is turned on.
  • the first power signal of the first potential is transmitted to the output terminal Eout through the turned-on third transistor T3.
  • the potential Vpd0 of the pull-down reference node PD0 is generally: Vgh-Vth1.
  • the potential Vpd1 of the first pull-down node PD1 is generally: Vgh-Vth2.
  • the noise reduction stage t5 the potential Vpd0 of the pull-down reference node PD0 is pulled to Vgh ⁇ Vth1+(Vgh ⁇ Vgl) by the second clock signal.
  • the potential Vpd1 of the first pull-down node PD1 is charged to Vpd0-Vth2, which is much greater than Vgh+Vth3, and then the third transistor T3 is reliably turned on.
  • Vth1 refers to the threshold voltage of the fifth transistor T5
  • Vth2 refers to the threshold voltage of the seventh transistor T7
  • Vth3 refers to the threshold voltage of the third transistor T3.
  • Vgh refers to the potential value of the first power supply signal
  • Vgl refers to the potential value of the second power supply signal.
  • the noise reduction stage t5 can be performed in the display stage T100 of the pixel circuit.
  • the input phase t1, the output phase t2, the first pull-down phase t3, and the noise reduction phase t5 described in the above embodiments are sequentially executed in the display phase T100. That is, in the display stage T100 of the pixel circuit, the input stage t1 can be executed first, then the output stage t2 can be executed, then the first pull-down stage t3 can be executed, and finally the noise reduction stage t5 can be executed. Only the second pull-down phase t4 is performed during the blanking phase T200 of the pixel circuit.
  • the period of the second clock signal and the period of the third clock signal may be the same, and in the output stage t2, the duty cycle of the second clock signal is greater than the duty cycle of the third clock signal Compare. That is, in the output phase t2, the pulse width of the second clock signal is greater than the pulse width of the third clock signal. In other words, the duration of the second clock signal at the first potential is longer than the duration of the third clock signal at the second potential. In this way, the second transistor T2 can be turned on again after the fifteenth transistor T15 is fully turned on.
  • the third transistor T3 is effectively turned off under the control of the second potential of the first pull-down node PD1 to ensure that the first power signal of the first potential is not transmitted to the output terminal Eout through the third transistor T3, and then the third transistor T3 is controlled.
  • the third power signal with two potentials is transmitted to the output terminal Eout through the turned-on second transistor T2.
  • the first power signal of the first potential transmitted by the first power terminal VGH coupled to the third transistor T3 is effectively prevented from interfering with the output terminal Eout, further improving the output waveform of the output terminal Eout. After testing, after the waveform is improved, the falling edge of the signal output from the output terminal Eout becomes smaller.
  • the potential of the third clock signal needs to rise to the first potential.
  • the second transistor T2 is a double-gate transistor, the second transistor T2 cannot be turned on quickly enough, and the output When the terminal Eout jumps from the second potential to the first potential, a step will appear.
  • the first potential Vpd1 of the first pull-down node PD1 is generally: Vgh-Vth1-Vth2, and Vpd1 is smaller than Vgh, the third transistor T3 is not fully turned on.
  • the first power signal of the first potential cannot be transmitted to the output terminal Eout through the third transistor T3.
  • the second transistor T2 as a single-gate transistor, it is possible to effectively avoid a step when the potential of the output terminal Eout jumps from the second potential to the first potential, and improve the output waveform of the output terminal Eout.
  • FIG. 23 shows the output waveforms of the output terminal Eout before and after improvement. It can be seen from FIG. 23 that if the second transistor T2 is set as a double-gate transistor, when the output terminal Eout jumps from the second potential to the first potential, a step-like phenomenon will appear. However, if the second transistor T2 is set to be a single-gate transistor, the output terminal Eout can directly jump from the second potential to the first potential without step phenomenon.
  • the display device described in the embodiments of the present disclosure may be: any display device with a display function, such as an organic light emitting diode (OLED) display device, a mobile phone, a tablet computer, a TV set, a monitor, a notebook computer, a digital photo frame, etc. product or part.
  • OLED organic light emitting diode
  • words like “a” or “one” do not denote a limitation in quantity, but indicate that there is at least one.
  • Words such as “comprises” or “comprising” and similar terms mean that the elements or items listed before “comprising” or “comprising” include the elements or items listed after “comprising” or “comprising” and their equivalents, and do not exclude other component or object.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Abstract

提供了一种显示面板及其移位寄存器单元(00)的驱动方法、移位寄存器，属于显示技术领域。移位寄存器单元(00)中，第二移位电路(02)还与使能控制端(EN)、第二电源端(VGL)和输出端(Eout)耦接，且第二移位电路(02)可以在使能控制端(EN)的控制下，控制第二电源端(VGL)与输出端(Eout)导通，控制第二电源端(VGL)向输出端(Eout)传输第二电源信号，提高了移位寄存器单元(00)控制输出端(Eout)的电位的灵活性。

Description

显示面板及其移位寄存器单元的驱动方法、移位寄存器 技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及其移位寄存器单元的驱动方法、移位寄存器。
背景技术
移位寄存器通常包括多个级联的移位寄存器单元，每个移位寄存器单元可以向一行像素单元提供发光控制信号，由该多个级联的移位寄存器单元可以实现对显示装置中各行像素单元的逐行驱动，以显示图像。
相关技术中，移位寄存器单元包括：两个移位电路。其中，一个移位电路分别与多个信号端和移位节点耦接，用于基于各个信号端提供的信号，控制移位节点的电位。另一个移位电路分别与该多个信号端、移位节点和输出端耦接，用于基于各个信号端提供的信号和移位节点的电位，控制输出端的电位，且该输出端与一行像素单元耦接。
但是，相关技术中的移位寄存器单元控制其输出端电位的灵活性较差。
发明内容
本公开实施例提供了一种显示面板及其移位寄存器单元的驱动方法、移位寄存器。所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有显示区和围绕所述显示区的非显示区；
以及，位于所述非显示区的移位寄存器单元；
其中，所述移位寄存器单元包括：第一移位电路和第二移位电路；
所述第一移位电路分别与第一时钟端、第二时钟端、输入信号端、第一电源端、第二电源端和移位节点耦接，所述第一移位电路用于响应于所述第一时钟端提供的第一时钟信号，所述第二时钟端提供的第二时钟信号，所述输入信号端提供的输入信号，所述第一电源端提供的第一电源信号和所述第二电源端 提供的第二电源信号，控制所述移位节点的电位；
所述第二移位电路分别与所述移位节点、所述第一时钟端、所述第二时钟端、第三时钟端、使能控制端、输出控制端、所述第一电源端、所述第二电源端和输出端耦接，所述第二移位电路用于响应于所述移位节点的电位，所述第一时钟信号，所述第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端的通断，响应于所述输出控制端提供的输出控制信号，控制所述第三时钟端与所述输出端的通断，且响应于所述使能控制端提供的使能控制信号，控制所述第二电源端与所述输出端的通断。
可选的，所述第二移位电路被配置为：在所述移位寄存器单元耦接的像素电路的显示阶段，响应于第二电位的所述使能控制信号，控制所述第二电源端与所述输出端断开连接；以及，在所述移位寄存器单元耦接的像素电路的消隐阶段，响应于第一电位的所述使能控制信号，控制所述第二电源端与所述输出端导通。
可选的，所述第二移位电路包括：第一输出控制子电路、第二输出控制子电路和第一输出子电路；
所述第一输出控制子电路分别与所述移位节点、所述第一时钟端、所述第二时钟端、所述第一电源端、所述第二电源端和所述输出端耦接，所述第一输出控制子电路用于响应于所述移位节点的电位，所述第一时钟信号，所述第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端的通断；
所述第二输出控制子电路分别与所述使能控制端、所述第二电源端和所述输出端耦接，所述第二输出控制子电路用于响应于所述使能控制信号，控制所述第二电源端与所述输出端的通断；
所述第一输出子电路分别与所述输出控制端、所述第三时钟端和所述输出端耦接，所述第一输出子电路用于响应于所述输出控制信号，控制所述第三时钟端与所述输出端的通断。
可选的，所述第二输出控制子电路包括：第一晶体管；
所述第一晶体管的栅极与所述使能控制端耦接，所述第一晶体管的第一极与所述第二电源端耦接，所述第一晶体管的第二极与所述输出端耦接。
可选的，所述第一输出子电路包括：第二晶体管，且所述第二晶体管为单 栅晶体管；
所述第二晶体管的栅极与所述输出控制端耦接，所述第二晶体管的第一极与所述第三时钟端耦接，所述第二晶体管的第二极与所述输出端耦接。
可选的，所述第一输出控制子电路包括：第一降噪控制子电路、第二降噪控制子电路和降噪子电路；
所述第一降噪控制子电路分别与所述移位节点、所述第一时钟端、所述第二时钟端、所述第一电源端、所述第二电源端和下拉参考节点耦接，所述第一降噪控制子电路用于响应于所述移位节点的电位，控制所述第二电源端与所述下拉参考节点的通断，响应于所述第一时钟信号，控制所述第一电源端与所述下拉参考节点的通断，以及基于所述第二时钟信号，控制所述下拉参考节点的电位；
所述第二降噪控制子电路分别与所述移位节点、所述第一电源端、所述第二电源端、所述下拉参考节点和第一下拉节点耦接，所述第二降噪控制子电路用于响应于所述移位节点的电位，控制所述第二电源端与所述第一下拉节点的通断，响应于所述下拉参考节点的电位，控制所述下拉参考节点与所述第一下拉节点的通断，以及基于所述第一电源信号，控制所述第一下拉节点的电位；
所述降噪子电路分别与所述第一下拉节点、所述第一电源端和所述输出端耦接，所述降噪子电路用于响应于所述第一下拉节点的电位，控制所述第一电源端与所述移位节点的通断。
可选的，所述降噪子电路包括：第三晶体管，且所述第三晶体管为单栅晶体管；
所述第三晶体管的栅极与所述第一下拉节点耦接，所述第三晶体管的第一极与所述第一电源端耦接，所述第三晶体管的第二极与所述输出端耦接。
可选的，所述第一降噪控制子电路包括：第四晶体管、第五晶体管和第一电容；所述第二降噪控制子电路包括：第六晶体管、第七晶体管和第二电容；
所述第四晶体管的栅极和所述第六晶体管的栅极均与所述移位节点耦接，所述第四晶体管的第一极和所述第六晶体管的第一极均与所述第二电源端耦接，所述第四晶体管的第二极与所述下拉参考节点耦接，所述第六晶体管的第二极与所述第一下拉节点耦接；
所述第五晶体管的栅极与所述第一时钟端耦接，所述第五晶体管的第一极 与所述第一电源端耦接，所述第五晶体管的第二极与所述下拉参考节点耦接；
所述第七晶体管的栅极和第一极均与所述下拉参考节点耦接，所述第七晶体管的第二极与所述第一下拉节点耦接；
所述第一电容的一端与所述下拉参考节点耦接，所述第一电容的另一端与所述第二时钟端耦接；
所述第二电容的一端与所述第一下拉节点耦接，所述第二电容的另一端与所述第一电源端耦接。
可选的，所述第一移位电路包括：输入子电路、控制子电路和第二输出子电路；
所述输入子电路分别与所述第一时钟端、所述第一电源端、所述输入信号端、上拉节点和第二下拉节点耦接，所述输入子电路用于响应于所述第一时钟信号，控制所述第一电源端与所述上拉节点的通断，以及控制所述输入信号端与所述第二下拉节点的通断；
所述控制子电路分别与所述上拉节点、所述第二下拉节点、所述第一时钟端、所述第二时钟端和所述第二电源端耦接，所述控制子电路用于响应于所述上拉节点的电位和所述第二时钟信号，控制所述第二电源端与所述第二下拉节点的通断，以及响应于所述第二下拉节点的电位，控制所述第一时钟端与所述上拉节点的通断；
所述第二输出子电路分别与所述上拉节点、所述第二下拉节点、所述第一电源端、所述第二电源端、所述第二时钟端和所述移位节点耦接，所述第二输出子电路用于响应于所述上拉节点的电位，控制所述第二电源端与所述移位节点的通断，以及响应于所述第二下拉节点的电位和所述第一电源信号，控制所述第二时钟端与所述移位节点的通断。
可选的，所述输入子电路包括：第八晶体管和第九晶体管；所述控制子电路包括：第十晶体管、第十一晶体管和第十二晶体管；所述第二输出子电路包括：第十三晶体管、第十四晶体管、第十五晶体管、第三电容和第四电容；
所述第八晶体管的栅极和所述第九晶体管的栅极均与所述第一时钟端耦接，所述第八晶体管的第一极与所述第一电源端耦接，所述第八晶体管的第二极与所述上拉节点耦接，所述第九晶体管的第一极与所述输入信号端耦接，所述第九晶体管的第二极与所述第二下拉节点耦接；
所述第十晶体管的栅极与所述第二下拉节点耦接，所述第十晶体管的第一极与所述第一时钟端耦接，所述第十晶体管的第二极与所述上拉节点耦接；
所述第十一晶体管的栅极与所述上拉节点耦接，所述第十一晶体管的第一极与所述第二电源端耦接，所述第十一晶体管的第二极与所述第十二晶体管的第一极耦接，所述第十二晶体管的栅极与所述第二时钟端耦接，所述第十二晶体管的第二极与所述第二下拉节点耦接；
所述第十三晶体管的栅极与所述上拉节点耦接，所述第十三晶体管的第一极与所述第二电源端耦接，所述第十三晶体管的第二极与所述移位节点耦接；
所述第十四晶体管的栅极与所述第一电源端耦接，所述第十四晶体管的第一极与所述第二下拉节点耦接，所述第十四晶体管的第二极与所述第十五晶体管的栅极耦接，所述第十五晶体管的第一极与所述第二时钟端耦接，所述第十五晶体管的第二极与所述移位节点耦接；
所述第三电容的一端与所述上拉节点耦接，所述第三电容的另一端与所述第二电源端耦接；
所述第四电容的一端与所述第十五晶体管的栅极耦接，所述第四电容的另一端与所述移位节点耦接。
可选的，所述输出控制端与所述第十五晶体管的栅极耦接。
可选的，所述移位寄存器单元包括的晶体管均为N型晶体管。
可选的，所述移位寄存器单元包括：位于所述衬底基板一侧的半导体层，第一导电层、第二导电层和第三导电层；
所述半导体层至少包括：所述移位寄存器单元中至少一个晶体管的沟道区、源极区和漏极区；
所述第一导电层至少包括：所述移位寄存器单元中至少一个晶体管的栅极和至少一个电容的第一电容电极，且所述至少一个晶体管的栅极与沟道区交叠；
所述第二导电层至少包括：所述移位寄存器单元中至少一个电容的第二电容电极，且所述至少一个电容的第二电容电极与第一电容电极交叠；
所述第三导电层至少包括：多条信号线，以及所述移位寄存器单元中至少一个晶体管的源极和漏极，且所述至少一个晶体管的源极与源极区耦接，所述至少一个晶体管的漏极与漏极区耦接，所述多条信号线分别与所述移位寄存器单元耦接的各个信号端耦接。
可选的，所述多条信号线包括：沿第一方向依次间隔排布的第一组信号线、第二组信号线和第三组信号线；
所述第一组信号线包括：耦接所述第一电源端的第一电源线；
所述第二组信号线包括：耦接所述使能控制端的使能控制线，
所述第三组信号线包括：所述第一电源线；
其中，所述第一组信号线，所述移位寄存器单元中的第一组晶体管，所述移位寄存器单元中的第一组电容，所述第二组信号线，所述移位寄存器单元中的第二组晶体管，所述移位寄存器单元中的第二组电容，以及所述第三组信号线沿所述第一方向依次排布；且所述多条信号线中至少一条信号线沿第二方向延伸，所述第一方向为从所述非显示区指向所述显示区的方向，所述第二方向与所述第一方向相交。
可选的，所述第一组信号线还包括：耦接所述输入信号端的输入信号线，耦接所述第一时钟端的第一时钟信号线，以及耦接所述第二时钟端的第二时钟信号线；
所述第二组信号线还包括：耦接所述第二电源端的第二电源线，所述第一时钟信号线和所述第二时钟信号线；
所述第三组信号线还包括：耦接所述第三时钟端的第三时钟信号线；
且，沿所述第一方向，所述第一组信号线中的输入信号线、第一时钟信号线、第二时钟信号线和第一电源线依次排布，所述第二组信号线中的第二电源线、使能控制线、第二时钟信号线和第一时钟信号线依次排布；所述第三组信号线中的第一电源线和第三时钟信号线依次排布。
可选的，所述第一组晶体管包括：所述移位寄存器单元中的第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管和第十五晶体管；
所述第一组电容包括：所述移位寄存器单元中的第三电容和第四电容；
所述第二组晶体管包括：所述移位寄存器单元中的第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第七晶体管；
所述第二组电容包括：所述移位寄存器单元中的第一电容和第二电容。
可选的，所述第四电容位于所述第十晶体管和所述第十三晶体管之间，且所述第十晶体管、所述第四电容和所述第十三晶体管沿靠近所述第二组信号线 的方向依次排布；
所述第十五晶体管、所述第九晶体管、所述第六晶体管和所述第三电容沿靠近所述第二组信号线的方向依次排布；
所述第十一晶体管位于所述第十五晶体管和所述第十晶体管之间，且相对于所述第十五晶体管远离所述第一组信号线；
所述第十二晶体管和所述第八晶体管位于所述第九晶体管与所述第四电容之间，且沿靠近所述第二组信号线的方向依次排布，且均相对于所述第十一晶体管靠近所述第十晶体管。
可选的，所述第四晶体管位于所述第一电容与所述第二电容之间，且所述第一电容、所述第四晶体管和所述第二电容沿靠近所述第三组信号线的方向依次排布；
所述第五晶体管、所述第一晶体管和所述第一电容沿所述第二方向依次排布；所述第七晶体管和所述第十四晶体管位于所述第五晶体管和所述第一晶体管之间，且沿靠近所述第三组信号线的方向依次排布；
所述第二晶体管和所述第三晶体管沿所述第二方向依次排布，且位于所述第十四晶体管远离所述第二组信号线的一侧，且所述第二晶体管相对于所述第三晶体管远离所述第四晶体管。
可选的，所述第五晶体管的半导体层、所述第七晶体管的半导体层和所述第十四晶体管的半导体层为一体结构；
且，所述第二晶体管的半导体层与所述第三晶体管的半导体层为一体结构。
可选的，所述第十五晶体管的栅极和所述第九晶体管的栅极为一体结构；
所述第三电容的第一电容电极、所述第八晶体管的栅极和所述第二晶体管的栅极为一体结构；
所述第七晶体管的栅极和所述第十四晶体管的栅极为一体结构；
所述第三晶体管的栅极和所述第二电容的第一电容电极为一体结构；
所述第四晶体管的栅极和所述第一电容的第一电容电极为一体结构；
且，所述第十晶体管的栅极与所述第四电容的第一电容电极为一体结构。
可选的，所述移位寄存器单元中，所述第二晶体管的栅极和/或所述第三晶体管的栅极在所述衬底基板上的正投影呈条形，且沿所述第一方向延伸；且，除栅极呈条形的晶体管外的其余晶体管的栅极在所述衬底基板上的正投影均呈 U型。
另一方面，提供了一种显示面板中移位寄存器单元的驱动方法，应用于如上述方面所述的移位寄存器单元中，所述方法包括：
输入阶段，第一移位电路响应于第一电位的第一时钟信号，第二电位的第二时钟信号，第一电位的输入信号，第一电位的第一电源信号和第二电位的第二电源信号，控制移位节点的电位为第二电位；第二移位电路响应于所述移位节点的第二电位，所述第一电位的第一时钟信号，所述第二电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端导通，响应于第一电位的输出控制信号控制第三时钟端与所述输出端导通，以及响应于第二电位的使能控制信号控制所述第二电源端与所述输出端断开连接，所述第三时钟端提供的第三时钟信号的电位为第一电位；
输出阶段，所述第一移位电路响应于第二电位的第一时钟信号，第一电位的第二时钟信号，第二电位的输入信号，所述第一电源信号和所述第二电源信号，控制所述移位节点的电位为第一电位；所述第二移位电路响应于所述移位节点的第一电位，所述第二电位的第一时钟信号，所述第一电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端断开连接，响应于第一电位的输出控制信号，控制所述第三时钟端与所述输出端导通，以及响应于第二电位的使能控制信号，控制所述第二电源端与所述输出端断开连接，所述第三时钟信号的电位为第二电位；
第一下拉阶段，所述第一移位电路响应于第一电位的第一时钟信号，第二电位的第二时钟信号，第二电位的输入信号，所述第一电源信号和所述第二电源信号，控制所述移位节点的电位为第二电位；所述第二移位电路响应于所述移位节点的第二电位，所述第一电位的第一时钟信号，所述第二电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端导通，响应于第二电位的输出控制信号，控制所述第三时钟端与所述输出端断开连接，以及响应于第二电位的使能控制信号，控制所述第二电源端与所述输出端断开连接，所述第三时钟信号的电位为第一电位；
其中，所述输入阶段，所述输出阶段和所述第一下拉阶段在所述移位寄存器单元耦接的像素电路的显示阶段执行。
可选的，在所述第一下拉阶段之后，所述方法还包括：
第二下拉阶段，所述第一移位电路响应于第二电位的第一时钟信号，第二电位的第二时钟信号，第一电位的输入信号，所述第一电源信号和所述第二电源信号，控制所述移位节点的电位为第二电位；所述第二移位电路响应于所述移位节点的第二电位，所述第二电位的第一时钟信号，所述第二电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端断开连接，响应于第二电位的输出控制信号，控制所述第三时钟端与所述输出端断开连接，以及响应于第一电位的使能控制信号，控制所述第二电源端与所述输出端导通，所述第三时钟信号的电位为第二电位；
其中，所述第二下拉阶段在所述像素电路的消隐阶段执行。
可选的，所述第二时钟信号的周期与所述第三时钟信号的周期相同，且在所述输出阶段，所述第二时钟信号的占空比大于所述第三时钟信号的占空比。
又一方面，提供了一种移位寄存器，所述移位寄存器包括：至少两个级联的移位寄存器单元；所述移位寄存器单元包括如上述方面所述的显示面板中的移位寄存器单元；
其中，每级所述移位寄存器单元的移位节点与级联的下一级所述移位寄存器单元的所述输入信号端耦接，且每级所述移位寄存器单元的输出端与目标信号线耦接，所述目标信号线为所述显示面板中像素电路所耦接的发光控制线。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示面板的结构示意图；
图2是本公开实施例提供的一种移位寄存器单元的结构示意图；
图3是本公开实施例提供的一种第二移位电路的结构示意图；
图4是本公开实施例提供的另一种第二移位电路的结构示意图；
图5是本公开实施例提供的又一种第二移位电路的结构示意图；
图6是本公开实施例提供的一种第一移位电路的结构示意图；
图7是本公开实施例提供的另一种第一移位电路的结构示意图；
图8是本公开实施例提供的另一种移位寄存器单元的结构示意图；
图9是本公开实施例提供的一种移位寄存器单元的结构版图；
图10是本公开实施例提供的一种移位寄存器单元包括的有源层的结构版图；
图11是本公开实施例提供的一种移位寄存器单元包括的第一导电层的结构版图；
图12是本公开实施例提供的一种移位寄存器单元包括的第二导电层的结构版图；
图13是本公开实施例提供的一种移位寄存器单元包括的第三导电层的结构版图；
图14是本公开实施例提供的一种移位寄存器单元包括的层间介定层的结构版图；
图15是本公开实施例提供的一种移位寄存器的结构示意图；
图16是本公开实施例提供的一种显示装置的结构示意图；
图17是本公开实施例提供的一种像素电路的结构示意图；
图18是本公开实施例提供的另一种像素电路的结构示意图；
图19是本公开实施例提供的一种像素电路耦接的各信号端的时序图；
图20是本公开实施例提供的一种移位寄存器单元的驱动方法流程图；
图21是本公开实施例提供的另一种移位寄存器单元的驱动方法流程图；
图22是本公开实施例提供的一种移位寄存器单元耦接的信号端的时序图；
图23是本公开实施例提供的一种移位寄存器单元的输出端的改善前后波形对比图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极，或者， 将其中漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有有效电位和无效电位，有效电位和无效电位仅代表该信号的电位有2个状态量，不代表全文中有效电位或无效电位具有特定的数值。
图1是本公开实施例提供的一种显示面板的结构示意图。如图1所示，该显示面板包括：具有显示区A0和非显示区B0的衬底基板10，以及位于非显示区B0的移位寄存器单元00。
其中，该显示区A0和围绕该显示区A0的非显示区B0。即，该显示区A0被非显示区B0包围。当然，在一些实施例中，非显示区B0可以仅部分围绕显示区A0。如，结合图1，显示区A0的四条边中仅三条边被非显示区B0包围。
图2是本公开实施例提供的一种移位寄存器单元的结构示意图。如图2所示，该移位寄存器单元00包括：第一移位电路01和第二移位电路02。
其中，第一移位电路01分别与第一时钟端CK、第二时钟端CB、输入信号端IN、第一电源端VGH、第二电源端VGL和移位节点GO耦接。该第一移位电路01用于响应于第一时钟端CK提供的第一时钟信号，第二时钟端CB提供的第二时钟信号，输入信号端IN提供的输入信号，第一电源端VGH提供的第一电源信号和第二电源端VGL提供的第二电源信号，控制移位节点GO的电位。
可选的，第一电源端VGH和第二电源端VGL可以为直流电源端，且第一电源信号的电位可以为第一电位，第二电源信号的电位可以为第二电位。第一电位可以为有效电位，第二电位可以为无效电位，且第一电位相对于第二电位可以为高电位。即，第一电位可以大于第二电位。
在此基础上，示例的，第一移位电路01可以在第一时钟信号的电位和输入信号的电位均为第一电位，且第二时钟信号的电位为第二电位时，控制移位节点GO的电位为第二电位。以及，该第一移位电路01可以在第一时钟信号的电位和输入信号的电位均为第二电位，且第二时钟信号的电位为第一电位时，控制移位节点GO的电位为第一电位。
第二移位电路02分别与移位节点GO、第一时钟端CK、第二时钟端CB、第三时钟端CBO、使能控制端EN、输出控制端CN_O、第一电源端VGH、第二电源端VGL和输出端Eout耦接。该第二移位电路02用于响应于移位节点GO的电位，第一时钟信号，第二时钟信号，第一电源信号和第二电源信号，控制第一电源端VGH与输出端Eout的通断，响应于输出控制端CN_O提供的输出控制信号，控制第三时钟端CBO与输出端Eout的通断，且响应于使能控制端EN提供的使能控制信号，控制第二电源端VGL与输出端Eout的通断。
例如，该第二移位电路02可以在移位节点GO的电位和第一时钟信号的电位均为第二电位，且第二时钟信号的电位为第一电位时，控制第一电源端VGH与输出端Eout导通。此时，第一电源端VGH可以向输出端Eout传输第一电位的第一电源信号。以及，该第二移位电路02可以在移位节点GO的电位和第二时钟信号的电位均为第一电位，且第一时钟信号的电位为第二电位时，控制第一电源端VGH与输出端Eout断开连接。
又例如，该第二移位电路02还可以在输出控制信号的电位为第一电位时，控制第三时钟端CBO与输出端Eout导通。此时，第三时钟端CBO可以向输出端Eout传输第三时钟信号。以及，该第二移位电路02还可以在输出控制信号的电位为第二电位时，控制第三时钟端CBO与输出端Eout断开连接。
再例如，该第二移位电路02还可以在使能控制信号的电位为第一电位时，控制第二电源端VGL与输出端Eout导通。此时，第二电源端VGL可以向输出端Eout传输第二电位的第二电源信号。以及，该第二移位电路02还可以在使能控制信号的电位为第二电位时，控制第二电源端VGL与输出端Eout断开连接。
综上所述，本公开实施例提供了一种显示面板，该显示面板中的移位寄存器单元包括第一移位电路和第二移位电路，且第二移位电路分别与使能控制端、第二电源端和输出端耦接，第二移位电路可以在使能控制端的控制下，控制第二电源端与输出端导通，即控制第二电源端向输出端提供第二电源信号。如此，相对于相关技术而言，提高了移位寄存器单元控制其输出端的电位的灵活性。
结合上述对第二移位电路02的工作原理论述可知，本公开实施例提供的第二移位电路02可以被配置为：在移位寄存器单元耦接的像素电路的显示阶段，响应于第二电位的使能控制信号，控制第二电源端VGL与输出端Eout断开连 接，此时，第二电源端VGL无法向输出端Eout提供第二电位的第二电源信号。以及，在移位寄存器单元耦接的像素电路的消隐阶段，响应于第一电位的使能控制信号，控制第二电源端VGL与输出端Eout导通，此时，第二电源端VGL可以向输出端Eout传输第二电位的第二电源信号。即，可以通过在显示阶段，控制使能控制端EN提供第二电位的使能控制信号；以及在消隐阶段，控制使能控制端EN提供第一电位的使能控制信号，以实现对输出端Eout的电位的灵活控制，确保在消隐阶段，向输出端Eout可靠提供第二电位的信号。
图3是本公开实施例提供的一种第二移位电路的结构示意图。如图3所示，该第二移位电路02可以包括：第一输出控制子电路021、第二输出控制子电路022和第一输出子电路023。
其中，第一输出控制子电路021可以分别与移位节点GO、第一时钟端CK、第二时钟端CB、第一电源端VGH、第二电源端VGL和输出端Eout耦接。该第一输出控制子电路021可以用于响应于移位节点GO的电位，第一时钟信号，第二时钟信号，第一电源信号和第二电源信号，控制第一电源端VGH与输出端Eout的通断。
例如，该第一输出控制子电路021可以在移位节点GO的电位和第一时钟信号的电位均为第二电位，且第二时钟信号的电位为第一电位时，控制第一电源端VGH与输出端Eout导通。以及，该第一输出控制子电路021可以在移位节点GO的电位和第二时钟信号的电位均为第一电位，且第一时钟信号的电位为第二电位时，控制第一电源端VGH与输出端Eout断开连接。
第二输出控制子电路022可以分别与使能控制端EN、第二电源端VGL和输出端Eout耦接。该第二输出控制子电路022可以用于响应于使能控制信号，控制第二电源端VGL与输出端Eout的通断。
例如，该第二输出控制子电路022可以在使能控制信号的电位为第一电位时，控制第二电源端VGL与输出端Eout导通。以及，该第一输出控制子电路021可以在使能控制信号的电位为第二电位时，控制第二电源端VGL与输出端Eout断开连接。
第一输出子电路023可以分别与输出控制端CN_O、第三时钟端CBO和输出端Eout耦接。第一输出子电路023可以用于响应于输出控制信号，控制第三时钟端CBO与输出端Eout的通断。
例如，该第一输出子电路023可以在输出控制信号的电位为第一电位时，控制第三时钟端CBO与输出端Eout导通。以及，该第一输出子电路023可以在输出控制信号的电位为第二电位时，控制第三时钟端CBO与输出端Eout断开连接。
图4是本公开实施例提供的另一种第二移位电路的结构示意图。如图4所示，该第一输出控制子电路021可以包括：第一降噪控制子电路0211、第二降噪控制子电路0212和降噪子电路0213。
其中，该第一降噪控制子电路0211可以分别与移位节点GO、第一时钟端CK、第二时钟端CB、第一电源端VGH、第二电源端VGL和下拉参考节点PD0耦接。该第一降噪控制子电路0211可以用于响应于移位节点GO的电位，控制第二电源端VGL与下拉参考节点PD0的通断，可以响应于第一时钟信号，控制第一电源端VGH与下拉参考节点PD0的通断，以及可以基于第二时钟信号，控制下拉参考节点PD0的电位。
例如，该第一降噪控制子电路0211可以在移位节点GO的电位为第一电位时，控制第二电源端VGL与下拉参考节点PD0导通，此时，第二电源端VGL可以向下拉参考节点PD0传输第二电位的第二电源信号。且该第一降噪控制子电路0211可以在移位节点GO的电位为第二电位时，控制第二电源端VGL与下拉参考节点PD0断开连接。
以及，该第一降噪控制子电路0211可以在第一时钟信号的电位为第一电位时，控制第一电源端VGH与下拉参考节点PD0导通，此时，第一电源端VGH可以向下拉参考节点PD0传输第一电位的第一电源信号。且该第一降噪控制子电路0211可以在第一时钟信号的电位为第二电位时，控制第一电源端VGH与下拉参考节点PD0断开连接。
该第二降噪控制子电路0212可以分别与移位节点GO、第一电源端VGH、第二电源端VGL、下拉参考节点PD0和第一下拉节点PD1耦接。该第二降噪控制子电路0212可以用于响应于移位节点GO的电位，控制第二电源端VGL与第一下拉节点PD1的通断，用于响应于下拉参考节点PD0的电位，控制下拉参考节点PD0与第一下拉节点PD1的通断，以及用于基于第一电源信号，控制第一下拉节点PD1的电位。
例如，该第二降噪控制子电路0212可以在移位节点GO的电位为第一电位 时，控制第二电源端VGL与下拉参考节点PD0导通，此时，第二电源端VGL可以向下拉参考节点PD0传输第二电位的第二电源信号。且该第二降噪控制子电路0212可以在移位节点GO的电位为第二电位时，控制第二电源端VGL与下拉参考节点PD0断开连接。
以及，该第二降噪控制子电路0212可以在下拉参考节点PD0的电位为第一电位时，控制下拉参考节点PD0与第一下拉节点PD1导通，此时，下拉参考节点PD0的电位可以传输至第一下拉节点PD1。且该第二降噪控制子电路0212可以在下拉参考节点PD0的电位为第二电位时，控制下拉参考节点PD0与第一下拉节点PD1断开连接。
该降噪子电路0213可以分别与第一下拉节点PD1、第一电源端VGH和输出端Eout耦接。该降噪子电路0213可以用于响应于第一下拉节点PD1的电位，控制第一电源端VGH与移位节点GO的通断。
例如，该降噪子电路0213可以在第一下拉节点PD1的电位为第一电位时，控制第一电源端VGH与移位节点GO导通，此时，第一电源端VGH可以向移位节点GO传输第一电位的第一电源信号。
以及，该降噪子电路0213可以在第一下拉节点PD1的电位为第二电位时，控制第一电源端VGH与移位节点GO断开连接。
图5是本公开实施例提供的又一种第二移位电路的结构示意图。如图5所示，第二移位电路02中，第二输出控制子电路022可以包括：第一晶体管T1。第一输出子电路023可以包括：第二晶体管T2。第一输出控制子电路021中，降噪子电路0213可以包括：第三晶体管T3。第一降噪控制子电路0211可以包括：第四晶体管T4、第五晶体管T5和第一电容C1。第二降噪控制子电路0212可以包括：第六晶体管T6、第七晶体管T7和第二电容C2。
其中，第一晶体管T1的栅极可以与使能控制端EN耦接，第一晶体管T1的第一极可以与第二电源端VGL耦接，第一晶体管T1的第二极可以与输出端Eout耦接。
第二晶体管T2的栅极可以与输出控制端CN_O耦接，第二晶体管T2的第一极可以与第三时钟端CBO耦接，第二晶体管T2的第二极可以与输出端Eout耦接。
第三晶体管T3的栅极可以与第一下拉节点PD1耦接，第三晶体管T3的第 一极可以与第一电源端VGH耦接，第三晶体管T3的第二极可以与输出端Eout耦接。
第四晶体管T4的栅极和第六晶体管T6的栅极可以均与移位节点GO耦接，第四晶体管T4的第一极和第六晶体管T6的第一极可以均与第二电源端VGL耦接，第四晶体管T4的第二极可以与下拉参考节点PD0耦接，第六晶体管T6的第二极可以与第一下拉节点PD1耦接。
第五晶体管T5的栅极可以与第一时钟端CK耦接，第五晶体管T5的第一极可以与第一电源端VGH耦接，第五晶体管T5的第二极可以与下拉参考节点PD0耦接。
第七晶体管T7的栅极和第一极可以均与下拉参考节点PD0耦接，第七晶体管T7的第二极可以与第一下拉节点PD1耦接。
第一电容C1的一端可以与下拉参考节点PD0耦接，第一电容C1的另一端可以与第二时钟端CB耦接。
第二电容C2的一端可以与第一下拉节点PD1耦接，第二电容C2的另一端可以与第一电源端VGH耦接。
可选的，第二晶体管T2和/或第三晶体管T3可以为单栅晶体管。除此之外，移位寄存器单元包括的其他晶体管可以均为双栅晶体管。
经测试，若第二晶体管T2为双栅晶体管，则第二晶体管T2的栅极和漏极之间的电容值则会较大，相应的，第二晶体管T2开启则较慢且开启不充分。如此，导致第一电位的第三时钟信号无法快速且完整的一次性传输至输出端Eout，输出端Eout的第一电位出现台阶现象。故通过将第二晶体管T2设置为单栅晶体管，可以有效减小第二晶体管T2的栅极和漏极之间的电容值，相应的，可以使得第二晶体管T2能够在合适的时机快速且充分开启，避免经第二晶体管T2传输至输出端Eout的第一电位出现台阶现象。由此改善了输出端Eout的输出不良问题。第三晶体管T3设置为双栅晶体管的有益效果同理，在此不再赘述。
可选的，在本公开实施例中，移位寄存器单元的输出端Eout可以与发光控制线耦接。其中，发光控制线一般与像素电路耦接，在像素电路驱动所耦接的发光元件发光时的发光阶段，发光控制线需要提供第一电位的发光控制信号，以使得像素电路向发光元件可靠传输驱动电流，以驱动发光元件发光。除发光阶段之外的其他阶段，发光控制线需要提供第二电位的发光控制信号。即，在 发光阶段，移位寄存器单元的输出端Eout需要传输第一电位的信号至发光控制线，除发光阶段之外的其他阶段，移位寄存器单元的输出端Eout需要传输第二电位的信号至发光控制线。
基于此可知，通过设置第二移位电路02还包括第二输出控制子电路022(即，第一晶体管T1)，且设置该第二输出控制子电路022响应于使能控制信号，向输出端Eout直接传输第二电位的第二电源信号，可以在灵活设置使能控制信号的电位的基础上，可靠确保在除发光阶段之外的其他阶段，输出端Eout能够持续向发光控制线传输第二电位的信号。即确保输出端Eout的电位保持稳定的低电平。
图6是本公开实施例提供的一种第一移位电路的结构示意图。如图6所示，第一移位电路01可以包括：输入子电路011、控制子电路012和第二输出子电路013。
其中，该输入子电路011可以分别与第一时钟端CK、第一电源端VGH、输入信号端IN、上拉节点PU和第二下拉节点PD2耦接。该输入子电路011可以用于响应于第一时钟信号，控制第一电源端VGH与上拉节点PU的通断，以及控制输入信号端IN与第二下拉节点PD2的通断。
例如，该输入子电路011可以在第一时钟信号的电位为第一电位时，控制第一电源端VGH与上拉节点PU导通，且控制输入信号端IN与第二下拉节点PD2导通。此时，第一电源端VGH可以向上拉节点PU传输第一电位的第一电源信号，且输入信号端IN可以向第二下拉节点PD2传输输入信号。
以及，该输入子电路011可以在第一时钟信号的电位为第二电位时，控制第一电源端VGH与上拉节点PU断开连接，且控制输入信号端IN与第二下拉节点PD2断开连接。
该控制子电路012可以分别与上拉节点PU、第二下拉节点PD2、第一时钟端CK、第二时钟端CB和第二电源端VGL耦接。该控制子电路012可以用于响应于上拉节点PU的电位和第二时钟信号，控制第二电源端VGL与第二下拉节点PD2的通断，以及可以响应于第二下拉节点PD2的电位，控制第一时钟端CK与上拉节点PU的通断。
例如，该控制子电路012可以在上拉节点PU的电位和第二时钟信号的电位均为第一电位时，控制第二电源端VGL与第二下拉节点PD2导通，此时，第二 电源端VGL可以向第二下拉节点PD2传输第二电位的第二电源信号。且该控制子电路012可以在上拉节点PU的电位和/或第二时钟信号的电位为第二电位时，控制第二电源端VGL与第二下拉节点PD2断开连接。
以及，该控制子电路012可以在第二下拉节点PD2的电位为第一电位时，控制第一时钟端CK与上拉节点PU导通，此时，第一时钟端CK可以向上拉节点PU传输第一时钟信号。且该控制子电路012可以在第二下拉节点PD2的电位为第二电位时，控制第一时钟端CK与上拉节点PU断开连接。
该第二输出子电路013可以分别与上拉节点PU、第二下拉节点PD2、第一电源端VGH、第二电源端VGL、第二时钟端CB和移位节点GO耦接。该第二输出子电路013可以用于响应于上拉节点PU的电位，控制第二电源端VGL与移位节点GO的通断，以及可以响应于第二下拉节点PD2的电位和第一电源信号，控制第二时钟端CB与移位节点GO的通断。
例如，该第二输出子电路013可以在上拉节点PU的电位为第一电位时，控制第二电源端VGL与移位节点GO导通。此时，第二电源端VGL可以向移位节点GO传输第二电位的第二电源信号。且该第二输出子电路013可以在上拉节点PU的电位为第二电位时，控制第二电源端VGL与移位节点GO断开连接。
以及，该第二输出子电路013可以在第二下拉节点PD2的电位为第一电位时，响应于该第二下拉节点PD2的电位和第一电位的第一电源信号，控制第二时钟端CB与移位节点GO导通。此时，第二时钟端CB可以向移位节点GO传输第二时钟信号。且该第二输出子电路013可以在第二下拉节点PD2的电位为第二电位时，响应于该第二下拉节点PD2的电位和第一电位的第一电源信号，控制第二时钟端CB与移位节点GO断开连接。
图7是本公开实施例提供的另一种第一移位电路的结构示意图。如图7所示，第一移位电路01中，输入子电路011可以包括：第八晶体管T8和第九晶体管T9。控制子电路012可以包括：第十晶体管T10、第十一晶体管T11和第十二晶体管T12。第二输出子电路013可以包括：第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第三电容C3和第四电容C4。
其中，第八晶体管T8的栅极和第九晶体管T9的栅极可以均与第一时钟端CK耦接，第八晶体管T8的第一极可以与第一电源端VGH耦接，第八晶体管T8的第二极可以与上拉节点PU耦接，第九晶体管T9的第一极可以与输入信号 端IN耦接，第九晶体管T9的第二极可以与第二下拉节点PD2耦接。
第十晶体管T10的栅极可以与第二下拉节点PD2耦接，第十晶体管T10的第一极可以与第一时钟端CK耦接，第十晶体管T10的第二极可以与上拉节点PU耦接。
第十一晶体管T11的栅极可以与上拉节点PU耦接，第十一晶体管T11的第一极可以与第二电源端VGL耦接，第十一晶体管T11的第二极可以与第十二晶体管T12的第一极耦接，第十二晶体管T12的栅极可以与第二时钟端CB耦接，第十二晶体管T12的第二极可以与第二下拉节点PD2耦接。
第十三晶体管T13的栅极可以与上拉节点PU耦接，第十三晶体管T13的第一极可以与第二电源端VGL耦接，第十三晶体管T13的第二极可以与移位节点GO耦接。
第十四晶体管T14的栅极可以与第一电源端VGH耦接，第十四晶体管T14的第一极可以与第二下拉节点PD2耦接，第十四晶体管T14的第二极可以与第十五晶体管T15的栅极耦接，第十五晶体管T15的第一极可以与第二时钟端CB耦接，第十五晶体管T15的第二极可以与移位节点GO耦接。
第三电容C3的一端可以与上拉节点PU耦接，第三电容C3的另一端可以与第二电源端VGL耦接。
第四电容C4的一端可以与第十五晶体管T15的栅极耦接，第四电容C4的另一端可以与移位节点GO耦接。
可选的，结合图5和7，图8示出了本公开实施例提供的另一种移位寄存器单元的整体结构示意图。参考图8可以看出，第一输出子电路023(即，第二晶体管T2)所耦接的输出控制端CN_O可以与第十五晶体管T15的栅极耦接。即，输出控制端CN_O提供的输出控制信号的电位可以与第十五晶体管T15的栅极处的电位相同。如此，可以简化所需设置的信号端的数量，节省成本。
可选的，本公开实施例记载的移位寄存器单元包括的晶体管可以均为N型晶体管。当然，在一些实施例中，各个晶体管还可以均为P型晶体管，若为P型晶体管，则第一电位相对于第二电位可以为低电位。
可选的，以图8所示结构，且第二晶体管T2为单栅晶体管为例，图9示出了一种移位寄存器单元的结构版图，图10至图14分别示出了图9所示结构版图中的不同层版图。参考图9至图14可以看出，移位寄存器单元可以包括：位 于衬底基板一侧的半导体层，第一导电层、第二导电层和第三导电层。
其中，半导体层至少包括：移位寄存器单元中至少一个晶体管的沟道区、源极区和漏极区。例如，参考图10可以看出，半导体层至少包括：第一晶体管T1的沟道区a11、源极区a21和漏极区a31。第二晶体管T2的沟道区a12、源极区a22和漏极区a32。第三晶体管T3的沟道区a13、源极区a23和漏极区a33。第四晶体管T4的沟道区a14、源极区a24和漏极区a34。第五晶体管T5的沟道区a15、源极区a25和漏极区a35。第六晶体管T2的沟道区a16、源极区a26和漏极区a36。第七晶体管T7的沟道区a17、源极区a27和漏极区a37。第八晶体管T8的沟道区a18、源极区a28和漏极区a38。第九晶体管T9的沟道区a19、源极区a29和漏极区a39。第十晶体管T10的沟道区a110、源极区a210和漏极区a310。第十一晶体管T11的沟道区a111、源极区a211和漏极区a311。第十三晶体管T13的沟道区a113、源极区a213和漏极区a313。第十四晶体管T2的沟道区a114、源极区a214和漏极区a314。
第一导电层至少可以包括：移位寄存器单元中至少一个晶体管的栅极和至少一个电容的第一电容电极，且至少一个晶体管的栅极与沟道区交叠。
例如，参考图11可以看出，第一导电层至少包括：第一晶体管T1的栅极b1，第二晶体管T2的栅极b2，第三晶体管T3的栅极b3，第四晶体管T4的栅极b4，第五晶体管T5的栅极b5，第六晶体管T6的栅极b6，第七晶体管T7的栅极b7，第八晶体管T8的栅极b8，第九晶体管T9的栅极b9，第十晶体管T10的栅极b10，第十一晶体管T11的栅极b11，第十二晶体管T12的栅极b12，第十三晶体管T13的栅极b13，第十四晶体管T14的栅极b14，第一电容C1的第一电容电极c10，第二电容C2的第一电容电极c20，第三电容C3的第一电容电极c30，以及第四电容C4的第一电容电极c40。且，结合图9和图10可以看出，每个晶体管的栅极均与其沟道区交叠。
第二导电层至少可以包括：移位寄存器单元中至少一个电容的第二电容电极，且至少一个电容的第二电容电极与第一电容电极交叠。
例如，参考图12可以看出，第二导电层至少包括：第一电容C1的第二电容电极c11，第二电容C2的第二电容电极c21，第三电容C3的第二电容电极c31，以及第四电容C4的第二电容电极c41。且结合图9和图11可以看出，每个电容的第一电容电极均与其第二电容电极交叠。如，第一电容C1的第一电容电极c10 与第二电容电极c11交叠。
第三导电层至少可以包括：多条信号线，以及移位寄存器单元中至少一个晶体管的源极和漏极，且至少一个晶体管的源极与源极区耦接，至少一个晶体管的漏极与漏极区耦接，多条信号线分别与移位寄存器单元耦接的各个信号端耦接。
例如，参考图13可以看出，第三导电层包括：第一电源线vgh1。输入信号线in1，第一时钟信号线ck1，第二时钟信号线cb1，使能控制线en1，第二电源线vgl2，以及第三时钟信号线cbo1。以及第一晶体管T1至第十四晶体管T14中每个晶体管的源极和漏极(图13中未标识)。且结合图9和图10可以看出，每个晶体管的源极均与其源极区耦接，漏极均与其漏极区耦接，且多条信号线分别与移位寄存器单元耦接的各个信号端耦接。如，第一电源线vgh1与第一电源端VGH耦接，输入信号线in1与输入信号端IN耦接，第一时钟信号线ck1与第一时钟端CK耦接，第二时钟信号线cb1与第二时钟端CB耦接，使能控制线en1与使能控制端EN耦接，第二电源线vgl2与第二电源端VGL耦接，且第三时钟信号线cbo1与第三时钟端CBO耦接。
此外，结合图9和图14还可以看出，本公开实施例提供的移位寄存器单元还包括：用于形成过孔的层间介定层。该过孔用于暴露依次层叠且需要耦接的各层导电层，以便导电层之间相互耦接。
结合图9和图13所示结构可知，本公开实施例提供的多条信号线可以包括：沿第一方向X1依次间隔排布的第一组信号线L01、第二组信号线L02和第三组信号线L03。
其中，第一组信号线L01可以包括：耦接第一电源端VGH的第一电源线vgh1，耦接输入信号端IN的输入信号线in1，耦接第一时钟端CK的第一时钟信号线ck1，以及耦接第二时钟端CB的第二时钟信号线cb1。第二组信号线L02可以包括：耦接使能控制端EN的使能控制线en1，耦接第二电源端VGL的第二电源线vgl2，第一时钟信号线ck1和第二时钟信号线cb1。第三组信号线L03可以包括：第一电源线vgh1，以及耦接第三时钟端CBO的第三时钟信号线cbo1。
可选的，继续参考图9和图13可以看出，第一组信号线L01，移位寄存器单元00中的第一组晶体管，移位寄存器单元00中的第一组电容，第二组信号线L02，移位寄存器单元00中的第二组晶体管，移位寄存器单元00中的第二组 电容，以及第三组信号线L03可以沿第一方向X1依次排布。多条信号线中至少一条信号线沿第二方向X2延伸。且，沿第一方向X1，第一组信号线L02中的输入信号线in1、第一时钟信号线ck1、第二时钟信号线cb1和第一电源线vgh1依次排布，第二组信号线L02中的第二电源线vgl2、使能控制线en1、第二时钟信号线cb1和第一时钟信号线ck1依次排布。第三组信号线L03中的第一电源线vgh1和第三时钟信号线cbo1依次排布。其中，第一方向X1为从非显示区B0指向显示区A0的方向，第二方向X2与第一方向X1相交。如，参考图9和图13可以看出，其示出的第一方向X1与第二方向X2相互垂直。
可选的，参考图9可以看出，第一组晶体管可以包括：移位寄存器单元00中的第五晶体管T5、第六晶体管T6、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13和第十五晶体管T15。第一组电容可以包括：移位寄存器单元00中的第三电容C3和第四电容C4。第二组晶体管可以包括：移位寄存器单元00中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第七晶体管T7。第二组电容可以包括：移位寄存器单元00中的第一电容C1和第二电容C2。
可选的，继续参考图9可以看出，第四电容C4可以位于第十晶体管T10和第十三晶体管T13之间，且第十晶体管T10、第四电容C4和第十三晶体管T13可以沿靠近第二组信号线L02的方向依次排布。第十五晶体管T15、第九晶体管T9、第六晶体管T6和第三电容C3可以沿靠近第二组信号线L02的方向依次排布。第十一晶体管T11可以位于第十五晶体管T15和第十晶体管T10之间，且相对于第十五晶体管T15远离第一组信号线L01。第十二晶体管T12和第八晶体管T8可以位于第九晶体管T9与第四电容C4之间，且沿靠近第二组信号线L02的方向依次排布，且均相对于第十一晶体管T11靠近第十晶体管T10。
可选的，继续参考图9可以看出，第四晶体管T4可以位于第一电容C1与第二电容C2之间，且第一电容C1、第四晶体管T4和第二电容C2沿靠近第三组信号线L03的方向依次排布。第五晶体管T5、第一晶体管T1和第一电容C1可以沿第二方向X2依次排布。第七晶体管T7和第十四晶体管T14可以位于第五晶体管T5和第一晶体管T1之间，且沿靠近第三组信号线L03的方向依次排布。第二晶体管T2和第三晶体管T3可以沿第二方向依次排布，且位于第十四晶体管T14远离第二组信号线L02的一侧，且第二晶体管T2相对于第三晶体管 T3远离第四晶体管T4。
可选的，结合图9和图10可以看出，第五晶体管T5的半导体层、第七晶体管T7的半导体层和第十四晶体管T14的半导体层可以为一体结构。且，第二晶体管T2的半导体层与第三晶体管T3的半导体层可以为一体结构。
可选的，结合图9和图11可以看出，第十五晶体管T15的栅极b15和第九晶体管T9的栅极b9可以为一体结构。第三电容C3的第一电容电极c30、第八晶体管T8的栅极b8和第二晶体管T2的栅极b2可以为一体结构。第七晶体管T7的栅极b7和第十四晶体管T14的栅极b14可以为一体结构。第三晶体管T3的栅极b3和第二电容C2的第一电容电极c20可以为一体结构。第四晶体管T4的栅极b4和第一电容C1的第一电容电极c10可以为一体结构。且，第十晶体管T10的栅极b10与第四电容C4的第一电容电极c40可以为一体结构。且，本公开实施例记载的移位寄存器单元00中，第二晶体管T2的栅极b2和/或第三晶体管T3的栅极b3在衬底基板10上的正投影可以呈条形，且沿第一方向X1延伸。且，除栅极呈条形的晶体管外的其余晶体管的栅极在衬底基板10上的正投影可以均呈U型，即为双栅结构。
需要说明的是，一体结构可以是指采用一次构图工艺形成，构图工艺可以包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
综上所述，本公开实施例提供了一种显示面板，该显示面板中的移位寄存器单元包括第一移位电路和第二移位电路，且第二移位电路分别与使能控制端、第二电源端和输出端耦接，第二移位电路可以在使能控制端的控制下，控制第二电源端与输出端导通，即控制第二电源端向输出端提供第二电源信号。如此，相对于相关技术而言，提高了移位寄存器单元控制其输出端的电位的灵活性。
图15是本公开实施例提供的一种移位寄存器的结构示意图。如图15所示， 该移位寄存器000包括：至少两个级联的如图2、图8和图9任一所示的移位寄存器单元00。
其中，每级移位寄存器单元00的移位节点GO可以与级联的下一级移位寄存器单元00的输入信号端IN耦接，且每级移位寄存器单元00的输出端Eout可以与目标信号线耦接(图中未示出)。
每级移位寄存器单元00可以通过其输出端Eout向所耦接的目标信号线传输驱动信号，该目标信号线可以与显示面板中的像素电路耦接，像素电路可以基于该目标信号线提供的信号，驱动所耦接的发光元件发光。示例的，如上述实施例记载，该目标信号线可以为发光控制线。
此外，结合上述实施例可知，每级移位寄存器单元00还可以与第一时钟端CK、第二时钟端CB、第三时钟端CBO、第一电源端VGH、第二电源端VGL和使能控制端EN耦接(图15未示出)。且，第一级移位寄存器单元00的输入信号端IN可以与图15示出的帧开启信号端STV耦接，用于接收来自帧开启信号端STV的帧开启信号。
图16是本公开实施例提供的一种显示装置的结构示意图。如图16所示，该显示装置可以包括：上述实施例记载的显示面板100。且该显示面板100还可以包括多个像素电路1001和多条目标信号线L1，多个像素电路1001与多条目标信号线L1一一对应耦接，每个像素电路1001还与一个发光元件耦接(图中未示出)。移位寄存器000可以与多条目标信号线L1耦接，移位寄存器000可以用于为多条目标信号线L1提供驱动信号。像素电路1001可以用于基于该驱动信号驱动所耦接的发光元件发光。
图17是本公开实施例提供的一种像素电路的结构示意图。如图17所示，像素电路1001可以包括：开关子电路10011、驱动子电路10012、发光控制子电路10013、外部补偿子电路10014和调节子电路10015。
其中，开关子电路10011可以分别与栅线G1、数据线D1和第一节点P1耦接。该开关子电路10011可以用于响应于来自栅线G1的栅极驱动信号，控制数据线D1与第一节点P1的通断。
例如，开关子电路10011可以在栅极驱动信号的电位为第一电位时，控制数据线D1与第一节点P1导通，此时，数据线D1可以向第一节点P1传输数据 信号。以及，该开关子电路1001可以在栅极驱动信号的电位为第二电位时，控制数据线D1与第一节点P1断开连接。
驱动子电路10012可以分别与第一节点P1、驱动电源端Vdd和第二节点P2耦接，驱动子电路10012可以用于基于第一节点P1的电位和驱动电源端Vdd提供的驱动电源信号，向第二节点P2传输驱动信号。
例如，驱动子电路10012可以基于第一节点P1的电位和驱动电源信号，向第二节点P2传输驱动电流。
发光控制子电路10013可以分别与发光控制线EM、第二节点P2和发光元件L0耦接。该发光控制子电路10013可以用于响应于来自发光控制线EM的发光控制信号，控制第二节点P2与发光元件L0的通断。
例如，发光控制子电路10013可以与发光元件L0的阳极耦接，发光元件L0的阴极还可以与下拉电源端ELVss耦接。该发光控制子电路10013可以在发光控制信号的电位为第一电位时，控制第二节点P2与发光元件L0导通，此时，驱动子电路10012传输至第二节点P2的驱动电流可以再经该发光控制子电路10013传输至发光元件L0，以驱动发光元件L0发光。以及，该发光控制子电路10013可以在发光控制信号的电位为第二电位时，控制第二节点P2与发光元件L0断开连接。
外部补偿子电路10014可以分别与扫描信号线S1、第二节点P2和检测信号线S0耦接。该外部补偿子电路10014可以用于响应于扫描信号线S1提供的扫描信号，控制第二节点P2与检测信号线S0的通断。
例如，该外部补偿子电路10014可以在扫描信号的电位为第一电位时，控制第二节点P2与检测信号线S0导通，此时，检测信号线S0可以向第二节点P2传输检测信号，且检测信号线S0可以采集第二节点P2的电位。以及，该外部补偿子电路10014可以在扫描信号的电位为第二电位时，控制第二节点P2与检测信号线S0断开连接。
调节子电路10015可以分别与第一节点P1和第二节点P2耦接。该调节子电路10015可以用于调节第一节点P1的电位和第二节点P2的电位。
例如，该调节子电路10015可以通过自举作用，调节第一节点P1的电位和第二节点P2的电位。
图18是本公开实施例提供的另一种像素电路的结构示意图。如图18所示， 开关子电路10011可以包括：开关晶体管K1。驱动子电路10012可以包括：驱动晶体管K2。发光控制子电路10013可以包括：发光控制晶体管K3。外部补偿子电路10014可以包括：补偿晶体管K4。调节子电路10015可以包括：存储电容C0。
其中，开关晶体管K1的栅极可以与栅线G1耦接，开关晶体管K1的第一极可以与数据线耦接，开关晶体管K1的第二极可以与第一节点P1耦接。
驱动晶体管K2的栅极可以与驱动电源端Vdd耦接，驱动晶体管K2的第一极可以与第一节点P1耦接，驱动晶体管K2的第二极可以与第二节点P2耦接。
发光控制晶体管K3的栅极可以与发光控制线EM耦接，发光控制晶体管K3的第一极可以与第二节点P2耦接，发光控制晶体管K3的第二极可以与发光元件L0耦接。
补偿晶体管K4的栅极可以与扫描信号线S1耦接，补偿晶体管K4的第一极可以与第二节点P2耦接，补偿晶体管K4的第二极可以与检测信号线S0耦接。
存储电容C0的一端可以与第一节点P1耦接，存储电容C0的另一端可以与第二节点P2耦接。
结合图17、图18以及上述实施例记载可知，本公开实施例记载的移位寄存器000所耦接的目标信号线可以为发光控制线EM。即，移位寄存器000包括的每级移位寄存器单元00的输出端Eout可以与发光控制线EM耦接，用于向发光控制线EM提供所需的发光控制信号。
可选的，在本公开实施例中，补偿晶体管K4耦接的检测信号线S0还可以与外部补偿电路耦接，数据线D1还可以与源极驱动电路耦接。外部补偿电路可以基于检测信号线S0采集到的第二节点P2的电位确定驱动晶体管K2的阈值电压，并将该阈值电压传输至源极驱动电路。源极驱动电路可以基于接收到的阈值电压，灵活调节向所耦接的数据线D1提供所需的数据信号，以避免阈值电压漂移对发光元件L1的发光效果造成不良影响。该过程也可以称为外部补偿。
以图18所示像素电路，且像素电路包括的各个晶体管均为N型晶体管为例，对像素电路的驱动过程进行如下说明。图19示出了一种像素电路中各信号端的驱动时序图。共包括显示阶段T100和消隐阶段T200两个阶段。其中，显示阶段T100又可以包括初始化阶段t01、数据写入阶段t02和发光阶段t03。
其中，参考图19可以看出，在初始化阶段t01，扫描信号线S1提供的扫描 信号的电位可以为第一电位，补偿晶体管K4开启。进而，检测信号线S0可以通过开启的补偿晶体管K4向第二节点P2传输第二电位的检测信号，从而实现对第二节点P2的复位。且在该初始化阶段t01，移位寄存器单元00可以向发光控制线EM提供第二电位的发光控制信号，即发光控制线EM提供的发光控制信号的电位为第二电位，发光控制晶体管K3关断。且栅线G1提供的栅极驱动信号的电位为第二电位，开关晶体管K1关断。进而，驱动晶体管K2也关断。
在数据写入阶段t02，移位寄存器单元00依然向发光控制线EM提供第二电位的发光控制信号，即发光控制信号的电位保持为第二电位，发光控制晶体管K3保持关断。扫描信号的电位跳变为第二电位，补偿晶体管K4关断。栅极驱动信号的电位跳变为第一电位，开关晶体管K1开启。进而，数据线D1提供的数据信号可以经开启的开关晶体管K1传输至第一节点P1，实现对第一节点P1的充电。
在发光阶段t03，扫描信号的电位保持为第二电位，补偿晶体管K4保持关断。栅极驱动信号的电位跳变为第二电位，开关晶体管K1关断。移位寄存器单元00此时可以向发光控制线EM提供第一电位的发光控制信号，即发光控制信号的电位跳变为第一电位，发光控制晶体管K3开启。第一节点P1的电位在存储电容C0的自举作用下保持为第一电位，驱动晶体管K2开启。驱动晶体管K2基于第一节点P1的电位和驱动电源端Vdd提供的驱动电源信号，向第二节点P2传输驱动电流。该驱动电流再经开启的发光控制晶体管K3传输至发光元件L1，发光元件L1发光。
在消隐阶段T200，移位寄存器单元00可以向发光控制线EM提供第二电位的发光控制信号，即发光控制信号的电位跳变为第二电位，发光控制晶体管K3关断。栅极驱动信号的电位保持为第二电位，开关晶体管K1关断。扫描信号的电位跳变为第一电位，补偿晶体管K4开启。此时，第二节点P2的电位可以经开启的补偿晶体管K4传输至检测信号线S0，检测信号线S0再将采集到的第二节点P2的电位传输至所耦接的外部补偿电路，以便外部补偿电路基于第二节点P2的电位对提供至数据线D1的数据信号进行外部补偿。
可选的，图19还示出了移位寄存器单元所耦接的使能控制端EN的时序。
其中，在显示阶段T100，使能控制端EN可以持续提供第二电位的使能控制信号，在消隐阶段，使能控制信号的电位可以跳变为第一电位。此时，结合 图8，移位寄存器单元00中的第一晶体管T1开启，第二电位的第二电源信号可以经开启的第一晶体管T1可靠传输至输出端Eout。因移位寄存器单元00的输出端Eout是与发光控制线EM耦接，故有效确保了在消隐阶段，发光控制线EM可以可靠接收到处于第二电位的发光控制信号，即确保发光控制信号能够在消隐阶段保持稳定的低电平。
图20本公开实施例提供的一种显示面板中移位寄存器单元的驱动方法的流程图，该方法可以应用于如上述附图所示的移位寄存器单元00中。如图20所示，该方法可以包括：
步骤2001、输入阶段，第一移位电路响应于第一电位的第一时钟信号，第二电位的第二时钟信号，第一电位的输入信号，第一电位的第一电源信号和第二电位的第二电源信号，控制移位节点的电位为第二电位，第二移位电路响应于移位节点的第二电位，第一电位的第一时钟信号，第二电位的第二时钟信号，第一电源信号和第二电源信号，控制第一电源端与输出端导通，响应于第一电位的输出控制信号控制第三时钟端与输出端导通，以及响应于第二电位的使能控制信号控制第二电源端与输出端断开连接。
步骤2002、输出阶段，第一移位电路响应于第二电位的第一时钟信号，第一电位的第二时钟信号，第二电位的输入信号，第一电源信号和第二电源信号，控制移位节点的电位为第一电位，第二移位电路响应于移位节点的第一电位，第二电位的第一时钟信号，第一电位的第二时钟信号，第一电源信号和第二电源信号，控制第一电源端与输出端断开连接，响应于第一电位的输出控制信号，控制第三时钟端与输出端导通，以及响应于第二电位的使能控制信号，控制第二电源端与输出端断开连接。
步骤2003、第一下拉阶段，第一移位电路响应于第一电位的第一时钟信号，第二电位的第二时钟信号，第二电位的输入信号，第一电源信号和第二电源信号，控制移位节点的电位为第二电位，第二移位电路响应于移位节点的第二电位，第一电位的第一时钟信号，第二电位的第二时钟信号，第一电源信号和第二电源信号，控制第一电源端与输出端导通，响应于第二电位的输出控制信号，控制第三时钟端与输出端断开连接，以及响应于第二电位的使能控制信号，控制第二电源端与输出端断开连接。
其中，结合图19，在本公开实施例中，输入阶段，输出阶段和第一下拉阶 段可以在像素电路的显示阶段T100依次执行。
可选的，参考图21示出的另一种移位寄存器单元的驱动方法流程图可以看出，在第一下拉阶段，即步骤2003之后，方法还可以包括：
步骤2004、第二下拉阶段，第一移位电路响应于第二电位的第一时钟信号，第二电位的第二时钟信号，第一电位的输入信号，第一电源信号和第二电源信号，控制移位节点的电位为第二电位，第二移位电路响应于移位节点的第二电位，第二电位的第一时钟信号，第二电位的第二时钟信号，第一电源信号和第二电源信号，控制第一电源端与输出端断开连接，响应于第二电位的输出控制信号，控制第三时钟端与输出端断开连接，以及响应于第一电位的使能控制信号，控制第二电源端与输出端导通。
其中，在输入阶段，第三时钟端提供的第三时钟信号的电位为第一电位。在输出阶段，第三时钟信号的电位为第二电位。在第一下拉阶段，第三时钟信号的电位为第一电位。在第二下拉阶段，第三时钟信号的电位为第二电位。且结合图19，在本公开实施例中，该第二下拉阶段可以在像素电路的消隐阶段T200执行。
以图8所示的移位寄存器单元，且移位寄存器单元中各个晶体管均为N型晶体管为例，对移位寄存器单元的驱动原理进行如下说明。图22示出了一种移位寄存器单元所耦接的各个信号端，以及移位节点GO的时序图。
参考图22可以看出，在输入阶段t1，输入信号端IN提供的输入信号的电位，第一时钟端CK提供的第一时钟信号的电位，以及第三时钟端CBO提供的第三时钟信号的电位均为第一电位；第二时钟端CB提供的第二时钟信号的电位，以及使能控制端EN提供的使能控制信号的电位均为第二电位。相应的，第五晶体管T5、第八晶体管T8和第九晶体管T9均开启，第一晶体管T1和第十二晶体管T12均关断。且第十四晶体管T14在第一电位的第一电源信号的控制下开启。
在上述晶体管通断基础上，第一电位的第一电源信号经开启的第八晶体管T8传输至上拉节点PU，第十三晶体管T13开启，第二电位的第二电源信号经开启的第十三晶体管T13传输至移位节点GO。且第一电位的输入信号经开启的第九晶体管T9传输至第二下拉节点PD2。相应的，第十晶体管T10开启，第一电位的第一时钟信号经开启的第十晶体管T10传输至上拉节点PU。且写入至第 二下拉节点PD2的第一电位的输入信号继续经开启的第十四晶体管T14传输至第十五晶体管T15的栅极。相应的，第十五晶体管T15开启，第二电位的第二时钟信号经开启的第十五晶体管T15传输至移位节点GO。第四晶体管T4和第六晶体管T6均关断。第一电位的第一电源信号经开启的第五晶体管T5传输至下拉参考节点PD0，相应的，第七晶体管T7开启。写入至下拉参考节点PD0的第一电位的第一电源信号继续经开启的第七晶体管T7传输至第一下拉节点PD1。第三晶体管T3开启。第一电位的第一电源信号经开启的第三晶体管T3传输至输出端Eout。且因输出控制端CN_O耦接至第十五晶体管T15的栅极，故，输出控制端CN_O提供的输入控制信号的电位也为第一电位，第二晶体管T2开启，第一电位的第三时钟信号经开启的第二晶体管T2传输至输出端Eout。
在输出阶段t2，第二时钟信号的电位跳变为第一电位，输入信号的电位，第一时钟信号的电位，以及第三时钟信号的电位均跳变为第二电位，使能控制信号的电位保持为第二电位。相应的，第一晶体管T1、第五晶体管T5、第八晶体管T8和第九晶体管T9均关断，第十二晶体管T12开启。第十五晶体管T15的栅极处的第一电位在第四电容C4的自举作用下保持为较高的第一电位，且此时第十五晶体管T15的栅极处的第一电位大于第一电源信号提供的第一电位，故第十四晶体管T14关断，第二晶体管T2保持开启。
在上述晶体管通断基础上，结合上述输入阶段t1的记载可知，第一电位的第二时钟信号能够经开启的第十五晶体管T15传输至移位节点GO，相应的，第四晶体管T4和第六晶体管T6均开启。第二电位的第二电源信号经开启的第四晶体管T4传输至下拉参考节点PD0，以及经开启的第六晶体管T6传输至第一下拉节点PD1。相应的，第七晶体管T7和第三晶体管T3关断。第二电位的第三时钟信号经开启的第二晶体管T2传输至输出端Eout。
在第一下拉阶段t3，输入信号的电位和使能控制信号的电位保持为第二电位，第一时钟信号的电位和第三时钟信号的电位均跳变为第一电位，第二时钟信号的电位跳变为第二电位。相应的，第五晶体管T5、第八晶体管T8和第九晶体管T9均开启，第一晶体管T1和第十二晶体管T12均关断。且第十四晶体管T14在第一电位的第一电源信号的控制下开启。
在上述晶体管通断基础上，第二电位的输入信号经开启的第九晶体管T9传输至第二下拉节点PD2，第十晶体管T10关断。第二电位的输入信号继续经开 启的第十四晶体管T14传输至第十五晶体管T15的栅极，第十五晶体管T15和第二晶体管T2均关断。第一电位的第一电源信号经开启的第八晶体管T8传输至上拉节点PU，第十三晶体管T13和第十一晶体管T11均开启。第二电位的第二电源信号经开启的第十三晶体管T13传输至移位节点GO，相应的，第四晶体管T4和第六晶体管T6均关断。第一电位的第一电源信号经开启的第五晶体管T5传输至下拉参考节点PD0，相应的，第七晶体管T7开启。写入至下拉参考节点PD0的第一电位的第一电源信号继续经开启的第七晶体管T7传输至第一下拉节点PD1。第三晶体管T3开启。第一电位的第一电源信号经开启的第三晶体管T3传输至输出端Eout。
在第二下拉阶段t4，使能控制信号的电位跳变为第一电位，其余信号的电位均为第二电位。相应的，仅第一晶体管T1开启，第二电位的第二电源信号经开启的第一晶体管T1传输至输出端Eout。
需要说明的是，在第一下拉阶段t3与第二下拉阶段t4之间还可以包括一个降噪阶段t5。在该降噪阶段t5，输入信号的电位和使能控制信号的电位均保持为第一电位，第一时钟信号的电位和第三时钟信号的电位均跳变为第二电位，第二时钟信号的电位跳变为第一电位。相应的，第一晶体管T1、第五晶体管T5、第八晶体管T8和第九晶体管T9均关断，第十二晶体管T12开启。且第十四晶体管T14在第一电位的第一电源信号的控制下开启。且第十四晶体管T14在第一电位的第一电源信号的控制下开启。
在上述晶体管通断基础上，写入至上拉节点PU的第一电位的第一电源信号在第二电容C2的自举作用下变得更高，即保持为第一电位。相应的，第十三晶体管T13和第十一晶体管T11均开启。第二电位的第二电源信号经开启的第十一晶体管T11和第十二晶体管T12传输至第二下拉节点PD2。写入至第二下拉节点PD2的第二电位的第二电源信号继续经开启的第十四晶体管T14传输至第十五晶体管T15的栅极。第二晶体管T2和第十五晶体管T15均关断。第二电位的第二电源信号经开启的第十三晶体管T13传输至移位节点GO。相应的，第四晶体管T4和第六晶体管T6均关断。此外，在第一电容C1的自举作用下，前一阶段写入至下拉参考节点PD0的第一电位的第一电源信号变得更高，即下拉参考节点PD0的电位在该阶段保持为第一电位。相应的，第七晶体管T7开启。下拉参考节点PD0的第一电位的第一电源信号继续经开启的第七晶体管T7传输至 第一下拉节点PD1。第三晶体管T3开启。第一电位的第一电源信号经开启的第三晶体管T3传输至输出端Eout。
需要说明的是，经测试，在第一下拉阶段t3，下拉参考节点PD0的电位Vpd0一般为：Vgh-Vth1。第一下拉节点PD1的电位Vpd1一般为：Vgh-Vth2。在降噪阶段t5，下拉参考节点PD0的电位Vpd0会被第二时钟信号拉到Vgh-Vth1+(Vgh-Vgl)。相应的，第一下拉节点PD1的电位Vpd1被充电至Vpd0-Vth2，远大于Vgh+Vth3，进而，第三晶体管T3可靠开启。
其中，Vth1是指第五晶体管T5的阈值电压，Vth2是指第七晶体管T7的阈值电压，Vth3是指第三晶体管T3的阈值电压。Vgh是指第一电源信号的电位值，Vgl是指第二电源信号的电位值。
需要说明的是，结合图19和图22可知，降噪阶段t5可以在像素电路的显示阶段T100执行。且，上述实施例记载的输入阶段t1、输出阶段t2、第一下拉阶段t3和降噪阶段t5是在显示阶段T100中依次执行。即，在像素电路的显示阶段T100，可以先执行输入阶段t1，再执行输出阶段t2，再执行第一下拉阶段t3，最后执行降噪阶段t5。在像素电路的消隐阶段T200仅执行第二下拉阶段t4。
可选的，继续结合图22可以看出，第二时钟信号的周期与第三时钟信号的周期可以相同，且在输出阶段t2，第二时钟信号的占空比大于第三时钟信号的占空比。即，在输出阶段t2，第二时钟信号的脉宽大于第三时钟信号的脉宽。换言之，第二时钟信号为第一电位的持续时长大于第三时钟信号为第二电位的持续时长。如此，可以使得在第十五晶体管T15充分开启后，第二晶体管T2再开启。即，使得第三晶体管T3在第一下拉节点PD1的第二电位控制下有效关断，确保第一电位的第一电源信号不会经第三晶体管T3传输至输出端Eout后，再控制第二电位的第三电源信号经开启的第二晶体管T2传输至输出端Eout。有效避免了在输出阶段t2，第三晶体管T3耦接的第一电源端VGH传输的第一电位的第一电源信号对输出端Eout造成干扰，进一步改善了输出端Eout的输出波形。经测试，在波形改善后，输出端Eout输出的信号的下降沿变小。
此外，在输出阶段t2过渡于第一下拉阶段t3时，第三时钟信号的电位需要上升至第一电位，若第二晶体管T2为双栅晶体管，则第二晶体管T2无法充分快速开启，输出端Eout由第二电位跳变为第一电位时会出现台阶。且，因在第一下拉阶段t3，第一下拉节点PD1的第一电位Vpd1一般为：Vgh-Vth1-Vth2， Vpd1小于Vgh，故第三晶体管T3开启也不充分。相应的，第一电位的第一电源信号也无法经第三晶体管T3传输至输出端Eout。即，无法快速将输出端Eout处的电位快速补充至第一电位，输出端Eout的第一电位出现的台阶持续时间较长。本公开通过设置第二晶体管T2为单栅晶体管，可以有效避免输出端Eout的电位由第二电位跳变为第一电位时出现台阶，改善了输出端Eout的输出波形。
示例的，图23示出了改善前后输出端Eout的输出波形。从图23可以看出，若设置第二晶体管T2为双栅晶体管，则输出端Eout由第二电位跳变为第一电位时，会出现台阶状现象。而若设置第二晶体管T2为单栅晶体管，则输出端Eout可以由第二电位直接跳变为第一电位，不会出现台阶现象。
可选的，本公开实施例记载的显示装置可以为：有机发光二极管(organic light emitting diode，OLED)显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框等任何具有显示功能的产品或部件。
可选的，本公开实施例记载的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。
同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。
“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。
“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (25)

  1. 一种显示面板，所述显示面板包括：
    衬底基板，所述衬底基板具有显示区和围绕所述显示区的非显示区；
    以及，位于所述非显示区的移位寄存器单元；
    其中，所述移位寄存器单元包括：第一移位电路和第二移位电路；
    所述第一移位电路分别与第一时钟端、第二时钟端、输入信号端、第一电源端、第二电源端和移位节点耦接，所述第一移位电路用于响应于所述第一时钟端提供的第一时钟信号，所述第二时钟端提供的第二时钟信号，所述输入信号端提供的输入信号，所述第一电源端提供的第一电源信号和所述第二电源端提供的第二电源信号，控制所述移位节点的电位；
    所述第二移位电路分别与所述移位节点、所述第一时钟端、所述第二时钟端、第三时钟端、使能控制端、输出控制端、所述第一电源端、所述第二电源端和输出端耦接，所述第二移位电路用于响应于所述移位节点的电位，所述第一时钟信号，所述第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端的通断，响应于所述输出控制端提供的输出控制信号，控制所述第三时钟端与所述输出端的通断，且响应于所述使能控制端提供的使能控制信号，控制所述第二电源端与所述输出端的通断。
  2. 根据权利要求1所述的显示面板，其中，所述第二移位电路被配置为：在所述移位寄存器单元耦接的像素电路的显示阶段，响应于第二电位的所述使能控制信号，控制所述第二电源端与所述输出端断开连接；以及，在所述移位寄存器单元耦接的像素电路的消隐阶段，响应于第一电位的所述使能控制信号，控制所述第二电源端与所述输出端导通。
  3. 根据权利要求1所述的显示面板，其中，所述第二移位电路包括：第一输出控制子电路、第二输出控制子电路和第一输出子电路；
    所述第一输出控制子电路分别与所述移位节点、所述第一时钟端、所述第二时钟端、所述第一电源端、所述第二电源端和所述输出端耦接，所述第一输出控制子电路用于响应于所述移位节点的电位，所述第一时钟信号，所述第二 时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端的通断；
    所述第二输出控制子电路分别与所述使能控制端、所述第二电源端和所述输出端耦接，所述第二输出控制子电路用于响应于所述使能控制信号，控制所述第二电源端与所述输出端的通断；
    所述第一输出子电路分别与所述输出控制端、所述第三时钟端和所述输出端耦接，所述第一输出子电路用于响应于所述输出控制信号，控制所述第三时钟端与所述输出端的通断。
  4. 根据权利要求3所述的显示面板，其中，所述第二输出控制子电路包括：第一晶体管；
    所述第一晶体管的栅极与所述使能控制端耦接，所述第一晶体管的第一极与所述第二电源端耦接，所述第一晶体管的第二极与所述输出端耦接。
  5. 根据权利要求3所述的显示面板，其中，所述第一输出子电路包括：第二晶体管，且所述第二晶体管为单栅晶体管；
    所述第二晶体管的栅极与所述输出控制端耦接，所述第二晶体管的第一极与所述第三时钟端耦接，所述第二晶体管的第二极与所述输出端耦接。
  6. 根据权利要求3至5任一所述的显示面板，其中，所述第一输出控制子电路包括：第一降噪控制子电路、第二降噪控制子电路和降噪子电路；
    所述第一降噪控制子电路分别与所述移位节点、所述第一时钟端、所述第二时钟端、所述第一电源端、所述第二电源端和下拉参考节点耦接，所述第一降噪控制子电路用于响应于所述移位节点的电位，控制所述第二电源端与所述下拉参考节点的通断，响应于所述第一时钟信号，控制所述第一电源端与所述下拉参考节点的通断，以及基于所述第二时钟信号，控制所述下拉参考节点的电位；
    所述第二降噪控制子电路分别与所述移位节点、所述第一电源端、所述第二电源端、所述下拉参考节点和第一下拉节点耦接，所述第二降噪控制子电路用于响应于所述移位节点的电位，控制所述第二电源端与所述第一下拉节点的 通断，响应于所述下拉参考节点的电位，控制所述下拉参考节点与所述第一下拉节点的通断，以及基于所述第一电源信号，控制所述第一下拉节点的电位；
    所述降噪子电路分别与所述第一下拉节点、所述第一电源端和所述输出端耦接，所述降噪子电路用于响应于所述第一下拉节点的电位，控制所述第一电源端与所述移位节点的通断。
  7. 根据权利要求6所述的显示面板，其中，所述降噪子电路包括：第三晶体管，且所述第三晶体管为单栅晶体管；
    所述第三晶体管的栅极与所述第一下拉节点耦接，所述第三晶体管的第一极与所述第一电源端耦接，所述第三晶体管的第二极与所述输出端耦接。
  8. 根据权利要求6所述的显示面板，其中，所述第一降噪控制子电路包括：第四晶体管、第五晶体管和第一电容；所述第二降噪控制子电路包括：第六晶体管、第七晶体管和第二电容；
    所述第四晶体管的栅极和所述第六晶体管的栅极均与所述移位节点耦接，所述第四晶体管的第一极和所述第六晶体管的第一极均与所述第二电源端耦接，所述第四晶体管的第二极与所述下拉参考节点耦接，所述第六晶体管的第二极与所述第一下拉节点耦接；
    所述第五晶体管的栅极与所述第一时钟端耦接，所述第五晶体管的第一极与所述第一电源端耦接，所述第五晶体管的第二极与所述下拉参考节点耦接；
    所述第七晶体管的栅极和第一极均与所述下拉参考节点耦接，所述第七晶体管的第二极与所述第一下拉节点耦接；
    所述第一电容的一端与所述下拉参考节点耦接，所述第一电容的另一端与所述第二时钟端耦接；
    所述第二电容的一端与所述第一下拉节点耦接，所述第二电容的另一端与所述第一电源端耦接。
  9. 根据权利要求1至8任一所述的显示面板，其中，所述第一移位电路包括：输入子电路、控制子电路和第二输出子电路；
    所述输入子电路分别与所述第一时钟端、所述第一电源端、所述输入信号 端、上拉节点和第二下拉节点耦接，所述输入子电路用于响应于所述第一时钟信号，控制所述第一电源端与所述上拉节点的通断，以及控制所述输入信号端与所述第二下拉节点的通断；
    所述控制子电路分别与所述上拉节点、所述第二下拉节点、所述第一时钟端、所述第二时钟端和所述第二电源端耦接，所述控制子电路用于响应于所述上拉节点的电位和所述第二时钟信号，控制所述第二电源端与所述第二下拉节点的通断，以及响应于所述第二下拉节点的电位，控制所述第一时钟端与所述上拉节点的通断；
    所述第二输出子电路分别与所述上拉节点、所述第二下拉节点、所述第一电源端、所述第二电源端、所述第二时钟端和所述移位节点耦接，所述第二输出子电路用于响应于所述上拉节点的电位，控制所述第二电源端与所述移位节点的通断，以及响应于所述第二下拉节点的电位和所述第一电源信号，控制所述第二时钟端与所述移位节点的通断。
  10. 根据权利要求9所述的显示面板，其中，所述输入子电路包括：第八晶体管和第九晶体管；所述控制子电路包括：第十晶体管、第十一晶体管和第十二晶体管；所述第二输出子电路包括：第十三晶体管、第十四晶体管、第十五晶体管、第三电容和第四电容；
    所述第八晶体管的栅极和所述第九晶体管的栅极均与所述第一时钟端耦接，所述第八晶体管的第一极与所述第一电源端耦接，所述第八晶体管的第二极与所述上拉节点耦接，所述第九晶体管的第一极与所述输入信号端耦接，所述第九晶体管的第二极与所述第二下拉节点耦接；
    所述第十晶体管的栅极与所述第二下拉节点耦接，所述第十晶体管的第一极与所述第一时钟端耦接，所述第十晶体管的第二极与所述上拉节点耦接；
    所述第十一晶体管的栅极与所述上拉节点耦接，所述第十一晶体管的第一极与所述第二电源端耦接，所述第十一晶体管的第二极与所述第十二晶体管的第一极耦接，所述第十二晶体管的栅极与所述第二时钟端耦接，所述第十二晶体管的第二极与所述第二下拉节点耦接；
    所述第十三晶体管的栅极与所述上拉节点耦接，所述第十三晶体管的第一极与所述第二电源端耦接，所述第十三晶体管的第二极与所述移位节点耦接；
    所述第十四晶体管的栅极与所述第一电源端耦接，所述第十四晶体管的第一极与所述第二下拉节点耦接，所述第十四晶体管的第二极与所述第十五晶体管的栅极耦接，所述第十五晶体管的第一极与所述第二时钟端耦接，所述第十五晶体管的第二极与所述移位节点耦接；
    所述第三电容的一端与所述上拉节点耦接，所述第三电容的另一端与所述第二电源端耦接；
    所述第四电容的一端与所述第十五晶体管的栅极耦接，所述第四电容的另一端与所述移位节点耦接。
  11. 根据权利要求10所述的显示面板，其中，所述输出控制端与所述第十五晶体管的栅极耦接。
  12. 根据权利要求1至11任一所述的显示面板，其中，所述移位寄存器单元包括的晶体管均为N型晶体管。
  13. 根据权利要求1至12任一所述的显示面板，其中，所述移位寄存器单元包括：位于所述衬底基板一侧的半导体层，第一导电层、第二导电层和第三导电层；
    所述半导体层至少包括：所述移位寄存器单元中至少一个晶体管的沟道区、源极区和漏极区；
    所述第一导电层至少包括：所述移位寄存器单元中至少一个晶体管的栅极和至少一个电容的第一电容电极，且所述至少一个晶体管的栅极与沟道区交叠；
    所述第二导电层至少包括：所述移位寄存器单元中至少一个电容的第二电容电极，且所述至少一个电容的第二电容电极与第一电容电极交叠；
    所述第三导电层至少包括：多条信号线，以及所述移位寄存器单元中至少一个晶体管的源极和漏极，且所述至少一个晶体管的源极与源极区耦接，所述至少一个晶体管的漏极与漏极区耦接，所述多条信号线分别与所述移位寄存器单元耦接的各个信号端耦接。
  14. 根据权利要求13所述的显示面板，其中，所述多条信号线包括：沿第一 方向依次间隔排布的第一组信号线、第二组信号线和第三组信号线；
    所述第一组信号线包括：耦接所述第一电源端的第一电源线；
    所述第二组信号线包括：耦接所述使能控制端的使能控制线，
    所述第三组信号线包括：所述第一电源线；
    其中，所述第一组信号线，所述移位寄存器单元中的第一组晶体管，所述移位寄存器单元中的第一组电容，所述第二组信号线，所述移位寄存器单元中的第二组晶体管，所述移位寄存器单元中的第二组电容，以及所述第三组信号线沿所述第一方向依次排布；且所述多条信号线中至少一条信号线沿第二方向延伸，所述第一方向为从所述非显示区指向所述显示区的方向，所述第二方向与所述第一方向相交。
  15. 根据权利要求14所述的显示面板，其中，所述第一组信号线还包括：耦接所述输入信号端的输入信号线，耦接所述第一时钟端的第一时钟信号线，以及耦接所述第二时钟端的第二时钟信号线；
    所述第二组信号线还包括：耦接所述第二电源端的第二电源线，所述第一时钟信号线和所述第二时钟信号线；
    所述第三组信号线还包括：耦接所述第三时钟端的第三时钟信号线；
    且，沿所述第一方向，所述第一组信号线中的输入信号线、第一时钟信号线、第二时钟信号线和第一电源线依次排布，所述第二组信号线中的第二电源线、使能控制线、第二时钟信号线和第一时钟信号线依次排布；所述第三组信号线中的第一电源线和第三时钟信号线依次排布。
  16. 根据权利要求14所述的显示面板，其中，所述第一组晶体管包括：所述移位寄存器单元中的第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管和第十五晶体管；
    所述第一组电容包括：所述移位寄存器单元中的第三电容和第四电容；
    所述第二组晶体管包括：所述移位寄存器单元中的第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第七晶体管；
    所述第二组电容包括：所述移位寄存器单元中的第一电容和第二电容。
  17. 根据权利要求16所述的显示面板，其中，所述第四电容位于所述第十晶体管和所述第十三晶体管之间，且所述第十晶体管、所述第四电容和所述第十三晶体管沿靠近所述第二组信号线的方向依次排布；
    所述第十五晶体管、所述第九晶体管、所述第六晶体管和所述第三电容沿靠近所述第二组信号线的方向依次排布；
    所述第十一晶体管位于所述第十五晶体管和所述第十晶体管之间，且相对于所述第十五晶体管远离所述第一组信号线；
    所述第十二晶体管和所述第八晶体管位于所述第九晶体管与所述第四电容之间，且沿靠近所述第二组信号线的方向依次排布，且均相对于所述第十一晶体管靠近所述第十晶体管。
  18. 根据权利要求16所述的显示面板，其中，所述第四晶体管位于所述第一电容与所述第二电容之间，且所述第一电容、所述第四晶体管和所述第二电容沿靠近所述第三组信号线的方向依次排布；
    所述第五晶体管、所述第一晶体管和所述第一电容沿所述第二方向依次排布；所述第七晶体管和所述第十四晶体管位于所述第五晶体管和所述第一晶体管之间，且沿靠近所述第三组信号线的方向依次排布；
    所述第二晶体管和所述第三晶体管沿所述第二方向依次排布，且位于所述第十四晶体管远离所述第二组信号线的一侧，且所述第二晶体管相对于所述第三晶体管远离所述第四晶体管。
  19. 根据权利要求16所述的显示面板，其中，所述第五晶体管的半导体层、所述第七晶体管的半导体层和所述第十四晶体管的半导体层为一体结构；
    且，所述第二晶体管的半导体层与所述第三晶体管的半导体层为一体结构。
  20. 根据权利要求16所述的显示面板，其中，所述第十五晶体管的栅极和所述第九晶体管的栅极为一体结构；
    所述第三电容的第一电容电极、所述第八晶体管的栅极和所述第二晶体管的栅极为一体结构；
    所述第七晶体管的栅极和所述第十四晶体管的栅极为一体结构；
    所述第三晶体管的栅极和所述第二电容的第一电容电极为一体结构；
    所述第四晶体管的栅极和所述第一电容的第一电容电极为一体结构；
    且，所述第十晶体管的栅极与所述第四电容的第一电容电极为一体结构。
  21. 根据权利要求16所述的显示面板，其中，所述移位寄存器单元中，所述第二晶体管的栅极和/或所述第三晶体管的栅极在所述衬底基板上的正投影呈条形，且沿所述第一方向延伸；且，除栅极呈条形的晶体管外的其余晶体管的栅极在所述衬底基板上的正投影均呈U型。
  22. 一种显示面板中移位寄存器单元的驱动方法，应用于如权利要求1至21任一所述的移位寄存器单元中，所述方法包括：
    输入阶段，第一移位电路响应于第一电位的第一时钟信号，第二电位的第二时钟信号，第一电位的输入信号，第一电位的第一电源信号和第二电位的第二电源信号，控制移位节点的电位为第二电位；第二移位电路响应于所述移位节点的第二电位，所述第一电位的第一时钟信号，所述第二电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端导通，响应于第一电位的输出控制信号控制第三时钟端与所述输出端导通，以及响应于第二电位的使能控制信号控制所述第二电源端与所述输出端断开连接，所述第三时钟端提供的第三时钟信号的电位为第一电位；
    输出阶段，所述第一移位电路响应于第二电位的第一时钟信号，第一电位的第二时钟信号，第二电位的输入信号，所述第一电源信号和所述第二电源信号，控制所述移位节点的电位为第一电位；所述第二移位电路响应于所述移位节点的第一电位，所述第二电位的第一时钟信号，所述第一电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端断开连接，响应于第一电位的输出控制信号，控制所述第三时钟端与所述输出端导通，以及响应于第二电位的使能控制信号，控制所述第二电源端与所述输出端断开连接，所述第三时钟信号的电位为第二电位；
    第一下拉阶段，所述第一移位电路响应于第一电位的第一时钟信号，第二电位的第二时钟信号，第二电位的输入信号，所述第一电源信号和所述第二电源信号，控制所述移位节点的电位为第二电位；所述第二移位电路响应于所述 移位节点的第二电位，所述第一电位的第一时钟信号，所述第二电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端导通，响应于第二电位的输出控制信号，控制所述第三时钟端与所述输出端断开连接，以及响应于第二电位的使能控制信号，控制所述第二电源端与所述输出端断开连接，所述第三时钟信号的电位为第一电位；
    其中，所述输入阶段，所述输出阶段和所述第一下拉阶段在所述移位寄存器单元耦接的像素电路的显示阶段执行。
  23. 根据权利要求22所述的方法，其中，在所述第一下拉阶段之后，所述方法还包括：
    第二下拉阶段，所述第一移位电路响应于第二电位的第一时钟信号，第二电位的第二时钟信号，第一电位的输入信号，所述第一电源信号和所述第二电源信号，控制所述移位节点的电位为第二电位；所述第二移位电路响应于所述移位节点的第二电位，所述第二电位的第一时钟信号，所述第二电位的第二时钟信号，所述第一电源信号和所述第二电源信号，控制所述第一电源端与所述输出端断开连接，响应于第二电位的输出控制信号，控制所述第三时钟端与所述输出端断开连接，以及响应于第一电位的使能控制信号，控制所述第二电源端与所述输出端导通，所述第三时钟信号的电位为第二电位；
    其中，所述第二下拉阶段在所述像素电路的消隐阶段执行。
  24. 根据权利要求22或23所述的方法，其中，所述第二时钟信号的周期与所述第三时钟信号的周期相同，且在所述输出阶段，所述第二时钟信号的占空比大于所述第三时钟信号的占空比。
  25. 一种移位寄存器，其中，所述移位寄存器包括：至少两个级联的移位寄存器单元；所述移位寄存器单元包括如权利要求1至21任一所述的显示面板中的移位寄存器单元；
    其中，每级所述移位寄存器单元的移位节点与级联的下一级所述移位寄存器单元的所述输入信号端耦接，且每级所述移位寄存器单元的输出端与目标信号线耦接，所述目标信号线为所述显示面板中像素电路所耦接的发光控制线。
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