WO2021210095A1 - 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 - Google Patents

半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 Download PDF

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WO2021210095A1
WO2021210095A1 PCT/JP2020/016567 JP2020016567W WO2021210095A1 WO 2021210095 A1 WO2021210095 A1 WO 2021210095A1 JP 2020016567 W JP2020016567 W JP 2020016567W WO 2021210095 A1 WO2021210095 A1 WO 2021210095A1
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semiconductor region
semiconductor
insulating film
semiconductor device
nanowire
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French (fr)
Japanese (ja)
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研一 河口
高橋　剛
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2022514920A priority Critical patent/JP7384273B2/ja
Priority to EP20931249.5A priority patent/EP4138141A4/en
Priority to CN202080099700.4A priority patent/CN115428166B/zh
Priority to PCT/JP2020/016567 priority patent/WO2021210095A1/ja
Publication of WO2021210095A1 publication Critical patent/WO2021210095A1/ja
Priority to US17/954,385 priority patent/US12363968B2/en
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Definitions

  • This disclosure relates to a semiconductor device, a reservoir computing system, and a method for manufacturing the semiconductor device.
  • a computing system for AI is underway in order to provide advanced information processing services that utilize artificial intelligence.
  • the movement to realize such a system by adopting neuromorphic computing inspired by the neural model of the living body is being developed.
  • reservoir computing is expected as a technology for advancing AI such as video recognition and prediction because it is capable of time-series information processing.
  • a network type circuit called a reservoir circuit which includes a plurality of nonlinear elements having different nonlinear characteristics, is used.
  • An object of the present disclosure is to provide a semiconductor device, a reservoir computing system, and a method for manufacturing a semiconductor device capable of arranging a plurality of non-linear elements having different non-linear characteristics with a high degree of integration.
  • each comprises a first conductive type first semiconductor region and a second conductive type second semiconductor region provided on the first semiconductor region and having the shape of a nanowire.
  • a plurality of tunnel diodes provided, an insulating film covering the side surface of the second semiconductor region, a plurality of first electrodes each connected to the first semiconductor region, and each connected to the second semiconductor region. It has a plurality of second electrodes, and the second electrode has a first surface facing the side surface of the second semiconductor region with the insulating film sandwiched between the plurality of tunnel diodes.
  • Semiconductor devices having different diameters of the second semiconductor region are provided.
  • a plurality of nonlinear elements having different nonlinear characteristics can be arranged with a high degree of integration.
  • the first embodiment relates to a semiconductor device including a semiconductor region having the shape of nanowires.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment.
  • the n-type semiconductor layer 102 is formed on the substrate 101, and the insulating film 103 is formed on the n-type semiconductor layer 102.
  • the insulating film 103 is formed with openings 21 and 22 that reach the n-type semiconductor layer 102.
  • the substrate 101 is a semi-insulating (SI) -GaAs (111) B substrate
  • the n-type semiconductor layer 102 is an n-type GaAs layer having a thickness of 100 nm to 300 nm.
  • the insulating film 103 is a silicon nitride film having a thickness of 40 nm to 60 nm, and the openings 21 and 22 have diameters of 40 nm to 200 nm. The diameter of the opening 21 is larger than the diameter of the opening 22.
  • the semiconductor device 100 has a first nanowire 11 that grows above the substrate 101 through the opening 21, and a second nanowire 12 that grows above the substrate 101 through the opening 22.
  • the diameters of the first nanowire 11 and the second nanowire 12 are 40 nm to 200 nm.
  • the first nanowire 11 is thicker than the second nanowire 12.
  • the n-type semiconductor layer 102 is separated into a region connected to the first nanowire 11 and a region connected to the second nanowire 12 by an element separation groove 109.
  • the first nanowire 11 has an n-type first semiconductor region 111 and a p-type second semiconductor region 112.
  • the first semiconductor region 111 is provided on the n-type semiconductor layer 102 and extends upward.
  • the second semiconductor region 112 is provided on the first semiconductor region 111 and extends upward.
  • a metal film 31 is formed on the second semiconductor region 112.
  • the metal film 31 is, for example, a gold (Au) film having a diameter of 40 nm to 200 nm.
  • the second nanowire 12 has an n-type first semiconductor region 121 and a p-type second semiconductor region 122.
  • the first semiconductor region 121 is provided on the n-type semiconductor layer 102 and extends upward.
  • the second semiconductor region 122 is provided on the first semiconductor region 121 and extends upward.
  • a metal film 32 is formed on the second semiconductor region 122.
  • the metal film 32 is, for example, a gold (Au) film having a diameter of 40 nm to 200 nm.
  • the second semiconductor regions 112 and 122 have the shape of nanowires.
  • the first semiconductor regions 111 and 121 may also have the shape of nanowires.
  • the first semiconductor region 111 and 121 are nanowire n-type InAs
  • the second semiconductor region 112 and 122 is a nanowire of p-type GaAs 1-x Sb x.
  • the Sb composition ratio x of GaAs 1-x Sb x is preferably 0.8 or more, and the Sb composition ratio x may be 1.0.
  • the n-type first semiconductor region 111 and the p-type second semiconductor region 112 are tunnel-junctioned to each other, and the n-type first semiconductor region 121 and the p-type second semiconductor region 122 are tunnel-junctioned to each other.
  • the first nanowire 11 and the second nanowire 12 are examples of tunnel diodes.
  • the heights (lengths) of the first semiconductor regions 111 and 121 are, for example, 0.5 ⁇ m to 0.7 ⁇ m, and the height of the first semiconductor region 111 and the height of the first semiconductor region 121 may be equal to each other.
  • the heights (lengths) of the second semiconductor regions 112 and 122 are, for example, 1.0 ⁇ m to 1.5 ⁇ m, and the height of the second semiconductor region 112 and the height of the second semiconductor region 122 may be equal to each other.
  • the height (length) of the first nanowire 11 and the second nanowire 12 is, for example, 1.5 ⁇ m to 2.0 ⁇ m, and the height of the first nanowire 11 and the height of the second nanowire 12 may be equal to each other.
  • An insulating film 104 is formed to cover the side surface of the first nanowire 11 and the side surface of the second nanowire 12.
  • the insulating film 104 is, for example, an aluminum oxide film or a hafnium oxide film having a thickness of 10 nm to 30 nm.
  • the thickness referred to here is the thickness in the direction perpendicular to the side surfaces 112A and 122A of the second semiconductor regions 112 and 122.
  • the insulating film 104 is also formed on the insulating film 103.
  • An organic insulating film 105 is formed on the insulating film 104.
  • the organic insulating film 105 is, for example, a benzocyclobutene (BCB) film.
  • the upper surface of the organic insulating film 105 is above the bonding interface 113 between the first semiconductor region 111 and the second semiconductor region 112 and the bonding interface 123 between the first semiconductor region 121 and the second semiconductor region 122.
  • a metal film 41 in contact with the metal film 31 and a metal film 42 in contact with the metal film 32 are formed on the organic insulating film 105.
  • the metal films 41 and 42 are, for example, a laminated film of a platinum (Pt) film and a gold (Au) film on the platinum (Pt) film.
  • the metal film 41 has a surface 41A facing the side surface 112A of the second semiconductor region 112 with the insulating film 104 interposed therebetween.
  • the metal film 42 has a surface 42A facing the side surface 122A of the second semiconductor region 122 with the insulating film 104 interposed therebetween.
  • the lower surface 41B of the metal film 41 and the lower surface 42B of the metal film 42 have a bonding interface 113 between the first semiconductor region 111 and the second semiconductor region 112 and a bonding interface 123 between the first semiconductor region 121 and the second semiconductor region 122.
  • the metal films 31 and 41 are included in the anode electrode 51, and the anode electrode 51 is in ohmic contact with the second semiconductor region 112.
  • the metal films 32 and 42 are included in the anode electrode 52, and the anode electrode 52 is in ohmic contact with the second semiconductor region 122.
  • the anode electrodes 51 and 52 are examples of the second electrode.
  • the surfaces 41A and 42A are examples of the first surface.
  • the organic insulating film 105, the insulating film 104, and the insulating film 103 are connected to an opening 71 that reaches a region connected to the first semiconductor region 111 of the n-type semiconductor layer 102 and a first semiconductor region 121 of the n-type semiconductor layer 102.
  • An opening 72 is formed to reach the region to be formed.
  • a cathode electrode 61 that contacts the n-type semiconductor layer 102 through the opening 71 and a cathode electrode 62 that contacts the n-type semiconductor layer 102 through the opening 72 are formed on the organic insulating film 105.
  • the metal films 41 and 42 are, for example, a laminated film of a gold germanium (AuGe) film and a gold (Au) film on the gold germanium (AuGe) film.
  • the cathode electrodes 61 and 62 are examples of the first electrode.
  • FIG. 2 is a cross-sectional view showing a semiconductor device 100 according to the first embodiment during operation.
  • FIG. 3 is a diagram showing voltage-current characteristics of the first nanowire 11 and the second nanowire 12.
  • the diameter of the second semiconductor region 112 is larger than the diameter of the second semiconductor region 122. Therefore, when the thicknesses of the depletion layers 114 and 124 are about the same, the ratio of the depletion layer 114 occupying the second semiconductor region 112 in the radial direction is the ratio of the depletion layer 124 occupying the second semiconductor region 122 in the radial direction. Is smaller than Therefore, as shown in FIG. 3, the voltage-current characteristic of the first nanowire 11 and the voltage-current characteristic of the second nanowire 12 are different. That is, the non-linear characteristics differ between the first nanowire 11 and the second nanowire 12. For example, the first nanowire 11 functions as an esaki diode and exhibits an S-shaped characteristic including a negative resistance component, whereas the second nanowire 12 exhibits a simple rectifying characteristic.
  • the thickness of the insulating film 104 is preferably 10 nm or more and 30 nm or less, and more preferably 10 nm or more and 20 nm or less. If the insulating film 104 is too thin, it may not be possible to sufficiently secure the insulating property between the second semiconductor region 112 and the metal film 41 and the insulating property between the second semiconductor region 122 and the metal film 42. If the insulating film 104 is too thick, the depletion layers 114 and 124 may not be sufficiently formed.
  • 4 to 12 are cross-sectional views showing a method of manufacturing the semiconductor device 100 according to the first embodiment.
  • the n-type semiconductor layer 102 is formed on the substrate 101.
  • the n-type semiconductor layer 102 can be grown by, for example, a metal organic chemical vapor deposition (MOCVD) method.
  • MOCVD metal organic chemical vapor deposition
  • the insulating film 103 is formed on the n-type semiconductor layer 102.
  • openings 21 and 22 are formed in the insulating film 103.
  • the openings 21 and 22 can be formed, for example, by forming a mask by lithography and etching the insulating film 103 using the mask.
  • the diameters of the openings 21 and 22 are 40 nm to 200 nm, and the diameter of the openings 21 is larger than the diameter of the openings 22.
  • a catalyst for nanowires for example, a disk-shaped metal film 31 is formed in the opening 21, and for example, a disk-shaped metal film 32 is formed in the opening 22.
  • gold (Au) is used as the material of the metal films 31 and 32.
  • a substrate for crystal growth including the substrate 101, the n-type semiconductor layer 102, the insulating film 103, the metal film 31 and the metal film 32 can be obtained.
  • the insulating film 103 in which the openings 21 and 22 are formed is an example of a growth mask.
  • first semiconductor regions 111 and 121 composed of n-type GaAs and having the shape of nanowires are grown above the substrate 101.
  • the first semiconductor region 111 is grown from the inside of the opening 21, and the first semiconductor region 121 is grown from the inside of the opening 22.
  • the first semiconductor regions 111 and 121 can be grown by, for example, the MOCVD method.
  • the growth temperature is 400 ° C. to 450 ° C.
  • the heights (lengths) of the first semiconductor regions 111 and 121 are 0.5 ⁇ m to 0.7 ⁇ m.
  • TMGa triethyl gallium
  • arsine (AsH 3 ) is used as a raw material for As.
  • raw materials used hydrogen sulfide (H 2 S) in n-type impurity is doped with sulfur (S) as n-type impurity.
  • S sulfur
  • the S concentration is, for example, 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 20 cm -3 .
  • the compositions of the first semiconductor regions 111 and 121 are equal to each other, and the concentrations of n-type impurities contained in the first semiconductor regions 111 and 121 are also equal to each other.
  • the second semiconductor regions 112 and 122 which are composed of p-type GaAsSb and have the shape of nanowires, are grown above the substrate 101.
  • the second semiconductor region 112 grows on the first semiconductor region 111
  • the second semiconductor region 122 grows on the first semiconductor region 121.
  • the second semiconductor regions 112 and 122 can be grown by the MOCVD method in the same manner as the first semiconductor regions 111 and 121.
  • the growth temperature is 400 ° C. to 450 ° C.
  • the heights (lengths) of the second semiconductor regions 112 and 122 are 1.0 ⁇ m to 1.5 ⁇ m.
  • triethyl gallium (TEGa) is used as a raw material for Ga
  • arsine (AsH 3 ) is used as a raw material for As
  • trimethylantimony (TMSb) is used as a raw material for Sb.
  • diethylzinc (DEZn) is used as a raw material for p-type impurities
  • Zn is doped as p-type impurities.
  • the Zn concentration is, for example, 1 ⁇ 10 18 cm -3 to 1 ⁇ 10 20 cm -3 .
  • the compositions of the second semiconductor regions 112 and 122 are equal to each other, and the concentrations of p-type impurities contained in the second semiconductor regions 112 and 122 are also equal to each other.
  • the first nanowire 11 having the first semiconductor region 111 and the second semiconductor region 112 and the second nanowire 12 having the first semiconductor region 121 and the second semiconductor region 122 are obtained.
  • the diameter of the first nanowire 11 is larger than the diameter of the second nanowire 12.
  • an insulating film 104 covering the first nanowire 11, the second nanowire 12, and the insulating film 103 is formed.
  • the insulating film 104 for example, an aluminum oxide film or a hafnium oxide film having a thickness of 10 nm to 30 nm, preferably 10 nm to 20 nm is formed.
  • the insulating film 104 can be formed, for example, by an atomic layer deposition (ALD) method.
  • the element separation groove 109 is formed in the insulating film 104, the insulating film 103, and the n-type semiconductor layer 102.
  • the element separation groove 109 is formed so as to separate the n-type semiconductor layer 102 into a region connected to the first nanowire 11 and a region connected to the second nanowire 12.
  • the element separation groove 109 can be formed, for example, by forming a mask by lithography and etching the insulating film 104, the insulating film 103, and the n-type semiconductor layer 102 using the mask.
  • the organic insulating film 105 is formed on the insulating film 104 while filling the element separation groove 109.
  • the organic insulating film 105 is preferably formed with a thickness such that the entire upper surface thereof is located above the tops of the metal films 31 and 32.
  • a BCB film is formed as the organic insulating film 105.
  • the organic insulating film 105 is dry-etched until its upper surface is thick enough to be located about 300 nm below the tops of the first nanowire 11 and the second nanowire 12.
  • a mixed gas of carbon tetrafluoride (CF 4 ) and oxygen (O 2) can be used for dry etching.
  • the portion of the insulating film 104 that covers the metal films 31 and 32 is also removed by utilizing the difference in etching rate between the organic insulating film 105 and the insulating film 104.
  • the portion covering the metal films 31 and 32 of the insulating film 104 cannot be sufficiently removed during the dry etching of the organic insulating film 105, the metal films 31 and 32 of the insulating film 104 are subjected to the dry etching of the organic insulating film 105.
  • the portion covering the above may be removed by, for example, ion sputtering using argon (Ar) ions.
  • a metal film 41 in contact with the metal film 31 and a metal film 42 in contact with the metal film 32 are formed on the organic insulating film 105.
  • the metal films 31 and 32 for example, a platinum (Pt) film and a laminated film with a gold (Au) film on the platinum (Pt) film are formed.
  • the metal films 31 and 41 are included in the anode electrode 51, and the metal films 32 and 42 are included in the anode electrode 52.
  • the organic insulating film 105, the insulating film 104, and the insulating film 103 have an opening 71 reaching a region connected to the first semiconductor region 111 of the n-type semiconductor layer 102, and an n-type semiconductor. It forms an opening 72 that reaches a region connected to the first semiconductor region 121 of the layer 102.
  • the openings 71 and 72 can be formed, for example, by forming a mask by lithography and etching the organic insulating film 105, the insulating film 104, and the insulating film 103 using the mask.
  • the insulating film 104 and the insulating film 103 may be removed by, for example, ion sputtering using argon (Ar) ions.
  • the cathode electrode 61 that contacts the n-type semiconductor layer 102 through the opening 71 and the cathode electrode 62 that contacts the n-type semiconductor layer 102 through the opening 72 are formed on the organic insulating film 105.
  • the metal films 41 and 42 for example, a laminated film of a gold germanium (AuGe) film and a gold (Au) film on the gold germanium (AuGe) film is formed.
  • the semiconductor device 100 according to the first embodiment can be manufactured.
  • this method it is possible to easily manufacture a semiconductor device 100 in which a plurality of nanowires (first nanowires 11 and second nanowires 12) having different voltage-current characteristics are arranged with a high degree of integration. Therefore, a plurality of nonlinear elements having different nonlinear characteristics can be arranged with a high degree of integration.
  • first nanowire 11 and the second nanowire 12 are provided above the substrate 101, but a larger number of nanowires may be provided.
  • the first semiconductor regions 111 and 121 do not have to have the shape of nanowires, but the second semiconductor regions 112 and 121 having the shape of nanowires when the first semiconductor regions 111 and 121 have the shape of nanowires. It is easy to form 122.
  • FIG. 13 is a diagram showing voltage-current characteristics of nanowires having various second semiconductor regions having different diameters.
  • FIG. 13 shows the voltage-current characteristics of a nanowire having a second semiconductor region with a diameter d of 20 nm to 200 nm, where p-type impurities are doped at a concentration of 5 ⁇ 10 17 cm -3.
  • the diameter region in which the forward current transitions from the microampere order to the nanoampere order the forward tunnel current can be greatly changed, and various non-linear elements can be prepared together. From this point of view, in the example shown in FIG. 13, the diameter is preferably about 60 nm to 200 nm.
  • the voltage-current characteristics of the first nanowire 11 and the second nanowire 12 include not only the diameters of the second semiconductor regions 112 and 122 but also the doping concentration of p-type impurities contained in the second semiconductor regions 112 and 122 (hereinafter, doping concentration). It also changes according to (sometimes).
  • doping concentration the doping concentration of p-type impurities contained in the second semiconductor regions 112 and 122
  • FIG. 14 is a diagram showing voltage-current characteristics of nanowires having various second semiconductor regions having different doping concentrations.
  • FIG. 14 shows the voltage-current characteristics of a nanowire having a second semiconductor region with a diameter of 60 nm and a doping concentration ⁇ of 1 ⁇ 10 17 cm -3 to 5 ⁇ 10 18 cm -3.
  • the doping concentration is preferably about 5 ⁇ 10 17 cm -3 to 5 ⁇ 10 18 cm -3.
  • the diameter d in the equation (1) is the diameter on the upper surface of the second semiconductor region. ..
  • the second embodiment relates to a reservoir circuit including a plurality of nanowires having different non-linear characteristics.
  • the reservoir circuit is an example of a semiconductor device.
  • 15 and 16 are diagrams showing a reservoir circuit according to the second embodiment.
  • FIG. 15 is a circuit diagram showing the connection relationship of a plurality of nanowires
  • FIG. 16 is a cross-sectional view showing the connection relationship of the plurality of nanowires. In FIG. 16, some configurations such as an insulating film are omitted.
  • the reservoir circuit 200 includes a substrate 101, an n-type semiconductor layer 102, a plurality of nanowires 20, wiring 233, wiring 234, wiring 235, and wiring 236. , Has an input terminal 231 and an output terminal 232.
  • the nanowire 20 has an n-type first semiconductor region 201 and a p-type second semiconductor region 202.
  • the first semiconductor region 201 is provided on the n-type semiconductor layer 102 and extends upward.
  • the second semiconductor region 202 is provided on the first semiconductor region 201 and extends upward.
  • the diameters differ among the plurality of nanowires 20. The diameters need not be different among all the nanowires 20, and may include nanowires 20 having the same diameter.
  • the n-type semiconductor layer 102 is element-separated for each nanowire 20.
  • a plurality of nanowires 20 are arranged at equal intervals in two directions (X direction and Y direction) orthogonal to each other. That is, the plurality of nanowires 20 are arranged above the substrate 101 in a grid pattern in a plan view.
  • the number of input terminals 231 and output terminals 232 is the same as the number of rows composed of a plurality of nanowires 20 arranged in the X direction.
  • the wiring 233 connects the input terminal 231 and the second semiconductor region 202 of the nanowires 20 located at one end of the plurality of nanowires 20 arranged in the X direction.
  • the wiring 234 connects the output terminal 232 and the n-type semiconductor layer 102 connected to the first semiconductor region 201 of the nanowires 20 located at the other end of the plurality of nanowires 20 arranged in the X direction.
  • the wiring 235 connects the n-type semiconductor layer 102 connected to one first semiconductor region 201 and the other second semiconductor region 202 between two nanowires 20 adjacent to each other in the X direction.
  • the wiring 236 connects one second semiconductor region 202 and the other second semiconductor region 202 between two nanowires 20 adjacent to each other in the Y direction.
  • a part of the wiring 233 and a part of the wiring 236 function as an anode electrode, and a part of the wiring 234 functions as a cathode electrode.
  • a part of the wiring 235 functions as an anode electrode, and a part of the wiring 235 functions as a cathode electrode.
  • the portion of the wiring 233, 235, and 236 that functions as the anode electrode has a surface facing the side surface of the second semiconductor region 202 with the insulating film 204 interposed therebetween, as in the metal films 41 and 42 in the first embodiment. It is configured as follows.
  • a plurality of nanowires 20 having different non-linear characteristics are connected in a network shape. Therefore, the reservoir circuit 200 including a plurality of non-linear elements having various non-linear characteristics with a high degree of integration can be obtained. Further, even if the material and composition are the same among the plurality of nanowires 20, if the diameters are different, the non-linear characteristics are different, so that the nanowires can be manufactured without complicated processing.
  • nanowires 20 of 6 ⁇ 6 are shown in FIG. 15, it is preferable that a larger number of nanowires 20 are provided.
  • FIG. 17 is a diagram showing a reservoir circuit according to a modified example of the second embodiment.
  • FIG. 17 is a circuit diagram showing a connection relationship between a plurality of nanowires.
  • the wiring 235 is not provided in a part of the pair of nanowires 20 adjacent to each other in the X direction. Further, wiring 236 is not provided in a part of a pair of nanowires 20 adjacent to each other in the Y direction.
  • the irregularity of the network of nonlinear elements can be made higher than that of the reservoir circuit 200 according to the second embodiment.
  • a plurality of second semiconductor regions are connected via wiring, or the first semiconductor region and the second semiconductor region are connected via wiring.
  • a plurality of first semiconductor regions may be connected.
  • a third embodiment relates to a reservoir circuit including a plurality of nanowires having different non-linear characteristics and including a variable weighting circuit.
  • the reservoir circuit is an example of a semiconductor device.
  • 18 and 19 are diagrams showing a reservoir circuit according to the third embodiment.
  • FIG. 18 is a circuit diagram showing the connection relationship of a plurality of nanowires
  • FIG. 19 is a cross-sectional view showing the connection relationship of the plurality of nanowires. In FIG. 19, some configurations such as an insulating film are omitted.
  • the reservoir circuit 300 includes a substrate 101, an n-type semiconductor layer 102, a plurality of nanowires 20, wiring 233, wiring 234, wiring 235, and wiring 236. , Wiring 237, variable weighting circuit 238, input terminal 231 and output terminal 232.
  • the substrate 101, the n-type semiconductor layer 102, the plurality of nanowires 20, the wiring 233, the wiring 235, and the wiring 236 are configured in the same manner as in the second embodiment.
  • the variable weighting circuit 238 includes an oxide memristor 239 provided for each row composed of a plurality of nanowires 20 arranged in the X direction.
  • the wiring 234 connects one end of the oxide memristor 239 and the n-type semiconductor layer 102 connected to the first semiconductor region 201 of the nanowires 20 located at the other end of the plurality of nanowires 20 arranged in the X direction. Connecting.
  • the wiring 237 connects the output terminal 232 and the n-type semiconductor layer 102 to which the other end of the oxide memristor 239 is connected.
  • the oxide memristor 239 is an example of an analog memory.
  • the resistance of the oxide memristor 239 changes according to the current (signal strength) output from the plurality of nanowires 20 through the wiring 234, and the weight information is held in the variable weighting circuit 238. Will be done.
  • the reservoir circuit 300 according to the third embodiment corresponds to a device that integrates up to linear readout in a reservoir computing system.
  • FIG. 20 is a block diagram showing a reservoir computing system according to the fourth embodiment.
  • the reservoir computing system 400 includes an input circuit 401, a reservoir circuit 402, and an output circuit 403.
  • the reservoir circuit 402 includes a read-to-weight unit 404.
  • the reservoir computing system 400 may further include a learning data circuit 405.
  • the reservoir circuit 402 the reservoir circuit 200 or 300 may be used.
  • learning data (teacher data) is input from the learning data circuit 405 to the read weighting unit 404, and the read weighting unit 404 is adjusted so that appropriate weighting is performed.
  • the read weighting unit 404 is an example of an analog memory.
  • the learning data circuit 405 is disconnected from the reservoir circuit 402. Then, data is input from the input circuit 401 to the reservoir circuit 402, and in the reservoir circuit 402, arithmetic processing such as weighting by the read-out weighting unit 404 is performed on the input data. The result of the arithmetic processing in the reservoir circuit 402 is output from the output circuit 403.
  • nanowires which are a plurality of non-linear elements included in the reservoir computing system 400, can be arranged with a high degree of integration.

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PCT/JP2020/016567 2020-04-15 2020-04-15 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 Ceased WO2021210095A1 (ja)

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EP20931249.5A EP4138141A4 (en) 2020-04-15 2020-04-15 SEMICONDUCTOR DEVICE, RESERVOIR COMPUTER SYSTEM AND METHOD OF MAKING A SEMICONDUCTOR DEVICE
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