CN115428166B - 半导体装置、储层计算系统以及半导体装置的制造方法 - Google Patents

半导体装置、储层计算系统以及半导体装置的制造方法

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Publication number
CN115428166B
CN115428166B CN202080099700.4A CN202080099700A CN115428166B CN 115428166 B CN115428166 B CN 115428166B CN 202080099700 A CN202080099700 A CN 202080099700A CN 115428166 B CN115428166 B CN 115428166B
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semiconductor region
semiconductor
insulating film
semiconductor device
nanowire
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CN115428166A (zh
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河口研一
高桥刚
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Fujitsu Ltd
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Fujitsu Ltd
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    • H10D8/00Diodes
    • H10D8/70Tunnel-effect diodes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/044Recurrent networks, e.g. Hopfield networks
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/117Shapes of semiconductor bodies
    • H10D62/118Nanostructure semiconductor bodies
    • H10D62/119Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/122Nanowire, nanosheet or nanotube semiconductor bodies oriented at angles to substrates, e.g. perpendicular to substrates
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    • H10D8/00Diodes
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    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
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    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
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    • H10D84/204Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/221Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
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    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
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    • H10P14/27Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
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    • H10P14/272Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using mask materials other than SiO2 or SiN
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    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
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    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
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    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3451Structure
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  • Electrodes Of Semiconductors (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN202080099700.4A 2020-04-15 2020-04-15 半导体装置、储层计算系统以及半导体装置的制造方法 Active CN115428166B (zh)

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PCT/JP2020/016567 WO2021210095A1 (ja) 2020-04-15 2020-04-15 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法

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US (1) US12363968B2 (https=)
EP (1) EP4138141A4 (https=)
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US12592279B2 (en) * 2022-06-28 2026-03-31 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Neural network hardware device and system

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GB9421138D0 (en) * 1994-10-20 1994-12-07 Hitachi Europ Ltd Memory device
US7335908B2 (en) * 2002-07-08 2008-02-26 Qunano Ab Nanostructures and methods for manufacturing the same
JP2008511985A (ja) * 2004-08-31 2008-04-17 エージェンシー フォー サイエンス,テクノロジー アンド リサーチ ナノ構造体及びそれを製造する方法
WO2010062644A2 (en) * 2008-10-28 2010-06-03 The Regents Of The University Of California Vertical group iii-v nanowires on si, heterostructures, flexible arrays and fabrication
JP5652827B2 (ja) * 2009-09-30 2015-01-14 国立大学法人北海道大学 トンネル電界効果トランジスタおよびその製造方法
KR20120099441A (ko) * 2009-10-22 2012-09-10 솔 발테익스 에이비 나노와이어 터널 다이오드 및 이의 제조 방법
EP2378557B1 (en) 2010-04-19 2015-12-23 Imec Method of manufacturing a vertical TFET
CA2864212A1 (en) * 2011-02-10 2012-08-16 The Royal Institution For The Advancement Of Learning/Mcgill University High efficiency broadband semiconductor nanowire devices and methods of fabricating without foreign metal catalysis
CN104603952B (zh) 2012-07-06 2017-07-21 昆南诺股份有限公司 径向纳米线江崎二极管装置和方法
US9012883B2 (en) * 2012-12-21 2015-04-21 Sol Voltaics Ab Recessed contact to semiconductor nanowires
US9730596B2 (en) * 2013-06-28 2017-08-15 Stmicroelectronics, Inc. Low power biological sensing system
DE102016013749A1 (de) * 2016-11-18 2018-05-24 Azur Space Solar Power Gmbh Stapelförmige Halbleiterstruktur

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US12363968B2 (en) 2025-07-15
US20230015231A1 (en) 2023-01-19
WO2021210095A1 (ja) 2021-10-21
JPWO2021210095A1 (https=) 2021-10-21
JP7384273B2 (ja) 2023-11-21
EP4138141A4 (en) 2023-06-07
EP4138141A1 (en) 2023-02-22
CN115428166A (zh) 2022-12-02

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