JP7384273B2 - 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 - Google Patents
半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP7384273B2 JP7384273B2 JP2022514920A JP2022514920A JP7384273B2 JP 7384273 B2 JP7384273 B2 JP 7384273B2 JP 2022514920 A JP2022514920 A JP 2022514920A JP 2022514920 A JP2022514920 A JP 2022514920A JP 7384273 B2 JP7384273 B2 JP 7384273B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- semiconductor
- insulating film
- nanowire
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/70—Tunnel-effect diodes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/044—Recurrent networks, e.g. Hopfield networks
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
- H10D62/118—Nanostructure semiconductor bodies
- H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
- H10D62/122—Nanowire, nanosheet or nanotube semiconductor bodies oriented at angles to substrates, e.g. perpendicular to substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/053—Manufacture or treatment of heterojunction diodes or of tunnel diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/70—Tunnel-effect diodes
- H10D8/75—Tunnel-effect PN diodes, e.g. Esaki diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
- H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
- H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
- H10P14/272—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using mask materials other than SiO2 or SiN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3421—Arsenides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3422—Antimonides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3441—Conductivity type
- H10P14/3442—N-type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3441—Conductivity type
- H10P14/3444—P-type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3451—Structure
- H10P14/3452—Microstructure
- H10P14/3462—Nanowires
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Biomedical Technology (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biophysics (AREA)
- General Health & Medical Sciences (AREA)
- Software Systems (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Artificial Intelligence (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Neurology (AREA)
- Electrodes Of Semiconductors (AREA)
- Nanotechnology (AREA)
- Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2020/016567 WO2021210095A1 (ja) | 2020-04-15 | 2020-04-15 | 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2021210095A1 JPWO2021210095A1 (https=) | 2021-10-21 |
| JPWO2021210095A5 JPWO2021210095A5 (https=) | 2022-12-02 |
| JP7384273B2 true JP7384273B2 (ja) | 2023-11-21 |
Family
ID=78083574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022514920A Active JP7384273B2 (ja) | 2020-04-15 | 2020-04-15 | 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US12363968B2 (https=) |
| EP (1) | EP4138141A4 (https=) |
| JP (1) | JP7384273B2 (https=) |
| CN (1) | CN115428166B (https=) |
| WO (1) | WO2021210095A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12592279B2 (en) * | 2022-06-28 | 2026-03-31 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Neural network hardware device and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008511985A (ja) | 2004-08-31 | 2008-04-17 | エージェンシー フォー サイエンス,テクノロジー アンド リサーチ | ナノ構造体及びそれを製造する方法 |
| JP2013508966A (ja) | 2009-10-22 | 2013-03-07 | ソル ヴォルタイクス アーベー | ナノワイヤトンネルダイオードおよびその製造方法 |
| JP2016510943A (ja) | 2012-12-21 | 2016-04-11 | ソル ヴォルテイックス エービーSol Voltaics Ab | 半導体ナノワイヤへの凹んだコンタクト |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9421138D0 (en) * | 1994-10-20 | 1994-12-07 | Hitachi Europ Ltd | Memory device |
| US7335908B2 (en) * | 2002-07-08 | 2008-02-26 | Qunano Ab | Nanostructures and methods for manufacturing the same |
| WO2010062644A2 (en) * | 2008-10-28 | 2010-06-03 | The Regents Of The University Of California | Vertical group iii-v nanowires on si, heterostructures, flexible arrays and fabrication |
| JP5652827B2 (ja) * | 2009-09-30 | 2015-01-14 | 国立大学法人北海道大学 | トンネル電界効果トランジスタおよびその製造方法 |
| EP2378557B1 (en) | 2010-04-19 | 2015-12-23 | Imec | Method of manufacturing a vertical TFET |
| CA2864212A1 (en) * | 2011-02-10 | 2012-08-16 | The Royal Institution For The Advancement Of Learning/Mcgill University | High efficiency broadband semiconductor nanowire devices and methods of fabricating without foreign metal catalysis |
| CN104603952B (zh) | 2012-07-06 | 2017-07-21 | 昆南诺股份有限公司 | 径向纳米线江崎二极管装置和方法 |
| US9730596B2 (en) * | 2013-06-28 | 2017-08-15 | Stmicroelectronics, Inc. | Low power biological sensing system |
| DE102016013749A1 (de) * | 2016-11-18 | 2018-05-24 | Azur Space Solar Power Gmbh | Stapelförmige Halbleiterstruktur |
-
2020
- 2020-04-15 WO PCT/JP2020/016567 patent/WO2021210095A1/ja not_active Ceased
- 2020-04-15 CN CN202080099700.4A patent/CN115428166B/zh active Active
- 2020-04-15 EP EP20931249.5A patent/EP4138141A4/en active Pending
- 2020-04-15 JP JP2022514920A patent/JP7384273B2/ja active Active
-
2022
- 2022-09-28 US US17/954,385 patent/US12363968B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008511985A (ja) | 2004-08-31 | 2008-04-17 | エージェンシー フォー サイエンス,テクノロジー アンド リサーチ | ナノ構造体及びそれを製造する方法 |
| JP2013508966A (ja) | 2009-10-22 | 2013-03-07 | ソル ヴォルタイクス アーベー | ナノワイヤトンネルダイオードおよびその製造方法 |
| JP2016510943A (ja) | 2012-12-21 | 2016-04-11 | ソル ヴォルテイックス エービーSol Voltaics Ab | 半導体ナノワイヤへの凹んだコンタクト |
Non-Patent Citations (2)
| Title |
|---|
| Ganjipour et al.,High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires,NANO LETTERS,11,米国,American Chemical Society,2011年09月06日,pp.4222-4226,dx.doi.org/10.1021/nl202180b |
| HU et al.,MultilayerRTD-memristor-basedcellularneuralnetworksforcolor imageprocessing,Neurocomputing,ND,ELSEVIER,2015年05月04日,Vol.162,pp.150-162,dx.doi.org/10.1016/j.neucom.2015.03.057 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115428166B (zh) | 2026-04-14 |
| US12363968B2 (en) | 2025-07-15 |
| US20230015231A1 (en) | 2023-01-19 |
| WO2021210095A1 (ja) | 2021-10-21 |
| JPWO2021210095A1 (https=) | 2021-10-21 |
| EP4138141A4 (en) | 2023-06-07 |
| EP4138141A1 (en) | 2023-02-22 |
| CN115428166A (zh) | 2022-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6528370B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP7384273B2 (ja) | 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法 | |
| KR920010671B1 (ko) | 반도체장치 | |
| US4794444A (en) | Ohmic contact and method for making same | |
| JP6970338B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
| JPS6095966A (ja) | ヘテロ接合バイポ−ラトランジスタとその製造方法 | |
| KR20210032240A (ko) | 부성미분저항 소자 제조방법 | |
| JP2001332565A (ja) | 負性微分抵抗素子およびその製造方法 | |
| JP2701583B2 (ja) | トンネルトランジスタ及びその製造方法 | |
| CN224124491U (zh) | 增强模式高电子迁移率晶体管器件 | |
| US4811070A (en) | Heterojunction bipolar transistor with inversion layer base | |
| JPH0230182B2 (https=) | ||
| CN104409506B (zh) | 量子点场效应晶体管及制作方法、阵列基板和检测装置 | |
| US20230246100A1 (en) | Enhancement-mode hemt and manufacturing process of the same | |
| JP4714959B2 (ja) | 半導体装置とその製造方法 | |
| JPH10107274A (ja) | トンネルトランジスタ及びその製造方法 | |
| JPH07297408A (ja) | トンネルトランジスタおよびその製造方法 | |
| JPH0243765A (ja) | 化合物半導体装置の製造方法 | |
| JPS639983A (ja) | 高速半導体装置 | |
| JPS61241972A (ja) | 化合物半導体装置 | |
| CN120500088A (zh) | 一种叠层沟道混合接触薄膜晶体管及其制备方法 | |
| JPS63304665A (ja) | 半導体装置 | |
| JPH01179457A (ja) | 接合型電界効果トランジスタ及びその製造方法 | |
| JPS61144882A (ja) | 半導体装置およびその製造方法 | |
| JPH01223773A (ja) | 電界効果トランジスタ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220926 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20220926 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20230613 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20230807 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20231010 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20231023 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 7384273 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |