JP2015529006A - 径方向ナノワイヤエサキダイオードデバイスおよび方法 - Google Patents
径方向ナノワイヤエサキダイオードデバイスおよび方法 Download PDFInfo
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- JP2015529006A JP2015529006A JP2015519381A JP2015519381A JP2015529006A JP 2015529006 A JP2015529006 A JP 2015529006A JP 2015519381 A JP2015519381 A JP 2015519381A JP 2015519381 A JP2015519381 A JP 2015519381A JP 2015529006 A JP2015529006 A JP 2015529006A
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Abstract
Description
Claims (27)
- 径方向ナノワイヤエサキダイオードを備えるデバイスであって、前記径方向ナノワイヤが第1の導電型の半導体コア、および前記第1の導電型と異なる第2の導電型の半導体シェルを備える、デバイス。
- ゲート制御された径方向ナノワイヤエサキダイオードを備える、請求項1に記載のデバイス。
- トンネリング電界効果トランジスタ(TFET)を備える、請求項2に記載のデバイス。
- 前記シェルのまわりに位置するゲート絶縁層、および前記ゲート絶縁層に隣接して位置するゲート電極をさらに備える、請求項3に記載のデバイス。
- 前記コアと前記シェル間のトンネル電流の方向が前記ナノワイヤを支持する基板の主表面と実質的に平行である、請求項4に記載のデバイス。
- 前記コアと前記シェル間のトンネル電流の方向が前記ナノワイヤおよび前記ゲート絶縁層に面する前記ゲート電極の表面と実質的に垂直である、請求項4に記載のデバイス。
- 前記コアと前記シェル間のトンネル電流の方向が前記ナノワイヤを支持する基板の主表面と実質的に平行であり、前記ナノワイヤおよび前記ゲート絶縁層に面する前記ゲート電極の表面に実質的に垂直である、請求項4に記載のデバイス。
- 前記コアと前記シェル間のトンネル電流の方向がゲート電界の方向と実質的に平行である、請求項2に記載のデバイス。
- 前記ナノワイヤコアが、第1のドーピング濃度を有する前記第1の導電型の下方の半導体部分、および前記下方部分上に位置する上方部分を備え、
前記上方部分が、電気的絶縁材料、または前記下方部分の前記第1のドーピング濃度よりも低く、前記シェルのドーピング濃度よりも低い第2のドーピング濃度を有する半導体材料を含み、
前記コアの前記下方部分が前記第1の導電型の半導体ソース領域と電気的に接触し、前記シェルが前記第2の導電型のドレイン領域と電気的に接触し、
前記シェルが前記コアの前記上方部分に隣接して位置し、pn接合を形成するように前記コアの前記下方部分と少なくとも部分的にオーバーラップし、
前記ゲート電極が前記pn接合と少なくとも部分的にオーバーラップする、
請求項4に記載のデバイス。 - 前記シェルが前記ゲート絶縁層と前記コア間に量子井戸を形成するのに十分に薄い、請求項4に記載のデバイス。
- 前記コアおよび前記シェルの少なくとも1つが前記デバイス中の電荷キャリヤのエネルギーを増加させるのに十分に薄い、請求項10に記載のデバイス。
- 前記コアと前記TFETのソース領域およびドレイン領域の少なくとも1つとの間に位置するバリア領域をさらに備える、請求項4に記載のデバイス。
- 前記バリア領域の材料が前記半導体コアの材料よりも高いバンドギャップを有する、請求項12に記載のデバイス。
- 前記バリア領域の材料が前記半導体コアの材料および前記半導体シェルの材料の両方よりも高いバンドギャップを有し、
前記バリア領域が漏れ電流を抑えるために伝導帯端および価電子帯エッジの両方で十分に高いバンドオフセットを有するプラグ形の領域を備え、
前記バリア領域が、電気的絶縁材料、あるいは1016cm-3以下のドーピング濃度を有する軽くドープされた、真性の、または半絶縁性半導体材料を備える、
請求項13に記載のデバイス。 - 太陽電池を備える、請求項1に記載のデバイス。
- 前記太陽電池が前記径方向ナノワイヤエサキダイオードに加えて平面状太陽電池を含むマルチ接合太陽電池を備える、請求項15に記載のデバイス。
- 前記ダイオードが前記平面状太陽電池の上面に直立する、請求項16に記載のデバイス。
- 前記平面状太陽電池がシリコンpn接合を備え、前記エサキダイオードがIII−V半導体pn接合を備える、請求項17に記載のデバイス。
- 径方向半導体ナノワイヤを備えるゲート制御されたエサキダイオードを動作させる方法であって、前記径方向半導体ナノワイヤの反対にドープされたコアとシェル間のトンネル電流が、ゲート電極によって前記径方向半導体ナノワイヤに提供される電界と実質的に平行に流れる、方法。
- 前記コアが第1の導電型の半導体コアを備え、前記シェルが前記第1の導電型と異なる第2の導電型の半導体シェルを備える、請求項19に記載の方法。
- 前記シェルのまわりに位置するゲート絶縁層、および前記ゲート絶縁層に隣接して位置する前記ゲート電極をさらに備える、請求項20に記載の方法。
- 前記コアと前記シェル間の前記トンネル電流が前記ナノワイヤを支持する基板の主表面と実質的に平行に流れる、請求項21に記載の方法。
- 前記コアと前記シェル間の前記トンネル電流が前記ナノワイヤおよび前記ゲート絶縁層に面する前記ゲート電極の表面と実質的に垂直に流れる、請求項21に記載の方法。
- 前記コアと前記シェル間の前記トンネル電流が前記ナノワイヤを支持する前記基板の主表面と実質的に平行に流れ、前記コアと前記シェル間の前記トンネル電流が前記ナノワイヤおよび前記ゲート絶縁層に面する前記ゲート電極の表面と実質的に垂直に流れる、請求項21に記載の方法。
- 前記ゲート制御されたエサキダイオードがTFETを備える、請求項21に記載の方法。
- 前記ナノワイヤコアが、第1のドーピング濃度を有する前記第1の導電型の下方の半導体部分および前記下方部分上に位置する上方部分を備え、
前記上方部分が、電気的絶縁材料、または下方部分の前記第1のドーピング濃度よりも低く、前記シェルのドーピング濃度よりも低い第2のドーピング濃度を有する半導体材料を含み、
前記コアの前記下方部分が、前記第1の導電型の半導体ソース領域と電気的に接触し、前記シェルが前記第2の導電型のドレイン領域と電気的に接触し、
前記シェルが前記コアの前記上方部分に隣接して位置し、pn接合を形成するように前記コアの前記下方部分と少なくとも部分的にオーバーラップし
前記ゲート電極が前記pn接合と少なくとも部分的にオーバーラップする、
請求項25に記載の方法。 - 前記コアの前記上方部分が、印加されたソースドレイン間電界と平行なトンネルキャリヤの大きな横方向の生成を阻止し、
前記ゲート電極が、ソースドレイン間およびゲート電界を含む前記pn接合を横切る全電界が、前記pn接合と本質的に垂直となるように、前記pn接合に垂直な電界を提供し、
フェルミ準位が前記pn接合の両面で実質的に一定であり、
前記pn接合を横切るフェルミ準位の実質的に階段状に誘起される変化が、60mV/dec未満のサブスレッショルドスイングを提供するサブサーマルなトンネルキャリヤの生成を提供する、
請求項26に記載の方法。
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