CN104603952A - 径向纳米线江崎二极管装置和方法 - Google Patents

径向纳米线江崎二极管装置和方法 Download PDF

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CN104603952A
CN104603952A CN201380036099.4A CN201380036099A CN104603952A CN 104603952 A CN104603952 A CN 104603952A CN 201380036099 A CN201380036099 A CN 201380036099A CN 104603952 A CN104603952 A CN 104603952A
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core
shell
semiconductor
nano wire
gate electrode
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CN104603952B (zh
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L-E.维尔纳松
E.林德
J.奥尔松
L.萨米尔松
M.比约克
C.舍兰德
A.迪
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BTG International Ltd
QuNano AB
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Abstract

径向纳米线二极管装置包括第一导电类型的半导体芯和不同于第一导电类型的第二导电类型的半导体壳。该装置可以是TFET或太阳能电池。

Description

径向纳米线江崎二极管装置和方法
背景技术
呈栅控江崎二极管（例如，具有负电阻特征和/或以反向或齐纳方向操作的栅控二极管）形式的隧道或隧穿场效晶体管（“TFET”）目前被认为用于在VDD< 0.3V操作的数字应用。这些晶体管的主要优点在于可能使用在晶体管低于kT/q发热限制而操作的情况下的陡斜率，以减小的栅极摆幅（gate swing），减小断开电流。晶体管操作依靠带通效应，其中，基于经由晶体管栅极控制的跨能带隙的隧穿（例如，电子从n型半导体材料的导带隧穿到pn结的相邻p型半导体材料的价带内）获得驱动电流。因为能带隙阻挡了载流子的直接隧穿，则由有限数量的可用状态而减小了断开电流。
隧道晶体管的主要优点包括驱动电流，即在接通状态相反亚阈值斜率（或亚阈值摆幅）的电流水平以及限定晶体管可能如何准确地断开的断开状态电流。断开状态对于TFET而言通常不成问题，因为断开状态电流由pn结的反向泄漏电流决定。通常，已知难以在亚阈值区域获得高驱动电流以及陡斜率。问题的部分涉及需要栅电极与pn结准确对准，其中未对准将减轻栅效应并且降低跨结的电场。在结的任一侧上的高掺杂水平将增加驱动电流，但另一方面，高掺杂水平将使反亚阈值斜率降级，这是由于在能带隙中引入带尾状态。陡斜率隧道装置的重要方面是参与隧穿的热激励载流子量；在结附近感应的任何可能的空穴将引入热载流子群（经由费米-狄拉克函数）。如果由那些载流子供应隧穿，亚阈值摆幅立即降级到最佳地60 毫伏/十进位（mV/decade）（热注入载流子的理论极限）。这通常是TFET装置的情况。
还已知江崎二极管优选地利用具有小的有效质量的材料制成以增加隧穿电流/隧道电流（tunneling current）并且异质结构优选地用以增加驱动电流，一个示例是InAs/GaSb。另一问题是Dit效应，其将增加斜率并且特别地对于异质结构装置而言，识别并且处理与不同半导体材料兼容的高k电介质是有挑战性的。
发明内容
在一实施例中，一种包括径向纳米线江崎二极管的装置，其中径向纳米线包括第一导电类型的半导体芯和不同于第一导电类型的第二导电类型的半导体壳。
在一实施例中，该装置包括栅控江崎二极管（例如，TFET），其包括径向半导体纳米线。在径向半导体纳米线的相反掺杂芯与壳之间的隧穿电流基本上平行于由栅电极提供给径向半导体纳米线的电场而流动。
在另一实施例中，该装置包括多结太阳能电池，多结太阳能电池包括平面太阳能电池和所述径向纳米线江崎二极管。
附图说明
图1A和图1B分别是沿着线B'-B和A'-A的径向纳米线TFET装置的相应顶视和侧视截面图。图1C为图1A和图1B的装置的能带图。
图2示出了TFET的替代实施例的侧视截面图。
图3为径向和轴向TFET的漏电流（漏极到源极电流）与栅极电压（栅极到源极电压）关系的模拟曲线图。
图4和图5分别为径向和轴向TFET的漏极电流（漏极到源极电流）与栅极电压（栅极到源极电压）关系的模拟曲线图。
图6至图7为径向TFET的尺寸曲线图以及图8至图9为轴向TFET的尺寸曲线图。
图10A和图10B分别为包含轴向和径向纳米线的模拟TFET的右侧部分的侧视截面图，其分别用于图4、图6、图7和图5、图8、图9的相应模拟。
图10C示出了图10B所示的结构的示例性实施例。
图11A至图11D为本发明的实施例的多结太阳能电池的侧视截面图。
图12A和图12B为根据本发明的一实施例，作为温度函数的电流与电压关系和PVCR与温度关系的相应曲线图，以示出江崎二极管的温度相关性电流-电压特征。
具体实施方式
本发明的实施例是基于包括所谓的纳米线的纳米结构。对于本申请的目的，纳米线被解释为在它们的宽度和直径方面具有纳米尺寸并且通常具有细长形状。这种结构通常也被称作纳米须、纳米杆、纳米管、一维纳米元件等。
优选地，纳米线基本上为杆形半导体结构，具有小于1微米的直径，诸如50mm或更小和多达数微米的长度。纳米线在其基部处连接到基板，基板可包括在纳米线下方的外延半导体层。
熟知的是通过粒子辅助生长或所谓的VLS（气-液-固）机制在基板上形成纳米线的基本工艺（描述于美国专利No. 7,335,908，其以全文引用的方式并入到本文中）以及不同类型的化学束外延和气相外延方法。然而，本发明并不限于这种纳米线也不限于这种VLS工艺。
在本领域中已知用于生长纳米线的其它合适方法并且例如在美国专利No. 7,829,443中示出，该专利以全文引用的方式并入到本文中。由此得出可以不使用粒子作为催化剂来生长纳米线。
纳米线穿过生长掩模中的开口而突伸，诸如由氮化硅制成的掩模或另一绝缘层。通过首先在基板上设置生长掩模并且在生长掩模中产生开口来生长纳米线。开口优选地在它们的直径和它们的相对定位方面受到良好控制。在本领域中已知的若干技术可以用于这个过程，包括（但不限于）电子束光刻（EBL）、纳米压印光刻、光学光刻和反应性离子蚀刻（RIE）或湿式化学蚀刻方法。优选地，开口具有大约100nm直径并且以0.5-5μm间距间隔开。开口限定待生产的纳米线的位置和直径。半导体纳米线芯然后通过基于CVD的工艺而生长。然后可以围绕芯形成径向半导体壳。
因此，也可包括选择性地生长的纳米线和纳米结构、蚀刻结构、其它纳米线、和由纳米线制成的结构。
纳米线沿着其径向方向（或者对于当从顶部观看时具有非圆形截面的纳米线而言，宽度方向）并不均匀。纳米尺寸不仅能允许在不存在有与纳米线材料匹配的晶格的基板上生长，而且也可以在纳米线中设置异质结构。（多个）异质结构包括与纳米线的一个或多个相邻壳部分不同组成的半导体材料芯。（多个）壳异质结构区段的材料可以具有与芯不同的组成和/或掺杂。异质结可以是突然的或缓变的。
本发明的一实施例提供一种纳米线TFET装置（例如，栅控江崎二极管）其中隧穿电流在纳米线结构的径向方向上流动并且其中围栅用于控制电流流动，使得栅电场基本上平行于隧穿电流流动。在一实施例中，在纳米线二极管的n型部分与p型部分之间的隧穿电流基本上平行于（例如，在平行的0-20度内）支承着纳米线的主基板表面和/或基本上垂直于（例如，在垂直的20度内）朝向纳米线和位于纳米线与栅电极之间的栅绝缘层的栅电极表面而流动。这允许同时调制电位以及电场，电位和电场都有助于构成跨二极管的p-n或p-i-n结的电流。
在具有不同大多数载流子的纳米线的两个区段（诸如，p型芯与n型壳或反之亦然）之间调制了在径向隧穿场效晶体管中的隧穿电流。当通过热激励载流子的运输最少并且载流子运输主要受直接隧穿机制支配时获得最大隧穿运输效率。所提到的装置将着重于/加强了隧穿贡献并且限制了其它贡献，诸如热激励的载流子和在偏置条件下的扩散性运输。还可以由在源极与漏极中的载流子库之间引入的屏障来进一步提高在前述贡献之间的比例。屏障或“插塞”可包括高能带隙半导体或缓变半导体并且起到最小化垂直于从栅极施加的电场的泄漏电流的目的，栅极被定位成使得主导隧穿电流平行于由栅极施加的电场。
图1A至图1C示出了根据本发明的一实施的TFET。纳米线优选地包括断裂或交错的能隙p-n结，诸如由高-k栅介质和围栅包围的(Al)GaSb/InAs(Sb)径向异质结构。具体而言，纳米线1生长于n型源极区域3上，诸如在基板上的n型InAs层和/或在基板中的n型掺杂InAs区域。纳米线包括n型InAsSb纳米线杆和与源极区域接触的径向壳部5和p型AlGaSb纳米线上芯部7。栅绝缘层，诸如高k电介质层（例如，二氧化铪、氧化铝、氧化钽等）9包围所述壳5。栅电极11邻近于栅绝缘层9而定位，使得栅绝缘层9夹在栅电极11与纳米线壳5之间。优选地，但并非必需地，栅电极11为中空圆柱形围栅，其完全包围栅绝缘层9，如图1A所示。替代地，栅电极11可以邻近于栅绝缘层的一个或多个部分定位，而不是完全包围栅绝缘层。P型GaSb漏极区域13被定位成在纳米线1的上部处与芯7接触。源电极和漏电极（为了清楚起见未图示）与相应源极3区域和漏极13区域接触。若需要，在纳米线1外侧的单独源极区域3和/或漏极区域13可以被省略并且源电极和漏电极可以直接接触纳米线1的相应区域5和7，相应区域5和7将会充当TFET的相应源极区域和漏极区域。而且，n型区域和p型区域的位置在二极管中可以颠倒并且可以使用任何其它合适半导体材料来代替上文所描述的材料。在一特定替代实施例中，纳米线芯包括由p-型(Al)GaSb壳包围的n型InAsSb芯。在此实施例中，不仅掺杂类型颠倒，相对应的材料也颠倒。任何其它合适材料可以用于芯和壳，由GaAsSb、GalnAs、InP和/或 InPAs例示，但不限于这些。在优选但非限制性实施例中，在芯/壳异质结构中的材料选择提供了交错的材料能带对准，其中导带和价带不连续中的任一个或二者(ΔEc, ΔΕv)在0.5与1.5 Eg之间，其中Eg为带隙能量（例如，以eV为单位）。换言之，0.5Eg <ΔEc < 1.5Eg，或者0.5Eg <ΔEv < 1.5Eg，如图1C所示。而且，通过缩放芯/壳尺寸比例到量子范围（quantum regime）而可实现带结构工程设计，其允许精确地控制能带对准。此外，载流子运输可以由在受约束半导体中形成的离散能量水平所控制，允许可用于运输的载流子的高度选择性。上述考虑可以用于本文所描述的任何和/或全部实施例装置。
如图1A至图1C所示，来自栅电极11的电场15沿着隧穿电流17的方向在区域5与区域7之间定向。因此，在纳米线二极管的n型5部分和p型7部分之间的隧穿电流17方向基本上平行于支承着纳米线的主基板表面3a和/或基本上垂直于朝向纳米线1和栅绝缘层9的栅电极11的表面11a。如本文所用的，在相反方向的流动（即，即，芯至壳与壳到芯）被认为是平行的。
优选地，InAsSb层5被制成充分薄使得量子阱形成于栅绝缘层9与芯7之间。这可以允许晶体管以量子电容极限操作。换言之，在InAsSb层5中的电位由来自周围栅电极11的电位调制。
在一非限制性配置中，壳层5充分薄以在量子阱中形成量子化状态，这有效地增加了载流子的能量。在一实施例中，量子化能量大于在断裂能带异质结构中导带与价带之间的能量差异。这有效地分别在n侧和p侧中的最低能量状态之间引入能量分离，充当甚至用于具有断裂带隙能带对准的材料组合的隧穿屏障。在再一实施例中，芯被制成充分薄以形成量子化状态，量子化状态以类似方式增加了能量。
在一实施例中，InAs(Sb)层5与(Al)GaSb层7充分较薄（例如，总厚度低于20nm，诸如总厚度2-15 nm）以最小化隧道距离并且由此增加隧道电流。在一实施例中，缓变掺杂分布可以存在于芯7中，从到杆5A的界面处的低掺杂到朝向漏极13的更高掺杂，以便维持均匀压降，和继而在整个隧穿区上的均匀隧穿电流（在壳5与芯7之间的界面）。换言之，掺杂在该装置的竖直方向上缓变，其中在该装置的底部部分中的掺杂浓度低于顶部部分中的掺杂浓度。
图1B所示的装置可以根据以下方法制造。首先，InAs(Sb)纳米线杆5A生长于源极区域3上。然后，轴向(Al)GaSb异质结构（即，上纳米线芯部）7生长于杆5A上。随后通过形成掩膜层9A，诸如由绝缘层（例如，SiNx、HSQ、SiO2等）来保护所得到的纳米线（例如，杆5A部分）的底部部分。InAs(Sb)的壳5然后生长于纳米线上，覆盖纳米线的外侧，除了受到掩膜层9A保护杆5A的底部部分之外。这形成被覆盖有径向 InAsSb壳5的InAs(Sb) 5A /(Al)GaSb 7轴向异质结构纳米线芯。栅绝缘层9和围栅电极11然后形成于径向纳米线周围。
图2示出了径向纳米线TFET的替代实施例。该装置包括：至少一根纳米线1，纳米线1包括生长于基板上的纳米线芯7和布置于芯7上并且至少部分地包围纳米线芯5以提供径向异质结构纳米线的至少第一壳层5。芯7和壳5优选地由相反导电类型（例如，如果芯7是p型，那么壳5是n型，并且反之亦然）半导体材料制成以形成pn结。若需要，可选的本征壳层可以位于芯7与壳5之间以形成pin结。栅绝缘层9位于壳5周围并且栅电极11邻近于栅绝缘层9定位，诸如围绕着栅绝缘层9。径向纳米线1的芯7（例如，n型芯）可能被定位成与基板中的相同导电类型半导体源极区域3（例如，n型区域）接触。源电极19可以定位成与区域3接触并漏电极21可以定位成与壳5接触。若需要，相同导电类型（例如，p型）的可选的半导体漏极区域13（例如，另一壳层或类似块体球形物（quasi-bulk bulb））可以被定位成与壳5接触，在此情况下，漏电极21接触漏极区域13。可选的夹层绝缘层（未图示）可以分隔栅电极9与源电极19和漏电极21。应当指出的是若需要，下文所描述的屏障“插塞”区域7B和/或上文所描述的缓变芯掺杂也可以添加到图2的装置。
本发明的实施例的一个非限制性优点是电场沿着隧穿电流方向定向并且晶体管无需依靠场效果或损耗。另一优点在于高k材料9将仅接触一种半导体材料（例如，区域5），这简化了材料整合。另一优点在于栅控二极管并不需要与任何异质结构的任何临界对准。另一优点在于电流密度可能较高并且晶体管形成为呈三维阵列。最终，该装置并不需要轴向装置那样强烈的直径缩放，因为临界尺寸由在侧部小平面上侧向过度生长来设置。
图3为关于径向和轴向TFET的漏极电流（漏极到源极电流）与栅极电压（栅极到源极电压）关系的模拟曲线图。图4和图5为关于相应径向和轴向TFET的漏极电流（漏极到源极电流）与栅极电压（栅极到源极电压）关系的模拟曲线图。图6至图7为本发明的实施例的径向TFET的尺寸曲线图并且图8至图9为比较示例的轴向TFET的尺寸曲线图。非局部隧穿速率在图7中被示出在径向纳米线壳中并且在图9中被示出在轴向纳米线中p-n结附近。图10A和图10B分别为包含轴向和径向纳米线的模拟TFET的右侧部分的侧视截面图，其分别用于图4、图6、图7和图5、图8、图9中的相应模拟。换言之，图10A和图10B仅示出了在竖直对称轴线右边的纳米线的右侧。
图10A所示的模拟轴向纳米线包含了在源极区域3上的下部p型半导体轴向部分8和上部n型半导体轴向部分6。高k氧化物栅绝缘层9包围纳米线的两个部分6、8并且围栅电极11被定位成邻近于纳米线的上部6与栅绝缘层9接触。漏极区域13定位于部分6上方。部分6和8形成TFET的pn结。纳米线半径为25nm，部分6包括n型InAs，具有10 17 cm -3 的供体掺杂浓度ND，并且部分8包括p型(Al)GaSb，p型(Al)GaSb具有1018 cm-3的受体掺杂浓度NA。栅绝缘层包括具有5 nm厚度和εr=25的高k氧化物层。
图10B示出的模拟径向纳米线包含芯7，芯7包括在源极区域3上的下部p型半导体部分7A和上部轻度掺杂的n型半导体部分（例如，屏障部分）7B。重度掺杂的n型壳5位于芯7周围，使得壳5环绕上部7B以及下部7A的至少顶部部分以形成TFET的pn结。高k氧化物栅绝缘层9包围壳5并且围栅电极11被定位成邻近于壳5与栅绝缘层9接触。夹层绝缘层10（其可以具有图1C所示的掩模层9A相同或不同形式）将栅电极11和壳5与源极区域3分离开。漏极区域13定位于部分6上。纳米线芯7半径为25nm，并且纳米线壳5半径为10nm，使得整个半导体纳米线具有35nm半径。壳5包括n型InAs，具有10 17 cm -3的供体掺杂浓度ND，并且下芯部7A包括p型(Al)GaSb，p型(Al)GaSb具有1018 cm-3的受体掺杂浓度NA。上芯部7B是可选的并且包括n型InP，n型InP具有1016cm-3的供体掺杂浓度ND。栅绝缘层9包括具有5 nm厚度和εr=25的高k氧化物层。
屏障部分7B设置成保持TFET电流在纳米线的芯7A与壳5之间流动，这通常在水平（例如，径向）方向，沿着栅场，其中竖直方向沿着纳米线芯的轴线。在替代实施例中，部分7B可以由与壳5相同的半导体材料制成，但具有比壳5更低的掺杂浓度。替代地，部分7B可以由电绝缘材料制成或者由不同于壳5的半导体材料制成。在一优选实施例中，屏障部分7B具有比壳5和芯部7A更高的能带隙。在一实施例中，屏障部分7B具有比壳5更高的能带隙和比芯部7A更低的掺杂水平。优选地，除了具有比芯部7A和壳5更大的能带隙之外，屏障部分7B应在导带和价带边缘二者处都具有足够高的偏移，使得屏障可以高效地抑制泄漏电流。因此，屏障部分7B可包括轻度掺杂的本征半绝缘半导体材料，其具有1016 cm-3或更低的掺杂浓度（例如，达到1016 cm-3的不可避免杂质水平）或者其可以包括电绝缘材料。部分7B在径向纳米线装置中可以被称作“插塞”。
因此，如图10B所示，纳米线芯7包括第一（例如，p）导电类型、具有第一（例如，高）掺杂浓度的第一（例如，下）半导体部分7A和邻近于第一部分7A（例如，在第一部分7A上）位于芯中的第二（例如，上）部分7B。壳5由第二（例如，n）导电类型半导体制成。上部7B包括电绝缘材料或具有低于下部7A和壳5的掺杂浓度的第二掺杂浓度的电绝缘材料或半导体材料。芯的下部7A电接触第一（例如，p）导电类型的半导体源极区域3并且壳电接触第二导电类型的漏极区域13。壳5邻近于芯的上部7B定位并且与芯的下部7A至少部分地重叠以形成pn结。栅电极11至少部分地与pn结重叠。P侧电极（为了清楚起见未图示）电接触所述源3而n侧电极（为了清楚起见未图示）电接触所述漏极区域13。导电类型（例如，p和n）可以颠倒并且不同于上文所描述那些的其它材料可以用于替代实施例中。
图10C示出了在图10B中示意性地示出的装置的结构的一实施例。径向隧穿场效晶体管或栅控江崎二极管包括径向半导体纳米线。在壳5与芯7之间在纳米线中调制了隧穿电流，壳5与芯7具有相反大多数载流子，诸如p型芯和n型壳或反之亦然。芯/壳可以生长在与壳5相同导电类型的半导体的杆5A顶部上，例如，InAs的n型杆将会例如适合于n-InAs壳。优选地，芯7将会包括阻挡屏障7B用于在杆5A与芯部7A之间的轴向泄漏电流。阻挡屏障7B可以实施为呈高能带隙半导体区段的形式，或者实施为缓变掺杂分布，其可以继续到部分7A内，并且在与芯部7A相同的材料中。引入屏障区段7B将会实现增加如上文所描述的径向-轴向隧穿电流比的目的。
优选地，源电极3和漏电极13将会被形成到纳米线的杆区段5A和芯部7A上。如从杆5A看出，在纳米线的相反端处，在芯/壳区段的一部分上对于壳5的选择性蚀刻将会允许电极直接形成到芯部7A上。使电流在杆5A和/或壳5与芯部7A之间传递将会导致隧穿电流，其中有源隧穿界面将会定位在介于芯部7A与壳5之间的结处。而且，纳米线将会被包覆在隔离体中，诸如高k电介质或氧化物9中，可能由原子层沉积来沉积隔离体以用于适形（conformal）覆盖。第三电极11将会用于调制在芯部7A与壳5之间的隧穿电流，在如上文所描述的全环栅/全包围栅（gate-all-around）装置架构中，第三电极11放置于有源隧穿结上，由隔离体9与壳5分离开，与相邻区段（例如，7B）具有或不具有部分重叠（overlap）或欠重叠/负重叠（underlap）。因此，第三电极（栅极）11将会施加与在芯部7A与壳5之间的隧穿电流平行的电场。
上文所描述的装置提供径向隧穿场效晶体管，其中，主导隧穿电流在具有不同的大多数载流子的纳米线的两个区段之间受调制，诸如，p型GaSb芯7和n型InAs壳5或反之亦然。该装置向电流提供径向隧穿贡献并且限制来自热激励载流子的贡献和偏置条件下的扩散运输。在前文提到的贡献之间的比例由引入于源极与漏极中的载流子库之间的屏障7B增加，其中源极3可以是与连接到n型 InAs壳5的n型InAs纳米线杆5A串联的n型InAs缓冲层，并且漏极可以是连接到金属电极13的全部或部分p型GaSb芯7A。屏障或“插塞”7B可包括高能带隙半导体，诸如GaAs或InP，或缓变半导体并且最小化了与从栅极施加的电场垂直的泄漏电流，其中栅极被定位成使得主导隧穿电流平行于由栅极施加的电场，即径向隧穿。
在图3至图9中的模拟使用了非局部隧穿模型，仅考虑在栅极区域处的直接隧穿。不希望受特定理论限制，本发明者假定这应合理地准确预测接通电流以及亚阈值斜率（SS），不存在能使反亚阈值斜率降级的任何缺陷/声子辅助的隧穿。也省略了负偏压（negative bias）的任何双极性（ambipolarity）。
在图4所示的轴向纳米线TFET的模拟中，欠重叠表示栅电极11并未以附图中提到的量到达纳米线的(Al)GaSb下部8（即，栅电极位于pn结上方）。部分重叠表示栅电极11以图4中提到的量到达纳米线的(Al)GaSb下部8（即，栅电极在pn结下方延伸）。在图5所示的径向纳米线TFET的模拟中，欠重叠表示栅电极11并未到达InAs壳5的端部（即，底部），而部分重叠表示栅电极11到达InAs壳5下方。
模拟装置示出了约7 毫伏/十进位(mV/ decade)的类似最小SS，其中十进位对应于漏极电流的10倍增加。然而，图10A的轴向TFET在栅欠重叠或部分重叠的情况下严重降级。相比而言，图10B的径向TFET对于欠重叠和部分重叠效应具有更好的免疫性，这将允许更牢靠得多的制造方案，因为栅电极可以被设计成与壳具有某些量的部分重叠或欠重叠。
图10B中所示的装置为优选实施例。与现有技术相比，这些结构提供以下优点。上纳米线“插塞”部分7B阻挡了隧道载流子的常用较大侧向降级（平行于施加的源极-漏极场）。具有漏极接触件13以及GaSb芯部7A的壳5提供很陡的径向pn结（断裂或交错带隙对准），取决于芯直径和壳厚度、掺杂水平和材料组成（例如，Sb和Al的量）。围栅11强加了垂直于pn结的场使得跨越所述结的总电场（源极-漏极和栅极场）基本上垂直于pn-结；这最小化了电位降低（在元件5至7A方向上，在穿过该结构的整个截面上，电位的竖直部分是恒定的）并且因此费米能阶在结的两侧上几乎恒定。场的平行部分包括源-漏电位。以此方式感应的跨越所述结的费米能阶中的几乎逐步变化允许实现提供亚60 mV/dec亚阈值摆幅和高隧道电流的载流子的亚热隧道生成。
本发明的另一实施例提供在江崎二极管中的极性反转，其可以用于形成多结太阳能电池。如图11A所示，太阳能电池101包括了在平面太阳能电池131上表面132上直立的平面pn或pin结太阳能电池131部分和径向江崎二极管1部分。具体而言，二极管1的纵向轴线可以垂直于平面太阳能电池131的上表面132延伸。
平面太阳能电池可包括第一导电类型（例如，n型）的第一区域（例如，上区域或层）133和第二导电类型（例如，p型）的第二区域（例如，下区域或层）135。区域133和135形成pn结。若需要，本征层可以位于区域133与135之间以形成pin结。
第二区域135可以包括掺杂半导体基板、在半导体基板中的掺杂区域或者形成于半导体上的掺杂半导体层、导电（例如，金属）或绝缘（例如，陶瓷、塑料、玻璃、石英等）基板（为了清楚起见未图示）。第一区域133可以包括在半导体基板中的掺杂区域或者在第二区域135上所形成的掺杂半导体层。区域133和135可以包括任何类型的半导体，诸如无机半导体，例如IV族（例如，硅、锗、SiGe等）、III-V族（例如，GaAs、InP等）或II- VI族（例如，CdTe等）半导体。例如，区域133可以是n型硅并且区域135可以是p型硅。
平面太阳能电池131的上表面132可以包括电绝缘掩膜层109A，诸如氮化硅、二氧化硅等。优选地，层109A对于太阳能辐射是透明的，特别地具有比在由芯7和壳5所形成的太阳能电池结中吸收的波长更高的波长。纳米线1穿过掩膜层109A中的开口111突伸。
纳米线1芯7可以生长于通过开口111暴露的半导体区域133上，无需使用如上文所描述的催化剂。替代地，纳米线1芯7可以使用金属催化剂粒子或经由选择性区域生长而首先生长在区域133的上表面132上，之后围绕纳米芯形成掩膜层109A并且然后围绕暴露的芯7而生长所述壳5，也如上文所描述那样。
纳米线芯7和平面太阳能电池131的第一区域133彼此接触并且具有相同导电类型（例如，n型）。壳5和平面太阳能电池131的第二区域135并不彼此接触并且具有与芯7和第一区域133的导电类型不同的相同导电类型（例如，p型）。
优选地，图11A所示的结构形成多结平面/纳米线混合太阳能电池的两个pn结，其中纳米线结优选地基于III/V半导体并且基板（例如，平面太阳能电池）结基于Si。芯和壳区域可包括III-V材料，诸如以GaAs/InP为例。
径向纳米线江崎二极管为利用重度掺杂n++/p++芯/壳区域和能带隙异质结构不连续性的“环绕”（例如，周向）异质结构江崎二极管用于改进性能。江崎带通极性反转有利于保留来自高能量带隙纳米线太阳能电池中所激励的载流子的带能量。这也提供用于使江崎二极管面积与结激励体积匹配的优点，以便于促成在结之间的临界电流匹配。这特别地优于使用轴向纳米线江崎二极管。
图11B示出了多结太阳能电池101的另一实施例，其中，壳5包括了在芯7的顶部部分处的球形物或类似块体区域。若需要，额外掩膜层109B可以形成于壳5与第一掩膜层109A之间。
图11C示出了另一实施例多结太阳能电池101，其中芯7包括异质结构，异质结构包含由上文所描述的栅控TFET应用的特殊值的第一导电类型的不同III-V半导体材料、和/或不同掺杂水平而组成的下7C区域和上7D区域。
图11D示出了n侧电极141和p侧电极143到太阳能电池101的连接。在形成n侧（例如，纳米线侧）电极141之前，额外壳层，第一导电类型（例如，n型）的块体或类似块体区域113形成于第二导电类型（例如，p型）壳5上并且与壳5接触。因此，在此实施方式中，在纳米线中的径向顺序将包括（在此型式中）：n++/p++/p/i/n/n+区域，其中第一n++/p++结组成/构成了江崎隧道二极管，P/i/n二极管为有源的、较大能带隙太阳能电池，并且n+层用于提供纳米线太阳能电池的接触表面层。
然后将n侧电极141形成为与区域113接触。如果太阳能电池101的纳米线侧将向太阳能辐射暴露，那么电极141由对于太阳能辐射基本上透明的导电材料（诸如，透明导电氧化物（TCO），例如氧化铟锡、氧化锌等）制成。P侧电极143被形成为与平面太阳能电池131的区域135接触。电极143可以由任何合适金属，诸如Al、Cu、Ti、Ag等和它们的合金制成。
如图11D所示，江崎二极管形成多结太阳能电池101的“第三结”，切换载流子的极性以便将平面和径向结串联而无任何金属接触，任何金属接触将会使能带隙高度为载流子所保留的“局部熵”转移或溢出。
若需要，可以使半导体区域的导电类型颠倒。而且，虽然示出了一根纳米线1，应了解大量（例如，多个）纳米线形成于平面太阳能电池131上，使得（几乎）所有光子被线阵列截留从而使得基板pn结仅向通过具有更高能带隙的纳米线pn结的光子暴露。
图12A和图12B示出了根据本发明的实施例的江崎二极管的温度相关性特征。 图12A为根据温度的电流与电压关系的曲线图并且图12B为PVCR与温度关系的曲线图，其中PVCR为用于径向纳米线江崎二极管的峰与谷电流比例（PVCR=Ipeak/Ivalley）。如在图12A中可以看出，曲线图包括了在4.2K与295K之间所有测量温度的根据电压的电流中的下降（即，谷）。这是负微分电阻和江崎隧穿二极管行为的特征。图12B示出了对于295K和更低的所有测量温度而言PVCR高于10（例如，在大约295K的室温，PVCR大于10，诸如11至14）；并且在更低的温度（例如，低于60K，诸如4.2-30K），PVCR高于100，诸如101至105。
二极管包括n型、重度硫掺杂InP芯和重度Zn掺杂的InGaAs壳。这种材料组合或其它合适材料，在上文描述的任何和/或所有实施例装置中，可以用于芯和壳，由GaAsSb、GalnAs、InP和/或InPAs例示，但不限于这些。而且，通过缩放芯/壳尺寸比例到量子范围而可实现能带结构工程设计，其允许精确地控制能带对准。此外，载流子运输可以受到在受约束半导体中所形成的离散能量水平控制，允许可用于运输的载流子的高度选择性。
提供所公开的实施例的前文的描述以使得本领域技术人员能做出和使用所描述的实施例。对这些实施例的各种修改将对于本领域技术人员显而易见，并且本文所限定的一般原理可以应用于其它实施例，而不偏离本公开的范围。因此，本发明并非预期限于本文所示的实施例，而是与根据所附权利要求和本文所公开的原理和新颖特征一致的最宽的范围。

Claims (27)

1.一种包括径向纳米线江崎二极管的装置，其中所述径向纳米线包括第一导电类型的半导体芯和不同于所述第一导电类型的第二导电类型的半导体壳。
2.根据权利要求1所述的装置，其特征在于，所述装置包括栅控径向纳米线江崎二极管。
3.根据权利要求2所述的装置，其特征在于，所述装置包括隧穿场效晶体管（TFET）。
4.根据权利要求3所述的装置，其特征在于，其还包括：定位于所述壳周围的栅绝缘层和邻近于所述栅绝缘层定位的栅电极。
5.根据权利要求4所述的装置，其特征在于，在所述芯与所述壳之间的隧穿电流方向基本上平行于支承所述纳米线的基板的主表面。
6.根据权利要求4所述的装置，其特征在于，在所述芯与所述壳之间的隧穿电流方向基本上垂直于所述栅电极的表面，所述栅电极朝向所述纳米线和所述栅绝缘层。
7.根据权利要求4所述的装置，其特征在于，在所述芯与所述壳之间的隧穿电流方向基本上平行于支承所述纳米线的基板的主表面并且基本上垂直于朝向所述纳米线和所述栅绝缘层的所述栅电极的表面。
8.根据权利要求2所述的装置，其特征在于，在所述芯与所述壳之间的隧穿电流方向基本上平行于栅电场方向。
9.根据权利要求4所述的装置，其特征在于：
所述纳米线芯包括具有第一掺杂浓度的第一导电类型的下部半导体部和位于所述下部上的上部；
所述上部包括具有比所述下部的所述第一掺杂浓度更低和比所述壳的掺杂浓度更低的第二掺杂浓度的电绝缘材料或半导体材料；
所述芯的所述下部电接触所述第一导电类型的半导体源极区域并且所述壳电接触所述第二导电类型的漏极区域；
所述壳邻近于所述芯的所述上部定位并且至少部分地与所述芯的所述下部重叠以形成pn结；以及
所述栅电极至少部分地与所述pn结重叠。
10.根据权利要求4所述的装置，其特征在于，所述壳充分地薄以在所述栅绝缘层与所述芯之间形成量子阱。
11.根据权利要求10所述的装置，其特征在于，所述芯和所述壳中的至少一个充分地薄以增加所述装置中的电荷载流子的能量。
12.根据权利要求4所述的装置，其特征在于，其还包括：位于所述芯与所述TFET的源极区域和漏极区域中至少一个之间的屏障区域。
13.根据权利要求12所述的装置，其特征在于，所述屏障区域材料具有比所述半导体芯材料更高的能带隙。
14.根据权利要求13所述的装置，其特征在于：
所述屏障区域材料具有比所述半导体芯材料和所述半导体壳材料更高的能带隙；
所述屏障区域包括插塞形区域，所述插塞形区域在导带与价带边缘二者处具有足够高的能带偏移以抑制泄漏电流；以及
所述屏障区域包括电绝缘材料或轻度掺杂的、本征的或半绝缘的半导体材料，其具有1016 cm-3或更低的掺杂浓度。
15.根据权利要求1所述的装置，其特征在于，所述装置包括太阳能电池。
16.根据权利要求15所述的装置，其特征在于，所述太阳能电池包括多结太阳能电池，所述多结太阳能电池除了所述径向纳米线江崎二极管之外还包括平面太阳能电池。
17.根据权利要求16所述的装置，其特征在于，所述二极管直立于所述平面太阳能电池的上表面上。
18.根据权利要求17所述的装置，其特征在于，所述平面太阳能电池包括硅pn结并且所述江崎二极管包括III- V半导体pn结。
19.一种操作包括径向半导体纳米线的栅控江崎二极管的方法，其中在所述径向半导体纳米线的相反地掺杂的芯与壳之间的隧穿电流基本上平行于由栅电极提供给所述径向半导体纳米线的电场而流动。
20.根据权利要求19所述的方法，其特征在于，所述芯包括第一导电类型的半导体芯并且所述壳包括不同于所述第一导电类型的第二导电类型的半导体壳。
21.根据权利要求20所述的方法，其特征在于，其还包括：定位于所述壳周围的栅绝缘层和邻近于所述栅绝缘层而定位的栅电极。
22.根据权利要求21所述的方法，其特征在于，在所述芯与所述壳之间的隧穿电流基本上平行于支承所述纳米线的基板的主表面而流动。
23.根据权利要求21所述的方法，其特征在于，在所述芯与所述壳之间的隧穿电流基本上垂直于朝向所述纳米线和所述栅绝缘层的所述栅电极的表面而流动。
24.根据权利要求21所述的方法，其特征在于，在所述芯与所述壳之间的隧穿电流基本上平行于支承所述纳米线的基板的主表面而流动并且在所述芯与所述壳之间的隧穿电流基本上垂直于朝向所述纳米线和所述栅绝缘层的所述栅电极的表面而流动。
25.根据权利要求21所述的方法，其特征在于，所述栅控江崎二极管包括TFET。
26.根据权利要求25所述的方法，其特征在于：
所述纳米线芯包括具有第一掺杂浓度的第一导电类型的下部半导体部和位于所述下部上的上部；
所述上部包括具有比所述下部的所述第一掺杂浓度更低和比所述壳的掺杂浓度更低的第二掺杂浓度的电绝缘材料或半导体材料；
所述芯的所述下部电接触所述第一导电类型的半导体源极区域并且所述壳电接触所述第二导电类型的漏极区域；
所述壳邻近于所述芯的所述上部定位并且至少部分地与所述芯的所述下部重叠以形成pn结；以及
所述栅电极至少部分地与所述pn结重叠。
27.根据权利要求26所述的方法，其特征在于:
所述芯的上部阻挡平行于所施加的源-漏场的隧道载流子的较大侧向生成；
所述栅电极提供垂直于所述pn结的场使得跨越包括源极-漏极和栅极场的所述pn结的总电场基本上垂直于所述pn结；
费米能阶在所述pn结的两侧上基本上恒定；以及
跨越所述pn结在费米能阶中基本上逐步感应的变化提供载流子的亚热隧道生成，所述载流子的亚热隧道生成提供小于60 mV/dec的亚阈值摆幅。
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