WO2021192040A1 - バイアス回路、並びに、センサ機器及びワイヤレスセンサ機器 - Google Patents

バイアス回路、並びに、センサ機器及びワイヤレスセンサ機器 Download PDF

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Publication number
WO2021192040A1
WO2021192040A1 PCT/JP2020/013038 JP2020013038W WO2021192040A1 WO 2021192040 A1 WO2021192040 A1 WO 2021192040A1 JP 2020013038 W JP2020013038 W JP 2020013038W WO 2021192040 A1 WO2021192040 A1 WO 2021192040A1
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Prior art keywords
node
voltage
circuit
state
bias circuit
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Ceased
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PCT/JP2020/013038
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English (en)
French (fr)
Japanese (ja)
Inventor
友和 小島
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2022509835A priority Critical patent/JP7650860B2/ja
Priority to US17/792,918 priority patent/US11967949B2/en
Priority to DE112020006949.4T priority patent/DE112020006949T5/de
Priority to CN202080098640.4A priority patent/CN115298634B/zh
Priority to PCT/JP2020/013038 priority patent/WO2021192040A1/ja
Publication of WO2021192040A1 publication Critical patent/WO2021192040A1/ja
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0084—Measuring voltage only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

Definitions

  • the present disclosure relates to a bias circuit, and a sensor device and a wireless sensor device provided with the bias circuit.
  • a circuit called a self-bias circuit that generates a bias voltage that does not directly depend on the power supply voltage is known.
  • a bandgap reference circuit for generating a constant reference voltage and current against temperature fluctuations and process fluctuations in addition to power supply voltage fluctuations is also known.
  • Patent Document 1 describes, as an example of such a self-bias circuit, a reference current generation circuit that does not require a PN junction diode and has a temperature dependence of approximately zero. ..
  • a starting circuit including a constant current source is arranged in order to escape from the zero bias point and start at a stable operating point.
  • the present disclosure has been made to solve such problems, and the purpose of the present disclosure is to achieve both stable startability, low power consumption after startup, and high bias accuracy. It is to provide the configuration of the bias circuit.
  • a bias circuit a current mirror circuit having first conductive type first and second transistors, a current generation circuit having a second conductive type transistor, and a start control circuit. And a starter circuit.
  • the first conductive type first and second transistors are connected between the first power supply node that supplies the first voltage and the first and second nodes, respectively.
  • the current generation circuit is connected between the second power supply node that supplies the second voltage and the first and second nodes.
  • the control electrodes of the first and second transistors connected to each other are electrically connected to one of the first and second nodes, at least in the second state.
  • the start circuit switches the connection destination of the control electrode between the first state and the second state when the bias circuit is started.
  • the activation circuit includes first to third switches. The first switch is connected between the control electrode and the first voltage node that supplies the off voltage for turning off the first and second transistors. The second switch is connected between the third node and the control electrode. The third switch is connected between the second voltage node, which supplies the on-voltage for turning on the first and second transistors, and the third node. The first switch and the second switch are turned off in the first state and turned on in the second state. The third switch is turned on in the first state and turned off in the second state.
  • the sensor device includes the bias circuit, the sensor, and the amplifier circuit.
  • the sensor outputs a detection voltage according to the physical quantity to be measured.
  • the bias circuit outputs at least the bias current.
  • the amplifier circuit generates an output voltage based on the voltage detected from the sensor by the amplification operation using the bias current from the bias circuit.
  • the wireless sensor device includes the bias circuit, the sensor, the amplifier circuit, and the wireless communication unit.
  • the sensor outputs a detection voltage according to the physical quantity to be measured.
  • the bias circuit outputs at least the bias current.
  • the amplifier circuit generates an output voltage based on the voltage detected from the sensor by the amplification operation using the bias current from the bias circuit.
  • the wireless communication unit outputs a transmission signal according to a predetermined communication protocol by wireless communication. The transmission signal is generated based on digital data obtained by analog-digital conversion of the output voltage of the amplifier circuit.
  • the current mirror circuit and the current generation circuit are reliably supplied at the time of circuit start. In addition to generating current, no unnecessary current is generated in the start circuit after startup. As a result, it is possible to achieve both stable startability, low power consumption after start-up, and high accuracy of bias.
  • FIG. It is a circuit diagram which shows the structure of the bias circuit which concerns on a comparative example. It is a circuit diagram which shows the structure of the bias circuit which concerns on Embodiment 1.
  • FIG. It is a circuit diagram explaining the 1st configuration example of the start control circuit shown in FIG. It is a waveform diagram explaining the operation of a start control circuit. It is a circuit diagram explaining the 2nd configuration example of the start control circuit shown in FIG. It is a circuit diagram which shows the structure of the bias circuit which concerns on 1st modification of Embodiment 1. It is a circuit diagram which shows the structure of the bias circuit which concerns on the 2nd modification of Embodiment 1. It is a circuit diagram which shows the structure of the bias circuit which concerns on the 3rd modification of Embodiment 1.
  • FIG. 1 is a circuit diagram showing a configuration of a bias circuit according to a comparative example.
  • the bias circuit 100 includes a current generation circuit 110a, a current mirror circuit 120, and a start circuit 200.
  • the current generation circuit 110a and the current mirror circuit 120 are connected in series between the power supply node Nd that supplies the power supply voltage A VDD and the grounding node Ng that supplies the grounding voltage AGND via the nodes N1 and N2.
  • the current mirror circuit 120 has P-type field effect transistors (hereinafter, also simply referred to as “Metal Oxide Semiconductor) transistors” MP1 and MP2.
  • the epitaxial transistor MP1 is connected between the power supply node Nd and the node N1
  • the epitaxial transistor MP2 is connected between the power supply node Nd and the node N2.
  • the gate which is the "control electrode" of the MPa transistors MP1 and MP2, is commonly connected to the node N2.
  • the current generation circuit 110a has N-type field effect transistors (hereinafter, also simply referred to as “MOS FET transistors”) MN1 and MN2, and a resistance element R0.
  • the NMOS transistor MN2 is connected between the node N1 and the grounded node Ng.
  • the NMOS transistor MN1 is connected between the nodes N2 and N3, and the resistance element R0 is connected between the node N3 and the grounded node Ng.
  • the gate (control electrode) of the NMOS transistor MN1 is connected to the node N1, and the gate (control electrode) of the NMOS transistor MN2 is connected to the node N3.
  • the circuit configuration by the current generation circuit 110a and the current mirror circuit 120 is equivalent to the circuit configuration in which the start circuit is excluded from the reference current generation circuit (X2) shown in FIG. 2 of Patent Document 1.
  • the bias circuit 100 further includes an output transistor BP1 and an output transistor BN1 for outputting a bias current.
  • the output transistor BN1 is composed of an NMOS transistor connected between the bias output node No1 and the ground node Ng.
  • the gate of the output transistor BN1 is connected to the node N3.
  • a load for example, a resistor or a MIMO transistor
  • the output transistor BN1 is transferred to the current I2 of the node N2 via the bias output node No1.
  • a proportional reference current IREF1 is output.
  • the output transistor BP1 is composed of a MIMO transistor connected between the power supply node Nd and the bias output node No2.
  • the gate of the output transistor BP1 is connected to the node N2.
  • a load for example, a resistor or an NMOS transistor
  • the output transistor BP1 passes through the bias output node No. 2 to the current I2 of the node N2.
  • a proportional reference current IREF2 is output.
  • the bias circuit 100 can generate the reference currents IREF1 and IREF2, which are proportional to the currents I2 flowing through the nodes N2 and N3, as the bias currents.
  • the operation of the bias circuit 100 in the configuration in which the start circuit 200 is excluded will be described.
  • a voltage higher than the threshold voltage Vt of the NMOS transistor MN2 is generated in the node N3, so that the NMOS transistor MN2 generates a drain current.
  • the voltage of the node N1 rises above the ground voltage AGND, and the voltage of the node N2 falls below the power supply voltage A VDD, so that drain currents are also generated in the NMOS transistors MN1 and the MPa transistors MP1 and MP2. ..
  • the current I2 of the node N2 is represented by the following equation (1) using the above threshold value Vt when the electric resistance value of the resistance element R0 is also expressed as R0.
  • the current I2 Vt / R0 ... (1)
  • the current I2 does not depend on the power supply voltage A VDD. Further, the temperature dependence of the current I2 can be reduced by selecting the resistance element R0 so that the temperature-dependent polarity of the electric resistance value R0 is opposite to the temperature-dependent polarity of the threshold voltage Vt. can.
  • the reference currents IREF1 and IREF2 are proportional to the current I2, that is, (Vt / R0). Therefore, the bias circuit 100 can operate as a self-bias circuit that does not depend on the power supply voltage AVDD and has a small temperature dependence and generates a bias current with high accuracy.
  • the bias circuit 100 in the zero bias state, no voltage is generated at the node N3 (the ground voltage remains AGND), and the gate voltage of the NMOS transistor MN2 is 0 (V), so that the drain current is almost zero. Become. Therefore, the voltage of the node N1 connected to the gate of the NMOS transistor MN1 does not increase, and the drain current of the NMOS transistor MN1 becomes almost zero.
  • the start-up circuit 200 has a MPLS transistor TPJ1 and an NMOS transistors TNJ1 and TNJ2.
  • the MPLS transistor TPJ1 and the NMOS transistor TNJ1 are connected in series between the power supply node Nd and the ground node Ng via the node Ns.
  • the gates of the MOSFET transistor TPJ1 and the NMOS transistor TNJ1 are connected to the node N3.
  • the NMOS transistor TNJ2 is connected between the node N2 and the grounded node Ng.
  • the gate of the NMOS transistor TNJ2 is connected to the node Ns.
  • the MOSFET transistor TPJ1 and the NMOS transistor TNJ1 operate as a CMOS (Complementary MOS) inverter having node N3 as an input node and node Ns as an output node.
  • the NMOS transistor TNJ2 is driven according to the output voltage of the CMOS inverter.
  • the above-mentioned zero bias state occurs when the voltage of the node N3 does not rise from the ground voltage AGND.
  • the epitaxial transistor TPJ1 is fully turned on, so that the voltage of the node Ns rises to the power supply voltage A VDD.
  • the NMOS transistor TNJ2 is fully turned on, the voltage of the node N2 drops to the ground voltage AGND.
  • the gate voltage of the epitaxial transistors MP1 and MP2 drops to the ground voltage AGND, a drain current is generated in the photodiode-connected polyclonal transistor MP2, and a drain current is also generated in the epitaxial transistor MP1 due to the action of the current mirror.
  • the drain current of the MOSFET transistor MP1 causes the voltage of the node N1 to rise, so that the gate voltage of the NMOS transistor MN1 rises.
  • the voltage of the node N3 rises.
  • the start circuit 200 By arranging the start circuit 200 in this way, the voltage of the node N3 can escape from the ground voltage AGND, so that the zero bias state is surely removed and the bias circuit 100 is operated at a stable operating point according to the equation (1). Can be made to.
  • the gate voltage of the NMOS transistor TNJ1 is the same as the gate voltage of the NMOS transistor MN2 through which the current I1 flows. Further, since the gate voltage of the NMOS transistor TPJ1 is also equivalent to Vt of the NMOS transistor MN2, a drain current of the NMOS transistor TPJ1 is generated. As a result, in the start-up circuit 200, in parallel with the supply of the reference currents IREF1 and IREF2 due to the generation of the currents I1 and I2, the current IS1 at the same level as the current I1 is supplied to the power supply via the NMOS transistors TPJ1 and the NMOS transistor TNJ1. It occurs between the node Nd and the grounded node Ng.
  • this current IS1 is a leak current that is originally unnecessary for the bias circuit 100, there is a concern that the power consumption of the bias circuit 100 will increase. Further, when the leak current is added to the currents I1 and I2 due to wraparound, the reference currents IREF1 and IREF2 do not meet the design values based on the current I2 in the equation (1), and the accuracy of the bias current may decrease. I am concerned. That is, in the reference current generation circuit of Patent Document 1 and the comparative example of FIG. 1, there is a concern about the same problem caused by the start-up circuit.
  • circuit configuration of Embodiment 1 In the present embodiment, the configuration of the bias circuit for low power consumption and high bias accuracy, which is characteristic of the configuration of the start circuit, will be described.
  • FIG. 2 is a circuit diagram illustrating the configuration of the bias circuit according to the first embodiment.
  • the bias circuit 101 according to the first embodiment includes a current generation circuit 110a and a current mirror circuit 120 similar to the bias circuit 100 according to the comparative example, a start circuit 130, and a start control circuit 150. To be equipped.
  • Each of the current generation circuit 110a and the current mirror circuit 120 is configured in the same manner as the bias circuit 100 according to the comparative example, and is connected in series between the power supply node Nd and the ground node Ng via the nodes N1 and N2. ing.
  • the start-up control circuit 150 generates start-up control signals POFF and XPOFF based on the level of the power supply voltage A VDD.
  • FIG. 3 shows a circuit diagram illustrating a first configuration example of the start control circuit 150.
  • the start-up control circuit 150x according to the first configuration example includes resistance elements Rd1 to Rd3, diodes D0, a comparator 160, and inverters 162 and 164.
  • the electric resistance values of the resistance elements Rd1 to Rd3 are also referred to as Rd1 to Rd3.
  • the resistance elements Rd1 and Rd2 are directly connected between the power supply node Nd and the grounding node Ng via the node Nx to form a voltage dividing circuit.
  • the resistance element Rd3 is connected between the power supply node and the node Ny.
  • the diode D0 is connected between the node Ny and the grounded node Ng with the direction from the node Ny to the grounded node Ng as the forward direction.
  • the comparator 160 outputs a comparison result between the voltage VNx of the node Nx and the voltage VNy of the node Ny. Specifically, when VNx> VNy, the comparator 160 outputs a logical high level (hereinafter, simply referred to as “H level”) signal, and when VNy> VNx, the comparator 160 outputs a logical low level (hereinafter, simply “L”). (Called "level”) signal is output.
  • H level logical high level
  • L logical low level
  • the inverter 162 inverts the logic level of the output signal of the comparator 160 and outputs the start control signal XPOFF.
  • the voltage VNx represented by the following equation (2) is generated according to the voltage division ratio by the resistance elements RDd and Rd2.
  • VNx A VDD ⁇ Rd2 / (Rd1 + Rd2)... (2)
  • FIG. 4 shows a waveform diagram illustrating the operation of the activation control circuit 150x.
  • the power supply voltage A VDD increases in response to the power supply being turned on at time t0.
  • the power supply voltage A VDD becomes a steady state after time t2.
  • the voltage VNx rises in proportion to the power supply voltage A VDD as shown in the equation (2).
  • the voltage VNy Vf is constant. Therefore, the comparator 160 operates so as to output a comparison result between the voltage VNx and the determination voltage Vr represented by the following equation (3) in an equivalent manner.
  • Vr Vf ⁇ (Rd1 + Rd2) / Rd2 ... (3) Therefore, since the comparator 160 outputs the L level from time t0 to t1 (power-off state) when the power supply voltage A VDD is equal to or less than the determination voltage Vr, the start control signal POFF is the L level and the start control signal XPOFF is the H level. Is set to.
  • the determination voltage Vr can be adjusted in advance so that the bias circuit 101 has a margin with respect to the minimum operating voltage that can be operated.
  • the comparator 160 outputs the H level, so that the start control signal POFF is H level and the start control signal XPOFF is L. Set to level. In this way, the start-up control circuit 150x can generate start-up control signals POFF and XPOFF so as to distinguish between the power-off state and the power-on state according to the power supply voltage A VDD.
  • the power-off state corresponds to the "first state” that continues from before the start of the bias circuit 101, and the power-on state corresponds to the "second state” that transitions from the "first state” with the start. ..
  • FIG. 5 shows a second configuration example of the activation control circuit 150 shown in FIG.
  • the start control circuit 150y includes resistance elements Ra and Rb, polyclonal transistors MPa and MPb, and inverters 170, 172 and 174.
  • the electric resistance values of the resistance elements Ra and Rb are also referred to as Ra and Rb.
  • the MIMO transistor MPa is connected between the power supply node Nd and the node Na, and the MIMO transistor MPb is connected between the power supply node Nd and the node Nb.
  • the resistance element Ra is connected between the node Na and the ground node Ng, and the resistance element Rb is connected between the node Nb and the ground node Ng.
  • the inverter 170 outputs an L level signal when the voltage of the node Nb is lower than the threshold voltage of the inverter 170, and outputs an H level signal when the voltage of the node Nb is higher than the threshold voltage. do.
  • the inverter 172 inverts the logic level of the output signal of the inverter 170 and outputs the start control signal POFF.
  • the inverter 174 inverts the logic level of the output signal (startup control signal POFF) of the inverter 172 and outputs the startup control signal XPOFF.
  • the gate of the MIMO transistor MPa is connected to the node Na, and is further connected to the gate of the MIMO transistor MPb. That is, the MPa transistor MPa is diode-connected, and when the power supply voltage A VDD becomes higher than the absolute value of the threshold voltage Vtp of the MIMO transistor MPa (A VDD >>
  • the drain current Ida in the saturation region can be expressed by the following equation (4).
  • ⁇ V in the equation (4) is an overdrive voltage due to the drain current, and ⁇ V ⁇ 0 in the epitaxial transistor.
  • the MPa transistor MPa operates in the saturation region.
  • the power-off state and the power-on state are distinguished according to the increase in the power supply voltage A VDD.
  • the control signals POFF and XPOFF can be generated.
  • the start-up control circuit 150x in FIG. 3 needs to raise the power supply voltage A VDD to some extent in order to operate the comparator 160 (for example, A VDD ⁇ 1.8 (V)).
  • the comparator 160 op amp
  • the voltage detection accuracy of the start control circuit 150x is higher than that of the start control circuit 150y.
  • the start circuit 130 has at least switches S1 to S3 that are on / off controlled by start control signals POFF and XPOFF.
  • start control signals POFF and XPOFF start control signals
  • the switch S1 is connected between the gate of the epitaxial transistors MP1 and MP2 constituting the current mirror circuit 120 and the node that supplies the gate voltage (hereinafter, “off voltage”) at which the epitaxial transistors MP1 and MP2 are turned off.
  • the switch S1 is composed of the PRIVATE transistors SBP1 connected between the power supply node Nd and the gate of the MPa transistors MP1 and MP2. NS.
  • the power supply node Nd corresponds to one embodiment of the “first voltage node” that supplies the off voltage of the current mirror circuit 120
  • the ground node Ng corresponds to the on voltage of the current mirror circuit 120.
  • the second voltage node corresponds to one embodiment of the "second voltage node” that supplies.
  • Switch S1 is turned on in the power-off state, while it is turned off in the power-on state. Therefore, a start control signal POFF set to the L level in the power-off state and set to the H level in the power-on state is input to the gate of the epitaxial transistor SBP1.
  • the switch S2 is connected between the gate of the MPa transistors MP1 and MP2 and the node N2.
  • the switch S3 is connected between the node N2 and the node that supplies the gate voltage (hereinafter, “on voltage”) at which the epitaxial transistors MP1 and MP2 are turned on. Since the on-voltage of the MOSFET transistors MP1 and MP2 can be the ground voltage AGND, in FIG. 2, the switch S3 is composed of the NMOS transistors SBN3 connected between the ground node Ng and the node N2.
  • Switch S3 is turned on in the power-off state, while it is turned off in the power-on state. Therefore, the start control signal XPOFF, which is set to the H level in the power-off state and set to the L level in the power-on state, is input to the gate of the NMOS transistor SBN3.
  • the switch S2 turns off in the power-off state, but turns on in the power-on state, so it turns on and off complementaryly with the switch S2 and the switch S3. Therefore, the switch S2 can be configured by the NMOS transistor SBP2 in which the start control signal XPOFF common to the NMOS transistor SBN3 is input to the gate.
  • the node N2 is separated from the ground node Ng by turning off the switch S3, and is connected to the gate of the epitaxial transistors MP1 and MP2 by turning on the switch S2. That is, the switch S2 that is turned on can form a path that connects the node N2 and the gates of the MPa transistors MP1 and MP2 (current mirror circuit 120), which is similar to the bias circuit 100 in FIG.
  • the current mirror circuit 120 and the current generation circuit 110a have the same circuit configuration as the bias circuit 100 in FIG. 1 with the start circuit 200 removed.
  • the bias current can be supplied through the output transistors BP1 and BN1 by using the currents I1 and I2.
  • the gate voltage of the epitaxial transistors MP1 and MP2 constituting the current mirror circuit 120 is forced so that a drain current is generated at the transition from the power-off state to the power-on state.
  • the currents I1 and I2 can be reliably generated.
  • an unnecessary current that is not directly related to the currents I1 and I2, such as the current IS1 in the bias circuit of the comparative example of FIG. 1, does not flow in the start circuit 130. As a result, it is possible to achieve both stable start-up characteristics, low power consumption after start-up, and high bias accuracy.
  • the activation circuit 130 may include a switch S4.
  • the switch S4 is connected between the gate of the NMOS transistor MN1 of the current generation circuit 110a and the node that supplies the off voltage of the NMOS transistor. That is, the switch S4 is composed of an NMOS transistor SBN4 connected between the node N1 and the ground node Ng.
  • Switch S4 is turned on in the power-off state, while it is turned off in the power-on state. Therefore, the start control signal XPOFF, which is set to the H level in the power-off state and set to the L level in the power-on state, is input to the gate of the NMOS transistor SBN4.
  • the switch S4 in the power-off state, the path of the current I2 is cut off by both the MPa transistor MP2 and the NMOS transistor MN1. As a result, the effect of suppressing the leak current of the bias circuit 101 in the power-off state is enhanced. Therefore, it is possible to suppress the standby power of the bias circuit 101 in the power-off state.
  • the switch S4 in the power-on state, when the switch S4 is turned off, the NMOS transistor MN1 (and the node N1) is disconnected from the ground node Ng, so that it is understood that the switch S4 does not affect the operation of the bias circuit 101. ..
  • FIG. 2 shows a configuration example in which switches S2 and S3 are connected in series between the gates of the epitaxial transistors MP1 and MP2 and the grounded node Ng (on voltage) via the node N2.
  • switches S2 and S3 can be connected in series via separate and independent nodes.
  • the gates of the MPa transistors MP1 and MP2 and the node N2 are connected in the same manner as in FIG. Will be.
  • the circuit area can be suppressed by effectively utilizing the node N2 as the on-voltage holding node.
  • the power supply node Nd connected to the current mirror circuit 120 corresponds to one embodiment of the “first power supply node”, and the power supply voltage A VDD corresponds to the “first voltage”.
  • the ground node Ng connected to the current generation circuit 110a corresponds to one embodiment of the "second power supply node”, and the ground voltage AGND corresponds to the "second voltage”.
  • the P type corresponds to one embodiment of the "first conductive type”
  • the N type corresponds to one embodiment of the "second conductive type”.
  • the switches S1 to S4 of the start circuit 130 correspond to the "first switch” to the "fourth switch", respectively, and the epitaxial transistors MP1 and MP2 constituting the current mirror circuit 120 correspond to the "first transistor” and the "first transistor”. Each corresponds to one embodiment of the "second transistor”.
  • the NMOS transistor MN1 corresponds to one embodiment of the "third transistor”.
  • the nodes N1 and N2 correspond to one embodiment of the "first node” and the "second node", and in particular, the node N2 connected to the gate of the epitaxial transistors MP1 and MP2 becomes "one node". handle.
  • FIG. 2 illustrates a configuration in which the “third node” in which the on-voltage is held is shared with the node N2 (one node).
  • FIG. 6 is a circuit diagram showing the configuration of the bias circuit 102 according to the first modification of the first embodiment.
  • the bias circuit 102 according to the first modification of the first embodiment is different from the bias circuit 101 according to the first embodiment in that it further includes a capacitor 210. Since the other configurations of the bias circuit 102 are the same as those of the bias circuit 101 (FIG. 2), the detailed description will not be repeated.
  • the capacitor 210 is arranged at the connection node of the switch S2 and the switch S3 to hold the on voltage (ground voltage AGND) of the epitaxial transistors MP1 and MP2 by turning on the switch S3.
  • FIG. 6 FIG. 2
  • the switch S2 is connected between the gates of the epitaxial transistors MP1 and MP2 and the node N2
  • the switch S3 is connected between the node N2 and the grounded node Ng.
  • the capacitor 210 is connected between the node N2 and the grounded node Ng.
  • the gate voltage of the MPa transistors MP1 and MP2 is surely set to the on voltage at the transition from the power-off state to the power-on state, that is, at the timing when the switch S2 changes from off to on.
  • the drain currents of the MPa transistors MP1 and MP2 can be generated more reliably.
  • the bias circuit can be started more reliably, so that the startability can be further improved as compared with the first embodiment.
  • FIG. 7 is a circuit diagram showing the configuration of the bias circuit 103 according to the second modification of the first embodiment.
  • the NMOS transistor MN1 in the current generation circuit 110a is different from the bias circuit 101 according to the first embodiment. The difference is that it is replaced by the transistor MNL1. Since the other configurations of the bias circuit 103 are the same as those of the bias circuit 101 (FIG. 2), the detailed description will not be repeated.
  • the NMOS transistor MNL1 has a smaller threshold voltage than the NMOS transistor MN1.
  • the NMOS transistor MNL1 has a lower absolute value of the threshold voltage than the enhancement type transistor, that is, a so-called low VT transistor (for example, a threshold value).
  • the absolute value of the voltage is about 0.2 (V)).
  • the low VT transistor enhances the absolute value of the threshold voltage by lowering the impurity concentration of the P well or N well or thinning the gate oxide film as compared with the enhancement type transistor.
  • a transistor having a smaller threshold voltage (absolute value) than a normal enhancement type transistor will be simply referred to as “LVT”.
  • the NMOS transistor MNL1 is generated in response to the generation of the drain current of the NMOS transistors MP1 and MP2 at the transition to the power-on state.
  • the LVT can be defined as a transistor having a smaller absolute value of the threshold voltage than the NMOS transistors MN2 and BN1.
  • the startability can be further improved by arranging the LVT.
  • the NMOS transistor MNL1 corresponds to an embodiment of the “third transistor”
  • the NMOS transistor MN2 corresponds to an embodiment of the “fourth transistor”.
  • FIG. 8 is a circuit diagram showing the configuration of the bias circuit 104 according to the third modification of the first embodiment.
  • the bias circuit 104 according to the third modification of the first embodiment further includes a capacitor 210 similar to that of FIG. 6 in addition to the configuration of the bias circuit 103 of FIG. Since the other configurations of the bias circuit 104 are the same as those of the bias circuit 103, the detailed description will not be repeated.
  • the drain currents of the MPa transistors MP1 and MP2 are surely generated by the arrangement of the capacitors 210, and the node N3 by the arrangement of the NMOS transistors MNL1 (LVT).
  • the startability can be further improved in combination with a reliable increase in voltage.
  • Embodiment 2 a modified example of the circuit configuration of the bias circuit, specifically, a modified example of the current generation circuit will be described. As described below, even if the configuration of the bias circuit excluding the start circuit is different, the start circuit 130 described in the first and second embodiments can be applied in common.
  • FIG. 9 is a circuit diagram showing the configuration of the bias circuit 101a according to the first example of the second embodiment.
  • the bias circuit 101a according to the first example of the second embodiment has a different gate connection destination of the output transistor BP1 as compared with the bias circuit 101 according to the first embodiment. Specifically, the gate of the output transistor BP1 is directly connected to the node N2. Since the other configurations of the bias circuit 101a are the same as those of the bias circuit 101 according to the first embodiment, detailed description thereof will not be repeated. Therefore, the current I2 and the reference currents IREF1 and IREF2 are the same as those in the first embodiment (bias circuit 101).
  • a start circuit 130 having switches S1 to S3 (or S1 to S4) can be arranged.
  • the start circuit 130 in the power-off state, when the switch S1 is turned on, the epitaxial transistors MP1 and MP2 are completely turned off, and when the switch S2 is turned off and the switch S3 is turned on, the connection nodes (node N2) of the switches S2 and S3 are turned on.
  • the on-voltage of the epitaxial transistors MP1 and MP2 can be held by utilizing the parasitic capacitance.
  • the switches S1 and S3 are turned off and the switch S2 is turned on, so that the drain current is surely generated in the NMOS transistors MN1 and MN2 of the NMOS transistors MP1 and MP2 and the current generation circuit 110a. be able to.
  • the bias circuit 101a also has the same embodiment as the bias circuit 101 according to the first embodiment by controlling the gate voltage of the MPa transistors MP1 and MP2 during the power-off state and at the transition to the power-on state.
  • the same effect as in 1 can be enjoyed.
  • the switch S4 shown in FIG. 2 can be provided between the gate (that is, the node N1) of the NMOS transistors MN1 and MN2 and the ground node.
  • FIG. 10 is a circuit diagram showing the configuration of the bias circuit 101b according to the second example of the second embodiment.
  • the bias circuit 101b is different from the bias circuit 101a shown in FIG. 9 in that it includes a current generation circuit 110b instead of the current generation circuit 110a.
  • the current generation circuit 110b is connected between the nodes N1 and N2 and the grounding node Ng, similarly to the current generation circuit 110a.
  • the current generation circuit 110b includes the NMOS transistors MN1 and MN2 and the resistance element Rs.
  • the electrical resistance value of the resistance element Rs is also referred to as Rs.
  • an output transistor (SiO) BP having a gate connected to the node N2 is arranged.
  • the output transistor BP connected between the power supply node Nd and the bias output node No. can output the reference current IREF as the bias current.
  • the NMOS transistor MN1 is connected in series with the resistance element Rs between the node N2 and the grounded node Ng.
  • the NMOS transistor MN2 is connected between the node N1 and the grounded node Ng.
  • the gates of the NMOS transistors MN1 and MN2 are both connected to the node N1.
  • the transistor size (current driving force) of the NMOS transistor MN1 is designed to be k times (a real number of k ⁇ 1) that of the transistor of the NMOS transistor MN2.
  • the reference current IREF when each transistor operates in the strong inversion region is calculated by the following equation (5) using the gain coefficient ⁇ , the electric resistance value Rs, and the transistor size ratio k. It is known to be shown.
  • the gain coefficient ⁇ is an element constant determined by the surface average mobility ⁇ of the NMOS transistor MN1, the channel length L, the channel width W, and the gate capacitance Cox per unit area, as shown in the following equation (6). ..
  • the reference current IREF can be expressed by the following equation (7) using the electric resistance value Rs and the transistor size ratio k. Are known.
  • VT ⁇ ⁇ VT ⁇ ln (k) / Rs... (7)
  • VT is a thermal voltage and ⁇ is a sub-threshold constant determined by the process value.
  • ⁇ a sub-threshold constant determined by the process value.
  • thermal voltage VT k ⁇ T / q at the absolute temperature T (k: Boltzmann's coefficient, q: electron charge amount).
  • the node N1 connected to the gates of the NMOS transistors MN1 and NM2 is connected to the power supply node Nd and the ground node Ng via the transistor. Therefore, the arrangement of the start circuit is indispensable for the current generation circuit 110b.
  • the start circuit 130 having switches S1 to S3 can also be applied to the bias circuit 101b in which the current generation circuit 110b and the current mirror circuit 120 are connected to the power supply node Nd and the ground node Ng via the nodes N1 and N2. can.
  • the gate voltage of the epitaxial transistors MP1 and MP2 can be controlled by the start circuit 130 during the power-off state and at the transition to the power-off state. As a result, drain currents can be reliably generated in the MOSFET transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 of the current generation circuit 110b.
  • the bias circuit 101b can also enjoy the same effect as the bias circuit 101 according to the first embodiment. Further, in the bias circuit 101b, the switch S4 shown in FIG. 2 can be provided between the gate (that is, the node N1) of the NMOS transistors MN1 and MN2 and the ground node.
  • FIG. 11 is a circuit diagram showing the configuration of the bias circuit 101c according to the third example of the second embodiment.
  • the bias circuit 101c is different from the bias circuit 101b shown in FIG. 10 in that it includes a current generation circuit 110c instead of the current generation circuit 110b.
  • the current generation circuit 110c is connected between the nodes N1 and N2 and the grounding node Ng, similarly to the current generation circuits 110a and 110b.
  • the current generation circuit 110c includes the NMOS transistors MN1 and MN2 and the resistance element Rs (electrical resistance value Rs).
  • the NMOS transistor MN1 is connected between the node N2 and the grounded node Ng.
  • the resistance element Rs is connected between the node N1 and the node N4.
  • the NMOS transistor MN2 is connected between the node N4 and the grounded node Ng.
  • the gate of the NMOS transistor MN1 is connected to the node N4, and the gate of the NMOS transistor NM2 is connected to the node N1.
  • the transistor size (current driving force) of the NMOS transistor MN1 is k times that of the transistor of the NMOS transistor MN2.
  • the reference current IREF output by the output transistor (SiO) BP is represented by the equation (5) or the equation (7) as in the bias circuit 101b.
  • a bias current can be generated regardless of whether each transistor operates in a strong inversion region or a weak inversion region. Further, in the bias circuit 101c, since the substrate bias effect does not occur, it is possible to improve the accuracy of the bias current as compared with the bias circuit 101b.
  • the start circuit 130 having switches S1 to S3 can also be applied to the bias circuit 101c in which the current generation circuit 110c and the current mirror circuit 120 are connected to the power supply node Nd and the ground node Ng via the nodes N1 and N2. can.
  • the bias circuit 101c also has the bias circuit 101 according to the first embodiment by controlling the gate voltage of the MPa transistors MP1 and MP2 during the power-off state and at the transition to the power-off state by the start circuit 130. A similar effect can be enjoyed. Further, in the bias circuit 101c, the switch S4 shown in FIG. 2 can be provided between the gate (that is, the node N1) of the NMOS transistors MN1 and MN2 and the ground node.
  • FIG. 12 is a circuit diagram showing the configuration of the bias circuit 101d according to the fourth example of the second embodiment.
  • the bias circuit 101d differs from the bias circuit 101b shown in FIG. 10 in that it includes a current generation circuit 110d instead of the current generation circuit 110b.
  • the current generation circuit 110d is connected between the nodes N1 and N2 and the grounding node Ng, similarly to the current generation circuits 110a to 110c.
  • the current generation circuit 110d includes NMOS transistors MN1 to MN3 and resistance elements Rs (electrical resistance value Rs).
  • the NMOS transistor MN1 is connected between the node N2 and the node N3, and the resistance element Rs is connected between the node N3 and the ground node Ng.
  • the NMOS transistor MN2 is connected between the node N1 and the node N4, and the NMOS transistor MN3 is connected between the node N4 and the ground node Ng.
  • the gates of the NMOS transistors MN1 and NM2 are connected to the node N1.
  • the gate of the NMOS transistor MN3 is connected to the node N4.
  • the NMOS transistors MN2 and MN3 connected between the node N1 and the grounded node Ng are diode-connected, so that the amplification stage is only the NMOS transistor MN1. Therefore, the bias circuit 101d can operate more stably than the bias circuits 101 and 101a, and phase compensation becomes unnecessary.
  • the start circuit 130 having switches S1 to S3 can also be applied to the bias circuit 101d in which the current generation circuit 110d and the current mirror circuit 120 are connected to the power supply node Nd and the ground node Ng via the nodes N1 and N2. can.
  • the bias circuit 101d also has the bias circuit 101 according to the first embodiment by controlling the gate voltage of the MPa transistors MP1 and MP2 during the power-off state and at the transition to the power-off state by the start circuit 130. A similar effect can be enjoyed. Further, in the bias circuit 101b, the switch S4 shown in FIG. 2 can be provided between the gate (that is, the node N1) of the NMOS transistors MN1 and MN2 and the ground node.
  • FIG. 13 is a circuit diagram showing the configuration of the bias circuit 101e according to the fifth example of the second embodiment.
  • the bias circuit 101e is different from the bias circuit 101b shown in FIG. 10 in that it includes a current generation circuit 110e instead of the current generation circuit 110b.
  • the current generation circuit 110e is connected between the nodes N1 and N2 and the grounding node Ng, similarly to the current generation circuits 110a to 110d.
  • the current generation circuit 110e includes an NMOS transistors MN1 and MN2, bipolar transistors (PNP transistors) QB1 and QB2, and resistance elements Rs (electrical resistance value Rs).
  • the NMOS transistor MN1 is connected between the nodes N2 and N3, and the NMOS transistor MN2 is connected between the nodes N1 and N4.
  • the gates of the NMOS transistors MN1 and MN2 are connected to the node N1.
  • the back gate (body) of the NMOS transistor MN1 is connected to the node N3, and the back gate (body) of the NMOS transistor MN2 is connected to the node N4.
  • the resistance element Rs and the PNP transistor QB1 are connected in series between the node N3 and the grounded node Ng.
  • the PNP transistor QB2 is connected between the node N4 and the grounded node Ng.
  • the bases of the PNP transistors QB1 and QB2 are connected to the ground node Ng.
  • the transistor size of the PNP transistor QB1 is k times (a real number of k ⁇ 1) that of the transistor of the PNP transistor QB2.
  • the basic operation of the current generation circuit 110e is the same as that of the current generation circuit 110a.
  • the reference currents IREF1 and IREF2 also have a current value proportional to the current I2.
  • the bias circuit 101e since there is no amplification action, the circuit operation is further stabilized. Therefore, the bias circuit 101e does not require phase compensation as in the bias circuit 101d (FIG. 12).
  • the start circuit 130 having switches S1 to S3 can also be applied to the bias circuit 101e in which the current generation circuit 110e and the current mirror circuit 120 are connected to the power supply node Nd and the ground node Ng via the nodes N1 and N2. can.
  • the bias circuit 101e also has the bias circuit 101 according to the first embodiment by controlling the gate voltage of the MPa transistors MP1 and MP2 during the power-off state and at the transition to the power-off state by the start circuit 130. A similar effect can be enjoyed. Further, in the bias circuit 101e, the switch S4 shown in FIG. 2 can be provided between the gate (that is, the node N1) of the NMOS transistors MN1 and MN2 and the ground node.
  • the current generation circuit 110 As described in the second embodiment, even if the configuration of the current generation circuit 110 (collectively referred to as the current generation circuits 110a to 110e) is changed, the current generation circuit 110 and the current mirror circuit are passed through the nodes N1 and N2.
  • the 120 In the configuration in which the 120 is connected in series between the power supply node Nd and the grounding node Ng, it is possible to commonly apply the start circuit 130 described in the first embodiment to ensure good startability.
  • the capacitor 210 can be further arranged between the connection node (node N2) of the switches S2 and S3 and the ground node Ng, as in FIG.
  • the NMOS transistor MN1 of the current generation circuit 110b can also be configured by LVT.
  • Embodiment 3 a bias circuit having a configuration in which the current mirror circuit 120 is composed of a P-type field effect transistor (NMR transistor) and the current generation circuit 110 is composed of an N-type field effect transistor (NMOS transistor) has been described. That is, a configuration example in which the P type corresponds to the "first conductive type” and the N type corresponds to the "second conductive type” has been described.
  • NMR transistor P-type field effect transistor
  • NMOS transistor N-type field effect transistor
  • the bias circuit according to the present embodiment it is also possible to replace the conductive type of the transistor from the configurations of the first and second embodiments. In the third embodiment, such a modification will be described.
  • FIG. 14 is a circuit diagram showing the configuration of the bias circuit according to the third embodiment.
  • the bias circuit 101x according to the third embodiment includes a current generation circuit 110x, a current mirror circuit 120, a start circuit 130, and a start control circuit 150.
  • the current generation circuit 110 and the current mirror circuit 120 are connected in series between the power supply node Nd and the ground node Ng via the nodes N1 and N2.
  • the start control circuit 150 is configured in the same manner as in the first embodiment to generate start control signals POFF and XPOFF. That is, as in the first and second embodiments, in the power-off state, the start control signal POFF is set to the L level, while the start control signal XPOFF is set to the H level. On the other hand, in the power-on state, the start control signal POFF is set to the H level, while the start control signal XPOFF is set to the L level.
  • the current mirror circuit 120 is composed of the NMOS transistors MN1 and MN2 and is connected between the grounded node Ng and the nodes N1 and N2.
  • the gates of the NMOS transistors MN1 and NM2 are connected to each other.
  • the current generation circuit 110x replaces the NMOS transistor with a NMOS transistor, and further, as for the connection destination, the nodes N1 and N2 are connected to the power supply node Nd. It can be configured by deforming the grounding node Ng side so as to connect to the node N1 or N2.
  • the off voltage of the transistors (NMOS transistors MN1 and MN2) constituting the current mirror circuit 120 is the ground voltage AGND, and the on voltage is the power supply voltage A VDD.
  • the grounding node Ng corresponds to one embodiment of the “first voltage node” that supplies the off voltage of the current mirror circuit 120
  • the power supply node Nd is the on voltage of the current mirror circuit 120.
  • the "second voltage node” that supplies.
  • the start-up circuit 130 includes at least switches S1 to S3.
  • the switch S1 is connected between the gates of the NMOS transistors MN1 and MN2 constituting the current mirror circuit 120 and the ground node Ng (that is, the node that supplies the off voltage).
  • the switch S1 is composed of an NMOS transistor SBN1 that receives a start control signal XPOFF at the gate. As a result, the switch S1 (IMS transistor SBN1) is turned on in the power-off state, while being turned off in the power-on state, as in the first and second embodiments.
  • the switch S2 is connected between the gates of the NMOS transistors MN1 and MN2 and the node N2.
  • the switch S2 is composed of an NMOS transistor SBN2 that receives a start control signal POFF at the gate.
  • the switch S2 IMS transistor SBN2 is turned off in the power-off state, while being turned on in the power-on state, as in the first and second embodiments.
  • the switch S3 is connected between the node N2 and the power supply node Nd (that is, the node that supplies the on-voltage).
  • the switch S2 is composed of a MIMO transistor SBP3 that receives a start control signal POFF at the gate.
  • the switch S3 (Pomycin transistor SBP3) is turned on in the power-off state, while being turned off in the power-on state, as in the first and second embodiments.
  • the NMOS transistors MN1 and MN2 are surely turned off by turning on the switch S1 and turning off the switch S2. Further, the power supply voltage A VDD (ON voltage) is held in the node N2 separated from the NMOS transistors MN1 and MN2 by turning off the switch S2 when the switch S3 is turned on.
  • VDD ON voltage
  • a drain current can be reliably generated in the NMOS transistors MN1 and MN2 constituting the current mirror circuit 120 at the time of transition from the power-off state to the power-on state. That is, as in the first and second embodiments, by controlling the gate voltage of the transistors (NMOS transistors MN1 and MN2) constituting the current mirror circuit 120 during the power-off state and at the transition to the power-off state.
  • the bias circuit 101x can be started stably, and the power consumption after the start can be reduced and the bias accuracy can be improved.
  • the gates of the NMOS transistors MN1 and MN2 and the node N2 are directly connected, and the switches S2 and S3 are connected in series via a separate independent node different from the node N2. It is also possible. Further, the same capacitor 210 as in FIG. 6 can be further arranged between the connection node (node N2) of the switches S2 and S3 and the ground node Ng.
  • the MOSFET transistor arranged in place of the NMOS transistor MN1 in the current generation circuits 110a to 110e can be configured by LVT.
  • the N type corresponds to one embodiment of the "first conductive type” and the P type corresponds to one embodiment of the "second conductive type”.
  • the ground node Ng connected to the current mirror circuit 120 corresponds to one embodiment of the “first power supply node”
  • the power supply node Nd connected to the current generation circuit 110 is the “second power supply node”. Will correspond to.
  • the ground voltage AGND corresponds to the "first voltage”
  • the power supply voltage A VDD corresponds to the "second voltage”.
  • the P-type field-effect transistor (PMOP transistor) is replaced with a PNP-type bipolar transistor
  • the N-type field-effect transistor (NMOS transistor) is replaced with an NPN-type bipolar transistor.
  • the "first and second transistors" in the present disclosure include both field effect transistors and bipolar transistors
  • the "first and second conductive types” include not only P-type and N-type, but also PNP-type and PNP-type. It also includes the NPN type.
  • a bias circuit having the same effect is realized by operating the start circuit 130 including at least the switches S1 to S3 on the base (control electrode) of the bipolar transistor constituting the current mirror circuit 120. be able to.
  • Embodiment 4 a configuration example of a device having the bias circuit described in the first to third embodiments as one of the elements will be described.
  • FIG. 15 is a block diagram illustrating a configuration example of the sensor device according to the first example of the fourth embodiment.
  • the sensor device 300 includes a bias circuit 101, a sensor 310, an amplifier circuit 320, an ADC (Analog to Digital Converter) 320, and an integrated circuit (IC: Integrated Circuit). It is equipped with 340.
  • the bias circuit 101 is a general term for the bias circuits 101 to 104, 101a to 101e, and 101x described in the first to third embodiments. As described above, the bias circuit 101 outputs at least a highly accurate bias current.
  • the sensor 310 is composed of, for example, an infrared sensor for detecting a person.
  • the sensor 310 outputs an analog voltage according to the physical quantity to be measured.
  • the amplifier circuit 320 uses the bias current from the bias circuit 101 to output an analog voltage obtained by amplifying the output voltage of the sensor 310.
  • the ADC 330 converts the analog voltage output by the amplifier circuit 320 into a plurality of bits of digital data. As a result, digital data indicating the output voltage of the sensor 310 can be obtained.
  • the digital data from the ADC 330 is input to the IC 340.
  • the IC 340 generates an output signal indicating the output voltage of the sensor 310 by processing the digital data as a signal. For example, in the IC 340, it is possible to execute noise removal processing or the like by applying a low-pass filter.
  • the power supply voltage A VDD and the ground voltage AGND are supplied to each element in FIG. 15 via the power supply node Nd and the ground node Ng described in the first to third embodiments.
  • the sensor device 300 is in the power-off state and the power-on state when the supply of the power supply voltage AVDD to the power supply node Nd is stopped and the supply of the power supply voltage AVDD by turning on the power is instructed from the outside of the sensor device 300. Will be one of.
  • the bias circuit 101 does not consume current in the power-off state, and can be reliably activated to generate a bias current with high accuracy at the time of transition to the power-on state. .. Further, in the power-on state, a useless current as described in Comparative Example and Patent Document 1 is not continuously generated. As a result, it is possible to reduce the power consumption of the entire system of the sensor device 300 by suppressing the power consumption of the bias circuit 101.
  • the bias circuit 101 is also suitable for applications in which the power-off state and the power-on state are frequently switched in order to intermittently operate the sensor device 300 for further reduction in power consumption. This is because the starting circuit 130 can reliably generate a bias current in response to the transition from the power-off state to the power-on state.
  • FIG. 16 is a block diagram illustrating a configuration example of the wireless sensor device according to the second example of the fourth embodiment.
  • the wireless sensor device 301 has the same bias circuit 101, sensor 310, amplifier circuit 320, and ADC 320 as in FIG. 15, and a computing unit (CPU: Central Processing Unit). It includes 350, a memory 360, and a wireless communication unit (IC) 370.
  • CPU Central Processing Unit
  • the arithmetic unit 350 can perform arbitrary signal processing on the digital data from the ADC 330 by executing the program stored in the memory 360.
  • the wireless communication unit 370 is configured to include an interface for transmitting or receiving a signal according to a predetermined wireless communication protocol, and can transmit and receive a signal to and from the wireless sensor device 301.
  • the data and information obtained by the signal processing in the arithmetic unit 350 that is, the transmission signal based on the digital data is transmitted to the outside of the wireless sensor device 301 according to a predetermined wireless communication protocol. Can be done.
  • the power supply voltage A VDD and the ground voltage AGND are also supplied to each element in FIG. 16 via the power supply node Nd and the ground node Ng described in the first to third embodiments.
  • the wireless sensor device 301 is in either the power-off state or the power-on state according to the supply stop of the power supply voltage A VDD and the supply start of the power supply voltage AVDD by turning on the power.
  • the wireless sensor device 301 shown in FIG. 16 also has the same effect as described in the sensor device 300 described above due to the good startability of the bias circuit 101, high bias accuracy after startup, and low power consumption. You can enjoy it.
  • the wireless communication unit 370 can receive a command or information from the outside of the wireless sensor device 301. Then, the arithmetic unit 350 can control the operation of the wireless sensor device 301 based on the received information and the information. For example, based on these information or commands, the power-on state and the power-off state can be switched by controlling the supply stop and supply start of the power supply voltage A VDD to the power supply node Nd inside the wireless sensor device 301. Is also possible. Also in this case, the bias circuit 101 can be reliably activated in response to the transition from the power-off state to the power-on state.
  • the bias circuit 101 can be applied to an analog circuit or an analog / digital mixed LSI (Large Scale Integrated circuit).

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PCT/JP2020/013038 2020-03-24 2020-03-24 バイアス回路、並びに、センサ機器及びワイヤレスセンサ機器 Ceased WO2021192040A1 (ja)

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US17/792,918 US11967949B2 (en) 2020-03-24 2020-03-24 Bias circuit, sensor device, and wireless sensor device
DE112020006949.4T DE112020006949T5 (de) 2020-03-24 2020-03-24 Bias-Schaltung, Sensorvorrichtung und drahtlose Sensorvorrichtung
CN202080098640.4A CN115298634B (zh) 2020-03-24 2020-03-24 偏置电路、传感器设备以及无线传感器设备
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114661649A (zh) * 2022-04-12 2022-06-24 湖南国科微电子股份有限公司 一种偏置电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002328732A (ja) * 2001-05-07 2002-11-15 Texas Instr Japan Ltd 基準電圧発生回路
JP2008197994A (ja) * 2007-02-14 2008-08-28 Oki Electric Ind Co Ltd 起動回路
JP2009093483A (ja) * 2007-10-10 2009-04-30 Kobe Univ 温度補償バイアス回路
JP2009193211A (ja) * 2008-02-13 2009-08-27 Seiko Instruments Inc 定電流回路
JP2010186360A (ja) * 2009-02-13 2010-08-26 New Japan Radio Co Ltd バイアス電流発生回路
JP2011186987A (ja) * 2010-03-11 2011-09-22 Renesas Electronics Corp 基準電流生成回路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4374254B2 (ja) * 2004-01-27 2009-12-02 Ｏｋｉセミコンダクタ株式会社 バイアス電圧発生回路
EP1812842A2 (en) 2004-11-11 2007-08-01 Koninklijke Philips Electronics N.V. All npn-transistor ptat current source
TW200903213A (en) * 2007-07-02 2009-01-16 Beyond Innovation Tech Co Ltd Bias supply, start-up circuit, and start-up method for bias circuit
US8669808B2 (en) * 2009-09-14 2014-03-11 Mediatek Inc. Bias circuit and phase-locked loop circuit using the same
US8400219B2 (en) * 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
JP2012252508A (ja) * 2011-06-02 2012-12-20 Lapis Semiconductor Co Ltd 半導体集積回路
JP5762205B2 (ja) * 2011-08-04 2015-08-12 ラピスセミコンダクタ株式会社 半導体集積回路
CN104898760B (zh) * 2015-04-30 2016-08-17 中国电子科技集团公司第三十八研究所 适用于低电压环境的电流镜电路
JP6782614B2 (ja) * 2016-11-21 2020-11-11 ラピスセミコンダクタ株式会社 出力回路及び液晶表示装置のデータドライバ
US10033364B1 (en) * 2017-05-31 2018-07-24 Silicon Laboratories Inc. Low power compact peak detector with improved accuracy

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002328732A (ja) * 2001-05-07 2002-11-15 Texas Instr Japan Ltd 基準電圧発生回路
JP2008197994A (ja) * 2007-02-14 2008-08-28 Oki Electric Ind Co Ltd 起動回路
JP2009093483A (ja) * 2007-10-10 2009-04-30 Kobe Univ 温度補償バイアス回路
JP2009193211A (ja) * 2008-02-13 2009-08-27 Seiko Instruments Inc 定電流回路
JP2010186360A (ja) * 2009-02-13 2010-08-26 New Japan Radio Co Ltd バイアス電流発生回路
JP2011186987A (ja) * 2010-03-11 2011-09-22 Renesas Electronics Corp 基準電流生成回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114661649A (zh) * 2022-04-12 2022-06-24 湖南国科微电子股份有限公司 一种偏置电路

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CN115298634A (zh) 2022-11-04
DE112020006949T5 (de) 2023-01-26

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