WO2021168953A1 - 一种键合结构及其制造方法 - Google Patents

一种键合结构及其制造方法 Download PDF

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Publication number
WO2021168953A1
WO2021168953A1 PCT/CN2020/080806 CN2020080806W WO2021168953A1 WO 2021168953 A1 WO2021168953 A1 WO 2021168953A1 CN 2020080806 W CN2020080806 W CN 2020080806W WO 2021168953 A1 WO2021168953 A1 WO 2021168953A1
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layer
chip
wafer
lead
bonding
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PCT/CN2020/080806
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English (en)
French (fr)
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占迪
胡杏
刘天建
胡胜
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武汉新芯集成电路制造有限公司
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Priority to US17/799,112 priority Critical patent/US20230163102A1/en
Publication of WO2021168953A1 publication Critical patent/WO2021168953A1/zh

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Definitions

  • the invention relates to the field of semiconductor devices and their manufacturing, in particular to a bonding structure and a manufacturing method thereof.
  • wafer-level packaging technology As semiconductor technology enters the post-Moore era, in order to meet the needs of high integration and high performance, the chip structure is developing in a three-dimensional direction, and wafer-level packaging technology has been widely used. It uses wafer-level packaging technology to combine different Wafer stacking and bonding together can shorten the signal transmission path between devices, provide more I/O, improve chip response speed and reduce chip size, and at the same time, it can realize the interconnection between different technology nodes and functional chips. , Reducing the design and process difficulty, thereby reducing manufacturing costs. However, as the number of stacked layers increases, the probability of chip failure increases. After the chip is stacked, electrical tests can obtain failure information, but it is difficult to trace which layer of chips caused the failure.
  • the purpose of the present invention is to provide a bonding structure and a manufacturing method thereof, which can test single-layer or multi-layer chips in a chip stack to obtain specific failed chip positions.
  • the present invention has the following technical solutions:
  • a bonding structure includes: a wafer stack formed by sequentially bonding multiple layers of wafers, wherein chip stacks are arranged in an array on the wafer stack, and the chip stacks include multiple layers of chips that are sequentially bonded.
  • An electrical lead-out structure is formed in the chip stack, and the electrical lead-out structure includes a full lead-out structure that electrically connects the interconnection layers in each layer of the chip, and a partial lead-out structure that electrically connects the interconnection layer of the partial-layer chip and/or the electrical connection single layer Single-lead structure of the interconnect layer in the chip.
  • the wafers in the wafer stack are bonded through a dielectric bonding layer, and the electrical lead-out structure includes a through silicon via and a rewiring layer connected to it.
  • At least part of the rewiring layer is connected to through silicon vias of different depths.
  • the wafers in the wafer stack are bonded by a hybrid bonding structure
  • the hybrid bonding structure includes a dielectric bonding layer and a metal bonding pad therein, and the metal bonding of adjacent layers of wafers
  • the bonding pads are bonded together, and part of the electrical lead-out structures include metal bonding pads and through silicon vias connected thereto, and part of the electrical lead-out structures include through silicon vias.
  • a bonding structure includes a chip stack, the chip stack includes multiple layers of chips that are sequentially bonded, and an electrical lead-out structure is formed in the chip stack.
  • a method for manufacturing a bonding structure includes:
  • a bottom wafer in which chips are arranged in an array, and a dielectric bonding layer is formed on the bottom wafer;
  • Each wafer to be bonded is provided, and chips are arranged in an array in each wafer to be bonded, and a dielectric bonding layer is formed on the wafer to be bonded;
  • the dielectric bonding layer is used to sequentially bond the wafers to be bonded on the bottom wafer, and after each bonding, a through silicon via and a rewiring layer electrically connected to it are formed to form an array
  • a wafer stack with chip stacks and an electrical lead-out structure in the chip stack are arranged.
  • the electrical lead-out structure includes a full lead-out structure that electrically connects the interconnection layers in each layer of the chip, and electrically connects the interconnection layers in the partial layer of the chip.
  • the partial lead-out structure and/or the single lead-out structure that electrically connects the interconnection layer in the single-layer chip.
  • At least part of the rewiring layer is connected to through silicon vias of different depths.
  • it also includes:
  • a pad is formed on the top redistribution layer.
  • Optional also includes:
  • the wafer stack is diced to form an independent chip stack.
  • a method for manufacturing a bonding structure includes:
  • a bottom wafer in which chips are arranged in an array, a hybrid bonding layer is formed on the bottom wafer, and the hybrid bonding layer includes a dielectric bonding layer and a metal bonding pad therein, so Part of the interconnection layer in the bottom wafer is electrically connected to the metal bonding pad;
  • Each wafer to be bonded is provided, and chips are arranged in an array in each wafer to be bonded, a hybrid bonding layer is formed on the wafer to be bonded, and a part of the interconnection layer in the wafer to be bonded is The metal bonding pad is electrically connected;
  • the method further includes: forming a hybrid bonding layer on the through silicon hole, the hybrid bonding layer includes a dielectric bonding layer and a metal bonding pad therein, and the to-be-bonded Part of the through silicon vias in the bonded wafer are electrically connected to the metal bonding pads, thereby forming a wafer stack in which the chip stacks are arranged in an array and an electrical lead-out structure in the chip stack, the electrical lead-out structure includes electrically connecting layers The full lead-out structure of the interconnection layer in the chip, and the partial lead-out structure that electrically connects the interconnection layer of the partial-layer chip and/or the single lead-out structure that electrically connects the interconnection layer of the single-layer chip.
  • the method further includes: forming a rewiring layer on the through silicon via.
  • it also includes:
  • a pad is formed on the top redistribution layer.
  • Optional also includes:
  • the wafer stack is diced to form an independent chip stack.
  • a bonding structure provided by an embodiment of the present invention is a wafer stack formed by sequentially bonding multiple layers of wafers.
  • the wafer stack is arrayed with chip stacks.
  • the chip stack includes multiple layers of chips that are sequentially bonded.
  • the chip stack An electrical lead-out structure is formed in the chip.
  • the electrical lead-out structure includes a full-lead structure that electrically connects the interconnection layers in each layer of the chip, and a partial lead-out structure that electrically connects the interconnection layer in the partial layer of the chip and/or electrically connects the interconnection in the single-layer chip Layered single-lead structure.
  • the electrical performance of the entire chip stack can be tested.
  • the electrical performance test of the chip and/or the single-lead structure that electrically connects the interconnection layer in the single-layer chip can perform electrical performance test on the single-layer chip in the chip stack, so as to realize the single-layer or multi-layer chip in the chip stack. Electrical performance test, and then get the specific location of the failed chip.
  • Figures 1-15 show schematic views of the structure in the process of forming a bonding structure according to the manufacturing method of an embodiment of the present invention.
  • a bonding structure provided by an embodiment of the present invention is a wafer stack formed by sequentially bonding multiple layers of wafers.
  • the wafer stack is arrayed with sequentially bonded multiple layers of chips, and the chip stack is formed with
  • the electrical lead-out structure includes a full lead-out structure that electrically connects the interconnection layers in each layer of the chip, and a partial lead-out structure that electrically connects the interconnection layer of the partial-layer chip and/or the single-lead structure that electrically connects the interconnection layer of the single-layer chip. Lead out the structure.
  • the electrical performance test of the chip and/or the single-lead structure that electrically connects the interconnection layer in the single-layer chip can perform electrical performance test on the single-layer chip in the chip stack, so as to realize the single-layer or multi-layer chip in the chip stack. Electrical performance test, and then get the specific location of the failed chip.
  • a wafer stack formed by sequentially bonding multiple layers of wafers, in which chip stacks are arranged in an array, the chip stacks include multiple layers of chips that are sequentially bonded, and the chip stacks
  • An electrical lead-out structure is formed in the chip.
  • the electrical lead-out structure includes a full lead-out structure that electrically connects the interconnection layers in each layer of the chip, and electrically connects the partial lead-out structure of the interconnection layer in the partial-layer chip and/or the electrical connection in the single-layer chip.
  • Single-lead structure of the interconnect layer Single-lead structure of the interconnect layer.
  • the wafer stack may be a wafer stack formed by sequentially bonding two or more layers of wafers, and each layer of wafers may be formed with multiple chips arranged in arrays.
  • the chips in each layer of wafers are sequentially bonded to form a chip stack, so that the chip stack is arranged in an array on the wafer stack, and the chips in each layer of the chip stack may have been formed on the substrate.
  • the device structure can include MOS field effect transistor devices, memory devices and/or other passive devices.
  • the device structure on each layer of the chip can be the same or different.
  • the device structure is composed of the medium Covered by the bonding layer
  • the dielectric bonding layer may be a single layer or a laminated structure, for example, may include an interlayer dielectric layer and an intermetal dielectric layer.
  • the dielectric bonding layer is a bonding dielectric material, such as silicon oxide (bonding oxide). ), silicon nitride, NDC (Nitrogen doped Silicon Carbide, nitrogen-doped silicon carbide) or their combination
  • the interconnection layer is formed in the dielectric bonding layer, the interconnection layer can be multiple layers, and the interconnection layers of different layers can pass Contact plugs, vias, etc. realize interconnection, and the interconnection layer may be a metal material, such as tungsten, aluminum, copper, etc.
  • An electrical lead-out structure may also be formed in the chip stack, and the electrical lead-out structure is connected to the interconnection layer, so that the interconnection of the device structure in the multilayer chip can be realized.
  • the electrical lead-out structure can include a full lead-out structure and a partial lead-out structure and/or a single lead-out structure.
  • the full lead-out structure can realize the interconnection of the devices in each layer of the chip stack, so that the electrical performance of each layer of the chip can be tested, and the partial lead structure can Realize the interconnection of some layers of chips in the chip stack, so as to perform electrical performance tests on some layers of chips.
  • the single-lead structure can lead out the single-layer chips in the chip stack to realize the electrical performance test of the single-layer chips.
  • the wafers in the wafer stack are bonded through a dielectric bonding layer, and the electrical lead-out structure includes a through silicon via and a rewiring layer connected to it, and an array of chip stacks are formed on the wafer stack
  • the electrical lead-out structure includes a through silicon via and a rewiring layer connected to it, and an array of chip stacks are formed on the wafer stack
  • the bonding structure will be described in detail.
  • the first wafer and the second wafer are bonded together through the first dielectric bonding layer 110 and the second dielectric bonding layer 210, and the second wafer and the third wafer are bonded together through the first cover layer 1200 and the third dielectric bonding layer.
  • the bonding layer 310 is bonded together. While the wafer is bonded to form a wafer stack, the chips on the wafer are sequentially bonded to form a chip stack, so that the wafer stack is arrayed with chip stacks. In this embodiment , Only one chip stack in the wafer stack is described in detail, and the three layers of chips in the chip stack are referred to as the first chip 10, the second chip 20, and the third chip 30 for the convenience of the subsequent description. Shown in Figure 7.
  • the electrical lead-out structure formed in the chip stack includes a through-silicon via and a rewiring layer connected to it. It may include a full lead-out structure that electrically connects the interconnection layers in each layer of the chip, and electrically connects some layers of the chip to each other. A partial lead-out structure of the interconnection layer, for example, two layers of chips, and/or a single lead-out structure that electrically connects the interconnection layer of one layer of the chips.
  • the full lead-out structure for electrically connecting the interconnection layers in the chips of each layer may include through silicon vias 120 that penetrate to the interconnection layer 111 in the first chip 10, through silicon vias 220 that penetrate to the interconnection layer 211 in the second chip 20, and through The TSV 320 to the interconnection layer 311 in the third chip 30 and the first rewiring layer 1201, the second rewiring layer 2301, and the first rewiring layer 1201 connect adjacent TSVs 120 of different depths and TSVs.
  • the second rewiring layer 2301 connects adjacent through silicon vias 123 and through silicon vias 320 of different depths, and the through silicon via 123 connects the first rewiring layer 1201 and the second rewiring layer 2301 are connected, so that the through silicon via 120, the through silicon via 220, and the through silicon via 320 are connected together through the first rewiring layer 1201 and the second rewiring layer 2301 to realize the first chip 10,
  • the interconnection of the second chip 20 and the third chip 30 can then perform electrical performance testing on the chip stack formed on the wafer stack.
  • the test passed indicates that the chips in the chip stack are all valid chips, and subsequent packaging and other operations can be performed.
  • the unqualified test indicates that there is a defective chip in the chip stack. You can subsequently test some layers or single-layer chips in the chip stack to obtain the specific location of the failed chip.
  • the part of the lead structure that electrically connects the interconnection layer in the partial layer chip may include through silicon vias 120, through silicon vias 220, through silicon vias 123, and a first rewiring layer 1201, a second rewiring layer 2301, and a first rewiring layer 1201. Connect adjacent through silicon vias 120 and through silicon vias 220 of different depths, so as to realize the connection of the first chip 10 and the second chip 20, and then connect the first chip 10 and the second chip through the through silicon via 123 and the second rewiring layer 2301. The second chip 20 is led out, so that the electrical performance test of the first chip 10 and the second chip 20 can be performed.
  • a qualified test indicates that the first chip 10 and the second chip 20 are qualified chips, and the unqualified test indicates the first chip 10 Or if there are defective chips in the second chip 20 or both layers of chips are defective chips, electrical performance tests can be performed on the first chip 10 and the second chip 20 respectively to obtain the specific positions of the failed chips.
  • the part of the lead structure that electrically connects the interconnection layer in the partial layer chip may also include through silicon vias 120, through silicon vias 123, through silicon vias 320, and a first rewiring layer 1201, a second rewiring layer 2301, and a first rewiring layer. 1201 connects through silicon vias 120 and through silicon vias 123, and the second rewiring layer 2301 connects adjacent through silicon vias 123 and through silicon vias 320 of different depths, so that through silicon vias 120 and through silicon vias 320 are connected to achieve The first chip 10 and the third chip 30 are connected, so that the electrical performance test of the first chip 10 and the third chip 30 can be performed.
  • the qualified test indicates that the first chip 10 and the third chip 30 are qualified chips, and the test fails. Qualified description There are unqualified chips in the first chip 10 or the third chip 30, or both layers of chips are unqualified chips. You can perform electrical performance tests on the first chip 10 and the third chip 30 respectively to obtain the specific failure chip Location.
  • the part of the lead structure that electrically connects the interconnection layer in the partial layer chip may also include through silicon vias 220, through silicon vias 123, through silicon vias 320, and a first rewiring layer 1201, a second rewiring layer 2301, and a first rewiring layer 1201 connects the through silicon via 220 and the through silicon via 123, and the second rewiring layer 2301 connects the adjacent through silicon vias 123 and the through silicon vias 320 of different depths, so that the through silicon via 220 in the second chip 20 is connected to the first through silicon via 220.
  • the through-silicon vias 320 in the three chips 30 are connected to realize the connection between the second chip 20 and the third chip 30, and then the second chip 20 and the third chip 30 can be tested for electrical performance.
  • the chips in the three chips 30 are qualified chips.
  • the unqualified test indicates that the second chip 20 or the third chip 30 has non-conforming chips or the two layers of chips are non-conforming chips.
  • the second chip 20 and the third chip 30 can be subsequently tested. Carry out electrical performance tests separately to obtain the specific location of the failed chip.
  • the single lead-out structure for electrically connecting the interconnection layers in the single-layer chip may include through silicon vias 120, through silicon vias 123, and a first rewiring layer 1201 and a second rewiring layer 2301.
  • the first rewiring layer 1201 is connected to the through silicon via 123.
  • the interconnection layer 111 in the first chip 10 is led out through the second rewiring layer 2301 connected to the through silicon hole 123, so as to realize the electrical performance test of the first chip 10 in the chip stack.
  • the single lead structure that electrically connects the interconnection layers in the single-layer chip may include through silicon vias 220, through silicon vias 123, and a first rewiring layer 1201 and a second rewiring layer 2301.
  • the first rewiring layer 1201 connects the through silicon vias 220. It is connected to the through silicon via 123, and then the interconnection layer 211 of the second chip 20 is led out through the second rewiring layer 2301 connected to the through silicon via 123, so that the electrical performance test of the second chip 20 in the chip stack can be performed.
  • the single lead-out structure for electrically connecting the interconnection layer in the single-layer chip may include a through silicon via 320 and a second rewiring 2301.
  • the second rewiring layer 2301 is connected to the through silicon via 320 to connect the interconnection layer 311 in the third chip 30. Lead out, so that the electrical performance test of the third chip 30 in the chip stack can be performed.
  • the bonding structure in the above embodiment forms an electrical lead-out structure including a through silicon via and a rewiring layer connected to the through silicon via process in the chip stack through the through silicon via process, which can perform electrical performance testing on single-layer or multi-layer chips in the chip stack. In this way, the location of the specific failed chip can be obtained, so as to selectively bypass the failed chip and connect only the valid chip to reduce the chip scrap rate.
  • the wafers in the wafer stack are bonded by a hybrid bonding structure
  • the hybrid bonding structure includes a dielectric bonding layer and a metal bonding pad therein, and the metal bonding of adjacent layers of wafers
  • the pads are bonded together
  • part of the electrical lead-out structure includes a metal bonding pad and its connected through silicon vias
  • part of the electrical lead-out structure includes a through silicon via.
  • the through-silicon via process is used to form an electrical lead-out structure including metal bonding pads and through-silicon vias connected thereto or an electrical lead-out structure including through-silicon vias.
  • the single-layer or multi-layer chips in the chip stack arranged in an array on the circle stack are tested for electrical performance.
  • the wafers are bonded by a hybrid bonding structure.
  • the hybrid bonding structure means that the bonding interface is formed by bonding materials of different materials.
  • the hybrid bonding structure includes a dielectric bond.
  • the bonding layer and the metal bonding pads therein, the metal bonding pads are electrically connected to the interconnection layer in the dielectric bonding layer, and the metal bonding pads can be formed on the interconnection layer to realize the electrical connection between the chips in the wafer Or it is the electrical lead-out of the interconnect layer in the chip.
  • the dielectric bonding layer is a dielectric material for bonding, which can be a single-layer or multi-layer structure, for example, silicon oxide (bonding oxide), silicon nitride, NDC (Nitrogen doped Silicon Carbide, nitrogen-doped silicon carbide) or a combination thereof,
  • the metal bonding pad may be a bonding metal material, for example, copper.
  • the bonding structure will be described in detail.
  • the three-layer wafers are referred to as the first wafer, the second wafer, and the third wafer.
  • the first dielectric bonding layer 110 in the first wafer and the second dielectric in the second wafer The bonding layer 210 is bonded, and the first metal bonding pad 112 in the first dielectric bonding layer 110 is bonded to the second metal bonding pad 212 in the second dielectric bonding layer 210 to realize the first wafer and Bonding of the second wafer.
  • the first cover layer 1200 on the second wafer is bonded to the third dielectric bonding layer 310 in the third wafer, while the metal bonding pad 1202 in the first cover layer 1200 is bonded to the third dielectric bonding layer 310
  • the third metal bonding pad 312 is bonded to realize the bonding between the second wafer and the third wafer, thereby forming a wafer stack containing three-layer wafers. It can also be continuously bonded on the third wafer to form a wafer stack containing Wafer stacking of more layers of wafers.
  • the metal bonding pad in the dielectric bonding layer can be formed together with the interconnection layer in the dielectric bonding layer.
  • the chips on the wafer are sequentially bonded to form a chip stack, so that the wafer stack is arrayed with chip stacks.
  • the three layers of chips in one chip stack on the wafer stack are referred to as the first chip 10, the second chip 20, and the third chip, respectively. 30. Refer to Figure 14.
  • a part of the electrical lead-out structure in the electrical lead-out structure formed in the chip stack, includes a metal bonding pad and a through silicon via connected thereto, and a part of the electrical lead-out structure includes a through silicon hole.
  • the electrical lead-out structure may include electrically connecting layers The full lead-out structure of the interconnection layer in the chip, and the partial lead-out structure that electrically connects the interconnection layer of the partial-layer chip and/or the single lead-out structure that electrically connects the interconnection layer of the single-layer chip.
  • the fully drawn-out structure that electrically connects the interconnection layers in each layer of the chip may include a first metal bonding pad 112, a second metal bonding pad 212, a through silicon via 220, and a first second.
  • the wiring layer 1201 and the metal bonding pad 1202 above it, the third metal bonding pad 312, the through silicon via 123, the second rewiring layer 2301, the first metal bonding pad 112 and the second metal bonding pad 212 are bonded
  • the first chip 10 and the second chip 20 are interconnected, and then connected to the first rewiring layer 1201 through the silicon through hole 220.
  • the metal bonding pad 1202 above the first rewiring layer 1201 is in the third chip 30.
  • the third metal bonding pad 312 of the first chip 10 is bonded, so that the interconnection layer 111 in the first chip 10 is connected with the interconnection layer 211 in the second chip 20 and the interconnection layer 311 in the third chip 30 to realize the first A chip 10, a second chip 20 and a third chip 30 are interconnected, and then the chip stack is led out by the second rewiring layer 2301 connected to the through silicon via 123, forming a metal bonding pad and a through silicon via connected thereto
  • the electrical lead-out structure can realize the electrical performance test of the chip stack.
  • a qualified test indicates that each layer of the chip in the chip stack is a qualified chip. If the test fails, the electrical performance test of two or one of the chips can be followed to obtain the failure The specific location of the chip.
  • the part of the lead-out structure that electrically connects the interconnection layer in the partial layer of the chip may include a first metal bonding pad 112, a second metal bonding pad 212, and through silicon vias thereon, the first metal bonding pad 112 and the second metal bonding
  • the bonding pad 212 is bonded to realize the interconnection of the first chip 10 and the second chip 20, and then the through silicon vias 220, 320 and the first rewiring layer are formed that penetrate the interconnection layer 211 above the second metal bonding pad 212 1201 and the second rewiring layer 2301 to form a partial lead structure including through silicon vias and metal bonding pads.
  • the first rewiring layer 1201 connects the through silicon vias 220 and the through silicon vias 320, and then passes through the through silicon vias 320.
  • the connected second rewiring layer 2301 leads the first chip 10 and the second chip 20 out, and then the electrical performance test of the first chip 10 and the second chip 20 can be performed.
  • the partial lead-out structure that electrically connects the interconnection layer in the partial layer chip may further include a through silicon via 220 penetrating to the interconnection layer 211 in the second chip 20, the first rewiring layer 1201 and the metal bonding pad 1202 above it, and The third metal bonding pad 312 in the third chip 30, the through silicon via 123 that penetrates to the interconnect layer 311 in the third chip 30, the second rewiring layer 2301, and the metal bonding pad above the first rewiring layer 1201 After 1202 is bonded to the third metal bonding pad 312, the interconnection layer 211 in the second chip 20 is led out through the through silicon via 220, and is connected to the second rewiring layer 2301 through the through silicon via 123, thereby forming a connected second Part of the electrical lead structure of the chip 20 and the third chip 30 realizes the electrical performance test of the second chip 20 and the third chip 30.
  • the part of the electrical lead-out structure that electrically connects the interconnection layer of the partial-layer chip may further include a through silicon via 120 penetrating to the interconnection layer 111 in the first chip 10, the first rewiring layer 1201 and the metal bonding pad 1202 thereon, and The third metal bonding pad 312 in the third chip 30, the through silicon via 123 that penetrates to the interconnect layer 311 in the third chip 30, the second rewiring layer 2301, and the metal bonding pad above the first rewiring layer 1201 1202 is bonded to the third metal bonding pad 312 and connected to the through silicon via 120, connecting the interconnection layer 111 in the first chip 10 with the interconnection layer 311 in the third chip 30, and then through the through silicon via 123 and the through silicon via 123.
  • the connected second rewiring layer 2301 leads out the interconnection layers in the first chip 10 and the third chip 30 to form a partial lead structure connecting the first chip 10 and the third chip 30 to realize the connection between the first chip 10 and the third chip 30. Electrical performance test of three chips 30.
  • the single-lead structure for electrically connecting the interconnection layer in the single-layer chip may include through-silicon vias 120, through-silicon vias 320, and the first rewiring layer 1201 and the second rewiring layer 2301 penetrating to the interconnection layer 111 in the first chip 10.
  • the first rewiring layer 1201 connects the through silicon via 120 and the through silicon via 320
  • the through silicon via 320 connects with the second rewiring layer 2301 to lead out the interconnection layer 111 in the first chip 10 to form a through silicon via
  • the electrical lead-out structure to achieve the electrical performance test of the first chip 10 in the chip stack.
  • the single lead-out structure that electrically connects the interconnection layer in the single-layer chip may further include through-silicon vias 220, through-silicon vias 320, and the first rewiring layer 1201 and the second rewiring layer that penetrate to the interconnection layer 211 in the second chip 20.
  • Layer 2301, the first rewiring layer 1201 connects the through silicon via 220 and the through silicon via 320, and the through silicon via 320 and the second rewiring layer 2301 lead out the interconnection layer 211 in the second chip 20 to form a through silicon via
  • the electrical lead-out structure of the hole realizes the electrical performance test of the second chip 20 in the chip stack.
  • the single lead-out structure that electrically connects the interconnection layer in the single-layer chip may include through silicon vias 123 penetrating to the interconnection layer 311 in the third chip 30, the second rewiring layer 2301, and the second rewiring layer 2301 connects the third chip 30
  • the interconnection layer 311 in the chip stack is led out to form an electrical lead-out structure including through silicon vias, so that the electrical performance test of the third chip 30 in the chip stack can be implemented.
  • the above-mentioned bonding structure forms an electrical lead-out structure in the chip stack through a hybrid bonding process and a through silicon via process.
  • Some of the electrical lead-out structures include metal bonding pads and through-silicon vias connected thereto, and some of the electrical lead-out structures include silicon. Through holes, the electrical performance of single-layer or multi-layer chips in the chip stack can be tested, so that the specific location of the failed chip can be obtained.
  • the bonding structure can be packaged, and the effective chip can be selectively connected during the packaging process to avoid connecting the electrical lead-out structure of the failed chip, make full use of the effective chip, and reduce the scrap rate.
  • a bonding structure of the embodiment of the present application is described in detail above.
  • the embodiment of the present application also provides another bonding structure, including a chip stack, and the chip stack includes multiple layers of chips that are sequentially bonded.
  • An electrical lead-out structure is formed in the chip stack, and the electrical lead-out structure includes a full lead-out structure that electrically connects the interconnection layers in each layer of the chip, and a partial lead-out structure and/or electrical connection that electrically connects the interconnection layer of the partial-layer chip Single-lead structure of the interconnection layer in a single-layer chip.
  • the electrical performance of each layer of the chip in the chip stack can be tested through the full lead-out structure in the chip stack, and the electrical performance of some layers of the chip in the chip can be tested through the partial lead-out structure in the chip stack.
  • the single-lead structure in the stack can test the electrical performance of a certain layer of chips in the chip stack.
  • the electrical performance test of each layer of the chips in the chip stack that are electrically connected together can be performed through the all-out structure first, and the test is qualified, indicating that there are no failed chips in the chip stack, and the chip stack can be followed up
  • unqualified testing indicates that there are failed chips in the chip stack, and then the electrical performance of certain layers of chips that are electrically connected together can be tested. If these layers of chips are qualified, you can continue to perform electrical performance on other layers of chips. Test, if these layers of chips fail the test, it means that there are failed chips in these layers of chips. You can continue to conduct separate electrical performance tests on each layer of chips in these layers through the single-lead structure, and then you can get specific failures. Position, so that there is no need to conduct a separate electrical performance test on each layer of the chip stack, which improves the efficiency of electrical performance testing.
  • a bottom wafer is provided, in which chips 10 are arranged in an array, and a dielectric bonding layer 110 is formed on the bottom wafer; the bottom wafer in the embodiment of the present application can also be called This is the first wafer.
  • Each wafer to be bonded is provided, and chips are arranged in an array in each wafer to be bonded, and a dielectric bonding layer is formed on the wafer to be bonded; each wafer to be bonded in the embodiments of the present application They can be called the second wafer, the third wafer, and so on, respectively.
  • the dielectric bonding layer is used to sequentially bond the wafers to be bonded on the bottom wafer, and after each bonding, a through-silicon via and a rewiring layer electrically connected to it are formed to form an array with chip stacks
  • the electrical lead-out structure includes a full lead-out structure that electrically connects the interconnect layers in the chips of each layer, and a partial lead-out structure that electrically connects the interconnect layers in the partial-layer chips and/ Or a single-lead structure that electrically connects the interconnect layers in a single-layer chip.
  • FIG. 1 shows a chip structure in the first wafer called the first chip 10.
  • the first wafer and the second wafer are bonded to form a wafer stack.
  • the backside of the substrate 200 of the wafer is thinned to simplify the subsequent through-silicon via process.
  • CMP chemical mechanical polishing
  • WET wet etching
  • a through silicon via that penetrates through the interconnect structure in the chip is formed in the bonded wafer, and an insulating dielectric layer may be formed on the sidewall of the through silicon via, for example, Silicon oxide, silicon nitride, etc., and then the through silicon via is filled with a metal material, such as tungsten, aluminum, copper, etc.
  • the through silicon via 120 is connected to the interconnection layer 111 in the first chip 10 on the first wafer
  • the through silicon via 220 is connected to the interconnection layer 211 in the second chip 20 on the second wafer, so that the first chip 10 in the first wafer and the second chip 20 in the second wafer can be connected
  • the interconnection layers are led out to achieve the electrical performance test of the first chip 10 and the second chip 20.
  • a first covering layer 1200 is formed on the second wafer, and the first covering layer 1200 is The first rewiring layer 1201 is formed.
  • the first covering layer 1200 can be a single layer or a laminated structure, and can be the same or different from the material of the dielectric bonding layer.
  • the first rewiring layer 1201 can be a metal material, for example, Tungsten, aluminum, copper, etc.
  • the first rewiring layer 1201 connects the through silicon via 120 and the through silicon via 220, thereby realizing the interconnection between the interconnection layer 111 in the first chip 10 on the first wafer and the second chip 20 on the second wafer
  • the connection of layer 211 forms a full lead structure that electrically connects the interconnect layers in the chip stack.
  • a single-lead structure that connects interconnect layers in a single-layer chip.
  • the third wafer can be bonded to the second wafer through the bonding of the third dielectric bonding layer 310 and the cover layer 1200 on the third wafer to form a bond containing three wafers.
  • Figure 5 shows the structure of one chip stack in a wafer stack containing three-layer wafers.
  • the chip stack is subjected to a through-silicon via process to form a connection to The through silicon via 123 of the first rewiring layer 1201 and the through silicon via 320 connected to the interconnection layer 311 in the third chip 30 on the third wafer, as shown in FIG.
  • the material of the second covering layer 2300 and the second covering layer 2300 may be the same as or different from the material of the first covering layer 1200.
  • a second rewiring layer 2301 is formed in the second covering layer 2300, and the second rewiring layer 2301 and The through silicon vias 123 and the through silicon vias 320 are connected to form an electrical lead-out structure of a three-layer chip stack. As shown in FIG. Part of the lead-out structure of the interconnection layer in the partial-layer chip and a single lead-out structure that electrically connects the interconnection layer of the single-layer chip.
  • the rewiring layer 1201 can connect adjacent through silicon vias 120 and 220, and the through silicon vias 120
  • the through-silicon via 220 has a different depth
  • the rewiring layer 2301 can connect adjacent through-silicon vias 123 and through-silicon vias 320 of different depths.
  • a pad 2302 can be formed on the top rewiring layer 2301 to connect different electrical lead-out structures. Choosing different electrical lead-out structures can achieve stacking of chips in the wafer stack. And some layers of chips or single-layer chips in the chip stack are tested for electrical performance to obtain the specific location of the failed chip.
  • the wafer stack is diced to form an independent chip stack.
  • the electrical performance of the chip stack can be tested after dicing, or the electrical performance of the chip stack can be tested before the dicing. , Complete the screening of unqualified chips, and then perform subsequent packaging operations on the stack of qualified chips.
  • the wafer stack can be cut along the cutting path between the chips in the wafer stack, so that multiple chip stacks can be obtained.
  • a bottom wafer is provided in which chips are arranged in an array, and a hybrid bonding layer is formed on the bottom wafer.
  • the hybrid bonding layer includes a dielectric bonding layer 110 and a metal bonding pad 112 therein , Part of the interconnect layer 111 in the bottom wafer is electrically connected to the metal bonding pad 112, as shown in FIG. 9; in the embodiment of the present application, it is the same as the description in the above-mentioned embodiment of the bonding structure manufacturing method.
  • the bottom wafer is called the first wafer.
  • Each wafer to be bonded is provided, chips are arranged in an array in each wafer to be bonded, a hybrid bonding layer is formed on the wafer to be bonded, and a part of the interconnection in the wafer to be bonded The layer is electrically connected to the metal bonding pad; in the embodiments of the present application, for the consistency of description, each wafer to be bonded is referred to as a first wafer, a second wafer, and so on.
  • the wafers to be bonded are sequentially bonded on the bottom wafer, and after each bonding, a through silicon via is formed, wherein when the wafer to be bonded When there are more than one, after forming the through silicon hole, it further includes: forming a hybrid bonding layer on the through silicon hole, the hybrid bonding layer including a dielectric bonding layer and a metal bonding pad therein, and the crystal to be bonded Part of the through-silicon vias in the circle are electrically connected to the metal bonding pads, thereby forming a wafer stack in which the chip stacks are arranged in an array and an electrical lead-out structure in the chip stack.
  • the electrical lead-out structure includes electrically connecting the chips in each layer The full lead-out structure of the interconnection layer, and the partial lead-out structure that electrically connects the interconnection layer of the partial-layer chip and/or the single lead-out structure that electrically connects the interconnection layer of the single-layer chip.
  • the first dielectric bonding layer 110 on the first wafer and the first metal bonding pad 112 therein are used to interact with the second dielectric bonding layer 210 on the second wafer.
  • the second metal bonding pad 212 is bonded to form a wafer stack.
  • the backside of the substrate 200 of the second wafer can be thinned to simplify the subsequent through silicon via process.
  • chemical Mechanical polishing CMP
  • WET Wet Etching
  • a through silicon via is formed in the bonded wafer to penetrate the interconnection layer in the chip, and the through silicon via 120 penetrates to the first chip 10 on the first wafer.
  • the first chip 10 in the circle is tested for electrical performance and the second chip 20 on the second wafer can be tested for electrical performance.
  • a first cover layer 1200 is formed on the second wafer.
  • a first rewiring layer 1201 and a metal bonding pad 1202 are formed in the first covering layer 1200.
  • the first metal bonding pad 112 and the second metal bonding pad 212 are bonded through silicon connected to the interconnect layer 211.
  • the through hole 220 is connected to the first rewiring layer 1201 to form a two-layer chip stack full lead structure.
  • the through silicon hole 120 is connected to the interconnect layer 111 in the first chip 10, and the through silicon hole 220 is connected to the second chip 20.
  • the interconnection layer 211 is connected to form a single-lead structure that electrically connects the interconnection layers in the single-layer chip.
  • the third wafer can be bonded continuously, and the third dielectric bonding layer 310 in the third wafer can be bonded to the first cover layer 1200, and the third metal bonding pad 312 can be bonded to the first rewiring layer 1201.
  • the bonding of the metal bonding pad 1202 realizes the bonding of the third wafer and the second wafer to form a wafer stack including three-layer wafers.
  • the wafers are formed with arrays of chips. When forming a wafer stack, the chips in the wafer are bonded to form a chip stack, as shown in FIG.
  • a through silicon via process is performed on the chip stack to form a through silicon via, and the through silicon via 123 penetrates to the third wafer
  • the through silicon via 320 penetrates to the first rewiring layer 1201
  • the second rewiring layer 2301 is formed on the through silicon vias 123 and 320
  • the second rewiring layer 2301 is formed on the first rewiring layer.
  • an electrical lead-out structure of a three-layer chip stack is formed.
  • the electrical lead-out structure includes a full lead-out structure that electrically connects the interconnection layers in each layer of the chip, a partial lead-out structure that electrically connects the interconnection layer of the partial-layer chip, and a single lead-out structure that electrically connects the interconnection layer of the single-layer chip.
  • a pad 2302 can be formed on the top rewiring layer 2301 to connect different electrical lead-out structures. Choosing different electrical lead-out structures can achieve stacking of chips in the wafer stack. And some layers of chips or single-layer chips in the chip stack are tested for electrical performance to obtain the specific location of the failed chip, and the failed chip can be selectively bypassed in the follow-up and only the valid chip is connected to reduce the chip scrap rate.
  • the wafer stack is diced to form an independent chip stack.
  • the electrical performance of the chip stack can be tested after dicing, or the electrical performance of the chip stack can be tested before the dicing. , Complete the screening of unqualified chips, and then perform subsequent packaging operations on the stack of qualified chips.
  • the wafer stack can be cut along the cutting path between the chips in the wafer stack, so that multiple chip stacks can be obtained.

Abstract

一种键合结构及其制造方法，由多层晶圆依次键合形成的晶圆堆叠，晶圆堆叠上阵列排布有芯片堆叠，所述芯片堆叠包括依次键合的多层芯片，芯片堆叠中形成有电引出结构，通过在芯片堆叠中形成电连接各层芯片中互连层的全引出结构，可以对整个芯片堆叠进行电性能测试，通过电连接的部分层芯片中的部分引出结构，可以对芯片堆叠中的部分层芯片进行电性能测试，和/或电连接单层芯片中互连层的单引出结构，可以对芯片堆叠中的单层芯片进行电性能测试，从而实现对芯片堆叠中单层或多层芯片的电性能测试，进而得到失效芯片的具体位置。

Description

一种键合结构及其制造方法
本申请要求于2020年02月25日提交中国专利局、申请号为202010115676.0、发明名称为“一种键合结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件及其制造领域，特别涉及一种键合结构及其制造方法。
背景技术
随着半导体技术进入后摩尔时代，为满足高集成度和高性能的需求，芯片结构向着三维方向发展，而晶圆级封装技术得到了广泛的应用，其是利用晶圆级封装技术将不同的晶圆堆叠键合在一起，可以缩短器件间的信号传输路径，提供更多的I/O数量，提高芯片响应速度以及减小芯片体积，同时，可以实现不同技术节点和功能芯片间的互连，降低了设计和工艺难度，从而降低制造成本。然而，随着堆叠层数的增加，芯片失效的几率增加，在芯片堆叠完成后通过电性测试可以获得失效的信息，但却难以追溯到是哪层芯片导致的失效。
发明内容
有鉴于此，本发明的目的在于提供一种键合结构及其制造方法，能够对芯片堆叠中的单层或多层芯片进行测试，得到具体的失效芯片位置。
为实现上述目的，本发明有如下技术方案：
一种键合结构，包括：由多层晶圆依次键合形成的晶圆堆叠，所述晶圆堆叠上阵列排布有芯片堆叠，所述芯片堆叠包括依次键合的多层芯片，所述芯片堆叠中形成有电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
可选的，所述晶圆堆叠中的晶圆之间通过介质键合层键合，所述电引出结构包括硅通孔和与其连接的再布线层。
可选的，至少部分所述再布线层连接不同深度的硅通孔。
可选的，所述晶圆堆叠中的晶圆之间通过混合键合结构键合，所述混合键合结构包括介质键合层和其中的金属键合垫，相邻层晶圆的金属键合垫键合在一起，部分所述电引出结构包括金属键合垫及与其连接的硅通孔，部分所述电引出结构包括硅通孔。
一种键合结构，包括芯片堆叠，所述芯片堆叠包括依次键合的多层芯片，所述芯片堆叠中形成有电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
一种键合结构的制造方法，包括：
提供底层晶圆，所述底层晶圆中阵列排布有芯片，所述底层晶圆上形成有介质键合层；
提供各待键合晶圆，各所述待键合晶圆中阵列排布有芯片，所述待键合晶圆上形成有介质键合层；
利用所述介质键合层在所述底层晶圆上依次键合所述各待键合晶圆，并在每次键合之后，形成硅通孔以及与其电连接的再布线层，以形成阵列排布有芯片堆叠的晶圆堆叠以及所述芯片堆叠中的电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
可选的，至少部分所述再布线层连接不同深度的硅通孔。
可选的，还包括：
在顶层再布线层上形成衬垫。
可选的，还包括:
将所述晶圆堆叠进行切割，以形成独立的芯片堆叠。
一种键合结构的制造方法，包括：
提供底层晶圆，所述底层晶圆中阵列排布有芯片，所述底层晶圆上形成有混合键合层，所述混合键合层包括介质键合层和其中的金属键合垫，所述底层 晶圆中部分的互连层与金属键合垫电连接；
提供各待键合晶圆，各待键合晶圆中阵列排布有芯片，所述待键合晶圆上形成有混合键合层，所述待键合晶圆中部分的互连层与金属键合垫电连接；
利用所述混合键合层，在所述底层晶圆上依次键合所述各待键合晶圆，并在每次键合之后，形成硅通孔，其中，当所述待键合晶圆为多个时，在形成硅通孔之后，还包括：在硅通孔之上形成混合键合层，所述混合键合层包括介质键合层和其中的金属键合垫，所述待键合晶圆中部分硅通孔电连接至金属键合垫，从而，形成阵列排布有芯片堆叠的晶圆堆叠以及所述芯片堆叠中的电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
可选的，在形成硅通孔之后，还包括：在硅通孔上形成再布线层。
可选的，还包括：
在顶层再布线层上形成衬垫。
可选的，还包括:
将所述晶圆堆叠进行切割，以形成独立的芯片堆叠。
本发明实施例提供的一种键合结构，由多层晶圆依次键合形成的晶圆堆叠，晶圆堆叠上阵列排布有芯片堆叠，芯片堆叠包括依次键合的多层芯片，芯片堆叠中形成有电引出结构，电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。通过在芯片堆叠中形成电连接各层芯片中互连层的全引出结构，可以对整个芯片堆叠进行电性能测试，通过电连接部分层芯片中的部分引出结构，可以对芯片堆叠中的部分层芯片进行电性能测试，和/或电连接单层芯片中互连层的单引出结构，可以对芯片堆叠中的单层芯片进行电性能测试，从而实现对芯片堆叠中单层或多层芯片的电性能测试，进而得到失效芯片的具体位置。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1-15示出了根据本发明实施例的制造方法形成键合结构过程中的结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
正如背景技术中的描述，随着半导体技术进入后摩尔时代，为满足高集成度和高性能的需求，芯片结构向着三维方向发展，而晶圆级封装技术得到了广泛的应用，其是利用晶圆级封装技术将不同的晶圆堆叠键合在一起，可以缩短器件间的信号传输路径，提供更多的I/O数量，提高芯片响应速度以及减小芯片体积，同时，可以实现不同技术节点和功能芯片间的互连，降低了设计和工艺难度，从而降低制造成本。然而，随着堆叠层数的增加，芯片失效的几率增加，在芯片堆叠完成后通过电性测试可以获得失效的信息，但却难以追溯到是哪层芯片导致的失效。
为此，本发明实施例提供的一种键合结构，由多层晶圆依次键合形成的晶圆堆叠，晶圆堆叠中阵列排布有依次键合的多层芯片，芯片堆叠中形成有电引 出结构，电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。通过在芯片堆叠中形成电连接各层芯片中互连层的全引出结构，可以对整个芯片堆叠进行电性能测试，通过电连接部分层芯片中的部分引出结构，可以对芯片堆叠中的部分层芯片进行电性能测试，和/或电连接单层芯片中互连层的单引出结构，可以对芯片堆叠中的单层芯片进行电性能测试，从而实现对芯片堆叠中单层或多层芯片的电性能测试，进而得到失效芯片的具体位置。
为了更好的理解本申请的技术方案和技术效果，以下将结合附图对具体的实施例进行详细的描述。
本申请实施例中，由多层晶圆依次键合形成的晶圆堆叠，所述晶圆堆叠中阵列排布有芯片堆叠，所述芯片堆叠包括依次键合的多层芯片，所述芯片堆叠中形成有电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
本申请实施例中，晶圆堆叠可以是两层或两层以上晶圆依次键合形成的晶圆堆叠，每一层晶圆上可以形成有多个阵列排布的芯片，在多层晶圆键合形成晶圆堆叠时，各层晶圆中的芯片依次键合形成芯片堆叠，从而使得晶圆堆叠上阵列排布有芯片堆叠，芯片堆叠中的各层芯片可以已在衬底上形成有器件结构以及电连接器件结构的互连层，器件结构可以包括MOS场效应晶体管器件、存储器件和/或其他无源器件，每一层芯片上的器件结构可以相同，可以不同，器件结构由介质键合层覆盖，该介质键合层可以为单层或叠层结构，例如可以包括层间介质层和金属间介质层，介质键合层为键合用介质材料，例如可以为氧化硅(bonding oxide)、氮化硅、NDC(Nitrogen doped Silicon Carbide，掺氮碳化硅)或者他们的组合，互连层形成于介质键合层中，互连层可以为多层，不同层的互连层可以通过接触塞、过孔等实现互连，互连层可以为金属材料，例如可以为钨、铝、铜等。
芯片堆叠中还可以形成有电引出结构，电引出结构与互连层连接，从而可 以实现多层芯片中的器件结构的互连。电引出结构可以包括全引出结构以及部分引出结构和/或单引出结构，全引出结构可以实现芯片堆叠中各层芯片中器件的互连，从而对各层芯片进行电性能测试，部分引出结构可以实现芯片堆叠中部分层芯片的互连，从而对部分层芯片进行电性能测试，单引出结构可以引出芯片堆叠中的单层芯片，实现单层芯片的电性能测试。
以下结合附图1-15对键合结构的不同的实施例进行详细的说明，但是本申请的技术方案并不局限于以下实施例，任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。
实施例一
本实施例中，晶圆堆叠中的晶圆之间通过介质键合层键合，电引出结构包括硅通孔和与其连接的再布线层，在晶圆堆叠上形成有阵列排布的芯片堆叠，利用硅通孔工艺在芯片堆叠中形成电引出结构，进而可以实现对晶圆堆叠上的芯片堆叠中的单层或多层芯片的电性能测试。
以晶圆数量为3为例，对键合结构进行详细的说明。第一晶圆与第二晶圆通过第一介质键合层110和第二介质键合层210键合在一起，第二晶圆与第三晶圆通过第一覆盖层1200和第三介质键合层310键合在一起，在晶圆键合形成晶圆堆叠的同时，晶圆上的芯片依次键合形成芯片堆叠，从而使得该晶圆堆叠上阵列排布有芯片堆叠，本实施例中，仅对晶圆堆叠中的一个芯片堆叠进行详细的描述，并且为了便于后续的描述将该芯片堆叠中的三层芯片分别称为第一芯片10、第二芯片20和第三芯片30，参考图7所示。
本实施例中，该芯片堆叠中形成的电引出结构包括硅通孔和与其连接的再布线层，可以包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构，例如其中两层芯片，和/或电连接其中一层芯片中互连层的单引出结构。
电连接各层芯片中互连层的全引出结构可以包括贯通至第一芯片10中互连层111的硅通孔120、贯通至第二芯片20中互连层211的硅通孔220、贯通 至第三芯片30中互连层311的硅通孔320以及第一再布线层1201、第二再布线层2301、第一再布线层1201连接相邻的不同深度的硅通孔120和硅通孔220，从而将第一芯片10和第二芯片20连接，第二再布线层2301连接相邻的不同深度的硅通孔123与硅通孔320，并且硅通孔123将第一再布线层1201和第二再布线层2301连接，从而通过第一再布线层1201和第二再布线层2301将硅通孔120、硅通孔220、硅通孔320连接在一起，实现第一芯片10、第二芯片20和第三芯片30的互连，进而可以对晶圆堆叠上形成的芯片堆叠进行电性能测试，测试合格说明芯片堆叠中的芯片均为有效芯片，可以进行后续的封装等操作，测试不合格说明芯片堆叠中存在失效芯片，可以后续对芯片堆叠中的部分层或单层芯片进行测试，得到失效芯片的具体位置。
电连接部分层芯片中互连层的部分引出结构可以包括硅通孔120、硅通孔220、硅通孔123以及第一再布线层1201、第二再布线层2301，第一再布线层1201连接相邻的不同深度的硅通孔120和硅通孔220，从而实现第一芯片10和第二芯片20的相连，而后通过硅通孔123以及第二再布线层2301将第一芯片10和第二芯片20引出，从而可以对第一芯片10和第二芯片20进行电性能测试，测试合格说明第一芯片10和第二芯片20中的芯片为合格芯片，测试不合格说明第一芯片10或第二芯片20中存在不合格芯片或者两层芯片均为不合格芯片，可以后续对第一芯片10和第二芯片20分别进行电性能测试，得到具体的失效芯片的位置。
电连接部分层芯片中互连层的部分引出结构还可以包括硅通孔120、硅通孔123、硅通孔320以及第一再布线层1201、第二再布线层2301，第一再布线层1201连通硅通孔120和硅通孔123，第二再布线层2301连接相邻的不同深度的硅通孔123和硅通孔320连接，从而使得硅通孔120与硅通孔320相连，实现第一芯片10与第三芯片30的相连，从而可以对第一芯片10和第三芯片30进行电性能测试，测试合格说明第一芯片10和第三芯片30中的芯片为合格芯片，测试不合格说明第一芯片10或第三芯片30中存在不合格芯片或两层芯片均为不合格芯片，可以后续对第一芯片10和第三芯片30分别进行电性能 测试，得到具体的失效芯片的位置。
电连接部分层芯片中互连层的部分引出结构还可以包括硅通孔220、硅通孔123、硅通孔320以及第一再布线层1201、第二再布线层2301，第一再布线层1201将硅通孔220与硅通孔123连接，第二再布线层2301连接相邻的不同深度的硅通孔123和硅通孔320，从而使得第二芯片20中的硅通孔220与第三芯片30中的硅通孔320连通，实现第二芯片20和第三芯片30的相连，而后可以对第二芯片20和第三芯片30进行电性能测试，测试合格说明第二芯片20和第三芯片30中的芯片为合格芯片，测试不合格说明第二芯片20或第三芯片30中存在不合格芯片或两层芯片均为不合格芯片，可以后续对第二芯片20和第三芯片30分别进行电性能测试，得到具体的失效芯片的位置。
电连接单层芯片中互连层的单引出结构可以包括硅通孔120、硅通孔123以及第一再布线层1201、第二再布线层2301，第一再布线层1201连通硅通孔123和硅通孔120，而后通过与硅通孔123连接的第二再布线层2301将第一芯片10中的互连层111引出，从而实现对芯片堆叠中第一芯片10进行电性能测试。
电连接单层芯片中互连层的单引出结构可以包括硅通孔220、硅通孔123以及第一再布线层1201、第二再布线层2301，第一再布线层1201将硅通孔220与硅通孔123连接，而后通过与硅通孔123连接的第二再布线层2301将第二芯片20的互连层211引出，从而可以对芯片堆叠中第二芯片20进行电性能测试。
电连接单层芯片中互连层的单引出结构可以包括硅通孔320、第二再布线2301，第二再布线层2301与硅通孔320相连，将第三芯片30中的互连层311引出，从而可以对芯片堆叠中第三芯片30进行电性能测试。
上述实施例中的键合结构通过硅通孔工艺在芯片堆叠中形成包括硅通孔和与其连接的再布线层的电引出结构，可以对芯片堆叠中单层或多层芯片进行电性能测试，从而能够得出具体的失效芯片的位置，以便于选择性绕过失效芯片，仅连接有效芯片，降低芯片报废率。
实施例二
本实施例中，晶圆堆叠中的晶圆之间通过混合键合结构键合，所述混合键合结构包括介质键合层和其中的金属键合垫，相邻层晶圆的金属键合垫键合在一起，部分所述电引出结构包括金属键合垫及其连接的硅通孔，部分所述电引出结构包括硅通孔。该晶圆堆叠中的晶圆在混合键合之后，利用硅通孔工艺形成包括金属键合垫及其连接的硅通孔的电引出结构或包括硅通孔的电引出结构，进而可以对晶圆堆叠上阵列排布的芯片堆叠中的单层或多层芯片进行电性能测试。
本实施例中，晶圆之间通过混合键合结构键合，混合键合结构是指键合界面由不同材质的键合材料(bonding)形成，本申请中，该混合键合结构包括介质键合层和其中的金属键合垫，金属键合垫与介质键合层中的互连层电连接，金属键合垫可以形成于互连层上，实现晶圆中的芯片之间的电连接或者是芯片中互连层的电引出。介质键合层为键合用介质材料，可以为单层或多层结构，例如可以为氧化硅(bonding oxide)、氮化硅、NDC(Nitrogen doped Silicon Carbide，掺氮碳化硅)或者他们的组合，金属键合垫可以为键合金属材料，例如可以为铜。
参考图14所示，以晶圆数量为3为例，对键合结构进行详细的说明。为了便于描述，将三层晶圆分别称为第一晶圆、第二晶圆和第三晶圆，第一晶圆中的第一介质键合层110与第二晶圆中的第二介质键合层210键合，同时第一介质键合层110中的第一金属键合垫112与第二介质键合层210中的第二金属键合垫212键合，实现第一晶圆和第二晶圆的键合。第二晶圆上的第一覆盖层1200与第三晶圆中的第三介质键合层310键合，同时第一覆盖层1200中的金属键合垫1202与第三介质键合层310中的第三金属键合垫312键合，实现第二晶圆与第三晶圆的键合，从而形成包含三层晶圆的晶圆堆叠，也可以在第三晶圆上继续键合形成包含更多层晶圆的晶圆堆叠。本实施例中，介质键合层中的金属键合垫可以与介质键合层中的互连层一同形成。
本申请实施例中，在晶圆键合形成晶圆堆叠的同时，晶圆上的芯片依次键 合形成芯片堆叠，从而使得该晶圆堆叠上阵列排布有芯片堆叠，本实施例中，仅对晶圆堆叠中的一个芯片堆叠进行详细的描述，并且为了便于后续的描述将晶圆堆叠上的一个芯片堆叠中的三层芯片分别称为第一芯片10、第二芯片20和第三芯片30，参考图14所示。
本实施例中，芯片堆叠中形成的电引出结构中，部分电引出结构包括金属键合垫及与其连接的硅通孔，部分电引出结构包括硅通孔，电引出结构可以包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
本实施例中，参考图14所示，电连接各层芯片中互连层的全引出结构可以包括第一金属键合垫112、第二金属键合垫212、硅通孔220、第一再布线层1201及其上方的金属键合垫1202、以及第三金属键合垫312、硅通孔123、第二再布线层2301，第一金属键合垫112和第二金属键合垫212键合，实现第一芯片10和第二芯片20的互连，而后通过硅通孔220与第一再布线层1201连接，第一再布线层1201上方的金属键合垫1202与第三芯片30中的第三金属键合垫312键合，使得第一芯片10中的互连层111与第二芯片20中的互连层211以及第三芯片30中的互连层311连接在一起，实现第一芯片10、第二芯片20和第三芯片30的互连，随后由与硅通孔123相连的第二再布线层2301将芯片堆叠引出，形成包括金属键合垫及与其连接的硅通孔的电引出结构，实现对芯片堆叠的电性能测试，测试合格说明芯片堆叠中各层芯片均为合格的芯片，测试不合格可以后续对其中两层或其中一层芯片进行电性能测试，得到失效芯片的具体位置。
电连接部分层芯片中互连层的部分引出结构可以包括第一金属键合垫112、第二金属键合垫212以及其上的硅通孔，第一金属键合垫112与第二金属键合垫212键合，实现第一芯片10和第二芯片20的互连，而后形成贯穿至第二金属键合垫212上方的互连层211的硅通孔220、320以及第一再布线层1201和第二再布线层2301，从而形成包括硅通孔和金属键合垫的部分引出结构，第一再布线层1201连接硅通孔220与硅通孔320，而后通过与硅通孔320 电连接的第二再布线层2301将第一芯片10和第二芯片20引出，进而可以对第一芯片10和第二芯片20进行电性能测试。
电连接部分层芯片中互连层的部分引出结构还可以包括贯通至第二芯片20中的互连层211的硅通孔220、第一再布线层1201及其上方的金属键合垫1202以及第三芯片30中的第三金属键合垫312、贯通至第三芯片30中互连层311的硅通孔123、第二再布线层2301，第一再布线层1201上方的金属键合垫1202与第三金属键合垫312键合后，通过硅通孔220将第二芯片20中互连层211引出，并通过硅通孔123与第二再布线层2301连接，从而形成连通第二芯片20和第三芯片30的部分电引出结构，实现对第二芯片20和第三芯片30的电性能测试。
电连接部分层芯片中互连层的部分电引出结构还可以包括贯通至第一芯片10中互连层111的硅通孔120、第一再布线层1201及其上的金属键合垫1202以及第三芯片30中的第三金属键合垫312、贯通至第三芯片30中互连层311的硅通孔123、第二再布线层2301，第一再布线层1201上方的金属键合垫1202与第三金属键合垫312键合并与硅通孔120连接，将第一芯片10中的互连层111与第三芯片30中的互连层311连接，而后通过硅通孔123以及与其连接的第二再布线层2301，将第一芯片10和第三芯片30中的互连层引出，形成连通第一芯片10和第三芯片30的部分引出结构，实现对第一芯片10和第三芯片30的电性能测试。
电连接单层芯片中互连层的单引出结构可以包括贯通至第一芯片10中互连层111的硅通孔120、硅通孔320以及第一再布线层1201、第二再布线层2301，第一再布线层1201将硅通孔120和硅通孔320连接，硅通孔320与第二再布线层2301连接，将第一芯片10中的互连层111引出，形成包括硅通孔的电引出结构，从而实现对芯片堆叠中第一芯片10的电性能测试。
电连接单层芯片中互连层的单引出结构还可以包括贯通至第二芯片20中的互连层211的硅通孔220、硅通孔320以及第一再布线层1201、第二再布线层2301，第一再布线层1201将硅通孔220与硅通孔320连接，硅通孔320与 第二再布线层2301，将第二芯片20中的互连层211引出，形成包括硅通孔的电引出结构，从而实现对芯片堆叠中第二芯片20的电性能测试。
电连接单层芯片中互连层的单引出结构可以包括贯通至第三芯片30中互连层311的硅通孔123、第二再布线层2301，第二再布线层2301将第三芯片30中的互连层311引出，形成包括硅通孔的电引出结构，从而可以实现对芯片堆叠中第三芯片30的电性能测试。
上述键合结构通过混合键合工艺和硅通孔工艺在芯片堆叠中形成电引出结构，部分所述电引出结构包括金属键合垫及其连接的硅通孔，部分所述电引出结构包括硅通孔，可以对芯片堆叠中单层或多层芯片进行电性能测试，从而能够得出具体的失效芯片的位置。
而后，可以对键合结构进行封装工艺，在封装过程中能够选择性地连接有效芯片，避免连接失效芯片的电引出结构，充分利用有效的芯片，降低报废率。
以上对本申请实施例的一种键合结构进行了详细的描述，此外，本申请实施例还提供了另一种键合结构，包括芯片堆叠，所述芯片堆叠包括依次键合的多层芯片，所述芯片堆叠中形成有电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
本实施例中，通过芯片堆叠中的全引出结构可以对芯片堆叠中的各层芯片进行电性能测试，通过芯片堆叠中的部分引出结构可以对芯片中的部分层芯片进行电性能测试，通过芯片堆叠中的单引出结构可以对芯片堆叠中的某一层芯片进行电性能测试。
在具体的实施例中，可以先通过全引出结构对芯片堆叠中的电连接在一起的各层芯片进行电性能测试，测试合格说明此芯片堆叠中不存在失效芯片，可以对该芯片堆叠进行后续的封装等操作，测试不合格说明芯片堆叠中存在失效芯片，而后可以对电连接在一起的某几层芯片进行电性能测试，若这几层芯片测试合格，可以继续对其他层芯片进行电性能测试，若这几层芯片测试不合格，说明这几层芯片中存在失效芯片，可以通过单引出结构继续对这几层芯片中的 各层芯片进行单独的电性能测试，进而可以得到具体的失效位置，这样不需要对芯片堆叠中的每一层芯片进行单独的电性能测试，提高电性能测试的效率。
以上对键合结构进行了详细描述，以下结合附图1-15对键合结构的制造方法的不同的实施例进行详细的描述，但是本申请的技术方案并不局限于以下实施例，任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。
在本实施例中，结合附图对1-8对一种键合结构的制造方法进行详细的描述。
参考图1所示，提供底层晶圆，所述底层晶圆中阵列排布有芯片10，所述底层晶圆上形成有介质键合层110；本申请实施例中的底层晶圆也可以称之为第一晶圆。
提供各待键合晶圆，各所述待键合晶圆中阵列排布有芯片，所述待键合晶圆上形成有介质键合层；本申请实施例中的各待键合晶圆可以分别称之为第二晶圆、第三晶圆等等。
利用介质键合层在底层晶圆上依次键合各待键合晶圆，并在每次键合之后，形成硅通孔以及与其电连接的再布线层，以形成阵列排布有芯片堆叠的晶圆堆叠以及所述芯片堆叠中的电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
本实施例中，为了使得说明书的描述更加清楚，以下将底层晶圆称之为第一晶圆，将各待键合晶圆分别称之为第二晶圆、第三晶圆等等。参考图1所示，图1示出的是第一晶圆中的一个芯片结构称之为第一芯片10。利用第一晶圆上的介质键合层110以及第二晶圆上的介质键合层210，将第一晶圆与第二晶圆键合形成晶圆堆叠，可以在键合后对第二晶圆的衬底200背面进行减薄，以简化后续的硅通孔工艺，例如可以采用化学机械研磨(Chemical Mechanism Polishing，CMP)、湿法刻蚀(Wet Etching，WET)工艺对第二晶圆的背面进 行减薄。参考图2所示，为第一晶圆和第二晶圆键合后形成的晶圆堆叠中的一个芯片堆叠的结构。
参考图3所示，在键合后的晶圆内形成贯通至芯片中互连结构的硅通孔(Through Silicon Via，TSV)，可以在硅通孔侧壁形成有绝缘介质层，例如可以为氧化硅、氮化硅等，而后在硅通孔中填充金属材料，例如可以为钨、铝、铜等，硅通孔120连通至第一晶圆上的第一芯片10中的互连层111，硅通孔220连通至第二晶圆上的第二芯片20中的互连层211，从而能够将第一晶圆中的第一芯片10和第二晶圆中的第二芯片20中的互连层分别引出，实现对第一芯片10和第二芯片20的电性能测试，而后，参考图4所示，在第二晶圆上形成第一覆盖层1200，在第一覆盖层1200中形成第一再布线层1201，第一覆盖层1200可以为单层或叠层结构，可以与介质键合层的材料相同，也可以不同，第一再布线层1201可以为金属材料，例如可以为钨、铝、铜等。第一再布线层1201连接硅通孔120与硅通孔220，从而实现第一晶圆上的第一芯片10中的互连层111以及第二晶圆上的第二芯片20中的互连层211的相连，形成电连接芯片堆叠中的互连层的全引出结构，硅通孔120与第一再布线层1201的连接以及硅通孔220与第一再布线层1201的连接，形成电连接单层芯片中互连层的单引出结构。
而后，继续键合第三晶圆，可以通过第三晶圆上的第三介质键合层310与覆盖层1200的键合，实现第三晶圆与第二晶圆的键合，形成包含三层晶圆的晶圆堆叠，参考图5所示，图5示出了包含三层晶圆的晶圆堆叠中的一个芯片堆叠的结构，随后对该芯片堆叠进行硅通孔工艺，形成连通至第一再布线层1201的硅通孔123以及连通至第三晶圆上的第三芯片30中的互连层311的硅通孔320，参考图6所示，而后在第三晶圆上形成第二覆盖层2300，第二覆盖层2300的材料可以与第一覆盖层1200的材料相同，也可以不同，第二覆盖层2300中形成有第二再布线层2301，第二再布线层2301与硅通孔123以及硅通孔320相连，从而形成三层芯片堆叠的电引出结构，参考图7所示，该电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互 连层的部分引出结构以及电连接单层芯片中互连层的单引出结构。
本实施例中，至少部分再布线层连接相邻的不同深度的硅通孔，参考图7所示，再布线层1201可以连接相邻的硅通孔120和硅通孔220，硅通孔120和硅通孔220具有不同的深度，再布线层2301可以连接相邻的不同深度的硅通孔123和硅通孔320。
本实施例中，参考图8所示，可以在顶层再布线层2301上形成衬垫2302，从而将不同的电引出结构接出，选择不同的电引出结构可以实现对晶圆堆叠中的芯片堆叠以及芯片堆叠中的部分层芯片或单层芯片进行电性能测试，得到失效芯片具体的位置。
本实施例中，在形成晶圆堆叠后，对晶圆堆叠进行切割，以形成独立的芯片堆叠，可以在切割之后对芯片堆叠进行电性能测试，也可以在切割之前对芯片堆叠进行电性能测试，完成不合格芯片的筛除，而后可以对合格的芯片堆叠进行后续的封装操作。本实施例中，可以沿着晶圆堆叠中芯片之间的切割道，对晶圆堆叠进行切割，从而可以得到多个芯片堆叠。
下面结合附图9-15对本申请实施例中另一种键合结构的制造方法进行详细的描述。
提供底层晶圆，所述底层晶圆中阵列排布有芯片，所述底层晶圆上形成有混合键合层，所述混合键合层包括介质键合层110和其中的金属键合垫112，底层晶圆中部分的互连层111与金属键合垫112电连接，参考图9所示；本申请实施例中，与上述关于键合结构的制造方法的实施例中的描述相同，将底层晶圆称之为第一晶圆。
提供各待键合晶圆，各所述待键合晶圆中阵列排布有芯片，所述待键合晶圆上形成有混合键合层，所述待键合晶圆中部分的互连层与金属键合垫电连接；本申请实施例中，为了描述的一致性，将各待键合晶圆分别称之为第一晶圆、第二晶圆等等。
利用所述混合键合层，在所述底层晶圆上依次键合所述各待键合晶圆，并在每次键合之后，形成硅通孔，其中，当所述待键合晶圆为多个时，在形成硅 通孔之后，还包括：在硅通孔之上形成混合键合层，所述混合键合层包括介质键合层和其中的金属键合垫，待键合晶圆中部分硅通孔电连接至金属键合垫，从而，形成阵列排布有芯片堆叠的晶圆堆叠以及所述芯片堆叠中的电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
本实施例中，参考图10所示，利用第一晶圆上的第一介质键合层110以及其中的第一金属键合垫112，与第二晶圆上的第二介质键合层210以及其中的第二金属键合垫212键合，形成晶圆堆叠，可以在键合后对第二晶圆的衬底200背面进行减薄，以简化后续的硅通孔工艺，例如可以采用化学机械研磨(Chemical Mechanism Polishing，CMP)、湿法刻蚀(Wet Etching，WET)工艺对第二晶圆的背面进行减薄。
参考图11所示，在键合后的晶圆内形成贯通至芯片中互连层的硅通孔(Through Silicon Via，TSV)，硅通孔120贯通至第一晶圆上的第一芯片10中的互连层111，硅通孔220贯通至第二晶圆上的第二芯片20中的互连层211，从而能够将第一芯片10和第二芯片20分别引出，可以对第一晶圆中的第一芯片10进行电性能测试以及可以对第二晶圆中的第二芯片20进行电性能测试，而后，参考图12所示，在第二晶圆上形成第一覆盖层1200，在第一覆盖层1200中形成第一再布线层1201以及其中的金属键合垫1202，第一金属键合垫112与第二金属键合垫212键合后通过与互连层211连接的硅通孔220与第一再布线层1201连接，形成两层芯片堆叠的全引出结构，硅通孔120与第一芯片10中的互连层111连接以及硅通孔220与第二芯片20中的互连层211的连接，形成电连接单层芯片中互连层的单引出结构。
而后，可以继续键合第三晶圆，可以通过第三晶圆中的第三介质键合层310与第一覆盖层1200键合以及第三金属键合垫312与第一再布线层1201上方的金属键合垫1202的键合，实现第三晶圆与第二晶圆的键合，形成包含三层晶圆的晶圆堆叠，晶圆上形成有阵列排布的芯片，在晶圆键合形成晶圆堆叠 时，晶圆中的芯片键合形成芯片堆叠，参考图13所示，随后对该芯片堆叠进行硅通孔工艺，形成硅通孔，硅通孔123贯通至第三晶圆上的第三芯片30的互连层311，硅通孔320贯通至第一再布线层1201，在硅通孔123、320上形成第二再布线层2301，第二再布线层2301形成于第二覆盖层2300中，参考图14所示，从而形成三层芯片堆叠的电引出结构。该电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构以及电连接单层芯片中互连层的单引出结构。
本实施例中，参考图15所示，可以在顶层再布线层2301上形成衬垫2302，从而将不同的电引出结构接出，选择不同的电引出结构可以实现对晶圆堆叠中的芯片堆叠以及芯片堆叠中的部分层芯片或单层芯片进行电性能测试，得到失效芯片具体的位置，可以在后续选择性地绕过失效芯片，仅连接有效芯片，降低芯片报废率。
本实施例中，在形成晶圆堆叠后，对晶圆堆叠进行切割，以形成独立的芯片堆叠，可以在切割之后对芯片堆叠进行电性能测试，也可以在切割之前对芯片堆叠进行电性能测试，完成不合格芯片的筛除，而后可以对合格的芯片堆叠进行后续的封装操作。本实施例中，可以沿着晶圆堆叠中芯片之间的切割道，对晶圆堆叠进行切割，从而可以得到多个芯片堆叠。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其它实施例的不同之处。
以上所述仅是本发明的优选实施方式，虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (13)

  1. 一种键合结构，其特征在于，包括：由多层晶圆依次键合形成的晶圆堆叠，所述晶圆堆叠上阵列排布有芯片堆叠，所述芯片堆叠包括依次键合的多层芯片，所述芯片堆叠中形成有电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
  2. 根据权利要求1所述的结构，其特征在于，所述晶圆堆叠中的晶圆之间通过介质键合层键合，所述电引出结构包括硅通孔和与其连接的再布线层。
  3. 根据权利要求2所述的结构，其特征在于，至少部分所述再布线层连接不同深度的硅通孔。
  4. 根据权利要求1所述的结构，其特征在于，所述晶圆堆叠中的晶圆之间通过混合键合结构键合，所述混合键合结构包括介质键合层和其中的金属键合垫，相邻层晶圆的金属键合垫键合在一起，部分所述电引出结构包括金属键合垫及与其连接的硅通孔，部分所述电引出结构包括硅通孔。
  5. 一种键合结构，其特征在于，包括芯片堆叠，所述芯片堆叠包括依次键合的多层芯片，所述芯片堆叠中形成有电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
  6. 一种键合结构的制造方法，其特征在于，包括：
    提供底层晶圆，所述底层晶圆中阵列排布有芯片，所述底层晶圆上形成有介质键合层；
    提供各待键合晶圆，各所述待键合晶圆中阵列排布有芯片，所述待键合晶圆上形成有介质键合层；
    利用所述介质键合层在所述底层晶圆上依次键合所述各待键合晶圆，并在每次键合之后，形成硅通孔以及与其电连接的再布线层，以形成阵列排布有芯片堆叠的晶圆堆叠以及所述芯片堆叠中的电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分 引出结构和/或电连接单层芯片中互连层的单引出结构。
  7. 根据权利要求6所述的制造方法，其特征在于，至少部分所述再布线层连接不同深度的硅通孔。
  8. 根据权利要求6或7所述的制造方法，其特征在于，还包括：
    在顶层再布线层上形成衬垫。
  9. 根据权利要求6所述的制造方法，其特征在于，还包括：
    将所述晶圆堆叠进行切割，以形成独立的芯片堆叠。
  10. 一种键合结构的制造方法，其特征在于，包括：
    提供底层晶圆，所述底层晶圆中阵列排布有芯片，所述底层晶圆上形成有混合键合层，所述混合键合层包括介质键合层和其中的金属键合垫，所述底层晶圆中部分的互连层与金属键合垫电连接；
    提供各待键合晶圆，各所述待键合晶圆中阵列排布有芯片，所述待键合晶圆上形成有混合键合层，所述待键合晶圆中部分的互连层与金属键合垫电连接；
    利用所述混合键合层，在所述底层晶圆上依次键合所述各待键合晶圆，并在每次键合之后，形成硅通孔，其中，当所述待键合晶圆为多个时，在形成硅通孔之后，还包括：在硅通孔之上形成混合键合层，所述混合键合层包括介质键合层和其中的金属键合垫，所述待键合晶圆中部分硅通孔电连接至金属键合垫，从而，形成阵列排布有芯片堆叠的晶圆堆叠以及所述芯片堆叠中的电引出结构，所述电引出结构包括电连接各层芯片中互连层的全引出结构，以及电连接部分层芯片中互连层的部分引出结构和/或电连接单层芯片中互连层的单引出结构。
  11. 根据权利要求10所述的方法，其特征在于，在形成硅通孔之后，还包括：在硅通孔上形成再布线层。
  12. 根据权利要求11所述的制造方法，其特征在于，还包括：
    在顶层再布线层上形成衬垫。
  13. 根据权利要求10所述的方法，其特征在于，还包括：
    将所述晶圆堆叠进行切割，以形成独立的芯片堆叠。
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