TWI735008B - 積體電路裝置的封裝及其形成方法 - Google Patents

積體電路裝置的封裝及其形成方法 Download PDF

Info

Publication number
TWI735008B
TWI735008B TW108125364A TW108125364A TWI735008B TW I735008 B TWI735008 B TW I735008B TW 108125364 A TW108125364 A TW 108125364A TW 108125364 A TW108125364 A TW 108125364A TW I735008 B TWI735008 B TW I735008B
Authority
TW
Taiwan
Prior art keywords
die
bonding pad
bonding
dummy
pad
Prior art date
Application number
TW108125364A
Other languages
English (en)
Other versions
TW202020998A (zh
Inventor
陳憲偉
陳明發
胡致嘉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202020998A publication Critical patent/TW202020998A/zh
Application granted granted Critical
Publication of TWI735008B publication Critical patent/TWI735008B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H01L2224/06517—Bonding areas having different functions including bonding areas providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0951—Function
    • H01L2224/09515—Bonding areas having different functions
    • H01L2224/09517—Bonding areas having different functions including bonding areas providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種方法包括：對第一晶粒的半導體基底進行研磨以顯 露出延伸至半導體基底中的第一穿孔；在半導體基底上形成介電層；以及在介電層中形成多個接合墊。所述多個接合墊包括主動接合墊及虛擬接合墊。主動接合墊電性耦合至第一穿孔。將第一晶粒接合至第二晶粒，且主動接合墊及虛擬接合墊二者接合至第二晶粒中對應的接合墊。

Description

積體電路裝置的封裝及其形成方法
本發明實施例是關於體電路裝置的封裝及其形成方法。
隨著更多裝置晶粒封裝於同一封裝中以達成更多功能，積體電路的封裝變得越來越複雜。舉例而言，封裝結構已發展至在同一封裝中包括例如處理器及記憶體立方體等多個裝置晶粒。封裝結構可包括利用不同技術形成且具有不同功能的裝置晶粒，其接合至同一裝置晶粒，因而會形成系統。此可節省製造成本且使裝置效能最佳化。舉例而言，記憶體晶粒可接合至邏輯晶粒。此外，記憶體晶粒可形成記憶體晶粒堆疊，其中上部記憶體晶粒接合至對應的下部記憶體晶粒。
根據本揭露的一些實施例，一種體電路裝置的封裝的形成方法包括：對第一晶粒的半導體基底進行研磨以顯露出延伸至所述半導體基底中的第一穿孔；在所述半導體基底上形成介電層；在所述介電層中形成多個接合墊，其中所述多個接合墊包括第一主動接合墊及第一虛擬接合墊，其中所述第一主動接合墊電 性耦合至所述第一穿孔；以及將所述第一晶粒接合至第二晶粒，其中所述第一主動接合墊及所述第一虛擬接合墊二者接合至所述第二晶粒中對應的接合墊。
根據本揭露的一些實施例，一種方法包括形成第一晶粒，所述第一晶粒包括第一半導體基底；以及第一穿孔，穿透第一半導體基底。所述方法更包括形成第二晶粒，所述第二晶粒包括第二半導體基底；第二穿孔，穿透所述第二半導體基底；第一主動接合墊；以及第一懸空接合墊。將所述第二晶粒接合於所述第一晶粒之上，其中所述第一主動接合墊藉由所述第一晶粒與所述第二晶粒之間的第二主動接合墊電性耦合至所述第一晶粒，且所述第一懸空接合墊接合至所述第一晶粒與所述第二晶粒之間的第一虛擬接墊。
根據本揭露的一些實施例，積體電路裝置的封裝包括：第一晶粒，所述第一晶粒包括第一半導體基底；第一穿孔，穿透所述第一半導體基底；以及第一介電層，位於所述第一半導體基底之上且接觸所述第一半導體基底；第二介電層，位於所述第一晶粒之上；第一主動接合墊，位於所述第二介電層中，所述第一主動接合墊位於所述第一穿孔之上且接觸所述第一穿孔；第一虛擬接合墊，位於所述第二介電層中，其中所述第一虛擬接合墊的整個底表面位於所述第一介電層之上且接觸所述第一介電層；以及第二晶粒，所述第二晶粒包括第二主動接合墊，位於所述第一主動接合墊之上且接合至所述第一主動接合墊；以及懸空接合墊，位於所述第一虛擬接合墊之上且接合至所述第一虛擬接合墊。
20、31:晶圓
22:基底
24:緩衝層
26、68、82-1、84、154:接合層
27:接合墊
28、56:溝渠
30、58:膠帶
32、32-1、32-n:虛擬晶粒
34:基底
36、136:積體電路裝置
37:介電層
38、138:內連結構
39、50、54、64:介電層
40、140:金屬線及通孔
42、142:穿孔
44:頂部金屬接墊
46、86:鈍化層
48、144、148:金屬接墊
51:通孔
52A、52B:接合墊
60、60-1、60-2、60-n:晶粒
62、85:載體
66:金屬特徵
70:晶粒
72:介電區
74、80-1:隔離層
76:接合層
78-1:介電區
78-n:間隙填充區
82-n:介電層
83:虛線
88:開口
90:聚合物層
92:電性連接件
93:金屬柱
94:焊料區
96:封裝
97:重構晶圓
134:半導體基底
152A、152B、152C、152D:接合墊
200:製程流程
201、202、203、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232:製程
252A、252B、252C、252D:接合墊
T1、T2、T3:厚度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據業界中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖4示出根據一些實施例的虛擬晶粒的形成製程中的各中間階段的剖視圖。
圖5至圖10示出根據一些實施例的裝置晶粒的形成製程中的各中間階段的剖視圖。
圖11至圖23示出根據一些實施例的具有堆疊晶粒的封裝的形成製程中的各中間階段的剖視圖。
圖24至圖32示出根據一些實施例的具有堆疊晶粒的一些封裝的剖視圖及俯視圖。
圖33示出根據一些實施例的形成封裝的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例而不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另 外，本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
另外，為易於說明，本文中可使用例如「在...之下」、「在...下方」、「下部」、「上覆」、「上部」等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外，涵蓋裝置在使用或操作中的不同定向。設備可被另外定向(旋轉90度或處於其他定向)，且本文所用的空間相對性描述語可同樣相應地作出解釋。
根據各種實施例，提供一種包括堆疊晶粒的封裝及一種形成所述封裝的方法。根據一些實施例，示出所述封裝的形成製程中的各中間階段。對一些實施例的一些變型進行論述。在各圖中及說明性實施例通篇中，相同的參考編號用於標示相同的元件。根據本揭露的一些實施例，封裝包括接合至底部晶粒的上部晶粒，其中上部晶粒包括主動接墊及懸空接墊。下部晶粒具有穿透相應半導體基底的穿孔。在穿孔之上形成介電層，且在介電層中形成主動接合墊及虛擬接墊。虛擬接墊接合至懸空接墊以提高接合強度並減少接合結構中的問題。
圖1至圖23示出根據本揭露一些實施例的封裝的形成製程中的各中間階段的剖視圖。對應的製程亦示意性地反映於圖33所示製程流程中。
圖1至圖4示出根據一些實施例的虛擬晶粒的形成，所述虛擬晶粒以晶粒堆疊來放置。相應製程在圖33所示製程流程200中示出為製程201。參照圖1，提供晶圓20。晶圓20包括基 底22及位於基底22之上的緩衝層24。根據本揭露的一些實施例，基底22為矽基底。根據其他實施例，基底22可由熱膨脹係數(Coefficient of Thermal Expansion，CTE)接近矽的熱膨脹係數且熱導率接近或大於矽的熱導率的材料形成。緩衝層24可由楊氏模數低於隨後形成的接合層26(圖2)的材料形成(因此更軟)，因而緩衝層24可充當吸收來自接合層26的應力的應力吸收層。舉例而言，緩衝層24可由原矽酸四乙酯(Tetra Ethyl Ortho Silicate，TEOS)氧化物、未經摻雜的矽酸鹽玻璃(Undoped Silicate Glass，USG)等形成。緩衝層24的形成可包括電漿增強型化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低壓化學氣相沉積(Low-Pressure Chemical Vapor Deposition，LPCVD)、化學氣相沉積(Chemical Vapor Deposition，CVD)等。
參照圖2，形成接合層26。根據本揭露的一些實施例，接合層26是由氧化物形成，所述氧化物可為例如氧化矽、氮氧化矽等含矽及氧的氧化物。接合層26可使用PECVD、LPCVD、CVD等形成。
根據一些實施例，在接合層26中形成虛擬金屬接合墊27。根據一些實施例，在接合層26中不形成虛擬金屬接墊。虛擬金屬接合墊27可由例如銅形成，且可能存在或可能不存在被形成以將虛擬金屬接合墊27中的銅與接合層26及緩衝層24分開的擴散阻障層。根據一些實施例，虛擬金屬接合墊27可使用單鑲嵌製程來形成。
圖3示出晶圓20中溝渠28的形成。當自晶圓20的頂部觀察時，溝渠28形成柵格(grid)。溝渠28自接合層26的頂表 面延伸至基底22的中間層面(intermediate level)，其中中間層面位於基底22的頂表面與底表面之間。溝渠28可使用刀片、雷射束等形成。
圖4示出藉由磨削(grinding)製程對晶圓20進行單體化。根據本揭露的一些實施例，將晶圓20顛倒，並貼合至膠帶30。接著自晶圓20的背側執行磨削製程以將基底22薄化，直至晶圓20的位於溝渠28之上的部分被移除。因此，晶圓20被分成分離(discrete)虛擬晶粒32。所得虛擬晶粒32不包括主動裝置及被動裝置，且所得虛擬晶粒32中可不含金屬。根據一些實施例，虛擬晶粒32包括基底22及平坦介電層，且除了可形成虛擬接合墊27之外，不包括其他金屬結構。
圖5至圖10示出上部晶粒的形成，所述上部晶粒之所以如此命名是由於其在封裝的形成製程中用作上層晶粒。相應製程在圖33所示製程流程200中示出為製程202。根據本揭露的一些實施例，上部晶粒是記憶體晶粒，同時上部晶粒可為邏輯晶粒、輸入-輸出(Input-Output，IO)晶粒等。記憶體晶粒可為靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒、反及(NAND)記憶體晶粒、電阻式隨機存取記憶體(Resistive Random Access Memory，RRAM)晶粒、磁阻式隨機存取記憶體(Magneto-resistive Random Access Memory，MRAM)晶粒等。如圖5所示，示出晶圓31。晶圓31包括半導體基底34，根據一些實施例，半導體基底34可為矽基底、矽鍺基底等。例如在半導體基底34的頂部處形成積體電路裝置36。積體電路裝置36可包括 電晶體、電阻器、電容器、電感器及/或類似元件。積體電路裝置36可執行記憶體功能、邏輯功能、輸入-輸出功能等。在半導體基底34之上形成內連結構38，且內連結構38包括介電層37及位於介電層37中的金屬線及通孔40。金屬線及通孔40電性連接至積體電路裝置36。
參照圖6，穿孔42形成為延伸至半導體基底34中。根據一些實施例，穿孔42自內連結構38的頂表面延伸至半導體基底34中。根據替代實施例，穿孔42是在內連結構38的整體或上部部分形成之前在半導體基底34中預先形成。穿孔42可由例如鎢、銅等導電材料形成。可形成隔離層(圖中未示出)以環繞穿孔42中的每一者，進而使對應的穿孔42與半導體基底34電性絕緣。穿孔42的形成可包括：對介電層37及半導體基底34進行蝕刻以形成開口；以及利用隔離層及導電材料來填充所述開口。可執行例如化學機械研磨(Chemical Mechanical Polish，CMP)製程或機械磨削製程等平坦化製程，以使穿孔42的頂表面與頂部介電層37的頂表面齊平。
圖7示出晶圓31的進一步形成。根據一些實施例，所述形成包括：形成介電層39以及金屬線及通孔40以使內連結構38延伸；在介電層39的頂層中形成頂部金屬接墊44；形成鈍化層46；以及形成金屬接墊48。根據本揭露的一些實施例，介電層37及39中的一些是由低介電常數介電材料形成。鈍化層46可由介電常數等於或高於氧化矽的介電常數(3.9)的非低介電常數介電材料形成。金屬接墊48可由鋁或鋁銅形成。
圖8示出介電層50、通孔51、介電層54以及介電層54 中的接合墊52A及52B的形成。根據一些實施例，如圖8所示，介電層50及54是在不同的形成製程中形成的分開的介電層。根據替代實施例，介電層50及54是在同一形成製程中形成的同一介電層的部分。介電層54可由例如氧化矽、氮氧化矽等含矽及氧的介電材料形成。介電層50可由與介電層54的材料相同的材料形成，或者可由與介電層54的材料不同的材料形成。舉例而言，介電層50可由氮化矽、氮氧化矽、氮化矽、氮碳化矽等形成。接合墊52A及52B以及通孔51可由銅形成，且可使用單鑲嵌製程或雙鑲嵌製程形成。介電層54的頂表面與接合墊52A及52B的頂表面共面。
圖9示出晶圓31中溝渠56的形成。當自晶圓31的頂部觀察時，溝渠56形成柵格，其中示出溝渠56中的一者作為實例。溝渠56自介電層54的頂表面延伸至半導體基底34的中間層面，其中中間層面位於半導體基底34的頂表面與底表面之間。溝渠56可使用刀片、雷射束等形成。
圖10示出藉由磨削製程對晶圓31進行單體化。根據本揭露的一些實施例，將晶圓31顛倒，並貼合至膠帶58。接著自晶圓31的背側執行磨削製程以將半導體基底34薄化，直至半導體基底34的位於溝渠56之上的部分被移除。因此，晶圓31被分成彼此相同的分離晶粒60。
圖11至圖23示出對虛擬晶粒32(圖4)及晶粒60(圖10)進行封裝以形成封裝的剖視圖。參照圖11，提供載體62。根據一些實施例，載體62是由矽、玻璃等形成，且是以晶圓形式來提供，載體62足夠大以容置將接合於上面的多個裝置晶粒。在載 體62上形成介電層64。相應製程在圖33所示製程流程200中示出為製程203。根據本揭露的一些實施例，介電層64是由相對軟的材料(其較隨後形成的接合層68軟)形成，且因此用作用於吸收應力的緩衝層。介電層64可由TEOS氧化物、USG等形成。介電層64的形成可包括PECVD、LPCVD、CVD等。根據一些實施例，在介電層64中形成金屬特徵66。金屬特徵66可用作對準標記以使對裝置晶粒的隨後放置及接合對準。金屬特徵66可例如藉由鑲嵌製程來形成。
參照圖12，形成接合層68。相應製程在圖33所示製程流程200中示出為製程204。根據本揭露的一些實施例，接合層68是由氧化物形成，所述氧化物可為例如氧化矽、氮氧化矽等含矽及氧的氧化物。接合層68可使用PECVD、LPCVD、CVD等形成。接合層68的形成可包括沉積製程、然後是平坦化製程。
圖13示出將層1晶粒(tier-1 die)70放置並接合於接合層68上。相應製程在圖33所示製程流程200中示出為製程206。儘管圖中示出一個層1晶粒70，然而將多個層1晶粒70放置並接合至接合層68上。所述多個層1晶粒70可排列成陣列。使用對準標記(金屬特徵66)將層1晶粒70對準至預期位置。根據一些實施例，層1晶粒70是邏輯晶粒，所述邏輯晶粒可為應用處理器(Application Processor，AP)晶粒、圖形處理單元(Graphics Processing Unit，GPU)晶粒、現場可程式化閘陣列(Field Programmable Gate Array，FPGA)晶粒、應用專用積體電路(Application-Specific Integrated Circuit，ASIC)晶粒、輸入-輸出(IO)晶粒、網路處理單元(Network Processing Unit，NPU)晶 粒、張量處理單元(Tensor Processing Unit，TPU)晶粒、人工智慧(Artificial Intelligence，AI)引擎晶粒等。除了層1晶粒70中的特徵的參考編號在晶粒60中的相同對應特徵的參考編號基礎上增大數字100以外，邏輯晶粒70中的特徵對應於晶粒60(圖10)的標誌進行標記。舉例而言，邏輯晶粒70可包括半導體基底134、積體電路裝置136、內連結構138、金屬線及通孔140、穿孔142、金屬接墊144及148以及接合層154。晶粒70的形成可包括與圖5至圖7所示製程步驟相似的製程步驟，然後是接合層154(圖13)的形成以及接著是圖9及圖10所示製程。層1晶粒70的被標記的特徵的一些材料亦可相似於晶粒60中對應的特徵的材料。層1晶粒70可具有與晶粒60(圖10)的結構不同的結構。如圖13所示，金屬接墊148嵌入介電層(例如接合層154)中。根據一些實施例，層1晶粒70的厚度T1介於約50微米與約150微米之間的範圍內。
將晶粒70接合至接合層64可藉由熔融接合(介電質至介電質接合(dielectric-to-dielectric bonding))來進行，所述熔融接合可形成Si-O-Si鍵以將接合層154及68接合在一起。
圖14示出用於形成介電區72的間隙填充製程，介電區72填充位於層1晶粒70之間並環繞層1晶粒70的間隙。相應製程在圖33所示製程流程200中示出為製程208。根據一些實施例，間隙填充製程包括：施配或塗佈可流動介電材料；以及接著固化所述可流動介電材料。對應的介電區72可由模製化合物、模製底部填充膠、樹脂、環氧樹脂等形成。根據替代實施例，介電區72的形成可包括沉積一或多個介電材料層。舉例而言，介電區72可 包括由氮化矽形成的介電襯墊以及位於介電襯墊之上的另一介電材料(例如氧化矽)。可執行例如CMP製程或機械磨削製程等平坦化製程以移除過量的介電材料，並使半導體基底134的頂表面與介電區72齊平。根據一些實施例，在間隙填充製程之後，層1晶粒70的厚度T2介於約10微米與約15微米之間的範圍內。
圖15示出用於將層1晶粒70薄化並顯露出穿孔142的背側磨削製程。相應製程在圖33所示製程流程200中示出為製程210。背側磨削製程可為圖14所示平坦化製程的接續部分，或者可為與圖14所示平坦化製程分開執行的單獨製程。在背側磨削製程之後，亦顯露出半導體基底134，其中其頂表面與穿孔142及介電區72的頂表面共面。接下來，使用蝕刻劑對半導體基底134進行蝕刻，所述蝕刻劑會侵蝕半導體基底134，而不侵蝕穿孔142及介電區72。結果，形成凹槽，其中穿孔142的頂部部分位於所述凹槽中且突出超過半導體基底134的剩餘部分的頂表面。在後續製程中，形成隔離層74。相應製程亦在圖33所示製程流程200中示出為製程210。隔離層74是由介電材料形成，所述介電材料可包括氧化矽、氮化矽、氮氧化矽、碳氧化矽等。接著執行平坦化製程以使穿孔142、隔離層74及介電區72的頂表面齊平。根據一些實施例，在形成隔離層74之後，層1晶粒70的厚度T3介於約3微米與約10微米之間的範圍內。
圖16示出接合層76以及接合層76中的接合墊152A及152B的形成。相應製程在圖33所示製程流程200中示出為製程212。接合層76可由例如氧化矽、氮氧化矽等含矽及氧的介電材料形成。形成方法可包括CVD、原子層沉積(atomic layer deposition，ALD)、PECVD等。接合墊152A及152B可包含銅，且可使用單鑲嵌製程形成。接合層76的頂表面與接合墊152A及152B的頂表面共面。根據一些實施例，接合墊152A是電性耦合及/或訊號耦合至積體電路裝置136的主動接合墊。另一方面，接合墊152B是在此時為電性浮置的虛擬接合墊。接合墊152B的底表面可接觸隔離層74的頂表面。
根據本揭露的一些實施例，當形成接合墊152A及152B時，亦同時形成接合墊152C及152D。在後續段落中參照圖27至圖32來詳細闡述接合墊152C及152D的功能及位置。根據本揭露的替代實施例，不形成接合墊152C及152D中的一者或二者。
參照圖17，將裝置晶粒60接合至裝置晶粒70。裝置晶粒60亦被稱為層2晶粒60-1。相應製程在圖33所示製程流程200中示出為製程214。在說明通篇中，特徵的參考編號之後可為破折符號及整數以識別其層次。舉例而言，晶粒60可根據其層次而被識別為60-1、60-2、...60-n(圖20)。根據本揭露的一些實施例，接合可包括熔融接合，所述熔融接合包括接合墊152A/152B與接合墊52A/52B之間的直接金屬接合以及介電層54與介電層(接合層76)之間的介電質至介電質接合。在接合之後，接合在一起的接合墊152A及52A用於層2晶粒60-1(其可為記憶體晶粒)與層1晶粒70之間的電性連接及/或訊號連接。舉例而言，層2晶粒60-1中的積體電路裝置36(其可包括記憶胞)藉由接合墊152A及52A電性連接及/或訊號連接至層1晶粒70中的積體電路裝置136。
接合墊52B是懸空接合件(dangling bond)，其在圖25 中被示意性示出以示出一些細節。接合墊52B電性連接至積體電路裝置36(圖17)(即使當各裝置晶粒60仍為分離晶粒時)。當對所得封裝96(圖23)加電時，懸空接合墊52B可具有自積體電路裝置36接收的電壓。若層2晶粒60-1在所得封裝的其他電路或其他部分中用作例如將在後續段落中論述的層3晶粒，則接合墊52B可為傳導電壓及/或電流的功能(主動)接墊。根據本揭露的一些實施例，由於層2晶粒60-1連接至層1晶粒70，因此接合墊52B不具有電性及訊號功能，且因此為懸空的。因此，可對接合墊52B及152B施加電壓，但由於接合墊152B是電流/電壓路徑的終端節點，因此不存在流經接合墊52B及152B的電流。
圖18示出將虛擬晶粒32-1接合至介電層(接合層76)。相應製程在圖33所示製程流程200中示出為製程216。接合可藉由熔融接合來進行，其中虛擬晶粒32-1中的介電層26接合至介電層(接合層76)。由於存在多個層2晶粒60-1(圖中示出一個)，因此將虛擬晶粒32-1放置於所述多個層2晶粒60-1之間以佔據否則將由間隙填充材料(介電區78-1)(圖19)佔據的空間。由於虛擬晶粒32-1的等效氧化物厚度(equivalent oxide thickness，EOT)接近層1晶粒70及層2晶粒60的EOT，因此虛擬晶粒32-1的添加會減小所得封裝中的應力及翹曲。
圖19示出用於形成環繞層2晶粒60-1的介電區78-1的間隙填充製程。相應製程在圖33所示製程流程200中示出為製程218。根據一些實施例，間隙填充製程包括：施配或塗佈可流動介電材料；以及接著固化所述可流動介電材料。對應的介電區78-1可由模製化合物、模製底部填充膠、樹脂、環氧樹脂等形成。根 據替代實施例，介電區78-1的形成可包括沉積一或多個介電材料層。舉例而言，介電區78-1可包括由氮化矽形成的介電襯墊以及位於介電襯墊之上的另一介電材料(例如氧化矽)。可執行例如CMP製程或機械磨削製程等平坦化製程以移除過量的介電材料，並使半導體基底34的頂表面與介電區78-1齊平。
在後續製程中，執行背側磨削製程以將層2晶粒60-1及虛擬晶粒32-1薄化並顯露出穿孔42。相應製程在圖33所示製程流程200中示出為製程220。在背側磨削製程之後，亦顯露出半導體基底34，其中其頂表面與穿孔42及介電區78-1的頂表面共面。接下來，對半導體基底34進行蝕刻以形成凹槽，其中穿孔42的頂部部分位於所述凹槽中且突出超過半導體基底34的剩餘部分的頂表面。在後續製程中，在凹槽中形成隔離層80-1。相應製程亦在圖33所示製程流程200中示出為製程220。隔離層80-1是由介電材料形成，所述介電材料可包括氧化矽、氮化矽、氮氧化矽、碳氧化矽等。接著執行平坦化製程以使穿孔42、隔離層80-1及介電區78-1的頂表面齊平。
圖19進一步示出接合層82-1以及接合層82-1中的接合墊252A及252B的形成。相應製程在圖33所示製程流程200中示出為製程222。接合層82-1可由例如氧化矽、氮氧化矽等含矽及氧的介電材料形成。形成方法可包括CVD、ALD、PECVD等。接合墊252A及252B可由銅形成，且可使用單鑲嵌製程形成。接合層82-1的頂表面與接合墊252A及252B的頂表面共面。根據一些實施例，接合墊252A是電性耦合至積體電路(例如36)的主動接合墊。舉例而言，當晶粒60-1與隨後接合的晶粒60-2彼此相同 時，接合墊252B可為與接合墊252A相同的主動接合墊。圖19示意性地示出表示將接合墊252B電性連接至積體電路裝置36的導電特徵的虛線83，所述導電特徵可包括穿孔及金屬接墊、金屬線、通孔等。根據替代實施例，接合墊252B亦可為虛擬接合墊。根據一些實施例，接合墊252A/252B與下伏接合墊52A/52B(及152A/152B)之間存在一一對應關係，其中接合墊252A/252B中的每一者垂直對準並交疊於對應的接合墊52A/52B及對應的接合墊152A/152B。
根據本揭露的一些實施例，當形成接合墊252A及252B時，亦同時形成接合墊252C及252D。在後續段落中參照圖27至圖32來詳細闡述接合墊252C及252D的功能及位置。
圖20示出圖17至圖19所示製程的重複以堆疊更多層晶粒60。舉例而言，假設存在n層晶粒60，其中頂層晶粒被稱為層n晶粒60-n。整數n可為等於或大於2的任何數。上層晶粒60-2至60-n可與層2晶粒60-1相同或不同。在將頂層晶粒60-n與虛擬晶粒32-n接合之後，形成間隙填充區78-n並對間隙填充區78-n進行平坦化，然後形成介電層82-n，介電層82-n亦可為接合層。
圖21示出載體切換(carrier-switch)製程。相應製程在圖33所示製程流程200中示出為製程224。藉由接合層84將載體85接合至介電層82-n，其中接合方法是熔融接合。根據一些實施例，載體85是由矽形成，且是不包括主動裝置、被動裝置、導電線等的空白載體。接合層84可由例如氧化矽、氮氧化矽等含矽及氧的材料形成。
接下來，例如在CMP製程或機械磨削製程中移除載體 62、緩衝層64及接合層68。在後續製程中，形成鈍化層86，鈍化層86可包含氧化矽、氮化矽或其複合層。在鈍化層86中形成開口88。相應製程在圖33所示製程流程200中示出為製程226。在圖22中示出所得結構。接著可例如藉由使探針卡(圖中未示出)的探針引腳接觸金屬接墊148來執行探測製程以確定所得封裝是否有缺陷。記錄已知良好封裝。相應製程在圖33所示製程流程200中示出為製程228。
圖23示出聚合物層90的形成，聚合物層90可由聚醯亞胺、聚苯并噁唑(polybenzoxazole，PBO)、苯并環丁烯(benzocyclobutene，BCB)等形成。接著在金屬接墊148上形成電性連接件92，電性連接件92可包括金屬柱93及焊料區94。相應製程在圖33所示製程流程200中示出為製程230。所得結構被稱為重構(reconstructed)晶圓(封裝)97。在後續製程中，對重構晶圓97執行單體化製程，且形成多個相同的封裝96。相應製程在圖33所示製程流程200中示出為製程232。
圖24至圖32示意性地示出根據本揭露一些實施例的封裝96的剖視圖及俯視圖。細節中的一些並未示出，且該些細節可參照圖11至圖23找到。在該些圖中，示出兩層裝置晶粒60以表示圖23所示相同的多層裝置晶粒60。示出功能(主動)接合墊52A及152A、懸空接合墊52B及虛擬接合墊152B。接合墊中的一些被示出為52A/52B以指示該些接合墊可為功能接合墊52A或懸空接合墊52B。類似地，接合墊中的一些被示出為152A/152B以指示該些接合墊可為功能接合墊152A或虛擬接合墊152B。應理解，儘管填充介電區72(圖23)在圖24至圖32中並未示出， 然而介電區72可位於(或可不位於)圖24至圖32所示封裝96中。
根據本揭露的一些實施例，如圖24所示，形成於層1晶粒70上的接合墊(包括152A及152B)均與層2晶粒60-1交疊，且不存在直接形成於介電區78-1及虛擬晶粒32-1之下並接觸介電區78-1及虛擬晶粒32-1的接合墊。圖25示出接合墊52A、52B、152A及152B的放大圖。
圖26示出接合墊52A、52B、152A及152B、層1晶粒70、層2晶粒60-1以及虛擬晶粒32-1的俯視圖。根據本揭露的一些實施例，接合墊52A、52B、152A及152B形成陣列且被限制於被層2晶粒60覆蓋的區中，其中沒有接合晶粒位於被層2晶粒60-1覆蓋的區之外。
圖27及圖28分別示出根據一些實施例的封裝96的俯視圖及剖視圖。除了在與介電區78-1交疊的區中進一步形成虛擬接合墊152C以外，該些實施例類似於圖24及圖26所示實施例。因此，在封裝96中，虛擬接合墊152C是電性浮置的，其中接合墊152C的頂表面接觸介電區78-1的底表面。此外，接合墊152C完全封閉於介電區中。在形成接合墊時，例如接墊陣列等密集接墊區的邊緣部分可為非均勻的，例如其中接墊陣列的邊緣部分較接墊陣列的中心部分被研磨得更多或更少。藉由形成虛擬接墊(虛擬接合墊152C)，非均勻性會集中於虛擬接合墊152C(虛擬接合墊152C是接墊陣列的邊緣部分)中，同時接合墊152A及152B會更均勻。
圖29及圖30分別示出根據一些實施例的封裝96的俯 視圖及剖視圖。除了在與介電區78-1及虛擬晶粒32-1交疊的區中進一步形成虛擬接合墊152C及152D以外，該些實施例類似於圖24及圖26所示實施例。在封裝96中，虛擬接合墊152C及152D是電性浮置的，其中接合墊152C的頂表面接觸介電區78-1的底表面，且接合墊152D的頂表面接觸虛擬晶粒32-1的底表面。根據一些實施例，虛擬接252墊152C及152D被完全封閉於介電區中。根據替代實施例，接合墊152D接合至虛擬晶粒32-1中的接合墊27。虛擬接墊(虛擬接合墊152C及152D)的形成會提高用於形成接合墊152A及152B的平坦化製程中的均勻性。
圖31及圖32分別示出根據一些實施例的封裝96的俯視圖及剖視圖。除了不採用虛擬晶粒32以外，該些實施例類似於圖24及圖26所示實施例。虛擬接合墊152C進一步形成於與介電區78-1交疊的區中。因此，在封裝96中，虛擬接合墊152C是電性浮置的，其中接合墊152C的頂表面接觸介電區78-1的底表面。此外，虛擬接合墊152C完全封閉於介電區中。虛擬接合墊152C的形成會提高用於形成接合墊152A及152B的平坦化製程中的均勻性。
在以上所示實施例中，根據本揭露的一些實施例來論述一些製程及特徵。亦可包括其他特徵及製程。舉例而言，可包括測試結構以幫助對三維(three dimensions，3D)封裝或三維積體電路(three dimensional integrated circuit，3DIC)裝置進行驗證測試。測試結構可包括例如形成於重佈線層中或基板上的測試接墊，所述測試接墊能夠對三維封裝或三維積體電路進行測試、使用探針及/或探針卡等。所述驗證測試可在中間結構以及最終結構 上執行。另外，本文所揭露的結構及方法可結合測試方法來使用，所述測試方法結合對已知良好晶粒(known good die)進行中間驗證來提高良率並降低成本。
本揭露的實施例具有一些有利特徵。藉由在下層晶粒中形成附加介電層及位於附加介電層中的虛擬接墊，上層晶粒中的懸空接墊會接合至虛擬接墊，而不接觸介電材料。因此會提高接合強度。
根據本揭露的一些實施例，一種方法包括：對第一晶粒的半導體基底進行研磨以顯露出延伸至所述半導體基底中的第一穿孔；在所述半導體基底上形成介電層；在所述介電層中形成多個接合墊，其中所述多個接合墊包括第一主動接合墊及第一虛擬接合墊，其中所述第一主動接合墊電性耦合至所述第一穿孔；以及將所述第一晶粒接合至第二晶粒，其中所述第一主動接合墊及所述第一虛擬接合墊二者接合至所述第二晶粒中對應的接合墊。在一實施例中，所述第一主動接合墊接合至所述第二晶粒中的多個第二主動接合墊，且所述第一虛擬接合墊接合至所述第二晶粒中的懸空接合墊，且其中所述多個第二主動接合墊及所述懸空接合墊二者電性連接至所述第二晶粒中的積體電路裝置。在一實施例中，所述第一晶粒與所述第二晶粒是藉由混合接合進行接合。在一實施例中，所述方法更包括將虛擬晶粒接合至所述第一晶粒。在一實施例中，所述多個接合墊更包括第二虛擬接合墊，且所述虛擬晶粒包括接合至所述第二虛擬接合墊的第三虛擬接合墊。在一實施例中，所述方法更包括：設置填充介電材料以環繞所述第二晶粒；對所述第二晶粒及所述填充介電材料進行平坦 化，直至所述第二晶粒中的第二穿孔被暴露出；以及形成電性耦合至所述第二穿孔的第三主動接合墊。在一實施例中，所述多個接合墊更包括第四虛擬接合墊，且所述第四虛擬接合墊的頂表面接觸所述填充介電材料。在一實施例中，所述第一晶粒是邏輯晶粒，且所述第二晶粒是記憶體晶粒。在一實施例中，所述方法更包括：在所述第二晶粒之上堆疊與所述第二晶粒相同的第三晶粒，其中所述第二晶粒中且亦接合至所述第三晶粒的接合墊均不用作懸空接合墊。
根據本揭露的一些實施例，一種方法包括形成第一晶粒，所述第一晶粒包括第一半導體基底；以及第一穿孔，穿透第一半導體基底。所述方法更包括形成第二晶粒，所述第二晶粒包括第二半導體基底；第二穿孔，穿透所述第二半導體基底；第一主動接合墊；以及第一懸空接合墊。將所述第二晶粒接合於所述第一晶粒之上，其中所述第一主動接合墊藉由所述第一晶粒與所述第二晶粒之間的第二主動接合墊電性耦合至所述第一晶粒，且所述第一懸空接合墊接合至所述第一晶粒與所述第二晶粒之間的第一虛擬接墊。在一實施例中，所述方法更包括：將所述第一晶粒放置於載體之上；將所述第一晶粒包封於填充介電材料中；形成與所述第一晶粒及所述填充介電材料交疊的介電層；以及在所述介電層中形成所述第二主動接合墊及所述第一懸空接合墊。在一實施例中，所述方法更包括：執行間隙填充製程以將所述第二晶粒嵌入間隙填充材料中，其中所述間隙填充材料位於第二虛擬接墊的頂表面之上且接觸第二虛擬接墊的頂表面，其中所述第二虛擬接墊位於所述第一晶粒與所述第二晶粒之間。在一實施例 中，所述方法更包括：將虛擬晶粒接合至所述第一晶粒，其中所述虛擬晶粒接觸所述第一晶粒與所述第二晶粒之間的第三虛擬接墊，且所述第三虛擬接墊位於與所述第二主動接合墊及所述第一虛擬接墊相同的水平高度處。在一實施例中，所述虛擬晶粒更包括接合至所述虛擬晶粒中的所述第三虛擬接墊的第四虛擬接墊。在一實施例中，在將所述第二晶粒接合至所述第一晶粒之前，所述第一虛擬接墊是電性浮置的。在一實施例中，所述方法更包括：對所述第一半導體基底進行研磨以顯露出所述第一穿孔；在所述第一半導體基底之上形成接觸所述第一半導體基底的介電層；以及在所述介電層中形成所述第二主動接合墊及所述第一虛擬接墊，其中所述第一虛擬接墊的整個底表面接觸所述第一晶粒中的附加介電層的頂表面。
根據本揭露的一些實施例，積體電路裝置的封裝包括：第一晶粒，所述第一晶粒包括第一半導體基底；第一穿孔，穿透所述第一半導體基底；以及第一介電層，位於所述第一半導體基底之上且接觸所述第一半導體基底；第二介電層，位於所述第一晶粒之上；第一主動接合墊，位於所述第二介電層中，所述第一主動接合墊位於所述第一穿孔之上且接觸所述第一穿孔；第一虛擬接合墊，位於所述第二介電層中，其中所述第一虛擬接合墊的整個底表面位於所述第一介電層之上且接觸所述第一介電層；以及第二晶粒，所述第二晶粒包括第二主動接合墊，位於所述第一主動接合墊之上且接合至所述第一主動接合墊；以及懸空接合墊，位於所述第一虛擬接合墊之上且接合至所述第一虛擬接合墊。在一實施例中，所述第一晶粒是邏輯晶粒，且所述第二晶粒 是記憶體晶粒。在一實施例中，所述封裝更包括：第二虛擬接合墊，位於所述第二介電層中；以及填充介電材料，環繞所述第二晶粒，其中所述填充介電材料接觸所述第二虛擬接合墊的頂表面。在一實施例中，所述封裝更包括：第二虛擬接合墊，位於所述第二介電層中；以及虛擬晶粒，位於所述第二虛擬接合墊之上且接觸所述第二虛擬接合墊。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應知，其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
200:製程流程
201、202、203、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232:製程

Claims (10)

  1. 一種積體電路裝置的封裝的形成方法，包括：對第一晶粒的半導體基底進行研磨以顯露出延伸至所述半導體基底中的第一穿孔；在所述半導體基底上形成介電層；在所述介電層中形成多個接合墊，其中所述多個接合墊包括第一主動接合墊及第一虛擬接合墊，其中所述第一主動接合墊電性耦合至所述第一穿孔；以及將所述第一晶粒接合至第二晶粒，其中所述第一主動接合墊及所述第一虛擬接合墊二者接合至所述第二晶粒中對應的接合墊，其中所述方法更包括將虛擬晶粒接合至所述第一晶粒。
  2. 如申請專利範圍第1項所述的積體電路裝置的封裝的形成方法，其中所述第一主動接合墊接合至所述第二晶粒中的多個第二主動接合墊，且所述第一虛擬接合墊接合至所述第二晶粒中的懸空接合墊，且其中所述多個第二主動接合墊及所述懸空接合墊二者電性連接至所述第二晶粒中的積體電路裝置。
  3. 如申請專利範圍第1項所述的積體電路裝置的封裝的形成方法，其中所述多個接合墊更包括第二虛擬接合墊，且所述虛擬晶粒包括接合至所述第二虛擬接合墊的第三虛擬接合墊。
  4. 如申請專利範圍第1項所述的積體電路裝置的封裝的形成方法，更包括在所述第二晶粒之上堆疊與所述第二晶粒相同的第三晶粒，其中在所述第二晶粒中且亦接合至所述第三晶粒的接合墊均不用作懸空接合墊。
  5. 一種積體電路裝置的封裝的形成方法，包括：形成第一晶粒，所述第一晶粒包括：第一半導體基底；以及第一穿孔，穿透所述第一半導體基底；形成第二晶粒，所述第二晶粒包括：第二半導體基底；第二穿孔，穿透所述第二半導體基底；第一主動接合墊；以及第一懸空接合墊；以及將所述第二晶粒接合於所述第一晶粒之上，其中所述第一主動接合墊藉由所述第一晶粒與所述第二晶粒之間的第二主動接合墊電性耦合至所述第一晶粒，且所述第一懸空接合墊接合至所述第一晶粒與所述第二晶粒之間的第一虛擬接墊。
  6. 如申請專利範圍第5項所述的積體電路裝置的封裝的形成方法，更包括：將所述第一晶粒放置於載體之上；將所述第一晶粒包封於填充介電材料中；形成與所述第一晶粒及所述填充介電材料交疊的介電層；以及在所述介電層中形成所述第二主動接合墊及所述第一懸空接合墊。
  7. 如申請專利範圍第5項所述的積體電路裝置的封裝的形成方法，更包括：執行間隙填充製程以將所述第二晶粒嵌入間隙填充材料中， 其中所述間隙填充材料位於第二虛擬接墊的頂表面之上且接觸第二虛擬接墊的頂表面，其中所述第二虛擬接墊位於所述第一晶粒與所述第二晶粒之間。
  8. 一種積體電路裝置的封裝，所述封裝包括：第一晶粒，包括：第一半導體基底；第一穿孔，穿透所述第一半導體基底；以及第一介電層，位於所述第一半導體基底之上且接觸所述第一半導體基底；第二介電層，位於所述第一晶粒之上；第一主動接合墊，位於所述第二介電層中，所述第一主動接合墊位於所述第一穿孔之上且接觸所述第一穿孔；第一虛擬接合墊，位於所述第二介電層中，其中所述第一虛擬接合墊的整個底表面位於所述第一介電層之上且接觸所述第一介電層；以及第二晶粒，包括：第二半導體基底；第二穿孔，穿透所述第二半導體基底；第二主動接合墊，位於所述第一主動接合墊之上且接合至所述第一主動接合墊；以及懸空接合墊，位於所述第一虛擬接合墊之上且接合至所述第一虛擬接合墊。
  9. 如申請專利範圍第8項所述的積體電路裝置的封裝，更包括： 第二虛擬接合墊，位於所述第二介電層中；以及填充介電材料，環繞所述第二晶粒，其中所述填充介電材料接觸所述第二虛擬接合墊的頂表面。
  10. 如申請專利範圍第8項所述的積體電路裝置的封裝，更包括：第二虛擬接合墊，位於所述第二介電層中；以及虛擬晶粒，位於所述第二虛擬接合墊之上且接觸所述第二虛擬接合墊。
TW108125364A 2018-11-21 2019-07-18 積體電路裝置的封裝及其形成方法 TWI735008B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862770396P 2018-11-21 2018-11-21
US62/770,396 2018-11-21
US16/371,863 US10861808B2 (en) 2018-11-21 2019-04-01 Bonding structure of dies with dangling bonds
US16/371,863 2019-04-01

Publications (2)

Publication Number Publication Date
TW202020998A TW202020998A (zh) 2020-06-01
TWI735008B true TWI735008B (zh) 2021-08-01

Family

ID=70727957

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108125364A TWI735008B (zh) 2018-11-21 2019-07-18 積體電路裝置的封裝及其形成方法

Country Status (4)

Country Link
US (2) US10861808B2 (zh)
KR (1) KR102268935B1 (zh)
CN (1) CN111211058B (zh)
TW (1) TWI735008B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US10811365B2 (en) 2018-12-28 2020-10-20 Micron Technology, Inc. Semiconductor devices having crack-inhibiting structures
US10784212B2 (en) * 2018-12-28 2020-09-22 Micron Technology, Inc. Semiconductor devices having crack-inhibiting structures
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
KR20220033619A (ko) * 2020-09-08 2022-03-17 삼성전자주식회사 반도체 패키지
US11552055B2 (en) * 2020-11-20 2023-01-10 Qualcomm Incorporated Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods
TWI757127B (zh) * 2021-02-19 2022-03-01 南亞科技股份有限公司 製造半導體裝置的方法
US11862599B2 (en) * 2021-03-26 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding to alignment marks with dummy alignment marks
US11562975B2 (en) * 2021-04-29 2023-01-24 Sandisk Technologies Llc Bonded assembly employing metal-semiconductor bonding and metal-metal bonding and methods of forming the same
TWI769814B (zh) * 2021-05-14 2022-07-01 聯華電子股份有限公司 改善半導體鍵合品質的方法
US20230178494A1 (en) * 2021-12-03 2023-06-08 Nanya Technology Corporation Semiconductor device having integral alignment marks with decoupling features and method for fabricating the same
US11791328B2 (en) 2021-12-20 2023-10-17 Nanya Technology Corporation Method for fabricating semiconductor device with integrated decoupling and alignment features
TWI809745B (zh) * 2021-12-20 2023-07-21 南亞科技股份有限公司 具有整合去耦合特徵以及對準特徵的半導體元件
US20240047395A1 (en) * 2022-08-08 2024-02-08 Nanya Technology Corporation Semiconductor structure
TWI841233B (zh) * 2023-02-09 2024-05-01 南亞科技股份有限公司 半導體結構的製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201401474A (zh) * 2012-03-26 2014-01-01 Renesas Electronics Corp 半導體積體電路裝置之製造方法
TW201539725A (zh) * 2014-03-28 2015-10-16 Taiwan Semiconductor Mfg Co Ltd 積體電路結構
TW201712824A (zh) * 2015-08-21 2017-04-01 蘋果公司 獨立３ｄ堆疊
TW201715660A (zh) * 2015-10-21 2017-05-01 Taiwan Semiconductor Mfg 晶片封裝體

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8212367B2 (en) 2004-11-10 2012-07-03 Sandisk Il Ltd. Integrated circuit die with logically equivalent bonding pads
US7812459B2 (en) * 2006-12-19 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuits with protection layers
JP5442394B2 (ja) * 2009-10-29 2014-03-12 ソニー株式会社 固体撮像装置とその製造方法、及び電子機器
US8174124B2 (en) * 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
JP5606182B2 (ja) * 2010-06-30 2014-10-15 キヤノン株式会社 固体撮像装置
US8847393B2 (en) 2011-02-28 2014-09-30 Freescale Semiconductor, Inc. Vias between conductive layers to improve reliability
EP3534399A1 (en) 2011-05-24 2019-09-04 Sony Corporation Semiconductor device
FR2980036A1 (fr) * 2011-09-12 2013-03-15 St Microelectronics Crolles 2 Procede de realisation d'une structure integree tridimensionnelle et structure correspondante
US8669780B2 (en) 2011-10-31 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit connection structure and method
US9557354B2 (en) 2012-01-31 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Switched capacitor comparator circuit
US8631372B2 (en) 2012-02-10 2014-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. System and method of electromigration mitigation in stacked IC designs
US9633149B2 (en) 2012-03-14 2017-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for modeling through silicon via
US8448100B1 (en) 2012-04-11 2013-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Tool and method for eliminating multi-patterning conflicts
US8766387B2 (en) * 2012-05-18 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Vertically integrated image sensor chips and methods for forming the same
US9275950B2 (en) 2012-05-29 2016-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bead for 2.5D/3D chip packaging application
US8754818B2 (en) 2012-07-05 2014-06-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated antenna structure on separate semiconductor die
US9086452B2 (en) 2012-08-10 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit and method for wireless information access thereof
US9165968B2 (en) 2012-09-14 2015-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. 3D-stacked backside illuminated image sensor and method of making the same
US8701073B1 (en) 2012-09-28 2014-04-15 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for across-chip thermal and power management in stacked IC designs
US9016939B2 (en) 2012-10-01 2015-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal sensor with second-order temperature curvature correction
US9431064B2 (en) 2012-11-02 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and cache circuit configuration
US9172242B2 (en) 2012-11-02 2015-10-27 Taiwan Semiconductor Manufacturing Co., Ltd. Electrostatic discharge protection for three dimensional integrated circuit
DE102012112388A1 (de) 2012-12-17 2014-07-03 Endress + Hauser Conducta Gesellschaft für Mess- und Regeltechnik mbH + Co. KG Induktiver Leitfähigkeitssensor und Verfahren zu dessen Herstellung
US9252593B2 (en) * 2012-12-17 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
US9619409B2 (en) 2013-01-08 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Data sampling alignment method for memory inferface
US8896094B2 (en) 2013-01-23 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for inductors and transformers in packages
US9171798B2 (en) 2013-01-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for transmission lines in packages
US9779990B2 (en) * 2013-02-27 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated antenna on interposer substrate
US9219038B2 (en) 2013-03-12 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Shielding for through-silicon-via
US9354254B2 (en) 2013-03-14 2016-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Test-yield improvement devices for high-density probing techniques and method of implementing the same
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US9293437B2 (en) * 2014-02-20 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Functional block stacked 3DIC and method of making same
US10600759B2 (en) * 2016-01-12 2020-03-24 Advanced Semiconductor Engineering, Inc. Power and ground design for through-silicon via structure
US10153222B2 (en) 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201401474A (zh) * 2012-03-26 2014-01-01 Renesas Electronics Corp 半導體積體電路裝置之製造方法
TW201539725A (zh) * 2014-03-28 2015-10-16 Taiwan Semiconductor Mfg Co Ltd 積體電路結構
TW201712824A (zh) * 2015-08-21 2017-04-01 蘋果公司 獨立３ｄ堆疊
TW201715660A (zh) * 2015-10-21 2017-05-01 Taiwan Semiconductor Mfg 晶片封裝體

Also Published As

Publication number Publication date
US11908817B2 (en) 2024-02-20
CN111211058B (zh) 2022-12-13
US20200161263A1 (en) 2020-05-21
KR102268935B1 (ko) 2021-06-28
CN111211058A (zh) 2020-05-29
US20210118832A1 (en) 2021-04-22
KR20200060670A (ko) 2020-06-01
TW202020998A (zh) 2020-06-01
US10861808B2 (en) 2020-12-08

Similar Documents

Publication Publication Date Title
TWI735008B (zh) 積體電路裝置的封裝及其形成方法
TWI820175B (zh) 半導體裝置及半導體封裝
TW202002099A (zh) 半導體裝置封裝及方法
US20170025384A1 (en) Semiconductor chip and semiconductor package having the same
US11417629B2 (en) Three-dimensional stacking structure and manufacturing method thereof
KR102318303B1 (ko) 다이 스택 및 그 형성 방법
TW201813008A (zh) 半導體封裝及其製造方法
US11699694B2 (en) Method of manufacturing semiconductor package structure
US11462495B2 (en) Chiplets 3D SoIC system integration and fabrication methods
CN104576585B (zh) 形成连接至多个穿透硅通孔(tsv)的图案化金属焊盘的机制
TW202109793A (zh) 封裝
US20240021576A1 (en) Through-dielectric vias for direct connection and method forming same
TW202117828A (zh) 半導體結構的製作方法
TW202141689A (zh) 具有通孔保護層的半導體裝置
TW202312395A (zh) 半導體封裝
CN116705736A (zh) 半导体封装件
US20240088077A1 (en) Chiplets 3d soic system integration and fabrication methods
KR20230127836A (ko) 활성 다이 및 더미 다이를 본딩하는 방법 및 그의 구조
US20240153899A1 (en) Bonding Structure of Dies with Dangling Bonds
US20230361048A1 (en) Semiconductor package and method of fabricating semiconductor package
US20140264833A1 (en) Semiconductor package and method for fabricating the same
TW202249175A (zh) 封裝結構、封裝結構的製造方法以及半導體結構
KR20240031901A (ko) 3dic 패키지 및 그 형성 방법
CN116646313A (zh) 半导体封装件及其形成方法