CN111211058B - 形成封装的方法以及集成电路器件的封装 - Google Patents

形成封装的方法以及集成电路器件的封装 Download PDF

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CN111211058B
CN111211058B CN201911139975.1A CN201911139975A CN111211058B CN 111211058 B CN111211058 B CN 111211058B CN 201911139975 A CN201911139975 A CN 201911139975A CN 111211058 B CN111211058 B CN 111211058B
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die
dummy
bond pad
pad
semiconductor substrate
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CN111211058A (zh
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陈宪伟
陈明发
胡致嘉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法，包括：抛光第一管芯的半导体衬底以露出延伸至所述半导体衬底中的第一通孔、在所述半导体衬底上形成第一介电层、以及在所述介电层中形成多个接合焊盘。所述多个接合焊盘包括有源接合焊盘和伪接合焊盘。所述有源接合焊盘电耦接至所述第一通孔。所述第一管芯接合至第二管芯，所述有源接合焊盘和所述伪接合焊盘均接合至所述第二管芯中的对应的接合焊盘。本发明的实施例涉及形成封装的方法、以及集成电路器件的封装。

Description

形成封装的方法以及集成电路器件的封装
技术领域
本发明的实施例涉及形成封装的方法、以及集成电路器件的封装。
背景技术
集成电路的封装正变得越来越复杂，其中更多的器件管芯封装在同一封装中以实现更多功能。例如，已经开发了一种封装结构，以在同一封装中包括多个器件管芯，比如，处理器和存储器立方体。封装结构可包括使用不同技术形成的器件管芯，并具有结合到相同的器件管芯的不同功能，从而形成系统。这可节省制造成本并优化器件性能。例如，存储器管芯可接合至逻辑管芯。此外，存储器管芯可形成存储器管芯叠层，其中上部存储器管芯接合至对应的下部存储器管芯。
发明内容
根据本发明一方面的实施例，提供一种形成封装的方法，包括：抛光第一管芯的半导体衬底以露出延伸至所述半导体衬底中的第一通孔；在所述半导体衬底上形成介电层；在所述介电层中形成多个接合焊盘，其中，所述多个接合焊盘包括第一有源接合焊盘和第一伪接合焊盘，其中，所述第一有源接合焊盘电耦接至所述第一通孔；以及将所述第一管芯接合至第二管芯，其中，所述第一有源接合焊盘和所述第一伪接合焊盘均接合至所述第二管芯中的对应的接合焊盘。
根据本发明又一方面的实施例，提供一种形成封装的方法，包括：形成第一管芯，所述第一管芯包括第一半导体衬底、以及穿透所述第一半导体衬底的第一通孔；形成第二管芯，所述第二管芯包括第二半导体衬底、穿透所述第二半导体衬底的第二通孔、第一有源接合焊盘、以及第一悬空接合焊盘；以及在所述第一管芯上接合所述第二管芯，其中，通过所述第一管芯和所述第二管芯之间的第二有源接合焊盘将所述第一有源接合焊盘电耦接至第一管芯，以及将所述第一悬空接合焊盘接合至所述第一管芯和所述第二管芯之间的第一伪焊盘。
根据本发明再一方面的实施例，提供一种集成电路器件的封装，所述封装包括：第一管芯，所述第一管芯包括第一半导体衬底、穿透所述第一半导体衬底的第一通孔、以及位于所述第一半导体衬底上并与所述第一半导体衬底接触的第一介电层；第二介电层，所述第二介电层位于所述第一管芯上；第一有源接合焊盘，所述第一有源接合焊盘位于所述第二介电层中，所述第一有源接合焊盘位于所述第一通孔上并与所述第一通孔接触；第一伪接合焊盘，所述第一伪接合焊盘位于所述第二介电层中，其中，所述第一伪接合焊盘的整个底面位于所述第一介电层上并与所述第一介电层接触；以及第二管芯，所述第二管芯包括位于所述第一有源接合焊盘上并与所述第一有源接合焊盘接合的第二有源接合焊盘、以及位于所述第一伪接合焊盘上并与所述第一伪接合焊盘接合的悬空接合焊盘。
本发明涉及管芯与悬空接合焊盘的接合结构。
附图说明
当与附图一起阅读时，从下面的详细描述可以最好地理解本发明的各方面。应该强调的是，根据工业中的标准实践，各个部件没有被按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以被任意增加或减少。
图1至图4示出了根据一些实施例的形成伪管芯的中间阶段的截面图。
图5至图10示出了根据一些实施例的形成器件管芯的中间阶段的截面图。
图11至图23示出了根据一些实施例的形成具有堆叠管芯的封装的中间阶段的截面图。
图24至图32示出了根据一些实施例的具有堆叠管芯的一些封装的截面图和俯视图。
图33示出了根据一些实施例的用于形成封装的工艺流程。
具体实施方式
以下公开为实现本发明的不同特征提供了诸多不同的实施例或者实例。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，也可以包括在第一部件和第二部件之间形成的附加部件使得第一部件和第二部件不直接接触的实施例。此外，本发明可能会在各种实例中重复参考标号和/或字母。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“底覆”、“在…下面”、“下部”、“上覆”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语意欲包括使用或操作过程中的器件的不同方位。该装置可以以其它方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可同样地作相应地解释。
根据各种实施例，提供一种包括堆叠管芯的封装及其形成方法。示出了根据一些实施例的形成该封装的中间阶段。讨论了一些实施例的一些变例。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。根据本发明公开的一些实施例，该封装包括接合至底部管芯的上部管芯，其中该上部管芯包括有源焊盘和悬空焊盘。该下部管芯具有穿透相应的半导体衬底的通孔。在该通孔上形成介电层，并在该介电层中形成有源接合焊盘和伪焊盘。将该伪焊盘接合至该悬空焊盘，以提高接合强度并减少接合结构中的问题。
图1至图23示出了根据本发明公开的一些实施例的形成封装的中间阶段的截面图。相应的工艺也在图33中所示的工艺流程中示意性地反映出来。
图1至图4示出了根据一些实施例的伪管芯的形成，其中将伪管芯放置在管芯叠层中。如图33所示，相应的工艺被示出为工艺流程200中的工艺201。参考图1，提供了晶圆20。晶圆20包括衬底22和衬底22上的缓冲层24。根据本发明公开的一些实施例，衬底22是硅衬底。根据其他实施例，衬底22可由具有接近硅的热膨胀系数(CTE)的材料形成，且其导热率接近或大于硅的导热率。缓冲层24可由具有比随后形成的接合层26(图2)更低的杨氏模量(因此更软)的材料形成，使得其可用作吸收来自接合层26的应力的应力吸收层。例如，缓冲层24可由正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃(USG)等形成。缓冲层24的形成可包括等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、化学气相沉积(CVD)等。
参考图2，形成了接合层26。根据本发明公开的一些实施例，接合层26由氧化物形成，该氧化物可以是含硅和氧的氧化物，比如氧化硅、氧氮化硅等。可使用PECVD、LPCVD、CVD等形成接合层26。
根据一些实施例，在接合层26中形成伪金属焊盘27。根据一些实施例，未在接合层26中形成任何伪金属焊盘。例如伪金属焊盘27可由铜形成，且可存在或不存在扩散阻挡层，形成的扩散阻挡层为了将伪金属焊盘27中的铜与接合层26和缓冲层24分离。根据一些实施例，可使用单镶嵌工艺来形成伪金属焊盘27。
图3示出了晶圆20中沟道28的形成。当从晶圆20的顶部观察时，沟道28形成网格。沟道28从接合层26的顶面延伸至中间层面的衬底22，其中中间层面位于衬底22的顶面和底面之间。可使用刀片、激光束等形成沟道28。
图4示出了通过研磨工艺来分割晶圆20。根据本发明公开的一些实施例，将晶圆20上下颠倒，并附接至带30上。然后从晶圆20的背面到薄衬底22执行研磨工艺，直至移除沟道28上的晶圆20的部分。因此，将晶圆20分成离散的伪管芯32。所得伪管芯32没有有源器件和无源器件，且其中可没有金属。根据一些实施例，伪管芯32包括衬底22和平面介电层，且其中除了可形成伪接合焊盘27之外没有其他金属部件。
图5至10示出了上部管芯的形成，由于该上部管芯在封装的形成中用作上层管芯，所以被命名为上部管芯。如图33所示，相应的工艺被示出为工艺流程200中的工艺202。根据本发明公开的一些实施例，上部管芯是存储器管芯，而上部管芯可以是逻辑管芯、输入-输出(IO)管芯等。存储器管芯可以是静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯、NAND存储器管芯、电阻随机存取存储器(RRAM)管芯、磁阻随机存取存储器(MRAM)管芯等。如图5所示，示出了晶圆31。根据一些实施例，晶圆31包括半导体衬底34，该半导体衬底可以是硅衬底、硅锗衬底等。例如，在半导体衬底34的顶部形成集成电路器件36。集成电路器件36可包括晶体管、电阻器、电容器、电感器和/或类似物。集成电路器件36可执行存储功能、逻辑功能、IO功能等。在半导体衬底34上形成互连结构38，且该互连结构包括介电层37和介电层37中的金属线和通孔42。将金属线和通孔42电连接至集成电路器件36。
参考图6，将通孔42形成为延伸进半导体衬底34。根据一些实施例，通孔42从互连结构38的顶面延伸进半导体衬底34。根据替代性实施例，在形成互连结构38的整体或上部之前，在半导体衬底34中预先形成通孔42。通孔42可由诸如钨、铜等的导电材料形成。可形成隔离层(未示出)以围绕每个通孔42，以使对应的通孔42与半导体衬底34电绝缘。通孔42的形成可包括蚀刻介电层37和半导体衬底34以形成开口，并用隔离层和导电材料填充该开口。可执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺，以使通孔42的顶面与顶部介电层37的顶面齐平。
图7示出了晶圆31的进一步形成。根据一些实施例，该形成包括形成介电层39及金属线和通孔40以延伸互连结构38、在介电层39的顶层中形成顶部金属焊盘44、形成钝化层46，以及形成金属焊盘48。根据本发明公开的一些实施例，一些介电层37和39由低k介电材料形成。钝化层46可由介电常数等于或高于氧化硅的介电常数(3.9)的非低k介电材料形成。金属焊盘48可由铝或铝铜形成。
图8示出了介电层50、通孔51、介电层54和介电层54中的接合焊盘52A和52B的形成。根据一些实施例，如图8所示，介电层50和54是在不同的形成工艺中形成的单独的介电层。根据替代性实施例，介电层50和54是在相同的形成工艺中形成的相同介电层的部分。介电层54可由含硅和氧的介电材料形成，比如氧化硅、氮氧化硅等。介电层50可由与介电层54的材料相同的材料形成，或可由与介电层54的材料不同的材料形成。例如，介电层50可由氧化硅、氧氮化硅、氮化硅、硅碳氮等形成。接合焊盘52A和52B以及通孔51可由铜形成，并可使用单镶嵌或双镶嵌工艺来形成。介电层54和接合焊盘52A和52B的顶面是共面的。
图9示出了晶圆31中沟道56的形成。当从晶圆31的顶部观察时，沟道56形成网格，其中示出一个沟道56作为示例。沟道56从介电层54的顶面延伸至半导体衬底34的中间层面，其中中间层面位于半导体衬底34的顶面和底面之间。可使用刀片、激光束等形成沟道56。
图10示出了通过研磨工艺来分割晶圆31。根据本发明公开的一些实施例，将晶圆31上下颠倒，并附接至带58上。然后执行从晶圆31的背面到薄半导体衬底34的研磨工艺，直至移除沟道56上的半导体衬底34的部分。因此，将晶圆31分成彼此相同的离散管芯60。
图11至23示出了封装伪管芯32(图4)和管芯60(图10)以形成封装的截面图。参考图11，提供了载体62。根据一些实施例，载体62由硅、玻璃等形成，并以晶圆形式提供，该晶圆形式足够大到可容纳将被接合在其上的多个器件管芯。在载体62上形成介电层64。如图33所示，相应的工艺被示出为工艺流程200中的工艺203。根据本发明公开的一些实施例，介电层64由比随后形成的接合层68更软的相对较软的材料形成，因此用作吸收应力的缓冲层。介电层64可由TEOS氧化物、USG等形成。介电层64的形成可包括PECVD、LPCVD、CVD等。根据一些实施例，在介电层64中形成金属部件66。金属部件66可用作对准标记，用于对准器件管芯的后续放置和接合。例如，可通过镶嵌工艺来形成金属部件66。
参考图12，形成了接合层68。如图33所示，相应的工艺被示出为工艺流程200中的工艺204。根据本发明公开的一些实施例，接合层68由氧化物形成，该氧化物可以是含硅和氧的氧化物，比如氧化硅、氧氮化硅等。可使用PECVD、LPCVD、CVD等形成接合层68。接合层68的形成可包括沉积工艺、然后是平坦化工艺。
图13示出了接合层68上的第1层管芯70之一的放置和接合。如图33所示，相应的工艺被示出为工艺流程200中的工艺206。尽管示出了一个第1层管芯70，但是可将多个第1管芯70放置并接合至接合层68上。可将多个第1层管芯70布置成阵列。对准标记66用于将第1层管芯70对准预期位置。根据一些实施例，第1层管芯70是逻辑管芯，该逻辑管芯可以是应用处理器(AP)管芯、图形处理单元(GPU)管芯、现场可编程门阵列(FPGA)管芯、专用集成电路(ASIC)管芯、输入输出(IO)管芯、网络处理单元(NPU)管芯、张量处理单元(TPU)管芯、人工智能(AI)引擎管芯等。除了第1层管芯70中的部件的附图标记数字比管芯60中的类似对应部件的附图标记数字增加了100，还将逻辑管芯70中的部件标记为对应于管芯60(图10)的标记。例如，逻辑管芯70可包括半导体衬底134、集成电路器件136、互连结构138、金属线和通孔140、通孔142、金属焊盘144和148，以及接合层154。管芯70的形成可包括类似于图5至7中所示的工艺步骤、然后是接合层154的形成(图13)、然后是图9和10中所示的工艺。第1层管芯70的标记部件的一些材料也可类似于管芯60中的相应部件的材料。第1层管芯70的结构与管芯60(图10)的结构不同。如图13所示，可将金属焊盘148嵌入介电层(比如，接合层154)。根据一些实施例，第1层管芯70的厚度T1在约50微米到约150微米的范围内。
管芯70与接合层64的接合可通过熔融接合(电介质与电介质接合)，这可形成Si-O-Si接合以将接合层154和68接合在一起。
图14示出了形成介电区域72的间隙填充工艺，该介电区域填充第1层管芯70之间的间隙并围绕该管芯。如图33所示，相应的工艺被示出为工艺流程200中的工艺208。根据一些实施例，间隙填充工艺包括分配或涂覆可流动的介电材料、然后是固化可流动的介电材料。对应的介电区域72可由模塑料、模塑底部填料、树脂、环氧树脂等形成。根据替代性实施例，介电区域72的形成可包括沉积一个或多个介电材料层。例如，介电区域72可包括由氮化硅形成的介电衬里，以及在介电衬里上方的另一种介电材料(例如氧化硅)。可执行诸如CMP工艺或机械研磨工艺的平坦化工艺以移除多余的介电材料，并使半导体衬底134的顶面与介电区域72齐平。根据一些实施例，在间隙填充工艺之后，第1层管芯70的厚度T2在约10微米到约15微米的范围内。
图15示出了减薄第1层管芯70并露出通孔142的背面研磨工艺。如图33所示，相应的工艺被示出为工艺流程200中的工艺210。背面研磨工艺可以是如图14所示的平坦化工艺的连续部分，或可以是与平坦化工艺分开执行的单独工艺，如图14所示。在背面研磨工艺之后，还露出了半导体衬底134，其中该半导体衬底的顶面与通孔142和介电区域72的顶面共面。接下来，使用侵蚀半导体衬底134而不侵蚀通孔142和介电区域72的蚀刻剂来蚀刻半导体衬底134。结果，形成凹槽，其中通孔142的顶部位于凹槽中并从半导体衬底134的剩余部分的顶面伸出。在后续工艺中，形成隔离层74。如图33所示，相应的工艺也被示出为工艺流程200中的工艺210。隔离层74由介电材料形成，该介电材料可包括氧化硅、氮化硅、氮氧化硅、碳氧化硅等。然后执行平坦化工艺，以平整通孔142、隔离层74和介电区域72的顶面。根据一些实施例，在形成隔离层74之后，第1层管芯70的厚度T3在约3微米到约10微米的范围内。
图16示出了接合层76及接合层76中的接合焊盘152A和152B的形成。如图33所示，相应的工艺被示出为工艺流程200中的工艺212。接合层76可由含硅和氧的介电材料形成，比如氧化硅、氮氧化硅等。该形成方法可包括CVD、ALD、PECVD等。接合焊盘152A和152B可包括铜，并可用单个镶嵌工艺来形成。接合层76和接合焊盘152A和152B的顶面是共面的。根据一些实施例，接合焊盘152A是有源接合焊盘，该有源接合焊盘电连接和/或信号耦合至集成电路器件136。另一方面，接合焊盘152B是此时电浮动的伪接合焊盘。接合焊盘152B可具有接触隔离层74的顶面的底面。
根据本发明公开的一些实施例，当形成接合焊盘152A和152B时，也同时形成接合焊盘152C和152D。将在后面的段落中参考图27至32详细讨论接合焊盘152C和152D的功能和位置。根据本发明公开的替代性实施例，未形成接合焊盘152C和152D中的一个或两个。
参考图17，将器件管芯60接合至器件管芯70。器件管芯60也称为第2层管芯60-1。如图33所示，相应的工艺被示出为工艺流程200中的工艺214。在整个说明中，部件的附图标记可跟在破折号和整数之后，用于识别它们的层级。例如，根据层级层面，可将管芯60标识为60-1、60-2...60-n(图20)。根据本发明公开的一些实施例，接合可包括熔融接合，该熔融接合包括接合焊盘152A/152B和接合焊盘52A/52B之间的直接金属接合，以及介电层54和介电层76之间的电介质与电介质接合。在接合之后，接合在一起的接合焊盘152A和52A用于第2层管芯60-1(可以是存储器管芯)和第1层管芯70之间的电和/或信号连接。例如，通过接合焊盘152A和52A将第2层管芯60-1中的集成电路器件36(可包括存储器单元)电连接和/或信号连接至第1层管芯70中的集成电路器件136。
接合焊盘52B是悬空接合，该悬空接合在图25中示意性地示出以示出一些细节。将接合焊盘52B电连接至集成电路器件36(图17)(即使在相应的器件管芯60仍然是离散管芯时)。当所得封装96(图23)通电时，悬空接合焊盘52B可具有从集成电路器件36接收的电压。如果第2层管芯60-1用于其他电路或所得封装的其他部分(例如，作为第3层管芯，这将在后续段落中讨论)，则接合焊盘52B可以是具有传导电压和/或电流功能的功能(有源)焊盘。根据本发明公开的一些实施例，由于将第2层管芯60-1连接至第1层管芯70，所以接合焊盘52B不具有电和信号功能，因此是悬空的。因此，可在接合焊盘52B和152B上施加电压，但是没有电流流过接合焊盘52B和152B，这是因为接合焊盘152B是电流/电压路径的终端节点。
图18示出了伪管芯32-1与介电层76的接合。如图33所示，相应的工艺被示出为工艺流程200中的工艺216。该接合可通过熔融接合，其中将伪管芯32-1中的介电层26接合至介电层76。由于存在多个第2层管芯60-1(示出一个)，因此在多个第2层管芯60-1之间放置伪管芯32-1以占据否则将被间隙填充材料78-1所占据的空间(图19)。由于伪管芯32-1具有接近第1层管芯70和第2层管芯60的EOT，因此伪管芯32-1的添加减少了所得封装中的应力和翘曲。
图19示出了形成围绕第2层管芯60-1的介电区域78-1的间隙填充工艺。如图33所示，相应的工艺被示出为工艺流程200中的工艺218。根据一些实施例，间隙填充工艺包括分配或涂覆可流动的介电材料、然后是固化可流动的介电材料。对应的介电区域78-1可由模塑料、模塑底部填料、树脂、环氧树脂等形成。根据替代性实施例，介电区域78-1的形成可包括沉积一个或多个介电材料层。例如，介电区域78-1可包括由氮化硅形成的介电衬里，以及在介电衬里上方的另一种介电材料(例如氧化硅)。可执行诸如CMP工艺或机械研磨工艺的平坦化工艺以移除多余的介电材料，并使半导体衬底34的顶面与介电区域78-1齐平。
在后续工艺中，执行背面研磨工艺，以减薄第2层管芯60-1和伪管芯32-1，并露出通孔42。如图33所示，相应的工艺被示出为工艺流程200中的工艺220。在背面研磨工艺之后，还露出了半导体衬底34，其中该半导体衬底的顶面与通孔42和介电区域78-1的顶面共面。接下来，蚀刻半导体衬底34以形成凹槽，其中通孔42的顶部位于凹槽中并从半导体衬底34的剩余部分的顶面伸出。在后续工艺中，在凹槽中形成隔离层80-1。如图33所示，相应的工艺也被示出为工艺流程200中的工艺220。隔离层80-1由介电材料形成，该介电材料可包括氧化硅、氮化硅、氮氧化硅、碳氧化硅等。然后执行平坦化工艺，以平整通孔42、隔离层80-1和介电区域78-1的顶面。
图19还示出了接合层82-1及接合层82-1中的接合焊盘252A和252B的形成。如图33所示，相应的工艺被示出为工艺流程200中的工艺222。接合层82-1可由含硅和氧的介电材料形成，比如氧化硅、氮氧化硅等。该形成方法可包括CVD、ALD、PECVD等。接合焊盘252A和252B可由铜形成，并可用单个镶嵌工艺来形成。接合层82-1和接合焊盘252A和252B的顶面是共面的。根据一些实施例，接合焊盘252A是有源接合焊盘，该有源接合焊盘电耦接至集成电路(比如，36)。例如，当管芯60-1和随后接合的管芯60-2彼此相同时，接合焊盘252B可以是与接合焊盘252A相同的有源接合焊盘。图19示意性地示出了虚线83，该虚线表示将接合焊盘252B电连接至集成电路器件36的导电部件，其中导电部件可包括过孔和金属焊盘、金属线、通孔等。根据替代性实施例，接合焊盘252B也可以是伪接合焊盘。根据一些实施例，在接合焊盘252A/252B与下覆接合焊盘52A/52B(和152A/152B)之间存在一对一的对应关系，其中每个接合焊盘252A/252B垂直地对准并叠覆相应的接合焊盘52A/52B和对应的接合焊盘152A/152B。
根据本发明公开的一些实施例，当形成接合焊盘252A和252B时，也同时形成接合焊盘252C和252D。将在后面的段落中参考图27至32详细讨论接合焊盘252C和252D的功能和位置。
图20示出了图17至19中所示的过程的重复，以堆叠更多层的管芯60。例如，假设存在n层管芯60，其中顶层管芯被称为第n层管芯60-n。整数n可以是等于或大于2的任何数字。上层管芯60-2至60-n可与第2层管芯60-1相同或不同。在顶层管芯60-n和伪管芯32-n接合之后，形成间隙填充区域78-n并进行平坦化，然后形成介电层82-n，该介电层也可以是接合层。
图21示出了载体切换工艺。如图33所示，相应的工艺被示出为工艺流程200中的工艺224。通过接合层84将载体85接合至接合层82-n，其中接合方法是熔融接合。根据一些实施例，载体85由硅形成，并是没有有源器件、无源器件、导电线等的空白载体。接合层84可由含硅和氧的材料形成，比如氧化硅、氮氧化硅等。
接下来，例如，在CMP工艺或机械研磨工艺中移除载体62、缓冲层64和接合层68。在后续工艺中，形成钝化层86，该钝化层可包括氧化硅、氮化硅或其复合层。在钝化层86中形成开口88。如图33所示，相应的工艺被示出为工艺流程200中的工艺226。所得结构如图22所示。例如，然后可通过使探针卡(未示出)的探针与金属焊盘148接触来执行探测过程，以确定所得封装是否有缺陷。记录已知的良好封装。如图33所示，相应的工艺被示出为工艺流程200中的工艺228。
图23示出了聚合物层90的形成，该聚合物层可由聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等形成。然后，可在金属焊盘148上形成电连接器92，该电连接器可包括金属柱93和焊接区域94。如图33所示，相应的工艺被示出为工艺流程200中的工艺230。所得结构被称为重构晶圆(封装)97。在后续工艺中，在重构晶圆97上执行分割工艺，并形成多个相同的封装96。如图33所示，相应的工艺被示出为工艺流程200中的工艺232。
图24至图32示意性示出了根据本发明公开的一些实施例的封装96的截面图和俯视图。未示出一些细节，而可参考图11至图23找到这些细节。在这些附图中，示出了两层器件管芯60，以表示可能的多层器件管芯60，如图23所示。示出了功能(有源)接合焊盘52A和152A、悬空接合焊盘52B和伪接合焊盘152B。一些接合焊盘被示为52A/52B，以表示这些接合焊盘可以是功能接合焊盘52A或悬空接合焊盘52B。类似地，一些接合焊盘被示为152A/152B，以表示这些接合焊盘可以是功能接合焊盘152A或伪接合焊盘152B。应了解，尽管在图24至32中未示出填充介电区域72(图23)，但是介电区域72可(或可不)在封装96中，如图24至32所示。
根据本发明公开的一些实施例，如图24所示，形成在第1层管芯70上的接合焊盘(包括152A和152B)全部由第2层管芯60-1叠覆，且没有直接形成在介电区域78-1和伪管芯32-1下面并与之接触的接合焊盘。图25示出了接合焊盘52A、52B、152A和152B的放大视图。
图26示出了接合焊盘52A、52B、152A和152B、第1层管芯70、第2层管芯60-1和伪管芯32-1的俯视图。根据本发明公开的一些实施例，接合焊盘52A、52B、152A和152B形成阵列，并在由第2层管芯60覆盖的区域中受到限制，其中在第2层管芯60-1覆盖的区域之外没有接合管芯。
图27和图28分别示出了根据一些实施例的封装96的俯视图和截面图。这些实施例类似于图24和26中的实施例，除了还在由介电区域78-1叠覆的区域中形成伪接合焊盘152C。因此，在封装96中，伪焊盘152C是电浮动的，其中焊盘152C的顶面与介电区域78-1的底面接触。此外，将接合焊盘152C完全封闭在介电区域中。在接合焊盘的形成中，诸如焊盘阵列的致密焊盘区域的边缘部分可以是不均匀的，例如，其中焊盘阵列的边缘部分比焊盘阵列的中心部分更多或更少地被抛光。通过形成伪焊盘152C，非均匀性集中在焊盘阵列的边缘部分的伪焊盘152C中，而接合焊盘152A和152B则更均匀。
图29和图30分别示出了根据一些实施例的封装96的俯视图和截面图。这些实施例类似于图24和26中的实施例，除了还在由介电区域78-1和伪管芯32-1叠覆的区域中形成伪接合焊盘152C和152D。在封装96中，伪焊盘152C和152D是电浮动的，其中接合焊盘152C的顶面与介电区域72的底面接触，且接合焊盘152D的顶面与伪管芯32的底面接触。根据一些实施例，将伪焊盘152C和152D完全封闭在介电区域中。根据替代性实施例，将接合焊盘152D接合至伪管芯32-1中的接合焊盘27。伪焊盘152C和152D的形成改善了用于形成焊盘152A和152B的平坦化工艺的均匀性。
图31和图32分别示出了根据一些实施例的封装96的俯视图和截面图。除了不采用伪管芯32之外，这些实施例类似于图24和26中的实施例。还将伪接合焊盘152C形成在由介电区域78-1叠覆的区域中。因此，在封装96中，伪焊盘152C是电浮动的，其中焊盘152C的顶面与介电区域72的底面接触。此外，将伪焊盘152C完全封闭在介电区域中。伪焊盘152C的形成改善了用于形成接合焊盘152A和152B的平坦化工艺的均匀性。
在上述实施例中，根据本发明的一些实施例讨论了一些工艺和部件。还可包括其他部件和工艺。例如，可包括测试结构以帮助3D封装或3D IC器件的验证测试。例如，测试结构可包括在再分布层中或衬底上形成的测试焊盘，以实现了3D封装或3D IC测试、探针和/或探针卡的使用等。可在中间结构以及最终结构上执行验证测试。另外，本发明公开的结构和方法可与测试方法结合使用，该测试方法对已知良好管芯进行中间验证，以提高产量并降低成本。
本发明公开的实施例具有一些有利特征。通过在下层管芯中的附加介电层中形成附加介电层和伪焊盘，上层管芯中的悬空焊盘与伪焊盘接合，而不是与介电材料接触。因此提高了接合强度。
根据本发明公开的一些实施例，一种方法，包括：抛光第一管芯的半导体衬底以露出延伸至所述半导体衬底中的第一通孔；在所述半导体衬底上形成介电层；在所述介电层中形成多个接合焊盘，其中所述多个接合焊盘包括第一有源接合焊盘和第一伪接合焊盘，其中，所述第一有源接合焊盘电耦接至所述第一通孔；以及将所述第一管芯接合至第二管芯，其中，所述第一有源接合焊盘和所述第一伪接合焊盘均接合至所述第二管芯中的对应的接合焊盘。在一个实施例中，将所述第一有源接合焊盘接合至所述第二管芯中的第二多个有源接合焊盘，并将所述第一伪接合焊盘接合至所述第二管芯中的悬空接合焊盘，并且所述第二多个有源接合焊盘和所述悬空接合焊盘均电连接至所述第二管芯中的集成电路器件。在一个实施例中，通过混合接合将所述第一管芯和所述第二管芯接合。在一个实施例中，所述方法还包括将伪管芯接合至所述第一管芯。在一个实施例中，所述多个接合焊盘还包括第二伪接合焊盘，并且所述伪管芯还包括接合至所述第二伪接合焊盘的第三伪接合焊盘。在一个实施例中，所述方法还包括：设置填充介电材料以包围所述第二管芯；将所述第二管芯和所述填充介电材料平坦化直至暴露所述第二管芯中的第二通孔，以及形成第三有源接合焊盘，所述第三有源接合焊盘电耦接至所述第二通孔。在一个实施例中，所述多个接合焊盘还包括第四伪接合焊盘，并且所述第四伪接合焊盘的顶面与所述填充介电材料接触。在一个实施例中，所述第一管芯是逻辑管芯，所述第二管芯是存储管芯。在一个实施例中，所述方法还包括在所述第二管芯上堆叠与所述第二管芯相同的第三管芯，其中，未将所述第二管芯中并也接合至所述第三管芯的接合焊盘用作悬空接合焊盘。
根据本发明公开的一些实施例，一种方法，包括形成第一管芯，所述第一管芯包括第一半导体衬底和穿透所述第一半导体衬底的第一通孔。所述方法还包括形成第二管芯，所述第二管芯包括第二半导体衬底、穿透所述第二半导体衬底的第二通孔、第一有源接合焊盘以及第一悬空接合焊盘。在所述第一管芯上接合所述第二管芯，其中，通过所述第一管芯和所述第二管芯之间的第二有源接合焊盘将所述第一有源接合焊盘电耦接至第一管芯，所述第一悬空接合焊盘接合至所述第一管芯和所述第二管芯之间的第一伪焊盘。在一个实施例中，所述方法还包括：在载体上放置所述第一管芯；将所述第一管芯包封在填充介电材料中；形成与所述第一管芯和所述填充介电材料重叠的介电层；以及在所述介电层中形成所述第二有源接合焊盘和所述第一悬空接合焊盘。在一个实施例中，所述方法还包括执行间隙填充工艺，以将所述第二管芯嵌入间隙填充材料中，其中，所述间隙填充材料位于第二伪焊盘的顶面上并与所述第二伪焊盘的顶面接触，其中所述第二伪焊盘位于所述第一管芯和所述第二管芯之间。在一个实施例中，所述方法还包括将伪管芯接合至所述第一管芯，其中，所述伪管芯接触所述第一管芯和所述第二管芯之间的第三伪焊盘，并且所述第三伪焊盘与所述第二有源接合焊盘和所述第一伪焊盘处于同一层面。在一个实施例中，所述伪管芯还包括第四伪焊盘，所述第四伪焊盘接合至所述伪管芯中的所述第三伪焊盘。在一个实施例中，在将所述第二管芯接合至所述第一管芯之前，所述第一伪焊盘是电浮动的。在一个实施例中，所述方法还包括：抛光所述第一半导体衬底以露出所述第一通孔；在所述第一半导体衬底上形成介电层并与所述第一半导体衬底接触；以及在所述介电层中形成所述第二有源接合焊盘和所述第一伪焊盘，其中，所述第一伪焊盘的整个底面与所述第一管芯中的额外介电层的顶面接触。
根据本发明公开的一些实施例，集成电路器件的封装包括：第一管芯，所述第一管芯包括第一半导体衬底、穿透所述第一半导体衬底的第一通孔、以及位于所述第一半导体衬底上并与所述第一半导体衬底接触的第一介电层；位于所述第一管芯上的第二介电层；位于所述第二介电层中的第一有源接合焊盘，所述第一有源接合焊盘位于所述第一通孔上并与所述第一通孔接触；位于所述第二介电层中的第一伪接合焊盘，其中，所述第一伪接合焊盘的整个底面位于所述第一介电层上并与所述第一介电层接触；以及第二管芯，所述第二管芯包括位于所述第一有源接合焊盘上并接合至所述第一有源接合焊盘的第二有源接合焊盘、以及位于所述第一伪接合焊盘上并接合至所述第一伪接合焊盘的悬空接合焊盘。在一个实施例中，所述第一管芯是逻辑管芯，所述第二管芯是存储管芯。在一个实施例中，所述封装还包括：第二伪接合焊盘，所述第二伪接合焊盘位于所述第二介电层中；以及填充介电材料，所述填充介电材料包围所述第二管芯，其中，所述填充介电材料接触所述第二伪接合焊盘的顶面。在一个实施例中，所述封装还包括：第二伪接合焊盘，所述第二伪接合焊盘位于所述第二介电层中；以及伪管芯，所述伪管芯位于所述第二伪接合焊盘上并与所述第二伪接合焊盘接触。
前述概述了若干实施例的特征，使得本领域技术人员可更好地理解本发明的各方面。本领域技术人员应当理解，他们可以容易地使用本公开作为基础来设计或修改其他用于达到与实施与本文所介绍的实施例相同目的和/或实现相同优点的工艺和结构。本领域技术人员还应该认识到，这样的等效结构不脱离本公开的精神和范围，并且在不脱离本公开的精神和范围的情况下，它们可以在本发明中进行各种改变、替换和变更。

Claims (20)

1.一种形成封装的方法，包括：
抛光第一管芯的半导体衬底以露出延伸至所述半导体衬底中的第一通孔；
在所述半导体衬底上形成介电层；
在所述介电层中形成多个接合焊盘，其中，所述多个接合焊盘包括第一有源接合焊盘和第一伪接合焊盘，其中，所述第一有源接合焊盘电耦接至所述第一通孔；
将所述第一管芯接合至第二管芯，其中，所述第一有源接合焊盘和所述第一伪接合焊盘均接合至所述第二管芯中的对应的接合焊盘；以及
设置填充介电材料以包围所述第二管芯，
其中，所述多个接合焊盘还包括第四伪接合焊盘，所述第四伪接合焊盘的顶面与所述填充介电材料接触，
其中，抛光第一管芯的半导体衬底以露出所述第一通孔包括：
使用背面研磨工艺使得所述半导体衬底的顶面与所述第一通孔的顶面共面；以及
使用侵蚀所述半导体衬底而不侵蚀所述第一通孔的蚀刻剂来蚀刻所述半导体衬底，从而形成凹槽，其中，所述第一通孔的顶部位于凹槽中并从所述半导体衬底的剩余部分的顶面伸出，
其中，在将所述第一管芯接合至所述第二管芯之前，将所述第一管芯接合至载体上方的接合层，其中，具有对准标记的附加介电层设置在所述载体和所述接合层之间。
2.根据权利要求1所述的方法，其中，将所述第一有源接合焊盘接合至所述第二管芯中的第二多个有源接合焊盘，并将所述第一伪接合焊盘接合至所述第二管芯中的悬空接合焊盘，并且将所述第二多个有源接合焊盘和所述悬空接合焊盘均电连接至所述第二管芯中的集成电路器件。
3.根据权利要求1所述的方法，其中，通过混合接合将所述第一管芯和所述第二管芯接合。
4.根据权利要求1所述的方法，还包括将伪管芯接合至所述第一管芯。
5.根据权利要求4所述的方法，其中，所述多个接合焊盘还包括第二伪接合焊盘，所述伪管芯还包括接合至所述第二伪接合焊盘的第三伪接合焊盘。
6.根据权利要求1所述的方法，还包括：
将所述第二管芯和所述填充介电材料平坦化，直至暴露所述第二管芯中的第二通孔；以及
形成第三有源接合焊盘，所述第三有源接合焊盘电耦接至所述第二通孔。
7.根据权利要求6所述的方法，其中，在顶视图中，所述第四伪接合焊盘围绕所述第二管芯。
8.根据权利要求1所述的方法，其中，所述第一管芯是逻辑管芯，所述第二管芯是存储管芯。
9.根据权利要求1所述的方法，还包括在所述第二管芯上堆叠与所述第二管芯相同的第三管芯，其中，所述第二管芯中的有源接合焊盘接合至所述第三管芯。
10.一种形成封装的方法，包括：
形成第一管芯，所述第一管芯包括：
第一半导体衬底；以及
第一通孔，所述第一通孔穿透所述第一半导体衬底；
形成第二管芯，所述第二管芯包括：
第二半导体衬底；
第二通孔，所述第二通孔穿透所述第二半导体衬底；
第一有源接合焊盘；以及
第一悬空接合焊盘；以及
在所述第一管芯上接合所述第二管芯，其中，通过所述第一管芯和所述第二管芯之间的第二有源接合焊盘将所述第一有源接合焊盘电耦接至第一管芯，以及将所述第一悬空接合焊盘接合至所述第一管芯和所述第二管芯之间的第一伪焊盘，
其中，形成所述第一管芯包括：
使用背面研磨工艺使得所述第一半导体衬底的顶面与所述第一通孔的顶面共面；以及
使用侵蚀所述第一半导体衬底而不侵蚀所述第一通孔的蚀刻剂来蚀刻所述第一半导体衬底，从而形成凹槽，其中，所述第一通孔的顶部位于凹槽中并从所述第一半导体衬底的剩余部分的顶面伸出，
其中，在所述第一管芯上接合所述第二管芯之前，将所述第一管芯接合至载体上方的接合层，其中，具有对准标记的附加介电层设置在所述载体和所述接合层之间。
11.根据权利要求10所述的方法，还包括：
在载体上放置所述第一管芯；
将所述第一管芯包封在填充介电材料中；
形成介电层，所述介电层与所述第一管芯和所述填充介电材料重叠；以及
在所述介电层中形成所述第二有源接合焊盘和第一伪接合焊盘。
12.根据权利要求10所述的方法，还包括：
执行间隙填充工艺以将所述第二管芯嵌入间隙填充材料中，其中所述间隙填充材料在第二伪焊盘的顶面上并与所述第二伪焊盘的顶面接触，并且所述第二伪焊盘位于所述第一管芯和所述第二管芯之间。
13.根据权利要求10所述的方法，还包括：
将伪管芯接合至所述第一管芯，其中所述伪管芯接触所述第一管芯和所述第二管芯之间的第三伪焊盘，并且所述第三伪焊盘与所述第二有源接合焊盘和所述第一伪焊盘处于同一层面。
14.根据权利要求13所述的方法，其中，所述伪管芯还包括第四伪焊盘，所述第四伪焊盘接合至所述第三伪焊盘。
15.根据权利要求10所述的方法，其中，在将所述第二管芯接合至所述第一管芯之前，所述第一伪焊盘是电浮动的。
16.根据权利要求10所述的方法，还包括：
抛光所述第一半导体衬底以露出所述第一通孔；
在所述第一半导体衬底上形成介电层并与所述第一半导体衬底接触；以及
在所述介电层中形成所述第二有源接合焊盘和所述第一伪焊盘，其中，所述第一伪焊盘的整个底面与所述第一管芯中的额外介电层的顶面接触。
17.一种集成电路器件的封装，所述封装包括：
第一管芯，所述第一管芯包括：
第一半导体衬底；
第一通孔，所述第一通孔穿透所述第一半导体衬底；以及
第一介电层，所述第一介电层位于所述第一半导体衬底上并与所述第一半导体衬底接触；
第二介电层，所述第二介电层位于所述第一管芯上；
第一有源接合焊盘，所述第一有源接合焊盘位于所述第二介电层中，所述第一有源接合焊盘位于所述第一通孔上并与所述第一通孔接触；
第一伪接合焊盘，所述第一伪接合焊盘位于所述第二介电层中，其中，所述第一伪接合焊盘的整个底面位于所述第一介电层上并与所述第一介电层接触；以及
第二管芯，所述第二管芯包括：
第二有源接合焊盘，所述第二有源接合焊盘位于所述第一有源接合焊盘上并与所述第一有源接合焊盘接合；
悬空接合焊盘，所述悬空接合焊盘位于所述第一伪接合焊盘上并与所述第一伪接合焊盘接合；以及
第二伪接合焊盘，所述第二伪接合焊盘位于所述第二介电层中；以及
填充介电材料，所述填充介电材料包围所述第二管芯，其中，所述填充介电材料接触所述第二伪接合焊盘的顶面，
其中，在顶视图中，所述第二伪接合焊盘从所述第二管芯的四个侧面围绕所述第二管芯，
其中，所述第一有源接合焊盘和所述第一伪接合焊盘比所述第二伪接合焊盘更均匀。
18.根据权利要求17所述的封装，其中，所述第一管芯是逻辑管芯，所述第二管芯是存储管芯。
19.根据权利要求17所述的封装，还包括：
第三管芯，堆叠在所述第二管芯上并且与所述第二管芯相同，其中，所述第二管芯中的有源接合焊盘接合至所述第三管芯。
20.根据权利要求17所述的封装，还包括：
伪管芯，所述伪管芯设置在所述填充介电材料周围。
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