CN114843247A - 具有可去除的探针衬垫的堆叠半导体器件 - Google Patents

具有可去除的探针衬垫的堆叠半导体器件 Download PDF

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CN114843247A
CN114843247A CN202210084465.4A CN202210084465A CN114843247A CN 114843247 A CN114843247 A CN 114843247A CN 202210084465 A CN202210084465 A CN 202210084465A CN 114843247 A CN114843247 A CN 114843247A
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insulating film
conductive pattern
interlayer insulating
region
semiconductor substrate
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横井直记
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本申请案涉及具有可去除的探针衬垫的堆叠半导体器件。本文公开一种方法，其包含：形成待嵌入在形成于半导体衬底上的第一绝缘膜中的接触插塞；在所述第一绝缘膜上形成探针衬垫以与所述接触插塞接触；通过探测所述探针衬垫来执行测试操作；去除探针衬垫；在去除所述探针衬垫之后形成第二绝缘膜以覆盖所述接触插塞；以及形成待嵌入在所述第二绝缘膜中的衬垫电极。

Description

具有可去除的探针衬垫的堆叠半导体器件
技术领域
本公开涉及半导体芯片，且确切地说，涉及具有可去除的探针衬垫的堆叠半导体器件。
背景技术
存在连接三维堆叠的半导体芯片的已知方法，其包含经由焊料凸块连接半导体芯片、在无焊料的情况下将上部半导体芯片和下部半导体芯片的衬垫电极彼此直接接合的直接接合，以及不仅将上部半导体芯片和下部半导体芯片的衬垫电极彼此接合，而且将位于上部半导体芯片和下部半导体芯片的最外表面上的绝缘膜彼此接合的混合接合的方法。为了实现混合接合，每一半导体芯片的接合表面需要为平坦的。然而，当半导体芯片在测试过程中经历探测时，存在探针标记形成于探针衬垫上的问题且其导致半导体芯片的接合表面的平坦度削弱。
发明内容
本公开的一方面提供一种装置，其包括：半导体衬底；多个层间绝缘膜，其位于半导体衬底上；以及多个导电图案，其嵌入在层间绝缘膜中，其中多个导电图案包含嵌入在多个层间绝缘膜中的最上一者中的第一导电图案和第二导电图案，其中第一导电图案具有从多个层间绝缘膜中的最上一者暴露的上部表面，且其中第二导电图案具有由多个层间绝缘膜中的最上一者覆盖而不暴露的上部表面。
本公开的另一方面提供一种装置，其包括：半导体衬底，其具有前表面和后表面；多个布线层，其形成于半导体衬底的前表面上；第一TSV和第二TSV，其穿透半导体衬底；绝缘膜，其覆盖半导体衬底的后表面；以及第一导电图案和第二导电图案，其嵌入在绝缘膜中，其中第一导电图案具有连接到第一TSV的上部表面和从绝缘膜暴露的下部表面，且其中第二导电图案具有连接到第二TSV的上部表面和由绝缘膜覆盖而不暴露的下部表面。
本公开的另一方面提供一种方法，其包括：形成待嵌入在形成于半导体衬底上的第一绝缘膜中的接触插塞；在第一绝缘膜上形成探针衬垫以与接触插塞接触；通过探测探针衬垫来执行测试操作；去除探针衬垫；在去除探针衬垫之后形成第二绝缘膜以覆盖接触插塞；以及形成待嵌入在第二绝缘膜中的衬垫电极。
附图说明
图1为用于解释根据第一实施例的半导体器件的结构的示意性横截面；
图2为根据第一实施例的半导体器件堆叠于其中的堆叠半导体器件的示意性横截面；
图3到17为用于解释制造根据第一实施例的半导体器件的方法的过程图；
图18为用于解释根据第二实施例的半导体器件的结构的示意性横截面；
图19为根据第二实施例的半导体器件堆叠于其中的堆叠半导体器件的示意性横截面；以及
图20到32为用于解释制造根据第二实施例的半导体器件的方法的过程图。
具体实施方式
下文将参考随附图式详细解释本发明的各种实施例。以下详细描述参考借助于说明展示可实践本发明的特定方面和实施例的随附图式。足够详细地描述这些实施例以使得所属领域的技术人员能够实践本发明。在不脱离本发明的范围的情况下可以利用其它实施例，且可以作出结构、逻辑和电性改变。本文中所公开的各种实施例不一定相互排斥，因为一些所公开的实施例可与一或多个其它所公开的实施例组合以形成新的实施例。
如图1中所示.根据第一实施例的半导体器件100包含硅衬底110、堆叠在硅衬底110的主表面111上的多个层间绝缘膜120以及嵌入在层间绝缘膜120中的多个导电图案130。层间绝缘膜120包含按此顺序堆叠的层间绝缘膜121到125。层间绝缘膜的数目不特定地限于任何数目。层间绝缘膜125为最上部层间绝缘膜且配置半导体器件100的最外表面中的一个。导电图案130包含嵌入在层间绝缘膜122中的导电图案131、嵌入在层间绝缘膜123中的导电图案132、嵌入在层间绝缘膜124中的导电图案133和134以及嵌入在层间绝缘膜125中的衬垫电极135和钨插塞136。导电图案130可由铜制成。最外层间绝缘膜125包含以此顺序堆叠的氧化硅膜125a、氮化硅膜125b以及氧化硅膜125c。其它层间绝缘膜121到124可主要含有氧化硅。提供衬垫电极135以穿透层间绝缘膜125。因此，衬垫电极135的表面从层间绝缘膜125的表面暴露。衬垫电极135的表面和层间绝缘膜125的表面大体上彼此共面。同时，钨插塞136被嵌入而不从层间绝缘膜125的表面暴露。钨插塞136的下部表面与导电图案134的上部表面完全接触，钨插塞136的侧表面由氧化硅膜125a完全覆盖，且钨插塞136的上部表面由氮化硅膜125b完全覆盖。也就是说，钨插塞136仅连接到导电图案134，且并不电连接到其它导电图案。
导电图案131连接到穿透硅衬底110的硅穿孔(TSV)140的上部端141。TSV 140的下部端142连接到衬垫电极160。然而，在本实施例中，在硅衬底110中提供TSV 140并非必需的。硅衬底110的后表面112由绝缘膜151到153覆盖。绝缘膜153配置半导体器件100的其它最外表面。衬垫电极160的表面和绝缘膜153的表面大体上彼此共面。
堆叠半导体器件100A可通过堆叠具有如图2中所示的此配置的多个半导体器件100而形成。在堆叠半导体器件100的情况下，下部半导体器件100和上部半导体器件100以使得作为下部半导体器件100的最上部膜的绝缘膜125c和作为上部半导体器件100的最下部膜的绝缘膜153面向彼此的方式堆叠，且执行混合接合。因此，下部半导体器件100的衬垫电极135和上部半导体器件100的衬垫电极160彼此接合，且绝缘膜125c和绝缘膜153彼此接合。
接着，描述制造半导体器件100的方法。
首先，在硅衬底110的主表面111上形成元件隔离区、晶体管、电容器等(未展示)，如图3中所示，此后形成将元件彼此连接的局部导线，且通过CVD形成覆盖其的层间绝缘膜121。此外，到达硅衬底110的内部的TSV 140由通孔中间工艺形成。TSV 140由铜制成。TSV140的表面由绝缘膜(未展示)覆盖，TSV 140借由所述绝缘膜与硅衬底110绝缘。接着，如图4中所示，形成层间绝缘膜122，且此后通过单镶嵌方法将包含导电图案131的多个导电图案嵌入在层间绝缘膜122中。导电图案131设置在与TSV 140重叠的位置处，且因此TSV 140的上部端141与导电图案131接触。接着，重复通过CVD形成层间绝缘膜和通过双镶嵌方法形成导电图案，由此形成层间绝缘膜122到125a和n个导电图案，如图5中所示。在竖直方向上彼此相邻的导电图案经由设置在位于其间的层间绝缘膜中的连接孔而彼此连接。
接着，通过使用光刻胶作为掩模对氧化硅膜125a进行干式蚀刻，由此在氧化硅膜125a中形成开口125d，导电图案134通过所述开口125d暴露，如图6中所示。在去除光刻胶之后，通过溅镀沉积由例如氮化钛制成的阻挡层以覆盖开口125d的内部和氧化硅膜125a的表面，且通过CVD或PVD进一步沉积钨，从而嵌入开口125d。随后，通过CMP或干式蚀刻去除形成于氧化硅膜125a的表面上的钨和阻挡层，从而形成钨插塞136。尽管图6中仅展示一个钨插塞136，但可形成两个或更多个钨插塞。
接着，如图7中所示，通过以钛、铝以及氮化钛的顺序溅镀将电极材料沉积在氧化硅膜125a的表面上，例如以与钨插塞136接触，且此后通过使用光刻胶作为掩模来执行干式蚀刻。因此，形成探针衬垫137。通常，钛和氮化钛的膜厚度为5到30nm，且铝的膜厚度为300到1500nm。例如Cl2或BCl3的氯气可用于此干式蚀刻。在此干式蚀刻中，执行过蚀刻以便完全去除除探针衬垫137以外的电极材料。因此，在氧化硅膜125a中在与探针衬垫137重叠的部分与不与探针衬垫137重叠的部分之间的边界处形成几十纳米的阶梯D1。接着，使测试仪的探针与探针衬垫137接触，且测试半导体器件100。
接着，如图8中所示，在不使用掩模的情况下对氧化硅膜125a的整个表面执行使用例如Cl2或BCl3的氯气的干式蚀刻，从而去除探针衬垫137。因此，暴露钨插塞136。在此蚀刻中，执行过蚀刻以便完全去除探针衬垫137。因此，通过对探针衬垫137的过蚀刻和后续清洁过程而略微蚀刻钨插塞136的表面，从而形成几十纳米的阶梯D2。因此，氧化硅膜125a包含包围钨插塞136的区域，且进一步包含包围包围钨插塞136的区域的另一区域。包围钨插塞136的区域具有大于其它区域的厚度。另外，氧化硅膜125a的包围钨插塞136的区域的厚度大于钨插塞136的厚度。接着，如图9中所示，通过CVD形成氮化硅膜125b以覆盖氧化硅膜125a的整个表面。氮化硅膜125b的厚度通常为5到50nm。
接着，如图10中所示，通过CVD沉积主要由氧化硅膜形成的绝缘膜125c以覆盖氮化硅膜125b的整个表面。绝缘膜125c的厚度通常为300到1000nm。由于沉积绝缘膜125c以遵循下伏阶梯D1和D2，因此小阶梯保持在其表面上。接着，如图11中所示，通过CMP去除绝缘膜125c的上部部分，从而获得平坦表面。因此，绝缘膜125c的上部表面在氧化硅膜125a的包围钨插塞136的区域与其它区域(包围包围钨插塞136的区域)之间的边界处为大体上平坦的。阶梯D1和/或阶梯D2不通过绝缘膜125c的上部表面反射。在阶梯D1和D2足够小的情况下，可省略此CMP。接着，如图12中所示，通过使用光刻胶作为掩模对层间绝缘膜125执行干式蚀刻，由此形成开口125e，导电图案133借由所述开口125e暴露。氟气可用于此干式蚀刻中。接着，如图13中所示，随后通过溅镀沉积钽和铜以覆盖层间绝缘膜125的表面和开口125e的内部。钽和铜的膜厚度通常分别为5到10nm和30到100nm。此外，通过电镀来沉积铜以完全填充开口125e。随后，通过CMP去除层间绝缘膜125的表面上的不必要的铜。因此，形成用于连接的衬垫电极135。尽管在图12和13中所示的过程中通过单镶嵌方法形成衬垫电极135，但可通过双镶嵌方法同时形成衬垫电极135的主体部分和将衬垫电极135的主体部分与导电图案133彼此连接的通孔导体部分。在使用双镶嵌方法的情况下，有可能在形成衬垫电极135的同时另外形成用于信号传输或供电的布线层。
在不形成TSV 140的情况下，通过以上过程完成半导体器件100的生产。在形成TSV140的情况下，随后执行以下过程。
首先，如图14中所示，硅衬底110倒置，且在主表面111侧上用粘着剂接合到由硅或玻璃制成的支撑衬底(未展示)。在此状态下，紧接在TSV 140的下部端142暴露之前从后表面112侧抛光硅衬底110。举例来说，在抛光结束时从后表面112到TSV 140的下部端142的距离为约2到10μm。此外，对硅衬底110的后表面112执行使用例如SF6气体的干式蚀刻，从而暴露TSV 140的下部端142。举例来说，TSV 140从硅衬底110的后表面112突出的长度为约2到10μm。TSV 140的下部端142由薄绝缘膜(未展示)覆盖，以便防止形成TSV 140的铜与硅衬底110之间的接触。接着，如图15中所示，通过CVD沉积氮化硅膜151以覆盖包含TSV 140的下部端142的硅衬底110的整个后表面112，且通过CVD进一步沉积氧化硅膜152。氮化硅膜151和氧化硅膜152的厚度分别为例如20到200nm和2到10μm。也就是说，氧化硅膜152的膜厚度与TSV 140的突出长度大致相同。
接着，如图16中所示，氧化硅膜152通过CMP平坦化。在此过程中，也抛光TSV140的下部端142，从而暴露形成TSV 140的铜。接着，如图17中所示，沉积主要由氧化硅膜形成的绝缘膜153以覆盖包含TSV 140的下部端142的整个氧化硅膜152。此外，通过使用光刻胶作为掩模对绝缘膜153执行干式蚀刻，由此在绝缘膜153中形成开口153a，TSV 140的下部端142借由所述开口153a暴露。接着，通过溅镀沉积钽和铜，进而覆盖绝缘膜153的表面和开口153a的内部。钽和铜的膜厚度通常分别为5到10nm和30到100nm。此外，通过电镀来沉积铜以完全填充开口153a。随后，通过CMP去除绝缘膜153的表面上的不必要的铜。因此，形成图1中所示的用于连接的衬垫电极160，且完成根据本实施例的半导体器件100。在通过镶嵌工艺形成衬垫电极160的过程中，可按需要同时在硅衬底110的后表面112上形成重布线层(RDL)。
堆叠半导体器件100A可通过堆叠以上文所描述的方式通过如图2中所示的混合接合产生的多个半导体器件100来配置。在图2中所示的堆叠半导体器件100A倒置实施的情况下，不必在最上部半导体器件100中提供TSV 140。
如上文所描述，根据本实施例的半导体器件100可具有混合接合所需的高平坦度，因为在使用探针衬垫137的操作测试之后去除探针衬垫137，且此后形成大体上彼此共面的衬垫电极135和层间绝缘膜125。此外，在形成衬垫电极135之后，有可能在无测试过程的情况下继续进行混合接合的过程。因此，减少用于连接的衬垫电极135暴露于大气的时间。因此，有可能使形成衬垫电极135的铜的腐蚀最小化。
接着，描述第二实施例。
如图18中所示，根据第二实施例的半导体器件200包含硅衬底210、堆叠在硅衬底210的主表面211上的多个层间绝缘膜220以及嵌入在层间绝缘膜220中的多个导电图案230。层间绝缘膜220包含按此顺序堆叠的层间绝缘膜221到225。层间绝缘膜的数目不特定地限于任何数目。层间绝缘膜225为最上部层间绝缘膜且配置半导体器件200的最外表面中的一个。导电图案230包含嵌入在层间绝缘膜222中的导电图案231和232、嵌入在层间绝缘膜224中的导电图案234以及嵌入在层间绝缘膜225中的衬垫电极233。导电图案230可由铜制成。层间绝缘膜220可主要含有氧化硅。衬垫电极233的表面从层间绝缘膜225的表面暴露。衬垫电极233的表面和层间绝缘膜225表面大体上彼此共面。
导电图案231连接到穿透硅衬底210的TSV 240的上部端241。TSV 240的下部端242连接到衬垫电极260。导电图案232连接到穿透硅衬底210的TSV 270的上部端271。TSV 270的下部端272连接到钨插塞261。硅衬底210的后表面212由绝缘膜251到255覆盖。绝缘膜251和254可由氮化硅制成，且绝缘膜252、253以及255可主要含有氧化硅。绝缘膜255配置半导体器件200的其它最外表面。衬垫电极260的表面和绝缘膜255的表面大体上彼此共面。同时，钨插塞261被嵌入而不从半导体器件200的其它最外表面暴露。钨插塞261的上部表面与TSV 270的下部端272完全接触，钨插塞261的侧表面由绝缘膜253完全覆盖，且钨插塞261的下部表面由绝缘膜254完全覆盖。
堆叠半导体器件200A可通过堆叠具有上文所描述的配置的多个半导体器件200来配置，如图19中所示。在堆叠半导体器件200的情况下，下部半导体器件200和上部半导体器件200以使得作为下部半导体器件200的最上部膜的绝缘膜225和作为上部半导体器件200的最下部膜的绝缘膜255面向彼此的方式堆叠，且执行混合接合。通过此接合，下部半导体器件200的衬垫电极233和上部半导体器件200的衬垫电极260彼此接合，且绝缘膜225和绝缘膜255彼此接合。
接着，描述制造半导体器件200的方法。
首先，如图20中所示，在硅衬底210的主表面211上形成元件隔离区、晶体管、电容器等(未展示)，此后形成将元件彼此连接的局部导线，且通过CVD形成覆盖其的层间绝缘膜221。此外，形成到达硅衬底210的内部的TSV 240和270。TSV 240和270由铜制成。TSV 240和270的表面分别由绝缘膜(未展示)覆盖，TSV 240和270借由绝缘膜与硅衬底210绝缘。接着，如图21中所示，形成层间绝缘膜222，且此后通过单镶嵌方法将包含导电图案231和232的多个导电图案嵌入在层间绝缘膜222中。导电图案231设置在与TSV 240重叠的位置处，从而TSV 240的上部端241与导电图案231接触。导电图案232设置在与TSV 270重叠的位置处，从而TSV 270的上部端271与导电图案232接触。接着，重复通过CVD形成层间绝缘膜和通过双镶嵌方法形成导电图案，由此形成层间绝缘膜222到225和n个导电图案，如图22中所示。在竖直方向上相邻的导电图案通过设置在位于其间的层间绝缘膜中的连接孔而彼此连接。
接着，如图23中所示，通过使用光刻胶作为掩模对层间绝缘膜225执行干式蚀刻以形成开口，导电图案234借由所述开口暴露，且此后通过单镶嵌方法形成用于连接的衬垫电极233。通过使用双镶嵌方法代替单镶嵌方法，可同时形成衬垫电极233的主体部分和将衬垫电极233的主体部分与导电图案234彼此连接的通孔导体部分。
接着，如图24中所示，硅衬底210倒置，且在主表面211侧上用粘着剂将硅衬底210接合到由硅或玻璃制成的支撑衬底(未展示)。在此状态下，紧接在TSV 240和270的下部端242和272暴露之前从后表面212侧抛光硅衬底210。举例来说，在抛光结束时从硅衬底210的后表面212到TSV 240和270的下部端242和272中的每一个的距离为约2到10μm。此外，通过使用例如SF6气体对硅衬底210的后表面212执行干式蚀刻，由此使得TSV 240和270的下部端242和272暴露。举例来说，TSV 240和270中的每一个从硅衬底210的后表面212突出的长度为约2到10μm。TSV 240和270的下部端242和272分别由薄绝缘膜(未展示)覆盖，以便防止形成TSV 240和270的铜与硅衬底210之间的接触。接着，如图25中所示，通过CVD沉积氮化硅膜251以覆盖包含TSV 240和270的下部端242和272的硅衬底210的整个后表面212，且通过CVD进一步沉积氧化硅膜252。氮化硅膜251和氧化硅膜252的厚度分别为例如20到200nm和2到10μm。也就是说，氧化硅膜252的厚度与TSV和270的突出长度大致相同。
接着，如图26中所示，氧化硅膜252通过CMP平坦化。在此抛光中，也抛光TSV 240和270的下部端242和272，从而暴露形成TSV 240和270的铜。接着，如图27中所示，提供主要由氧化硅膜形成的绝缘膜253以覆盖包含TSV 240和270的下部端242和272的整个氧化硅膜252，且使用光刻胶作为掩模进一步进行干式蚀刻。因此，到达TSV 270的开口261a形成于绝缘膜253中。在去除光刻胶之后，通过溅镀沉积由例如氮化钛制成的阻挡层以覆盖开口261a的内部和绝缘膜253的表面，且通过CVD或PVD进一步沉积钨，从而嵌入开口261a。随后，通过CMP或干式蚀刻去除绝缘膜253的表面上的钨和阻挡层，由此形成钨插塞261。尽管图27中仅展示一个钨插塞261，但可形成两个或更多个钨插塞。在形成钨插塞261的过程中，可视需要同时形成由钨制成的RDL。
接着，如图28中所示，通过在待与钨插塞261接触的绝缘膜253的表面上按例如钛、铝以及氮化钛的顺序溅镀来沉积电极材料，且此后执行使用光刻胶作为掩模的干式蚀刻。因此，形成探针衬垫235。通常，钛和氮化钛的膜厚度为5到30nm，且铝的膜厚度为300到1500nm。例如Cl2或BCl3的氯气可用于此干式蚀刻中。在此干式蚀刻中，执行过蚀刻以便完全去除除探针衬垫235以外的电极材料。因此，绝缘膜253在与探针衬垫235重叠的部分与不与探针衬垫235重叠的部分之间的边界处具有几十纳米的阶梯D3。接着，使测试仪的探针与探针衬垫253接触，且测试半导体器件200。如上文所描述，在本实施例中，通过从硅衬底210的后表面212侧探测来测试半导体器件200。
接着，如图29中所示，在不使用掩模的情况下对绝缘膜253的整个表面执行使用例如Cl2或BCl3的氯气的干式蚀刻，由此去除探针衬垫235。因此，暴露钨插塞261。在此蚀刻中，执行过蚀刻以便完全去除探针衬垫235。因此，通过对探针衬垫235的过蚀刻和后续清洁过程而略微蚀刻钨插塞261的表面，从而形成几十纳米的阶梯D4。因此，绝缘膜253包含包围钨插塞261的区域，且进一步包含包围包围钨插塞261的区域的另一区域。包围钨插塞261的区域具有大于其它区域的厚度。另外，氧化硅膜253的包围钨插塞261的区域的厚度大于钨插塞261的厚度。接着，如图30中所示，通过CVD形成氮化硅膜254以完全覆盖绝缘膜253的表面。氮化硅膜254的膜厚度通常为5到50nm。随后，通过CVD沉积主要由氧化硅膜形成的绝缘膜255以完全覆盖氮化硅膜254的表面。绝缘膜255的膜厚度通常为300到1000nm。由于沉积绝缘膜255以遵循下伏阶梯D3和D4，因此小阶梯保持在其表面上。接着，如图31中所示，通过CMP去除绝缘膜255的上部部分，从而获得平坦表面。因此，绝缘膜253的上部表面在氧化硅膜253的包围钨插塞261的区域与其它区域(包围包围钨插塞261的区域)之间的边界处为大体上平坦的。阶梯D3和/或阶梯D4不由绝缘膜253的上部表面反射。在阶梯D3和D4足够小的情况下，可省略此CMP。接着，如图32中所示，通过使用光刻胶作为掩模对绝缘膜255、氮化硅膜254以及绝缘膜253执行干式蚀刻，由此形成开口260a，TSV 240的下部端242借由所述开口260a暴露。氟气可用于此干式蚀刻中。
接着，通过溅镀沉积钽和铜，进而覆盖绝缘膜255的表面和开口260a的内部。钽和铜的膜厚度通常分别为5到10nm和30到100nm。此外，通过电镀来沉积铜以完全填充开口260a。随后，通过由CMP去除绝缘膜255的表面上的不必要铜形成图18中所示的用于连接的衬垫电极260，且因此完成根据本实施例的半导体器件200。双镶嵌方法可用于形成衬垫电极260。此外，在通过镶嵌工艺形成衬垫电极260的过程中，可按需要同时在硅衬底210的后表面212上形成RDL。
堆叠半导体器件200A可通过堆叠以上文所描述的方式通过如图19中所示的混合接合产生的多个半导体器件200来配置。如上文所描述，根据本实施例的半导体器件200可获得与根据第一实施例的半导体器件100的效果相同的有利效果。
上文所描述的半导体器件100和200中的每一个可应用于叠层芯片(CoC)、衬底上芯片(CoS)以及晶片上芯片(CoW)，其中一个芯片或两个芯片以个别芯片或多个芯片的形式堆叠，且还可应用于在单体化之前堆叠两个芯片的晶片上晶片(WoW)。在WoW中，由于无论每一芯片是否有缺陷都执行堆叠，因此可执行以下方法。也就是说，当堆叠n个晶片时，第一到第(n-1)个晶片以面向下的方法堆叠，其中省略探针衬垫235，且图28中所示的探针衬垫235仅形成于第n个晶片上。在使探针与探针衬垫235接触且执行操作测试之后，如图29中所示，去除探针衬垫235，且提供用于连接的衬垫电极260。此外，仅形成连接衬垫的CAP晶片堆叠在第n个晶片上。尽管在以上实例中硅衬底制作得较薄，且随后堆叠在WoW的堆叠中，但有可能在仅形成前表面侧衬垫的同时执行堆叠，且此后硅衬底制作得较薄，且提供背表面侧衬垫。
虽然已经在某些优选实施例和实例的上下文中公开了本发明，但是所属领域的技术人员应理解，本发明延伸超出专门公开的实施例到其它替代实施例和/或本发明及其显而易见的修改及等效物的使用。另外，基于本公开，在本发明的范围内的其它修改对于所属领域的技术人员来说将是显而易见的。还预期可进行实施例的特定特征和方面的各种组合或子组合并仍然处于本发明的范围内。应理解，所公开实施例的各种特征和方面可彼此组合或替换以便形成所公开的发明的变化模式。因此，希望本文所公开的本发明中的至少一些的范围不应受上文所描述的特定公开实施例的限制。

Claims (20)

1.一种装置，其包括：
半导体衬底；
多个层间绝缘膜，其位于所述半导体衬底上；以及
多个导电图案，其嵌入在所述层间绝缘膜中，
其中所述多个导电图案包含嵌入在所述多个层间绝缘膜中的最上一者中的第一导电图案和第二导电图案，
其中所述第一导电图案具有从所述多个层间绝缘膜中的所述最上一者暴露的上部表面，且
其中所述第二导电图案具有由所述多个层间绝缘膜中的所述最上一者覆盖而不暴露的上部表面。
2.根据权利要求1所述的装置，其中所述第一导电图案的所述上部表面与所述多个层间绝缘膜中的所述最上一者的上部表面大体上共面。
3.根据权利要求1所述的装置，
其中所述多个导电图案进一步包含嵌入在与所述多个层间绝缘膜中的所述最上一者相邻的所述多个层间绝缘膜中的另一者中的第三导电图案，且
其中所述第二导电图案的整个下部表面与所述第三导电图案的上部表面接触，使得所述第二导电图案不电连接到所述多个导电图案中除所述第三导电图案以外的任一个。
4.根据权利要求3所述的装置，其中所述第二导电图案由与所述第三导电图案不同的材料制成。
5.根据权利要求4所述的装置，其中所述第二导电图案由与所述第一导电图案不同的材料制成。
6.根据权利要求3所述的装置，其中所述第二导电图案的整个侧表面由所述多个层间绝缘膜中的所述最上一者覆盖。
7.根据权利要求1所述的装置，
其中所述多个层间绝缘膜中的所述最上一者包含第一绝缘膜和第二绝缘膜，且其中所述第二导电图案具有由所述第一绝缘膜覆盖的侧表面和由所述第二绝缘膜覆盖的上部表面。
8.根据权利要求7所述的装置，
其中所述第一绝缘膜具有包围所述第二导电图案的第一区域和包围所述第一区域的第二区域，且
其中所述第一区域在厚度上大于所述第二区域。
9.根据权利要求8所述的装置，其中所述第一区域在厚度上大于所述第二导电图案。
10.根据权利要求8所述的装置，
其中所述多个层间绝缘膜中的所述最上一者进一步包含所述第二绝缘膜上的第三绝缘膜，且
其中所述第三绝缘膜的上部表面在所述第一区域与所述第二区域之间的边界处为大体上平坦的。
11.根据权利要求1所述的装置，其进一步包括穿透所述半导体衬底的TSV，其中所述TSV与所述第一导电图案重叠。
12.一种装置，其包括：
半导体衬底，其具有前表面和后表面；
多个布线层，其形成于所述半导体衬底的所述前表面上；
第一TSV和第二TSV，其穿透所述半导体衬底；
绝缘膜，其覆盖所述半导体衬底的所述后表面；以及
第一导电图案和第二导电图案，其嵌入在所述绝缘膜中，
其中所述第一导电图案具有连接到所述第一TSV的上部表面和从所述绝缘膜暴露的下部表面，且
其中所述第二导电图案具有连接到所述第二TSV的上部表面和由所述绝缘膜覆盖而不暴露的下部表面。
13.根据权利要求12所述的装置，其中所述第一导电图案的所述下部表面与所述绝缘膜的下部表面大体上共面。
14.根据权利要求12所述的装置，
其中所述多个布线层包含位于所述多个布线层中的最上一者处的第三导电图案，其中暴露所述第三导电层的上部表面，且
其中所述第三导电图案与所述第一导电图案重叠。
15.根据权利要求12所述的装置，
其中所述绝缘膜包含覆盖所述第二导电图案的侧表面的第一绝缘膜和覆盖所述第二导电图案的所述下部表面的第二绝缘膜，
其中所述第一绝缘膜具有包围所述第二导电图案的第一区域和包围所述第一区域的第二区域，且
其中所述第一区域在厚度上大于所述第二区域。
16.根据权利要求15所述的装置，其中所述第一区域在厚度上大于所述第二导电图案。
17.一种方法，其包括：
形成待嵌入在形成于半导体衬底上的第一绝缘膜中的接触插塞；
在所述第一绝缘膜上形成探针衬垫以与所述接触插塞接触；
通过探测所述探针衬垫来执行测试操作；
去除所述探针衬垫；
在去除所述探针衬垫之后形成第二绝缘膜以覆盖所述接触插塞；以及
形成待嵌入在所述第二绝缘膜中的衬垫电极。
18.根据权利要求17所述的方法，其进一步包括在形成所述衬垫电极之后执行CMP，使得所述衬垫电极的经暴露表面与所述第二绝缘膜大体上彼此共面。
19.根据权利要求17所述的方法，其进一步包括在与所述衬垫电极重叠的位置处形成穿透所述半导体衬底的第一TSV。
20.根据权利要求19所述的方法，其进一步包括形成穿透所述半导体衬底且连接到所述接触插塞的第二TSV。
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