WO2021164583A1 - 背板及其制备方法、显示装置 - Google Patents

背板及其制备方法、显示装置 Download PDF

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Publication number
WO2021164583A1
WO2021164583A1 PCT/CN2021/075601 CN2021075601W WO2021164583A1 WO 2021164583 A1 WO2021164583 A1 WO 2021164583A1 CN 2021075601 W CN2021075601 W CN 2021075601W WO 2021164583 A1 WO2021164583 A1 WO 2021164583A1
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Prior art keywords
light
emitting diode
layer
reflective layer
sub
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PCT/CN2021/075601
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English (en)
French (fr)
Inventor
李沛
孙海威
翟明
禹璐
常康乐
李金鹏
曹鹏军
浩育涛
张树柏
王硕
秦沛
高泽文
张亚莉
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/626,154 priority Critical patent/US11960167B2/en
Publication of WO2021164583A1 publication Critical patent/WO2021164583A1/zh
Priority to US18/601,499 priority patent/US20240210754A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133605—Direct backlight including specially adapted reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133606—Direct backlight including a specially adapted diffusing, scattering or light controlling members
    • G02F1/133607—Direct backlight including a specially adapted diffusing, scattering or light controlling members the light controlling member including light directing or refracting elements, e.g. prisms or lenses
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133614—Illuminating devices using photoluminescence, e.g. phosphors illuminated by UV or blue light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
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    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0041—Processes relating to semiconductor body packages relating to wavelength conversion elements
    • H—ELECTRICITY
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    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/505—Wavelength conversion elements characterised by the shape, e.g. plate or foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a backplane, a preparation method thereof, and a display device.
  • Mini Light Emitting Diode (Mini LED) and Micro Light Emitting Diode (Micro LED) as self-luminous light-emitting devices can be used as passive displays such as Liquid Crystal Display (LCD)
  • LCD Liquid Crystal Display
  • the backlight of the device can be directly used as a pixel unit in the display panel for display. Since light-emitting diodes have characteristics such as stable performance, and liquid crystal display panels have the advantages of low cost and long service life, this makes the application of light-emitting diodes to liquid crystal display panels more diverse.
  • a backplane in one aspect, includes a substrate, a first reflective layer, a plurality of light-emitting diode chips, and a plurality of optical structures.
  • the substrate includes a circuit structure layer.
  • the first reflective layer is arranged on the bearing surface of the substrate; the first reflective layer includes a plurality of through holes arranged at intervals.
  • One light emitting diode chip of the multiple light emitting diode chips is located in one of the multiple through holes, and the multiple light emitting diode chips are electrically connected to the circuit structure layer; the circuit structure layer is configured to drive the multiple light emitting diode chips to emit light.
  • One of the multiple optical structures covers the light-emitting surface of one of the multiple light-emitting diode chips, and the light-incident surface of the optical structure is in contact with the light-emitting surface of the light-emitting diode chip, and the light-emitting surface of the optical structure includes a curved surface.
  • the light-emitting surface of the optical structure is a convex surface that protrudes toward the side of the light-emitting diode chip away from the substrate.
  • the through hole includes a first sub-through hole and a second sub-through hole that are sequentially away from the substrate.
  • the aperture of the first sub-through hole is smaller than the aperture of the second sub-through hole; and the optical structure is at least in contact with the hole wall of the first sub-through hole.
  • the orthographic projection of the wall of the first sub-via on the substrate is within the orthographic projection of the wall of the second sub-via on the substrate.
  • the optical structure is also in contact with the hole wall of the second sub-via.
  • the first reflective layer is an ink structure layer.
  • the first reflective layer is a white reflective sheet, and the white reflective sheet includes a plurality of micro air bubbles.
  • the side surface of the light emitting diode chip away from the carrying surface of the substrate has a first maximum distance from the carrying surface of the substrate.
  • a side surface of the first reflective layer away from the bearing surface of the substrate has a second maximum distance from the bearing surface of the substrate. Wherein, the first maximum distance is greater than or less than the second maximum distance; or, the first maximum distance is less than the second maximum distance.
  • the backplane further includes a second reflective layer.
  • the second reflective layer is located on the side of the circuit structure layer close to the first reflective layer; the second reflective layer includes a plurality of hollow areas, the circuit structure layer includes a plurality of pads, and one hollow area of the plurality of hollow areas exposes a plurality of hollow areas At least one of the bonding pads, one light-emitting diode chip is electrically connected to two bonding pads among the plurality of bonding pads.
  • the second reflective layer is located on the side of the circuit structure layer away from the first reflective layer;
  • the circuit structure layer has a plurality of metal wiring areas and a light-transmitting area between two adjacent metal wiring areas;
  • the circuit structure layer It includes a plurality of pads arranged in the metal wiring area, one light emitting diode chip is electrically connected to two of the plurality of pads; the light-transmitting area is configured to pass through the light emitted by the light emitting diode chip and be Part of the light reflected by the reflective layer.
  • the second reflective layer includes a first sub-transparent insulating layer, a metal reflective layer, and a second sub-transparent insulating layer that are sequentially stacked along the thickness direction of the substrate.
  • the backplane further includes an adhesive layer, the adhesive layer is located between the first reflective layer and the substrate, and the adhesive layer is configured to bond the first reflective layer to the substrate.
  • the backplane further includes a hydrophobic layer, and the hydrophobic layer is disposed on a side of the first reflective layer away from the substrate; the hydrophobic layer includes a plurality of opening regions, and one of the plurality of opening regions exposes a plurality of through holes. A through hole in the.
  • the materials constituting the optical structure include transparent colloidal materials and fumed silica materials.
  • the material constituting the optical structure includes a transparent colloidal material and a light conversion material mixed in the transparent colloidal material; the light conversion material is configured to convert the color of light emitted by the light emitting diode chip.
  • the backplane further includes a light conversion layer, and the light conversion layer is located on a surface of the optical structure away from the substrate.
  • a display device in another aspect, includes the backplane as in any of the above-mentioned embodiments.
  • the backplane is a display substrate; or, the backplane is a backlight module, and the display device further includes a liquid crystal display panel located on the light emitting side of the backlight module.
  • a method for preparing a backplane includes the following steps.
  • a substrate is provided; the substrate includes a circuit structure layer.
  • a first reflective layer and a plurality of light emitting diode chips are formed on the substrate; the first reflective layer includes a plurality of through holes arranged at intervals; one light emitting diode chip of the plurality of light emitting diode chips is located in one of the through holes , And the plurality of light emitting diode chips are electrically connected to the circuit structure layer; the circuit structure layer is configured to drive the plurality of light emitting diode chips to emit light.
  • multiple optical structures are formed through a dispensing process; one of the multiple optical structures covers the light-emitting surface of one of the multiple light-emitting diode chips, and the optical structure
  • the light-incident surface of the light-emitting diode chip is in contact with the light-emitting surface of the light-emitting diode chip, and the light-emitting surface of the optical structure includes a curved surface.
  • the circuit structure layer includes a plurality of pads; forming a first reflective layer and a plurality of light-emitting diode chips on the substrate includes: forming a first ink film on the carrying surface of the substrate, and forming a first ink film on the substrate. A plurality of through holes are formed thereon to form the first reflective layer. A plurality of light-emitting diodes are formed on the substrate on which the first reflective layer is formed, one light-emitting diode chip of the plurality of light-emitting diode chips is located in one of the plurality of through holes, and each light-emitting diode chip is in a plurality of bonding pads. The two pads are electrically connected.
  • forming the first reflective layer includes: forming a first sub-ink film on the bearing surface of the substrate, and forming a first sub-through hole on the first sub-ink film.
  • a second sub-ink film is formed on the first sub-ink film, and a second sub-through hole is formed on the second sub-ink film.
  • the first sub-through hole and the second sub-through hole are connected to form a through hole; A reflective layer.
  • the circuit structure layer includes a plurality of pads; forming the first reflective layer and the plurality of light-emitting diode chips on the substrate includes: combining one of the plurality of light-emitting diode chips with the plurality of pads The two pads are electrically connected.
  • a reflective sheet is provided, an adhesive layer is formed on the non-functional surface of the reflective sheet, and a first protective film is attached to the adhesive layer.
  • a plurality of through holes are formed on the reflective sheet adhered to the first protective film, and the through holes penetrate the reflective sheet, the adhesive layer and the first protective film. The first protective film is torn off, and the reflective sheet is attached to the carrying surface of the substrate through the adhesive layer, so that the plurality of light-emitting diode chips are located in the plurality of through holes in a one-to-one correspondence.
  • the manufacturing method of the backplane before forming the first reflective layer and the plurality of light-emitting diode chips, the manufacturing method of the backplane further includes: forming a second reflective layer on any side surface of the circuit structure layer.
  • the circuit structure layer includes a plurality of pads; forming the second reflective layer on any side surface of the circuit structure layer includes: forming a second ink film on the bearing surface of the substrate, and forming a second ink film on the second ink film A plurality of hollow areas are formed on the upper surface to expose the pads in the circuit structure layer to form a second reflective layer.
  • a first sub-transparent insulating layer is formed on the bearing surface of the substrate; a metal reflective layer is formed on the first sub-transparent insulating layer; a second sub-transparent insulating layer is formed on the metal reflective layer; the first sub-transparent insulating layer, metal The reflective layer and the second sub-transparent insulating layer constitute a second reflective layer.
  • forming multiple optical structures through a glue dispensing process includes: mixing a transparent colloid material and a light conversion material, and forming multiple optical structures through a glue dispensing process.
  • the light conversion material is configured to convert the color of light emitted by the light emitting diode chip.
  • FIG. 1A is a structural diagram of a liquid crystal display device according to some embodiments.
  • FIG. 1B is a structural diagram of an electroluminescence display device or a photoluminescence display device according to some embodiments
  • Figure 2A is a structural diagram of a backplane according to some embodiments.
  • 2B is a structural diagram of a white reflective sheet according to some embodiments.
  • 2C is a top view of the arrangement relationship between two optical structures and light-emitting diode chips according to some embodiments
  • 2D is a diagram of a connection relationship between a light emitting diode chip and a circuit structure layer according to some embodiments
  • Figure 3 is a structural diagram of a backplane according to the related art
  • 4A is a structural diagram of another backplane according to some embodiments.
  • 4B is a structural diagram of still another backplane according to some embodiments.
  • Fig. 4C is an enlarged structural view at A in Fig. 4B;
  • 4D is a structural diagram of yet another backplane according to some embodiments.
  • Fig. 4E is an enlarged structural diagram at B in Fig. 4D;
  • 5A to 5C are structural diagrams of yet another backplane according to some embodiments.
  • FIGS. 6A to 6D are structural diagrams of yet another backplane according to some embodiments.
  • Figure 7 is a structural diagram of yet another backplane according to some embodiments.
  • Figure 8 is a structural diagram of yet another backplane according to some embodiments.
  • Figure 9 is a structural diagram of yet another backplane according to some embodiments.
  • FIGS. 10A to 10C are structural diagrams of yet another backplane according to some embodiments.
  • FIG. 11 is a flowchart of a method for manufacturing a backlight according to some embodiments.
  • Figure 12A is a flow chart of another method for preparing a backplane according to some embodiments.
  • 12B-12C are diagrams of a manufacturing process of a backplane according to some embodiments.
  • FIG. 13A is a flowchart of yet another method for preparing a backplane according to some embodiments.
  • FIGS. 13B to 13C are diagrams of the preparation process of another backplane according to some embodiments.
  • FIG. 14A is a flowchart of yet another method for preparing a backplane according to some embodiments.
  • FIGS. 14B-14G are diagrams of the preparation process of still another backplane according to some embodiments.
  • FIG. 15 is a flowchart of yet another method for preparing a backplane according to some embodiments.
  • FIG. 16A is a flowchart of yet another method for preparing a backplane according to some embodiments.
  • FIG. 16B is a flowchart of yet another method for preparing a backplane according to some embodiments.
  • 16C to 16F are diagrams of the preparation process of yet another backplane according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • connection and its extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the display device 200 may be a liquid crystal display device (Liquid Crystal Display, LCD); the display device 200 may also be an electroluminescent display device Or photoluminescence display device.
  • the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device (Quantum Dot Light Emitting). Diode, QLED).
  • the photoluminescence display device may be a quantum dot photoluminescence display device.
  • the liquid crystal display device 201 may include a backlight module 21 and a liquid crystal display panel 22, etc., and the backlight module 21 may provide a light source for the liquid crystal display panel 22 .
  • the structure of the electroluminescence display device 202 may include a display substrate 23 (for example, an electroluminescence display substrate or a photoluminescence display substrate) and an encapsulation layer 24, etc.
  • some embodiments of the present disclosure provide a backplane 1, which includes a substrate 10, a first reflective layer 11, a plurality of light emitting diode (LED) chips 12, and a plurality of optical structures 13. It should be noted that the backplane 1 can be used as a backlight module or a display substrate in the above-mentioned display device.
  • a backplane 1 which includes a substrate 10, a first reflective layer 11, a plurality of light emitting diode (LED) chips 12, and a plurality of optical structures 13.
  • the backplane 1 can be used as a backlight module or a display substrate in the above-mentioned display device.
  • the substrate 10 includes a circuit structure layer 101.
  • the substrate 10 may further include a substrate 100 for carrying the circuit structure layer 101.
  • the substrate 100 may be a flexible material, such as polyimide; the substrate 100 may also be a rigid material, such as glass, silicon, or PCB (Printed Circuit Board, printed circuit board), etc. This disclosure is not concerned with this. Make a limit.
  • the first reflective layer 11 is disposed on the carrying surface of the substrate 10.
  • the bearing surface of the substrate 10 is the functional surface of the substrate 10 or can also be understood as the front surface of the substrate 10.
  • the surface of the circuit structure layer 101 away from the substrate 100 is a functional surface of the substrate 10.
  • the first reflective layer 11 includes a plurality of through holes 110 arranged at intervals.
  • the first reflective layer 11 is used to reflect light incident on its surface (for example, the partially totally reflected light 20 in the light 2 shown in FIG. 2A).
  • the through hole 110 is used for accommodating the light emitting diode chip, so the shape and size of the through hole 110 need to be selected according to the size and shape of the light emitting diode chip.
  • the top view of the through hole 110 may be a regular pattern such as a circle, a rectangle, a square, or the like, or the top view of the through hole 110 may also be an irregular pattern, which is not limited in the present disclosure.
  • the material of the first reflective layer 11 may be an organic or inorganic reflective material with photosensitive and thermal curing properties, and its reflectivity may be, for example, between about 70% and about 99%.
  • the reflectance can be 70%, 80%, 99%, or the like.
  • the first reflective layer 11 is an ink structure layer.
  • the material of the ink structure layer may be white ink.
  • the reflectance of the white ink to the light 2 is about 90%, which can improve the first reflection.
  • the layer 11 reflects the amount of light, so as to achieve a better light utilization effect.
  • the first reflective layer 11 can also be a white reflective sheet 11A, and the white reflective sheet 11A can be adhered to the bearing surface of the substrate 10, and the white reflective sheet 11A has a reflectance of the light 2 About 98%. In this way, most of the light passing through the first reflective layer 11 can be reflected to a greater extent, thereby increasing the amount of light emitted by the back plate 1 and further improving the display effect of the display device 200.
  • the white reflective sheet 11A includes a plurality of micro air bubbles 110A, and the diameter of each micro air bubble 110A is, for example, about 1 ⁇ m to about 5 ⁇ m.
  • the white reflective sheet 11A with micro air bubbles 110A is formed with through holes, because the micro air bubbles 110A have a small diameter, high density, and high reflectivity, it is incident from the hole wall of the through hole to the white reflection The light in the film can still exit from the white reflective film.
  • the thickness of the first reflective layer 11 is, for example, 50 ⁇ m, 100 ⁇ m, 150 ⁇ m, 180 ⁇ m, 300 ⁇ m, etc., which can be selected according to actual needs.
  • One light emitting diode chip 12 of the plurality of light emitting diode chips 12 is located in one of the through holes 110; and the plurality of light emitting diode chips 12 are electrically connected to the circuit structure layer 101, and the circuit structure layer 101 is configured as Electrical signals are provided to the plurality of light-emitting diode chips 12 to drive the plurality of light-emitting diode chips 12 to emit light.
  • the cross-sectional dimension (length, width, diagonal or diameter, etc.) of the LED chip 12 is between about 100 ⁇ m and about 300 ⁇ m; the thickness of the LED chip 12 is, for example, 100 ⁇ m.
  • the cross-sectional shape of the through hole 110 is, for example, an ellipse.
  • the long axis of the ellipse is parallel to the long side of the rectangle
  • the short axis of the ellipse is parallel to the short side of the rectangle
  • the intersection of the diagonals of the rectangle and the intersection between the long and short axes of the ellipse coincide.
  • the cross-sectional shape of the through hole 110 is, for example, a circle.
  • the intersection of the diagonals of the square coincides with the center of the circle.
  • the shape of the light-emitting diode chip 12 matches the cross-sectional shape of the through hole 110, so that on the one hand, the gap between the light-emitting diode chip 12 and the through hole 110 can be made smaller, and the reflection of light by the first reflective layer 11 can be improved.
  • the larger area of the through hole 110 due to the larger area of the through hole 110, more light is emitted from the through hole 110, and at the same time, the light emitting rate of the light emitting diode chip 12 can be improved.
  • the structure of the circuit structure layer 101 includes a plurality of pads 1012, and two electrodes of one light emitting diode chip 12 are electrically connected to two corresponding pads 1012.
  • the light-emitting diode chip 12 includes a light-emitting layer, an N electrode, and a P electrode; the light-emitting layer of the light-emitting diode chip 12 emits light in a 360° three-dimensional manner. If the N electrode and the P electrode are made of non-transparent metal, Therefore, no light will be emitted in the area where the N electrode and the P electrode are provided in the light emitting diode chip 12.
  • the N electrode and P electrode of the light-emitting diode chip 12 are bonded to the pad 1012 in the circuit structure layer 101 through conductive materials 4 such as solder or silver glue; the pad 1012 is for example connected to the circuit structure layer.
  • the thin film transistors in 101 are connected to electrical components such as capacitors, and are used to provide electrical signals to the light emitting diode chip 12.
  • FIG. 2D a rectangular frame is used to represent the light-emitting diode chip 12, and the rectangular frame does not constitute a reference to the shape and structure of the light-emitting diode chip. And other qualifications.
  • the light-emitting color of the light-emitting diode chip 12 may be any one of the three primary colors, or white. In some embodiments of the present disclosure, the light emitting diode chip 12 is a blue LED chip.
  • One of the multiple optical structures 13 covers the light-emitting surface of one of the multiple light-emitting diode chips 12, and the light-incident surface of the optical structure 13 is in contact with the light-emitting surface of the light-emitting diode chip 12.
  • the light-emitting surface 130 of the structure 13 includes a curved surface.
  • the material of the optical structure 13 at least includes a transparent colloid material, the transparent colloid material is, for example, an encapsulating glue, and the encapsulating glue is, for example, at least one of silica gel, epoxy glue, and acrylic glue.
  • the light-incident surface of the optical structure 13 is in contact with the light-emitting surface of the light-emitting diode chip 12, that is, there is no gap between the optical structure 13 and the light-emitting surface of the light-emitting diode chip 12; and those skilled in the art can understand that the optical structure 13 is made of encapsulant. It can be attached to the light-emitting diode chip 12 to wrap the light-emitting diode chip 12.
  • the optical structure 13 is prepared by a glue dispensing process.
  • the light-emitting surface of the optical structure 13 is a convex surface that protrudes toward the side of the light-emitting diode chip away from the substrate.
  • the optical structure 13 may be an optical lens, for example, a convex lens.
  • the optical structure 13 has a function of condensing light, which can improve the light-emitting efficiency of the light-emitting diode chip 12.
  • the refractive index of the optical structure 13 is in the range of about 1.3 to about 1.7.
  • the light exit surface 130 (the surface on the side away from the substrate 10) of each optical structure 13 is a curved surface with a certain curvature.
  • the totally reflected light 20 When the reflected light 20 propagates on the first reflective layer 11 in the optical structure 13, it will be reflected by the first reflective layer 11 and exit in a direction away from the substrate 10.
  • the curvature of the “curved surface with a certain curvature” is related to the incident angle of light emitted by the light emitting diode chip 12, that is, the setting of the curvature is related to the shape and size of the light emitting diode chip 12.
  • the light 2 is totally reflected when passing through the light-emitting surface 130, and it is sufficient to ensure that more light 2 is emitted normally.
  • the backplane 01 includes a substrate 10, a light emitting diode chip 12 electrically connected to a circuit structure layer 101 in the substrate 10, and a protective layer 3.
  • the material of the protective layer 3 can be, for example, an encapsulant, which covers the entire layer of the light-emitting diode chip 12, but because the light-emitting surface of the protective layer 3 (the surface away from the substrate 10) is a plane, part of the light-emitting diode chip 12
  • the incident angle of the emitted light 2 on the light-emitting surface of the protective layer 3 is relatively large, and the light 2 with a large incident angle of this part will be totally reflected.
  • the totally reflected light 2 is called the totally reflected light 20, which is shown in the figure.
  • the total reflection light 20 shown in 3 the total reflection light 20 will propagate in the direction toward the side of the substrate 10. This part of the total reflection light 20 cannot travel in the direction away from the substrate 10, and therefore cannot be used, resulting in
  • the light-emitting efficiency of the light-emitting diode chip 12 is low, the power consumption of the backplane 01 is relatively high, and the protective layer 3 entirely covers the light-emitting diode chip 12, and the amount of packaging glue is relatively large, resulting in high production cost of the backplane 01.
  • the first reflective layer 11 and the optical structure 13 are provided in the backplane 1.
  • the light-emitting surface 130 of the optical structure 13 has a curved surface, the light 2 is less likely to be totally reflected on this curved surface, the amount of the totally reflected light 20 is less, and the light 2 normally emitted is more, so the light-emitting diode chip 12 is improved.
  • Light extraction efficiency; on the other hand, the totally reflected light 20 and other light rays 2 propagating toward the substrate 10 will change their propagation direction after encountering the first reflective layer 11, and can again propagate to the side away from the substrate 10, thereby The light-emitting efficiency of the light-emitting diode chip 12 can be further improved.
  • the backplane 1 After the light-emitting efficiency of the light-emitting diode chip 12 is improved, the power consumption of the backplane 1 can be reduced; on the other hand, since the number of optical structures 13 is multiple, under the premise of the same thickness Compared with the protective layer 13 in the related art, the backplane 1 provided by some embodiments of the present disclosure can reduce the amount of packaging glue, thereby effectively reducing the production cost of the backplane 1.
  • optical The structure 13 covers the light-emitting diode chip 12, which can protect the light-emitting diode chip 12 and reduce the probability of the light-emitting diode chip 12 being damaged.
  • the through hole 110 includes a first sub-through hole 1101 and a second sub-through hole 1102 that are sequentially away from the substrate 10, and the first sub-through hole 1101 And the second sub-through hole 1102 communicate with each other; wherein the aperture of the first sub-through hole 1101 is smaller than the aperture of the second sub-through hole 1102, and the optical structure 13 is in contact with at least the hole wall of the first sub-through hole 1101.
  • the difference between the aperture d1 of the first through-hole 1101 and the aperture d2 of the second through-hole 1102 is within a value range of about 0.4 mm to about 1.0 mm.
  • the orthographic projection of the edge of the first sub-through hole 1101 on the substrate 10 is within the orthographic projection of the edge of the second sub-through hole 1102 on the substrate 10.
  • the first sub-through hole 1101 and the second sub-through hole 1102 may be coaxially arranged.
  • the longitudinal section of the through hole 110 may be similar to a "T" shape.
  • the optical structure 13 may only directly contact the wall of the first sub-via 1101, but not the wall of the second sub-via 1102.
  • the production of the optical structure 13 is restricted by the wall of the first sub-through hole 1101, which facilitates the molding of the optical structure 13, and at the same time prevents the optical structure 13 from being difficult to mold due to poor molding when using transparent glue with low viscosity.
  • the optical structure 13 can also form a certain adhesive effect with the wall of the first sub-through hole 1101 during molding, which is beneficial to the stability of the optical structure 13 after molding.
  • the optical structure 13 may directly contact the hole walls of the first sub-via 1101 and the second sub-via 1102 at the same time. In this way, the optical structure 13 and the first sub-through hole 1101 and the second sub-through hole 1102 both form a certain bonding effect, thereby improving the stability of the optical structure 13 after molding.
  • the process alignment accuracy requirement when the optical structure 13 is manufactured by the dispensing process can be reduced.
  • part of the light emitted by the light-emitting diode chip 12 and part of the total reflection light 20 may be directed from the gap to a side of the substrate 10 Side propagation, and the smaller the gap, the more light 2 that can be reflected by the first reflective layer 11, and the higher the light-emitting efficiency of the light-emitting diode chip 12 is.
  • the gap between the light-emitting diode chip 12 and the wall of the first sub-via 1101 can be reduced, thereby increasing The light-emitting efficiency of the light-emitting diode chip 12.
  • the bearing surface of the substrate 10 is the upper surface of the circuit structure layer 101.
  • a surface of the light emitting diode chip 12 away from the carrying surface of the substrate 10 has a first maximum distance L1 between it and the carrying surface of the substrate 10.
  • a surface of the first reflective layer 11 away from the bearing surface of the substrate 10 has a second maximum distance L2 from the bearing surface of the substrate 10.
  • the first maximum spacing L1 and the second maximum spacing L2 are not equal; in Figure 4C, the first maximum spacing L1 is greater than the second maximum spacing L2; in Figure 4E, the first maximum spacing L1 is less than The second maximum distance L2.
  • the first maximum distance L1 is greater than the second maximum distance L2, that is to say, the light emitting surface of the light emitting diode chip 12 is higher than the side of the first reflective layer 11 away from the substrate 10.
  • the LED chip 12 is relatively high, when the optical structure 13 is made, it is beneficial to increase the curvature of the light-emitting surface 130 of the optical structure 13, further reduce the amount of light 2 that is totally reflected, and improve the light-emitting diode The light output efficiency of the chip 12.
  • the first maximum distance L1 is smaller than the second maximum distance L2, that is to say, the light-emitting surface of the light-emitting diode chip 12 is lower than the first reflective layer 11 away from the substrate 10.
  • Side surface In this structure, because the light-emitting diode chip 12 is relatively low, when the optical structure 13 is made, the amount of transparent colloid material required for the optical structure 13 is less, which is beneficial to reduce production costs.
  • the first reflective layer 11 includes a first sub-reflective layer 111 and a second sub-reflective layer 112; the first sub-via 1101 is located in the first sub-reflective layer. On 111, the second sub-via 1102 is located on the second sub-reflective layer 112.
  • the first sub-through holes 1101 and the second sub-through holes 1102 can also be manufactured separately in stages, especially in the production of first sub-holes with different apertures.
  • the difficulty of making the through hole 110 can be reduced.
  • the first sub-reflective layer 111 and the second sub-reflective layer 112 are both ink structure layers, and the first sub-reflective layer 111 and the second sub-reflective layer 112 The materials are all white ink.
  • the first sub-reflective layer 111 and the second sub-reflective layer 112 can be produced in two steps. For example, the first layer of white ink (solid-liquid mixed state) is formed first, the first sub-via 1101 is formed through a patterning process after pre-curing, and then the The first layer of white ink is completely cured to complete the production of the first sub-reflective layer 111; then, a second layer of white ink is formed on the first sub-reflective layer 111. Among them, the second layer of white ink will be partially located in the first sub-via 1101. In the patterning process of forming the second sub-via 1102, the etching solution will not interact with the first sub-reflective layer 111 that has been completely cured.
  • reaction will only react with the second layer of white ink that has not been fully cured (including removing the uncured white ink located in the first sub-via 1101) to form a second sub-via 1102 to complete the second sub-via Fabrication of the reflective layer 112.
  • the light-emitting surface of the LED chip 12 is higher than the surface of the second sub-reflective layer 112 away from the substrate 10, and the optical structure 13 is in contact with the hole wall of the first sub-via 1101. In this way, the optical structure 13 can form a good convex lens structure, and at the same time, the stability of the optical structure 13 after molding can be ensured to a certain extent.
  • the light-emitting surface of the LED chip 12 is higher than the surface of the second sub-reflective layer 112 away from the substrate 10, and the optical structure 13 is connected to the first sub-through hole 1101 and the second sub-through hole 1101 and the second sub-reflective layer 112.
  • the walls of the through holes 1102 are all in contact.
  • the optical structure 13 may cover a part of the surface of the second sub-reflective layer 112 (that is, the surface of the second sub-reflective layer 112 away from the first sub-reflective layer 111). This can further improve the stability of the optical structure 13 after molding.
  • the light-emitting surface of the light-emitting diode chip 12 is higher than the first sub-reflective layer 111 and lower than the surface of the second sub-reflective layer 112 away from the substrate 10, that is, the surface of the light-emitting diode chip 12
  • the light-emitting surface is located between the surfaces on both sides of the second sub-reflective layer 112.
  • the optical structure 13 is in contact with the hole wall of the first sub-through hole 1101. In this way, the optical structure 13 can also be formed into a good convex lens structure, and the stability of the optical structure 13 after molding can be ensured to a certain extent. At the same time, the amount of materials used to form the optical structure can be reduced.
  • the substrate 10 further includes a second reflective layer 14.
  • the gap directly or indirectly exposes at least part of the surface of the second reflective layer 14 close to the first reflective layer 11.
  • the second reflective layer 14 is located on the side of the circuit structure layer 101 close to the first reflective layer 11.
  • the gap can directly expose the second reflective layer 14 close to the first reflective layer 11.
  • the second reflective layer 14 is located on the side of the circuit structure layer 101 away from the first reflective layer 11.
  • the gap can indirectly expose the second reflective layer 14 close to At least part of the surface of the first reflective layer 11, that is, in the example of FIG. 6C, the gap is grounded through the light-transmitting section of the circuit structure layer 14 to expose a part of the surface of the second reflective layer 14; and in the example of FIG. The gap is grounded through the light-transmitting section of the circuit structure layer 14 and the insulating layer 15 to expose a part of the surface of the second reflective layer 14.
  • the second reflective layer 14 includes a plurality of hollow areas.
  • the orthographic projection of each through hole 110 of the first reflective layer 11 on the substrate 10 covers the orthographic projection of at least one hollow area on the substrate 10.
  • each through hole 110 may expose one hollow area.
  • one hollow area exposes two pads of the circuit structure layer 101; in other examples, each through hole 110 may expose two pads.
  • the size of the gap D between the hole wall of the through hole 110 of the first reflective layer 11 and the light emitting diode chip 12 may be, for example, in a value range of about 1 um to about 5 um.
  • the gap between the hole wall of the through hole 110 of the first reflective layer 11 and the light emitting diode chip 12 can be filled with the material for making the optical structure 13, which can improve the light extraction efficiency and use stability of the light emitting diode chip 12.
  • the bearing surface of the substrate 10 is the upper surface of the second reflective layer 14 (the surface on the side away from the substrate 100).
  • the bearing surface of the substrate 10 is the upper surface of the circuit structure layer 101.
  • the material of the second reflective layer 14 may be metal or non-metal; the metal material is, for example, silver or aluminum, the non-metal is, for example, ink, and the ink is, for example, white ink.
  • the material of the second reflective layer 14 when the material of the second reflective layer 14 is a metal material, it can be formed by magnetron sputtering.
  • the second reflective layer 14 is located on the upper side of the circuit structure layer 101 in FIGS. 6A and 6B, and the second reflective layer 14 is located on the lower side of the circuit structure layer 101 in FIGS. 6C and 6D. Regardless of whether the second reflective layer 14 is located on the upper side or the lower side of the circuit structure layer 101, when the material of the second reflective layer 14 is conductive metal, in order to prevent the second reflective layer 14 from affecting the normal operation of the circuit structure layer 101, the second reflective layer The layer 14 needs to be insulated from the circuit structure layer 101.
  • the pattern of the second reflective layer 14 does not overlap with the orthographic projection of the conductive pattern (such as the metal trace area) in the circuit structure layer 101 on the substrate; or it is required between the second reflective layer 14 and the circuit structure layer 101
  • a transparent insulating layer is provided, and the material of the insulating layer may be an organic material or an inorganic material, such as at least one of silicon oxide and silicon nitride.
  • an insulating layer 15 is provided between the second reflective layer 14 and the circuit structure layer 101.
  • the second reflective layer 14 is located on the side of the circuit structure layer 101 close to the light-emitting diode chip 12. A hollow area is formed thereon to expose the pads in the circuit structure layer 101.
  • the second reflective layer 14 is located on the side of the circuit structure layer 101 away from the light emitting diode chip 12. When other light rays 2 propagating toward the substrate 10 are incident on the second reflective layer 14, they pass The reflection effect of the second reflective layer 14 will emit light again.
  • the second reflective layer 14 can further improve the light-emitting efficiency of the LED chip 12.
  • the light emitting diode chip 12 when the light emitting diode chip 12 emits light in a 360° three-dimensional manner, at least part of the light emitted from the light emitting diode chip 12 toward the surface of the second reflective layer 14 may be incident from the area between the light emitting diode chip 12 and the second reflective layer 14 After the second reflective layer 14 is reflected by the second reflective layer 14, it will emit light again, which helps to improve the light-emitting efficiency of the light-emitting diode chip 12.
  • the layer 14 provides the light-emitting efficiency of the light-emitting diode chip 12.
  • the circuit structure layer 101 is located on the upper side of the second reflective layer 14, there are light-transmitting areas and non-light-transmitting areas in the circuit structure layer 101, and the non-light-transmitting areas are located in the light-emitting diode chip 12.
  • the pad is located in the non-transmissive area, and the transparent area is between adjacent non-transmissive areas. Therefore, light 2 incident into the substrate 10 from the gap between the light emitting diode chip 12 and the wall of the through hole 110 and/or incident into the substrate 10 from the area between the light emitting diode chip 12 and the second reflective layer 14 The light 2 can still be reflected by the second reflective layer 14.
  • the second reflective layer 14 is located on the side of the circuit structure layer 101 close to the first reflective layer 11; the second reflective layer 14 includes a plurality of hollow areas, and One of the hollow areas exposes at least one of the plurality of pads in the circuit structure layer 101, and one light-emitting diode chip 12 is electrically connected to two of the plurality of pads.
  • the second reflective layer 14 When the second reflective layer 14 is located on the side of the circuit structure layer 101 close to the first reflective layer 11, on the one hand, it is convenient to fabricate the second reflective layer 14; on the other hand, between the second reflective layer 14 and the light-emitting surface 130 of the optical structure 13 The distance between the light beam 2 and the second reflective layer 14 is shorter, the loss is less, and the light output rate of the light emitting diode chip 12 can be further improved.
  • the second reflective layer 14 includes a first sub-transparent insulating layer 141, a metal reflective layer 142 and a second sub-transparent insulating layer 143 sequentially stacked along the thickness direction of the substrate 10.
  • the second reflective layer 14 is an insulating structure as a whole, regardless of whether it is located on the upper side or the lower side of the circuit structure layer 101, and because the two insulating layers are sandwiched between the two insulating layers with a higher reflectivity metal reflector. Layer 142, the light-emitting efficiency of the light-emitting diode chip 12 can be further improved.
  • the second reflective layer 14 is located on the side of the circuit structure layer 101 away from the first reflective layer 11; the circuit structure layer 101 has a plurality of metal wiring regions 1010, and is located The light-transmitting area 1011 between two adjacent metal wiring areas 1010.
  • the circuit structure layer 101 includes a plurality of pads arranged in the metal wiring area 1010, and one light-emitting diode chip 12 is electrically connected to two of the plurality of pads; the light-transmitting area 1011 is configured to pass through the light-emitting diode chip 12 Among the emitted light 2, part of the light 2 reflected by the second reflective layer 14, the metal wiring area 1010 is a non-transparent area.
  • the light 2 is incident on the second reflective layer 14 from the light-transmitting area 1011, and will be emitted again after being reflected by the second reflective layer 14.
  • the light-emitting efficiency of the light-emitting diode chip 12 is relatively high.
  • the backplane 1 further includes an adhesive layer 16.
  • the adhesive layer 16 is located between the first reflective layer 11 and the substrate 10, and the adhesive layer 16 is used to The reflective layer 11 is adhered to the substrate 10.
  • the material of the adhesive layer 16 may be acrylic glue, for example.
  • the reflective sheet may be adhered to the substrate 10 through the adhesive layer 16 to fix the first reflective layer 11 and the substrate 10.
  • the material constituting the optical structure 13 includes a transparent colloidal material and a fumed silica material.
  • the fumed silica material can increase the viscosity of the transparent colloidal material, which is beneficial to the shaping of the optical structure 13.
  • the material constituting the optical structure 13 includes a transparent colloidal material and a light conversion material mixed with the transparent colloidal material, and the light conversion material is configured to convert the color of the light 2 emitted by the light emitting diode chip 12.
  • the materials constituting the optical structure 13 include transparent colloidal materials, fumed silica materials, and light conversion materials.
  • the above-mentioned transparent colloid material is, for example, an encapsulant, and the light conversion material is, for example, a phosphor, a quantum dot material, a perovskite material, and the like.
  • the blue light when the light emitting diode chip 12 emits blue light, by arranging a light conversion material in the optical structure 13, the blue light can be converted into white light or red light or green light.
  • Adding a light conversion material to the material of the optical structure 13 can not only optimize the structure of the backplane 1 but also reduce the cost of the backplane 1.
  • the backplane 1 further includes a hydrophobic layer 110, the hydrophobic layer 110 is located on the side of the first reflective layer 11 away from the substrate 10, and the hydrophobic layer 110 includes a plurality of opening areas. One of the open areas exposes one of the through holes, and one optical structure 13 is located in one open area.
  • the material of the hydrophobic layer is a hydrophobic material, such as fluorinated polymers such as fluorinated polyethylene and fluorocarbon wax.
  • the hydrophobic layer can make the adjacent optical structures 13 difficult to adhere together, and thus facilitates the molding of the optical structures 13.
  • the backplane 1 when the light conversion material is not included in the material of the optical structure 13, the backplane 1 further includes a light conversion layer 17, and the light conversion layer 17 is located in the optical structure 13. The side away from the substrate 10.
  • the light conversion layer 17 can convert the light 2 emitted by the light-emitting diode chip 12 whose light-emitting color is at least one of the three primary colors into white light.
  • the light conversion layer 17 can convert blue light into white light.
  • the light conversion layer 17 converts the light color of the light-emitting diode chip 12, and the conversion efficiency and conversion effect are better.
  • the quality of the light 2 emitted by the back plate 1 can be improved, and the display effect of the display substrate with the back plate 1 can be ensured.
  • the backplane 1 can be used as a backlight module.
  • the back plate 1 may further include a lower diffusion film, an upper diffusion film and a prism film which are sequentially arranged on the light exit side of the back plate 1.
  • the light conversion layer 17 may be provided between the lower diffusion film and the upper diffusion film.
  • the light conversion layer 17 may be a quantum dot film.
  • the prism film and the upper diffusion film can make the light output of the back plate 1 as the backlight module more uniform and improve the light output effect.
  • the light-emitting diode chips 12 in the backplane 1 can be directly used as pixels for display, that is, the backplane 1 can be a display substrate, for example, as a display in a Mini LED display device and a Micro LED display device. part.
  • some embodiments of the present disclosure provide a method for preparing the back plate 1.
  • the preparation method of the back plate 1 includes:
  • a substrate 10 is provided; the substrate 10 includes a circuit structure layer 101.
  • a first reflective layer 11 and a plurality of light-emitting diode chips 12 are formed on the substrate 10; the first reflective layer 11 includes a plurality of through holes 110 arranged at intervals; one light-emitting diode chip 12 of the plurality of light-emitting diode chips 12 is located in the In one of the through holes 110, the plurality of light emitting diode chips 12 are electrically connected to the circuit structure layer 101; the circuit structure layer 101 is configured to drive the plurality of light emitting diode chips 12 to emit light.
  • a plurality of optical structures 13 are formed by a dispensing process; one optical structure 13 of the plurality of optical structures 13 covers one light-emitting diode of the plurality of light-emitting diode chips 12
  • the light-emitting surface of the chip 12 and the light-incident surface of the optical structure 13 are in contact with the light-emitting surface of the LED chip 12, and the light-emitting surface 130 of the optical structure 13 includes a curved surface.
  • the optical structure 13 includes, for example, a transparent colloidal material.
  • the material of the optical structure 13 may include a fumed silica material in addition to a transparent colloidal material.
  • the fumed silica material can increase the viscosity of the transparent colloidal material, which is beneficial to the shaping of the optical structure 13.
  • the preparation method of the back plate 1 has the same beneficial effects as the above-mentioned back plate 1, so it will not be repeated.
  • the circuit structure layer 101 includes a plurality of pads 1012.
  • the step of forming the first reflective layer 11 and the plurality of light-emitting diode chips 12 on the substrate 10 includes:
  • a first ink film is formed on the bearing surface of the substrate 10, and a plurality of through holes 110 are formed on the first ink film to form the first reflective layer 11.
  • the material of the first ink film is white ink, and the first ink film can be formed by screen printing or coating, for example.
  • the formation of the plurality of through holes 110 on the first ink film may be formed by a patterning process, for example.
  • one light-emitting diode chip 12 of the plurality of light-emitting diode chips 12 is electrically connected to two pads 1012 of the plurality of pads 1012 .
  • the light emitting diode chip 12 is a blue LED chip.
  • the optical structure 13 may include a light conversion material in addition to a transparent colloidal material.
  • the step of forming the first reflective layer 11 includes:
  • a first sub-ink film is formed on the bearing surface of the substrate 10, and a first sub-through hole 1101 is formed on the first sub-ink film.
  • a second sub-ink film is formed on the first sub-ink film, and a second sub-through hole 1102 is formed on the second sub-ink film, and the second sub-through hole 1102 is connected to the first sub-through hole.
  • the holes 1101 are in communication, and the first sub-through hole 1101 and the second sub-through hole 1102 constitute the through hole 110, thereby forming the first reflective layer 11.
  • the material and manufacturing process of the second sub-ink film are the same as those of the first sub-ink film, and the manufacturing process of the second sub-through hole 1102 is the same as the manufacturing process of the first sub-through hole 1101.
  • the diameter of the first sub-through hole 1101 is smaller than the diameter of the second sub-through hole 1102.
  • the second sub-through hole 1102 has a large diameter, which is beneficial to reduce the alignment accuracy of the dispensing process, and the double-layer ink structure is beneficial to the molding of the optical structure 13 and improves the reflectivity of the first reflective layer 11.
  • the circuit structure layer 101 includes a plurality of pads 1012.
  • the step of forming the first reflective layer 11 and the plurality of light-emitting diode chips 12 on the substrate 10 includes:
  • one light-emitting diode chip 12 of the plurality of light-emitting diode chips 12 is electrically connected to two of the plurality of bonding pads.
  • the circuit structure layer 101 includes a metal wiring area 1010 and a light-transmitting area 1011, and the pad may be located in the metal wiring area 1010.
  • a reflective sheet is provided, an adhesive layer 16 is formed on the non-functional surface of the reflective sheet, and a first protective film 18 is attached to the adhesive layer 16.
  • a coating or slit process can be used to uniformly fabricate the adhesive on the non-functional surface of the reflective sheet, thereby forming the adhesive layer 16.
  • the non-functional surface of the reflective sheet is located on the side of the substrate 100 that is close to the substrate 10, that is, the functional surface of the reflective sheet is located on the side of the substrate 100 that is away from the substrate 10.
  • the reflectivity of the functional surface of the reflective sheet is greater than the reflectivity of the non-functional surface of the reflective sheet, which can be used to distinguish the functional surface and the non-functional surface of the reflective sheet.
  • the thickness of the adhesive layer 16 may be in the range of about 10 ⁇ m to about 50 ⁇ m, and the peeling force between the adhesive layer 16 and the substrate 10 is, for example, greater than 50 gf.
  • the reflective sheet is used as the first reflective layer 11, and the reflectance of the functional surface of the reflective sheet to the light 2 can reach 98%, and the reflectivity is relatively high.
  • a plurality of through holes 110 are formed on the reflective sheet adhered to the first protective film 18, and the through holes 110 penetrate the reflective sheet, the adhesive layer 16 and the first protective film 18.
  • the formation of the through hole 110 may be formed by methods such as laser drilling, mechanical knife cutting, chemical etching, or the like. Among them, when a mechanical cutter is used to cut the through hole 110, the high reflection characteristic of the cut end surface can be well maintained.
  • the first protective film 18 is torn off, and the reflective sheet is attached to the carrying surface of the substrate 10 through the adhesive layer 16.
  • the plurality of light-emitting diode chips 12 are located in the plurality of through holes 110 in one-to-one correspondence. middle.
  • the alignment can be performed manually, for example. It is carried out with alignment or automatic optical inspection device (belonging to automatic fixture).
  • the attachment between the reflective sheet and the substrate 10 can be carried out by pressing a jig or a sealed high-pressure chamber.
  • the jig is, for example, a roller, and the closed high-pressure chamber can make the reflective sheet adhere to the substrate 10 through air pressure. superior.
  • the roller since the light-emitting surface of the light emitting diode chip 12 is higher than the upper surface of the reflective sheet (the surface away from the substrate 10), the roller is directly used The light-emitting diode chip 12 may be damaged.
  • a second protective film may be attached to the functional surface of the reflective sheet.
  • the second protective film may be release paper.
  • the structure after attaching the second protective film on the reflective sheet is shown in Fig. 14F.
  • the total thickness of the second protective film 19, the reflective layer 11 and the adhesive layer 16 is greater than or equal to the height of the light emitting diode chip 12.
  • the specific height difference should be considered The amount of compression generated during the pressing and attaching to ensure that the light-emitting diode chip 12 is not crushed.
  • the height difference between the total thickness of the second protective film 19, the reflective layer 11 and the adhesive layer 16 and the height of the light emitting diode chip 12 is as small as possible, thereby facilitating the emission of light around the light emitting diode chip.
  • the roller can be used to press to make the reflective sheet closely adhere to the substrate 10; after the pressing is completed, the second protective film 19 can be removed.
  • the roller can be directly used for pressing.
  • the second protective film 19 may not be attached.
  • the preparation method of the above-mentioned back plate 1 has the same beneficial effects as the above-mentioned back plate 1, so it will not be repeated.
  • the preparation method of the back plate 1 further includes:
  • the second reflective layer 14 is located on the side of the circuit structure layer 101 away from the substrate 100;
  • the second reflective layer 14 is located between the circuit structure layer 101 and the substrate 100.
  • the step of forming the second reflective layer 14 on any side surface of the circuit structure layer 101 includes:
  • a second ink film is formed on the bearing surface of the substrate 10, and a plurality of hollow areas are formed on the second ink film to expose the pads in the circuit structure layer 101 to form a second reflective layer 14.
  • the material of the second ink film may be the same as the material of the first ink film.
  • the step of forming the second reflective layer 14 on any side surface of the circuit structure layer 101 includes:
  • a first sub-transparent insulating layer 141 is formed on the carrying surface of the substrate 10.
  • the carrying surface of the substrate 10 is the upper surface of the circuit structure layer 101.
  • the material of the first sub-transparent insulating layer 141 is, for example, one of polyimide and plastic.
  • the pads need to be exposed.
  • a metal reflective layer 142 is formed on the first sub-transparent insulating layer 141.
  • the material of the metal reflective layer 142 is aluminum, for example.
  • a second sub-transparent insulating layer 143 is formed on the metal reflective layer; the first sub-transparent insulating layer 141, the metal reflective layer 142, and the second sub-transparent insulating layer 143 constitute the second reflective layer 14.
  • the material of the second sub-transparent insulating layer 143 is, for example, one of polyimide and plastic.
  • the second reflective layer 14 is fabricated on the bearing surface of the substrate 10, the fabrication process is relatively simple, and the total reflection light 20 and other rays 2 propagating toward the substrate 10 have a shorter path to the second reflective layer 14 and have less loss. .
  • forming a plurality of optical structures 13 through a glue dispensing process includes:
  • the transparent colloid material and the light conversion material are mixed, and a plurality of optical structures 13 are formed through a glue dispensing process; wherein the light conversion material is configured to convert the color of the light 2 emitted by the light emitting diode chip 12.
  • the light conversion material is, for example, a quantum dot material, and the quantum dot material has a relatively high light conversion efficiency.
  • the structure of the back plate 1 can be reduced, and the production cost can be reduced.
  • the dispensing process may be a needle-tube dispensing process, which can improve the accuracy of the dispensing process.
  • the light output efficiency of the light emitting diode chip 12 is equal to the light output of the backplane divided by the light output of all the light emitting diode chips.

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Abstract

一种背板，该背板包括基板、第一反射层、多个发光二极管芯片以及多个光学结构。基板包括电路结构层。第一反射层设置于基板的承载面；第一反射层包括间隔设置的多个通孔。多个发光二极管芯片中的一个发光二极管芯片位于多个通孔中的一个通孔内，且多个发光二极管芯片与电路结构层电连接；电路结构层被配置为驱动多个发光二极管芯片发光。多个光学结构中的一个光学结构覆盖多个发光二极管芯片中的一个发光二极管芯片的出光面，且光学结构的入光面与发光二极管芯片的出光面接触，光学结构的出光面包括曲面。

Description

背板及其制备方法、显示装置
本申请要求于2020年02月17日提交的、申请号为202010097212.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种背板及其制备方法、显示装置。
背景技术
迷你发光二极管(Mini Light Emitting Diode，Mini LED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)作为自发光型发光器件，既可以用作液晶显示装置(Liquid Crystal Display，LCD)等被动型显示装置的背光源，又可以直接作为显示面板中的像素单元进行显示。由于发光二极管具有性能稳定等特性，而液晶显示面板具有成本低廉、使用寿命较长等优点，这使得将发光二极管应用于液晶显示面板的场景愈加丰富。
发明内容
一方面，提供一种背板，该背板包括基板、第一反射层、多个发光二极管芯片以及多个光学结构。基板包括电路结构层。第一反射层设置于基板的承载面；第一反射层包括间隔设置的多个通孔。多个发光二极管芯片中的一个发光二极管芯片位于多个通孔中的一个通孔内，且多个发光二极管芯片与电路结构层电连接；电路结构层被配置为驱动多个发光二极管芯片发光。多个光学结构中的一个光学结构覆盖多个发光二极管芯片中的一个发光二极管芯片的出光面，且光学结构的入光面与发光二极管芯片的出光面接触，光学结构的出光面包括曲面。
在一些实施例中，光学结构的出光面为向发光二极管芯片远离基板的一侧凸起的凸面。
在一些实施例中，通孔包括依次远离基板的第一子通孔和第二子通孔。其中，第一子通孔的孔径小于第二子通孔的孔径；光学结构至少与第一子通孔的孔壁接触。
在一些实施例中，第一子通孔的孔壁在基板上的正投影位于第二子通孔的孔壁在基板上的正投影之内。
在一些实施例中，光学结构还与第二子通孔的孔壁接触。
在一些实施例中，所述第一反射层为油墨结构层。或者，所述第一反射层为白色反射片，所述白色反射片中包括多个微空气泡。
在一些实施例中，发光二极管芯片远离基板的承载面的一侧表面，与基 板的承载面之间具有第一最大间距。第一反射层远离基板的承载面的一侧表面，与基板的承载面之间具有第二最大间距。其中，第一最大间距大于或者小于第二最大间距；或者，第一最大间距小于第二最大间距。
在一些实施例中，背板还包括第二反射层。其中，第二反射层位于电路结构层靠近第一反射层的一侧；第二反射层包括多个镂空区，电路结构层包括多个焊盘，多个镂空区中的一个镂空区露出多个焊盘中的至少一个焊盘，一个发光二极管芯片与多个焊盘中的两个焊盘电连接。或者，第二反射层位于电路结构层远离第一反射层的一侧；电路结构层具有多个金属走线区，以及位于相邻两个金属走线区之间的透光区；电路结构层包括设置于金属走线区的多个焊盘，一个发光二极管芯片与多个焊盘中的两个焊盘电连接；透光区被配置为透过发光二极管芯片所发出的光线中被第二反射层反射的部分光线。
在一些实施例中，通孔的孔壁与发光二极管芯片之间具有间隙；间隙直接或者间接露出第二反射层靠近第一反射层的至少部分表面。
在一些实施例中，第二反射层包括沿基板厚度方向依次层叠的第一子透明绝缘层、金属反射层和第二子透明绝缘层。
在一些实施例中，背板还包括粘接层，粘接层位于第一反射层与基板之间，粘接层被配置为将第一反射层粘接在基板上。
在一些实施例中，背板还包括疏水层，疏水层设置于第一反射层远离基板的一侧；疏水层包括多个开口区，多个开口区中的一个开口区暴露出多个通孔中的一个通孔。
在一些实施例中，构成光学结构的材料包括透明胶体材料以及气相二氧化硅材料。
在一些实施例中，构成光学结构的材料包括透明胶体材料以及混合于透明胶体材料中的光转换材料；光转换材料被配置为转换发光二极管芯片发出的光线的颜色。和/或，背板还包括光转换层，光转换层位于光学结构远离基板的一侧表面。
另一方面，提供一种显示装置。显示装置包括如上述任一实施例的背板。其中，背板为显示基板；或者，背板为背光模组，显示装置还包括位于背光模组出光侧的液晶显示面板。
再一方面，提供一种背板的制备方法。该制备方法包括以下步骤。提供基板；基板包括电路结构层。在基板上形成第一反射层和多个发光二极管芯片；第一反射层包括间隔设置的多个通孔；多个发光二极管芯片中的一个发 光二极管芯片位于多个通孔中的一个通孔内，且多个发光二极管芯片与电路结构层电连接；电路结构层被配置为驱动多个发光二极管芯片发光。在多个发光二极管芯片远离基板的一侧，通过点胶工艺形成多个光学结构；多个光学结构中的一个光学结构覆盖多个发光二极管芯片中的一个发光二极管芯片的出光面，且光学结构的入光面与发光二极管芯片的出光面接触，光学结构的出光面包括曲面。
在一些实施例中，电路结构层包括多个焊盘；在基板上形成第一反射层和多个发光二极管芯片，包括：在基板的承载面上形成第一油墨薄膜，并在第一油墨薄膜上形成多个通孔，以形成第一反射层。在形成有第一反射层的基板上形成多个发光二极管，多个发光二极管芯片中的一个发光二极管芯片位于多个通孔中的一个通孔内，每个发光二极管芯片与多个焊盘中的两个焊盘电连接。
在一些实施例中，形成第一反射层包括：在基板的承载面形成第一子油墨薄膜，并在第一子油墨薄膜上形成第一子通孔。在第一子油墨薄膜上形成第二子油墨薄膜，并在第二子油墨薄膜上形成第二子通孔，第一子通孔和第二子通孔相连通以构成通孔；从而形成第一反射层。
在一些实施例中，电路结构层包括多个焊盘；在基板上形成第一反射层和多个发光二极管芯片，包括：将多个发光二极管芯片中的一个发光二极管芯片与多个焊盘中的两个焊盘电连接。提供反射片，在反射片的非功能面形成粘接层，并在粘接层上贴附第一保护膜。在与第一保护膜粘接的反射片上形成多个通孔，通孔贯穿反射片、粘接层和第一保护膜。撕除第一保护膜，通过粘接层将反射片贴附在基板的承载面上，使多个发光二极管芯片一一对应的位于多个通孔中。
在一些实施例中，在形成第一反射层和多个发光二极管芯片之前，背板的制备方法还包括：在电路结构层的任意一侧表面形成第二反射层。
在一些实施例中，电路结构层包括多个焊盘；在电路结构层的任意一侧表面形成第二反射层，包括：在基板的承载面上形成第二油墨薄膜，并在第二油墨薄膜上形成多个镂空区，露出电路结构层中的焊盘，以形成第二反射层。或者，在基板的承载面上形成第一子透明绝缘层；在第一子透明绝缘层上形成金属反射层；在金属反射层上形成第二子透明绝缘层；第一子透明绝缘层、金属反射层和第二子透明绝缘层构成第二反射层。
在一些实施例中，通过点胶工艺形成多个光学结构，包括：将透明胶体材料和光转换材料混合，通过点胶工艺形成多个光学结构。其中，光转换材 料被配置为转换发光二极管芯片发出的光线的颜色。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据一些实施例的一种液晶显示装置的结构图；
图1B为根据一些实施例的一种电致发光显示装置或光致发光显示装置的结构图；
图2A为根据一些实施例的一种背板的结构图；
图2B为根据一些实施例的一种白色反射片的结构图；
图2C为根据一些实施例的两种光学结构与发光二极管芯片布置关系的俯视图；
图2D为根据一些实施例的一种发光二极管芯片与电路结构层的连接关系图；
图3为根据相关技术的一种背板的结构图；
图4A为根据一些实施例的另一种背板的结构图；
图4B为根据一些实施例的再一种背板的结构图；
图4C为图4B中A处的放大结构图；
图4D为根据一些实施例的又一种背板的结构图；
图4E为图4D中B处的放大结构图；
图5A～图5C为根据一些实施例的又一种背板的结构图；
图6A～图6D为根据一些实施例的又一种背板的结构图；
图7为根据一些实施例的又一种背板的结构图；
图8为根据一些实施例的又一种背板的结构图；
图9为根据一些实施例的又一种背板的结构图；
图10A～图10C为根据一些实施例的又一种背板的结构图；
图11为根据一些实施例的一种背光的制备方法流程图；
图12A为根据一些实施例的另一种背板的制备方法流程图；
图12B～12C为根据一些实施例的一种背板的制备过程图；
图13A为根据一些实施例的再一种背板的制备方法流程图；
图13B～图13C为根据一些实施例的另一种背板的制备过程图；
图14A为根据一些实施例的又一种背板的制备方法流程图；
图14B～图14G为根据一些实施例的再一种背板的制备过程图；
图15为根据一些实施例的又一种背板的制备方法流程图；
图16A为根据一些实施例的又一种背板的制备方法流程图；
图16B为根据一些实施例的又一种背板的制备方法流程图；
图16C～图16F为根据一些实施例的又一种背板的制备过程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“大约”或“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
参见图1A和图1B，本公开的一些实施例提供了一种显示装置200，该显示装置200可以为液晶显示装置(Liquid Crystal Display，LCD)；该显示装置200也可以为电致发光显示装置或光致发光显示装置。在该显示装置200为电致发光显示装置的情况下，电致发光显示装置可以为有机电致发光显示装置(Organic Light-Emitting Diode，OLED)或量子点电致发光显示装置(Quantum Dot Light Emitting Diode，QLED)。在该显示装置200为光致发光显示装置的情况下，光致发光显示装置可以为量子点光致发光显示装置。
在该显示装置200为液晶显示装置201的情况下，如图1A所示，该液晶显示装置201可以包括背光模组21和液晶显示面板22等，背光模组21可以为液晶显示面板22提供光源。
在该显示装置200为电致发光显示装置202(或光致发光显示装置)的情况下，如图1B所示，电致发光显示装置202(或光致发光显示装置)的结构可以包括显示基板23(例如电致发光显示基板或光致发光显示基板)以及封装层24等。
如图2A所示，本公开一些实施例提供一种背板1，该背板1包括基板10、第一反射层11、多个发光二极管(Light Emitting Diode，LED)芯片12和多个光学结构13。需要说明的是，该背板1可以作为上述显示装置中的背光模组或显示基板。
基板10包括电路结构层101。基板10还可以包括用于承载电路结构层101的衬底100。该衬底100可以为柔性材料，例如为聚酰亚胺；该衬底100 也可以为刚性材料，例如为玻璃、硅或者PCB(Printed Circuit Board，印制电路板)等，本公开对此不做限定。
第一反射层11设置于基板10的承载面。基板10的承载面为基板10的功能面，或者也可以理解为基板10的正面。在一些示例中，电路结构层101远离衬底100的表面为基板10的功能面。第一反射层11包括间隔设置的多个通孔110。第一反射层11用于对入射至其表面的光线(例如图2A中示出的光线2中的部分全反射光线20)进行反射。通孔110用于容置发光二极管芯片，因此通孔110的形状和大小需要根据发光二极管芯片的大小和形状进行选择。
在本公开的一些实施例中，通孔110的俯视图例如为圆形、矩形、正方形等规则图形，或者通孔110的俯视图也可以为不规则图形，本公开对此不做限定。
在本公开的一些实施例中，第一反射层11的材料可以为具有感光和热固化特性的有机或无机反射材料，其反射率例如可以在大约70％～大约99％之间。示例性的，该反射率可以为70％、80％、或99％等。
在本公开的一些实施例中，第一反射层11为油墨结构层，该油墨结构层的材料可以为白色油墨，白色油墨对光线2的反射率为大约90％左右，这样可以提高第一反射层11对光线的反射量，从而达到较好的光线利用效果。
或者，如图2B所示，第一反射层11还可以为白色反射片11A，且该白色反射片11A可以粘接在基板10的承载面上，而白色反射片11A对光线2的反射率为大约98％左右。这样可以较大程度地将经过第一反射层11的大部分光线进行反射用，从而提高背板1的出光量，进而提高显示装置200的显示效果。
在本公开的一些实施例中，继续参照图2B，白色反射片11A中包括多个微空气泡110A，每个微空气泡110A的直径例如为大约1μm～大约5μm。
这样设置，带有微空气泡110A的白色反射片11A在形成通孔后，由于微空气泡110A的直径小且密度高，其反射率也较高，因此从通孔的孔壁入射至白色反射片中的光线仍然可以从白色反射片出射。
在本公开的一些实施例中，第一反射层11的厚度例如为50μm、100μm、150μm、180μm、300μm等，可根据实际需要进行选择。
多个发光二极管芯片12中的一个发光二极管芯片12位于多个通孔110中的一个通孔110内；且多个发光二极管芯片12均与电路结构层101电连接，电路结构层101被配置为向多个发光二极管芯片12提供电信号，驱动多个发 光二极管芯片12发光。
在本公开的一些实施例中，发光二极管芯片12的截面尺寸(长、宽或者对角线或者直径等参数)在大约100μm～大约300μm之间；发光二极管芯片12的厚度例如为100μm。
在本公开的一些实施例中，如图2C所示，当发光二极管芯片12的俯视图为长方形时，通孔110的截面形状例如为椭圆形。示例性的，椭圆形的长轴与长方形的长边相平行，椭圆形的短轴与长方形的短边相平行，长方形的对角线的交点与椭圆形的长轴和短轴之间的交点重合。当发光二极管芯片12的俯视图为正方形时，通孔110的截面形状例如为圆形。示例性的，正方形的对角线的交点与圆形的圆心重合。
在上述情况下，发光二极管芯片12的形状与通孔110的截面形状搭配，这样一方面可以使得发光二极管芯片12与通孔110之间的间隙较小，提高第一反射层11对光线的反射量；另一方面，由于通孔110的面积较大，从通孔110中出射的光线较多，同时可以提高发光二极管芯片12的出光率。
在本公开的一些实施例中，如图2D所示，电路结构层101结构包括多个焊盘1012，一个发光二极管芯片12的两个电极与相对应的两个焊盘1012电连接。
示例性的，如图2D所示，发光二极管芯片12包括发光层和N电极、P电极；发光二极管芯片12的发光层为360°立体出光，如果N电极、P电极采用非透光金属制作，则在发光二极管芯片12设置N电极、P电极的区域不会有光线出射。在本公开的一些实施例中，发光二极管芯片12的N电极、P电极通过焊锡、银胶等导电材料4与电路结构层101中的焊盘1012进行键合；焊盘1012例如与电路结构层101中的薄膜晶体管和电容等电学元件相连接，并用于向发光二极管芯片12提供电信号。
本领域技术人员可以理解的是，为了便于示意，在本公开的除图2D以外的其他附图中，均使用矩形框代表发光二极管芯片12，而该矩形框不构成对发光二极管芯片形状、结构等限定。
发光二极管芯片12的发光颜色例如可以为三基色中的任一种，也可以为白色。在本公开的一些实施例中，发光二极管芯片12为蓝光LED芯片。
多个光学结构13中的一个光学结构13覆盖多个发光二极管芯片12中的一个发光二极管芯片12的出光面，且光学结构13的入光面与发光二极管芯片12的出光面接触，多个光学结构13的出光面130包括曲面。
光学结构13的材料至少包括透明胶体材料，透明胶体材料例如为封装胶， 该封装胶例如为硅胶、环氧类胶、丙烯酸类胶中的至少一种。光学结构13的入光面与发光二极管芯片12的出光面接触，即光学结构13与发光二极管芯片12的出光面之间无间隙；而本领域技术人员可以理解到材质为封装胶的光学结构13可以附着在发光二极管芯片12上，包裹住发光二极管芯片12。在本公开的一些实施例中，光学结构13通过点胶工艺制备。
在本公开的一些实施例中，光学结构13的出光面为向发光二极管芯片远离基板的一侧凸起的凸面。示例性的，光学结构13可以为光学透镜，该光学透镜例如为凸透镜，此时，光学结构13具有会聚光线作用，可以提高发光二极管芯片12的出光效率。
在本公开的一些实施例中，光学结构13的折射率在大约1.3～大约1.7的取值范围内。
如图2A所示，每个光学结构13的出光面130(远离基板10一侧的表面)均为具有一定曲率的曲面，当从发光二极管芯片12中出射的光线2入射至光学结构13的出光面130时，由于入射角度较小，大部分光线2将正常出射，部分光线2在光学结构13的出光面130上发生全反射，将发生全反射的光线2称为全反射光线20，该全反射光线20在光学结构13中传播至第一反射层11上时，将会被第一反射层11反射，沿远离基板10的一侧方向出射。
需要说明的是，上述“具有一定曲率的曲面”的曲率与发光二极管芯片12发出光线的入射角度相关，即曲率的设置与发光二极管芯片12的形状和尺寸大小相关，只要能够使相对较少的光线2在经过出光面130时发生全反射，保证较多的光线2正常出射即可。
如图3所示，在相关技术中，背板01包括基板10、与基板10中电路结构层101电连接的发光二极管芯片12以及保护层3。该保护层3的材料例如可以为封装胶，其整层覆盖在发光二极管芯片12上，但由于保护层3的出光面(远离基板10的一侧表面)为平面，从而导致部分从发光二极管芯片12出射的光线2在保护层3的出光面处的入射角较大，该部分入射角较大的光线2将发生全反射，将发生全反射的光线2称为全反射光线20，即在图3中所示的全反射光线20，全反射光线20将向朝向基板10一侧的方向传播，该部分全反射光线20由于无法沿远离基板10的一侧方向传播，从而无法被利用，进而导致发光二极管芯片12的出光效率较低，背板01的功耗较高，且保护层3整层覆盖发光二极管芯片12，封装胶的用量较大，导致背板01的生产成本较高。
而在本公开的一些实施例中，背板1中设置了第一反射层11和光学结构 13。一方面，由于光学结构13的出光面130具有曲面，光线2在该曲面上不易发生全反射，全反射光线20的量较少，正常出射的光线2较多，因此提高了发光二极管芯片12的出光效率；另一方面，全反射光线20和其它向朝向基板10一侧传播的光线2在遇到第一反射层11后传播方向会改变，能够再次向远离基板10的一侧方向传播，从而可以进一步提高发光二极管芯片12的出光效率，发光二极管芯片12的出光效率提高后，可以降低背板1的功耗；再一方面，由于光学结构13的数量为多个，在厚度相同的前提下，本公开的一些实施例提供的背板1相对于相关技术中的保护层13整层覆盖的结构，可以降低封装胶的用量，从而可以有效降低背板1的生产成本；又一方面，光学结构13覆盖发光二极管芯片12，可以保护发光二极管芯片12，降低发光二极管芯片12被损坏的概率。
在本公开的一些实施例中，如图4A、图4B和图4D所示，通孔110包括依次远离基板10的第一子通孔1101和第二子通孔1102，第一子通孔1101和第二子通孔1102彼此相连通；其中，第一子通孔1101的孔径小于第二子通孔1102的孔径，且光学结构13至少与第一子通孔1101的孔壁接触。
示例性的，如图4A所示，第一子通孔1101的孔径d1与第二子通孔1102的孔径d2之差在大约0.4mm～大约1.0mm的取值范围内。
参照图4A～图4E，示例性的，第一子通孔1101的边缘在基板10上的正投影位于第二子通孔1102的边缘在基板10上的正投影之内。其中，第一子通孔1101与第二子通孔1102可以同轴设置。
示例性的，如图4A～图4E所示，通孔110纵截面可以类似“T”字型。
在一些实施例中，如图4A和图4D所示，光学结构13可以只与第一子通孔1101的孔壁直接接触，而不与第二子通孔1102的孔壁接触。这样，一方面通过第一子通孔1101的孔壁对光学结构13的制作进行限制，便于光学结构13的成型，同时避免光学结构13在使用粘度较低的透明胶水时由于成型较差而难以形成良好的凸透镜结构。另一方面，光学结构13在成型时还能与第一子通孔1101孔壁形成一定的粘接作用，从而有利于光学结构13成型后的稳定性。
在另一些实施例中，如图4B所示，光学结构13可以同时与第一子通孔1101和第二子通孔1102的孔壁直接接触。这样使得光学结构13与第一子通孔1101和第二子通孔1102均形成一定的粘接作用，从而提高光学结构13成型后的稳定性。
本公开一些实施例提供的背板1，一方面，由于第二子通孔1102的孔径 大于第一子通孔1101的孔径，可以降低通过点胶工艺制作光学结构13时的工艺对位精度要求；另一方面，由于发光二极管芯片12与第一子通孔1101的孔壁之间具有间隙，发光二极管芯片12发出的部分光线和部分全反射光线20均可能从该间隙向朝向基板10的一侧传播，而该间隙越小，能够被第一反射层11反射的光线2越多，发光二极管芯片12的出光效率越高。因此，在设置时，通过使第一子通孔1101的孔径小于第二子通孔1102的孔径，可以减小发光二极管芯片12与第一子通孔1101的孔壁之间的间隙，从而提高发光二极管芯片12的出光效率。
如图4C和图4E所示，在该种结构下，基板10的承载面为电路结构层101的上表面。发光二极管芯片12远离基板10的承载面的一侧表面，与基板10的承载面之间具有第一最大间距L1。
第一反射层11远离基板10的承载面的一侧表面，与基板10的承载面之间具有第二最大间距L2。
在图4C和图4E中，第一最大间距L1和第二最大间距L2不相等；在图4C中，第一最大间距L1大于第二最大间距L2；在图4E中，第一最大间距L1小于第二最大间距L2。
在本公开的一些实施例中，如图4C所示，第一最大间距L1大于第二最大间距L2，也就是说发光二极管芯片12的出光面高于第一反射层11远离基板10的一侧表面；在该种结构下，由于发光二极管芯片12较高，在制作光学结构13时，有利于增大光学结构13出光面130的曲率，进一步降低发生全反射的光线2的数量，提高发光二极管芯片12的出光效率。
在本公开的另一些实施例中，如图4E所示，第一最大间距L1小于第二最大间距L2，也就是说发光二极管芯片12的出光面低于第一反射层11远离基板10的一侧表面；在该种结构下，由于发光二极管芯片12较低，在制作光学结构13时，光学结构13所需使用的透明胶体材料量较少，这样有利于降低生产成本。
在本公开的一些实施例中，如图5A～图5C所示，第一反射层11包括第一子反射层111和第二子反射层112；第一子通孔1101位于第一子反射层111上，第二子通孔1102位于第二子反射层112上。
由于第一子反射层111和第二子反射层112分次分别制作，因此第一子通孔1101和第二子通孔1102也可以分次分别制作的，尤其在制作孔径不同的第一子通孔1101和第二子通孔1102时，分次分别制作可以降低制作通孔110的制作难度。
在第一子通孔1101的直径小于第二子通孔1102的直径时，即第二子通孔1102相对于第一子通孔1101外扩，还可以避免因第二子反射层112位置偏差出现遮盖第二子通孔1102内暴露出的焊盘的问题。
在本公开的一些实施例中，继续参照图5A～图5C，第一子反射层111和第二子反射层112均为油墨结构层，而第一子反射层111和第二子反射层112的材质均为白色油墨。
第一子反射层111和第二子反射层112可以分两次制作，例如先形成第一层白色油墨(固液混合态)，预固化后通过构图工艺形成第一子通孔1101，之后对第一层白色油墨进行完全固化，以完成第一子反射层111的制作；然后，在第一子反射层111上形成第二层白色油墨。其中，第二层白色油墨会有部分位于第一子通孔1101中，在接下来形成第二子通孔1102的构图工艺中，刻蚀液不会与已经完全固化的第一子反射层111进行反应，只会与未经过完全固化的第二层白色油墨发生反应(包括去除位于第一子通孔1101中的未固化的白色油墨)，形成第二子通孔1102，以完成第二子反射层112的制作。
在一定的厚度范围内，白色油墨层的厚度越大，其对光线2的反射率越高，而受制备白色油墨层所采用的印刷工艺所限，一般只能形成厚度小于30μm的单层白色油墨，而单层白色油墨对光线的反射率小于90％；因此可以将第一反射层11设置为双层油墨的结构，以提高第一反射层11对光线2的反射率。
在一些示例中，如图5A所示，发光二极管芯片12的出光面高于第二子反射层112远离基板10的一侧表面，而光学结构13与第一子通孔1101的孔壁接触。这样可以使光学结构13形成良好的凸透镜结构，同时在一定程度保证光学结构13成型后的稳定性。
在另一些示例中，如图5B所示，发光二极管芯片12的出光面高于第二子反射层112远离基板10的一侧表面，且光学结构13与第一子通孔1101和第二子通孔1102的孔壁均发生接触。例如，光学结构13可以覆盖第二子反射层112的部分表面(即第二子反射层112远离第一子反射层111一侧表面)。这样可以进一步提高光学结构13成型后的稳定性。
在又一些示例中，如图5C所示，发光二极管芯片12的出光面高于第一子反射层111且低于第二子反射层112远离基板10的一侧表面，即发光二极管芯片12的出光面位于第二子反射层112两侧的表面之间。此时，光学结构13与第一子通孔1101的孔壁接触。这样同样可以使光学结构13形成良好的 凸透镜结构，在一定程度保证光学结构13成型后的稳定性，同时可以减小形成光学结构的材料用量。
在本公开的一些实施例中，如图6A～图6D所示，基板10还包括第二反射层14。第一反射层11的通孔110的孔壁与发光二极管芯片12之间具有间隙。该间隙直接或间接露出第二反射层14靠近第一反射层11的至少部分表面。例如，在图6A和图6B中，第二反射层14位于电路结构层101靠近第一反射层11的一侧，此时，该间隙可以直接露出第二反射层14靠近第一反射层11的至少部分表面；又例如，在图6C和图6D中，第二反射层14位于电路结构层101远离第一反射层11的一侧，此时，该间隙可以间接地露出第二反射层14靠近第一反射层11的至少部分表面，即，在图6C的示例中，该间隙通过电路结构层14的透光区间接地露出第二反射层14的部分表面；而在图6D的示例中，该间隙通过电路结构层14和绝缘层15的透光区间接地露出第二反射层14的部分表面。
如图6A和图6B所示，第二反射层14包括多个镂空区。第一反射层11的每个通孔110在基板10上的正投影覆盖至少一个镂空区在基板10上的正投影。在一些示例中，每个通孔110可以暴露出一个镂空区，此时，一个镂空区暴露出电路结构层101的两个焊盘；在另一些示例中，每个通孔110可以暴露出两个镂空区，此时，每个镂空区可以暴露出电路结构层101的一个焊盘。
在本公开的一些实施例中，第一反射层11的通孔110的孔壁与发光二极管芯片12之间的间隙D的大小例如可以在大约1um～大约5um的取值范围内。此时，第一反射层11的通孔110的孔壁与发光二极管芯片12之间的间隙可以填满制作光学结构13的材料，这样可以提高发光二极管芯片12的出光效率以及使用稳定性。
在如图6A和图6B所示的结构中，基板10的承载面为第二反射层14的上表面(远离衬底100的一侧表面)。
在如图6C和图6D所示的结构中，基板10的承载面为电路结构层101的上表面。
第二反射层14的材质可以为金属，也可以为非金属；其中金属材质例如为银、铝，非金属例如为油墨，该油墨例如为白色油墨。
在本公开的一些实施例中，第二反射层14的材料为金属材料时，可以通过磁控溅射的方式形成。
在图6A和图6B中第二反射层14位于电路结构层101的上侧，在图6C 和图6D中第二反射层14位于电路结构层101的下侧。无论第二反射层14位于电路结构层101的上侧还是下侧，当第二反射层14的材料为导电金属时，为了避免第二反射层14影响电路结构层101的正常工作，第二反射层14需要与电路结构层101之间绝缘。也就是说第二反射层14的图案与电路结构层101中导电图案(例如金属走线区)在衬底上的正投影不重叠；或者在第二反射层14与电路结构层101之间需要设置有透明的绝缘层，该绝缘层的材料可以为有机材料，也可以为无机材料，例如氧化硅、氮化硅中的至少一种。在本公开的一些实施例中，如图6B和图6D所示，第二反射层14与电路结构层101之间设置有绝缘层15。
其中，“上侧”和“下侧”仅是参见图6A和图6B对本公开的一些实施例进行说明，不作为限定语。
如图6A和图6B所示，第二反射层14位于电路结构层101靠近发光二极管芯片12的一侧，在制作时，需要在第二反射层14或者在第二反射层14和绝缘层15上形成镂空区，以露出电路结构层101中的焊盘。
如图6C和图6D所示，第二反射层14位于电路结构层101远离发光二极管芯片12的一侧，当其他向朝向基板10一侧传播的光线2入射至第二反射层14时，经过第二反射层14的反射作用，将会再次出射。
在一些示例中，第一反射层11的通孔110的孔壁与发光二极管芯片12之间具有间隙，部分光线2(包括全反射光线20)会通过间隙入射至基板10中，而基板10中设置有第二反射层14，从间隙入射至基板10中的光线2将会被第二反射层14反射，从而再次出射，因此第二反射层14可以进一步提高发光二极管芯片12的出光效率。
此外，当发光二极管芯片12为360°立体出光时，由发光二极管芯片12朝向第二反射层14的表面出射的至少部分光线可以从发光二极管芯片12与第二反射层14之间的区域入射至第二反射层14，之后，经过第二反射层14的反射作用，也将会再次出射，有助于提高发光二极管芯片12的出光效率。
需要说明的是，第一反射层11的通孔110的孔壁与发光二极管芯片12之间也可以没有间隙，此时，由于发光二极管芯片12为360°立体出光，因此仍可以利用第二反射层14来提供发光二极管芯片12的出光效率。
在图6C和图6D中，虽然电路结构层101位于第二反射层14的上侧，但是，电路结构层101中存在透光区和非透光区，其中非透光区位于发光二极管芯片12在电路结构层的正投影的区域，焊盘位于非透光区，相邻非透光区之间为透光区。因此，从发光二极管芯片12和通孔110的孔壁之间的间隙入 射至基板10中的光线2和/或从发光二极管芯片12与第二反射层14之间的区域入射至基板10中的光线2仍然可以被第二反射层14反射。
在本公开的一些实施例中，如图6A和图6B所示，第二反射层14位于电路结构层101靠近第一反射层11的一侧；第二反射层14包括多个镂空区，多个镂空区中的一个镂空区露出电路结构层101中多个焊盘中的至少一个焊盘，一个发光二极管芯片12与多个焊盘中的两个焊盘电连接。
第二反射层14位于电路结构层101靠近第一反射层11的一侧时，一方面便于制作第二反射层14；另一方面，第二反射层14与光学结构13的出光面130之间的距离较短，光线2入射至第二反射层14的距离较短，损耗较少，可以进一步提高发光二极管芯片12的出光率。
在本公开的一些实施例中，如图7所示，第二反射层14包括沿基板10厚度方向依次层叠的第一子透明绝缘层141、金属反射层142和第二子透明绝缘层143。
在该种结构下，第二反射层14整体为绝缘结构，无论其位于电路结构层101的上侧和下侧均可，且由于两个绝缘层之间夹设有反射率较高的金属反射层142，发光二极管芯片12的出光效率可以进一步提高。
在本公开的一些实施例中，如图8所示，第二反射层14位于电路结构层101远离第一反射层11的一侧；电路结构层101具有多个金属走线区1010，以及位于相邻两个金属走线区1010之间的透光区1011。电路结构层101包括设置于金属走线区1010的多个焊盘，一个发光二极管芯片12与多个焊盘中的两个焊盘电连接；透光区1011被配置为透过发光二极管芯片12所发出的光线2中被第二反射层14反射的部分光线2，金属走线区1010为非透光区。
光线2从透光区1011入射至第二反射层14，经过第二反射层14的反射，将再次出射，发光二极管芯片12的出光效率较高。
在本公开的一些实施例中，如图9所示，背板1还包括粘接层16，粘接层16位于第一反射层11与基板10之间，粘接层16用于将第一反射层11粘接在基板10上。
其中，粘结层16的材料例如可以为亚克力胶。
在第一反射层11为反射片的情况下，可以通过粘接层16将反射片粘接在基板10上，以固定第一反射层11和基板10。
在本公开的一些实施例中，构成光学结构13的材料包括透明胶体材料和气相二氧化硅材料。气相二氧化硅材料可以增大透明胶体材料的粘性，有利于光学结构13的成型。
在本公开的另一些实施例中，构成光学结构13的材料包括透明胶体材料以及混合与透明胶体材料中的光转换材料，光转换材料被配置为转换发光二极管芯片12发出的光线2的颜色。
在本公开的又一些实施例中，构成光学结构13的材料包括透明胶体材料、气相二氧化硅材料和光转换材料。
上述透明胶体材料例如为封装胶，光转换材料例如为荧光粉、量子点材料、钙钛矿材料等。
在本公开的一些实施例中，在发光二极管芯片12发蓝光时，通过在光学结构13中设置光转换材料，可以将蓝光转化为白光或者红光或者绿光。
在光学结构13的材料中添加光转换材料，不仅可以优化背板1的结构，且可以降低背板1的成本。
在本公开的一些实施例中，如图10A所示，背板1还包括疏水层110，疏水层110位于第一反射层11远离基板10的一侧，疏水层110包括多个开口区，多个开口区中的一个开口区暴露出多个通孔中的一个通孔，一个光学结构13位于一个开口区。
疏水层的材料为疏水材料，例如为氟化聚乙烯、氟碳蜡等含氟聚合物。
疏水层可以使得相邻的光学结构13不易黏连在一起，因此有利于光学结构13的成型。
在本公开的一些实施例中，如图10B和图10C所示，在光学结构13的材料中未包括光转换材料时，背板1还包括光转换层17，光转换层17位于光学结构13远离基板10的一侧。
示例性的，光转换层17可以将发光颜色为三基色中至少一种颜色的发光二极管芯片12发出的光线2转换为白光。例如，光转换层17可以将蓝光转换为白光。
通过光转换层17转换发光二极管芯片12的光线颜色，转化效率和转换效果较好，能够提高背板1出射的光线2的品质，保证具有该背板1的显示基板的显示效果。
在本公开的一些实施例中，背板1可以作为背光模组。在此基础上，示例性的，背板1还可以包括依次设置于背板1出光侧的下扩散膜、上扩散膜和棱镜膜。在背板1包括上述光转换层17的情况下，光转换层17可以设置在下扩散膜与上扩散膜之间。其中，光转换层17可以为量子点膜。棱镜膜和上扩散膜可以使得作为背光模组的背板1的出光更为均匀，提高出光效果。
在本公开的另一些实施例中，背板1中的发光二极管芯片12可以直接作 为像素点进行显示，即背板1可以为显示基板，例如作为Mini LED显示装置和Micro LED显示装置中的显示部件。
参见图12，本公开一些实施例提供一种背板1的制备方法。如图2A和图12所示，该背板1的制备方法包括：
S1、提供基板10；基板10包括电路结构层101。
S2、在基板10上形成第一反射层11和多个发光二极管芯片12；第一反射层11包括间隔设置的多个通孔110；多个发光二极管芯片12中的一个发光二极管芯片12位于多个通孔110中的一个通孔110内，且多个发光二极管芯片12与电路结构层101电连接；电路结构层101被配置为驱动多个发光二极管芯片12发光。
S3、在多个发光二极管芯片12远离基板10的一侧，通过点胶工艺形成多个光学结构13；多个光学结构13中的一个光学结构13覆盖多个发光二极管芯片12中的一个发光二极管芯片12的出光面，且光学结构13的入光面与发光二极管芯片12的出光面接触，光学结构13的出光面130包括曲面。
在本公开的一些实施例中，光学结构13例如包括透明胶体材料。
在本公开的一些实施例中，光学结构13的材料中除包括透明胶体材料外，还可以包括气相二氧化硅材料。气相二氧化硅材料可以增大透明胶体材料的粘性，有利于光学结构13的成型。
背板1的制备方法与上述的背板1具有相同的有益效果，因此不再赘述。
在本公开的一些实施例中，如图2D所示，电路结构层101包括多个焊盘1012。在此基础上，如图12A所示，上述制备方法S2中，在基板10上形成第一反射层11和多个发光二极管芯片12的步骤，包括：
S21、如图12B所示，在基板10的承载面上形成第一油墨薄膜，并在第一油墨薄膜上形成多个通孔110，以形成第一反射层11。
第一油墨薄膜的材料为白色油墨，形成第一油墨薄膜例如可以通过丝网印刷、涂覆的方式形成。
在第一油墨薄膜上形成多个通孔110例如可以通过构图工艺的方式形成。
S22、如图12C所示，在形成有第一反射层11的基板10上，将多个发光二极管芯片12中的一个发光二极管芯片12与多个焊盘1012中的两个焊盘1012电连接。
在本公开的一些实施例中，发光二极管芯片12为蓝光LED芯片。
在本公开的一些实施例中，光学结构13除包括透明胶体材料外，还可以包括光转换材料。
在本公开的一些实施例中，如图13A所示，上述制备方法S21中，形成第一反射层11的步骤包括：
S211、如图13B所示，在基板10的承载面形成第一子油墨薄膜，并在第一子油墨薄膜上形成第一子通孔1101。
S212、如图13C所示，在第一子油墨薄膜上形成第二子油墨薄膜，并在第二子油墨薄膜上形成第二子通孔1102，且第二子通孔1102和第一子通孔1101相连通，第一子通孔1101和第二子通孔1102构成通孔110，从而形成第一反射层11。
在本公开的一些实施例中，第二子油墨薄膜的材料和制作工艺与第一子油墨薄膜相同，第二子通孔1102的制作工艺与第一子通孔1101的制作工艺相同。
在本公开的一些实施例中，第一子通孔1101的直径小于第二子通孔1102的直径。
第二子通孔1102的直径较大，有利于降低点胶工艺的对位精度，且双层油墨结构有利于光学结构13成型，以及提高第一反射层11的反射率。
本公开的另一些实施例中，如图2D所示，电路结构层101包括多个焊盘1012。如图14A所示，上述制备方法S2中，在基板10上形成第一反射层11和多个发光二极管芯片12的步骤，包括：
S201、如图14B所示，将多个发光二极管芯片12中的一个发光二极管芯片12与多个焊盘中的两个焊盘电连接。
其中，电路结构层101包括金属走线区1010和透光区1011，焊盘可以位于金属走线区1010。
S202、如图14C所示，提供反射片，在反射片的非功能面形成粘接层16，并在粘接层16上贴附第一保护膜18。
其中，可以采用涂覆或者狭缝工艺将黏贴胶均匀制作到反射片的非功能面，从而形成粘接层16。
反射片的非功能面位于反射片靠近基板10的衬底100一侧，也即反射片的功能面则位于反射片远离基板10的衬底100一侧。
在一些示例中，反射片的功能面的反射率大于反射片的非功能面的反射率，可以以此区分反射片的功能面和非功能面。
粘接层16的厚度例如可以在大约10μm～大约50μm的取值范围内，其与基板10之间的剥离力例如大于50gf。
在该结构中，将反射片作为第一反射层11，其中反射片的功能面对光线 2的反射率可以达到98％，反射率较高。
S203、如图14D所示，在与第一保护膜18粘接的反射片上形成多个通孔110，通孔110贯穿反射片、粘接层16和第一保护膜18。
形成通孔110例如可采用激光打孔、机械刀具切割、化学刻蚀等方法形成。其中，采用机械刀具切割通孔110时，可以很好的保持裁切端面的高反射特性。
S204、如图14E所示，撕除第一保护膜18，通过粘接层16将反射片贴附在基板10的承载面上，多个发光二极管芯片12一一对应的位于多个通孔110中。
在反射片贴附在基板10上时，需要对反射片和基板10进行对位，以使反射片上的通孔110与基板10上的至少一个焊盘对应；其中的对位例如可采用手动治具对位或者自动光学检测装置(属于自动治具)进行。
反射片与基板10之间的贴附例如可通过治具按压或者密闭高压腔室进行贴附，其中的治具例如为滚轮，而密闭高压腔室可通过空气压力使得反射片贴附在基板10上。
如图14E所示，在通过滚轮按压使得反射片贴附在基板10上时，由于发光二极管芯片12的出光面高于反射片的上表面(远离基板10的一侧表面)，因此直接使用滚轮可能会损坏发光二极管芯片12。
基于此，在一些实施例中，可以在反射片的功能面上贴附一层第二保护膜。该第二保护膜可以为离型纸。在反射片上贴附第二保护膜后的结构如图14F所示，第二保护膜19、反射层11和黏接层16的总厚度大于或者等于发光二极管芯片12的高度，具体高度差要考虑按压贴附时所产生的压缩量，以确保发光二极管芯片12不被压坏。示例性的，第二保护膜19、反射层11和黏接层16的总厚度与发光二极管芯片12的高度之间的高度差越小越好，从而有利于发光二极管芯片四周的光线出射。如图14G所示，将带有第二保护膜19的反射片与基板10对位完成后，确保第二保护膜19的上表面与发光二极管芯片12的上表面高于发光二极管芯片12的上表面或者与发光二极管芯片12的上表面大致平齐，便可使用滚轮按压使得反射片与基板10紧贴；在按压完成后，可以撕除第二保护膜19。
需要说明的是，当反射片的上表面高于或者与发光二极管芯片12的出光面大致平齐时，均可以直接使用滚轮进行按压，在该种结构中可以不用贴附第二保护膜19。
上述背板1的制备方法与上述的背板1具有相同的有益效果，因此不再 赘述。
在本公开的一些实施例中，如图6A、图6C和图15所示，在形成第一反射层11之前，即在上述制备方法S2之前，背板1的制备方法还包括：
S11、在电路结构层101的任意一侧表面形成第二反射层14。
在一些示例中，如图6A所示，第二反射层14位于电路结构层101远离衬底100的一侧；
在另一些示例中，如图6C所示，第二反射层14位于电路结构层101与衬底100之间。
在本公开的一些实施例中，参见图16A，在电路结构层101的任意一侧表面形成第二反射层14的步骤，包括：
S111、如图16C所示，在基板10的承载面上形成第二油墨薄膜，并在第二油墨薄膜上形成多个镂空区，露出电路结构层101中的焊盘，以形成第二反射层14。
其中，第二油墨薄膜的材料可以与第一油墨薄膜的材料相同。
在本公开的一些实施例中，如图16B所示，在电路结构层101的任意一侧表面形成第二反射层14的步骤，包括：
S101、如图16D所示，在基板10的承载面上形成第一子透明绝缘层141。
在本公开的一些实施例中，基板10的承载面为电路结构层101的上表面。
在本公开的一些实施例中，第一子透明绝缘层141的材料例如为聚酰亚胺、塑料中的一种。
在形成第一子透明绝缘层141时需要露出焊盘。
S102、如图16E所示，在第一子透明绝缘层141上形成金属反射层142。
在本公开的一些实施例中，金属反射层142的材料例如为铝。
S103、如图16F所示，在金属反射层上形成第二子透明绝缘层143；第一子透明绝缘层141、金属反射层142和第二子透明绝缘层143构成第二反射层14。
在本公开的一些实施例中，第二子透明绝缘层143的材料例如为聚酰亚胺、塑料中的一种。
在基板10的承载面制作第二反射层14，制作工艺较为简单，且全反射光线20和其它向朝向基板10一侧传播的光线2入射至第二反射层14的路径较短，损耗较少。
在本公开的一些实施例中，通过点胶工艺形成多个光学结构13，包括：
将透明胶体材料和光转换材料混合，通过点胶工艺形成多个光学结构13； 其中光转换材料被配置为将转换发光二极管芯片12发出的光线2的颜色。
在本公开的一些实施例中，光转换材料例如为量子点材料，量子点材料对光的转换效率较高。
在该种结构下，可以降低背板1的结构，降低生产成本。
在本公开的一些实施例中，点胶工艺可以为针管式点胶工艺，这样可以提高点胶工艺过程中的精准度。
本文中，本领域技术人员应该可以理解的是，发光二极管芯片12的出光效率等于背板的出光量除以所有发光二极管芯片的出光量。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种背板，包括：
    基板，包括电路结构层；
    第一反射层，设置于所述基板的承载面；所述第一反射层包括间隔设置的多个通孔；
    多个发光二极管芯片，所述多个发光二极管芯片中的一个发光二极管芯片位于所述多个通孔中的一个通孔内，且所述多个发光二极管芯片与所述电路结构层电连接；所述电路结构层被配置为驱动所述多个发光二极管芯片发光；
    多个光学结构，所述多个光学结构中的一个光学结构覆盖所述多个发光二极管芯片中的一个发光二极管芯片的出光面，且所述光学结构的入光面与所述发光二极管芯片的出光面接触，所述光学结构的出光面包括曲面。
  2. 根据权利要求1所述的背板，其中，所述光学结构的出光面为向所述发光二极管芯片远离所述基板的一侧凸起的凸面。
  3. 根据权利要求1或2所述的背板，其中，所述通孔包括依次远离所述基板的第一子通孔和第二子通孔；
    其中，所述第一子通孔的孔径小于所述第二子通孔的孔径；
    所述光学结构至少与所述第一子通孔的孔壁接触。
  4. 根据权利要求3所述的背板，其中，所述第一子通孔的孔壁在所述基板上的正投影位于所述第二子通孔的孔壁在所述基板上的正投影之内。
  5. 根据权利要求3或4所述的背板，其中，所述光学结构还与所述第二子通孔的孔壁接触。
  6. 根据权利要求3～5中任一项所述的背板，其中，所述第一反射层包括第一子反射层和第二子反射层；所述第一子通孔位于所述第一子反射层上，所述第二子通孔位于所述第二子反射层上。
  7. 根据权利要求1～6中任一项所述的背板，其中，
    所述第一反射层为油墨结构层；或者，
    所述第一反射层为白色反射片，所述白色反射片中包括多个微空气泡。
  8. 根据权利要求1～7中任一项所述的背板，其中，所述发光二极管芯片远离所述基板的承载面的一侧表面，与所述基板的承载面之间具有第一最大间距；所述第一反射层远离所述基板的承载面的一侧表面，与所述基板的承载面之间具有第二最大间距；
    其中，所述第一最大间距大于所述第二最大间距；或者，所述第一最大 间距小于所述第二最大间距。
  9. 根据权利要求1～8中任一项所述的背板，还包括：第二反射层；
    其中，所述第二反射层位于所述电路结构层靠近所述第一反射层的一侧；所述第二反射层包括多个镂空区，所述电路结构层包括多个焊盘，所述多个镂空区中的一个镂空区露出所述多个焊盘中的至少一个焊盘，一个所述发光二极管芯片与所述多个焊盘中的两个焊盘电连接；或者，
    所述第二反射层位于所述电路结构层远离所述第一反射层的一侧；所述电路结构层具有多个金属走线区，以及位于相邻两个金属走线区之间的透光区；所述电路结构层包括设置于所述金属走线区的多个焊盘，一个所述发光二极管芯片与所述多个焊盘中的两个焊盘电连接；所述透光区被配置为透过发光二极管芯片所发出的光线中被所述第二反射层反射的部分光线。
  10. 根据权利要求9所述的背板，其中，
    所述通孔的孔壁与所述发光二极管芯片之间具有间隙；
    所述间隙直接或间接露出所述第二反射层靠近所述第一反射层的至少部分表面。
  11. 根据权利要求9或10所述的背板，其中，所述第二反射层包括沿所述基板厚度方向依次层叠的第一子透明绝缘层、金属反射层和第二子透明绝缘层。
  12. 根据权利要求1～11中任一项所述的背板，还包括：
    粘接层，位于所述第一反射层与所述基板之间，所述粘接层被配置为将所述第一反射层粘接在所述基板上。
  13. 根据权利要求1～12中任一项所述的背板，还包括：
    疏水层，设置于所述第一反射层远离所述基板的一侧；所述疏水层包括多个开口区，所述多个开口区中的一个开口区暴露出所述多个通孔中的一个通孔。
  14. 根据权利要求1～13中任一项所述的背板，其中，构成所述光学结构的材料包括透明胶体材料以及气相二氧化硅材料。
  15. 根据权利要求1～14中任一项所述的背板，其中，构成所述光学结构的材料包括透明胶体材料以及混合于所述透明胶体材料中的光转换材料；所述光转换材料被配置为转换所述发光二极管芯片发出的光线的颜色；和/或，
    所述背板还包括光转换层，所述光转换层位于所述光学结构远离所述基板的一侧表面。
  16. 一种显示装置，包括：
    如权利要求1～15中任一项所述的背板；
    其中，所述背板为显示基板；或者，
    所述背板为背光模组，所述显示装置还包括位于所述背光模组出光侧的液晶显示面板。
  17. 一种背板的制备方法，包括：
    提供基板；所述基板包括电路结构层；
    在所述基板上形成第一反射层和多个发光二极管芯片；所述第一反射层包括间隔设置的多个通孔；所述多个发光二极管芯片中的一个发光二极管芯片位于所述多个通孔中的一个通孔内，且所述多个发光二极管芯片与所述电路结构层电连接；所述电路结构层被配置为驱动所述多个发光二极管芯片发光；
    在所述多个发光二极管芯片远离所述基板的一侧，通过点胶工艺形成多个光学结构；所述多个光学结构中的一个光学结构覆盖所述多个发光二极管芯片中的一个发光二极管芯片的出光面，且所述光学结构的入光面与所述发光二极管芯片的出光面接触，所述光学结构的出光面包括曲面。
  18. 根据权利要求17所述的背板的制备方法，其中，所述电路结构层包括多个焊盘；所述在所述基板上形成第一反射层和多个发光二极管芯片，包括：
    在基板的承载面上形成第一油墨薄膜，并在所述第一油墨薄膜上形成多个通孔，以形成第一反射层；
    在形成有第一反射层的所述基板上形成多个发光二极管，所述多个发光二极管芯片中的一个发光二极管芯片位于所述多个通孔中的一个通孔内，每个所述发光二极管芯片与所述多个焊盘中的两个焊盘电连接。
  19. 根据权利要求18所述的背板的制备方法，其中，所述形成第一反射层包括：
    在所述基板的承载面形成第一子油墨薄膜，并在第一子油墨薄膜上形成第一子通孔；
    在所述第一子油墨薄膜上形成第二子油墨薄膜，并在第二子油墨薄膜上形成第二子通孔，所述第一子通孔和所述第二子通孔相连通以构成所述通孔；从而形成第一反射层。
  20. 根据权利要求17所述的背板的制备方法，其中，所述电路结构层包括多个焊盘；所述在所述基板上形成第一反射层和多个发光二极管芯片，包 括：
    将多个发光二极管芯片中的一个发光二极管芯片与所述多个焊盘中的两个焊盘电连接；
    提供反射片，在反射片的非功能面形成粘接层，并在粘接层上贴附第一保护膜；
    在与第一保护膜粘接的反射片上形成多个通孔，所述通孔贯穿所述反射片、粘接层和第一保护膜；
    撕除第一保护膜，通过所述粘接层将所述反射片贴附在所述基板的承载面上，使所述多个发光二极管芯片一一对应的位于多个通孔中。
  21. 根据权利要求17～20中任一项所述的背板的制备方法，其中，在形成所述第一反射层和所述多个发光二极管芯片之前，所述背板的制备方法还包括：
    在所述电路结构层的任意一侧表面形成第二反射层。
  22. 根据权利要求21所述的背板的制备方法，其中，所述电路结构层包括多个焊盘；所述在所述电路结构层的任意一侧表面形成第二反射层，包括：
    在所述基板的承载面上形成第二油墨薄膜，并在所述第二油墨薄膜上形成多个镂空区，露出所述电路结构层中的所述焊盘，以形成第二反射层；
    或者，在所述基板的承载面上形成第一子透明绝缘层；
    在所述第一子透明绝缘层上形成金属反射层；
    在所述金属反射层上形成第二子透明绝缘层；所述第一子透明绝缘层、金属反射层和第二子透明绝缘层构成第二反射层。
  23. 根据权利要求17～22中任一项所述的背板的制备方法，其中，所述通过点胶工艺形成多个光学结构，包括：
    将透明胶体材料和光转换材料混合，通过点胶工艺形成多个光学结构；其中，所述光转换材料被配置为转换所述发光二极管芯片发出的光线的颜色。
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